1. A wireless camera system, comprising: a plurality of battery-powered, wireless node cameras, each node camera comprising an image sensor for capturing image data, a radio for performing wireless communications, at least one processor for controlling the image sensor and the radio, and at least one battery; andan access point configured to communicate wirelessly with each of the node cameras, and further configured to communicate with a control center that communicatively couples the access point to a computer network,
wherein the at least one processor in each node camera, comprises: a host processor configured to control execution of one or more active-state operations; and
a secondary processor coupled to the host processor and the radio, configured to control execution of one or more low-priority operations while the host processor is powered down, wherein the secondary processor is further configured to determine if an active-state operation is pending, and if it is determined that an active-state operation is pending, to power up the host processor to control execution of the active-state operation, wherein the host processor is configured to automatically enter a sleep mode after completion of the active-state operation and the host processor is configured to save state information pertaining to the host processor in a memory of the secondary processor and thereafter send a command to the secondary processor to shut off power from the at least one battery to the host processor and
wherein, upon being subsequently powered on, the host processor is configured to access the state information from the memory of the secondary processor and transition to the state it was in prior to being powered down, and
wherein if a low-priority operation is being executed when the active-state operation is determined to be pending, the secondary processor is further configured to suspend the low-priority operation, save information pertaining to a state of the low-priority operation in a memory, and thereafter power up the host processor to control execution of the active-state operation.