US Pat. No. 9,383,967

ACCUMULATION OF WAVEFORM DATA USING ALTERNATING MEMORY BANKS

National Instruments Corp...

1. A system for accumulating waveform data, the system comprising:
a digitizer, comprising:
a circuit;
a first memory bank, coupled to the circuit; and
a second memory bank, coupled to the circuit;
wherein the circuit is configured to:
a) store a first subset of the waveforms in the first memory bank;
b) accumulate each waveform of the first subset of waveforms in a chunk-wise manner, wherein each chunk has a specified size,
thereby generating a first bank sum comprising a first partial accumulation of the set of waveforms;

c) store a second subset of waveforms in the second memory bank concurrently with b);
d) accumulate each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum
comprising a second partial accumulation of the set of waveforms; and

wherein the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of
the set of waveforms.

US Pat. No. 9,391,818

PILOT SEQUENCE DESIGN FOR WIRELESS COMMUNICATIONS

National Instruments Corp...

1. An apparatus, comprising:
one or more processing elements configured to generate data that includes a pilot sequence with a null portion for channel
estimation;

the pilot sequence is a complex-valued sequence generated by:
determining a constant amplitude zero autocorrelation (CAZAC) sequence as a first sequence;
iteratively performing the following operations on the first sequence until a Fourier Transform (FT) of a zero-padded instance
of the first sequence has a flat magnitude, thereby generating a final sequence, wherein said iteratively performing comprises:

padding a respective instance of the first sequence with zeros;
determining whether a FT of the zero-padded instance of the first sequence has a flat magnitude;
adjusting the phase of a second sequence that has a desired frequency response to match a phase of the FT of the respective
zero-padded instance of the first sequence, thereby producing an adjusted second sequence; and

determining an inverse FT of the adjusted second sequence to generate an inverse FT result, wherein the inverse FT result
is used as the respective instance of the first sequence in a next iteration; and

the one or more processing elements being further configured to output the generated data, including the generated pilot sequence,
to at least one other element for wireless transmission.

US Pat. No. 9,160,313

COMPENSATED TEMPERATURE VARIABLE RESISTOR

National Instruments Corp...

1. A resistance circuit comprising:
a first transistor device configured to operate in linear mode, and having an operative resistance value representative of
a specified nominal resistance value;

a second transistor device having device characteristics commensurate with characteristics of the first transistor device,
wherein the second transistor device is configured to operate in linear mode, and have an operative resistance value representative
of the specified nominal resistance value; and

control circuitry configured to:
cause the operative resistance value of the second transistor device to return to the specified nominal resistance value when
the operative resistance value of the second transistor device drifts away from the specified nominal resistance value due
to changes in temperature; and

control the first transistor device by a control signal generated according to operation of the second transistor device,
causing the operative resistance value of the first transistor device to return to the specified nominal resistance value
when the operative resistance value of the first transistor device drifts away from the specified nominal resistance value
due to changes in temperature.

US Pat. No. 9,235,395

GRAPHICAL DEVELOPMENT AND DEPLOYMENT OF PARALLEL FLOATING-POINT MATH FUNCTIONALITY ON A SYSTEM WITH HETEROGENEOUS HARDWARE COMPONENTS

National Instruments Corp...

1. A non-transitory computer accessible memory medium that stores program instructions for configuring a system of heterogeneous
hardware components, wherein the program instructions are executable by a processor to:
create a graphical program that includes floating point math functionality, wherein the graphical program comprises a plurality
of interconnected nodes that visually indicate functionality of the graphical program, wherein the graphical program is targeted
for distributed deployment on a system comprising heterogeneous hardware components, including at least one programmable hardware
element, at least one digital signal processor (DSP) core, and at least one programmable communication element (PCE);

automatically determine respective portions of the graphical program for deployment to respective ones of the heterogeneous
hardware components, including automatically determining respective execution timing for the respective portions;

automatically generate first program code implementing communication functionality between the at least one programmable hardware
element and the at least one DSP core, wherein the first program code is targeted for deployment to the at least one programmable
communication element; and

automatically generate at least one hardware configuration program from the graphical program and the first program code,
wherein said automatically generating comprises compiling the respective portions of the graphical program and the first program
code for deployment to respective ones of the heterogeneous hardware components;

wherein the hardware configuration program is deployable to the system, wherein after deployment, the system is configured
to execute the graphical program concurrently, including the floating point math functionality.

US Pat. No. 9,135,497

IDENTIFYING RANDOMLY DISTRIBUTED MICROPARTICLES IN IMAGES TO SEQUENCE A POLYNUCLEOTIDE

National Instruments Corp...

1. A computer-implemented method for performing sequencing of a polynucleotide, comprising:
receiving, by the computer, a first image of microparticles, wherein the first image is stored in a memory of the computer,
wherein the microparticles are distributed in a random fashion on a substrate wherein the microparticles have respective random
positions on the substrate, wherein the respective random positions are not pre-determined and are not regularly spaced, and
wherein each of the microparticles comprises a plurality of similar oligonucleotides of the polynucleotide;

receiving, by the computer, a second image of the microparticles, wherein the second image of the microparticles highlights
at least some of the microparticles in response to fluorescent chemicals attached to the oligonucleotides based on terminal
nucleotides of the oligonucleotides on the microparticles, and wherein the second image is stored in the memory of the computer;

determining, by the computer, a plurality of first subportions of the first image, wherein each subportion comprises a respective
plurality of microparticles distributed in a random fashion, and wherein each first subportion's random distribution comprises
a respective unique pattern;

analyzing, by the computer, the second image to identify a plurality of second subportions in the second image that each corresponds
to a respective one of the plurality of first subportions based on the respective unique patterns;

matching, by the computer, a plurality of the microparticles in the first and second images based on said analyzing using
the respective unique patterns; and

determining, by the computer, the sequence of nucleotides of the polynucleotide based on said matching and the highlighted
microparticles, wherein the sequence of nucleotides is stored in the memory of the computer.

US Pat. No. 9,088,331

IQ BASEBAND MATCHING CALIBRATION TECHNIQUE

National Instruments Corp...

1. A non-transitory memory medium storing program instructions, for determining gain and/or phase imbalance of a signal generation
system and/or a signal digitizing system, wherein the program instructions, when executed by a processor, cause the processor
to implement:
(a) after a first output and a second output of the signal generation system has been connected respectively to a first input
and a second input of the signal digitizing system using respectively a first electrical conductor and a second electrical
conductor:

directing the signal generation system to generate a first vector calibration signal and to transmit a first vector output
signal via the first output and the second output based on the first vector calibration signal, and

directing the signal digitizing system to capture a first set of vector samples from the first input and second input in response
to the transmission of the first vector output signal;

(b) after the first output and the second output of the signal generation system have been connected respectively to the second
input and the first input of the signal digitizing system using the first and second electrical conductors:

directing the signal generation system to generate a second vector calibration signal and transmit a second vector output
signal based on the second vector calibration signal, and

directing the signal digitizing system to capture a second set of vector samples from the first input and second input in
response to the transmission of the second vector output signal;

(c) computing a measurement of gain and/or phase imbalance of the signal generation system and/or a measurement of gain and/or
phase imbalance of the signal digitizing system based on input data including the first set of vector samples and the second
set of vector samples.

US Pat. No. 9,285,801

AUTOMATIC GENERATION OF A MOTION CONTROLLER

National Instruments Corp...

1. A computer implemented method comprising:
utilizing a computer to perform:
receiving user input specifying desired characteristics for a motion controller, wherein the desired characteristics specified
by the user input include supervisory control functions and trajectory generation functions;

automatically generating a motion controller program that realizes the desired characteristics for the motion controller based
on the user input, wherein said automatically generating the motion controller program comprises automatically generating
program instructions implementing the supervisory control functions and the trajectory generation functions;

downloading the motion controller program to a hardware platform;
wherein the hardware platform executes the motion controller program to implement the motion controller having the desired
characteristics, and wherein the motion controller program executes on the hardware platform to receive application level
commands from a motion control application and generate corresponding control signals for at least one drive unit;

automatically generating an application programming interface (API) corresponding to the motion controller program, wherein
the API provides a software interface to the motion controller program executing on the hardware platform for applications
running on a host computer.

US Pat. No. 9,160,472

CLOCK SYNCHRONIZATION OVER A SWITCHED FABRIC

National Instruments Corp...

1. A system, comprising:
a master device, comprising:
a first functional unit; and
at least one first I/O port, coupled to the first functional unit; and
a slave device, comprising:
a second functional unit; and
at least one second I/O port, coupled to the second functional unit;
wherein the first functional unit is configured to:
maintain a global time;
read a first counter value of a counter of a switch coupled to the at least one first I/O port over a memory-mapped fabric;
determine a first mapping between the global time and the counter of the switch based on the global time and the first counter
value; and

send the first mapping to the slave device via the at least one first I/O port over the memory-mapped fabric; and
wherein the second functional unit is configured to:
maintain a local time;
read a second counter value of the counter of the switch coupled to the at least one second I/O port over the memory-mapped
fabric;

determine a second mapping between the local time and the counter of the switch based on the local time and the second counter
value;

receive the first mapping between the counter and the global time from the master device over the memory-mapped fabric; and
synchronize the local time to the global time based on the first and second mappings.

US Pat. No. 9,135,062

HARDWARE ASSISTED METHOD AND SYSTEM FOR SCHEDULING TIME CRITICAL TASKS

National Instruments Corp...

1. A method for monitoring a time critical task, the method comprising:
receiving timing information for executing the time critical task, wherein the time critical task executes program instructions
via a thread on a core of a processing unit;

scheduling the time critical task, wherein said scheduling comprises determining, based on the received timing information,
a wakeup time, a thread cycle time, an overall thread deadline, and a time critical task deadline;

wherein the time critical task deadline is a function of the overall thread deadline and a specified thread bandwidth, wherein
the specified thread bandwidth indicates a fraction of the thread cycle time reserved for the time critical task;

programming a lateness timer based on the wakeup time and the time critical task deadline;
waiting for the wakeup time to obtain;
notifying the processing unit of said scheduling, wherein said notifying indicates to the processing unit that the thread
is in an idle state, wherein the idle state indicates that the thread is awake and ready to resume execution and execute the
time critical task in accordance with said scheduling;

executing, on the core of the processing unit, the time critical task in accordance with said scheduling;
monitoring the lateness timer; and
asserting a thread interrupt in response to the lateness timer expiring, wherein said asserting interrupts said executing,
thereby suspending execution of the time critical task.

US Pat. No. 9,313,235

SYSTEMS AND METHODS FOR NETWORK INTEROPERABILITY

National Instruments Corp...

1. A system for interoperating between a first network and one or more second networks, the system comprising:
a plurality of ports, comprising:
at least one port coupled to the first network, wherein the first network is configured to operate according to a first real
time network protocol; and

one or more ports coupled respectively to the one or more second networks, wherein each of the one or more second networks
are configured to operate according to respective second real time traffic protocols, wherein the first real time network
protocol is not compatible with the respective second real time traffic protocols; and

a switch coupled to the plurality of ports, wherein the switch is configured with a mapping that specifies data routing between
the plurality of ports, wherein the switch is configured to:

route packets between the first network and the one or more second networks based on the mapping, thereby maintaining real
time behavior between the first network and the one or more second networks;

insert routing information in packets routed from the one or more second networks to the first network;
remove routing information from packets routed from the first network to the one or more second networks; and
route, based on the mapping, packets to distinct queues for the first network and the one or more second networks for processing
by an application executing on at least one device.

US Pat. No. 9,157,952

SWITCH MATRIX SYSTEM AND METHOD

National Instruments Corp...

1. A radio frequency (RF) switch system, comprising:
a plurality of switch inputs;
a plurality of switch outputs;
an RF analog switch matrix comprising a plurality of 2×2 RF analog switching elements configured to selectively couple one
or more of the plurality of switch inputs to one or more of the plurality of switch outputs during use to provide one or more
paths for routing RF analog signals from one or more of the switch inputs to one or more of the switch outputs during use,
wherein the RF analog switch matrix comprises one or more multi-dimensional RF analog switching elements, each comprising
a respective plural subset of the plurality of 2×2 RF analog switching elements;

wherein the RF analog switch matrix comprises a first topology that defines connectivity of the RF analog switch matrix, wherein
at least one of the one or more multi-dimensional RF analog switching elements comprises a second topology that defines connectivity
of the at least one multi-dimensional RF analog switching element, and wherein the first topology is topologically distinct
from the second topology.

US Pat. No. 9,141,347

EDITING A GRAPHICAL DATA FLOW PROGRAM IN A WEB BROWSER ON A CLIENT COMPUTER

National Instruments Corp...

1. A non-transitory computer-accessible memory medium that stores program instructions executable by a processor of a client
computer to:
establish a network connection with a server computer over a network;
send a universal resource identifier (URI) to the server computer over the network, wherein the URI indicates a graphical
data flow program (GDFP) or a graphical data flow program editor (GDFP editor) for creating or editing the GDFP;

receive the GDFP editor from the server computer over the network in response to the URI;
execute the GDFP editor in a web browser on the client computer;
display the GDFP in the web browser, wherein the GDFP comprises a plurality of nodes connected by lines, wherein the lines
specify flow of data among the nodes, and wherein the GDFP has an architecture and behavior in accordance with a data flow
model of computation wherein the nodes execute when all necessary inputs are available, wherein the GDFP has an associated
representation implemented in a browser supported format, wherein the representation of the GDFP does not include the GDFP,
and wherein the representation of the GDFP is receivable by client systems for display in browsers on the client systems,
including browsers that do not support execution of the GDFP;

receive user input to the GDFP editor executing in the web browser, wherein the user input indicates one or more edit operations
to be performed on the GDFP;

edit the GDFP in the web browser on the client computer via the GDFP editor in accordance with the one or more edit operations,
thereby generating an edited GDFP; and

display the edited GDFP in the web browser.

US Pat. No. 9,460,036

CONTROLLING BUS ACCESS PRIORITY IN A REAL-TIME COMPUTER SYSTEM

National Instruments Corp...

1. A non-transitory computer-readable memory medium storing program instructions executable by one or more processors to:
set a priority level for each respective device used in an application, including one or more scheduled devices that access
a bus according to a first static time schedule that defines at least specific execution start times in the application, and
one or more unscheduled devices that attempt to access the bus at times not defined by the first static time schedule, where
the priority level for each respective device specifies a priority at which the respective device is allowed to access the
bus;

launch the application, wherein the one or more scheduled devices and the one or more unscheduled devices attempt to access
the bus while the application is running; and

change the priority level for at least one unscheduled device of the one or more unscheduled devices one or more times while
the application is running.

US Pat. No. 9,310,832

BACKPLANE CLOCK SYNCHRONIZATION

National Instruments Corp...

1. An apparatus, comprising:
a backplane that includes a clock, wherein the apparatus is configured to generate timestamps periodically based on the clock;
at least one processing element coupled to the clock via the backplane; and
a synchronization interface coupled to or included in the at least one processing element;
wherein the at least one processing element is configured to:
compare a first timestamp received from the clock via the backplane with a second timestamp received from the synchronization
interface to determine time error information, wherein the second timestamp is generated based on an external clock;

determine adjustment information based on the time error information; and
synchronize the clock with the external clock using the adjustment information, via the backplane.

US Pat. No. 9,311,266

HIDDEN BASE ADDRESS REGISTER PROGRAMMING IN PERIPHERAL COMPONENT INTERCONNECT EXPRESS BUSES

National Instruments Corp...

1. A system comprising:
a semi transparent bridge configured to couple an upstream host to a downstream switch fabric, which comprises intermediary
bridges and respective switch fabric endpoints coupled downstream from the intermediary bridges, wherein the intermediary
bridges are hidden from the upstream host and the respective switch fabric endpoints are visible to the host; and

a configuration block configured to:
during a setup phase, provide, to the upstream host, first resource requirement information corresponding to the intermediary
bridges and interpreted by the upstream host as resource requirement information corresponding to the respective switch fabric
endpoints; and

during a runtime phase, provide, to the upstream host, second resource requirement information corresponding to the respective
switch fabric endpoints and interpreted by the upstream host as the resource requirement information corresponding to the
respective switch fabric endpoints.

US Pat. No. 9,188,611

RESAMPLING A SIGNAL TO PERFORM POWER QUALITY MEASUREMENT

National Instruments Corp...

1. A method for performing power quality measurement, comprising:
measuring, by at least one power signal measurement device configured with power quality analysis functionality, power of
a power system, wherein said measuring produces a first power signal, wherein the first power signal is stored in a memory,
and wherein the stored first power signal comprises a plurality of cycles;

applying, by the at least one power signal measurement device, a filter to the stored first power signal, thereby generating
a stored filtered first power signal;

performing, by the at least one power signal measurement device, zero crossing detection on the stored filtered first power
signal, wherein said performing zero crossing detection comprises determining start and end positions of each of the plurality
of cycles;

determining, by the at least one power signal measurement device, even angle positions and a fundamental frequency for each
cycle of the plurality of cycles of the stored first filtered power signal based on the determined start and end positions;

resampling, by the at least one power signal measurement device, the stored filtered first power signal at the even angle
positions based on the fundamental frequency to produce an even angle power signal, wherein the even angle power signal is
stored in the memory; and

performing, by the at least one power signal measurement device, one or more power quality measurements of the power system
using the even angle power signal to perform power quality measurement of the power system.

US Pat. No. 9,135,143

AUTOMATED ANALYSIS OF COMPILATION PROCESSES IN A GRAPHICAL SPECIFICATION AND CONSTRAINT LANGUAGE

National Instruments Corp...

1. A computer-implemented method, comprising:
receiving a program representative of a hardware design of one or more functions;
producing a hardware representation of the hardware design by running the received program through a compilation process that
comprises multiple stages, wherein the hardware representation of the hardware design is subject to one or more constraints,
wherein said producing the hardware representation of the hardware design comprises;

collecting information relating to characteristics of the hardware design throughout the compilation process, wherein the
characteristics of the hardware design include timing path information of the hardware design;

wherein the hardware representation of the hardware design does not meet at least one of the one or more constraints; and
performing, until the one or more constraints are met:
automatically adjust one or more stages of the compilation process based on the collected information via a programming interface,
including automatically adjusting timing path implementation decisions, thereby adjusting the compilation process; and

performing said producing via the adjusted compilation process;
wherein said performing until the one or more constraints are met comprises:
producing a timing report resulting from the compilation process;
comparing the timing report with a prior timing report obtained from a previous compilation process performed on the received
program, said comparing comprising:

parsing failed timing constraint paths in the timing report; and
comparing timing delays comprised in the failed timing constraint paths to timing delays comprised in corresponding timing
constraint paths in the prior timing report; and

adjusting timing paths in the hardware design according to results of the comparison of the timing report with the prior timing
report, wherein said adjusting comprises:

undoing previous timing adjustments that didn't produce desired results, responsive to comparing the timing delays; and
identifying a longest preexisting component delay from the failed timing constraint paths, and adding a register in a timing
path corresponding to the identified delay.

US Pat. No. 9,134,895

WIRING METHOD FOR A GRAPHICAL PROGRAMMING SYSTEM ON A TOUCH-BASED MOBILE DEVICE

National Instruments Corp...

1. A method comprising:
displaying a plurality of nodes in a graphical program on a touch-based display device; and
connecting a particular input terminal of a first node of the plurality of nodes to a particular output terminal of a second
node of the plurality of nodes in response to touch gesture input received to the graphical program, wherein said connecting
includes:

displaying a magnified view of one or more input terminals of the first node in response to touch gesture input, wherein said
displaying the magnified view of the one or more input terminals of the first node in response to touch gesture input comprises
displaying a respective terminal icon corresponding to each respective input terminal of the one or more input terminals,
and wherein said displaying a respective terminal icon corresponding to each respective input terminal of the one or more
input terminals comprises arranging the terminal icons along a curved arc;

selecting the particular input terminal from the magnified view of the one or more input terminals in response to touch gesture
input, wherein said selecting comprises selecting the respective terminal icon corresponding to the particular input terminal;
and

displaying a data flow wire connecting the particular input terminal of the first node to the particular output terminal of
the second node.

US Pat. No. 9,110,558

PHYSICS BASED GRAPHICAL PROGRAM EDITOR

National Instruments Corp...

1. A non-transitory computer-accessible memory medium that stores program instructions executable by a processor to implement:
displaying a graphical program on a display device, wherein the graphical program comprises a plurality of interconnected
nodes that visually indicate functionality of the graphical program;

receiving user input editing the graphical program, thereby generating an edited graphical program;
adjusting placement of one or more elements within the edited graphical program based on said editing, wherein said adjusting
is performed based on determined forces applied to the one or more elements in the edited graphical program, wherein said
adjusting placement results in an adjusted edited graphical program, wherein said adjusting placement of one or more elements
comprises:

determining one or more forces for each of the one or more elements based on their positions;
summing the forces on each of the one or more elements, thereby determining resultant forces;
moving the one or more elements based on the resultant forces; and
repeating said determining, said summing, and said moving one or more times in an iterative manner until an equilibrium condition
obtains; and

displaying the adjusted edited graphical program on the display device.

US Pat. No. 9,288,157

TIME-SENSITIVE SWITCH FOR SCHEDULED DATA EGRESS

National Instruments Corp...

1. A method for scheduled data egress, comprising:
providing a time-sensitive (TS) network switch, wherein the TS network switch comprises:
a functional unit;
a plurality of ports coupled to the functional unit, wherein each port is associated with a respective set of network addresses
for TS packets, wherein each port is configured with a respective set of egress periods, wherein each TS packet has a destination
address and a type that specifies a respective egress period, wherein each egress period specifies a respective time window
and frequency for egressing TS packets to network nodes based on the type of the TS packets; and

a plurality of queues, coupled to the plurality of ports and the functional unit, wherein each queue is associated with a
respective TS packet type and a respective port of the plurality of ports; and

configuring the functional unit to:
receive two or more TS packets asynchronously from a network node via a first port;
determine a second port of the plurality of ports for egressing at least two of the two or more TS packets based on the destination
address of the at least two TS packets;

determine an egress period for egressing the at least two TS packets based on the type of the at least two TS packets;
determine that the at least two TS packets cannot currently be egressed from the second port;
queue the at least two TS packets in a first queue of the plurality of queues based on the respective TS packet type and destination
address in response to determining that the at least two TS packets cannot currently be egressed, wherein the first queue
is associated with the second port; and

egress the at least two TS packets in the respective time window from the second port, wherein specifying the respective time
window of the determined egress comprises:

determining a quantity of the at least two TS packets to egress each egress period; and
configuring the respective time window to allow the egress of the quantity each egress period.

US Pat. No. 9,244,874

SELECTIVELY TRANSPARENT BRIDGE FOR PERIPHERAL COMPONENT INTERCONNECT EXPRESS BUS SYSTEMS

National Instruments Corp...

1. A system comprising:
a PCIe (Peripheral Component Interconnect Express) subsystem comprising PCIe devices;
a host system; and
a bus extender coupling the host system to the PCIe subsystem, and configured to:
create a virtual bus topology corresponding to an actual bus topology of the PCIe subsystem;
selectively hide one or more devices of the PCIe devices from the host system by omitting the one or more devices from the
virtual bus topology, resulting in the one or more devices being hidden from the host system, and remaining devices of the
PCIe devices being visible to the host system;

make the virtual bus topology apparent to the host system during configuration of the PCIe devices;
intercept configuration packets generated by the host system based on the virtual bus topology for configuring the visible
remaining devices; and

configure the selectively hidden one or more devices and the visible remaining devices according to the actual bus topology,
and based at least partially on contents of the intercepted configuration packets.

US Pat. No. 9,326,174

SPECTRAL STITCHING METHOD TO INCREASE INSTANTANEOUS BANDWIDTH IN VECTOR SIGNAL ANALYZERS

National Instruments Corp...

1. A method for processing a signal using a plurality of vector signal analyzers, the method comprising:
providing to each of the vector signal analyzers a respective component signal comprising a copy of a respective frequency
band of the signal, each respective frequency band having a respective center frequency and having a respective region of
overlap with at least one other respective frequency band, wherein a combination of the respective frequency bands comprises
an aggregate frequency band having an aggregate center frequency, wherein the respective center frequency of each respective
frequency band has a respective frequency offset from the aggregate center frequency, wherein each of the vector signal analyzers
is phase-locked and time-synchronized with respect to the other vector signal analyzers;

at each of the vector signal analyzers, processing the respective component signal, wherein said processing comprises:
digitizing at least the respective frequency band of the respective component signal;
frequency-shifting, after said digitizing, at least the respective frequency band of the respective component signal such
that the respective center frequency is offset from baseband by the respective frequency offset;

filtering at least the respective frequency band of the respective component signal, wherein said filtering of the respective
component signals is configured to cause a sum of the component signals to have a unity frequency response within each region
of overlap; and

adjusting gain and phase of at least the respective frequency band of the respective component signal, wherein said adjusting
gain and phase of the respective component signals is configured to cause the sum of the component signals to have a continuous
frequency response over the aggregate frequency band; and

summing the respective component signals to obtain a composite signal.

US Pat. No. 9,287,789

DC-TO-DC CONVERTER INPUT STAGE WITH CAPACITIVE CURRENT LIMIT

National Instruments Corp...

1. A converter input stage for transferring energy to an output stage:
an input configured to couple to a supply source providing an input voltage;
a pair of transformer coils;
switching circuitry configured to energize the pair of transformer coils, wherein in energizing the pair of transformer coils,
the switching circuitry is configured to apply an input signal to the pair of transformer coils according to the input voltage;
and

a limiting circuit coupled between the pair of transformer coils, and configured to cause the converter input stage to stop
drawing energy from the supply source once an amount of charge drawn from the supply source reaches a specific value;

wherein stored energy in a leakage inductance of the pair of transformer coils continues to provide power to the output stage
for at least a period of time, once the limiting circuit has caused the converter input stage to stop drawing energy from
the supply source.

US Pat. No. 9,098,164

PHYSICS BASED DIAGRAM EDITOR

National Instruments Corp...

1. A non-transitory computer-accessible memory medium that stores program instructions executable by a processor to implement:
displaying a graphical diagram on a display device, wherein the graphical diagram comprises a plurality of interconnected
icons;

receiving user input editing the graphical diagram, thereby generating an edited graphical diagram;
adjusting placement of one or more elements within the edited graphical diagram based on said editing, wherein said adjusting
is performed based on determined forces applied to the one or more elements in the edited graphical diagram, and wherein said
adjusting placement of one or more elements comprises:

determining one or more forces for each of the one or more elements based on their positions;
summing the forces on each of the one or more elements, thereby determining resultant forces;
moving the one or more elements based on the resultant forces; and
repeating said determining, said summing, and said moving one or more times in an iterative manner until an equilibrium condition
obtains, wherein said adjusting placement results in an adjusted edited graphical diagram; and

displaying the adjusted edited graphical diagram on the display device.

US Pat. No. 9,483,372

CONTINUOUS POWER LEVELING OF A SYSTEM UNDER TEST

NATIONAL INSTRUMENTS CORP...

1. A method, comprising:
executing an initial power leveling operation for a system under test (SUT), thereby establishing a specified power level;
testing the SUT after executing the initial power leveling operation, wherein said testing includes taking performance measurements
of the SUT; and

performing, during said testing the SUT, a plurality of power leveling operations for the power signal, wherein each of the
plurality of power leveling operations comprises:

measuring power of a signal generated by the SUT over a specified measuring interval, wherein the signal is generated by the
SUT in response to an input signal provided to the SUT; and

adjusting the input signal provided to the SUT based on said measuring;
wherein said performing the plurality of power leveling operations operates to maintain the specified power level during said
testing the SUT, thereby correcting for thermal droop.

US Pat. No. 9,098,307

REARRANGEMENT OF ALGEBRAIC EXPRESSIONS BASED ON OPERAND RANKING SCHEMES

National Instruments Corp...

1. A method for operating a compiler, the method comprising:
utilizing a computer to perform:
scanning program code to identify a first algebraic expression specified by the program code, wherein the first algebraic
expression includes two or more mutually-compatible binary operations and three or more input operands, wherein the three
or more input operands include two or more scalar operands and one or more array operands; and

operating on the first algebraic expression to obtain a final algebraic expression by:
(a) computing a rank vector for each of the three or more input operands, wherein the rank vector for any given one of the
three or more input operands includes a first component that is based on an invariance rank of the input operand and a second
component that is based on a dimension of the input operand, and

(b) performing transformations on selected subexpressions of the first algebraic expression, wherein the transformations include
one or more commute transformations and one or more associate transformations, wherein each of the commute transformations
exchanges input operands of a corresponding one of the two or more binary operations to order the input operands according
to an ordering of possible states of the rank vector, wherein the ordering of possible states gives precedence to the first
component over the second component;

wherein the final algebraic expression specifies an order of execution for the two or more binary operations such that the
three or more input operands are combined in an order that agrees with the ordering of possible states of the rank vector.

US Pat. No. 9,081,583

COMPILE TIME EXECUTION

National Instruments Corp...

1. A non-transitory computer-accessible memory medium that stores program instructions executable by a computer system to:
receive an input program representative of a design comprising one or more functions;
compile the received input program to produce an output;
during the compile of the received input program, after the compile starts, and before the compile completes:
generate information about one or more elements of the design by executing portions of the received input program, wherein
the portions are less than the entire input program, wherein at least one portion of the received input program is in a fan
in cone of array indices in the input program, wherein the information comprises information about value traces of the array
indices in the input program, and wherein said executing comprises:

determining and executing compiled executable instructions implementing each of the portions of the received program;
analyze the information; and
optimize the output by applying transformations to the compile, including applying one or more transformations to arrays or
array operations in the input program, responsive to analyzing the information.

US Pat. No. 9,459,295

MEASUREMENT SYSTEM UTILIZING A FREQUENCY-DITHERED LOCAL OSCILLATOR

National Instruments Corp...

1. A receiver system comprising:
an input configured to receive an input signal;
a signal generating circuit configured to generate a desired oscillator signal that is a single sideband radio frequency (RF)
signal, wherein an oscillation frequency of the desired oscillator signal shifts over time;

a downconversion stage configured to generate an intermediate frequency (IF) signal based on the input signal and the desired
oscillator signal; and

a signal processing block configured to produce an output signal based on the IF signal, wherein in generating the output
signal, the signal processing block is configured to track any signal in the IF that moves one-for-one in frequency with the
desired oscillator signal by frequency shifting receive data corresponding to the IF signal by an amount that compensates
for a shift of the oscillation frequency of the desired oscillator signal.

US Pat. No. 9,285,208

REAL-TIME RESAMPLING OF OPTICAL COHERENCE TOMOGRAPHY SIGNALS USING A FIELD PROGRAMMABLE GATE ARRAY

National Instruments Corp...

1. A method for performing optical coherence tomography (OCT), the method comprising:
receiving a control signal at a processing device;
receiving an OCT signal at the processing device;
extracting, by the processing device, phase information of the received control signal;
unwrapping, by the processing device, the extracted phase information;
multiplying, by the processing device, the unwrapped extracted phase information with an interpolation factor to obtain recalculated
phase information;

determining, by the processing device, one or more integer crossing points corresponding to the recalculated phase information;
interpolating, by the processing device, one or more values of the received OCT signal according to the determined one or
more integer crossing points; and

outputting a sampled version of the received OCT signal according to the interpolated one or more values of the received OCT
signal.

US Pat. No. 9,201,633

CREATION AND DEPLOYMENT OF RESTFUL WEB SERVICES IN A GRAPHICAL PROGRAMMING LANGUAGE

National Instruments Corp...

1. A method for generating a web service, the method comprising:
utilizing a computer to perform:
displaying a node representing a new web service in a graphical user interface (GUI) in response to user input invoking initial
creation of the new web service;

displaying a plurality of sub nodes in the GUI hierarchically below the node representing the web service, wherein the plurality
of sub nodes includes:

at least one sub node that represents startup resources, configured to perform initialization and communication with one or
more web methods for the web service; and

at least one sub node that represents web resources, configured for inclusion in the web service, wherein the web resources
implement the one or more web methods for the web service;

including one or more graphical data flow programs in the at least one sub node, in response to user input selecting the one
or more graphical data flow programs for inclusion in the web service, wherein each graphical data flow program comprises
a plurality of interconnected nodes that visually indicate functionality of the graphical data flow program, wherein each
graphical data flow program implements a respective startup resource or a respective web method that implements or requests
a respective action, and wherein at least one of the selected one or more graphical data flow programs implements a startup
resource; and

generating the web service based at least in part on the selected one or more graphical data flow programs, wherein the web
service is deployable to a server for hosting, wherein the web service is invocable over a network to perform the one or more
web methods.

US Pat. No. 9,189,209

GRAPHICAL PROGRAMMING SYSTEM WITH NATIVE ACCESS TO EXTERNAL MEMORY BUFFERS

National Instruments Corp...

1. A method comprising:
executing a graphical program on a computer system, wherein the graphical program includes a plurality of interconnected nodes
that visually indicate functionality of the graphical program, wherein the graphical program executes within a graphical program
execution environment;

wherein the plurality of interconnected nodes includes a first one or more nodes and a second one or more nodes, wherein the
first one or more nodes are configured to generate a reference to an external memory buffer in memory of the computer system,
wherein the external memory buffer is external to the graphical program execution environment, wherein said executing the
graphical program comprises the first one or more nodes executing to generate the reference to the external memory buffer;

wherein the first one or more nodes are connected to the second one or more nodes, wherein said executing the graphical program
further comprises the second one or more nodes executing to receive the reference to the external memory buffer and natively
access the external memory buffer to store data in the external memory buffer;

wherein the method further comprises executing a consumer program concurrently with the graphical program, wherein the consumer
program executes to access the data in the external memory buffer.

US Pat. No. 9,158,826

DATA RENDERING WITH SPECIFIED CONSTRAINTS

National Instruments Corp...

1. A non-transitory computer accessible memory medium that stores program instructions executable to perform:
receiving a request for data from a data set, wherein the data set comprises time-stamped historical data comprising a plurality
of reduced data sets, each reduced data set having a respective resolution, and wherein the request specifies a time frame;

determining a first reduced data set of the plurality of reduced data sets based on the specified time frame, wherein the
first reduced data set is specified or organized in intervals along an independent axis, wherein each interval comprises between
zero and a specified number of data points, and wherein said determining comprises:

for each interval that includes one or more data points, determining one or more characteristic data points for the interval,
comprising first, last, minimum, and maximum data points in the interval, wherein the characteristic data points for the interval
characterize the data for that interval, and wherein the one or more characteristic data points are associated with a respective
single value on the independent axis for the interval;

retrieving first data from the first reduced data set, wherein the first data corresponds to the specified time frame; and
displaying the first data on a display device, comprising:
for intervals that include one or more data points:
presenting a vertical line at the respective single value on the independent axis for the interval, wherein endpoints of the
vertical line are values on the dependent axis of the minimum and maximum data points for the interval;

connecting the vertical line to an immediately previous interval that includes one or more data points via a line from the
last data point of the immediately previous interval to the first data point of the interval, wherein said connecting crosses
any intervening empty intervals between the interval and the immediately previous interval that includes one or more data
points; and/or

connecting the vertical line to an immediately subsequent interval that includes one or more data points via a line from the
last data point of the interval to the first data point of the immediately subsequent interval, wherein said connecting crosses
any intervening empty intervals between the interval and the immediately subsequent interval that includes one or more data
points;

wherein the displayed first data visually indicates the character of the data from the data set.

US Pat. No. 9,135,131

CUSTOMIZING OPERATION OF A TEST INSTRUMENT BASED ON INFORMATION FROM A SYSTEM UNDER TEST

National Instruments Corp...

1. A method for customizing a test instrument, comprising:
utilizing a computer to perform:
storing first code for execution by a processor of the test instrument;
storing second code for implementation on a programmable hardware element of the test instrument;
receiving user input customizing the second code prior to said storing the second code, wherein the user input specifies adaptive
behavior for the test instrument based on information from a system under test (SUT);

generating and storing a hardware description for the programmable hardware element based on the user input;
wherein, after implementation of the hardware description on the programmable hardware element and during testing of the SUT
coupled to the test instrument, the test instrument is configured to determine information received from the SUT during testing
of the SUT;

wherein operation of the test instrument is automatically modified based on the adaptive behavior specified by the user input
and the information received from the SUT during testing of the SUT, wherein modification of the operation comprises one or
more of:

configuration of the test instrument; or
configuration of the SUT.

US Pat. No. 9,083,594

MECHANISM FOR PERFORMING EQUALIZATION WITHOUT PRIOR KNOWLEDGE OF MODULATION TYPE OR CONSTELLATION ORDER

National Instruments Corp...

1. A method for operating a receiver system to perform blind equalization, the method comprising:
receiving, by the receiver system, a communication signal from a communication channel in response to a transmission of a
transmit signal onto the communication channel by a transmitter;

generating, by the receiver system, samples of the received communication signal;
equalizing, by the receiver system, a block of the samples, wherein said equalizing includes minimizing a function J of a
vector argument f to determine a minimizing vector fMIN, wherein each evaluation of the function J includes convolving the vector argument f with the block of samples to obtain
a sequence {yn} of equalized samples, and evaluating a quadratic form in terms of expressions {|yn|2??}, wherein ? is a current modulus parameter value;

updating, by the receiver system, the current modulus parameter value ? based on a ratio of a fourth moment value to a second
moment value, wherein the fourth moment value is a fourth moment of the sequence {yn} corresponding to the minimizing vector fMIN, wherein the second moment value is a second moment of the sequence {yn} corresponding to the minimizing vector fMIN;

repeating said equalizing and said updating a plurality of times using respective blocks of the samples; and
convolving at least a subset of the samples with the minimizing vector fMIN from one of said repetitions of said equalizing and said updating in order to determine final equalized samples, wherein the
final equalized samples are representative of the transmit signal.

US Pat. No. 9,413,165

PROGRAMMABLE PROTECTED INPUT CIRCUITS

National Instruments Corp...

3. An electronic control unit comprising:
a plurality of inputs;
a different respective input protection circuit coupled to each input of the plurality of inputs, wherein each input protection
circuit comprises:

an input node coupled to a respective input of the plurality of inputs;
an output node configured to provide a protected output signal based on an input signal appearing at the respective input;
protection circuitry coupled between the input node and the output node, and configured to establish a current path that bypasses
the input node and pulls the output pin to a specified reference voltage level in the event of a transient at the input node;
and

a push-pull power supply configured to provide and maintain the specified reference voltage level for the current path, and
dissipate any excess voltage by burning it off in a semiconductor device comprised in the push-pull power supply.

US Pat. No. 9,286,258

OPAQUE BRIDGE FOR PERIPHERAL COMPONENT INTERCONNECT EXPRESS BUS SYSTEMS

National Instruments Corp...

14. A method for configuring and operating PCIe (Peripheral Component Interconnect Express) devices comprised in a PCIe subsystem
coupled to a host system, the method comprising:
preallocating specified one or more memory ranges to a bus extender appearing to the host system as a bridge to a bus of unknown
type;

configuring memory requirements of the PCIe devices, said configuring comprising:
using the preallocated specified one or more memory ranges; and
configuring the memory requirements without recognizing that the memory requirements are intended for PCIe devices.

US Pat. No. 9,188,617

USING A SHARED LOCAL OSCILLATOR TO MAKE LOW-NOISE VECTOR MEASUREMENTS

National Instruments Corp...

1. A measurement system comprising:
a local oscillator configured to generate a periodic signal;
a signal generator configured to receive the periodic signal, and generate a stimulus signal based on the received periodic
signal;

a test port configured to output a test signal based on the stimulus signal; and
a receiver configured to:
receive the periodic signal;
alternately receive, as an input signal, a first coupled signal derived from the stimulus signal, and a second coupled signal
derived from the stimulus signal;

generate an output signal based on the received input signal according to the periodic signal.

US Pat. No. 9,176,931

SOFTWARE TOOL FOR IMPLEMENTING MODIFIED QR DECOMPOSITION IN HARDWARE

National Instruments Corp...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a processor to implement:
including a first function in a first program in response to user input, wherein the first function is user configurable to
specify an auxiliary function to be performed by a modified QR decomposition circuit in addition to QR decomposition of a
matrix A into two matrices Q and R using a Modified Gram Schmidt (MGS) process, wherein Q represents an orthonormal basis
that spans a column space of A, and wherein R is a triangular matrix;

automatically generating a second program based on a configuration of the QR decomposition and the auxiliary function, wherein
the second program comprises program code that implements the QR decomposition and the auxiliary function for the first function
in the first program; and

automatically generating a hardware configuration program based on the first program, including the second program, wherein
the hardware configuration program is deployable to programmable hardware, thereby implementing the modified QR decomposition
circuit, including the QR decomposition of the matrix A and the auxiliary function;

wherein the hardware configuration program specifies that the modified QR decomposition circuit comprise:
an input;
a first set of hardware components, coupled to the input, wherein the first set of hardware components are dedicated to computing
matrix Q; and

an output;
wherein the input is configured to:
receive a first set of inputs at the input, wherein the first set of inputs includes the matrix A and a scaling factor ?;
wherein the first set of hardware components is configured to:
compute matrix Q based on the first set of inputs using the MGS process;
scale an identity matrix I by the scaling factor ?, thereby generating scaled identity matrix ?I;
receive a second set of inputs, wherein the second set of inputs is different from the first set of inputs, and wherein the
second set of inputs comprises the scaled identity matrix;

compute scaled matrix ?R?1 based on the second set of inputs using the MGS process;

unscale the scaled matrix ?R?1, thereby computing matrix R?1, wherein matrix R?1 is the inverse of matrix R; and

wherein the output is configured to:
output the matrix Q and/or matrix R?1 via the output.

US Pat. No. 9,128,132

RESAMPLING A SIGNAL TO PERFORM POWER QUALITY AND SYNCHROPHASOR MEASUREMENT

National Instruments Corp...

1. A method for performing synchrophasor and power quality analysis using shared resources, comprising:
measuring, by at least one power signal measurement device configured with power quality and synchrophasor analysis functionality,
power of a first power system, wherein said measuring produces a first power signal, wherein the first power signal is stored
in a memory medium, wherein the stored first power signal corresponds to the power system, and wherein the stored first power
signal comprises a plurality of cycles;

resampling, by the at least one power signal measurement device, the stored first power signal to generate a first even angle
power signal, wherein said resampling is performed using a first algorithm by a first one or more processing elements, wherein
said resampling the stored first power signal using the first algorithm comprises:

performing zero crossing detection on the stored first power signal, including determining start and end positions of each
of the plurality of cycles; and

determining even angle positions and a fundamental frequency for each cycle of the plurality of cycles of the stored first
power signal based on the determined start and end positions, wherein said resampling is based on the even angle positions
and fundamental frequency for each cycle;

performing, by the at least one power signal measurement device, one or more power quality measurements on the first even
angle power signal to perform the power quality analysis;

measuring, by the at least one power signal measurement device configured with power quality and synchrophasor analysis functionality,
power of a second power system, wherein said measuring produces a second power signal, wherein the second power signal is
stored in the memory medium, and wherein the stored second power signal comprises a plurality of cycles;

resampling, by the at least one power signal measurement device, the stored second power signal to generate a second even
angle power signal, wherein said resampling is performed using the first algorithm by the first one or more processing elements;
and

performing, by the at least one power signal measurement device, one or more synchrophasor measurements on the second even
angle power signal to perform the synchrophasor analysis.

US Pat. No. 9,106,474

LOSSLESS DATA STREAMING TO MULTIPLE CLIENTS

National Instruments Corp...

1. A system for streaming data in a lossless manner for test, measurement, automation, or control, the system comprising:
a host device, comprising:
a server; and
one or more host device internals;
configured to acquire data from a data source for test, measurement, automation, or control;
wherein the server is configured to:
communicate with one or more client devices over a network via a lossless transmission protocol;
receive an initial request from a first client device of the one or more client devices to initiate the acquisition of the
data by the server;

initiate the acquisition of the data in response to the initial request;
receive a request from at least one of the one or more client devices for data from the server, wherein the request specifies
a range of data to stream to the at least one client device; and

stream the data over the network to the at least one client device in a lossless manner for test, measurement, automation,
or control via the lossless transmission protocol in accordance with the request.

US Pat. No. 9,935,637

SYSTEMS AND METHODS FOR FPGA DEVELOPMENT AND OPERATION

NATIONAL INSTRUMENTS CORP...

1. A field programmable gate array (FPGA)-based scalable system, comprising:a first FPGA unit, comprising:
a partition for a user design;
a reconfigurable interface that is: (i) implemented using FPGA reconfigurable circuits, and (ii) configured to exchange data with the user design and each of a first interface unit and a second interface unit; and
a control interface configured to establish a first communication channel between the first interface unit and a first external module and a second communication channel between the second interface unit and a second external module; and
a processing module configured to run an operating environment that interfaces with the user design and observes and controls the user design during execution of the user design by the first FPGA unit.

US Pat. No. 9,063,691

ZERO CLIENT DEVICE WITH MULTI-BOOT CAPABILITY SUPPORTING MULTIPLE ZERO CLIENT PROTOCOLS

NATIONAL INSTRUMENTS CORP...

1. A zero client device, comprising:
a housing;
two or more transcoding processing units, comprised in the housing,
wherein each of the two or more transcoding processing units is implemented on a respective first circuit board,
wherein each of the two or more transcoding processing units is configured to implement and execute a respective different
zero client protocol, and wherein each zero client protocol is an application level protocol that specifies respective rules
for zero client communications of the zero client device; and

a communications processing unit, comprised in the housing and interfaced directly to the two or more transcoding processing
units, wherein the communications processing unit is configured to connect to devices over a network;

wherein the zero client device is configured to:
receive user input selecting a zero client protocol of the two or more different zero client protocols for operation;
select and initialize a transcoding processing unit corresponding to the selected zero client protocol, wherein only the transcoding
processing unit corresponding to the selected zero client protocol is initialized; and

establish a connection between the transcoding processing unit and human interface devices, including one or more peripheral
devices and a display device;

wherein the zero client device has no user-modifiable mass storage medium, preventing the zero client device from being configured
by a user;

wherein the communications processing unit is configured to:
determine an identifier of a server to which connection is desired; and
provide a network communication channel to the selected transcoding processing unit for accessing the server;
wherein the selected transcoding processing unit is configured to:
instantiate a zero client session with the server through the network communication channel provided by the communications
processing unit;

wherein the selected transcoding processing unit is further configured to:
receive input data from one or more human interface devices;
encode the input data; and
provide the encoded input data to the communications processing unit for transmission over the network to the server via the
zero client session;

wherein the communications processing unit is configured to:
receive the encoded input data from the selected transcoding processing unit;
transmit the encoded input data over the network to the server via the zero client session;
receive the output data from the server over the network via the zero client session;
decode the output data; and
send the decoded output data to at least one of the one or more human interface devices.

US Pat. No. 9,287,062

MAGNETIC SWITCHING SYSTEM

National Instruments Corp...

1. An analog switching element that is at least partially implemented in one or more printed wiring boards (PWBs), comprising:
a first input and a plurality of outputs integrated into the one or more PWBs;
a plurality of electromagnets, coupled to or comprised in at least one of the one or more PWBs; and
a plurality of floating contact bars, wherein each floating contact bar is comprised in a respective contact bar pocket internal
to at least one of the PWBs, wherein each floating contact bar comprises a conductive metal or alloy that is attracted by
a magnetic field;

wherein the switching element, via actuation of at least one of the floating contact bars by an externally applied magnetic
field of a respective one or more electromagnets, is selectively operable in:

a first state wherein the first input is coupled to a first output of the plurality of outputs such that an analog signal
input to the first input is routed to the first output; and

a second state wherein the first input is coupled to a second output of the plurality of outputs such that an analog signal
input to the first input is routed to the second output.

US Pat. No. 9,252,734

HIGH FREQUENCY HIGH ISOLATION MULTICHIP MODULE HYBRID PACKAGE

National Instruments Corp...

1. A high frequency module, comprising: a substrate including a first surface and a second surface substantially opposite
of the first surface, wherein the substrate comprises a multi-layer printed circuit board (PCB), wherein at least one layer
of the PCB is used for provision of direct current (DC) for power and control signals; a high frequency component mounted
on the second surface, wherein high frequency comprises radio, microwave, and/or optical frequencies, and wherein a DC current
is provided to the high frequency component using the at least one layer of the PCB; a conductive housing coupled to the second
surface of the substrate, wherein the conductive housing comprises: at least one opening extending through the conductive
housing, wherein the at least one opening forms a cavity, wherein the high frequency component is positioned in the cavity;
and at least one connector configured to convey a high frequency signal through the conductive housing to the high frequency
component; and a cover coupled to the conductive housing such that the high frequency component is positioned in the cavity
between the substrate and the cover; wherein during operation, the cavity independently constrains high frequency signals
to propagate through the high frequency component.

US Pat. No. 9,244,591

MOTION CONTROLLER WITH STANDARD AND USER CUSTOMIZED COMPONENTS

National Instruments Corp...

1. A non-transitory computer-readable memory medium comprising program instructions for developing a motion application, wherein
the program instructions are executable by a programmable logic controller (PLC) to implement:
a motion manager component, wherein the motion manager component implements:
a supervisory control function and at least one trajectory generation algorithm;
a first application programming interface (API) that interfaces the motion manager component to a user developed motion control
application on the PLC; and

a second API that allows a user developed custom communication interface program on the PLC to read drive command data from
the motion manager component and write drive current data to the motion manager component, wherein the user developed custom
communication interface program is executable by the PLC to communicate with a motion element comprising a motion drive device
configured to move an actuator.

US Pat. No. 9,189,215

CONVERGENCE ANALYSIS OF PROGRAM VARIABLES

National Instruments Corp...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a processor to implement:
determining, based on dependencies of one or more variables in a first program, one or more state variables of the first program,
wherein the one or more variables comprise one or more of:

at least one variable in at least one array indexing expression for an array in the first program;
at least one set of variables that is dependent upon itself; or
at least one variable whose value is set by an operation that includes input or output range properties to be optimized;
creating, based on the one or more state variables and dependencies of the one or more state variables, a second program corresponding
to the first program;

executing the second program a plurality of times, comprising:
for each execution:
recording values of the one or more state variables;
determining an execution count;
comparing the values to corresponding values from previous executions of the second program; and
terminating said executing in response to determining that the values match corresponding values from at least one previous
execution of the second program;

determining, based on the execution count, a convergence property for the first program that indicates a number of executions
of the first program required to generate all possible values of the one or more variables; and

storing the convergence property, wherein the convergence property is useable to optimize the first program.

US Pat. No. 9,651,585

VIA LAYOUT TECHNIQUES FOR IMPROVED LOW CURRENT MEASUREMENTS

NATIONAL INSTRUMENTS CORP...

1. A printed circuit board (PCB), comprising:
first and second measurement nodes, wherein the first and second measurement nodes are configured to measure current responsive
to an applied signal; and

a plurality of rows of vias configured to establish a plurality of current pathways away from the first measurement node,
wherein the plurality of current pathways reduce leakage current resulting from dielectric absorption at the first measurement
node responsive to the applied signal.

US Pat. No. 9,411,920

SPECIFYING AND IMPLEMENTING RELATIVE HARDWARE CLOCKING IN A HIGH LEVEL PROGRAMMING LANGUAGE

National Instruments Corp...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a processor to implement:
receiving user input specifying a program, wherein the program is specified for deployment to a programmable hardware element,
and wherein the program comprises:

a first code portion; and
a second code portion;
wherein the first code portion and the second code portion are configured to communicate with each other during execution;
and

wherein the user input specifying the program further specifies:
a rational ratio of respective execution rates for the first code portion and the second code portion; and
automatically generating a hardware configuration program implementing the specified program, including automatically determining
a respective clock rate for at least one of the first code portion or the second code portion based at least in part on the
specified rational ratio of respective execution rates for the first code portion and the second code portion;

wherein the hardware configuration program is deployable to the programmable hardware element, including implementing first
and second clocks for controlling execution of the first code portion and the second code portion in accordance with the specified
rational ratio and the automatically determined respective clock rate for the at least one of the first code portion or the
second code portion.

US Pat. No. 9,332,450

UNIT TESTING AND ANALYSIS OF MULTIPLE UUTS

National Instruments Corp...

1. A non-transitory computer accessible memory medium that stores program instructions for testing units under test (UUTs),
wherein the program instructions are executable to implement:
performing at least one test on each UUT of a plurality of UUTs, comprising:
for each respective UUT of the plurality of UUTs:
acquiring a respective signal from the respective UUT;
retrieving a reference signal, wherein the reference signal is derived from a transmitted signal that is characteristic of
the respective UUT; and

analyzing the respective signal with respect to the reference signal;
wherein synchronization of acquiring the respective signal to the reference signal is based on a latency of an initial test,
wherein the latency is determined by elapsed time between initiating an initial stimulus signal and receiving an initial response;
and

storing results of said performing the at least one test on each UUT of the plurality of UUTs, wherein the results are useable
to characterize each UUT of the plurality of UUTs.

US Pat. No. 9,262,129

MIXED SIGNAL ANALYSIS

National Instruments Corp...

1. A non-transitory computer readable memory medium comprising program instructions for implementing an integrated interface
for a plurality of instruments for signal analysis, wherein the memory medium is in a computer system comprising a display,
wherein the program instructions are executable to implement:
a) receiving user input specifying an operation, wherein the operation implements at least a portion of a signal analysis
function;

b) performing the operation in response to the specifying, wherein said performing utilizes at least one of the plurality
of instruments to perform the operation;

c) displaying an icon on the display in response to said specifying, wherein the icon comprises a graphical representation
of the operation, and wherein the icon is displayed upon said specifying;

d) storing information specifying the operation; and
repeating a)-d) a plurality of times to specify the signal analysis function;
wherein the operations in the signal analysis function comprise at least one of 1) generating signals displayed in a graph,
and 2) modifying one or more signals displayed in the graph;

wherein, during said repeating, each of the user specified operations continues to be performed;
wherein the signal analysis function utilizes at least a first plurality of the plurality of instruments;
wherein after said repeating a plurality of icons are displayed on the display representing a plurality of operations, wherein
the plurality of icons are arranged to visually indicate the signal analysis function; and

wherein said repeating produces a set of stored information representing the plurality of operations in the signal analysis
function.

US Pat. No. 9,250,894

SEQUENTIALLY CONSTRUCTIVE MODEL OF COMPUTATION

National Instruments Corp...

1. A computer-implemented method, comprising:
utilizing a computing system to perform:
receiving a program, wherein the program specifies a plurality of operations using a variable within a logical tick such that
the variable has multiple values within the logical tick;

statically analyzing the program according to a specified model of computation that specifies program execution based on logical
ticks, wherein said statically analyzing the program includes:

determining that the program has deterministic semantics, wherein the deterministic semantics specify deterministic results
for each logical tick during execution of the program, including specifying deterministic results of the plurality of operations
performed within the logical tick;

wherein the deterministic semantics is based on, within a given logical tick:
a scheduling of operations that are sequential with respect to each other as specified by the program according to the specified
sequence; and

a scheduling of operations that are concurrent with each other such that assignments to a variable are performed before reads
of the variable, including scheduling the assignment operations to the variable that are concurrent with each other such that
a first assignment operation is scheduled before one or more other assignment operations, wherein the order of the one or
more other assignment operations does not influence a final result of the variable for the logical tick; and

validating the program in accordance with the specified model of computation in response to said determining.

US Pat. No. 9,047,168

AUTOMATICALLY GENERATING DOCUMENTATION FOR A DIAGRAM INCLUDING A PLURALITY OF STATES AND TRANSITIONS

National Instruments Corp...

1. A non-transitory computer accessible memory medium storing program instructions executable by a processor to:
store a first diagram, wherein the first diagram specifies a plurality of states and a plurality of transitions between the
states, wherein the first diagram includes a plurality of state icons, wherein each of the state icons represents one of the
states, wherein the first diagram specifies first functionality;

automatically generate user documentation for the first diagram based on the first diagram, wherein the user documentation
describes the first diagram, wherein in said automatically generating the user documentation, the program instructions are
executable by the processor to automatically include one or more images of one or more of the state icons in the user documentation
and to automatically include human language describing the plurality of states and the plurality of transitions of the first
diagram in the user documentation, and wherein automatic generation of the user documentation is performed without manual
user input specifying the user documentation, wherein said generating the user documentation comprises generating one or more
markup language files, wherein the human language describing the plurality of states and the plurality of transitions of the
first diagram is included in the one or more markup language files; and

display the user documentation on a display, wherein in said displaying the user documentation, the program instructions are
executable by the processor to display the one or more images and display the human language describing the plurality of states
and the plurality of transitions of the first diagram.

US Pat. No. 9,935,757

CHANNEL QUALITY REPORTING FOR FULL-DUPLEX RADIO

NATIONAL INSTRUMENTS CORP...

1. An apparatus, comprising:one or more processing elements including analog self-interference cancelation (SIC) circuitry and one or more digital SIC processing elements, wherein the one or more processing elements are configured to:
receive a reference signal in a wireless communication; and
determine an effective signal to interference plus noise ratio (SINR) for full-duplex (FD) communications, based on the reference signal, wherein the effective SINR for FD communications is based on:
a measured SINR of the reference signal; and
one or more measured self-interference cancelation (SIC) levels that include an analog SIC level generated by the analog SIC circuitry and a digital SIC level generated by the one or more digital SIC processing elements, wherein the analog SIC level is determined based on power of a wireless transmission by the apparatus and a measured residual power of the wireless transmission after analog self-interference cancelation.

US Pat. No. 9,495,265

TEST EXECUTIVE SYSTEM WITH PROCESSING OF RESULTS DATA IN CHUNKS

National Instruments Corp...

10. A non-transitory computer-accessible memory medium that stores program instructions executable by one or more processors
to implement:
creating a test executive sequence, wherein the test executive sequence includes a first plurality of steps to be performed
by a test executive engine to test a unit under test (UUT); and

configuring the test executive sequence with a process model, wherein the process model includes a second plurality of steps
to be performed by the test executive engine before and/or after executing the first plurality of steps, wherein the process
model is configured to accept process model plug-ins to define the second plurality of steps, wherein said configuring the
test executive sequence with the process model comprises selecting one or more process model plug-ins for the process model,
wherein each process model plug-in includes two or more of the second plurality of steps;

wherein the one or more process model plug-ins include a first process model plug-in configured to store and/or process test
result data dispatched to the first process model plug-in in chunks, wherein chunk size is controllable by an auto-tuned threshold
that is based on time measured for the dispatch and processing of prior results.

US Pat. No. 9,483,304

INTERFACE WIRES FOR A MEASUREMENT SYSTEM DIAGRAM

NATIONAL INSTRUMENTS CORP...

1. A method comprising:
a computer system displaying a first node and a second node in a system diagram, wherein the first node comprises program
code, wherein the second node implements one or more software object interfaces, wherein each software object interface includes
one or more callable software functions, wherein the system diagram visually indicates one or more hardware devices on which
the first node and the second node are deployed;

the computer system adding and displaying a wire connecting the first node to the second node in response to user input; and
the computer system automatically configuring the first node to access at least one of the one or more software object interfaces
of the second node in response to said adding and displaying the wire, wherein said automatically configuring comprises automatically
modifying the program code of the first node to enable the first node to use the one or more callable software functions of
the second node, and wherein after said automatically configuring, the first node is operable to call the one or more callable
software functions of the at least one software object interface at runtime to communicate with the second node;

wherein the first node is implemented by a graphical program;
wherein the computer system automatically configures the first node to access the at least one of the one or more interfaces
of the second node by automatically modifying the graphical program.

US Pat. No. 9,476,919

LOW PROFILE CURRENT MEASUREMENT CONNECTOR AND USE

NATIONAL INSTRUMENTS CORP...

1. A current measurement connector, comprising:
a first part, wherein the first part comprises:
a first mount; and
a first joint;
a second part, wherein the second part is physically separate and distinct from the first part, and wherein the second part
comprises:

a second mount; and
a second joint; and
a current transformer, interposed between the first part and the second part;
wherein the first part and the second part physically connect together at and via the first and second joints and extend through
the current transformer, thereby electrically coupling the first mount to the second mount so as to allow the first mount
and the second mount to conductively receive a first current from a current source; and

wherein the current measurement connector is configured to pass the first current from the current source through the first
and second joints thereby inducing a second current in the current transformer, wherein the second current is useable to measure
the first current.

US Pat. No. 9,418,338

DETERMINATION OF UNCERTAINTY MEASURE FOR ESTIMATE OF NOISE POWER SPECTRAL DENSITY

National Instruments Corp...

1. A method comprising:
determining at a computational device a measure of uncertainty for an estimate of a power spectral density of a noise signal,
wherein the estimate is determined by computing an average of n power spectral densities derived from n respective sets of
samples of the noise signal, wherein each of the n power spectral densities is computed based on a corresponding one of the
sample sets, wherein said determining the uncertainty measure includes computing the uncertainty measure based on the number
n, wherein said determining the uncertainty measure includes computing an effective number of independent averages corresponding
to said power spectral density estimate based on data including the number n and a relative amount of overlap between successive
ones of the n sample sets, wherein the uncertainty measure is computed based on the effective number of independent averages;
and

storing the uncertainty measure in a memory.

US Pat. No. 9,294,057

EFFICIENT LOW NOISE HIGH SPEED AMPLIFIER

National Instruments Corp...

1. An amplifier structure comprising:
a switching amplifier configured to generate a first amplified output signal, wherein the first amplified output signal has
an amplitude referenced to a value of a reference voltage provided at a reference node for the switching amplifier, wherein
the reference voltage provided at the reference node provides a signal reference of the switching amplifier instead of the
signal reference of the switching amplifier being provided by actual ground; and

a linear amplifier coupled to the switching amplifier and configured to:
generate a second amplified output signal based at least on an input signal; and
adjust the value of the reference voltage at the reference node, wherein to adjust the value of the reference voltage at the
reference node, the linear amplifier is further configured to drive the reference node with the second amplified output signal.

US Pat. No. 9,137,044

SYSTEM AND METHOD FOR INTEROPERABILITY BETWEEN MULTIPLE NETWORKS

National Instruments Corp...

7. A method for interoperating between a time-sensitive (TS) network and a non-time-sensitive (NTS) network, the method comprising:
configuring a TS network switch, comprising a plurality of ports and a first functional unit coupled to the plurality of ports,
wherein said configuring comprises:

configuring a first port of the plurality of ports to couple to an NTS node of the NTS network; and
configuring a second port of the plurality of ports to couple to a TS network interface controller (NIC); and
configuring the first functional unit to:
insert a virtual local area network (VLAN) tag indicating the NTS network into each NTS packet received from the NTS network
by the first port before routing each NTS packet to one or more other ports of the plurality of ports in the TS network switch,
thereby generating tagged NTS packets; and

remove the VLAN tag from each received VLAN tagged NTS packet before forwarding, via the first port, each received VLAN tagged
NTS packet to the NTS node;

receive one or more of the tagged NTS packets from the first port and forward, via the second port, the one or more tagged
NTS packets to the TS NIC; and

receive, by the second port, tagged NTS packets from the TS NIC and route tagged NTS packets to the first port; and
configuring the TS NIC, wherein the TS NIC comprises:
a second functional unit;
a third port, coupled to the second functional unit;
a plurality of NTS receive packet queues, coupled to the second functional unit and the third port, configured to store received
packets from respective NTS networks, wherein a first NTS receive packet queue corresponds to the NTS network; and

a corresponding plurality of NTS transmit packet queues, coupled to the second functional unit and the third port, configured
to store packets received from a device coupled to the TS NIC for the respective NTS networks, wherein a first NTS transmit
packet queue corresponds to the NTS network; and

wherein said configuring the TS NIC comprises:
configuring the second functional unit to:
queue tagged NTS packets received via the third port in the first NTS receive packet queue for subsequent provision to the
device coupled to the TS NIC; and

queue NTS packets received from the device coupled to the TS NIC in the first NTS transmit packet queue and insert the VLAN
tag indicating the NTS network into each NTS packet received from the first NTS transmit packet queue before forwarding, via
the third port, each NTS packet to the second port, thereby generating tagged NTS packets.

US Pat. No. 9,310,975

AUTOMATICALLY DETERMINING DATA TRANSFER FUNCTIONALITY FOR WIRES IN A GRAPHICAL DIAGRAM

National Instruments Corp...

1. A non-transitory computer accessible memory medium comprising program instructions for creating a diagram, wherein the
program instructions are executable to:
receive user input connecting a wire to an output of a first node and an input of a second node, wherein the first node, the
second node, and the wire are comprised in the graphical diagram, and wherein the first wire indicates that data produced
on the output of the first node is provided to the input of the second node;

automatically determine data transfer functionality of the wire based on at least one of the first node or the second node,
wherein the data transfer functionality comprises one or more of:

data exchange semantics;
data transport protocol; or
data transport medium; and
store information on a memory medium which specifies the determined data transfer functionality of the wire;
wherein during execution of the diagram data are transferred between the first node and the second node according to the data
transfer functionality.

US Pat. No. 9,336,051

PROGRAMMABLE CONTROLLER WITH MULTIPLE PROCESSORS USING A SCANNING ARCHITECTURE

National Instruments Corp...

1. A programmable controller, comprising:
a plurality of channels for receiving input;
a plurality of processors, the plurality of processors comprising a first one or more processors and a second one or more
processors;

at least one memory medium coupled to the plurality of processors and the plurality of channels, wherein the memory medium
stores:

an I/O scanning engine that is executable by at least one of the first one or more processors, wherein the I/O scanning engine
is executable to receive input from the plurality of channels of the programmable controller according to a scanning architecture;

a plurality of user programs, wherein the plurality of user programs are each executable to perform a function based on input
received from the plurality of channels;

a scheduler program that is executable by at least one of the processors, wherein the scheduler program is executable to allocate
each of the plurality of user programs to respective one or more of the plurality of processors, wherein the scheduler program
is executable to schedule each of at least two user programs to execute on a respective one or more processors concurrently;

wherein the scheduler program is executable to dynamically schedule a first subset of the plurality of user programs to execute
on the first one or more processors according to the scanning architecture, wherein the scanning architecture specifies that
execution of the first subset of the plurality of user programs is time-driven according to a periodic execution cycle, not
in response to asynchronous events; and

wherein the scheduler program is executable to dynamically schedule a second subset of the plurality of user programs to execute
on the second one or more processors in response to asynchronous events, not according to a periodic execution cycle, and
wherein execution of the second subset of the plurality of user programs on the second one or more processors does not introduce
a delay in execution of the first subset of the plurality of user programs executing on the first one or more processors.

US Pat. No. 9,047,007

SEMANTIC ZOOM WITHIN A DIAGRAM OF A SYSTEM

National Instruments Corp...

1. A non-transitory, computer accessible memory medium storing program instructions for performing semantic zoom in a diagram
of a hardware system, wherein the program instructions are executable to:
display the diagram of the hardware system, wherein the diagram comprises a plurality of icons representing electronic hardware
components of the hardware system, wherein the diagram further comprises a plurality of graphical wires connecting the icons
representing the electronic hardware components, wherein the graphical wires represent physical connectivity between the electronic
hardware components in the hardware system, wherein the plurality of icons comprise a first icon representing a first electronic
hardware component, wherein the first icon is displayed at a first level of magnification, wherein the first icon visually
depicts a first representation of the first electronic hardware component;

receive user input to zoom on a first position of the diagram, wherein the first icon is displayed proximate to the first
position of the diagram;

update the diagram to zoom on the first position in response to the user input, wherein said updating the diagram comprises
displaying the first icon at a second level of magnification that is greater than the first level of magnification, wherein,
after updating the diagram, the first icon visually depicts a second representation of the first electronic hardware component,
and wherein the first representation is less complex than the second representation and shows less information regarding the
electronic hardware component than the second representation, and wherein the second representation of the first electronic
hardware component comprises one or more of:

a detailed image of the first electronic hardware component;
one or more icons representing software components implemented by or deployed on the first electronic hardware component;
or

a hardware schematic of the first electronic hardware component.

US Pat. No. 9,323,699

METHODS FOR DATA ACQUISITION SYSTEMS IN REAL TIME APPLICATIONS

National Instruments Corp...

1. A peripheral device comprising:
a function module configured to acquire data samples, and further configured to generate one or more process interrupts associated
with acquiring the data samples;

a bus interface module coupled to the function module and configured to interface with a host system via a bus, wherein the
bus interface module is configured to:

receive the one or more process interrupts generated by the function module;
gather interrupt information required to handle the one or more process interrupts, wherein the interrupt information comprises
respective interrupt status information associated with each respective process interrupt of the one or more process interrupts,
wherein the respective interrupt status information is used for servicing the respective process interrupt;

transmit the interrupt information through the bus to a first location in system memory configured in the host system;
transmit to a second location in the system memory, through the bus, identification information identifying the one or more
process interrupts, wherein the identification information comprises respective identification information corresponding to
each respective process interrupt wherein the respective identification information is used for identifying the respective
process interrupt so the respective process interrupt can be serviced; and

generate and transmit a system interrupt to the host system through the bus, once the interrupt information and the identification
information have been transmitted through the bus, wherein the system interrupt notifies the host system of the one or more
process interrupts.

US Pat. No. 9,048,775

H-BRIDGE FOR COMBINED SOLENOID AND PIEZO INJECTION CONTROL

National Instruments Corp...

1. A drive circuit comprising:
a plurality (N) of pins, each pin of the N pins configured to couple to an actuator; and
a plurality (M) of switches;
wherein each pin of the N pins is coupled to:
a different respective low-side switch of the M switches; and
a different respective set of high-side switches of the M switches;
wherein the switches are configured to be selectively operated to control a specified number of actuators according to:
a multiplexing configuration that defines a connectivity between at least a subset of pins of the N pins and the specified
number of actuators; and

actuator type of each actuator of the specified number of actuators.

US Pat. No. 9,065,609

BLIND MECHANISM FOR ESTIMATION AND CORRECTION OF I/Q IMPAIRMENTS

National Instruments Corp...

1. A method for blind estimation of receiver correction parameters, the method comprising:
(a) receiving complex samples of a complex baseband signal from a receiver;
(b) computing a value of cross-correlation between a I component of the complex samples and a Q component of the complex samples,
wherein the cross-correlation is a time-domain cross correlation between the I component and the Q component;

(c) computing a mean square value IMS of the I component of the complex samples, and computing a mean square value QMS of the Q component of the complex samples;

(d) computing an estimate for a cross-channel gain k based on the cross-correlation value and one or both of the mean square
values IMS and QMS;

(e) applying a cross-channel gain correction to the complex samples based on the estimate for the cross-channel gain k, in
order to obtain modified complex samples;

(f) computing an estimate of a gain imbalance based on the mean square values IMS and QMS, wherein the gain imbalance estimate is useable to correct an I/Q gain imbalance present in the complex samples;

computing an estimate of an I-channel DC offset based on the I component of the complex samples;
computing an estimate of a Q-channel DC offset based on the Q component of the complex samples; and
applying DC offset corrections to the complex samples of the complex baseband signal based on the estimate of the I-channel
DC offset and the estimate of the Q-channel DC offset.

US Pat. No. 9,910,074

DIGITAL APPROACH TO THE REMOVAL OF AC PARASITICS FOR IMPEDANCE MEASUREMENTS

NATIONAL INSTRUMENTS CORP...

1. A measurement circuit comprising:
a first test terminal configured to couple to a first device terminal of a device under test (DUT);
a second test terminal configured to couple to a second device terminal of the DUT;
a first control circuit configured to generate a first control signal with a respective programmable frequency and respective
continuously variable phase and amplitude, and configured to develop at least a portion of a first voltage at the first device
terminal of the DUT by providing the first control signal to the first terminal; and

a second control circuit configured to generate a second control signal with a respective programmable frequency and respective
continuously variable phase and amplitude, and configured to develop at least a portion of a second voltage at the second
device terminal of the DUT by providing the second control signal to a shunt element coupled to the second terminal;

wherein the respective phase and amplitude of the first control signal and the respective phase and amplitude of the second
control signal are adjustable to cause the second voltage to remain at a specified value that is within a specified range
inclusive of a nominal value.

US Pat. No. 9,335,977

OPTIMIZATION OF A DATA FLOW PROGRAM BASED ON ACCESS PATTERN INFORMATION

National Instruments Corp...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a processor to implement:
receiving access pattern information for a data flow diagram, wherein the data flow diagram includes a plurality of interconnected
actors visually indicating functionality of the data flow diagram, wherein the access pattern information includes one or
more of: a) input pattern information specifying the time at which tokens are consumed by at least one of the actors, or b)
output pattern information specifying the time at which tokens are produced by at least one of the actors;

generating a program that implements the functionality of the data flow diagram based at least in part on the access pattern
information, wherein the functionality comprises digital signal processing (DSP) and communications, industrial test and measurement,
or industrial automation and control; and

configuring a hardware device according to the generated program.

US Pat. No. 9,250,272

LOW PROFILE CURRENT MEASUREMENT CONNECTOR

National Instruments Corp...

1. A current measurement connector, comprising:
a first part, wherein the first part comprises:
a first mount; and
a first joint;
a second part, wherein the second part comprises:
a second mount; and
a second joint;
a current transformer, interposed between the first part and the second part; and
a spacer, interposed between the first mount and the second mount, wherein the spacer is configured to:
isolate the first mount and second mount from mechanical vibration; and
prevent an alternative electrical coupling between the first mount and second mount
wherein the first part and the second part connect at the first and second joints through the current transformer, thereby
electrically coupling the first mount to the second mount, wherein the first mount and the second mount are configured to
receive a first current from a current source; and

wherein the current measurement connector is configured to pass the first current from the current source through the first
and second joints thereby inducing a second current in the current transformer, wherein the second current is useable to measure
the first current.

US Pat. No. 10,019,286

TIME CRITICAL TASKS SCHEDULING

NATIONAL INSTRUMENTS CORP...

1. An apparatus for scheduling a time critical task, the apparatus comprising:a hardware assist scheduler; and
a memory coupled to the hardware assist scheduler;
wherein the apparatus is configured to:
determine a schedule for the time critical task based on received timing information, wherein the schedule comprises a wakeup time, a specified thread bandwidth and an overall thread deadline, wherein the time critical task executes program instructions via a thread on a core of the processing unit in accordance with the schedule, and wherein the processing unit is configured to communicate with the memory and the hardware assist scheduler; and
suspend execution of the time critical task via assertion of a thread interrupt in response to a lateness timer expiring, wherein the lateness timer is based on the wakeup time.

US Pat. No. 9,251,296

INTERACTIVELY SETTING A SEARCH VALUE IN A DATA FINDER TOOL

National Instruments Corp...

1. A computer-accessible memory medium storing program instructions executable to:
create an index of a plurality of measurement data files, wherein each measurement data file includes a plurality of measurements,
wherein each measurement includes measurement data and meta-data describing attributes and attribute values of the measurement
data, wherein creating the index comprises adding the meta-data from the measurement data files to the index;

receive user input specifying a particular measurement data attribute to be used in search criteria for desired measurement
data, wherein the search criteria also requires an attribute value for the measurement data attribute;

search the index to find a plurality of possible attribute values for the particular measurement data attribute to be used
in the search criteria, wherein each of the possible attribute values matches one or more of the indexed measurements and
is found by retrieving the meta-data of the one or more measurements from the index;

display the plurality of possible attribute values for the particular measurement data attribute in response to said searching;
receive user input selecting a particular attribute value from the displayed plurality of possible attribute values;
complete the search criteria by including the particular attribute value in the search criteria in response to the user input
selecting the particular attribute value; and

search for the desired measurement data using the completed search criteria, wherein said searching for the desired measurement
data uses the particular measurement data attribute and the particular attribute value.

US Pat. No. 9,854,552

METHOD AND APPARATUS FOR IMPROVED SCHMIDL-COX-BASED SIGNAL DETECTION

NATIONAL INSTRUMENTS CORP...

1. A method, comprising:
generating an autocorrelation result for a training field in a received wireless message;
generating differentiation information based on the autocorrelation result;
determining that one or more signal recognition criteria are met, wherein the signal recognition criteria include:
a first criterion that a first peak in the differentiation information satisfies a first threshold for at least a first time
interval; and

one or more additional criterion that include at least one of:
a second criterion that a second peak in the differentiation information satisfies a second threshold for at least a second
time interval, wherein the first and second peaks have different polarities;

a third criterion that the first peak corresponds to an autocorrelation result value that is below a particular autocorrelation
threshold; and

performing at least one of time synchronization or frequency synchronization for the wireless message in response to determining
that the one or more signal recognition criteria are met.

US Pat. No. 9,489,181

CORRELATION ANALYSIS OF PROGRAM STRUCTURES

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a processor to implement:
storing a program, wherein the program comprises a plurality of program structures and one or more data objects, wherein each
of the one or more data objects is shared by a respective at least two program structures of the plurality of program structures;

for each program structure of the plurality of program structures, analyzing decomposition effects on each of the one or more
data objects resulting from each of a respective one or more optimizing transforms applied to the program structure, wherein
said analyzing comprises:

applying, for at least one transform of the respective one or more optimizing transforms, a corresponding transform to a model
of the program structure and the at least one data object, wherein said applying generates estimated decomposition effects
of the at least one transform; and

analyzing the estimated decomposition effects;
determining, based on said analyzing the estimated decomposition effects, a plurality of groups of correlated structures of
which two or more groups share a program structure, each group comprising:

two or more program structures that share at least one data object; and
at least one optimizing transform that is compatible with respect to the two or more program structures and the shared at
least one data object;

analyzing the two or more groups;
determining, based on said analyzing the two or more groups, that a respective at least one optimizing transform of at least
two of the two or more groups is compatible with all other groups of the two or more groups;

analyzing each of the respective at least one optimizing transforms of the at least two of the two or more groups;
selecting a first respective at least one optimizing transform based on said analyzing each of the respective at least one
optimizing transforms; and

transforming the respective two or more program structures and the at least one data object of each of the two or more groups
to meet the specified optimization objective, using the first respective at least one optimizing transform.

US Pat. No. 9,477,566

POWER LEVELING OF A SYSTEM UNDER TEST

NATIONAL INSTRUMENTS CORP...

1. A method for adjusting a signal provided to a system under test (SUT), the method comprising:
providing an input signal at an initial power level to the SUT; and
performing a plurality of iterations, wherein each iteration includes:
measuring, over a specified measuring interval, power of a signal produced by the SUT in response to the input signal; and
dynamically adjusting the power level of the input signal provided to the SUT based on said measuring;
wherein said performing the plurality of iterations comprises:
increasing the specified measuring interval over the plurality of iterations, thereby increasing accuracy of said measuring
over the plurality of iterations while converging the signal to a specified power level.

US Pat. No. 9,252,470

ULTRA-BROADBAND DIPLEXER USING WAVEGUIDE AND PLANAR TRANSMISSION LINES

National Instruments Corp...

1. A diplexer comprising:
an input configured to receive a broadband signal, wherein the input is configured to couple to a first coaxial transmission
line;

a first output, configured to couple to a second coaxial transmission line;
a low-pass filter configured to receive the broadband signal and further configured to provide a first output signal to the
first output, wherein the first output is configured to convey the first output signal, and wherein the low-pass filter is
implemented using a planar transmission line;

a second output, configured to couple to a third coaxial transmission line;
a high-pass filter configured to receive the broadband signal and to provide a second output signal to the second output,
wherein the second output is configured to convey the second output signal, wherein the high-pass filter is implemented using
a waveguide.

US Pat. No. 9,246,852

LOSSLESS TIME BASED DATA ACQUISITION AND CONTROL IN A DISTRIBUTED SYSTEM

National Instruments Corp...

1. A method for configuring the mapping of an iterative time-based data acquisition (DAQ) operation to an isochronous data
transfer channel of a network, the method comprising:
configuring buffer size of a time-sensitive buffer (TSB) for the iterative time-based DAQ operation, wherein the iterative
time-based DAQ operation comprises an associated data transfer per iteration, wherein a block of data comprises data transferred
by one or more of the associated data transfers, and wherein the TSB is associated with the isochronous data transfer channel
of the network;

configuring a transfer frequency of the TSB;
configuring a data rate clock to synchronize to a global clock of the network;
configuring a start time for transferring one or more blocks of data to the TSB based on the buffer size, a start time of
the iterative time-based DAQ operation, a data rate of the iterative time-based DAQ operation in accordance with the data
rate clock, and size of a block of the data transferred, wherein the start time of the iterative time-based DAQ operation
is in phase with the global clock of the network;

configuring a size of a local buffer based on the size of the block of the data transferred, the transfer frequency of the
TSB, and the data rate of the iterative time-based DAQ operation;

configuring the local buffer for transfer of the one or more blocks of data to the local buffer in response to continuous
performance of the iterative time-based DAQ operation;

configuring a functional unit to:
initiate the continuous performance of the iterative time-based DAQ operation at the start time of the iterative time-based
DAQ operation;

transfer the one or more blocks of data to the local buffer in response to the continuous performance of the iterative time-based
DAQ operation;

initiate transfer of the one or more blocks of data between the local buffer and the TSB at the start time for transferring
the one or more blocks of data; and

repeat said transferring and said initiating transfer one or more times in an iterative manner, thereby transferring the one
or more blocks of data between the local buffer and the TSB; and

configuring the TSB to communicate the one or more blocks of data over the isochronous data transfer channel of the network
over at least one cycle at the transfer frequency of the TSB, thereby mapping the iterative time-based DAQ operation to the
isochronous data transfer channel of the network.

US Pat. No. 9,477,386

SYSTEMS AND METHODS FOR HIGH THROUGHPUT SIGNAL PROCESSING USING INTERLEAVED DATA CONVERTERS

NATIONAL INSTRUMENTS CORP...

1. A method for processing a signal, the method comprising:
configuring a programmable hardware element of a device to comprise a plurality N of processing portions, wherein the number
N of processing portions is based on a processing rate of the programmable hardware element and an effective sampling rate
K;

receiving, at the device, an input signal;
sampling, by an analog to digital converter (ADC) of the device, the input signal, wherein said sampling is performed in an
interleaved fashion on a per sample basis at the effective sampling rate K and wherein said sampling produces a plurality
N of parallel data streams, wherein the effective rate K is greater than the processing rate of the programmable hardware
element, wherein each of the N data streams has a rate K/N, wherein the rate K/N is not greater than the processing rate of
the programmable hardware element;

each of the N processing portions processing a respective one of the N parallel data streams in parallel, wherein said processing
produces a plurality of intermediate data streams; and

combining the plurality of intermediate data streams to produce output data.

US Pat. No. 9,479,200

ULTRA-BROADBAND PROGRAMMABLE HYBRID STEP ATTENUATOR

NATIONAL INSTRUMENTS CORP...

1. A programmable step attenuator, comprising:
a first diplexer, wherein the first diplexer comprises an input, a first output and a second output, wherein the first diplexer
is configured to:

receive a signal at the input;
selectively provide the signal to the first output if the signal is in a first portion of the frequency spectrum; and
selectively provide the signal to the second output if the signal is in a second portion of the frequency spectrum;
a plurality of pin-diode switches coupled to the first output of the first diplexer, wherein the plurality of pin-diode switches
operate as a first step attenuator for the signal if the signal is in the first portion of the frequency spectrum;

a plurality of radio frequency (RF) micro-electro-mechanical system (MEMS) switches, coupled to the second output of the first
diplexer, wherein the plurality of RF MEMS switches operate as a second step attenuator for the signal if the signal is in
the second portion of the frequency spectrum; and

a second diplexer comprising a first input, a second input, and an output, wherein the first input is coupled to the first
step attenuator, and wherein the second input is coupled to the second step attenuator, wherein the second diplexer is configured
to output a step attenuated signal from either the first or second portion of the frequency spectrum.

US Pat. No. 9,361,155

TIME CRITICAL TASKS SCHEDULING

National Instruments Corp...

1. A method for monitoring a time critical task, the method comprising:
determining a schedule for the time critical task based on received timing information, wherein the time critical task executes
program instructions via a thread on a core of a processing unit, wherein the time critical task is a function of the overall
thread deadline and a specified thread bandwidth, and wherein said determining comprises determining a wakeup time, a thread
cycle time, and an overall thread deadline;

executing, on the core of the processing unit, the time critical task in accordance with the schedule; and
suspending execution of the time critical task via assertion of a thread interrupt in response to a lateness timer expiring,
wherein the lateness timer is based on the wakeup time and the time critical task deadline.

US Pat. No. 9,201,849

IMPLEMENTING MODIFIED QR DECOMPOSITION IN HARDWARE

National Instruments Corp...

1. A circuit, configured to implement a QR decomposition of a matrix A into two matrices Q and R using a Modified Gram Schmidt
(MGS) process, wherein Q represents an orthonormal basis that spans a column space of A, and wherein R is a triangular matrix,
the circuit comprising:
an input;
a specified set of hardware components, coupled to the input, wherein the specified set of hardware components are dedicated
to computing matrix Q; and

an output;
wherein the circuit is configured to:
receive a first set of inputs at the input, wherein the first set of inputs includes the matrix A and a scaling factor ?;
compute matrix Q via the specified set of hardware components dedicated to computing matrix Q, based on the first set of inputs
using the MGS process;

scale the identity matrix by the scaling factor ?, thereby generating scaled identity matrix ?I;
receive a second set of inputs to the specified set of hardware components dedicated to computing matrix Q, wherein the second
set of inputs is different from the first set of inputs, wherein the second set of inputs comprises the scaled identity matrix;

compute scaled matrix ?R?1 via the specified set of hardware components dedicated to computing matrix Q, based on the second set of inputs using the
MGS process;

unscale the scaled matrix ?R?1, thereby computing matrix R?1, wherein matrix R?1 is the inverse of matrix R;

output the matrix Q and/or matrix R?1 via the output; and

use the matrix Q and/or matrix R?1 to perform signal estimation on a noisy channel.

US Pat. No. 9,609,653

SPECTRAL STITCHING METHOD TO INCREASE INSTANTANEOUS BANDWIDTH IN VECTOR SIGNAL GENERATORS

NATIONAL INSTRUMENTS CORP...

1. A method for processing a digital signal using a plurality of parallel processing paths, the method comprising:
providing to each of the parallel processing paths a respective component signal comprising a copy of at least a respective
frequency band of the digital signal, each respective frequency band having a respective center frequency and having a respective
region of overlap with at least one other respective frequency band, wherein the combination of the respective frequency bands
comprises an aggregate frequency band having an aggregate center frequency, wherein the respective center frequency of each
respective frequency band has a respective frequency offset from the aggregate center frequency, wherein at least a portion
of each of the parallel processing paths is phase-locked and time-synchronized with respect to the other parallel processing
paths;

at each of the parallel processing paths, processing the respective component signal, wherein said processing comprises:
frequency-shifting at least the respective frequency band of the respective component signal such that the respective center
frequency is shifted to baseband;

filtering at least the respective frequency band of the respective component signal, wherein said filtering of the respective
component signals is configured to cause a sum of the component signals to have a unity frequency response within each region
of overlap;

adjusting at least one of gain and phase of at least the respective frequency band of the respective component signal, wherein
said adjusting at least one of gain and phase of the respective component signals is configured to cause the sum of the component
signals to have a continuous frequency response over the aggregate frequency band; and

converting at least the respective frequency band of the respective component signal to a respective analog signal using a
respective vector signal generator associated with the respective parallel processing path; and

combining the respective analog signals to obtain a composite signal.

US Pat. No. 9,577,729

SYNCHRONIZATION OF LARGE ANTENNA COUNT SYSTEMS

NATIONAL INSTRUMENTS CORP...

1. A large antenna count (LAC) system, comprising:
a master device;
a plurality of slave radios communicatively coupled to the master device and to respective antennas in the large antenna count
system, wherein each slave radio includes a local clock;

a clock and trigger distribution system, coupled to the master device and the plurality of slave radios, wherein the clock
and trigger distribution system comprises a hierarchy of clock and trigger distribution modules;

wherein the plurality of slave radios are configured to establish and maintain a fixed relationship between a reference clock
and their respective local clocks, wherein the reference clock is distributed via the clock and trigger distribution system;

wherein the master device and the plurality of slave radios are configured to generate and align respective common periodic
time reference signals that have a lower frequency than the respective local clocks;

wherein the master device is configured to transmit, based on an edge of its common periodic time reference signal, a trigger
signal via the clock and trigger distribution system to the plurality of slave radios; and

wherein the plurality of slave radios are configured to perform an action based on the trigger signal at a subsequent edge
of their common periodic time reference signals.

US Pat. No. 9,413,107

SERIAL BUS RECEPTACLE WITH ADJUSTABLE EXTERIOR SOCKET CLAMPING

National Instruments Corp...

1. A system, comprising:
a housing, wherein the housing is configured to couple to a serial communication bus;
a serial bus receptacle comprised in the housing, wherein the serial bus receptacle is configured to communicatively couple
to the serial communication bus and comprises one or more internal retention springs situated inside the serial bus receptacle
that are configured to grip a male serial bus plug with a retention force when the male serial bus plug is inserted into the
serial bus receptacle;

a clamp, comprised in or coupled to the housing, wherein the clamp is external to the serial bus receptacle; and
a clamping adjustment mechanism configured to couple to the clamp and adjust the clamp to constrain the one or more internal
retention springs, thereby augmenting the retention force of the one or more internal retention springs;

wherein, when the male serial bus plug is inserted into the serial bus receptacle, the clamp is adjustable via a clamping
adjustment mechanism to augment the retention force of the one or more internal retention springs to secure the male serial
bus plug in the serial bus receptacle.

US Pat. No. 9,520,691

USE OF CRUSHABLE CONNECTOR INTERFACE

National Instruments Corp...

1. A method for forming a connection, comprising:
inserting an adapter into a receiving connector;
deforming through contact with the adapter a raised deformable annulus mounted on a flat annular surface of an annular end
piece extending radially inward from a first end of a wall region of the receiving connector by rotating the adapter within
the receiving connector, wherein the raised deformable annulus comprises a conductive material; and

conducting current across a physical contact connection between the flat annular surface and the adapter, wherein the physical
contact connection is generated by the deforming.

US Pat. No. 9,097,757

SWITCHING ELEMENT SYSTEM AND METHOD

National Instruments Corp...

1. A 2×2 switching element for routing analog signals, comprising:
a first relay comprising a first terminal, a second terminal and a third terminal, wherein the first relay is configured to
selectively operate between a first state configured to connect the first terminal of the first relay to the second terminal
of the first relay and a second state configured to connect the first terminal of the first relay to the third terminal of
the first relay; and

a second relay comprising a first terminal, a second terminal and a third terminal, wherein the second relay is configured
to selectively operate between a third state configured to connect the first terminal of the second relay to the second terminal
of the second relay and a fourth state configured to connect the first terminal of the second relay to the third terminal
of the second relay;

wherein the first relay is disposed on a first face of a printed circuit board (PCB) and the second relay is disposed on a
second face of the PCB that is opposite from the first face;

wherein the second terminals of the first and second relays are coupled to one another, and comprise or are coupled to an
input terminal of the 2×2 switching element configured to receive the analog signals;

wherein the third terminals of the first and second relays are coupled to one another, and comprise or are coupled to an output
terminal of the 2×2 switching element configured to output the analog signals; and

wherein the 2×2 switching element is selectively operable between:
a first switching state wherein the first relay is operated in the first state to connect the first terminal of the first
relay to the second terminal of the first relay and the second relay is operated in the fourth state to connect the first
terminal of the second relay to the third terminal of the second relay; and

a second switching state wherein the first relay is operated in the second state to connect the first terminal of the first
relay to the third terminal of the first relay and the second relay is operated in the third state to connect the first terminal
of the second relay to the second terminal of the second relay;

wherein the first terminal of the first relay is coupled to a first conductive path, the second terminal of the first and
second relays are coupled to a second conductive path, the third terminals of the first and second relays are coupled to a
third conductive path, and the first terminal of the second relay is coupled to a fourth conductive path, such that:

when the 2×2 switching element is operated in the first switching state, the 2×2 switching element is configured to route
a signal between the first and second conductive paths and to route a signal between the fourth and third conductive paths;
and

when the 2×2 switching element is operated in the second switching state, the 2×2 switching element is configured to route
a signal between the first and third conductive paths and to route a signal between the fourth and second conductive paths;

wherein the second terminals of the first and second relays are substantially vertically aligned with one another, and the
third terminals of the first and second relays are substantially vertically aligned with one another, thereby reducing size
of stubs in the first, second, third, and fourth conductive paths, resulting in effectively stubless conductive paths during
operation, thereby reducing interference and associated capacitive loads.

US Pat. No. 10,219,405

AIRFLOW STRAIGHTENER IN AN ELECTRONICS CHASSIS

NATIONAL INSTRUMENTS CORP...

1. A chassis, comprising:two or more electronic devices arranged along a first direction;
one or more fans, wherein the one or more fans are configured to provide a flow of air through the chassis;
at least one channel configured to direct the flow of air from the one or more fans to the two or more electronic devices, wherein the at least one channel has at least first and second regions, wherein the first region is larger in cross sectional area than the second region, and wherein the first region comprises a sloped region that compresses the flow of air into the second region;
at least one grating located in the first region of the at least one channel, wherein the at least one grating is comprised of a plurality of first dividers predominantly oriented along a second direction and arranged along the first direction, and a plurality of second dividers predominantly oriented along the first direction and arranged along the second direction, wherein the first and second dividers are oriented to direct the flow of air, wherein a spacing between adjacent ones of the first dividers is smaller than a spacing between adjacent ones of the second dividers, wherein a depth of the first dividers is oriented along a third direction that is perpendicular to each of the first and second directions, and wherein the third direction is intermediate between a slope of the sloped region and a slope of the second region; and
wherein the at least one grating is configured to increase uniformity of the flow of air through the at least one channel.

US Pat. No. 9,813,225

LOSSLESS TIME BASED DATA ACQUISITION AND CONTROL IN A DISTRIBUTED SYSTEM

National Instruments Corp...

1. A method for mapping of continuous time-based data acquisitions to isochronous data transfer channels of a network, the
method comprising:
initiating performance of each respective continuous time-based data acquisition at a start time of the continuous time-based
data acquisition, wherein the respective continuous time-based data acquisition is performed according to a first clock, wherein
the first clock is synchronized to a global clock of the network, wherein the start time of the respective continuous time-based
data acquisition is based on the global clock of the network, and wherein the data from the respective continuous time-based
data acquisition is stored in respective local buffers;

transfer the data from each respective local buffer to respective first buffers, wherein the transfer from the respective
local buffer to the respective first buffer is performed according to the first clock, and wherein each first buffer is associated
with a respective isochronous data transfer channel; and

communicating, from each first buffer, at the start time of the first buffer, respective data for the respective continuous
time-based data acquisition over the respective isochronous data transfer channel of the network at a transfer frequency of
the respective first buffer, thereby mapping the respective continuous time-based data acquisition to the respective isochronous
data transfer channel of the network;

wherein the start time of each first buffer is based on a buffer size of the first buffer, the start time of the respective
continuous time-based data acquisition, a data rate of the respective continuous time-based data acquisition, and a time necessary
to transfer data from the respective local buffer to the first buffer.

US Pat. No. 10,091,027

SYSTEMS AND METHODS FOR NETWORK INTEROPERABILITY

NATIONAL INSTRUMENTS CORP...

1. A system for interoperating between a first network and at least one second network, the system comprising:a first port coupled to the first network, wherein the first network is configured to operate according to a first real time network protocol;
at least one second port coupled the at least one second network, wherein the at least one second network is configured to operate according to a second real time network protocol, wherein the first real time network protocol is not compatible with the second real time network protocol; and
switch circuitry coupled to the first port and the at least one second port, wherein the switch circuitry includes a mapping specifying data routing between ports, wherein the switch circuitry is configured to:
route packets between the first network and the at least one second network based on the mapping, wherein the switch circuitry is configured to maintain real time behavior between the first network and the at least one second network, wherein to route the packets, the switch circuitry is further configured to:
insert routing information in packets routed to the first network;
route, based on the mapping, packets to distinct queues for the first network and the at least one second network for processing by an application executing on at least one device, wherein the distinct queues comprise first queue pairs associated with traffic on the first network and second queue pairs associated with traffic on the at least one second network;
time stamp ingress and egress of packets to/from the first queue pairs and the second queue pairs; and
remove routing information from packets routed to the at least one second network.

US Pat. No. 9,753,881

FPGA BASED ATCA (ADVANCED TELECOMMUNICATIONS COMPUTING ARCHITECTURE) PLATFORM

NATIONAL INSTRUMENTS CORP...

1. A computing system comprising a first board conforming to a form factor of the Advanced Telecommunications Computing Architecture
(ATCA) standard, the first board comprising:
a first local field programmable gate array (FPGA) based computing node;
a second local FPGA based computing node, wherein the first and second local FPGA based computing nodes are configured to
perform direct point-to-point communications with one another via a dedicated link, wherein the dedicated link is shared exclusively
between the first FPGA based computing node and the second FPGA based computing node; and

an optical communication link configured for providing selectable point-to-point communication between the first local FPGA
based node and a remote FPGA based node on a second board of another, different computing system, wherein the second board
also conforms to the form factor of the ATCA standard, wherein the optical communications link includes a first optical transceiver
directly coupled to the first local FPGA based node, wherein no other FPGA based node on the first board is coupled to the
first optical transceiver.

US Pat. No. 9,755,496

SOLID STATE WIDEBAND HIGH IMPEDANCE VOLTAGE CONVERTER

NATIONAL INSTRUMENTS CORP...

1. An input circuit for establishing a switchable voltage converter, the input circuit comprising:
two or more input terminals, each input terminal of the two or more input terminals configured to couple to a respective input
network, each input network comprising a respective input pathway;

two or more feedback terminals, each feedback terminal of the two or more feedback terminals configured to couple to a respective
feedback network, each feedback network comprising a respective feedback pathway;

a switching network comprising:
a first set of low-voltage switches configured to selectively couple the respective input pathway of a selected respective
input network across an input of the voltage converter and a first node; and

a second set of low-voltage switches configured to selectively couple the respective feedback pathway of a selected respective
feedback network across a second node and an output of the voltage converter, wherein the selected respective input network
and the selected respective feedback network together define an input signal value range of the voltage converter;

an output configured to provide an output signal having a value within an output signal value range according to the defined
input signal value range; and

a control circuit configured to controllably adjust an AC gain of the voltage converter to match a DC gain of the voltage
converter.

US Pat. No. 9,654,188

SCALABLE MASSIVE MIMO

NATIONAL INSTRUMENTS CORP...

1. An apparatus, comprising:
a plurality of antennas;
a plurality of processing elements coupled to the plurality of antennas and configured to perform processing for received
wireless communications via the plurality of antennas;

one or more interconnects configured to couple ones of the plurality of processing elements with other ones of the plurality
of processing elements;

wherein the apparatus is configured to combine signals received by multiple antennas of the plurality of antennas;
wherein, for at least a subset of the processing elements, each processing element is configured to operate on a different
portion of the combined signal in parallel, wherein each portion includes signals from multiple antennas of the plurality
of antennas; and

wherein the apparatus is configured to operate in:
a first mode in which a first number of the plurality of processing elements process received wireless communications from
a first number of the plurality of antennas; and

a second mode in which a second number of the plurality of processing elements that is smaller than the first number of processing
elements process received wireless communications from a second number of the plurality of antennas that is smaller than the
first number of antennas.

US Pat. No. 9,652,370

ADDRESS RANGE DECOMPOSITION

NATIONAL INSTRUMENTS CORP...

1. A smart bridge, configured to be interposed between a bus host device and a plurality of devices that require respective
amounts of memory resources of the bus host device, wherein the smart bridge comprises:
a functional unit;
memory, coupled to the functional unit; and
at least one switch, coupled to the functional unit, wherein the at least one switch is configured to route data between the
bus host device and the plurality of devices using a routing table;

wherein the memory stores program instructions executable by the functional unit to:
store a forwarding address range comprising a bridge representation of a plurality of hardware memory resources required by
a plurality of devices, wherein the forwarding address range is an integer multiple of a first specified minimum size and
is aligned with the first specified minimum size; and

convert the bridge representation of the plurality of hardware memory resources to an endpoint representation comprising a
plurality of virtual memory resources based on a starting address of the forwarding address range, wherein each virtual memory
resource comprises a respective sub-address range with a size that is a power of 2 multiple of a second specified minimum
size and is aligned with its size, wherein the second specified minimum size is less than the first specified minimum size;
and

wherein the endpoint representation is usable by the at least one switch or the bus host device to allocate the virtual memory
resources to the plurality of devices; and

wherein the bridge representation and the forwarding address range are binary numbers, and wherein to convert the bridge representation
of the plurality of hardware memory resources to the endpoint representation, the program instructions are executable to:

while there are virtual memory resources to allocate:
determine if a current base address of the forwarding address range is aligned;
allocate a next virtual memory resource to the forwarding address range at the current base address, where the size of the
sub-address range of the virtual memory resource is based on the least significant 1 bit of the current base address, in response
to determining that the starting address of the forwarding address range is not aligned; and

allocate the next virtual memory resource to the forwarding address range at the current base address, where the size of the
sub-address range of the virtual memory resource is based on the most significant 1 bit of the current forwarding address
size, in response to determining that the starting address of the forwarding address range is aligned.

US Pat. No. 9,618,551

CALIBRATION OF STEP ATTENUATOR

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a processor to implement:
receiving N attenuation measurements of a step attenuator, wherein the step attenuator comprises M series-connected attenuation
sections, wherein each attenuation section is configured to be switchable to provide a respective level of attenuation, wherein
N is greater than M, and wherein the step attenuator is modeled via M+1 coefficients, comprising a coefficient for a no-attenuation
state and respective coefficients for the attenuation sections; and

calibrating the step attenuator, wherein calibrating the step attenuator comprises determining, via least squares estimation
using the N attenuation measurements, values of the coefficients.

US Pat. No. 9,582,342

API CONSTRAINT LANGUAGE FOR A COMMUNICATION DEVICE

NATIONAL INSTRUMENTS CORP...

1. A method for communicating within a communication stack comprising layers, the method comprising:
receiving, by a first layer of the communication stack executing in a first communication device, one or more application
programming interface (API) messages from a second layer of the communication stack executing in the first communication device;

receiving, by the first layer, one or more resource constraints with the one or more API messages, wherein said receiving
the one or more resource constraints comprises receiving an API Constraint Vector, wherein the API Constraint Vector (ACV)
is a data structure comprising the one or more resource constraints, wherein the ACV comprises a plurality of fields which
are predefined to store information regarding respective ones of the resource constraints; and

executing, by the first layer, one or more communication functions based on the one or more API messages and subject to the
one or more resource constraints, wherein the one or more resource constraints affect usage of one or more hardware and/or
software resources of the first communication device during execution of the one or more communication functions.

US Pat. No. 9,477,624

CONTROLLING BUS ACCESS IN A REAL-TIME COMPUTER SYSTEM

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer-readable memory medium storing program instructions executable by one or more processors to:
execute, in response to an application being launched, one or more software tasks scheduled according to a static time schedule
defined for the application, wherein the static time schedule defines specific execution start times for the one or more software
tasks, wherein one or more unscheduled devices attempt to access a bus at times not defined by the static time schedule, wherein
the static time schedule defines specific times when bus access for the one or more unscheduled devices is allowed and specific
times when bus access for the one or more unscheduled devices is not allowed; and

allowing and not allowing bus access for the one or more unscheduled devices at the specific times defined by the static time
schedule.

US Pat. No. 9,436,438

GRAPHICAL SPECIFICATION AND CONSTRAINT LANGUAGE FOR DEVELOPING PROGRAMS FOR HARDWARE IMPLEMENTATION AND USE

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer-accessible memory medium that stores program instructions executable by a computer system to
perform:
providing a graphical program development environment comprising a graphical specification and constraint language that allows
specification of a model of computation and explicit declaration of constraints; and

creating a graphical program in the graphical specification and constraint language in response to user input, wherein the
graphical program comprises:

a specified model of computation;
a plurality of interconnected functional blocks that visually indicate functionality of the graphical program in accordance
with the specified model of computation; and

graphically indicated specifications or constraints for at least one of the functional blocks in the graphical program;
wherein the specifications or constraints comprise:
initiation interval (II), comprising a minimum number of cycles between firings of the at least one functional block;
input pattern (IP), comprising a sequence of Boolean values of length at most II, wherein the sequence of Boolean values aligns
with the beginning of firing of the at least one functional block, wherein each true value in the sequence denotes consumption
of a token at an input terminal of the at least one functional block; and

output pattern (OP), comprising a sequence of Boolean values of length at most II, wherein the sequence of Boolean values
aligns with the end of firing of the at least one functional block, wherein each true value in the sequence denotes production
of a token at an output terminal of the at least one functional block; and

automatically generating an output program based on the graphical program, wherein the output program implements the functionality
of the graphical program in accordance with the specified model of computation, and further implements the specifications
or constraints;

wherein the output program is useable to configure a programmable hardware element to perform the functionality subject to
the specifications or constraints.

US Pat. No. 9,921,815

PROGRAM VARIABLE CONVERGENCE ANALYSIS

National Instruments Corp...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a processor to implement:
determining, based on dependencies of one or more variables in a first program, one or more state variables of the first program;
creating, based on the one or more state variables and dependencies of the one or more state variables, a second program corresponding
to the first program;

executing the second program a plurality of times, comprising:
for each execution:
recording values of the one or more state variables;
determining an execution count;
comparing the values to corresponding values from previous executions of the second program; and
terminating said executing in response to determining that the values match corresponding values from at least one previous
execution of the second program;

determining, based on the execution count, a convergence property for the first program that indicates a number of executions
of the first program required to generate all possible values of the one or more variables; and

storing the convergence property, wherein the convergence property is useable to optimize the first program;
wherein said determining one or more state variables, said creating, and said executing are performed as part of compiling
the first program.

US Pat. No. 9,797,936

COUNTER ENHANCEMENTS FOR IMPROVED PERFORMANCE AND EASE-OF-USE

NATIONAL INSTRUMENTS CORP...

1. A counter comprising:
a first input configured to receive a divisor value associated with a first method of operation;
a second input configured to receive a measurement time value associated with a second method of operation; and
counter circuitry configured to:
perform a first measurement on an input signal according to the first method of operation using at least the divisor value;
and

perform a second measurement on the input signal according to the second method of operation using at least the measurement
time value, wherein performance of the first measurement at least partially overlaps with performance of the second measurement;
and

provide a measurement value obtained from whichever respective measurement of the first measurement and the second measurement
completes first.

US Pat. No. 9,703,740

OPAQUE BRIDGE FOR PERIPHERAL COMPONENT INTERCONNECT EXPRESS BUS SYSTEMS

NATIONAL INSTRUMENTS CORP...

14. A method for configuring and operating first devices comprised in a switch fabric subsystem coupled to a host system,
the method comprising:
preallocating specified one or more memory ranges to a bus extender appearing to the host system as a bridge to a bus of unknown
type;

configuring memory requirements of the first devices, said configuring comprising:
using the preallocated specified one or more memory ranges; and
configuring the memory requirements without recognizing that the memory requirements are intended for devices operating according
to a first bus protocol associated with the switch fabric subsystem.

US Pat. No. 9,654,416

SWITCH FOR SCHEDULED TIME-SENSITIVE DATA EGRESS

NATIONAL INSTRUMENTS CORP...

1. A method for scheduled data egress, comprising:
configuring a time-sensitive (TS) network switch to implement:
receiving one or more TS packets asynchronously from a network node via a first port, wherein each TS packet has a destination
address and a type that specifies a respective egress period, wherein each egress period specifies a respective time window
for egressing TS packets to network nodes based on the type of the TS packets;

determining a second port for egressing at least one of the one or more TS packets based on the destination address of the
at least one TS packet;

determining an egress period for egressing the at least one TS packet based on the type of the at least one TS packet;
determining that the at least one TS packet cannot currently be egressed from the second port;
queuing the at least one TS packet in a first queue based on the respective TS packet type and destination address in response
to determining that the at least one TS packet cannot currently be egressed, wherein the first queue is associated with the
second port; and

egressing the at least one TS packet in the respective time window from the second port.

US Pat. No. 9,626,233

GRAPHICAL PROGRAMMING SYSTEM FOR DATA SHARING BETWEEN PROGRAMS VIA A MEMORY BUFFER

NATIONAL INSTRUMENTS CORP...

1. A method comprising:
executing a graphical program, a first program, and a second program on a computer system, wherein the graphical program includes
a plurality of nodes that visually indicate functionality of the graphical program, wherein the graphical program executes
within a graphical program execution environment, wherein the first program and the second program execute externally from
the graphical program and the graphical program execution environment, wherein the graphical program execution environment
is one or more programs, including a graphical program execution engine, and wherein the graphical program, the first program,
and the second program are distinct and separate programs;

wherein the graphical program executes via the graphical program execution engine to receive a reference to a block of memory
allocated by the first program externally from the graphical program and to pass the reference to the second program;

wherein the second program executes to:
access the block of memory; and
after accessing the block of memory, asynchronously notify the graphical program execution environment that the second program
is done accessing the block of memory;

wherein the graphical program execution environment executes to:
notify the first program that the block of memory is no longer in use in response to the second program notifying the graphical
program execution environment.

US Pat. No. 9,611,797

DIRECT INJECTION FLEXIBLE MULTIPLEXING SCHEME

NATIONAL INSTRUMENTS CORP...

1. An engine control system comprising:
a plurality (N) of pins, each pin of the N pins configured to couple to an injector; and
a control unit configured to:
switch between a plurality (P) of multiplexing configurations, wherein each multiplexing configuration of the P multiplexing
configurations comprises a different combination of specified individual injectors of a plurality (M) of injectors coupled
across corresponding pairs of pins of the N pins, and wherein when the control unit switches to a respective multiplexing
configuration of the P multiplexing configurations, the respective multiplexing configuration becomes an active multiplexing
configuration; and

operate the specified individual injectors through the corresponding pairs of pins in the active multiplexing configuration;
wherein N is an integer greater than 2, and M is an integer greater than 1.

US Pat. No. 9,519,491

TIME MONITORING IN A PROCESSING ELEMENT AND USE

National Instruments Corp...

1. A system comprising:
a processing element, comprising:
a clock;
a thread suspend/resume logic block, configured to suspend execution of a thread without interrupting the processing element
and in response to a received suspend thread instruction;

a local reference clock, coupled to the processing element and to a peripheral device, wherein the peripheral device is configured
to provide a global time to the processing element; and

a time monitor circuit (TMC), wherein the TMC is configured to:
receive an indication of a wakeup time;
discipline the clock via adjustment of the global time based on a difference between a local reference time and a subsequent
local reference time, thereby compensating for latency due to the provision of the global time by the software, wherein the
subsequent local reference time is retrieved from the local reference clock, wherein the global time is provided by software,
and wherein to provide the global time, the software is executable to:

retrieve the local reference time from the local reference clock that corresponds to the global time; and
provide the global time and the local reference time to the processing element;
monitor time via the clock until the wakeup time obtains; and
invoke the thread suspend/resume logic block to resume execution of the thread in response to the wakeup time obtaining.

US Pat. No. 9,304,810

TIME MONITORING IN A PROCESSING ELEMENT AND USE

National Instruments Corp...

1. A system comprising:
a processing element, comprising:
a clock;
a thread suspend/resume logic block, configured to suspend execution of a thread in response to a received suspend thread
instruction; and

a time monitor circuit (TMC); and
a local reference clock, coupled to the processing element and to a peripheral device;
wherein the TMC is configured to:
receive an indication of a wakeup time;
monitor time via the clock until the wakeup time obtains; and
invoke the thread suspend/resume logic block to resume execution of the thread in response to the wakeup time obtaining;
wherein the TMC is further configured to discipline the clock via an external time source, wherein to discipline the clock
via an external time source, the TMC is configured to discipline the clock using a global time provided by software, wherein
the peripheral device is configured to provide the global time to the processing element;

wherein to provide the global time, the software is executable to retrieve a local reference time from the local reference
clock that corresponds to the global time, and provide the global time and the local reference time to the processing element;
and

wherein to discipline the clock, the TMC is configured to retrieve a subsequent local reference time from the local reference
clock, and adjust the global time based on a difference between the subsequent local reference time and the local reference
time, thereby compensating for latency due to the provision of the global time by the software.

US Pat. No. 10,019,339

SEQUENTIALLY CONSTRUCTIVE MODEL OF COMPUTATION

NATIONAL INSTRUMENTS CORP...

1. A computer-implemented method, comprising:utilizing a computing system to perform:
receiving a program, wherein the program specifies a plurality of operations using a variable within a logical tick such that the variable has multiple values within the logical tick, wherein said having multiple values comprises transitioning from an initial value to a second value within the logical tick, wherein all computations within the logical tick are interpreted as being instantaneous, and wherein logical ticks specify the resolution of functional synchronization for execution of the program;
statically analyzing the program according to a specified model of computation that specifies synchronous program execution based on logical ticks, wherein said statically analyzing the program includes:
determining that the program has deterministic semantics, wherein the deterministic semantics specify deterministic results for each logical tick during execution of the program, including specifying deterministic results of the plurality of operations performed within the logical tick, wherein the deterministic results comprise a final result of the variable within the logical tick and observable side effects of the multiple values of the variable during the logical tick; and
validating the program in accordance with the specified model of computation in response to said determining; and
using a compiler or interpreter, transforming the program to produce deterministically executable output code and executing the deterministically executable output code.

US Pat. No. 9,996,407

METHODS FOR DATA ACQUISITION SYSTEMS IN REAL TIME APPLICATIONS

National Instruments Corp...

1. A peripheral device comprising:a first register; a second register, and a third register;
control circuitry configured to:
generate an output signal, alternating between generating the output signal at least according to contents of the first register and generating the output signal at least according to contents of the second register;
copy contents of the third register into the first register when generating the output signal at least according to the contents of the second register;
copy the contents of the third register into the second register when generating the output signal at least according to the contents of the first register; and
update the contents of the third register subsequent to having copied the contents of the third register into either the first register or the second register; and
error detection circuitry configured to perform data timing error detection, wherein to perform the data timing error detection, the error detection circuitry is configured to:
receive incoming data from a host system;
detect a present first error if expected first data of the incoming data does not reach the third register in time to be available for a present sample clock period, and report the present first error to the host system upon detecting the present first error;
detect a present second error if more than the expected first data reaches the third register and is available for the present sample clock period, and report the present second error to the host system upon detecting the present second error; and
report to the host system whether expected second data of the incoming data has been received correctly for a most recent previous sample clock period.

US Pat. No. 9,917,755

PROVIDING FAST RADIO-FREQUENCY DELAY MEASUREMENTS FOR ENVELOPE TRACKING

National Instruments Corp...

1. A method for determining delay in a radio frequency (RF) device, wherein the RF device comprises a power amplifier and
an envelope tracker, the method comprising:
transmitting a first stimuli signal to the power amplifier;
transmitting a second stimuli signal to the envelope tracker;
receiving, from the power amplifier, an output signal based on each of the first stimuli signal and the second stimuli signal,
cross-correlating a reference signal with the output signal to determine a first delay offset;
determining a second delay offset based on an amplitude distortion of the output signal; and
determining a relative delay between the first and second stimuli signals based on a difference between the first and second
delay offsets.

US Pat. No. 9,852,036

CONFIGURABLE INPUT/OUTPUT SUB-CHANNELS FOR OPTIMIZED DIAGNOSTICS

NATIONAL INSTRUMENTS CORP...

1. A configurable digital input/output channel comprising:
an input terminal;
an output terminal;
a digital input sub-channel configured to selectively couple to the input terminal and further configured to perform first
diagnostics; and

a digital output sub-channel coupled to the output terminal and configured to perform second diagnostics;
wherein the digital input sub-channel and the digital output sub-channel are configured to be selectively coupled together,
wherein when coupled together, the digital input sub-channel and the digital output sub-channel interoperate as an enhanced
digital channel configured to perform advanced diagnostics in addition to the first diagnostics and the second diagnostics.

US Pat. No. 9,785,415

REMOTE INTERFACE TO LOGICAL INSTRUMENTS

NATIONAL INSTRUMENTS CORP...

1. A method for controlling a custom modular measurement system, comprising:
receiving, by an editor, user input specifying one or more system definitions, wherein each system definition maps message
based commands, parameters, variables and/or metadata accordant with a control protocol for standalone instruments to functions
and data in a programming language;

generating, by the editor, the one or more system definitions based on the user input, wherein each system definition is used
by a client application to interface with a custom modular measurement system that includes multiple logical instruments via
the message based commands, parameters, variables, and/or metadata, each logical instrument providing custom measurement or
analysis functionality for at least one physical measurement device;

deploying at least one of the system definitions onto the custom modular measurement system;
accepting, by a run-time engine of the custom modular measurement system, a message based command from the client application;
calling, by the run-time engine, a function that corresponds to the message based command, based on the at least one of the
one or more system definitions; and

performing, by the run-time engine, said accepting and said calling a plurality of times, wherein at least one called function
invokes operation of at least one of the logical instruments, wherein each of the multiple logical instruments is configured
to lock the measurement device during an exclusive phase of operation of the measurement device, the exclusive phase including
an acquire portion of a measure phase, wherein during the measure phase, data are acquired via the measurement device.

US Pat. No. 9,784,279

ZERO RIPPLE FAN NOISE SUPPRESSION

NATIONAL INSTRUMENTS CORP...

1. A system, comprising:
at least one fan, wherein the at least one fan comprises a power input for receiving power from a power source; and
a fan noise suppression circuit coupled between the power source and the power input of the at least one fan, wherein the
fan noise suppression circuit is configured to provide power to the at least one fan from at least the power source, wherein
in providing power to the at least one fan, the fan noise suppression circuit is configured to:

provide an inductance having a first inductance value within a first range during an output voltage transient and having a
second inductance value within a second range during a steady state output voltage, wherein values within the first range
are smaller than values within the second range;

draw constant current from the power source; and
provide constant average power to the at least one fan.

US Pat. No. 9,690,550

PROGRAM OPTIMIZATION VIA COMPILE TIME EXECUTION

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer-accessible memory medium that stores program instructions executable by a computer system to:
receive an input program representative of a design comprising one or more functions;
compile the received input program to produce an output;
during the compile of the received input program, after the compile starts, and before the compile completes:
generate information about one or more elements of the design by executing portions of the received input program, wherein
the portions are less than the entire input program, wherein at least one portion of the received input program are array
indices in the input program, wherein the information comprises information about value traces of at least one of the one
or more variables in the input program, and wherein said executing comprises:

determining and executing compiled executable instructions implementing each of the portions of the received program;
analyze the information; and
optimize the output by applying one or more transformations to the compile, including applying one or more transformations
to arrays or array operations in the input program, responsive to analyzing the information.

US Pat. No. 9,621,387

I/Q MODULATOR AND DEMODULATOR WITH WIDE INSTANTANEOUS BANDWIDTH AND HIGH LOCAL-OSCILLATOR-PORT-TO-RADIO-FREQUENCY-PORT ISOLATION

NATIONAL INSTRUMENTS CORP...

1. A modulator/demodulator comprising:
an RF port;
a first circuit comprising a first port coupled to the RF port, and further comprising a second port and a third port, wherein
the first circuit is configured to:

generate a pair of out-of-phase input signals at the second port and third port, responsive to the first port being excited
by a first signal received at the RF port; and

generate a summed output signal at the first port, responsive to the second port and the third port being excited by a pair
of out-of-phase output signals;

a first mixer coupled to the second port, and configured to:
downconvert a first out-of-phase input signal of the pair of out-of-phase input signals to a first pair of incoming baseband
signals; and

upconvert a first pair of outgoing baseband signals to a first out-of-phase output signal of the pair of out-of-phase output
signals; and

a second mixer coupled to the third port, and configured to:
downconvert a second out-of-phase input signal of the pair of out-of-phase input signals to a second pair of incoming baseband
signals; and

upconvert a second pair of outgoing baseband signals to a second out-of-phase output signal of the pair of out-of-phase output
signals.

US Pat. No. 9,558,099

STAGED PROGRAM COMPILATION WITH AUTOMATED TIMING CLOSURE

National Instruments Corp...

1. A computer-implemented method, comprising:
receiving a program representative of a hardware design of one or more functions;
producing a hardware representation of the hardware design by running the received program through a compilation process that
comprises multiple stages, wherein the hardware representation of the hardware design is subject to one or more constraints,
wherein said producing the hardware representation of the hardware design comprises:

collecting information relating to characteristics of the hardware design throughout the compilation process, wherein the
characteristics of the hardware design include timing path information of the hardware design, and wherein the hardware representation
of the hardware design does not meet at least one of the one or more constraints; and

performing, until the one or more constraints are met:
automatically adjusting one or more stages of the compilation process prior to completion of the compilation process, based
on the collected information via a programming interface, including automatically adjusting timing path implementation decisions,
thereby adjusting the compilation process, including:

producing a timing report resulting from the compilation process, wherein the timing report comprises one or more failed timing
constraint paths; and

adding one or more registers along at least one of the one or more failed timing constraint paths in response to receiving
input instructions via the programming interface, in order to improve the timing paths; and

performing said producing via the adjusted compilation process;
wherein said automatically adjusting one or more stages of the compilation process comprises:
comparing the timing report with a prior timing report obtained from a previous compilation process performed on the received
program, said comparing comprising:

parsing the one or more failed timing constraint paths in the timing report; and
comparing timing delays comprised in the failed timing constraint paths to timing delays comprised in corresponding timing
constraint paths in the prior timing report; and

adjusting timing paths in the hardware design according to results of the comparison of the timing report with the prior timing
report, wherein said adjusting comprises:

finding a longest preexisting component delay from the failed timing constraint paths; and
adding a register in a timing path corresponding to the found delay.

US Pat. No. 10,120,405

SINGLE-JUNCTION VOLTAGE REFERENCE

NATIONAL INSTRUMENTS CORP...

1. A method for implementing a temperature compensated reference voltage using a single semiconductor junction, the method comprising:obtaining a set of voltage values, comprising obtaining one or more first voltage values and one or more second voltage values, wherein each of the one or more first voltage values is representative of a first voltage developed across a single semiconductor junction (SSJ), and each of the one or more second voltage values is representative of a second voltage developed across the SSJ, said obtaining comprising alternately applying:
a first current to the SSJ to develop the first voltage; and
a second current to the SSJ to develop the second voltage;
varying a temperature of the SSJ over a temperature range during said obtaining the set of voltage values; and
determining one or more parameters based on the one or more first voltage values and the one or more second voltage values, wherein the one or more parameters are parameters of a function of the first voltage and the second voltage, wherein the function yields a temperature compensated voltage value of a reference voltage derived from the SSJ.

US Pat. No. 10,103,928

NYQUIST AND SQUARE ROOT NYQUIST FILTERS FOR PULSE SHAPING IN WIRELESS COMMUNICATIONS

National Instruments Corp...

1. An apparatus to receive wireless communications, comprising:an antenna;
receive circuitry coupled to receive input signals from the antenna, the input signals having a pulse shaping modulation; and
a matched filter within the receive circuitry coupled to receive the input signals and to remove the pulse shaping modulation;
wherein the matched filter is a generalized Nyquist filter that has a frequency response (H(f)) represented by frequency response equations:

where f represents frequency, An represent coefficients, T represents a symbol period, n represents an integer, and ? represents a roll-off factor.

US Pat. No. 9,965,371

AUTOMATICALLY DETERMINING AND INDICATING SYSTEM POSITIONS OF DEVICES IN A HIERARCHICAL BUS NETWORKED SYSTEM

NATIONAL INSTRUMENTS CORP...

18. A system comprising:at least one processor; and
a memory coupled to the at least one processor, wherein the memory has stored thereon instructions executable by the at least one processor to:
store characteristic information regarding each of a plurality of devices connected to the system in a system hierarchy of a bus networked system, wherein the characteristic information for each device comprises:
a device hierarchy associated with the device, wherein the device hierarchy identifies a respective set of hardware nodes comprised in the device,
wherein the respective set of hardware nodes comprises at least one port,
wherein the at least one port connects to a connected port of the computer system or of a second device; and
one or more visual attributes of the device;
automatically determine a respective system position of a subset of the plurality of devices based on the respective device hierarchy of the subset of the plurality of devices;
automatically determine a respective point of reference of at least one device of the plurality of devices, wherein the respective point of reference is one of the plurality of devices and is determined based on the characteristic information of one or more of the plurality of devices, wherein for at least a subset of the at least one device, the respective point of reference is another one of the plurality of devices;
generate, for the at least one device of the plurality of devices, information that indicates the respective system position of the at least one device relative to the respective point of reference of the at least one device; and
output the information that indicates the respective system position of the at least one device, wherein the information is useable to visually identify the at least one device in the bus networked system.

US Pat. No. 9,918,316

SPECTRAL STITCHING METHOD TO INCREASE INSTANTANEOUS BANDWIDTH IN VECTOR SIGNAL GENERATORS

National Instruments Corp...

1. A method for processing a digital signal, the method comprising:
frequency-shifting each of a plurality of component signals, each component signal comprising a respective frequency band
of interest of the digital signal, each frequency band of interest having a region of overlap with a frequency band of interest
of at least one other component signal, such that a respective center frequency of each frequency band of interest is shifted
to baseband;

filtering the component signals;
adjusting at least one of gain and phase of the component signals;
converting at least the frequency bands of interest of the component signals to respective analog signals using respective
vector signal generators, wherein the vector signal generators are phase-locked and time-synchronized; and

combining the respective analog signals to obtain a composite signal, wherein said filtering the component signals is configured
to cause the composite signal to have a unity frequency response within each region of overlap, and wherein said adjusting
at least one of gain and phase of the component signals is configured to cause the composite signal to have a continuous frequency
response over an aggregate frequency band.

US Pat. No. 9,880,030

EXTENDING PROGRAMMABLE MEASUREMENT DEVICE FUNCTIONALITY

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a processor to perform:
receiving first user input specifying custom IP (intellectual property) for a programmable measurement device, wherein the
programmable measurement device includes:

a programmable hardware element; and
standard driver IP provided by a vendor of the programmable measurement device, wherein the standard driver IP is configured
to operate in conjunction with a standard device driver for the programmable measurement device that is provided by a vendor
of the standard device driver and is resident on a host device configured to couple to the programmable measurement device
for operation of the programmable measurement device; and

generating the custom IP based on the first user input, wherein the custom IP is deployable to the programmable measurement
device;

wherein once the custom IP is deployed to the programmable measurement device, during operation of the host device and the
programmable measurement device the custom IP communicates directly with the standard driver IP, and provides custom functionality
of the programmable measurement device while preserving functionality of the standard driver IP on the programmable measurement
device and the standard device driver.

US Pat. No. 9,626,415

DATA REDUCTION WITH SPECIFIED CONSTRAINTS

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer accessible memory medium that stores program instructions executable to perform:
receiving a request for data from a data set, wherein the data set comprises time-stamped historical data comprising a plurality
of reduced data sets, each reduced data set having a respective resolution, and wherein the request specifies a time frame
and further specifies a return data constraint that limits a return data size;

determining a first reduced data set of the plurality of reduced data sets based on the specified time frame, wherein the
first reduced data set is specified or organized in intervals along an independent axis;

retrieving first data from the first reduced data set, wherein the first data corresponds to the specified time frame, wherein
said retrieving first data from the first reduced data set comprises:

retrieving initial data from the first reduced data set, wherein the initial data has an initial size at an initial resolution,
and wherein the initial size is greater than the specified return data constraint; and

further reducing the initial data to an adjusted size that is of the same order as the specified return data constraint, thereby
generating the first data, wherein the adjusted size does not exceed 2*n+2 of the specified return data constraint, where
n is the specified return data constraint;

for each interval that includes one or more data points, determining one or more characteristic data points for the interval
that characterize the data for that interval, and wherein the one or more characteristic data points are associated with a
respective single value on the independent axis for the interval; and

displaying the first data on a display device, including visually representing the character of the data based on the one
or more characteristic data points for each interval that includes one or more data points.

US Pat. No. 9,990,250

SINGLE-IC LDPC ENCODING AND DECODING IMPLEMENTATIONS

NATIONAL INSTRUMENTS CORP...

1. An apparatus, comprising:decode circuitry;
message circuitry configured to receive or generate message data for a message to be encoded;
encode circuitry configured to perform low density parity check (LDPC) encoding on the message data to generate an encoded message;
noise circuitry configured to:
apply artificial noise to the encoded message to generate a noisy encoded message, wherein the artificial noise is generated based on one or more input noise parameters that specify intensity of the artificial noise, signal to noise ratio for the noisy encoded message, and a type of noise, and wherein the artificial noise is applied prior to transmitting any data associated with the encoded message to the decode circuitry; and
transmit the noisy encoded message to the decode circuitry;
wherein the decode circuitry is configured to perform LDPC decoding on the noisy encoded message;
error check circuitry configured to generate error data based on a comparison of the message data and the decoded message from the decode circuitry;
wherein the message circuitry, the encode circuitry, the noise circuitry, and the decode circuitry are included on a single integrated circuit and wherein the noisy encoded message is transmitted internally via the integrated circuit.

US Pat. No. 9,985,701

SIGNALING AND FRAME STRUCTURE FOR MASSIVE MIMO CELLULAR TELECOMMUNICATION SYSTEMS

NATIONAL INSTRUMENTS CORP...

1. An apparatus, comprising:a plurality of antennas; and
a plurality of radios configured to:
receive an uplink pilot symbol from a mobile devices over a channel;
receive uplink data from the mobile device over the channel, wherein the uplink data is includes in one more frequency division multiplexing (FDM) symbols at a symbol rate;
wherein the apparatus is configured to:
determine channel information based on the uplink pilot symbol by using a first plurality of processing elements each configured to operate on a different frequency portion of the uplink pilot symbol in parallel;
precode downlink data based on the channel information using a second plurality of processing elements each configured to precode a different frequency portion of the downlink data in parallel, and combine outputs of the second plurality of processing elements to generate precoded downlink data; and
transmit, via one or more of the plurality of antennas, the precoded downlink data to the mobile device;
wherein a transition interval between receiving the uplink pilot symbol and beginning to transmit the precoded downlink data corresponds to less than five FDM symbols at the symbol rate; and
wherein the apparatus is configured to receive the uplink pilot symbol and transmit the precoded downlink data within the same sub-frame.

US Pat. No. 9,898,267

CORRELATION ANALYSIS OF PROGRAM STRUCTURES

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a processor to implement:
storing a program, wherein the program comprises a plurality of program structures and one or more data objects distinct from
the plurality of program structures, and wherein each of the one or more data objects is shared by a respective at least two
of the plurality of program structures;

for each program structure of the plurality of program structures, analyzing decomposition effects on each of the one or more
data objects shared by the program structure resulting from each of a respective one or more optimizing transforms applied
to the program structure, wherein said analyzing is performed in context of the program structure and independent of other
program structures in the program, wherein the decomposition effects comprise results of how the one or more data objects
would be modified as a consequence of the respective one or more optimizing transforms being applied to the program structure;
and

determining, based on said analyzing, one or more groups of correlated structures, each group comprising:
two or more program structures that share at least one data object; and
at least one optimizing transform that is compatible with respect to the two or more program structures and the shared at
least one data object, wherein the at least one optimizing transform can operate on the two or more program structures without
causing conflicting modifications of the shared at least one data object; and

transforming the two or more program structures to meet a specified optimization objective, using the at least one optimizing
transform for at least one group of correlated structures.

US Pat. No. 9,871,649

REAL TIME SUBSAMPLE TIME RESOLUTION SIGNAL ALIGNMENT IN TIME DOMAIN

NATIONAL INSTRUMENTS CORP...

1. A system, comprising:
an input;
a functional unit, coupled to the input; and
an output, coupled to the functional unit;
wherein the functional unit is configured to:
a) acquire, via the input, a current set of samples of a first signal and a second signal;
b) generate a delayed copy of the current set of samples of the first signal using a first delay;
c) subtract the delayed copy of the current set of samples of the first signal from the current set of samples of the first
signal, thereby generating a third signal;

d) generate a delayed copy of the current set of samples of the second signal using a second delay, wherein the second delay
has a current subsample resolution time duration;

e) subtract the delayed copy of the current set of samples of the second signal from the current set of samples of the first
signal, thereby generating a fourth signal;

f) generate an error in alignment of the first and second signals based on a product of the third and fourth signals; and
g) adjust the current subsample resolution time duration based on the error in alignment;
perform a)-g) one or more times in an iterative manner, wherein iteratively adjusting the current subsample resolution time
duration generates a subsample resolution delay that aligns the second signal to the first signal; and

output, via the output, subsequent sets of samples of the first signal and the second signal in accordance with the subsample
resolution delay, wherein the subsequent sets of samples of the second signal are aligned with the subsequent sets of samples
of the first signal.

US Pat. No. 9,870,206

REPLICATION STRUCTURE IN A GRAPHICAL PROGRAMMING LANGUAGE

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a functional unit to
implement:
including a replication structure in a graphical program, wherein the including comprises displaying a replication structure
icon in the graphical program displayed on a display, wherein the replication structure icon comprises an interior portion,
wherein the replication structure specifies replication of any graphical program code inside the interior portion of the replication
structure icon:

including graphical program code inside the interior portion of the replication structure icon:
automatically generating an implementation of the graphical program, including:
generating multiple instances of an implementation of the graphical program code within the implementation of the graphical
program, wherein said generating is performed in response to including the graphical program code inside the interior portion
of the replication structure icon:
wherein the multiple instances of an implementation of the graphical program code are executed during execution of the implementation
of the graphical program.

US Pat. No. 9,860,052

DIGITAL PREDISTORTION FOR FULL-DUPLEX RADIO

National Instruments Corp...

1. An apparatus, comprising:
one or more antennas, wherein the apparatus is configured to simultaneously transmit and receive wireless signals via at least
partially overlapping frequency resources using the one or more antennas;

receive chain circuitry configured to process, during the simultaneous transmission and reception:
wireless signals transmitted by the apparatus via the one or more antennas; and
wireless signals from one or more other computing devices;
one or more processing elements configured to, during the simultaneous transmission and reception:
perform digital self-interference cancelation to cancel at least a portion of signals wirelessly transmitted by the apparatus
via the one or more antennas and processed by the receive chain circuitry;

determine one or more digital predistortion parameters based on the wireless signals transmitted by the apparatus via the
one or more antennas and processed by the receive chain circuitry; and

apply predistortion to transmitted wireless signals based on the one or more digital predistortion parameters.

US Pat. No. 9,740,411

CONFIGURING CIRCUITRY WITH MEMORY ACCESS CONSTRAINTS FOR A PROGRAM

NATIONAL INSTRUMENTS CORP...

11. A system, comprising:
one or more processors; and
one or more memories having program instructions stored thereon that are executable by the one or more processors to cause
the system to perform operations comprising:

determining a sequence of memory accesses for a program;
generating information specifying memory access constraints based on the sequence of memory accesses, wherein the memory access
constraints are usable to avoid memory access hazards for the sequence of memory accesses, wherein the generating is performed
during compilation of the program; and

configuring first circuitry using the information, wherein the first circuitry is included in or coupled to a memory, wherein
after said configuring the first circuitry is operable to:

receive the sequence of memory accesses based on execution of the program, wherein a processor executing the program sends
the sequence of memory accesses without waiting for resolution of memory access hazards; and

perform memory access requests to the memory corresponding to the sequence of memory accesses while avoiding the memory access
hazards, wherein the first circuitry is configured to avoid the memory access hazards without receiving other information
indicating the memory access hazards.

US Pat. No. 9,769,006

SPECTRAL STITCHING METHOD TO INCREASE INSTANTANEOUS BANDWIDTH IN VECTOR SIGNAL ANALYZERS

NATIONAL INSTRUMENTS CORP...

1. An apparatus for processing a signal, the apparatus comprising:
a first signal processing pathway configured to:
receive a first component signal comprising a first frequency band of an input signal; and
digitize the first component signal;
a second signal processing pathway, phase-locked and time-synchronized with respect to the first signal processing pathway,
the second signal processing pathway configured to:

receive a second component signal comprising a second frequency band of the input signal, the second frequency band having
a region of overlap with the first frequency band; and

digitize the second component signal;
wherein, when the second signal processing pathway is in a calibration mode, the second signal processing pathway is further
configured to compute a complex calibration constant, wherein the complex calibration constant is computed based on a phase
difference between a first digitized version of a calibration tone output of by the first signal processing pathway and a
second digitized version of the calibration tone output by the second signal processing pathway, wherein the calibration tone
is included within the region of overlap between the first frequency band and the second frequency band; and

a memory configured to store the complex calibration constant.

US Pat. No. 9,768,805

LPDC ENCODING TECHNIQUES USING A MATRIX REPRESENTATION

NATIONAL INSTRUMENTS CORP...

1. An apparatus, comprising:
one or more wireless radios; and
encoder circuitry configured to encode a message using a set of operations, wherein the set of operations are generated based
on a low-density parity-check (LDPC) encoding matrix and a second matrix, wherein the second matrix is smaller than the LDPC
encoding matrix and specifies columns in the LDPC encoding matrix that correspond to locations of non-zero entries in the
LDPC encoding matrix; and

wherein the one or more wireless radios are configured to:
transmit the encoded message.

US Pat. No. 9,753,835

DEBUGGING PARALLEL GRAPHICAL PROGRAM CODE

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a functional unit to
implement:
receiving a graphical program that includes parallel graphical program portions, wherein each graphical program portion comprises
at least one of:

a graphical subprogram; or
an execution path in the graphical program; and
single step debugging a first graphical program portion of the parallel graphical program portions, comprising:
for each step:
executing the single step in the first graphical program portion of the parallel graphical program; and
executing, concurrently and in the background, code in each of the other graphical program portions of the parallel graphical
program scheduled to execute between start and end of the single step in the first graphical program portion.

US Pat. No. 9,667,390

TIME-DOMAIN MECHANISM FOR COMPUTING ERROR VECTOR MAGNITUDE OF OFDM SIGNALS

NATIONAL INSTRUMENTS CORP...

1. A method comprising:
utilizing digital circuitry to perform a set of operations including:
(a) accessing an orthogonal frequency-division multiplexing (OFDM) input signal from memory, wherein the OFDM input signal
includes a sequence of time-domain OFDM input symbols, wherein the OFDM input signal is derived from a baseband signal produced
by an RF signal analyzer in response to a transmission of an RF OFDM signal from a device under test;

(b) accessing a reference signal, wherein the reference signal includes a sequence of time-domain OFDM reference symbols;
(c) computing a first error vector magnitude (EVM) in the time domain, wherein the first EVM is computed based on a time-domain
difference signal, wherein the time-domain difference signal is a time-domain difference between the sequence of time-domain
OFDM input symbols and the sequence of time-domain OFDM reference symbols, wherein the first EVM is determined without transforming
the sequence of time-domain OFDM input symbols to the frequency domain, and wherein derivation of the OFDM input signal from
the baseband signal does not include any transform to the frequency domain; and

(d) storing the first EVM in memory.

US Pat. No. 9,569,119

SELF-ADDRESSING MEMORY

NATIONAL INSTRUMENTS CORP...

1. A method, comprising:
receiving, by addressing circuity, memory access requests corresponding to a specified sequence of memory accesses from a
program, wherein the memory access requests do not include address information;

assigning, by the addressing circuitry, addresses to the memory access requests for the specified sequence of memory accesses,
wherein the addresses are assigned according to the specified sequence, wherein ordering and addresses of the specified sequence
are determined during compilation of the program, wherein the compilation includes execution of portions of the program to
determine the sequence of memory accesses; and

performing, by a memory, the sequence of memory accesses using the assigned addresses.

US Pat. No. 9,558,903

MEMS-BASED SWITCHING SYSTEM

National Instruments Corp...

1. An analog switching element that is at least partially implemented in one or more printed wiring boards (PWBs), comprising:
a plurality of inputs and a plurality of outputs integrated into the one or more PWBs;
a plurality of electromagnets coupled to or comprised in at least one of the one or more PWBs; and
a plurality of contact bars, wherein each contact bar is comprised in a respective contact bar pocket bounded at least partially
by at least one of the PWBs, wherein each contact bar comprises a conductive metal or alloy that is attracted by a magnetic
field, wherein each of the contact bars, via actuation by an externally applied magnetic field of a respective one of the
plurality of electromagnets, is selectively operable in:

a first state, wherein the at least one contact bar couples one of the plurality of inputs to one of the plurality of outputs
such that an analog signal input to the respective input is routed to the respective output; and

a second state, wherein the at least one contact bar is held in an off state.

US Pat. No. 10,089,157

AUTONOMOUS MANAGEMENT OF CONCURRENT SERVICING OF MULTIPLE CLIENTS BY AN INSTRUMENT

NATIONAL INSTRUMENTS CORP...

1. A non-volatile memory device storing autonomous concurrency management (ACM) programming instructions executable to cause an instrument to concurrently serve at least two clients, wherein to cause the instrument to concurrently serve the at least two clients, the programming instructions are executable to:implement a software lock function that tracks which clients of the at least two clients are active; and
implement at least one of the following:
a client separator function that keeps the at least two clients separated for a specified time duration;
a client rendezvous function that makes asynchronous clients of the at least two clients temporally synchronous clients that actively use the instrument at the same time; or
a client observer function that provides context information used to determine when to join two or more of the at least two clients.

US Pat. No. 9,983,852

GRAPHICAL SPECIFICATION AND CONSTRAINT LANGUAGE FOR DEVELOPING PROGRAMS FOR HARDWARE IMPLEMENTATION AND USE

National Instruments Corp...

1. An apparatus, comprising one or more processing elements configured to:receive first user input relating to a first functional block in a graphical program, wherein the user input specifies annotation information indicating a model of computation and constraints for the first functional block;
select the first functional block, based on the annotation information, for use in a graphical program that uses the model of computation;
wherein the constraints include:
initiation interval (II) information that indicates a minimum number of cycles between firings of the first functional block;
input pattern (IP) information that comprises a first sequence of values having a length that is smaller than or equal to the minimum number of cycles, wherein the first sequence of values aligns with the beginning of firing of the first functional block, wherein each instance of a particular value in the first sequence denotes consumption of a token at an input terminal of the first functional block; and
output pattern (OP) information that comprises a second sequence of values having a length that is smaller than or equal to the minimum number of cycles, wherein the second sequence of values aligns with the end of firing of the first functional block, wherein each instance of a particular value in the second sequence denotes production of a token at an output terminal of the first functional block; and
automatically generate an output program based on the graphical program, wherein the output program implements the functionality of the graphical program in accordance with the indicated model of computation, and further implements the constraints; and
wherein the output program configures a programmable hardware element to perform functionality of the selected functional block subject to the constraints.

US Pat. No. 9,977,564

PHYSICS BASED GRAPHICAL PROGRAM EDITOR AND USE

National Instruments Corp...

1. A non-transitory computer-accessible memory medium that stores program instructions executable by a processor to implement:displaying a graphical program on a display device, wherein the graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program;
receiving user input editing the graphical program, thereby generating an edited graphical program;
automatically adjusting placement of one or more elements within the edited graphical program based on said editing, wherein said adjusting is performed based on determined forces applied to the one or more elements in the edited graphical program, wherein said adjusting placement results in an adjusted edited graphical program, wherein said automatically adjusting comprises:
for a first element of the one or more elements, determining one or more attractive or repulsive forces based on the position of the first element and at least one other element; and
automatically adjusting the position of the first element based on the one or more attractive or repulsive forces; and
displaying the adjusted edited graphical program on the display device.

US Pat. No. 9,692,586

FLEXIBLE REAL TIME SCHEDULER FOR TIME DIVISION DUPLEXING AND/OR FREQUENCY DIVISION DUPLEXING

NATIONAL INSTRUMENTS CORP...

1. A method for operating a wireless communication node to enable dynamic control of frame structure, wherein the wireless
communication node comprises one or more antennas configured to transmit and receive wireless communications, and one or more
processors coupled to the one or more antennas, the method comprising, by the one or more antennas and the one or more processors:
(a) receiving a set of one or more transmit slot indices for a given frame in a sequence of frames, wherein each of the frames
includes a common number NS of slots, wherein the one or more transmit slot indices indicate which of the NS slots of the given frame are to be transmit slots;

(b) generating a first sequence of NS pulses for the given frame, wherein each pulse of said first sequence indicates a start of a corresponding slot within the
given frame;

(c) for each pulse of the first sequence, performing operations including:
determining if an index n of the pulse within the first sequence equals a current one of the transmit slot indices; and
in response to determining that the index n of the pulse within the first sequence equals the current transmit slot index,
processing payload data using the one or more processors to obtain samples for the nth slot of the given frame using first transmission parameters corresponding to said current transmit slot index, and transmitting
said samples using the one or more antennas within the nth slot of the given frame using second transmission parameters corresponding to said current transmit slot index.

US Pat. No. 9,581,630

METHOD FOR CALIBRATING A VECTOR NETWORK ANALYZER

NATIONAL INSTRUMENTS CORP...

1. A method for calibrating a vector network analyzer, said vector network analyzer comprising a plurality of ports and a
plurality of signal sources, the method comprising:
performing a first set of measurements using a set of known terminations connected to a first port of said plurality so that
a well-conditioned set of equations is obtained,

determining error coefficients for said first port by solving said well-conditioned set of equations, thereby obtaining a
first calibrated port,

for at least one uncalibrated port of said plurality of ports performing:
establishing a connection via a known through between an already calibrated port and said uncalibrated port,
applying to said already calibrated port a first signal from a first source of said plurality of signal sources and to said
uncalibrated port a second signal from a second source of said plurality of signal sources,

performing a further set of measurements using a set of terminations being realized with respect to said uncalibrated port
by manipulating said first and second source so that a further well-conditioned set of equations is obtained,

determining error coefficients for said uncalibrated port by solving said further well-conditioned set of equations, including
their relation with respect to said error coefficients at said already calibrated port, such that said uncalibrated port becomes
a calibrated port.

US Pat. No. 10,110,679

TIMED FUNCTIONS FOR DISTRIBUTED DECENTRALIZED REAL TIME SYSTEMS

NATIONAL INSTRUMENTS CORP...

1. An apparatus for scheduling a decentralized distributed real time system, comprising:a memory element configured to store first information; and
at least one centralized configuration device, configured to use at least a portion of the stored first information to implement at least one schedule generator, wherein the at least one centralized configuration device is configured to couple to a plurality of master devices, wherein each master device of the plurality of master devices is connected to a respective plurality of slave devices;
wherein each master device comprises respective one or more timed functions which, when locally executed by the master device, control timing of:
physical input operations and/or physical output operations for the respective plurality of slave devices connected to the master device; and
streams between the master device and the respective plurality of slave devices connected to the master device;
wherein, for each master device, the at least one schedule generator is configured to:
receive respective second information indicating:
a respective set of temporal properties for each timed function of the respective one or more timed functions on the master device, wherein each respective set of temporal properties pertains to:
execution of the timed function; and
coordination of the physical input operations and/or physical output operations of slave devices under control of the timed function with respect to other timed functions; and
associations between the respective one or more timed functions and respective second streams communicated between the master device and other ones of the plurality of master devices;
generate a respective schedule for the master device, based at least in part on the respective second information, wherein the respective schedule, when used by the master device, enables the master device to:
execute and coordinate the respective one or more timed functions in real time according to the respective schedule; and
coordinate the respective second streams between the master device and the other ones of the plurality of master devices in real time according to the respective schedule; and
distribute the respective schedule to the master device.

US Pat. No. 9,995,638

COLD-JUNCTION-COMPENSATED INPUT TERMINAL OF A THERMOCOUPLE INSTRUMENT

National Instruments Corp...

1. An input terminal of a thermocouple (TC) instrument, comprising:a printed circuit board (PCB);
a thermal sensor, mounted on the PCB, and configured to measure temperature at or near a cold junction of the input terminal; and
a TC receptacle portion, coupled to the PCB, and configured to receive a mating TC plug;
wherein the PCB comprises:
an input portion, configured to receive TC signals from a thermocouple; and
an output portion, configured to communicatively connect to the TC instrument;
first traces connecting the input portion of the PCB to the output portion of the PCB, and configured to send the TC signals to the TC instrument; and
second traces connecting the thermal sensor to the output portion of the PCB, and configured to send temperature signals to the TC instrument; and
wherein the traces at the output portion of the PCB implement a plurality of PCB implemented pins configured to provide the TC signals and the temperature signals to the TC instrument without using metal pins.

US Pat. No. 9,979,585

SPECTRAL STITCHING METHOD TO INCREASE INSTANTANEOUS BANDWIDTH IN VECTOR SIGNAL ANALYZERS

National Instruments Corp...

1. A method for processing a received signal, the method comprising:summing a plurality of component signals to obtain a composite signal;
digitizing, prior to the summing, each of the plurality of component signals, each component signal comprising a respective frequency band of the received signal;
frequency-shifting the component signals, prior to the summing, such that the respective frequency band of each component signal has a respective region of overlap with the frequency band of at least one other of the component signals;
shaping a frequency response of the component signals, by a digital filter prior to the summing, wherein a shape of the digital filter is based on the regions of overlap, wherein the digital filter has a reduced gain in at least a portion of the regions of overlap to reduce artificial increases in magnitude in the sum of the component signals in the regions of overlap; and
wherein said digitizing, frequency-shifting, and shaping, are performed by a respective signal processing pathway for each component signal and wherein the component signals are phase-locked.

US Pat. No. 9,977,563

PHYSICS BASED GRAPHICAL DIAGRAM EDITOR

National Instruments Corp...

1. A non-transitory computer-accessible memory medium that stores program instructions executable by a processor to implement:displaying a graphical diagram on a display device, wherein the graphical diagram comprises a plurality of interconnected nodes that visually indicate functionality of the graphical diagram;
receiving user input editing the graphical diagram, thereby generating an edited graphical diagram;
automatically adjusting placement of one or more elements within the edited graphical diagram based on said editing, wherein said adjusting is performed based on determined forces applied to the one or more elements in the edited graphical diagram, wherein said adjusting placement results in an adjusted edited graphical diagram, wherein said automatically adjusting comprises:
for a first element of the one or more elements, determining one or more attractive or repulsive forces based on the position of the first element and at least one other element; and
automatically adjusting the position of the first element based on the one or more attractive or repulsive forces; and
displaying the adjusted edited graphical diagram on the display device.

US Pat. No. 9,904,523

GRAPHICAL DEVELOPMENT AND DEPLOYMENT OF PARALLEL FLOATING-POINT MATH FUNCTIONALITY ON A SYSTEM WITH HETEROGENEOUS HARDWARE COMPONENTS

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer accessible memory medium that stores program instructions for configuring a system of heterogeneous
hardware components, wherein the program instructions are executable by a processor to:
create a graphical program that includes floating point math functionality, wherein the graphical program comprises a plurality
of interconnected nodes that visually indicate functionality of the graphical program, wherein the graphical program is targeted
for distributed deployment on a system comprising heterogeneous hardware components, including at least one programmable hardware
element and at least one processor;

automatically determine respective portions of the graphical program for deployment to respective ones of the heterogeneous
hardware components, including automatically determining respective execution timing for the respective portions;

automatically generate first program code implementing communication functionality between the at least one programmable hardware
element and the at least one processor, wherein the first program code is targeted for deployment to the at least one programmable
communication element; and

automatically generate at least one hardware configuration program from the graphical program and the first program code,
wherein said automatically generating comprises compiling the respective portions of the graphical program and the first program
code for deployment to respective ones of the heterogeneous hardware components;

wherein the hardware configuration program is deployable to the system, wherein after deployment, the system is configured
to execute portions of the graphical program concurrently, including the floating point math functionality.

US Pat. No. 9,800,229

PHASE ALIGNED INTERLEAVED SAMPLING OF MULTIPLE DATA CHANNELS

NATIONAL INSTRUMENTS CORP...

1. A method for processing data samples corresponding to a plurality of data channels, the method comprising:
obtaining, by data acquisition circuitry, a plurality of data samples derived from corresponding electrical signals received
by the plurality of data channels, said obtaining comprising successively receiving a respective data sample corresponding
to each data channel serially at a serial input port, said obtaining further comprising performing said successively receiving
a plurality of times during a specified time period, wherein each respective data sample is obtained at a respective sample
time, and wherein each respective sample time is relative to a single specified reference point in time; and
for each respective data sample:
determining, by a data processing circuit, a respective channel-dependent coefficient value corresponding to the respective
sample time at which the respective data sample is obtained; and

applying by the data processing circuit, the respective channel-dependent coefficient value to the respective data sample
to phase align the plurality of data channels.

US Pat. No. 9,733,911

VALUE TRANSFER BETWEEN PROGRAM VARIABLES USING DYNAMIC MEMORY RESOURCE MAPPING

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer accessibly memory medium that stores program instructions executable by a functional unit to
perform:
compiling a program, comprising:
determining one or more value transfer operations in the program, wherein each value transfer operation specifies a value
transfer between a respective one or more source variables and a destination variable;

for each of the one or more value transfer operations:
implementing the value transfer operation, wherein the implementation of the value transfer operation is executable to perform:
assigning each variable of the value transfer operation to a respective memory resource, thereby mapping the variables to
the memory resources; and

dynamically changing the mapping, including assigning the destination variable to the memory resource of a first source variable
of the one or more source variables, thereby transferring the value from the first source variable to the destination variable
without copying the value between the memory resources.

US Pat. No. 9,967,209

SWITCH FOR SCHEDULED DATA EGRESS

NATIONAL INSTRUMENTS CORP...

1. A method for configuring a network switch, comprising:configuring the network switch to receive network packets non-deterministically from a network node of a real time network, wherein each network packet has a destination address and a type that specifies a respective egress period, wherein the network switch comprises a plurality of ports, wherein each port is configured with a respective set of destination addresses and a respective set of egress periods, and is associated with respective queues for the egress periods;
configuring the network switch to deterministically route the network packets based on the destination address and type of each network packet, comprising, for a first network packet, configuring the network switch to:
determine a port of the plurality of ports for the first network packet based on the destination address of the first network packet;
determine an egress period for the first network packet based on the type of the first network packet, wherein the respective egress period specifies a time window for egressing the first network packet;
determine that the first network packet cannot currently be egressed from the determined port; and
in response to determining that the first network packet cannot currently be egressed:
store the first network packet in a queue associated with the port based on the destination address and type of the first network packet; and
egress the first network packet from the port during the egress period, thereby deterministically egressing the first network packet in the time window specified by the egress period.

US Pat. No. 9,733,914

LOOP PARALLELIZATION ANALYZER FOR DATA FLOW PROGRAMS

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a processor to:
store a data flow program, wherein the data flow program comprises one or more iterative data flow program portions, wherein
each iterative data flow program portion comprises data flow program code configured to execute repeatedly in an iterative
manner;

automatically analyze the data flow program, including performing dependence analysis for each of the one or more iterative
data flow program portions, thereby determining whether each of the one or more iterative data flow program portions is parallelizable,
wherein said performing dependence analysis comprises determining whether output from a first subset or iteration of data
flow program code of the iterative data flow program portion is required by a second subset or iteration of the data flow
program code of the iterative data flow program portion; and

store an indication of each of the one or more iterative data flow program portions that is parallelizable, wherein the indications
are useable to parallelize the data flow program.

US Pat. No. 9,755,289

RIGHT ANGLE TRANSITION TO CIRCUIT

NATIONAL INSTRUMENTS CORP...

1. A system, comprising:
a conductive plate;
a coaxial transmission line, comprising:
a center pin protruding orthogonally through a hole in the conductive plate;
an outer conductor formed by a conductive surface of the hole;
a solid dielectric surrounding the center pin and disposed within the coaxial transmission line; and
air dielectric between the center pin and the outer conductor;
a circuit, parallel to the conductive plate, the circuit comprising:
a top conducting layer;
a ground plane, comprising a first cutout; and
an insulating substrate between the top conducting layer and the ground plane, wherein the insulating substrate of the circuit
abuts the center pin of the coaxial transmission line;

wherein the ground plane is affixed to the conductive plate, wherein the hole in the conductive plate forms a second cutout
with a larger radius than the first cutout; and

a right angle transition from the coaxial transmission line to the circuit, wherein the right angle transition comprises:
the center pin of the coaxial transmission line;
a conductive element that electrically connects the center pin of the coaxial transmission line to the top conducting layer
of the circuit;

the outer conductor;
the air dielectric between the center pin and the outer conductor;
the abutment of the insulating substrate of the circuit against the center pin of the coaxial transmission line;
the first cutout; and
the second cutout
wherein the abutment and the first cutout operate to minimize manufacturing variations regarding distance between the center
pin and the ground plane;

wherein during operation the right angle transition tunes out inductance introduced by bonding the center pin of the coaxial
transmission line to the top conducting layer, and wherein the solid dielectric of the coaxial transmission line has a larger
radius than a radius of the first cutout and a radius of the second cutout.

US Pat. No. 9,699,100

LOSSLESS TIME BASED DATA ACQUISITION AND CONTROL IN A DISTRIBUTED SYSTEM

NATIONAL INSTRUMENTS CORP...

1. A method for configuring the mapping of a time-based data acquisition to an isochronous data transfer channel of a network,
the method comprising:
configuring a local buffer for receiving data from the time-based data acquisition, comprising configuring a size of the local
buffer, wherein the size of the local buffer is based on a transfer frequency of a first buffer and a data rate of the time-based
data acquisition;

configuring buffer size of the first buffer for receiving data from the local buffer, wherein the first buffer is associated
with the isochronous data transfer channel of the network; and

configuring a functional unit to:
initiate continuous performance of the time-based data acquisition, wherein the time-based data acquisition is performed according
to a first clock, wherein the data from the continuous performance of the time-based data acquisition is stored in the local
buffer; and

initiate continuous transfer of the data from the local buffer to the first buffer, wherein the transfer from the local buffer
to the first buffer is performed according to the first clock.

US Pat. No. 10,122,495

FLEXIBLE POLYNOMIAL-BASED INTERLEAVER

NATIONAL INSTRUMENTS CORP...

1. An apparatus, comprising:a plurality of memory blocks configured to store interleaved input data samples in parallel;
one or more circuit elements configured to:
receive input data samples, a plurality of polynomial coefficients, a start index, and information indicating a window size for non-sequential traversal of interleaver indices, wherein the plurality of polynomial coefficients includes coefficients for at least a third-order polynomial; and
generate interleaved bank and address information for writing the input data samples to the plurality of memory blocks, based on an order of the polynomial, a code block length, the start index, and the information indicating the window size; and
output circuitry configured to provide interleaved data samples from the plurality of memory blocks.

US Pat. No. 9,991,938

INTRA-NODE CHANNEL RECIPROCITY COMPENSATION FOR RADIO ACCESS IN MIMO WIRELESS COMMUNICATION SYSTEMS

NATIONAL INSTRUMENTS CORP...

1. A method, comprising:for each antenna of M antennas of a wireless cellular base station:
transmitting, by the antenna, a calibration pilot symbol over the air; and
receiving, by the other M?1 antennas, the calibration pilot symbol over the air;
selecting one of the M antennas as a reference antenna;
for each antenna of the M antennas:
calculating channel reciprocity calibration coefficients of the antenna with respect to the reference antenna based on the received calibration pilot symbols;
applying the calculated channel reciprocity calibration coefficients within receive and/or transmit path circuitry of the base station; and
wherein said applying the calculated channel reciprocity calibration coefficients within receive and/or transmit path circuitry of the base station comprises:
for each antenna of the M antennas, averaging the calculated channel reciprocity calibration coefficients associated with the antenna over all subcarriers of a plurality of subcarriers to obtain a single coefficient for the antenna and applying the single coefficient within the receive and/or transmit path circuitry.

US Pat. No. 9,702,313

DIRECT INJECTION CROSS POINT SWITCHING FOR MULTIPLEXING CONTROL IN AN ENGINE CONTROL SYSTEM

NATIONAL INSTRUMENTS CORP...

1. An engine control system comprising:
a plurality (N) of pins, each respective pin of the N pins configured to couple to an injector;
a plurality of measurement circuits comprising a different individual measurement circuit coupled to each respective pin of
the N pins, each individual measurement circuit configured to provide a respective output corresponding to a voltage developed
at the respective pin coupled to the individual measurement circuit;

a plurality of subtraction circuits, each subtraction circuit of the plurality of subtraction circuits having a respective
pair of inputs and configured to provide an output corresponding to a difference between respective input values that appear
at the pair of inputs of the subtraction circuit;

a plurality of cross-point switches coupled to the plurality of measurement circuits and the plurality of subtraction circuits;
and

a control block configured to determine a voltage difference between any two pins of the N pins by operating the cross-point
switch to selectively couple the respective output of each of the two individual measurement circuits coupled to the any two
pins, to a corresponding respective input of the pair of inputs of any one of the plurality of subtraction circuits.

US Pat. No. 10,069,400

COMMON-MODE CURRENT CANCELLATION WITH SWITCHING WAVEFORMS FROM ISOLATED APPLICATIONS USING A VARIABLE CAPACITOR NETWORK

NATIONAL INSTRUMENTS CORP...

1. A system comprising:a first subsystem configured to generate a compensation signal, wherein the first subsystem comprises:
a driver circuit configured to generate drive signals for an isolation mechanism, and provide the drive signals to the isolation mechanism; and
a compensation circuit configured to receive the drive signals and generate the compensation signal according to at least the drive signals; and
an isolated subsystem coupled to the first subsystem via the isolation mechanism, wherein the isolation mechanism is configured to block DC signals from being received at the isolated subsystem, wherein the isolated subsystem is configured to receive a common-mode current from the first subsystem via the isolation mechanism;
wherein the compensation circuit is configured to provide the compensation signal to a ground plane of the isolated subsystem to reduce or eliminate the common-mode current received at the isolated subsystem.

US Pat. No. 10,181,858

AUTO-ZERO ALGORITHM FOR REDUCING MEASUREMENT NOISE IN ANALOG-TO-DIGITAL SYSTEMS OVER A WIDE RANGE OF SAMPLING RATES

NATIONAL INSTRUMENTS CORP...

1. A data acquisition (DAQ) system comprising:an input terminal configured to receive a signal;
a first circuit configured to sample the signal according to a specified sampling rate that defines a sampling time interval, wherein during each sampling time interval:
the signal is a reference signal during a first time period of the sampling time interval for obtaining first samples representative of the reference signal; and
the signal is an input signal during a second time period of the sampling time interval for obtaining second samples representative of the input signal;
wherein a ratio of the second time period to the first time period is determined based on the sampling rate; and
a second circuit configured to:
process the first samples to obtain an offset value;
process the second samples to obtain an input signal value; and
adjust the input signal value based on the offset value.

US Pat. No. 10,175,334

SELF-CALIBRATION OF SOURCE-MEASURE UNIT VIA CAPACITOR

NATIONAL INSTRUMENTS CORP...

1. A method for calibrating and operating a source-measure unit (SMU), the method comprising:applying an excitation signal by the SMU to a capacitor;
obtaining one or more of:
a current calibration coefficient (CCC) corresponding to a current-range setting of the SMU, said obtaining the CCC comprising:
determining a value of a first current developed in the capacitor responsive to the excitation signal and determining a value of a second current developed in the capacitor responsive to the excitation signal; and
determining the CCC from the value of the first current and the value of the second current; or
a voltage calibration coefficient (VCC) corresponding to a voltage-range setting of the SMU, said obtaining the VCC comprising:
determining a value of a first voltage developed across the capacitor responsive to the excitation signal and determining a value of a second voltage developed across the capacitor responsive to the excitation signal; and
determining the VCC from the value of the first voltage and the value of the second voltage;
performing a measurement, by the SMU, on a device under test; and
correcting an error in the measurement, using one or more of:
the obtained CCC; or
the obtained VCC.

US Pat. No. 10,164,670

TIME SEQUENCED SPECTRAL STITCHING

NATIONAL INSTRUMENTS CORP...

17. An apparatus for representing a finite time period of a frequency band of interest of a repeating received signal, the apparatus comprising:a memory configured to store a plurality of digitized component signals, each of the digitized component signal representing a digital representation of a frequency subset of a frequency band of interest of a repeating signal, each frequency subset based on a respective repetition of the repeating signal, each frequency subset having a respective center frequency with a respective frequency offset from a center frequency of the frequency band of interest, and each frequency subset having at least one overlap portion constituting a region of frequency overlap with another frequency subset;
a summing device configured to sum the digitized component signals to obtain a composite signal having a composite frequency band representing at least the frequency band of interest; and
a plurality of signal processing paths, each signal processing path comprising:
a digital filter configured to filter a respective digitized component signal, prior to the summing, the digital filter having a reduced gain in at least a portion of the overlap portions to reduce artificial increases in magnitude in the composite signal within the overlap portions; and
a frequency-shift device configured to frequency-shift a respective digitized component signal, prior to the summing, by the respective frequency offset of the respective subset of the frequency band of interest.

US Pat. No. 10,164,793

SYSTEM AND METHOD FOR INTEROPERABILITY BETWEEN MULTIPLE NETWORKS

NATIONAL INSTRUMENTS CORP...

1. A system for interoperating between a first real time network and one or more second real time networks, the system comprising:a plurality of ports, comprising:
at least one port coupled to the first real time network, wherein the first real time network carries first traffic comprising best effort traffic and first real time traffic; and
one or more ports coupled respectively to the one or more second real time networks, wherein each of the one or more second real time networks carries second traffic comprising only second real time traffic, and wherein the first real time network and the one or more second real time networks operate according to different protocols; and
switch circuitry, coupled to the plurality of ports, wherein the switch circuitry is configured with a mapping that specifies data routing between the plurality of ports;
wherein the switch circuitry is configured to route packets between the first real time network and the one or more second real time networks based on the mapping, thereby maintaining real time behavior between the first real time traffic and the second real time traffic, wherein the switch circuitry inserts routing information in packets routed from the one or more second real time networks to the first real time network, and wherein the switch circuitry removes routing information from the packets routed from the first real time network to the one or more second real time networks;
wherein the switch circuitry is configured to route packets to distinct queues for the first traffic and the second traffic for processing by an application executing on at least one device and time stamp ingress and egress of packets to/from the first queue pairs and the one or more second queue pairs, wherein said routing of the packets to the distinct queues is performed based on the mapping, wherein the distinct queues comprise first queue pairs associated with first traffic and one or more second queue pairs associated with second traffic, and wherein the application correlates clock synchronization information of the first real time network and one or more second real time networks based on the time stamps.

US Pat. No. 10,218,548

WIRELESS RADIO RECEIVER THAT PERFORMS ADAPTIVE PHASE TRACKING

National Instruments Corp...

1. A wireless radio receiver that estimates and compensates for phase drift in a series of signal blocks received from a wireless channel, wherein each signal block of the series of signal blocks comprises a collection of data symbols, wherein an initial signal sequence and a terminal signal sequence are associated with each signal block of the series of signal blocks, wherein the initial and terminal signal sequences of each signal block are identical as transmitted by a transmitter, wherein the initial signal sequence either immediately precedes the signal block or comprises an initial portion of the data symbols of the signal block, wherein the terminal signal sequence either immediately follows the signal block or comprises a terminal portion of the data symbols of the signal block, the receiver comprising:a pre-equalization phase tracking unit configured to, for each signal block of the series of signal blocks:
compute an autocorrelation between a portion of the initial and terminal sequences associated with the signal block and compute a phase of the autocorrelation;
estimate a start phase of a first symbol within a block processing window associated with the signal block using the computed phase of the autocorrelation and the start phase of the first symbol within the block processing window associated with the previous signal block in the series of signal blocks;
estimate a phase drift within the block processing window by interpolating using the estimated start phases of the first symbol within the block processing windows associated with at least the signal block and the next signal block in the series of signal blocks; and
compute a phase compensation signal using the estimated phase drift within the block processing window and compensate for the estimated phase drift using the computed phase compensation signal.

US Pat. No. 10,218,549

WIRELESS RADIO RECEIVER THAT PERFORMS ADAPTIVE PHASE TRACKING

National Instruments Corp...

1. A wireless radio receiver that estimates and compensates for phase drift in a series of signal blocks received from a wireless channel, comprising:a post-equalization phase tracking unit configured to, for each signal block of the series of signal blocks:
compute an absolute phase rotation at the beginning of the signal block using an equalized version of pilot symbols preceding the signal block;
subdivide the signal block into a time sequence of groups of equalized modulated data symbols;
initialize an accumulated phase associated with the first-in-time group of the time sequence of groups with the computed absolute phase rotation; and
for each group of the time sequence of groups in time sequential order, wherein the group has an associated previous group in the time sequence of groups:
compute a de-rotated version of each equalized modulated data symbol within the group using the accumulated phase associated with the previous group;
blindly estimate a residual phase within the group using the de-rotated version of the equalized modulated data symbols within the group;
assign the accumulated phase associated with the group with a sum of the blindly estimated residual phase within the group and the accumulated phase associated with the previous group;
estimate phase drift within the group by using at least the accumulated phase associated with the group; and
compute a phase compensation signal for the group using the estimated phase drift within the group and compensate for phase drift on each equalized modulated data symbol within the group using the computed phase compensation signal.

US Pat. No. 10,205,824

METHODS AND SYSTEMS FOR ESIM PROGRAMMING OF CELLULAR DEVICES DURING WIRELESS POWER PROVISION

National Instruments Corp...

1. An apparatus, comprising:a wireless power supply configured to wirelessly provide power to a cellular device having an embedded subscriber identification module (eSIM) while the cellular device is placed adjacent to the wireless power supply;
a radio;
a processor programmed to control the radio to wirelessly provide a subscriber identification module (SIM) profile to the cellular device for loading into the eSIM while the wireless power supply wirelessly provides power to the cellular device;
wherein the radio comprises a cellular frequency radio; and
a radio frequency (RF) shielded chamber configured to receive the cellular device while the wireless power supply wirelessly provides power to the cellular device and while the radio wirelessly provides the SIM profile to the cellular device.

US Pat. No. 10,201,020

MULTI-USER RANDOM ACCESS PROCEDURES FOR MASSIVE MIMO WIRELESS COMMUNICATION SYSTEMS

National Instruments Corp...

1. A method for performing multi-user random access procedures in a mobile telecommunications network between a base station and a user equipment (UE) having a plurality of antennas, the method comprising:transmitting a random access signal set (RASS) message using one or more antennas of the plurality of UE antennas;
in response to receiving the RASS message:
transmitting, by the base station, a random access response physical downlink control channel (RAR-PDCCH) message; and
in response to receiving the RAR-PDCCH message:
transmitting a reciprocity reference signal set (RRSS) signal using the plurality of UE antennas.

US Pat. No. 10,181,913

FREQUENCY RESPONSE CALIBRATION OF SYNCHRONIZED MIMO MEASUREMENT RECEIVERS WITH LOCAL AND REMOTE TRANSMITTERS

NATIONAL INSTRUMENTS CORP...

1. A method for calibrating a remote transmitter (RT) to a plurality of receivers in a multiple input multiple output (MIMO) communication system, the method comprising:operating in a first calibration mode, wherein operating in the first calibration mode comprises:
deriving first equalizers for a local transmitter (LT), wherein the first equalizers align a time and a phase, and correct a non-uniform frequency response, associated with communication between the LT and the plurality of receivers; and
deriving second equalizers for the RT, wherein the second equalizers align a time and a phase, and correct a non-uniform frequency response, associated with communication between the RT and the plurality of receivers; and
operating in a second calibration mode, wherein the RT is located remotely from the MIMO system while operating in the second calibration mode, wherein operating in the second calibration mode comprises:
deriving third equalizers for the LT, wherein the third equalizers align a time and a phase, and correct a non-uniform frequency response, associated with communication between the LT and the plurality of receivers; and
deriving fourth equalizers that are based on each of the first, second, and third equalizers, wherein the fourth equalizers are usable to calibrate communications received by the MIMO system from the remotely located RT.

US Pat. No. 10,176,137

SELECTIVELY TRANSPARENT BRIDGE FOR PERIPHERAL COMPONENT INTERCONNECT EXPRESS BUS SYSTEM

NATIONAL INSTRUMENTS CORP...

1. A system comprising:a switch fabric subsystem having a point to point topology and comprising respective devices that operate according to a bus protocol associated with the switch fabric;
a host system; and
a bus extender coupling the host system to the switch fabric subsystem, and configured to:
create a virtual bus topology corresponding to an actual bus topology of the switch fabric subsystem;
selectively hide one or more devices of the respective devices from the host system by omitting the one or more devices from the virtual bus topology, resulting in the one or more devices being hidden from the host system, and remaining devices of the respective devices being visible to the host system;
make the virtual bus topology apparent to the host system during configuration of the respective devices;
intercept configuration packets generated by the host system based on the virtual bus topology for configuring the visible remaining devices; and
configure the selectively hidden one or more devices and the visible remaining devices according to the actual bus topology, and based at least partially on contents of the intercepted configuration packets.

US Pat. No. 10,125,706

BOOST POWER SUPPLY SEQUENCING

NATIONAL INSTRUMENTS CORP...

1. A boost power supply comprising:a plurality of switching power supplies, each switching power supply of the plurality of switching power supplies configured to source a respective portion current of a combined output current provided by the boost power supply to a load at an output of the boost power supply; and
control circuitry configured to:
control each switching power supply by a different respective switch control signal of a plurality of switch control signals to regulate the respective portion current sourced by the switching power supply to provide a different percentage of the combined output current at any given time than a percentage of the combined output current provided by another one of the plurality of switching power supplies at the given time; and
assert each different respective switch control signal of the plurality of switch control signals out of phase with respect to each other different respective switch control signal, and simultaneously with at least one other different respective switch control signal for at least a specified duration, such that the combined output current is prevented from exceeding a specified threshold current value while maintaining at least a specified average current draw from the boost power supply.

US Pat. No. 10,257,005

RADIO FREQUENCY (RF) COMMUNICATION SYSTEMS USING RF SWITCHING GUARD PERIODS TO TRANSMIT SPECIAL SYMBOLS IN BLOCK SYMBOL TRANSMISSIONS

National Instruments Corp...

1. A method, comprising:processing a subframe as part of a time-domain signal frame structure used for radio frequency communications;
wherein the subframe includes:
a plurality of block symbols each having an associated time-domain guard period;
one or more radio frequency (RF) switching guard periods; and
wherein the time-domain guard period comprises a zero prefix, cyclic prefix or post fix;
wherein each block symbol of the plurality of block symbols is either a common block symbol or a special block symbol;
wherein the common block symbols have a common time-domain guard period;
wherein the special block symbols have a time-domain guard period different from the common time-domain guard period;
wherein all the special block symbols in the subframe are placed into the one or more RF switching guard periods; and
wherein two or more of the special block symbols have a time-domain guard period that is different from each other and that is different from the common time-domain guard period.

US Pat. No. 10,257,329

WIRELESS COMMUNICATIONS APPARATUS AND METHOD FOR PERFORMING LOW LATENCY HIGH THROUGHPUT LAYER 2 OPERATIONS

National Instruments Corp...

1. An apparatus for use in performing wireless communications, comprising:at least one memory unit;
a first data source/sink that sources/sinks packet data convergence protocol (PDCP) service data units (SDU) for transfer to/from the memory unit;
a second data source/sink that sources/sinks media access control (MAC) protocol data units (PDU) for transfer to/from the memory unit;
a plurality of hardware accelerators coupled to the memory unit;
a control processor that controls the plurality of hardware accelerators;
wherein in response to the first data source sourcing one or more transmit PDCP SDU for transfer to the memory unit, the control processor controls the plurality of hardware accelerators to:
generate and write PDCP, radio link control (RLC), and MAC headers to the memory unit; and
assemble the generated PDCP, RLC and MAC headers and the one or more transmit PDCP SDU from the memory unit into one or more transmit MAC PDU for provision to the second data sink; and
wherein in response to the second data source sourcing one or more receive MAC PDU for transfer to the memory unit, the control processor controls the plurality of hardware accelerators to:
decode PDCP, RLC and MAC headers of the one or more receive MAC PDU in the memory unit to determine locations of one or more receive PDCP SDU in the memory unit; and
fetch the one or more receive PDCP SDU from the determined locations in the memory unit for provision to the first data sink.

US Pat. No. 10,243,678

LINEARIZATION OF RADIO FREQUENCY TRANSCEIVERS AND TEST SYSTEMS THROUGH DYNAMIC EXTRACTION OF COMPLEX NONLINEAR MODELS THEREOF

National Instruments Corp...

1. A method for obtaining a complex high-order nonlinear model of a signal path of a radio frequency (RF) system, the method comprising:adjusting a first signal path of the RF system to operate according to specified settings;
configuring a second signal path of the RF system to operate in a high-linearity mode;
when the first signal path comprises a transmit signal chain and the second signal path comprises a receive signal chain:
generating, in the first signal path, a test signal at a desired level according to the specified settings, wherein the test signal is generated from a baseband signal having at least two tones; and
receiving, by the second signal path operating in the high-linearity mode, the generated test signal, and outputting an acquired test signal resulting from the generated test signal at an output of the second signal path;
when the first signal path comprises a receive signal chain and the second signal path comprises a transmit signal chain:
generating, in the second signal path operating in the high-linearity mode, the test signal at the desired level; and
receiving, by the first signal path operating according to the specified settings, the generated test signal, and outputting the acquired test signal at an output of the first signal path; and
extracting, by a processing unit, a complex high-order nonlinear memory-less model representative of the first signal path, wherein the extracting comprises analyzing, by the processing unit, the acquired test signal according to a specified algorithm that analytically identifies and isolates passband nonlinear components of the acquired test signal.

US Pat. No. 10,243,715

UNIFIED FLEXIBLE RADIO ACCESS TECHNOLOGY (RAT) FOR 5G MOBILE COMMUNICATION SYSTEMS

National Instruments Corp...

1. An apparatus for wireless communications, comprising:one or more antennas;
one or more radios coupled to the one or more antennas; and
one or more processors coupled to the one or more radios and programmed to:
receive communication frames including OFDM (orthogonal frequency division multiplex) symbols from a plurality of wireless devices through the one or more radios and the one or more antennas; and
transmit communication frames including OFDM symbols to the plurality of wireless devices through the one or more radios and the one or more antennas;
wherein the communication frames comprise multi-partition frames having a mix of different partition types;
wherein the different partition types comprise configuration parameters including sampling rate and subcarrier spacing;
wherein the different partition types have different subcarrier spacings and a common sampling rate;
wherein frame scheduling applies the different partition types to the multi-partition frames on a dynamic basis;
wherein the one or more processors are further configured to communicate control messages for configuration with the plurality of wireless devices through the one or more radios and the one or more antennas, the control messages comprising the configuration parameters of the different partition types; and
wherein the one or more processors are further configured to communicate reconfiguration messages with the plurality of wireless devices through the one or more radios and the one or more antennas to reconfigure the frame scheduling for the multi-partition frames.

US Pat. No. 10,241,764

AUTOMATICALLY TRANSFORM PASS-BY-VALUE SEMANTICS INTO PASS-BY-REFERENCE IMPLEMENTATION

National Instruments Corp...

1. An apparatus, comprising:a processor; and
a non-transitory computer accessible memory medium coupled to the processor that stores program instructions executable by the apparatus to perform:
compiling a program to generate output code, the compiling comprising:
determining one or more program structures in the program containing one or more variables at the entry or exit of each of these program structures, wherein each variable at the entry or exit of a program structure specifies a value transfer between outside of a program structure and inside the program structure, and wherein each value transfer specifies a value transfer from one or more source variables to a destination variable; and
implementing each of the value transfer operations in the output code, wherein, during operation based on the output code, the implementation of the value transfer operation includes:
assigning each variable of the value transfer operation to a respective memory resource, thereby mapping the variables to the memory resources;
determining a subset of the destination variables for which assigning the destination variable to a memory resource of a corresponding source variable does not disrupt the functionality of the program; and
for the subset of the destination variables, dynamically changing the mapping, including assigning the destination variable to the memory resource of a first source variable of the one or more source variables, thereby transferring the value from the first source variable to the destination variable without copying the value between the memory resources.

US Pat. No. 10,235,477

PROTOTYPING AN IMAGE PROCESSING ALGORITHM AND EMULATING OR SIMULATING EXECUTION ON A HARDWARE ACCELERATOR TO ESTIMATE RESOURCE USAGE OR PERFORMANCE

National Instruments Corp...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a processor to implement:storing a machine vision prototype, the machine vision prototype comprising:
a plurality of machine vision steps, wherein the plurality of machine vision steps specifies a machine vision image processing algorithm and associated parameters, and wherein the plurality of machine vision steps is interpretable by an emulator to perform the specified image processing on an image by emulating or simulating execution of the plurality of machine vision steps by a hardware accelerator;
analyzing the machine vision prototype;
automatically generating, based on said analyzing, a graphical program implementing the specified image processing algorithm, wherein the graphical program parallelizes at least a portion of the image processing, and wherein the graphical program is targeted for deployment to the hardware accelerator;
estimating resource usage or performance of execution of the graphical program by the hardware accelerator;
based on the estimated resource usage or performance, determining that the hardware accelerator is capable of executing the graphical program; and
based on the determination that the hardware accelerator is capable of executing the graphical program, deploying the graphical program to the hardware accelerator.

US Pat. No. 10,235,265

SEQUENTIALLY CONSTRUCTIVE MODEL OF COMPUTATION

National Instruments Corp...

1. A non-transitory computer-readable storage medium having instructions stored thereon that are executable by a computing device to perform operations comprising:receiving a program that specifies relative sequencing of a first plurality of operations within a logical tick and does not specify relative sequencing of a second plurality of operations within the logical tick, wherein all computations within the logical tick are interpreted as being instantaneous, and wherein logical ticks specify the resolution of functional synchronization for execution of the program;
statically analyzing the program according to a specified model of computation that specifies synchronous program execution based on logical ticks, wherein said statically analyzing the program includes:
determining that the first plurality of operations preserves deterministic execution within the logical tick based on sequence information, wherein deterministic execution comprises a final result of the first plurality of operations within the logical tick; and
determining that the second plurality of operations meets a set of criteria for a deterministic result regardless of ordering, wherein the set of criteria includes one or more of:
a criterion that reads of a variable follow assignments to the variable, unless it is determined that ordering of the reads and assignments is not required for deterministic semantics:
a criterion that at most one absolute assignment is performed for a given variable;
a criterion that assignment operations to a given variable are commutative and associative; or
a criterion that assignment operations to a given variable are of a same type;
wherein one or more of the first plurality of operations do not meet one or more criteria of the set of criteria;
validating the program in accordance with the specified model of computation based on said statically analyzing; and
transforming the program to generate deterministically executable code; and
performing one of:
executing the deterministically executable code using hardware; or
implementing the deterministically executable code in hardware.

US Pat. No. 10,235,868

EMBEDDED SHARED LOGICAL INSTRUMENT

National Instruments Corp...

1. A system, comprising:a processor; and
a memory, coupled to the processor, wherein the processor is configured to execute program instructions stored on the processor, wherein the program instructions to cause the processor to implement:
a plurality of logical instruments, wherein each logical instrument is configured to perform measurement functions via at least one corresponding physical measurement device;
a plurality of isolated memory spaces in the memory, wherein each isolated memory space is configured to store configuration information and working data for a respective logical instrument; and
at least one measurement engine;
wherein the plurality of logical instruments are configured to operate concurrently, and wherein each of the plurality of logical instruments is configured to:
communicate with a respective client application independently; and
acquire, generate, or process data using the at least one corresponding physical measurement device via the at least one measurement engine per the configuration information; and
wherein during operation, at least two of the logical instruments share use of a single physical measurement device.

US Pat. No. 10,230,434

WIRELESS TRANSCEIVER STATION WITH PERFORMS MULTI-PATH RECIPROCITY CALIBRATION WITH MULTIPLE REFERENCE ANTENNAS

National Instruments Corp...

1. A wireless transceiver station, comprising:M antennas connected to radio transceivers; and
a processor, programmed to:
designate an antenna of the M antennas as a target reference antenna; and
for each antenna m of the M antennas other than the target reference antenna:
define N distinct paths from the antenna m to the target reference antenna through zero or more intermediate reference antennas of the M antennas, wherein N for the antenna m is two or more;
wherein each of the N distinct paths has a distinct associated set of one or more antenna pairs of the M antennas;
for each antenna pair of the sets of antenna pairs:
estimate an effective forward and backward channel response by sending calibration pilots forth and back between the antenna pair; and
calculate a reciprocity coefficient for the antenna pair using the estimated channel responses;
for each path of the N distinct paths:
calculate a reciprocity coefficient estimate using the reciprocity coefficients calculated for the set of antenna pairs associated with the path; and
combine the N calculated reciprocity coefficient estimates to produce a final reciprocity coefficient estimate for antenna pair (m, target reference antenna).

US Pat. No. 10,218,405

I/Q MODULATOR AND DEMODULATOR WITH WIDE INSTANTANEOUS BANDWIDTH AND HIGH LOCAL-OSCILLATOR-PORT-TO-RADIO-FREQUENCY-PORT ISOLATION

NATIONAL INSTRUMENTS CORP...

1. An apparatus comprising:a first circuit comprising a radio frequency (RF) port; and
a plurality of mixers comprising a first set of ports coupled to the first circuit, and further comprising a second set of ports, wherein the plurality of mixers are configured to:
operate as downconverters when signals are applied to the plurality of mixers at the first set of ports; and
operate as upconverters when signals are applied to the plurality of mixers at the second set of ports.

US Pat. No. 10,216,495

PROGRAM VARIABLE CONVERGENCE ANALYSIS

NATIONAL INSTRUMENTS CORP...

1. A non-transitory computer accessible memory medium that stores program instructions executable by a processor to implement:initiating an analysis of a first program;
in response to initiating the analysis, determining, based on dependencies of one or more variables in the first program, one or more state variables of the first program;
creating, based on the one or more state variables and dependencies of the one or more state variables, a second program corresponding to the first program;
executing the second program a plurality of times, comprising:
for each execution:
recording values of the one or more state variables;
incrementing an execution count;
comparing the values to corresponding values from previous executions of the second program; and
terminating said executing in response to determining that the values match corresponding values from at least one previous execution of the second program;
determining, based on the execution count, a convergence property for the first program that indicates a number of executions of the first program required to generate all possible values of the one or more variables, wherein the convergence property is useable to optimize the first program; and
displaying the convergence property,
wherein said executing the second program comprises one or more of:
running compiled code on a computer, wherein the compiled code is generated from at least a portion of the second program;
interpreting program statements of at least a portion of the second program; or
evaluating operations in a graph generated from at least a portion of the second program.

US Pat. No. 10,145,866

MANUFACTURING A LOW PROFILE CURRENT MEASUREMENT CONNECTOR

NATIONAL INSTRUMENTS CORP...

1. A method for manufacturing a current measurement connector, the method comprising:casting a first part of the current measurement connector, wherein the first part comprises:
a first mount; and
a first joint;
casting a second part of the current measurement connector, wherein the second part comprises:
a second mount; and
a second joint; and
joining the first part and the second part via the first and second joints through an opening of a current transformer interposed between the first part and the second part, thereby electrically coupling the first mount to the second mount, wherein the first mount and the second mount are configured to receive a first current from a current source;
wherein the current measurement connector is configured to pass the first current through the first and second joints thereby inducing a second current in the current transformer, wherein the second current is useable to measure the first current.

US Pat. No. 10,277,734

METHODS AND SYSTEMS FOR ESIM PROGRAMMING OF CELLULAR DEVICES

National Instruments Corp...

1. An apparatus, comprising:a cellular frequency radio, either coupled to or configured to be coupled to an antenna, wherein the antenna is disposed within a radio frequency (RF) shielded chamber that is configured to receive a cellular device;
wherein the cellular device comprises an embedded subscriber identification module (eSIM); and
a processor programmed to, while the cellular device is in the shielded chamber, control the radio to use the antenna to:
transmit a subscriber identification module (SIM) profile to the cellular device, wherein the SIM profile includes a subscriber phone number and authentication information; and
subsequently use the RF-shielded chamber to simulate a cellular base station of a cellular communication system associated with the SIM profile to communicate with the cellular device via the cellular frequency radio to perform an authentication procedure that requires the cellular device to use the eSIM loaded with the SIM profile to test operation of the cellular device to verify that the cellular device has successfully loaded the SIM profile into the eSIM in order to subsequently communicate with the cellular communication system associated with the SIM profile after being removed from the RF-shielded chamber.