US Pat. No. 9,276,001

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor device comprising:
a substrate comprising at least two first pillars and at least two second pillars between the two first pillars;
a word line formed in the substrate between one of the at least two first pillars and one of the at least two second pillars;
an insulation material formed on the word line;
a digit line formed on an etch stop material;
the etch stop material formed on the insulating material and around the pillar, wherein the etch stop material comprises at
least two recesses and at least one protrusion between the at least two recesses, and a bottom of the recess is lower than
an upper surface of the pillar;

the protrusion covers the entire upper surface of the two second pillars between the two first pillars;
the recess exposes the upper surface of the first pillar;
the insulation material comprises silicon dioxide; and
the etch stop material comprises nitride.

US Pat. No. 9,128,716

MEMORY DEVICE AND CONTROL METHOD

NANYA TECHNOLOGY CORPORAT...

1. A memory device, comprising:
a delay locked loop module configured to generate a system clock signal when enabled by a control signal;
a memory bank module configured to read or write a plurality of data signals in accordance with the system clock signal and
a read command or a write command, wherein the memory bank module comprises a termination resistor; and

a control module configured to receive at least one control command to generate the control signal, wherein the control module
disables the delay locked loop module, when the memory bank module goes to a precharge mode or a powerdown mode, and the control
module disables the delay locked loop module after an adjustment to the termination resistor is completed.

US Pat. No. 9,245,844

PITCH-HALVING INTEGRATED CIRCUIT PROCESS AND INTEGRATED CIRCUIT STRUCTURE MADE THEREBY

NANYA TECHNOLOGY CORPORAT...

1. An integrated circuit (IC) structure, comprising:
a plurality of parallel conductive lines, arranged in a plurality of pairs;
a plurality of contact pads, each of which is connected with a conductive line at one end of the conductive line, wherein
the two contact pads of each pair of conductive lines form an opened loop, the opened loops are arranged at a first side and
a second side of the plurality of conductive lines alternately, and the opened loops at the first or second side are arranged
in a staggered manner.

US Pat. No. 9,229,463

VOLTAGE TRACKING CIRCUIT

NANYA TECHNOLOGY CORPORAT...

1. A voltage tracking circuit comprising:
a voltage generating device configured to provide a fixed voltage;
a first operational amplifier comprising a first input terminal configured to receive the fixed voltage, a second input terminal
coupled with a protected device model, and an output terminal;

a first voltage generator coupled with the output terminal of the first operational amplifier and a voltage limiter that is
coupled with devices under protection; and

a diode-connected device disposed in a feedback loop connecting the second input terminal of the first operational amplifier
and the first voltage generator.

US Pat. No. 9,207,733

DATA BUFFER SYSTEM AND POWER CONTROL METHOD

NANYA TECHNOLOGY CORPORAT...

1. A data buffer system, comprising:
a plurality of data buffer modules, wherein each of the data buffer modules comprises a plurality of buffers electrically
coupled in series; and

a plurality of switching units for supplying power to the buffers in accordance with a regulated voltage, wherein each of
the switching units is electrically coupled between a corresponding one of the buffers and a supply voltage,

wherein each of the buffers comprises an even number of the inverters electrically coupled in series, wherein each of the
inverters comprises a P-type transistor and an N-type transistor electrically coupled to the P-type transistor in cascade.

US Pat. No. 9,252,105

CHIP PACKAGE

NANYA TECHNOLOGY CORPORAT...

1. A chip package comprising at least one chip, the at least one chip comprising:
a substrate;
a chip circuit formed on the substrate;
a plurality of insulation layers formed on the substrate;
a chip selection terminal formed on the substrate or within the insulation layers and connecting to the chip circuit for enabling
the chip circuit;

a plurality of first conductors separated at different levels by the plurality of insulation layers;
a plurality of first vertical connections respectively connecting to the plurality of first conductors and extending to a
surface of the substrate opposite to the plurality of insulation layers;

a plurality of second vertical connections respectively connecting to the plurality of first conductors and extending to a
surface of the plurality of insulation layers opposite to the substrate;

a third vertical connection electrically connecting to the chip selection terminal and extending to the surface of the substrate;
a fourth vertical connection formed through the plurality of insulation layers and the substrate;
a second conductor formed on the surface of the plurality of insulation layers and connecting to the fourth vertical connection;
a plurality of first pads formed on the surface of the substrate and respectively connecting to the plurality of first vertical
connections, the third vertical connection and the fourth vertical connection; and

a plurality of second pads formed on the surface of the plurality of insulation layers and respectively connecting to the
plurality of second vertical connections.

US Pat. No. 9,053,815

CIRCUIT IN DYNAMIC RANDOM ACCESS MEMORY DEVICES

NANYA TECHNOLOGY CORPORAT...

1. A circuit in dynamic random access memory devices, comprising:
a command extension circuit configured to generate at least one multiple-cycle command signal by lengthening a single-cycle
command signal from a command decoding circuit;

wherein the command extension circuit further comprises:
a first flip-flop coupled to the command decoding circuit, a second flip-flop and a first Or circuit, wherein the first flip-flop
generates a first delay signal according to the single-cycle command signal from the command decoding circuit and sends the
first delay signal to the second flip-flop and the first Or circuit; and

a third flip-flop coupled to a second Or circuit, the second flip-flop and the first Or circuit, wherein the third flip-flop
generates a third delay signal according to a second delay signal from the second flip-flop and a reset signal from a second
Or circuit and sends the third delay signal to the first Or circuit;

wherein the second delay signal is generated by the second flip-flop according to the first delay signal and the reset signal;
wherein the reset signal is generated by the second Or circuit according to a burst length signal and an output signal of
a second And circuit;

wherein the output signal is generated by the second And circuit according to an A12 signal and a burst chop signal;
wherein the first Or circuit is configured to generate the multiple-cycle command signal to a delay lock loop (DLL) circuit
according to the first delay signal, the second delay signal, the third delay signal and the single-cycle command signal.

US Pat. No. 9,922,920

SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor package, comprising:
an interposer layer having a first surface and a second surface opposite to the first surface, wherein the interposer layer
comprises M first through interposer vias (TIVs) and a plurality of second through interposer vias embedded inside, and said
M first through interposer vias and the second through interposer vias extended from the first surface toward the second surface,
wherein said M first through interposer vias are patterned to form a plurality of repetitive polygonal-packing units, and
each of N of said M first through interposer vias is configured to be grouped within at least two distinct said polygonal-packing
units, wherein M and N are integer, and M>N, and each of the second through interposer vias is located within a center of
a corresponded one of the polygonal-packing units;

at least one first redistribution layer disposed on the first surface, the first redistribution layer comprising first terminals
formed on a surface of the first redistribution layer away from the interposer layer, wherein a first group of the first terminals
is connected to the corresponded first through interposer vias respectively, and a second group of the first terminals is
connected to the corresponded second through interposer vias respectively; and

at least one semiconductor chip having an active surface disposed on the first redistribution layer, wherein the active surface
is electrically connected to the first terminals respectively.

US Pat. No. 9,318,186

DRAM WORDLINE CONTROL CIRCUIT, DRAM MODULE AND METHOD OF CONTROLLING DRAM WORDLINE VOLTAGE

NANYA TECHNOLOGY CORPORAT...

1. A DRAM wordline voltage control circuit, comprising:
a sensing module configured to receive a first control signal and a feedback signal corresponding to a wordline voltage signal,
and generate a second control signal according to the first control signal and the feedback signal corresponding to the wordline
voltage signal, wherein the sensing module is further configured to set the second control signal enabled when the first control
signal is enabled and the feedback signal corresponding to the wordline voltage signal is smaller than a threshold voltage;

an oscillator electrically connected with the sensing module, the oscillator being configured to receive the second control
signal and output an oscillating signal when the second control signal is enabled; and

a charging pump electrically connected with the oscillator, the charging pump being configured to increase a voltage value
of the wordline voltage signal when the oscillator outputs the oscillating signal.

US Pat. No. 9,111,931

METHOD OF FORMING AN INTERCONNECT STRUCTURE WITH HIGH PROCESS MARGINS

NANYA TECHNOLOGY CORPORAT...

1. An interconnect structure, comprising:
a substrate;
a first insulating layer disposed over the substrate, wherein the first insulating layer has a plurality of via holes filled
with a first conductive material;

a second insulating layer disposed over the first insulating layer, wherein the second insulating layer has a plurality of
trenches filled with a second conductive material without the first conductive material;

a first mask layer disposed between the first insulating layer and the second insulating layer, wherein the first mask layer
has a plurality of openings connecting the plurality of via holes and the plurality of trenches; and

wherein the plurality of via holes are self-aligned with the plurality of trenches.

US Pat. No. 9,984,987

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor structure, comprising:a substrate including a first surface and a second surface opposite to the first surface;
a pad disposed over the first surface;
a first passivation disposed over the first surface and partially covering the pad; and
a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line;
wherein the conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, the land portion includes a plurality of first protrusions protruded away from the first passivation, and
wherein the land portion includes a plurality of second protrusions protruded towards the substrate and surrounded by the first passivation.

US Pat. No. 9,438,034

TRANSIENT VOLTAGE SUPPRESSOR

NANYA TECHNOLOGY CORPORAT...

1. A transient voltage suppressor, comprising: N first transistors, respectively having N bases which are directly connected
to a reference power line, N emitters which are directly connected to a reference ground, and N collectors which are directly
connected to N pads respectively, wherein the first transistors are controlled by a voltage on the reference power line; and
N semiconductor units, coupled between the reference ground and the N pads respectively, or coupled between the reference
power line and the N pads respectively, N is a positive integer;
wherein the semiconductor units are respectively N second transistors, and the second transistors are coupled between the
N pads respectively and the reference power line, the second transistors are controlled by the reference ground;

wherein a type of the first transistors and a type of the second transistor are the same,
wherein the first transistors and the second transistors are PNP bipolar transistors.

US Pat. No. 9,324,721

PITCH-HALVING INTEGRATED CIRCUIT PROCESS

NANYA TECHNOLOGY CORPORAT...

1. A pitch-halving integrated circuit (IC) process, comprising:
forming, over a substrate, a plurality of parallel base line patterns each of which is connected with a hammerhead pattern
at a first side or a second side of the plurality of base line patterns, wherein the hammerhead patterns are arranged at the
first side and the second side alternately, and the hammerhead patterns at the first or second side are arranged in a staggered
manner;

trimming each base line pattern and each hammerhead pattern;
forming, on sidewalls of each trimmed base line pattern and the corresponding trimmed hammerhead pattern as a spacer, a pair
of derivative line patterns, a loop pattern around the trimmed hammerhead pattern, and a turning pattern at an end of the
trimmed base line pattern without the corresponding trimmed hammerhead pattern;

removing the trimmed base line patterns and the trimmed hammerhead patterns; and
removing a portion of each loop pattern and at least a portion of each turning pattern to disconnect each pair of derivative
line patterns, such that each remaining loop pattern includes two contact pad patterns.

US Pat. No. 9,305,902

CHIP PACKAGE AND METHOD FOR FORMING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A method for forming a chip package comprising:
forming a first lower vertical connection, a plurality of second lower vertical connections and a third lower vertical connection
in a substrate of at least one semiconductor device;

forming a chip select terminal and a plurality of chip select pads on the substrate, wherein the chip select terminal connects
to the first lower vertical connection, and wherein the plurality of chip select pads correspondingly connect to the plurality
of second lower vertical connections;

forming an insulation layer on the substrate;
forming a plurality of upper vertical connections in the insulation layer, wherein the plurality of upper vertical connections
correspondingly connect to the plurality of chip select pads and the third lower vertical connection, and in which the third
lower vertical connection and a corresponding one of the upper vertical connections form a vertical through connection that
goes straight through the substrate and the insulation layer;

forming a plurality of conductors on the insulation layer, wherein the plurality of conductors correspondingly connect to
the plurality of upper vertical connections and the vertical through connection; and

forming an insulation pad on one of the plurality of conductors, wherein the one of the plurality of conductors on which the
insulation pad is formed connects with the vertical through connection,

wherein the first lower vertical connection, the plurality of second lower vertical connections and the third lower vertical
connection are arranged in two dimensions, and

wherein a maximum width of the insulation pad is substantially the same as a maximum width of the vertical through connection.

US Pat. No. 9,286,967

METHOD FOR CLOCK CONTROL IN DYNAMIC RANDOM ACCESS MEMORY DEVICES

NANYA TECHNOLOGY CORPORAT...

1. A method for clock control in dynamic random access memory devices, comprising the steps of:
transitioning a logic level according to availability of an active zone of a dQ-Enable-Delay (QED) shifter stack, or whether
a gap command signal is received;

calculating the logic level with a logic level of a clock signal for generating a result;
wherein the calculated logic level is configured to enable the clock signal according to the result, wherein the result is
a first result; and

wherein the calculated logic level is configured to disable the clock signal according to the result, wherein the result is
a second result.

US Pat. No. 9,240,381

CHIP PACKAGE AND METHOD FOR FORMING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A chip package comprising:
at least one semiconductor device, wherein the at least one semiconductor device comprises:
a die having a die circuit and a substrate;
a chip select terminal formed on the substrate and electrically connecting to the die circuit;
a plurality of chip select pads formed on the substrate and electrically isolated from the die circuit;
a first lower vertical connection formed through the substrate and connecting to the chip select terminal;
a plurality of second lower vertical connections formed through the substrate and correspondingly connecting to the plurality
of chip select pads;

an insulation layer formed on the substrate;
a plurality of upper vertical connections formed through the insulation layer and correspondingly connecting to the plurality
of chip select pads;

a vertical through connection that goes straight through the substrate and the insulation layer;
a plurality of conductors formed on the insulation layer, wherein each of the plurality of conductors connects to a corresponding
one of the plurality of upper vertical connections and the vertical through connection and extends to a location above a corresponding
one of the first lower vertical connection and the plurality of second lower vertical connections; and

an insulation pad formed on one of the plurality of conductors, wherein the one of the plurality of conductors on which the
insulation pad is formed connects with the vertical through connection,

wherein the first lower vertical connection, the plurality of second lower vertical connections and the vertical through connection
are arranged in two dimensions, and

wherein a maximum width of the insulation pad is substantially the same as a maximum width of the vertical through connection.

US Pat. No. 9,134,628

OVERLAY MARK AND APPLICATION THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A method of checking alignment accuracy between a former layer and a later layer on a wafer, comprising:
providing an overlay mark, the overlay mark comprises:
at least one former pattern, as a part of the former layer, having two parallel opposite edges each forming a sharp angle
? with an x-axis of the wafer; and

at least one later pattern as a part of a patterned photoresist layer defining the later layer, having two parallel opposite
edges each forming the sharp angle ? with the x-axis of the wafer, wherein the at least one later pattern does not overlay
the at least one former pattern, and the at least one later pattern and the at least one former pattern are parallel;

determining, along a direction perpendicular to the parallel opposite edges of the at least one later pattern, a shift ?L
of the at least one later pattern from a predetermined position where the at least one later pattern would be if no overlay
error is present; and

calculating, from the shift ?L, an x-directional overlay error as ?L·sin? and a y-directional overlay error as ?L·cos?,
wherein the at least one former pattern comprises two former patterns that comprise a first pattern and a second pattern,
the at least one later pattern comprises two later patterns that comprises a third pattern and a fourth pattern,
the first pattern and the third pattern are disposed in a pair,
the second pattern and the fourth pattern are disposed in a pair, and
the third pattern and the fourth pattern are disposed between the first pattern and the second pattern.

US Pat. No. 9,111,599

MEMORY DEVICE

NANYA TECHNOLOGY CORPORAT...

1. A memory device, comprising:
a training circuit;
a data strobe transmission path comprising:
a first input path having a first input connected to the training circuit and an external data strobe signal source; and
a tree circuit connected to a first output of the first input path;
a plurality of data transmission paths each comprising:
a second input path having a second input connected to an external data signal source, and the second input of the second
input path of at least one of the data transmission paths is further connected to the training circuit; and

an adjustable delay circuit connected to a second output of the second input path;
a plurality of data latching circuits each connected to outputs of the adjustable delay circuit of one of the data transmission
paths and the tree circuit;

a phase detection circuit connected to the outputs of the adjustable delay circuit of at least one of the data transmission
paths and the tree circuit; and

wherein when the memory device is under a training mode, a training process is performed on at least one of the data transmission
paths such that the training circuit is activated to generate a training clock signal to both of the first input path and
the second input path and further to the tree circuit and the adjustable delay circuit to generate a first clock signal and
a second clock signal respectively, wherein the phase detection circuit detects a phase difference between the first clock
signal and the second clock signal to adjust a delay time of the adjustable delay circuit until the first clock signal and
the second clock signal are in phase;

wherein when the memory device is under an operation mode, the training circuit is deactivated such that the first input path
receives an external data strobe signal to generate a data strobe signal to the tree circuit and the second input path receives
an external data signal to generate a data signal to the adjustable delay circuit, wherein each of the data latching circuits
receives a treed data strobe signal from the tree circuit to latch a delayed data signal received from the adjustable delay
circuit of one of the data transmission paths.

US Pat. No. 10,076,034

ELECTRONIC STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. An electronic structure, comprising:a first board structure;
a first contact pad disposed on the first board structure;
a first joint member disposed on the first contact pad, wherein the first joint member has a first Young's modulus;
a second joint member disposed on the first joint member, wherein the second joint member has a second Young's modulus, and the second Young's modulus is greater than the first Young's modulus; and
a third joint member in contact with the second joint member, wherein the third joint member has a third Young's modulus, and the second Young's modulus is greater than the third Young's modulus.

US Pat. No. 9,831,155

CHIP PACKAGE HAVING TILTED THROUGH SILICON VIA

Nanya Technology Corporat...

1. A chip package comprising at least one integrated circuit die, the at least one integrated circuit die comprising:
a substrate portion having an internal plane between a front side and a back side;
an electrical interconnect portion contacting the front side of the substrate portion;
a plurality of first connection terminals on an upper surface of the electrical interconnect portion;
a plurality of second connection terminals on the back side of the substrate portion;
a plurality of connection wirings electrically connecting the first connection terminals and the second connection terminals;
a chip selection terminal between the internal plane of the substrate portion and the upper surface of the electrical interconnect
portion; and

a chip selection wiring connected to the chip selection terminal and one of the second connection terminals and the first
connection terminals;

wherein at least one of the chip selection wiring and the plurality of connection wirings comprises a tilted portion with
respect to the back side of the substrate portion.

US Pat. No. 9,264,029

CLOCK CYCLE COMPENSATOR AND THE METHOD THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A clock cycle compensator, comprising:
an input buffer for generating an input reference clock signal;
an output buffer for generating a system clock signal;
a delay lock loop electrically connected between the input buffer and the output buffer, wherein the delay lock loop is configured
for locking a duty cycle center of a duty cycle range of the system clock signal;

a duty cycle controlling module, comprising:
a duty cycle detection unit for detecting a current system duty cycle of the system clock signal; and
a duty cycle compensation unit for determining a duty cycle correction amount according to a gap between the current system
duty cycle and a target duty cycle, the duty cycle compensation unit generating a compensation signal according to whether
the duty cycle correction amount exceeds a threshold amount or not; and

a bimodal polarity control unit for changing a polarity of the input reference clock signal on the input buffer according
to the compensation signal,

wherein the bimodal polarity control unit toggles the polarity of the input reference clock signal when the duty cycle correction
amount remains within the threshold amount, and the threshold amount is other than 0.

US Pat. No. 9,147,642

INTEGRATED CIRCUIT DEVICE

NANYA TECHNOLOGY CORPORAT...

1. An integrated circuit device, comprising:
a substrate having at least one via passing therethrough;
at least one transistor at least partially disposed in the substrate;
at least one metal layer disposed on or above the substrate;
a conductive pillar disposed in the via; and
a connecting structure at least partially disposed in the via and connecting the conductive pillar and the metal layer, wherein
a diameter of the conductive pillar is substantially the same as a diameter of the connecting structure, the entire connecting
structure is made of a stress releasing material having a coefficient of thermal expansion less than a coefficient of thermal
expansion of the conductive pillar, a projection of the transistor in the via overlaps with the connecting structure, and
the connecting structure comprises:

a first portion made of oxide; and
a second portion connecting the conductive pillar and the metal layer, and the second portion is made of a conductive material.

US Pat. No. 9,059,142

SEMICONDUCTOR DEVICE HAVING VERTICAL GATES AND FABRICATION THEREOF

Nanya Technology Corporat...

1. A method for forming a semiconductor device with a vertical gate, comprising:
providing a substrate;
forming a recess in the substrate;
forming a gate dielectric layer on a sidewall and a bottom of the recess;
forming a polysilicon layer on the substrate;
after forming of the polysilicon layer on the substrate, forming source/drain regions in the polysilicon layer, wherein the
substrate is separated from the source/drain regions by the gate dielectric layer;

forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride
layer; and

forming a gate layer in the recess and on the adhesion layer.

US Pat. No. 9,812,414

CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A chip package comprising:
a first substrate;
a first insulation layer disposed over the first substrate;
a conductive structure disposed within the first insulation layer;
a buffering member embedded into the first insulation layer;
a redistribution layer (RDL) electrically connected with the conductive structure and disposed over the conductive structure
and the buffering member; and

a second insulation layer disposed over the RDL, wherein a portion of the RDL is exposed from the second insulation layer
and disposed over the buffering member,

wherein a width of the buffering member is substantially equal to a width of the portion of the RDL exposed from the second
insulation layer,

wherein a thickness of the buffering member is about 0.05 ?m to about 5 ?m, and
wherein the buffering member includes elastic, flexible or soft material.

US Pat. No. 9,362,254

WIRE BONDING METHOD AND CHIP STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A package structure, comprising:
a substrate comprising a first surface and at least one metal finger disposed on the first surface;
a first chip disposed on the first surface and comprising a first active surface and at least one first bonding pad disposed
on the first active surface;

at least one metal ball bump disposed on the corresponding metal finger respectively;
at least one first wire connected between the corresponding metal ball bump and the corresponding first bonding pads respectively;
and

at least one first free air ball connected to the corresponding first wire and disposed on the corresponding first bonding
pad respectively, such that the first wire is located between the corresponding first free air ball and the corresponding
first bonding pad, wherein the first wire and the first free air ball connecting thereto are integrally formed.

US Pat. No. 9,354,274

CIRCUIT TEST SYSTEM ELECTRIC ELEMENT MEMORY CONTROL CHIP UNDER DIFFERENT TEST MODES

NANYA TECHNOLOGY CORPORAT...

1. A circuit test system, comprising:
a circuit test apparatus providing a first clock signal; and
a circuit to be tested coupled to the circuit test apparatus, wherein the circuit to be tested comprising:
a plurality of input/output pads, wherein at least two first input/output pads of the input/output pads are connected to each
other to form a first test loop during a first test mode;

at least one first clock pad receiving the first clock signal; and
at least one second clock pad connected to at least one second input/output pad of the input/output pads to form a second
test loop during a second test mode,

wherein the circuit to be tested multiplies a frequency of the first clock signal to generate a second clock signal, and the
first test loop of the circuit to be tested is tested based on the second clock signal during the first test mode, and the
first test loop and the second test loop of the circuit to be tested are tested based on the second clock signal during the
second test mode,

wherein during the second test mode, a read clock is generated based on the second clock signal, outputted from a clock generation
unit, and transmitted through a data register unit, a transmission unit of one of the at least two first input/output pads,
the at least two first input/output pads, and a reception unit of another one of the at least two first input/output pads
in the first test loop, and back to the data register unit,

wherein during the second test mode, the read clock is outputted from the clock generation unit, and transmitted through the
data register unit, the transmission unit of the at least one second input/output pad, the at least one second input/output
pad, the at least one second clock pad, and a reception unit of the at least one second clock pad in the second test loop,
and back to the clock generation unit.

US Pat. No. 9,087,604

PRE-CHARGING METHOD APPLIED IN DYNAMIC RANDOM ACCESS MEMORIES

NANYA TECHNOLOGY CORPORAT...

1. A pre-charging method applied in dynamic random access memories (DRAM), comprising:
disabling wordlines in an active array;
equilibrating digital lines in the active array and an reference array to half of a power supply voltage;
disabling wordlines in the reference array; and
pre-charging the digital lines in the active array and the reference array to the power supply voltage.

US Pat. No. 10,037,937

METHOD FOR FORMING SEMICONDUCTOR PACKAGE

NANYA TECHNOLOGY CORPORAT...

1. A method for forming semiconductor packages comprising:providing an interposer layer having a first surface and a second surface opposite to the first surface, wherein the interposer layer comprises M first through interposer vias (TIVs) embedded inside, and said M first through interposer vias extended from the first surface toward the second surface, wherein said M first through interposer vias are patterned to form a plurality of repetitive polygonal-packing units, and each of N of said M first through interposer vias is configured to be grouped within at least two distinct said polygonal-packing units, wherein M and N are integer, and M>N;
forming at least one first redistribution layer on the first surface to form a plurality of first terminals on a surface of the first redistribution layer away from the interposer layer, wherein the plurality of first terminals are selectively connected to the corresponded first through interposer vias respectively; and
disposing at least one semiconductor chip on the first redistribution layer, wherein the semiconductor chip comprises an active surface electrically connected to the plurality of first terminals respectively, wherein the interposer layer further comprises a plurality of second through interposer vias embedded inside thereof and extended from the first surface toward the second surface, each of the second through interposer vias is located within a center of a corresponded one of the polygonal-packing units, a first group of the plurality of first terminals is connected to the corresponded first through interposer vias respectively, and a second group of the plurality of first terminals is connected to the corresponded second through interposer vias respectively.

US Pat. No. 9,704,818

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Nanya Technology Corporat...

1. A semiconductor structure comprising:
a substrate;
a pad disposed over the substrate;
a passivation disposed over the substrate and exposing a portion of the pad; and
a bump disposed over the portion of the pad;
wherein the bump includes a buffering member disposed over the portion of the pad, and a conductive layer surrounding the
buffering member and electrically connected to the pad;

wherein a portion of the buffering member is disposed within or extended into the pad.

US Pat. No. 9,508,673

WIRE BONDING METHOD

NANYA TECHNOLOGY CORPORAT...

1. A wire bonding method, comprising:
providing a substrate comprising at least one metal finger;
disposing a first chip on the substrate and the first chip comprising at least one first boding pad;
forming a metal ball bump on the corresponding metal finger;
forming a first wire from the metal ball bump toward the corresponding first boding pad;
forming a first free air ball on the first wire by electronic flame-off process; and
pressing the first free air ball connected to the first wire on the corresponding first boding pad, such that the first wire
is located between the first free air ball and the corresponding first boding pad.

US Pat. No. 9,263,317

METHOD OF FORMING BURIED WORD LINE STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A method of forming a buried word line structure, comprising:
sequentially forming a first mask layer, an interlayer and a second mask layer on a substrate, wherein the second mask layer
has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps comprises first gaps and second
gaps arranged alternately;

forming a dielectric pattern in each first gap and simultaneously forming spacers on sidewalls of each second gap, wherein
during the step of forming the dielectric patterns and the spacers, a first trench is formed between the adjacent spacers
and exposes a portion of the first mask layer;

removing the mask patterns to form second trenches; and
performing an etching process by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened
to the substrate and the second trenches are deepened to the first mask layer,

wherein the second trenches are deepened with a greater etching rate than the first trenches.

US Pat. No. 9,147,604

MEMORY PROCESS

NANYA TECHNOLOGY CORPORAT...

1. A memory process, comprising:
providing a substrate, wherein the substrate has therein a plurality of trenches and a plurality of conductive lines buried
in the trenches and has thereon an array area, and each of the conductive lines has an array portion in the array area;

defining a contact area apart from the array area on the substrate, wherein each of the conductive lines has a contact portion
in the contact area;

etching the substrate between the contact portions of the conductive lines down to below tops of the conductive layers to
form a plurality of gaps between the contact portions of the conductive lines; and

filling the gaps with an insulating layer.

US Pat. No. 9,054,131

VERTICAL MOSFET ELECTROSTATIC DISCHARGE DEVICE

Nanya Technology Corporat...

1. A vertical MOSFET electrostatic discharge device, comprising:
a substrate comprising a plurality of trenches;
a recessed gate, wherein the recessed gate is comb-shaped from a top view and comprises a plurality of teeth, and wherein
each of the plurality of teeth is disposed in a respective one of the plurality of trenches;

a plurality of drain regions, wherein in each of the plurality of drain regions is disposed between a neighboring two of the
teeth, and each of the plurality of drain regions is doped with first type dopants;

a plurality of electrostatic discharge implant regions, wherein each of the plurality of electrostatic discharge implant regions
is disposed under a respective one of the plurality of drain regions and comprises a bottom side and a vertical side; and

a source region surrounding and disposed under the plurality of teeth and the plurality of electrostatic discharge implant
regions, wherein the source region directly contacts the bottom side of each of the plurality of electrostatic discharge implant
regions without contacting the vertical side thereof.

US Pat. No. 10,026,690

FUSE BLOWING METHOD AND FUSE BLOWING SYSTEM

NANYA TECHNOLOGY CORPORAT...

1. A fuse blowing method, comprising:receiving a number signal, wherein the number signal comprises a number;
triggering the number of a plurality of fuse pumps according to the number signal; and
generating a current to blow a fuse.

US Pat. No. 9,786,593

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

NANYA TECHNOLOGY CORPORAT...

12. A method for forming a semiconductor device, the method comprising:
receiving a substrate comprising a back side and a front side having a conductor thereon;
forming a via hole in the substrate and exposing the conductor;
forming a groove extending from the back side into the substrate without penetrating the front side, and arranging the groove
surrounding the via hole;

forming a first material layer in the via hole;
forming a second material layer in the groove; and
forming an under bump metallization (UBM) on the second material layer, wherein a bottom surface of the UBM and top surfaces
of the first material layer and the second material layer are coplanar.

US Pat. No. 9,711,442

SEMICONDUCTOR STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor structure, comprising:
an electronic component; and
a board structure, comprising:
a dielectric layer structure having a mount region and a peripheral region surrounding the mount region, wherein the electronic
component is disposed on the mount region, and the peripheral region has at least one first through hole; and

at least one elastomer disposed in the first through hole.

US Pat. No. 9,076,558

MEMORY TEST SYSTEM AND MEMORY TEST METHOD

NANYA TECHNOLOGY CORPORAT...

1. A memory test system, for testing a memory unit, comprising:
a control unit, generating and outputting a first read command and a first write command according to an external command;
a data reading channel, coupled to the memory unit and the control unit and reading data from the memory unit according to
the first read command;

a data writing channel, coupled to the memory unit and the control unit and writing the data to the memory unit according
to the first write command; and

a test channel, coupled to the data reading channel and the data writing channel, and having an input end and an output end,
wherein the input end receives the data from the data reading channel, and the output end transmits the data back to the data
writing channel, the data writing channel receives the data after a time delay,

wherein when each time the external command is received by the control unit, the first read command and the first write command
are generated and respectively outputted to the data reading channel and the data writing channel, the data reading channel
receives the first read command at a first time before the data writing channel receives the first write command at a second
time, a time interval between the first time and the second time is substantially equal to the time delay, and the time interval
comprises a generation time of the first write command by the control unit and a programmable offset time.

US Pat. No. 9,054,113

BOX-IN-BOX OVERLAY MARK

NANYA TECHNOLOGY CORPORAT...

1. A box-in-box overlay mark, comprising
an inner box region and an outer box region surrounding the inner box region;
dense narrow trenches in a previous layer in the inner box region and the outer box region, wherein at least the dense narrow
trenches in the inner box region are orientated in a direction different from an x- or y-direction;

a plurality of x-directional and y-directional linear photoresist patterns defining a rectangle over the dense narrow trenches
in the inner box region, wherein the linear photoresist patterns are defined in or from a photoresist layer for defining a
current layer, and each of the linear photoresist pattern is wider than each of the dense narrow trenches; and

a plurality of x-directional and y-directional linear patterns defining another rectangle in the outer box region, wherein
the linear patterns are defined in or from the previously layer, and each of the linear patterns is wider than each of the
dense narrow trenches.

US Pat. No. 10,062,620

HOUSING ASSEMBLY AND MEMORY DEVICE

Nanya Technology Corporat...

15. A memory device, comprising:a housing assembly, including:
a housing, including:
a bulk assembly, including:
a conductive bulk defining a first hole in the conductive bulk, wherein a voltage level of the conductive bulk is kept at a reference ground; and
an insulating bulk, integrated with the conductive bulk, defining a second hole in the insulating bulk; and
an insulating layer on the conductive bulk;
a first pin, in the first hole and insulated from the conductive bulk by the insulation layer, wherein the first pin is configured to transmit a data signal; and
a second pin, in the second hole and in contact with the insulation bulk, wherein the second pin is configured to transmit a data signal,
wherein the number of pins functioning to transmit data signals and surrounding the first pin is greater than the number of pins surrounding the second pin.

US Pat. No. 9,960,146

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor structure, comprising:a first stacking interposer, comprising:
a first interposer having a first surface and a second surface opposite thereto;
a plurality of first conductive pillars penetrating through the first interposer from the first surface to the second surface;
a plurality of first bumps disposed at a side of the first surface of the first interposer and electrically connected to the first conductive pillars, wherein the first surface has a clearance region where is free of the first bumps and the clearance region is level with the side of the first surface;
a conductive pad extending on the first surface and bridging two adjacent ones of the first conductive pillars, wherein the conductive pad covers the two adjacent ones of the first conductive pillars and is interposed between the two adjacent ones of the first conductive pillars and one of the first bumps; and
a first redistribution layer disposed on the second surface of the first interposer;
a first chip disposed over the first redistribution layer, wherein the first chip is aligned with the clearance region of the first surface of the first interposer in a direction perpendicular to the first surface; and
a plurality of second bumps interconnecting the first redistribution layer with the first chip.

US Pat. No. 9,659,886

METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING VOIDS BETWEEN TOP METAL LAYERS OF METAL INTERCONNECTS

NANYA TECHNOLOGY CORPORAT...

1. A method of fabricating a semiconductor device, comprising:
providing a substrate, the substrate comprising a non-device region and a device region;
forming a dielectric layer on the non-device region and the device region;
forming a first metal interconnect in the dielectric layer of the non-device region, wherein the first metal interconnect
comprises a plurality of first top metal layers;

forming a buffer layer on the dielectric layer of the device region, wherein the buffer layer comprises a metal, metal nitride,
or a combination thereof;

forming a conductive layer on the dielectric layer;
patterning the conductive layer to form a dummy bonding pad, a bonding pad, and a redistribution layer, wherein the dummy
bonding pad is on the non-device region and is electrically connected to the first metal interconnect, the bonding pad is
on the buffer layer of the device region, and the redistribution layer connects the dummy bonding pad and the bonding pad;
and

forming a second metal interconnect in the dielectric layer below the bonding pad of the device region, wherein the second
metal interconnect is not directly connected to the bonding pad, the second metal interconnect comprises a plurality of second
top metal layers, a plurality of first voids are in a plurality of gaps between the first top metal layers and a plurality
of second voids are in a plurality of gaps between the second top metal layers, and a number of the second voids is greater
than a number of the first voids.

US Pat. No. 9,418,949

SEMICONDUCTOR DEVICE HAVING VOIDS BETWEEN TOP METAL LAYERS OF METAL INTERCONNECTS

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor device, comprising:
a substrate comprising a non-device region and a device region, wherein no semiconductor electronic device is disposed in
the non-device region;

a dielectric layer on the non-device region and the device region;
a dummy bonding pad on the dielectric layer of the non-device region;
a first metal interconnect in the dielectric layer of the non-device region and directly connected to the dummy bonding pad,
the first metal interconnect comprises a plurality of first top metal layers;

a bonding pad on the dielectric layer of the device region;
a second metal interconnect in the dielectric layer below the bonding pad of the device region, the second metal interconnect
is not directly connected to the bonding pad, the second metal interconnect comprises a plurality of second top metal layers,
a plurality of first voids are between a plurality of gaps between the first top metal layers and a plurality of second voids
are in a plurality of gaps between the second top metal layers, and a number of the second voids is greater than a number
of the first voids;

a buffer layer between the bonding pad and the dielectric layer, wherein the buffer layer comprises a metal, metal nitride,
or a combination thereof; and

a redistribution layer on the dielectric layer, wherein the redistribution layer connects the dummy bonding pad and the bonding
pad.

US Pat. No. 9,153,665

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor device, comprising:
a plurality of pillars disposed on a substrate, wherein a plurality of trenches are formed around each pillar;
a plurality of doped regions, wherein each doped region is disposed at a bottom of each pillar;
a plurality of insulation layers, wherein each insulation layer is disposed below each doped region; and
a shielding layer disposed in the trenches, wherein the shielding layer is electrically connected to the substrate.

US Pat. No. 9,123,784

MEMORY PROCESS AND MEMORY STRUCTURE MADE THEREBY

NANYA TECHNOLOGY CORPORAT...

1. A memory structure, comprising:
a substrate, having therein a plurality of trenches, and having thereon an array area and a contact area apart from the array
area, wherein each trench has a first portion in the contact area and a second portion in the array area, and the substrate
between the first portions of the trenches is also in the contact area and has a surface lower than a surface of the substrate
between the trenches outside of the contact area;

a plurality of conductive lines, each buried in a trench and having an array portion in the array area and a contact portion
in the contact area, wherein the contact portion is protruding above the lower surface of the substrate between the first
portions of the trenches in the contact area; and

an insulating layer, filling in gaps between protruding parts of the contact portions of the conductive lines in the contact
area.

US Pat. No. 10,049,719

VOLTAGE SYSTEM AND METHOD FOR OPERATING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A voltage system of a DRAM, comprising:a first regulator;
a second regulator; and
a control device configured to determine the amount of regulators required based on an operation mode which the DRAM is instructed to operate under, and, based on the determination, receive an active instruction and a first instruction so as to pass the active instruction to the first regulator and the second regulator and enable the first regulator and the second regulator, or receive the active instruction and a second instruction so as to pass the active instruction to one of the first regulator and the second regulator and enable one of the first regulator and the second regulator, which receives the active instruction, and disable the remaining regulator, wherein the amount of the enabled regulators is equal to the determined amount of regulators required,
wherein the one or more enabled regulators provide a current which serves as an operation current of a bank of the DRAM.

US Pat. No. 9,905,549

SEMICONDUCTOR APPARATUS AND METHOD FOR PREPARING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor apparatus, comprising:
a semiconductor logic die having a first active surface and an internal conductive element extending from the first active
surface to a back surface of the semiconductor logic die;

a semiconductor memory die stacked onto the semiconductor logic die, wherein the first active surface of the semiconductor
logic die faces a second active surface of the semiconductor memory die;

a bump structure electrically connecting a first terminal on the first active surface to a second terminal on the second active
surface; and

a conductive plug penetrating the molding member.

US Pat. No. 9,831,303

CAPACITOR STRUCTURE AND PROCESS FOR FABRICATING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A capacitor structure, comprising:
a substrate;
a bottom electrode, disposed on the substrate and having a substantially perpendicular tube shape with a substantially uniform
thickness, and comprising at least one first wider portion and at least one first narrower portion that are arranged alternately
in a perpendicular direction, wherein the at least one first wider portion and the at least one first narrower portion are
connected by a slant portion and the at least one first wider portion is located below the at least one first narrower portion,
wherein sidewalls of the at least one first wider portion and the at least one first narrower portion are perpendicular with
respect to a top surface of the substrate;

a top electrode;
a dielectric layer between the bottom electrode and the top electrode, wherein the dielectric layer is in direct contact with
the at least one first wider portion and the at least one first narrower portion of the bottom electrode; and

a cap layer, surrounding a topmost portion of the bottom electrode, so that a topmost surface of the bottom electrode is coplanar
with a top surface of the cap layer, wherein the top electrode covers the top surface, a bottom surface and sidewalls of the
cap layer, and the dielectric layer is in direct contact with the top surface and the bottom surface of the cap layer, wherein
a thickness of the cap layer is less than a length of the at least one first narrower portion perpendicular with respect to
the top surface of the substrate.

US Pat. No. 9,653,401

METHOD FOR FORMING BURIED CONDUCTIVE LINE AND STRUCTURE OF BURIED CONDUCTIVE LINE

NANYA TECHNOLOGY CORPORAT...

1. A structure of a buried conductive line, comprising:
a semiconductor substrate, having a trench therein and a contact area thereon, wherein the trench has an end portion in the
contact area;

a conductive layer filled in the trench, wherein a top of the conductive layer in the end portion of the trench is higher
than a top of the conductive layer not in the end portion of the trench;

a cap layer located in the trench, wherein the cap layer only covers the top of the conductive layer not in the end portion
of the trench,

wherein a bottom of the conductive layer located in the contact area and not located in the contact area has a substantially
constant bottom level,

wherein the conductive layer located in the contact area contacts the conductive layer not located in the contact area;
a dielectric layer covering the semiconductor substrate and the conductive layer;
at least one contact window in the dielectric layer and on the conductive layer in the end portion of the trench, wherein
the at least one contact window is located in the contact area; and

an insulating layer in a bottom of the trench separating the conductive layer from the semiconductor substrate, and in a side
of the trench separating the conductive layer from the semiconductor substrate.

US Pat. No. 9,214,926

THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A three dimensional integrated circuit, comprising:
a master circuit configured to receive and process an input data, a data strobe signal (DQS) and an input command to output
a writing data signal to a master die, wherein the master circuit comprises:

a latch circuit configured to receive the input data and the DQS and output a data signal based on the input data and the
DQS;

a serial to parallel data conversion circuit configured to convert the data signal from a serial data into a parallel data;
a command decoder configured to decode the input command and output a command signal;
a writing command controller configured to receive and process the command signal to output a write control signal;
a writing timing generation circuit configured to receive and process the write control signal and the DQS to output a data
release signal; and

a data driver configured to receive and process the data signal and the data release signal to output the writing data signal
to the master die;

a slave circuit; and
a through-silicon via (TSV) electrically coupled between the master circuit and the slave circuit;
wherein the master circuit is configured to transfer the writing data signal to a slave die through the TSV.

US Pat. No. 10,019,350

DRAM AND METHOD FOR ACCESSING A DRAM

Nanya Technology Corporat...

1. A dynamic random access memory (DRAM), comprising:a normal area including a plurality of memory cells controllable by a normal word line and configured to store a data;
a hot area including a plurality of memory cells controllable by a hot word line;
a control device configured to copy the data stored in the memory cells associated with the normal word line which has been frequently accessed into the memory cells associated with the hot word line before a condition, of an access frequency of the normal word line reaching a first threshold frequency, is satisfied; to access the normal word line before the condition is satisfied; to access the hot word line associated with the copied data only if the condition is satisfied; to no longer access the data from the normal word line only if the condition is satisfied
wherein the controller is further configured to access the normal word line if the access frequency of the normal word line does not reach a second threshold frequency; and to access the hot word line if the access frequency of the normal line reaches the second threshold frequency.

US Pat. No. 9,881,867

CONDUCTIVE CONNECTION STRUCTURE HAVING STRESS BUFFER LAYER

NANYA TECHNOLOGY CORPORAT...

1. A conductive connection structure, comprising:
a semiconductor substrate;
a conductive pillar in the semiconductor substrate;
a stress buffer layer between the semiconductor substrate and the conductive pillar, wherein the conductive pillar has a protruding
portion penetrating through the stress buffer layer, and

a dielectric layer between the stress buffer layer and the semiconductor substrate, wherein the protruding portion of the
conductive pillar is in direct contract with the dielectric layer.

US Pat. No. 9,799,624

WIRE BONDING METHOD AND WIRE BONDING STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A wire bonding method, comprising:
forming a Free Air Ball (FAB) at an end of a metal wire;
pressing the FAB onto a flat surface of a metal finger on a substrate to deform the FAB;
contacting the deformed FAB to a metal pad on the substrate, wherein the metal pad is made of a first material and the metal
wire is made of a second material, and a hardness of the first material is smaller than a hardness of the second material;
and

bonding the deformed FAB on the metal pad to make a portion of the deformed FAB sink into the metal pad.

US Pat. No. 9,664,852

OPTICAL WAVEGUIDE HAVING SEVERAL DIELECTRIC LAYERS AND AT LEAST ONE METAL CLADDING LAYER

NANYA TECHNOLOGY CORPORAT...

1. A waveguide, comprising:
a substrate;
a plurality of cladding layers present on the substrate and defining at least one tunnel therein, at least one of the cladding
layers being made of metal;

a first dielectric layer disposed in the tunnel and having a first refractive index N1;
a second dielectric layer disposed in the tunnel and having a second refractive index N2; and
a third dielectric layer disposed in the tunnel and having a third refractive index N3, and N2>N1 and N2>N3, wherein the second
dielectric layer is present between the first and third dielectric layers, wherein at least one of the cladding layers is
present between the substrate and the first dielectric layer and protrudes toward the tunnel and away from the substrate,
a portion of the first dielectric layer protrudes away from the substrate, and the second and third dielectric layers are
conformal to the first dielectric layer.

US Pat. No. 9,318,412

METHOD FOR SEMICONDUCTOR SELF-ALIGNED PATTERNING

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor self-aligned structure, comprising:
a carrier;
a first pattern with a first feature size that is positioned above the carrier, wherein the first feature size is a space
between adjacent; first features, wherein the first feature size being smaller than that obtainable by a photoresist pattern
printing, and the first pattern is symmetric about a central axis; and

a second pattern with a second feature size that is positioned on the carrier, wherein the second feature size is a space
between adjacent second features; and in which materials composing a first portion of the second pattern are different from
materials composing a second portion of the second pattern;

wherein the first portion is above the carrier, the second portion is above the first portion such that the first portion
is sandwiched between the second portion and the carrier;

wherein width of the first portion is substantially the same as width of the second portion;
wherein width is measured in the same direction as feature size; and
wherein a sidewall of the first portion is not covered by the materials composing the second portion.

US Pat. No. 9,264,025

GLITCH FILTER AND FILTERING METHOD

NANYA TECHNOLOGY CORPORAT...

1. A glitch filter, comprising:
a high glitch filter circuit configured for generating a pull-up control signal in accordance with an input signal;
a low glitch filter circuit configured for generating a pull-down control signal in accordance with the input signal;
a control circuit configured for determining a logic level of an output of the glitch filter in accordance with the pull-up
control signal and the pull-down control signal; and

a latch electrically coupled to the output of the glitch filter in parallel, wherein the latch comprises:
a first inverter configured for inverting the output of the glitch filter;
a second inverter, wherein an input of the second inverter is electrically coupled to an output of the first inverter, and
an output of the second inverter is electrically coupled to the output of the glitch filter;

a first enable unit configured for turning on a pull-up path of the second inverter in accordance with the pull-down control
signal; and

a second enable unit configured for turning on a pull-down path of the second inverter in accordance with the pull-up control
signal.

US Pat. No. 10,068,822

SEMICONDUCTOR PACKAGE AND METHOD FOR FORMING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A method for forming semiconductors package comprising:disposing at least one flow hindering supporter onto a substrate, wherein the substrate has at least one active region and at least one gap region surrounded the active region, the flow hindering supporter is located on the gap region, wherein the flow hindering supporter has a first end proximal to the substrate and a second end distal to the substrate, and an area of an end surface of the first end is substantially greater than or equal to and area of an end surface of the second end;
disposing at least one die structure onto at least one active region of the substrate;
injecting a molding compound flowed into the gap region, to mold the flow hindering supporters and the die structures with the molding compound; and
dividing the at least one flow hindering supporter while singulating the at least one die structure.

US Pat. No. 10,049,877

PATTERNING METHOD

NANYA TECHNOLOGY CORPORAT...

1. A patterning method comprising:sequentially forming a bottom layer, a hard mask layer, a buffer mask layer and at least one mask layer on a substrate;
patterning the at least one mask layer and the buffer mask layer to form a plurality of first columnar bodies;
removing a portion of the buffer mask layer in the first columnar bodies;
filling a sacrificial dielectric material in a plurality of first gaps between the first columnar bodies, wherein the sacrificial dielectric material is flowable oxide or spin-on glass (SOG);
patterning the sacrificial dielectric material by using the at least one mask layer of the first columnar bodies as a mask to form a plurality of second columnar bodies;
depositing a conformal spacer layer on the second columnar bodies and forming a spaced columnar body between the adjacent second columnar bodies, wherein a second gap is between the spaced columnar body and the second columnar body;
etching the conformal spacer layer to expose the hard mask layer under the second gaps;
forming a core mask layer within the second gaps;
removing the at least one mask layer and the sacrificial dielectric material; and
removing a portion of the hard mask layer and the bottom layer by using the core mask layer and the buffer mask layer as a mask.

US Pat. No. 9,935,071

SEMICONDUCTOR PACKAGE WITH LATERAL BUMP STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor package, comprising:a semiconductor device having an upper surface and a side, wherein the upper surface and the side form a corner of the semiconductor device;
a lateral bump structure entirely disposed on the side and implementing a lateral signal path of the semiconductor device; and
a vertical bump structure, separated from the lateral bump structure, disposed entirely over the upper surface.

US Pat. No. 9,761,535

INTERPOSER, SEMICONDUCTOR PACKAGE WITH THE SAME AND METHOD FOR PREPARING A SEMICONDUCTOR PACKAGE WITH THE SAME

NANYA TECHNOLOGY CORPORAT...

1. An interposer for a semiconductor package, comprising:
a substrate portion having a first side, a second side, and an electrical interconnect structure between the first side and
the second side, wherein the substrate portion is substantially free from conductive through vias; and

a wall portion disposed on the first side and defining an aperture exposing a portion of the electrical interconnect structure,
wherein the wall portion comprises an intervening layer disposed on the substrate portion and a stiffener disposed on the
intervening layer, the intervening layer and the stiffener having a same width.

US Pat. No. 9,142,267

POWER GENERATOR FOR DATA LINE OF MEMORY APPARATUS

NANYA TECHNOLOGY CORPORAT...

1. A power generator for data transporting buffers of a memory apparatus, comprising:
a bias voltage generator, generating a bias voltage according to a reference voltage; and
a voltage clamping circuit, coupled to the bias voltage generator, the voltage clamping circuit receiving a supply voltage
and the bias voltage and respectively outputting a plurality of data line powers to the data transporting buffers by clamping
the supply voltage according to the bias voltage,

wherein, the supply voltage is varied between a voltage range, and voltage levels of the data line powers are all constant.

US Pat. No. 9,059,053

MULTI-DIE STACK STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A multi-die stack structure, comprising N dies stacked vertically, wherein
N is an integer larger than or equal to 2,
each die comprises N die-specific input pads, wherein a specific pad among the N pads is for an input of the die,
the specific pad of each die above a bottom die is electrically connected with a different pad of the bottom die other than
the specific pad of the bottom die, via at least one through-substrate via and, when not being in the die neighboring to the
bottom die, also via a different pad of each underlying die above the bottom die, and

the specific pad of the bottom die is electrically connected with at least one pad of the overlying die(s) that is not the
specific pad of any overlying die and not any pad electrically connected with the specific pad of any overlying die.

US Pat. No. 10,115,594

METHOD OF FORMING FINE ISLAND PATTERNS OF SEMICONDUCTOR DEVICES

NANYA TECHNOLOGY CORPORAT...

1. A method of forming fine island patterns, the method comprising:forming a plurality of first mask pillars on a hard mask layer on a substrate comprising:
forming a lower buffer mask layer on the hard mask layer;
forming a plurality of through vias in the lower buffer mask layer;
filling the through vias with a mask material to form the first mask pillars; and
removing the lower buffer mask layer; and
forming an upper buffer mask layer over the hard mask layer to cover the first mask pillars;
patterning a plurality of islands in the upper buffer mask layer;
separating each of the islands into a plurality of sub-islands;
etching the upper buffer mask layer to form a plurality of second mask pillars on the hard mask layer;
etching an exposed portion of the hard mask layer exposed by the first mask pillars and the second mask pillars until portions of the substrate are etched; and
removing the first mask pillars, the second mask pillars, and remaining portions of the hard mask layer.

US Pat. No. 10,102,921

FUSE BLOWING METHOD AND FUSE BLOWING SYSTEM

NANYA TECHNOLOGY CORPORAT...

1. A fuse blowing method for a memory, wherein the memory comprises a plurality of word lines and a plurality of memory cells, and the fuse blowing method comprises:detecting, by a voltage detector connected to the word lines, a plurality of voltages of the word lines, wherein the memory cells comprise a plurality of normal memory cells and a plurality of redundant memory cells, a gate of a transistor of each of the normal memory cells is electrically connected to one of the word lines, a gate of a transistor of each of the redundant memory cells is electrically connected to one of the word lines via a fuse;
sending, by a post package repair circuit connected to the voltage detector and a fuse circuit, an enabling signal to the fuse circuit when one of the voltages of the word lines is below a voltage threshold, wherein the one of the voltages corresponds to a first word line of the word lines; and
blowing, by the fuse circuit connected to the post package repair circuit, one of the fuses, wherein the one of the fuses is connected between the gate of the transistor of one of the redundant memory cells and the first word line, such that the one of the voltages is higher than the voltage threshold.

US Pat. No. 9,985,521

VOLTAGE SYSTEM

NANYA TECHNOLOGY CORPORAT...

1. A voltage system, comprising:a switch device connected to a basis supply voltage port and an output port of the voltage system and configured to regulate an output voltage at the output port of the voltage system;
a pull-up device connected to a supply voltage port and the output port of the voltage system and configured to pull up the output voltage at the output port of the voltage system while the pull-up device is activated, wherein the pull-up device includes a transistor, and the transistor includes a source coupled to supply voltage port and a drain coupled to the output port; and
a control device, including a pulse width modulation device, connected to the switch device, the pull-up device and a reference voltage and configured to adjust the duty cycle of the switch device and to activate the pull-up device when the output voltage is lower than the reference voltage, wherein the control device is further connected to a basis reference voltage and includes the pulse width modulation device and a controller independent from each other, wherein the pulse width modulation device is configured to, based on the basis reference voltage and the output voltage, adjust a duty cycle of the switch device, and the controller is configured to, based on the reference voltage and the output voltage, determine whether to activate the pull-up device;
wherein the switch device receives the basis supply voltage and the supply voltage is higher than the basis supply voltage.

US Pat. No. 9,966,363

SEMICONDUCTOR APPARATUS AND METHOD FOR PREPARING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor apparatus, comprising:a first semiconductor die, comprising:
a substrate;
a circuit portion disposed on the substrate;
a first chip selection terminal disposed in the circuit portion above or below the substrate; and
a first lower terminal electrically connected to the first chip selection terminal; and
a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner, the second semiconductor die comprising a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die,
wherein the first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.

US Pat. No. 10,074,499

SYSTEM AND METHOD FOR BLOWING A FUSE

Nanya Technology Corporat...

1. A system, comprising:a fuse pump;
a fuse that can be blown by the fuse pump; and
a voltage source configured to provide a first voltage and a second voltage;
wherein if the voltage source and the fuse pump receive an enable signal, the voltage source provides the first voltage as a supply voltage to the fuse pump and the fuse pump is enabled to blow the fuse,
wherein if the voltage source and the fuse pump do not receive the enable signal, the voltage source provides the second voltage as the supply voltage of the fuse pump and the fuse pump is disabled from blowing the fuse, and
wherein the first voltage is higher than the second voltage.

US Pat. No. 10,068,865

COMBING BUMP STRUCTURE AND MANUFACTURING METHOD THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A combing bump structure, comprising:a first semiconductor substrate;
a first pad disposed on the first semiconductor substrate;
a first conductive layer disposed on the first pad;
a first solder bump disposed on the first conductive layer; and
at least two first metal side walls disposed along opposing outer side walls of the first solder bump respectively;
a second semiconductor substrate;
a second pad disposed on the second semiconductor substrate;
a second conductive layer disposed on the second pad;
a second solder bump disposed on the second conductive layer; and
at least two second metal side walls disposed along opposing outer side walls of the second solder bump respectively, and the second solder bump configured to form a solder joint with the first solder bump when the first and second solder bumps are brought together and a reflow process is performed,
wherein one of the two first metal side walls is disposed in the solder joint and positioned between the two second metal side walls,
wherein one of the two second metal side walls is disposed in the solder joint and positioned between the two first metal side walls,
wherein a melting temperature of the one of the two first metal side walls and the one of the two second metal side walls is lower than a melting temperature of the other of the two first metal side walls and the other of the two second metal side walls.

US Pat. No. 9,985,105

METHOD OF MANUFACTURING A PMOS TRANSISTOR COMPRISING A DUAL WORK FUNCTION METAL GATE

Nanya Technology Corporat...

1. A method for fabricating a semiconductor device, comprising:providing a substrate;
forming a dummy gate on the substrate;
forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate;
performing a first chemical mechanical polishing (CMP) process to the inter-layer dielectric layer (ILD) to expose an upper surface of the dummy gate;
forming a metal layer on the upper surface of the dummy gate;
removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD);
conformally forming a gate dielectric layer in the trench;
conformally forming a first conductive type metal layer on the gate dielectric layer;
anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD) and to expose a portion of the gate dielectric layer, wherein the first conductive type metal layer is divided into two first conductive type metal layers defining the gap;
filling a second conductive type metal layer in the gap, wherein the second conductive type metal layer is sandwiched between the two first conductive type metal layers to form a dual work function metal gate layer, wherein the two first conductive type metal layers are n+ metal layers and the second conductive type metal layer is a p+ metal layer, and wherein the first conductive type metal layer and the second conductive type metal layer both directly contact the gate dielectric layer; and
performing a second chemical mechanical polishing (CMP) process to the second conductive type metal layer and the metal layer to expose an upper surface of the dual work function metal gate layer.

US Pat. No. 9,984,995

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor package comprising:a package substrate;
a first semiconductor chip and a second semiconductor chip disposed on the package substrate;
an underfill dispenser configured to mechanically bond the first semiconductor chip and the second semiconductor chip;
a top interposer electrically connected to the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip are disposed between the package substrate and the top interposer, and wherein there is an air gap between the underfill dispenser and the substrate or between the underfill dispenser and the top interposer;
a first connection element disposed between the top interposer and the first semiconductor chip to electrically interconnect the top interposer and the first semiconductor chip; and
a second connection element disposed between the top interposer and the second semiconductor chip to electrically interconnect the top interposer and the second semiconductor chip.

US Pat. No. 10,090,154

METHOD FOR PREPARING A SEMICONDUCTOR STRUCTURE HAVING SECOND LINE PATTERNS AND THIRD LINE PATTERNS FORMED OVER FIRST LINE PATTERNS

NANYA TECHNOLOGY CORPORAT...

1. A method for preparing a semiconductor structure, comprising:forming a plurality of linear core patterns and a plurality of linear spacer patterns on a substrate, wherein the plurality of linear spacer patterns are formed on sidewalls of the linear core patterns;
removing the plurality of linear core patterns from the substrate;
removing a portion of the substrate not covered by the plurality of linear spacer patterns to form a plurality of first line patterns, wherein the plurality of first line patterns extend along a first direction;
depositing an etched layer on the first line patterns of the substrate;
performing a first litho-etch process to remove a first surface portion of the etched layer to form a plurality of second line patterns over the first line patterns, wherein the plurality of second line patterns extend along a second direction different from the first direction; and
performing a second litho-etch process to remove a second surface portion of the etched layer, which is different from the first surface portion, to form a plurality of third line patterns over the first line patterns, wherein the plurality of second line patterns and the plurality of third line patterns are formed on the etched layer and over the first line patterns in an alternate manner, wherein the plurality of second line patterns and the plurality of third line patterns are positioned at substantially the same level on the substrate.

US Pat. No. 9,892,985

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Nanya Technology Corporat...

1. A semiconductor device, comprising:
an integrated circuit die;
at least one conductive terminal disposed on the integrated circuit die;
a frame positioned on the integrated circuit die, wherein the frame substantially exposes the at least one conductive terminal;
and

at least one conductive bump positioned in the frame, wherein the at least one conductive bump electrically connects the at
least one conductive terminal,

wherein the frame comprises a supporting layer of non-conductive material selected from the group consisting of silicon and
silicon oxide.

US Pat. No. 9,893,037

MULTI-CHIP SEMICONDUCTOR PACKAGE, VERTICALLY-STACKED DEVICES AND MANUFACTURING THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor chip comprising:
a semiconductor device having an upper surface and a lower surface opposite to the upper surface, wherein the semiconductor
device comprises:

an input terminal;
a plurality of through silicon vias (TSVs) extended through the semiconductor device, wherein one of the through silicon vias
is connected to the input terminal; and

a plurality of selection pads disposed on the lower surface, wherein one of the selection pads is connected to the input terminal,
and rest of the selection pads are connected to the rest of the through silicon vias respectively;

a plurality of tilt pads disposed on the upper surface and connected to the selection pads through the through silicon vias
respectively, wherein each tilt pad comprises a pad surface that is non-parallel to the upper surface; and

a plurality of tilt conductive structures disposed on the corresponding tilt pads respectively, wherein a lower end of each
tilt conductive structure is in contact with the pad surface of each tilt pad, and an upper end of each tilt conductive structure
is vertically overlapped with an immediately-adjacent one of the tilt pads.

US Pat. No. 9,799,391

DRAM CIRCUIT, REDUNDANT REFRESH CIRCUIT AND REFRESH METHOD

Nanya Technology Corporat...

1. A DRAM circuit, comprising:
an array including a normal word line, a first redundant word line and a second redundant word line immediately adjacent to
the first redundant word line, wherein the second redundant word line is activated if the normal word line is assigned, by
a memory controller external to the DRAM circuit, to be activated, wherein the normal word line is a second normal word line,
the array further includes a first normal word line immediately adjacent to the second normal word line;

a redundant refresh circuit configured to determine that the first redundant word line is required to be refreshed in response
to the second redundant word line being activated;

a row decoder configured to, according to the determination of the redundant refresh circuit, refresh the first redundant
word line; and

a target row counter configured to deter mine that the first normal word line is required to be refreshed in response to the
second normal word line being assigned to be activated, wherein the row decoder ignores the determination from the target
row counter, and, according to the determination from the redundant refresh circuit, refresh the first redundant word line.

US Pat. No. 10,170,328

SEMICONDUCTOR PATTERN HAVING SEMICONDUCTOR STRUCTURES OF DIFFERENT LENGTHS

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor pattern comprising:a substrate;
a plurality of first semiconductor structures disposed over the substrate, the first semiconductor structures comprising a first length;
a plurality of second semiconductor structures disposed over the substrate, the second semiconductor features comprising a second length, and the first semiconductor features and the second semiconductor features being alternately arranged; and
a semiconductor frame structure disposed over the substrate, the semiconductor frame structure encircling the first semiconductor structures and the second semiconductor structures,
wherein the first length of the first semiconductor structures is less than the second length of the second semiconductor structures.

US Pat. No. 10,170,339

SEMICONDUCTOR STRUCTURE AND A MANUFACTURING METHOD THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A method of manufacturing a semiconductor structure, comprising:providing a substrate and a chip disposed over the substrate;
disposing the substrate over a first molding member;
disposing a second molding member over the substrate to encapsulate the chip;
disposing a molding material around the chip;
forming a molding over the substrate and around the chip;
removing the first molding member;
removing the second molding member,
wherein the first molding member includes a curved surface protruded towards the substrate, the chip or the second molding member,
wherein the substrate or the chip is curved to match a curvature of the curved surface of the first molding member before disposing the molding material, and
wherein the substrate and the chip are entirely encapsulated by the first molding member and the second molding member before disposing the molding material.

US Pat. No. 9,991,215

SEMICONDUCTOR STRUCTURE WITH THROUGH SUBSTRATE VIA AND MANUFACTURING METHOD THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor structure, comprising:a substrate including a first side and a second side opposite to the first side;
a first conductive via extending through the substrate;
a second conductive via extending through the substrate;
a metallic structure disposed between the first conductive via and the second conductive via; and
first dielectric liners entirely surrounding the first conductive via and the second conductive via, respectively; and
second dielectric liners only partially surrounding the metallic structure and only covering sides of the metallic structure facing the first conductive via and the second conductive via,
wherein the first conductive via is isolated from the second conductive via by the metallic structure, the first conductive via and the second conductive via are configured to connect to a signal source or transmit a signal, and the metallic structure is configured to connect to a power or a ground, and
wherein a cross-sectional shape of the metallic structure is different from a cross-sectional shape of the first conductive via and the second conductive via.

US Pat. No. 10,170,432

SEMICONDUCTOR STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor structure, comprising:a substrate having a front side surface and a back side surface;
at least one semiconductor device disposed on the front side surface;
a through-substrate via (TSV) disposed in the substrate, wherein the TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device;
a shield structure disposed in the substrate and surrounding the TSV, wherein the shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure and the TSV having bottom ends at different heights; and
a first dielectric layer covering a side surface and a bottom surface of the shield structure, wherein the back side surface of the substrate is lower than a bottom surface of the first dielectric layer.

US Pat. No. 10,050,021

DIE DEVICE, SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME

Nanya Technology Corporat...

1. A semiconductor device, comprising:a first die device including:
a first die including:
a first active layer; and
a first interconnect feature configured for electrical connection of the first active layer; and
a second die device including:
a second die including:
a second active layer; and
a bump, independent of the second die, configured for electrical connection of the second active layer, wherein the bump is surrounded by the first interconnect feature.

US Pat. No. 10,170,340

SEMICONDUCTOR STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor structure, comprising:a substrate;
a chip disposed over the substrate; and
a molding disposed over the substrate and surrounding the chip at a molding temperature,
wherein the substrate includes a curved configuration at a side opposite to the chip, and the molding includes a reduced size which compensates a warpage of the curved configuration of the substrate at the molding temperature, so that the warpage of the substrate is convex or about zero at the molding temperature or 10° C. more or less than the molding temperature.

US Pat. No. 10,049,714

DRAM AND METHOD FOR MANAGING POWER THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A dynamic access memory (DRAM), comprising:a memory array of memory cells;
a control device configured to derive an information associated with a command, and determine, based on the information, whether to provide an amount of electrical energy greater than, less than, or equal to an amount of electrical energy currently required; and
a charge pump circuit configured to provide the memory array with the resultant amount of electrical energy based on the determination,
wherein the control device derives the information associated with the command by monitoring a ratio of command occupancy in a queue, and the charge pump circuit provides a same amount of electrical energy as the amount of electrical energy currently required when the monitor result indicates that the ratio of command occupancy is less than a highest endpoint of a ratio range and greater than a lowest endpoint of the ratio range.

US Pat. No. 9,893,035

STACKED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A stacked package structure, comprising:
a first package structure having a first surface and a second surface opposite to the first surface, the first package structure
comprising:

at least one first die having a first active region disposed at a bottom of the first die;
a first redistribution layer disposed on the first die, wherein a top surface of the first redistribution layer serves as
the first surface of the first package structure;

a first molding material and a plurality of first conductive features formed in the first molding material, wherein a bottom
surface of the first conductive features, a bottom surface of the first molding material, and a bottom surface of the first
active region are substantially coplanar; and

a plurality of first bumps disposed under the first active region, wherein the first bumps directly contact with the first
active region and the first conductive features.

US Pat. No. 10,063,225

VOLTAGE SWITCHING DEVICE AND METHOD

NANYA TECHNOLOGY CORPORAT...

1. A voltage switching device, comprising:a receiver;
a voltage controlled switch connected between an input data terminal and the receiver;
a first voltage generator circuit configured to provide a first voltage;
a voltage detector configured to output a first logic signal while detecting the first voltage higher than a predetermined voltage;
a first switch circuit connected between the first voltage generator circuit and the voltage controlled switch, the first switch circuit being turned on according to the first logic signal, so that the voltage controlled switch is turned on by the first voltage, and data are transmitted from the input data terminal to the receiver;
a second voltage generator circuit configured to provide a second voltage after the voltage detector outputs a second logic signal while detecting the first voltage dropped lower than the predetermined voltage; and
a second switch circuit connected between the second voltage generator circuit and the voltage controlled switch, wherein the first switch circuit is turned off according to the second logic signal, and the second switch circuit is turned on according to the second logic signal, so that the voltage controlled switch is turned on by the second voltage, and the data are transmitted from the input data terminal to the receiver,
wherein the first switch circuit comprises:
a first semiconductor switch connected between the first voltage generator circuit and the voltage controlled switch; and
a first inverter connected between the voltage detector and the first switch, wherein when the voltage detector outputs the first logic signal, the first inverter inverts the first logic signal into the second logic signal to turn on the first semiconductor switch, so that the first voltage generator circuit outputs the first voltage to turn on the voltage controlled switch through the first semiconductor switch.

US Pat. No. 10,103,114

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor structure comprising: a substrate;a pad disposed over the substrate;
a first passivation disposed over the substrate, surrounding the pad, the first passivation having a bottom surface contacting the substrate and a top surface opposite to the bottom surface and including a protrusion protruded from the top surface of the first passivation and away from the substrate;
a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and
a second passivation disposed over a first portion of the conductive layer, wherein a second portion of the conductive layer disposed over the protrusion is exposed from the second passivation and is protruded through the second passivation, and
wherein the second portion of the conductive layer is disposed conformal to the protrusion, and
wherein, the first passivation includes a first dielectric layer disposed over the substrate and partially covering the pad, and a second dielectric layer disposed over an entire top surface of the first dielectric layer, partially covering the pad and including the protrusion protruded from the second dielectric layer and away from the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are formed from different materials.

US Pat. No. 10,147,608

METHOD FOR PREPARING A PATTERNED TARGET LAYER

NANYA TECHNOLOGY CORPORAT...

1. A method for preparing a patterned target layer, comprising:forming a target layer over a substrate;
forming a multi-layered hard mask layer over the target layer, wherein the multi-layered hard mask layer comprises a first hard mask layer over the target layer, a second hard mask layer between the target layer and the first hard mask layer, and a third hard mask layer between the target layer and the second hard mask layer, wherein a material of the second hard mask layer is different from a material of the first hard mask layer and a material of the third hard mask layer,
patterning the first hard mask layer to form a plurality of first hard mask patterns;
patterning the second hard mask layer to form a plurality of second hard mask patterns, wherein a portion of the second hard mask patterns is covered with the first hard mask patterns, and another portion of the second hard mask patterns is exposed through the first hard mask patterns;
removing the third hard mask layer exposed through the first hard mask patterns and the second hard mask patterns to form a plurality of third hard mask patterns; and
removing the target layer exposed through the third hard mask patterns.

US Pat. No. 10,127,967

DRAM AND METHOD FOR OPERATING THE SAME

Nanya Technology Corporat...

1. A dynamic random access memory (DRAM), comprising:a refresh unit including a target row on which a read/write (R/W) operation is requested to be performed; and
an accessing device configured to perform the R/W operation on the target row while the refresh unit is being refreshed;
wherein if the refresh unit is being refreshed, and the target row has not been refreshed, then the accessing device is configured to perform the R/W operation on the target row while the refresh unit is being refreshed.

US Pat. No. 10,141,275

METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A method of manufacturing a semiconductor structure, comprising:providing a substrate;
disposing a pad over the substrate;
disposing a first passivation over the substrate to partially cover the pad;
disposing a conductive material over the first passivation and the pad to form a conductive line electrically connected to the pad;
disposing a second passivation over the first passivation to partially cover the conductive line; and
forming a plurality of first protrusions over the conductive line exposed from the second passivation;
wherein the method further comprising:
disposing a patterned mask including a plurality of openings over the first passivation;
removing portions of the first passivation exposed from the patterned mask to form a plurality of recesses over the first passivation;
removing the patterned mask; and
disposing the conductive material within the plurality of recesses to form a plurality of second protrusions protruded from the conductive line towards the substrate.

US Pat. No. 10,211,061

METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A method for manufacturing a semiconductor structure, comprising:forming a target layer, a lower hard mask layer, a middle hard mask layer, and an upper hard mask layer in sequence on a substrate;
forming a first mask layer on the upper hard mask layer, wherein the first mask layer has a plurality of openings exposing a portion of the upper hard mask layer;
etching the exposed portion of the upper hard mask layer to form a first patterned upper hard mask layer comprising at least one recess, at least one remained portion under the recess, and at least one highland portion adjacent to the recess, wherein the remained portion remains a thickness that is less than a depth of the recess;
forming a patterned organic layer on the recess of the first patterned upper hard mask layer, wherein the patterned organic layer and the highland portion of the first patterned upper hard mask layer are misaligned;
etching the first patterned upper hard mask layer to form a second patterned upper hard mask layer having a plurality of apertures exposing a portion of the middle hard mask layer; and
etching the middle hard mask layer, the lower hard mask layer, and the target layer by using the second patterned upper hard mask layer as a mask to form a patterned target layer.

US Pat. No. 10,153,161

METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A method for manufacturing a semiconductor structure, comprising:forming a target layer, a lower hard mask layer, a middle hard mask layer, and an upper hard mask layer in sequence on a substrate;
forming a first mask layer on the upper hard mask layer, wherein the first mask layer has a plurality of openings exposing a portion of the upper hard mask layer;
etching the exposed portion of the upper hard mask layer to form a patterned upper hard mask layer having a plurality of apertures exposing a portion of the middle hard mask layer;
forming a patterned organic layer on the exposed portion of the middle hard mask layer; and
etching the patterned upper hard mask layer, the patterned organic layer, the middle hard mask layer, the lower hard mask layer, and a portion of the target layer to form a patterned target layer, wherein the etching of the patterned target layer forms a plurality of recesses thereon and forms a plurality of bottom portions of the patterned target layer, and each bottom portion is under a corresponding one of the recesses.

US Pat. No. 10,153,032

PUMP SYSTEM OF A DRAM AND METHOD FOR OPERATING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A pump system of a DRAM, comprising:a pump device configured to provide a first current sufficient to allow a bank of the DRAM to operate at a normal refresh rate without other spare pump devices in response to a normal instruction which indicates that the bank is instructed to operate at the normal refresh rate;
a spare pump assembly, coupled with the pump device in parallel, which would otherwise provide, in combination with the pump device, the first current sufficient to allow the bank of the DRAM to operate at the normal refresh rate only when a circuit structure of the DRAM is redesigned by metal option, wherein the spare pump assembly includes a first spare pump device configured to provide, in combination with the pump device, a second current sufficient to allow the bank to operate at a first refresh rate greater than the normal refresh rate in response to a first instruction which indicates that the bank is instructed to operate at the first refresh rate; and
a controller configured to disable the first spare pump device in response to the normal instruction, and to enable the first spare pump device in response to the first instruction.

US Pat. No. 10,147,611

METHOD FOR PREPARING SEMICONDUCTOR STRUCTURES

NANYA TECHNOLOGY CORPORAT...

1. A method for preparing semiconductor structures, comprising:providing a substrate;
forming a plurality of first core features spaced apart from each other over the substrate;
forming a spacer layer over the first core features, the spacer layer covering sidewalls and top surfaces of each first core feature;
forming a plurality of second core features over the substrate, wherein portions of the spacer layer are exposed through the second core features;
performing a densification treatment on the second core features; and
removing the spacer layer to form a plurality of openings between the first core feature and the second core features after the densification treatment.

US Pat. No. 10,250,132

VOLTAGE SYSTEM AND OPERATING METHOD THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A voltage system, comprising:an oscillator configured to provide an oscillation signal exhibiting a first frequency when a voltage level of a supply voltage is greater than a reference voltage level, and to provide the oscillation signal exhibiting a second frequency greater than the first frequency when the voltage level of the supply voltage is less than the reference voltage level; and
a pump device configured to provide the supply voltage, based on a frequency of the oscillation signal provided by the oscillator, by performing a charging operation;
the reference voltage level being a second reference voltage level, wherein the oscillator is deactivated when the voltage level of the supply voltage is greater than a first reference voltage level greater than the second reference voltage level;
wherein the oscillator provides the oscillation signal exhibiting the first frequency when the voltage level of the supply voltage is less than the first reference voltage level and greater than the second reference voltage level.

US Pat. No. 10,242,978

SEMICONDUCTOR ELECTROSTATIC DISCHARGE PROTECTION DEVICE

Nanya Technology Corporat...

1. A semiconductor electrostatic discharge (ESD) protection device comprising:a substrate comprising a first conductivity type;
a gate formed on the substrate;
a source region and a drain region formed in the substrate, the source region and the drain region comprising a second conductivity type complementary to the first conductivity type; and
a body region formed in the substrate, the body region comprising the first conductivity type,
wherein the drain region is electrically connected to a power pad or an I/O pad, and the source region is electrically connected to a ground pad,
wherein the gate is electrically connected to the power pad or the I/O pad through a capacitor, and electrically connected to the ground pad through a resistor,
wherein the body region is electrically connected to the gate through a wiring layer without the resistor.

US Pat. No. 10,236,035

DRAM MEMORY DEVICE ADJUSTABLE REFRESH RATE METHOD TO ALLEVIATE EFFECTS OF ROW HAMMER EVENTS

NANYA TECHNOLOGY CORPORAT...

1. A dynamic random access memory (DRAM), comprising:a refresh unit having a plurality of memory rows;
an accessing device configured to access the memory rows; and
a refresh device configured to refresh the refresh unit in a first manner in response to a first event, in which an access time of the refresh unit reaches a threshold number of times within a self-refresh cycle and a quantity of accessed memory rows of the refresh unit is not greater than a threshold quantity, and in a second manner in response to a second event, in which the access time of the refresh unit reaches the threshold number of times within the self-refresh cycle and the quantity of accessed memory rows of the refresh unit is greater than the threshold quantity.

US Pat. No. 10,229,877

SEMICONDUCTOR CHIP AND MULTI-CHIP PACKAGE USING THEREOF

Nanya Technology Corporat...

1. A chip package comprising a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip comprises:a semiconductor substrate having a first side and a second side;
a conductive through plug extending through the semiconductor substrate from the first side to the second side; and
a non-through plug extending from the first side to an internal plane of the semiconductor substrate without extending through the second side, wherein the non-through plug includes an exposed surface that is coplanar to the first side;
wherein the second semiconductor chip is adjacent to the first semiconductor chip, and the second semiconductor chip includes a conductive member with a thickness, and wherein the conductive through plug is coupled to the conductive member of the second semiconductor chip, while the non-through plug is not electrically coupled to the conductive member of the second semiconductor chip;
wherein the exposed surface of the non-through plug contacts a space between the second semiconductor chip and the first side of the first semiconductor chip, and the space has a height at least more than the thickness of the conductive member of the second semiconductor chip;
wherein the non-through plug is aligned with an alignment pattern on the second semiconductor chip.

US Pat. No. 10,204,783

METHOD OF FORMING FINE ISLAND PATTERNS OF SEMICONDUCTOR DEVICES

NANYA TECHNOLOGY CORPORAT...

1. A method of forming fine island patterns, the method comprising:forming a plurality of first mask pillars on a hard mask layer on a substrate;
forming an upper buffer mask layer over the hard mask layer by spin-coating to cover the first mask pillars;
forming a plurality of first linear patterns each extending along a first direction, a plurality of second linear patterns each extending along a second direction, and a plurality of third linear patterns each extending along a third direction in the upper buffer mask layer by at least one patterning process;
etching the upper buffer mask layer to form a plurality of second mask pillars on the hard mask layer;
etching an exposed portion of the hard mask layer exposed by the first mask pillars and the second mask pillars until portions of the substrate are etched; and
removing the first mask pillars, the second mask pillars, and remaining portions of the hard mask layer.

US Pat. No. 10,192,841

SEMICONDUCTOR PACKAGE AND METHOD FOR PREPARING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor package, comprising:a first device having a first upper surface and a first side, wherein the first upper surface and the first side form a first corner of the first device; and
a bump structure disposed over the first upper surface, wherein the bump structure extends laterally across the first side of the first device;
wherein the first device comprises a missing corner, and the bump structure fills the missing corner.

US Pat. No. 10,192,853

METHOD FOR PREPARING A SEMICONDUCTOR APPARATUS

NANYA TECHNOLOGY CORPORAT...

1. A method for preparing a semiconductor apparatus, comprising:preparing a first semiconductor die, wherein the first semiconductor die comprises a substrate, a circuit portion disposed on the substrate, a first chip selection terminal disposed in the circuit portion above or below the substrate, a first upper terminal, and a first lower terminal electrically connected to the first chip selection terminals;
preparing a second semiconductor die, wherein the second semiconductor die comprises a second chip selection chip terminal and a second lower terminal electrically connected to the second chip selection terminal, wherein the second chip selection terminal is electrically connected to the first upper terminal of the first semiconductor die via the second lower terminal; and
attaching the second semiconductor die to the first semiconductor die in a horizontally shifted manner;
wherein the first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.

US Pat. No. 10,181,472

MEMORY CELL WITH VERTICAL TRANSISTOR

NANYA TECHNOLOGY CORPORAT...

1. A memory cell comprising:a substrate;
a deep trench capacitor formed in the substrate, wherein the deep trench capacitor comprises a buried plate, a storage node and a node dielectric layer sandwiched between the buried plate and the storage node; and
a vertical transistor formed on the substrate and electrically connected to the deep trench capacitor, the vertical transistor comprising:
a source region and a drain region vertically stacked on the substrate;
a channel region vertically sandwiched between the source region and the drain region;
a gate structure annularly wrapping around the channel region; and
a diffusion region formed in the substrate, and electrically connected to the storage node of the deep trench capacitor and the source region of the vertical transistor.

US Pat. No. 10,181,401

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

NANYA TECHNOLOGY CORPORAT...

1. A method for manufacturing a semiconductor device, comprising following operations:forming a first patterned target layer on a substrate having a first region and a second region, wherein the first patterned target layer has a plurality of first openings along a first direction in the first region, the first openings expose a portion of the substrate;
forming a patterned hard mask layer over the first patterned target layer, wherein the patterned hard mask layer has a plurality of first recesses along a second direction in the first region and a plurality of second recesses along the first direction thereon in the second region;
forming a patterned photoresist layer over the patterned hard mask layer, wherein the patterned photoresist layer has a plurality of stripe structures along the second direction in the first region and a plurality of block structures along the first direction in the second region; and
etching the patterned photoresist layer, the patterned hard mask layer, and the first patterned target layer by using the patterned hard mask layer and the patterned photoresist layer as etching masks to form a second patterned target layer.

US Pat. No. 10,147,178

METHOD OF RECOGNIZING WAFER

NANYA TECHNOLOGY CORPORAT...

1. A method, comprising:obtaining image information including a first vector and a second vector by respectively capturing an image of a first wafer and an image of a second, wherein the first wafer is known to be a good product, wherein the second wafer is known to be a defective product;
calculating a projection vector based on a covariance matrix associated with the first vector and the second vector;
obtaining image information including a third vector by capturing an image of a third wafer under a test;
projecting each of the first vector, the second vector and the third vector onto the projection vector; and
classifying the third wafer as either the good product or the defective product based on the projected first vector, the projected second vector and the projected third vector.

US Pat. No. 10,141,043

DRAM AND METHOD FOR MANAGING POWER THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A dynamic random access memory (DRAM), comprising:a plurality of banks, each of the banks including a plurality of subarrays;
a power source; and
a control device configured to derive information on a quantity of operated subarrays among the subarrays, and determine how much electrical energy to provide based on the information,
wherein the power source provides the resultant amount of electrical energy based on the determination from the control device;
wherein the control device determines to provide a first amount of electrical energy when a quantity ratio of the operated subarrays is greater than or equal to a highest endpoint of a ratio range, and provide a second amount of electrical energy less than the first amount of electrical energy when the quantity ratio of the operated subarrays is less than or equal to a lowest endpoint of the ratio range.

US Pat. No. 10,256,179

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A package structure, comprising:an interconnection layer;
a pad disposed in the interconnection layer;
a first passivation layer disposed on the interconnection layer, wherein the first passivation layer has at least one first opening and a second opening, the second opening exposes the pad;
at least one elastic bump disposed on the interconnection layer, wherein a portion of the elastic bump is embedded in the first opening, and the portion of the elastic bump extends below the first passivation layer; and
a conductive layer disposed on the elastic bump and the first passivation layer, wherein the conductive layer is in contact with the pad through the second opening, the elastic bump is between the first passivation layer and the conductive layer, and the conductive layer covers a top surface of the elastic bump.