US Pat. No. 9,521,754

EMBEDDED COMPONENTS IN A SUBSTRATE

Multek Technologies Limit...

1. A printed circuit board comprising:
a core substrate layer comprising a first copper layer laminated to a first surface of a first pre-preg layer and a second
copper layer laminated to a second surface of the pre-preg layer;

an adhesive layer of a same material applied to an entire first surface of the first copper layer;
an electronic component having a first surface adhered to the adhesive layer;
a second pre-preg layer laminated to the first copper layer, wherein the second pre-preg layer includes a component cut-out
and the second pre-preg layer is coupled to the adhesive layer and configured such that the electronic component fits within
the component cut-out and the second pre-preg layer contacts the electronic component due to flow of the second pre-preg layer
during lamination;

a third copper layer laminated to the second pre-preg layer.

US Pat. No. 9,867,290

SELECTIVE SEGMENT VIA PLATING PROCESS AND STRUCTURE

Multek Technologies Limit...

1. A circuit board comprising:
a laminated stack comprising a plurality of non-conductive layers and a plurality of conductive layers, wherein the laminated
stack further comprises an inner plug layer comprising a plurality of plating resist layers, the inner plug layer stacked
within an interior of the laminated stack;

a via formed through the laminated stack, wherein side walls of the via are plated with conductive material except where the
via passes through the inner plug layer, thereby forming a via side wall plating discontinuity, wherein the via side walls
define a via diameter, and a surface of the via side wall plating facing into the via defines a plated via diameter that is
less than the via diameter; and

a plurality of cavities, one cavity for each plating resist layer, each cavity extending transversely from a longitudinal
axis of the via at a same layer within the lamented stack as a corresponding plating resist layer, wherein each cavity is
defined by cavity side walls that are recessed from the via side walls and by top and bottom surfaces corresponding to layers
of the laminated stack adjacently laminated to both sides of the corresponding plating resist layer, wherein the cavity side
wall comprises plating resist.

US Pat. No. 9,763,327

SELECTIVE SEGMENT VIA PLATING PROCESS AND STRUCTURE

Multek Technologies Limit...

1. A circuit board comprising:
a laminated stack comprising a plurality of non-conductive layers and a plurality of conductive layers, wherein the laminated
stack further comprises an inner plug subassembly comprising a plating resist, the inner plug subassembly stacked within an
interior of the laminated stack;

a via formed through the laminated stack, wherein via side walls define a via diameter, and the via side walls are plated
with conductive material except where the via passes through the inner plug subassembly, thereby forming a via side wall plating
discontinuity, wherein a surface of the via side wall plating facing into the via defines a plated via diameter that is less
than the via diameter; and

a cavity extending transversely from a longitudinal axis of the via at a same layer within the lamented stack as the inner
plug subassembly, the cavity defined by cavity side walls that are recessed from the via side walls and by top and bottom
surfaces corresponding to layers of the laminated stack adjacently laminated to both sides of the inner plug subassembly,
wherein the cavity side wall comprises the plating resist.

US Pat. No. 10,064,292

RECESSED CAVITY IN PRINTED CIRCUIT BOARD PROTECTED BY LPI

Multek Technologies Limit...

1. A printed circuit board comprising:a laminated stack comprising a plurality of non-conductive layers and a plurality of conductive layers, wherein a recessed cavity is formed in the laminated stack, the recessed cavity having cavity side walls and a cavity bottom surface; and
a photo imageable polymer structure formed within the laminated stack, wherein the photo imageable structure forms a perimeter boundary of the recessed cavity within the cavity side walls adjacent to the cavity bottom surface.

US Pat. No. 10,009,992

PCB HYBRID REDISTRIBUTION LAYER

Multek Technologies Limit...

1. A printed circuit board comprising:a. an inner core structure comprising a laminated stack of a plurality of non-conductive layers and a plurality of conductive layers, wherein the plurality of non-conductive layers have a first coefficient of thermal expansion value and a first elastic modulus value;
b. a buffer layer laminated to the inner core structure, wherein the buffer layer comprises a first dielectric material having a second coefficient of thermal expansion value less than the first coefficient of thermal expansion value, further wherein the buffer layer has a second elastic modulus value;
c. an intermediate conductive layer coupled to the buffer layer;
d. an outer layer coupled to the intermediate conductive layer and the buffer layer, wherein the outer layer comprises a second dielectric material having a third coefficient of expansion value less than the second coefficient of thermal expansion value, further wherein the outer layer has a third elastic modulus value, wherein the second elastic modulus value is less than the first elastic modulus value and the second elastic modulus value is less than the third elastic modulus value; and
e. an outer conductive layer coupled to the outer layer.

US Pat. No. 9,992,880

RIGID-BEND PRINTED CIRCUIT BOARD FABRICATION

Multek Technologies Limit...

1. A method of manufacturing a printed circuit board comprising:a. forming core structure having core circuitry on at least one surface of the core structure;
b. forming a printed circuit board stack up, wherein the printed circuit board stack up comprises the core structure, a dummy core, one or more non-conductive layers and one or more conductive layers, wherein one of the non-conductive layers is positioned between the dummy core and the core circuitry, further wherein the dummy core comprises a non-conductive layer and a conductive layer, and forming the printed circuit board stack up further comprises positioning the conductive layer of the dummy core in contact with the one non-conductive layer stacked in contact with the core circuitry;
c. laminating the printed circuit board stack up, thereby forming a laminated stack;
d. forming a depth controlled rout from a surface of the laminated stack to the dummy core and around a perimeter of the dummy core, wherein a portion of the laminated stack within the perimeter of the rout and to a depth including the dummy core forms a laminated stack plug; and
e. removing the laminated stack plug, thereby exposing the one non-conductive layer positioned between the dummy core and the core circuitry, wherein the exposed non-conductive layer has an exposed surface that is smooth.

US Pat. No. 9,999,134

SELF-DECAP CAVITY FABRICATION PROCESS AND STRUCTURE

Multek Technologies Limit...

1. A printed circuit board comprising: a. a laminated stack comprising a plurality of non-conductive layers and a plurality of conductive layers, wherein a recessed cavity is formed in the laminated stack, the recessed cavity having cavity side walls and a cavity bottom surface, further wherein inner core circuitry is formed on the cavity bottom surface; b. a photo imageable polymer structure formed within the laminated stack, wherein the photo imageable polymer structure is a solder mask frame, further wherein the photo imageable polymer structure forms a perimeter boundary of the recessed cavity within the cavity side walls adjacent to the cavity bottom surface; and c. a protective film on the photo imageable polymer structure and formed within the laminated stack.

US Pat. No. 10,123,603

DIFFUSE FIBER OPTIC LIGHTING FOR LUGGAGE

Multek Technologies Limit...

1. A luggage lighting system comprising:a. piece of luggage having an outer surface, wherein the outer surface includes one or more seams; and
b. a lighting module coupled to the piece of luggage, wherein the lighting module comprises a light source and a light diffuser, further wherein the light diffuser is coupled to the outer surface at or adjacent to, and in physical contact with, at least one of the one or more seams of the luggage, wherein the lighting module further comprises a proximity indicator that indicates that the luggage is in proximity of a remote control source.

US Pat. No. 10,321,560

DUMMY CORE PLUS PLATING RESIST RESTRICT RESIN PROCESS AND STRUCTURE

Multek Technologies Limit...

1. A printed circuit board comprising:a. a rigid printed circuit board portion comprising a laminated stack of a plurality of non-conducting layers and a plurality of conductive layers, wherein the laminated stack further comprises a first portion of an inner core structure; and
b. a semi-flexible printed circuit board portion comprising a second portion of the inner core structure and exposed plating resist, wherein the inner core structure is a continuous structure that extends through both the rigid printed circuit board portion and the semi-flexible printed circuit board portion, further wherein the second portion of the inner core structure comprises exposed inner core circuitry, wherein the plating resist is limited to the semi-flexible printed circuit board portion of the printed circuit board and is limited to contacting a side wall of the rigid circuit board portion corresponding to a non-conducting layer of the rigid printed circuit board portion and the second portion of the inner core structure immediately adjacent the side wall of the rigid circuit board portion, further wherein the inner core structure comprises an inner core non-conductive layer having a first surface and a second surface opposite the first surface, and the first surface and the second surface of the inner core non-conductive layer form a continuous planar surface across the entire semi-flexible printed circuit board portion.

US Pat. No. 10,292,279

DISCONNECT CAVITY BY PLATING RESIST PROCESS AND STRUCTURE

Multek Technologies Limit...

1. A printed circuit board comprising:a. a laminated stack comprising a plurality of non-conducting layers and a plurality of conductive layers;
b. a via formed from an outer surface of the laminated stack and terminating within the laminated stack at a terminating end; and
c. a disconnect cavity at the terminating end of the via, wherein the disconnect cavity comprises a bottom surface that forms a closed end of the disconnect cavity and disconnect cavity side walls, further wherein the bottom surface and the disconnect cavity side walls are free of conductive plating.

US Pat. No. 10,458,778

INLINE METROLOGY ON AIR FLOTATION FOR PCB APPLICATIONS

Multek Technologies Limit...

1. A measurement system comprising:a. a printed circuit board panel comprising a substrate having a first side and a second side opposing the first side, wherein the first side comprises an insulating layer with a surface feature positioned on the insulating layer, wherein the surface feature is a conductive patterned interconnect;
b. a light emitter and detector device comprising a light source and a sensor, wherein the light emitter and detector device is positioned relative to the printed circuit board panel such that a light beam output from the light source impinges one or more sample points on the first side of the substrate, further wherein the sensor is configured to receive a reflected light corresponding to the light beam;
c. a movement and alignment apparatus coupled to the printed circuit board panel and the light emitter and detector device, wherein the movement and alignment apparatus is configured to provide relative movement between the light emitter and detector device and the printed circuit board panel and to scan the light beam over at least a portion of the first side of the printed circuit board panel; and
d. a controller configured to receive data from the sensor corresponding to the received reflected light and to determine a distance measurement corresponding to each sample point, and to determine a relative thickness of the printed circuit board panel and a height of the surface feature.

US Pat. No. 10,772,220

DUMMY CORE RESTRICT RESIN PROCESS AND STRUCTURE

Multek Technologies Limit...

1. A method of manufacturing a printed circuit board comprising:a. forming an inner core structure having an inner core circuitry on at least one surface of the inner core structure;
b. applying a coverlay material over the inner core circuitry;
c. forming a printed circuit board stack up, wherein the printed circuit board stack up comprises the inner core structure, a dummy core, one or more non-conductive layers and one or more conductive layers, wherein the dummy core is a metal clad base material, wherein the dummy core is stacked on the coverlay material;
d. laminating the printed circuit board stack up, thereby forming a laminated stack;
e. forming a depth controlled rout from a surface of the laminated stack to the dummy core and around a perimeter of the dummy core, wherein a portion of the laminated stack within the perimeter of the rout and to a depth including the dummy core forms a laminated stack cap;
f. removing the laminated stack cap, thereby exposing the coverlay material and forming a flexible portion of the printed circuit board.

US Pat. No. 10,712,398

MEASURING COMPLEX PCB-BASED INTERCONNECTS IN A PRODUCTION ENVIRONMENT

Multek Technologies Limit...

1. A method of testing a printed circuit board, the method comprising:a. defining a specific interconnect structure of the printed circuit board to be tested;
b. defining a predetermined reflection coefficient signature corresponding to the specific interconnect structure;
c. defining a reflection envelope around the reflection coefficient signature, wherein the reflection envelope defines tolerance boundaries on both sides of the reflection coefficient signature;
d. measuring a reflection coefficient for the specific interconnect structure to determine a measured reflection coefficient curve corresponding to the specific interconnect structure; and
e. comparing the measured reflection coefficient curve to the reflection envelope, wherein if all values of the measured reflection coefficient curve are within the reflection envelope then the specific interconnect structure passes the test, and if one or more values of the measured reflection coefficient curve are not within the reflection envelope then the specific interconnect structure fails the test.