US Pat. No. 9,408,272

LIGHT DRIVER AND THE CONTROLLER AND DRIVING METHOD THEREOF

Chengdu Monolithic Power ...

18. A driving method of providing a driving current to drive a light device, comprising:
receiving a dimming signal and a thermal signal;
converting the dimming signal and the thermal signal respectively into a converted dimming signal and a converted thermal
signal;

selecting the smaller one of the converted dimming signal and the converted thermal signal;
generating a reference signal based on the selected smaller signal;
receiving a feedback signal representative of the driving current; and
generating a control signal based on the reference signal and the feedback signal to regulate the driving current.

US Pat. No. 9,479,046

MULTI-MODE PFC CONTROL AND CONTROL METHOD THEREOF

CHENGDU MONOLITHIC POWER ...

1. A Power Factor Correction (PFC) circuit comprising:
a switching circuit comprising a power switch, the switching circuit having an input terminal configured to receive an input
voltage, the switching circuit further having an output terminal configured to provide an output voltage for supplying a load;

an on time control circuit configured to provide an on time control signal for controlling an on time period of the power
switch;

a first off time control circuit configured to provide a first off time control signal;
a second off time control circuit configured to provide a second off time control signal; and
a logic circuit configured to selectively control the power switch working under a Continuous Conduction Mode (CCM) or a Discontinuous
Conduction Mode (DCM) based on a load condition of the load, and wherein the logic circuit is configured to receive the on
time control signal, the first off time control signal and the second off time control signal, and to generate a switching
control signal that is coupled to the power switch; wherein

when working under CCM, the power switch is turned on in responding to the first off time control signal, and is turned off
in responding to the on time control signal; and

when working under DCM, the power switch is turned on in responding to the second off time control signal, and is turned off
in responding to the on time control signal.

US Pat. No. 9,431,913

VOLTAGE DETECTING CIRCUIT FOR SWITCHING CONVERTERS AND THE METHOD THEREOF

Chengdu Monolithic Power ...

1. A voltage detecting circuit used with a switching converter, wherein the switching converter comprises an energy storage
component, a first power switch and a second power switch coupled to the energy storage component, and the energy storage
component stores energy when the first power switch is ON and provides energy to a load when the first power switch is OFF,
the voltage detecting circuit comprising:
a sample and hold circuit having an input terminal and an output terminal, wherein the input terminal is coupled to a connection
node of the energy storage component and the first power switch, and wherein the sample and hold circuit samples the voltage
at the connection node when the first power switch is OFF and the second power switch is ON, and provides a sampled signal
at the output terminal; and

an average circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal
of the sample and hold circuit to receive the sampled signal, and the average circuit performs an arithmetic operation on
the sampled signal and provides a detecting signal based on the sampled signal at the output terminal, wherein the detecting
signal is in proportional to the output voltage;

wherein the average circuit comprises:
a first switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to
the output terminal of the sample and hold circuit, and the control terminal is configured to receive a first control signal,
and wherein the first switch is turned ON by the first control signal when the first power switch is ON, and is turned OFF
by the first control signal when the first power switch is OFF;

a second switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to
the second terminal of the first switch, the second terminal is coupled to a reference ground, and the control terminal is
configured to receive a second control signal, and wherein the second switch is turned ON by the second control signal when
the second power switch is ON, and is turned OFF by the second control signal when the second power switch is OFF; and

a low pass filter circuit having an input terminal coupled to the connection node of the first switch and the second switch,
and an output terminal configured to provide a detecting signal indicating the output voltage of the switching converter.

US Pat. No. 9,449,546

LED DRIVER, LED DRIVING METHOD AND CONTROLLER FOR LED DRIVER

CHENGDU MONOLITHIC POWER ...

1. A control circuit used in a LED driver, the LED driver includes an input port configured to receive an input signal, an
output port configured to provide a driving voltage to a LED string, an intermediate node, a step-up stage having a first
power switch coupled between the input port and the intermediate node, and a step-down stage having a second power switch
and a third power switch coupled between the intermediate node and the output port, the control circuit comprising:
a phase detector, having an input terminal coupled to the input port to receive the input signal, a first output terminal
configured to generate a phase detecting signal indicative of phase information of the input signal, and a second output terminal
configured to generate a cycle detecting signal indicative of cycle information of the input signal, wherein the cycle detecting
signal is a short pulse signal;

a step-up comparator, having a first input terminal configured to receive a reference signal, a second input terminal configured
to receive a voltage feedback signal indicative of a voltage at the Intermediate node, and an output terminal configured to
generate a step-up comparison signal based on the reference signal and the voltage feedback signal;

a logical OR unit, having a first input terminal coupled to the second output terminal of the phase detector to receive the
cycle detecting signal, a second input terminal coupled to the output terminal of the step-up comparator to receive the step-up
comparison signal, and an output terminal configured to generate a step-up enable signal by executing logical OR operation
on the cycle detecting signal and the step-up comparison signal;

a step-up controller, coupled to the logical OR unit to receive the step-up enable signal, to get enabled or disabled by the
step-up enable signal, and to generate a step-up control signal, the step-up control signal being used to control the first
power switch;

a logical AND unit, having a first input terminal coupled to the first output terminal of the phase detector to receive the
phase detecting signal, a second input terminal coupled to the step-up comparator to receive the step-up comparison signal,
and an output terminal configured to generate a logical AND signal by executing logical AND operation on the phase detecting
signal and the step-up comparison signal;

an average circuit, coupled to the output terminal of the logical AND unit to receive the logical AND signal and to generate
an average signal; and

a step-down controller, having a first input terminal configured to receive a LED current sense signal indicative of a current
flowing through the LED string, a second input terminal coupled to the average circuit to receive the average signal, and
an output terminal configured to generate a step-down control signal to control the second power switch and the third power
switch.

US Pat. No. 9,350,340

POWER LOSS CONTROL METHOD FOR METAL-OXIDE-SEMICONDUCTOR UNIT AND ASSOCIATED APPARATUS

Chengdu Monolithic Power ...

9. A power loss control apparatus for a MOS unit, wherein the MOS unit comprises a plurality of MOS devices coupled in parallel,
the power loss control apparatus comprising:
a load condition detecting device, configured to detect a load condition of the MOS unit and designate the load condition
as either a light load condition or a heavy load condition; and

a power loss controlling device, configured to adjust a driving loss of the MOS unit based on the load condition designation;
and wherein the driving loss of the MOS unit is configured to decrease when the MOS unit is under a designated light load
condition; wherein

the power loss controlling device comprises a driving voltage controlling device, wherein the driving voltage controlling
device is configured to decrease voltage of a driving signal of the MOS unit under the designated light load condition.

US Pat. No. 9,485,819

SINGLE STAGE LED DRIVER SYSTEM, CONTROL CIRCUIT AND ASSOCIATED CONTROL METHOD

CHENGDU MONOLITHIC POWER ...

1. A light-emitting element driver system, comprising:
a power conversion circuit, configured to provide a first signal, wherein the power conversion circuit comprising:
a primary circuit, comprising a first switch, the first switch is turned ON and OFF in each switching period of the primary
circuit to provide an AC signal;

a transformer, comprising a primary winding, a first secondary winding and a second secondary winding, the primary winding
is coupled to the primary circuit to receive the AC signal;

a first rectified circuit, coupled to the first secondary winding and having an output terminal;
a second rectified circuit, coupled to the second secondary winding and having an output terminal configured to provide the
first signal;

a second switch, having a first terminal and a second terminal, wherein the first terminal is coupled to the output terminal
of the first rectified circuit and the second terminal is configured to provide a second signal; and

a control circuit, configured to provide a first control signal to control the power conversion circuit and a second control
signal to control the second switch; wherein

when a dimming signal is in a first state, the first signal is regulated by turning ON and turning OFF the first switch, meanwhile
the second signal is regulated by turning ON and turning OFF the second switch, and during each switching period of the primary
circuit, the second switch is turned OFF in response to the turning OFF of the first switch.

US Pat. No. 9,429,970

POWER SUPPLY SYSTEM, ASSOCIATED CURRENT RIPPLE SUPPRESSION CIRCUIT AND METHOD

CHENGDU MONOLITHIC POWER ...

1. A power supply system, comprising:
a current source having an output, wherein the output of the current source is configured to provide an output current;
a load having a first end and a second end, wherein the first end of the load is coupled to the output of the current source,
and wherein the current source is configured to supply the load with the output current; and

a current ripple suppression circuit having a first end and a second end, wherein the first end of the current ripple suppression
circuit is coupled to the second end of the load, and the second end of the current ripple suppression circuit is coupled
to a reference ground;

wherein the current ripple suppression circuit is configured to suppress the current ripple in the output current and adaptively
adjust the output current of the current source at a predetermined current level by comparing the voltage at the first end
of the current ripple suppression circuit with a reference voltage, and wherein when the voltage at the first end of the current
ripple suppression circuit is higher than the reference voltage, the current ripple suppression circuit is configured to increase
a current flowing through the load, and when the voltage at the first end of the current ripple suppression circuit is lower
than the reference voltage, the current ripple suppression circuit is configured to decrease the current flowing through the
load.

US Pat. No. 9,148,049

DISCHARGE CIRCUITS FOR EMI FILTERS CAPACITORS AND METHODS THEREOF

Chengdu Monolithic Power ...

1. A discharge circuit for an EMI filter capacitor, wherein the EMI filter capacitor is coupled between input terminals of
a switching converter, the discharge circuit comprises:
a detecting circuit configured to detect whether an electrical source is coupled to the input terminals of the switching converter,
and configured to generate a flag signal based on the detection; and

a current source having a first terminal and a second terminal, wherein the first terminal is coupled to the input terminals
of the switching converter;

a first switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to
the second terminal of the current source, the second terminal is coupled to ground, and the control terminal is coupled to
the detecting circuit to receive the flag signal;

a second switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to
the second terminal of the current source and the first terminal of the first switch, the second terminal is coupled to a
power supply capacitor, and the control terminal is coupled to the detecting circuit to receive the flag signal; and

an under voltage lock out circuit having an input terminal and an output terminal, wherein the input terminal is coupled to
the first terminal of the first switch, and wherein the under voltage lock out circuit compares the voltage across the first
switch with a first threshold voltage and a second threshold voltage, and generates a lock out signal at the output terminal
to turn on or turn off the current source; wherein

when the electrical source is uncoupled from the input terminals of the switching converter, the first switch is turned on
and the second switch is turned off, the EMI filter capacitor is discharged by the current source; when the electrical source
is coupled to the input terminals of the switching converter, the first switch is turned off and the second switch is turned
on, the current source is configured to provide a power supply voltage across the power supply capacitor.

US Pat. No. 9,345,081

LED DRIVER SYSTEM, CONTROLLER AND ASSOCIATED METHOD

Chengdu Monolithic Power ...

1. A light emitting diode (LED) driver system, comprising:
a LED converter at least comprising a main switch, the LED converter configured to convert an input voltage to an output voltage
to drive a LED load;

a sensing circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the LED load,
the sensing circuit configured to generate a feedback signal on the output terminal according to a load current through the
LED load;

an over-shoot detecting circuit coupled to the sensing circuit and further receiving a second reference signal, the over-shoot
detecting circuit configured to generate an over-shoot signal according to the load current and the second reference signal;

a logic circuit configured to receive the over-shoot signal and a control signal, and to generate a switching signal accordingly
to control the main switch ON and OFF, wherein the control signal is generated according to the feedback signal and a first
reference signal; and

wherein the second reference signal is larger than the first reference signal.

US Pat. No. 9,425,689

LOAD REGULATION COMPENSATION MODULE AND SWITCHING CONVERTER COMPRISING THE SAME

Chengdu Monolithic Power ...

1. A load regulation compensation module for a switching converter, wherein the switching converter comprises a switch module
referenced to an internal reference ground connected to a package ground pin via a resistive component, and wherein the switch
module is switched on and off based on a feedback signal indicative of an output voltage of the switching converter and a
first reference signal indicative of a desired value of the output voltage, and wherein the on and off switching of the switch
module generates a switching current flowing through the resistive component, resulting in an average offset voltage between
the internal reference ground and the package ground pin, and wherein the load regulation compensation module comprises:
a current sense circuit, configured to sense the switching current flowing through the resistive component, and to provide
a sense signal indicative of that switching current;

a first filtering circuit, configured to receive the sense signal, and filter the sense signal to provide a first average
signal indicative of an average of the sense signal;

a gain circuit, configured to receive the first average signal, and to apply a first gain to the first average signal to generate
a compensation signal; and

a superposing circuit, configured to receive the compensation signal and a second reference signal having a bandgap reference
voltage with respect to the internal reference ground, and to compensate the second reference signal with the compensation
signal to generate the first reference signal, so that the average offset voltage is substantially cancelled out from the
first reference signal with respect to the package ground pin.

US Pat. No. 9,172,300

CHARGE-PUMP VOLTAGE DIVIDER AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A charge-pump voltage divider, comprising:
a first switch, a second switch, a third switch and a fourth switch sequentially connected in series between an input terminal
and ground;

a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled
to a common connection of the first switch and the second switch, and the second terminal of the first capacitor is coupled
to a common connection of the third switch and the fourth switch;

a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled
to a common connection of the second switch and the third switch, and the second terminal of the second capacitor is connected
to ground;

a start-up circuit comprising the first switch;
a load control switch having a first terminal and a second terminal, wherein the first terminal of the load control switch
is coupled to a load of the charge-pump voltage divider, and the second terminal of the load control switch is connected to
ground; and

a logic controller, configured to provide a plurality of control signals to the start-up circuit, the second switch, the third
switch, the fourth switch and the load control switch according to an output voltage across the second capacitor of the charge-pump
voltage divider; and wherein

when the output voltage is lower than a threshold voltage, the plurality of control signals is configured to control the charge-pump
to operate in a start-up stage so as to turn the load control switch OFF to disconnect the load from the charge-pump voltage
divider, and to operate the first switch in a linear region;

when the output voltage is higher than the threshold voltage, the plurality of control signals is configured to turn the load
control switch ON to connect the load to the charge-pump voltage divider, and is further configured to switch the first switch
ON and OFF alternately; and wherein

during the start-up stage of the charge-pump voltage divider, the plurality of control signals is configured to maintain the
second switch and the fourth switch ON, and maintain the third switch OFF.

US Pat. No. 9,420,648

TIMING CIRCUITS AND DRIVING CIRCUITS USED IN LIGHTING SYSTEMS

Chengdu Monolithic Power ...

1. A timing circuit, comprising:
a first logic circuit having an input terminal, a first output terminal and a second output terminal, wherein the input terminal
is configured to receive a detecting signal, and wherein based on a falling edge of the detecting signal, the first logic
circuit provides a first logic signal and a second logic signal at the first output terminal and the second output terminal
respectively;

a first counter having a control terminal, a first output terminal and a second output terminal, wherein the control terminal
is coupled to the second output terminal of the first logic circuit for receiving the second logic signal, and wherein based
on the second logic signal, the first counter generates a first counting signal at the first output terminal and a second
counting signal at the second output terminal, and wherein a counting period of the first counting signal is longer than a
counting period of the second counting signal;

a latching circuit having a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled
to the first output terminal of the first logic circuit for receiving the first logic signal, and wherein the input terminal
is coupled to the first output terminal of the first counter for receiving the first counting signal, and wherein based on
the first logic signal, the latching circuit samples and holds the first counting signal and provides a third counting signal
at the output terminal; and

a judging circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal
is coupled to the second output terminal of the first counter for receiving the second counting signal, the second input terminal
is coupled to the output terminal of the latching circuit for receiving the third counting signal, and wherein the judging
circuit detects whether the second counting signal is equal to the third counting signal and provides a timing signal at the
output terminal accordingly.

US Pat. No. 9,236,801

SWITCH MODE POWER SUPPLY, CONTROL CIRCUIT AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A control circuit for controlling a switch mode power supply, the switch mode power supply having a first switch with a
control terminal, a second switch, and an output terminal configured to provide an output voltage, wherein the control circuit
comprising:
an input terminal, configured to receive a voltage feedback signal representing the output voltage;
an output terminal, configured to provide a first switching control signal to the control terminal of the first switch to
turn ON and turn OFF the first switch; and

a zero-crossing detector, having an output terminal configured to provide a zero-crossing signal, wherein the zero-crossing
signal becomes effective when a current flowing through the second switch is less than a bias current, and the zero-crossing
signal becomes ineffective when the current flowing through the second switch is larger than the bias current; and wherein

when the switch mode power supply works in a power saving mode, the control circuit is configured to turn ON the first switch
if the voltage feedback signal is less than a reference voltage and the zero-crossing signal is effective; and

when the switch mode power supply works in a normal mode, the control circuit is configured to turn ON the first switch if
the voltage feedback signal is less than the reference voltage.

US Pat. No. 9,450,052

EEPROM MEMORY CELL WITH A COUPLER REGION AND METHOD OF MAKING THE SAME

CHENGDU MONOLITHIC POWER ...

1. An electrically erasable programmable read only memory (EEPROM) cell formed in a semiconductor body having a top surface,
the EEPROM memory cell comprising:
a first well and a second well both adjacent to the top surface of the semiconductor body;
a drain and a source formed in the first well and spaced apart from each other, wherein a first channel region is defined
between the source and the drain;

a second channel region defined as extending from the top surface of the semiconductor body into the second well;
a floating gate insulatively formed over the first channel region and the second channel region and forming an uninterrupted
conducting path extending from the second well to the first well; and

at least one feeder region formed in the second well, wherein the at least one feeder region has a conductivity type opposite
to that of the second well and is configured to provide the majority carriers thereof to the second channel region so that
the portion of the second channel region proximate the top surface of the semiconductor body is inverted during an erase operation,
and wherein a portion of the at least one feeder region laterally extends below the floating gate, and the floating gate comprises
a region overlapping the at least one feeder region and a remaining region, and wherein the region of the floating gate overlapping
the at least one feeder region is doped with the same conductivity type as that of the at least one feeder region and the
remaining region of the floating gate is doped with the opposite conductivity type to that of the at least one feeder region.

US Pat. No. 9,407,155

ISOLATED SWITCHING CONVERTER WITH SECONDARY SIDE MODULATION AND CONTROL METHOD

Chengdu Monolithic Power ...

11. An isolated switching converter, comprising:
a transformer having a primary winding and a secondary winding, wherein the secondary winding is coupled to provide an output
signal to a load;

a primary switch coupled between the primary winding and a primary reference ground;
a secondary switch coupled between the secondary winding and the load;
an error amplifying circuit configured to receive a reference signal and a feedback signal indicative of the output signal,
wherein based on the difference between the reference signal ad the feedback signal, the error amplifying circuit generates
a compensation signal;

a modulation signal generator configured to generate a modulation signal;
a first comparison circuit coupled to the error amplifying circuit and the modulation signal generator, wherein the first
comparison circuit compares the compensation signal with the modulation signal and generates a first comparison signal;

a primary off detection circuit configured to detect whether the primary switch is off and to generate a primary off detection
signal;

a zero cross detection circuit configured to detect whether the current flowing the secondary switch crosses zero and generate
a zero cross detection signal;

a secondary logic circuit coupled to the first comparison circuit, the primary off detection circuit and the zero cross detection
circuit, wherein based on the first comparison signal, the primary off detection signal and the zero cross detection signal,
the secondary logic circuit generates a secondary control signal to control the secondary switch, and wherein the secondary
logic circuit turns on the secondary switch when the primary off detection circuit detects the primary switch is off, and
turns off the secondary switch when the compensation signal is smaller than the modulation signal or a zero cross of the current
flowing through the secondary switch is detected;

an isolation circuit coupled to the first comparison circuit to receive the first comparison signal, wherein based on the
first comparison signal, the isolation circuit generates a synchronous signal electrically isolated from the first comparison
signal;

a threshold generator coupled to the isolation circuit to receive the synchronous signal, wherein based on the synchronous
signal, the threshold generator generates a first threshold voltage;

a second comparison circuit coupled to the threshold generator, wherein the second comparison circuit compares a primary current
sensing signal indicative of the current flowing through the primary switch with the first threshold voltage and generates
a second comparison signal; and

a primary logic circuit coupled to the isolation circuit and the second comparison circuit, wherein based on the synchronous
signal and the second comparison signal, the primary logic circuit generates a primary control signal to control the primary
switch, and wherein the primary logic circuit turns on the primary switch in accordance with the synchronous signal, and turns
off the primary switch when the primary current sensing signal is larger than the first threshold voltage.

US Pat. No. 9,401,647

SWITCHING MODE POWER SUPPLY AND THE CONTROL METHOD THEREOF

Chengdu Monolithic Power ...

1. A switching mode power supply, comprising:
a power switch;
an energy storage component coupled to the power switch, the energy storage component storing energy when the power switch
is on and transferring energy when the power switch is off;

a current sense resistor coupled between the power switch and a ground reference to generate a current sense signal based
on a current flowing through the power switch;

a mode select resistor having a first terminal and a second terminal, the first terminal coupled to a connection node of the
current sense resistor and the power switch;

a ZCD (zero cross detecting) circuit configured to generate a ZCD signal based on a voltage across the power switch;
a first diode having an anode terminal and a cathode terminal, the anode terminal coupled to the ZCD circuit to receive the
ZCD signal; and

a control circuit configured to provide a switch control signal to control the on and off of the power switch, the control
circuit having a multi-function pin coupled to the second terminal of the mode select resistor and the cathode terminal of
the first diode;

wherein: in a startup period of the switching mode power supply, the control circuit compares a signal received by the multi-function
pin with a mode control reference signal, and determines a work mode of the switching mode power supply based on a comparison
result; in a normal operation period of the switching mode power supply, the control circuit compares the signal received
by the multi-function pin with a peak current signal when the power switch is on, and compares the signal received by the
multi-function pin with a ZCD reference signal when the power switch is off, and controlling the on and off of the power switch
based on comparison results.

US Pat. No. 9,431,906

VOLTAGE CONVERTER CIRCUIT AND ASSOCIATED CONTROL METHOD TO IMPROVE TRANSIENT PERFORMANCE

Chengdu Monolithic Power ...

1. A switch-mode converter circuit for converting an input voltage to an output voltage, the converter circuit comprising:
a primary switch;
an error amplifier, having two inputs and an output, wherein the two inputs respectively receive a feedback signal of the
output voltage and a reference signal, and wherein the output generates an error signal;

a proportional amplifier, having two inputs and an output, wherein the two inputs respectively receive the output voltage
and the error signal, and wherein the output generates a gain signal, wherein the gain signal proportionally declines in response
to an increase of the output voltage;

a first comparator, having two inputs and an output, wherein the two inputs respectively receive the gain signal and a comparison
signal, and wherein the output generates a pulse signal; and

a timer, having an input and an output, wherein the input is coupled to the output of the first comparator, and wherein the
output generates a timing signal to indicate an on time and an off time of the primary switch;

wherein either the gain signal or the comparison signal comprises a ramp component, wherein the ramp component at least depends
on the output voltage, and wherein the on time is constant.

US Pat. No. 9,331,583

SWITCH MODE POWER SUPPLY, CONTROL CIRCUIT AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A control circuit for controlling a switch mode power supply, the switch mode power supply having an output terminal configured
to provide an output voltage and having a first switch with a control terminal, wherein the control circuit comprising:
a mode management unit, having an input terminal and an output terminal, wherein the output terminal of the mode management
unit is configured to provide a mode control signal;

a skip cycle mode control unit, having an input terminal and an output terminal, wherein the input terminal of the skip cycle
mode control unit is configured to receive a feedback signal representing the output voltage, wherein the output terminal
of the skip cycle mode control unit is configured to provide a first pulse signal having a first frequency and a second frequency,
wherein the first frequency and the second frequency are predetermined;

a normal mode control unit, having an output terminal configured to provide a second pulse signal; and
a drive signal management unit, having a first input terminal, a second input terminal, a third input terminal and an output
terminal, wherein the first input terminal of the drive signal management unit is coupled to the output terminal of the mode
management unit, the second input terminal of the drive signal management unit is coupled to the output terminal of the skip
cycle mode control unit, the third input terminal of the drive signal management unit is coupled to the output terminal of
the normal mode control unit, and the output terminal of the drive signal management unit is configured to provide a switching
control signal to the control terminal of the first switch based on the first pulse signal, the second pulse signal and the
mode control signal; wherein

the input terminal of the mode management unit is configured to receive the switching control signal, and the output terminal
of the mode management unit is configured to provide the mode control signal via comparing a frequency of the switching control
signal with a frequency threshold.

US Pat. No. 9,179,519

PHASE-SHIFT DIMMING FOR LED CONTROLLER AND THE METHOD THEREOF

Chengdu Monolithic Power ...

1. A phase-shift dimming control circuit, comprising:
a frequency multiply circuit configured to receive a PWM input signal to provide a square signal having a frequency at least
two times higher than that of the PWM input signal;

a delayed rising signal generator configured to receive the square signal and the PWM input signal to provide a plurality
of set signals having pulses;

a delayed falling signal generator configured to receive the square signal and the PWM input signal to provide a plurality
of reset signals having pulses;

a plurality of latches configured to respectively receive the plurality of pairs of set signal and reset signal to generate
a corresponding plurality of PWM output signals, each of the PWM output signals having pulses, and wherein the rising edge
of the pulses of the PWM output signals is based on the corresponding set signal pulses, and the falling edge of the pulses
of the PWM output signals is based on the corresponding reset signal pulses;

wherein the delayed rising signal generator comprises:
a rising-edge pulse generator configured to receive the PWM input signal to provide a rising-edge pulse signal having a pulse
at every rising edge of the PWM input signal;

a rising-edge clock generator configured to receive the square signal to generate a rising clock signal having a cycle length
corresponding to a phase difference between two successive PWM output signals;

a counter configured to count the rising clock signal to generate a M bits binary digit signal, M being a positive integer;
and

an encoder configured to encode the M bits binary digit signal to 2M set signals.

US Pat. No. 9,418,983

SEMICONDUCTOR DEVICE AND ASSOCIATED METHOD FOR MANUFACTURING

CHENGDU MONOLITHIC POWER ...

1. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type and having an active cell area and a termination area;
a semiconductor transistor, formed in the active cell area and having a drain region, a gate region, and a source region;
a source metal, formed over the active cell area of the substrate and electrically coupled to the source region;
a gate metal, formed over the termination area of the substrate and electrically coupled to the gate region, wherein the gate
metal is formed around the source metal and is separated from the source metal with a gap; and

an ESD protection structure, formed atop the termination area of the semiconductor substrate and disposed substantially between
the source metal and the gate metal, wherein the ESD protection structure comprises a first isolation layer and an ESD protection
layer, and wherein the first isolation layer is disposed between the ESD protection layer and the substrate to isolate the
ESD protection layer from the substrate; and

wherein the ESD protection structure has a first portion adjacent to the source metal, a second portion adjacent to the gate
metal and a middle portion between and connecting the first portion and the second portion, wherein the middle portion has
a greater thickness than a thickness at any point along the first portion and the second portion.

US Pat. No. 9,331,509

CHARGER SYSTEM, DIGITAL INTERFACE CIRCUIT AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A charger system, comprising a power supply circuit, a load, a battery, a system management bus (SMBus) host, a control
circuit, a first switch and a second switch, wherein the control circuit comprises a digital interface circuit, and wherein
the digital interface circuit comprises an N-bit control register, and wherein N is a positive integer no less than 2, and
wherein the N-bit control register comprises:
a primary state machine, at a first portion of addresses of the N-bit control register, configured to instruct operation statuses
of the SMBus host;

a secondary state machine, at a second portion of addresses of the N-bit control register, configured to instruct data bit
of transmission of a corresponding control instruction under each of the operation statuses of the SMBus host;

wherein the charger system further comprises a data line and a clock line, wherein the power supply circuit is coupled to
a first end of the first switch, a second end of the first switch is coupled to a first end of the second switch and the load,
a second end of the second switch is coupled to a first end of the battery, the battery is further coupled to the SMBus host
through the data line and the clock line, the SMBus host is further configured to provide a battery information signal to
the control circuit through the data line and the clock line, and the control circuit is further configured to provide a control
signal to control the ON and OFF of the first switch and the second switch;

the digital interface circuit further comprises a control bus, a data register and a data bus, wherein the control register
is configured to receive information from the clock line and provide the control instruction according to the primary state
machine and the secondary state machine; and

wherein the control bus is further coupled to the data bus, enabling the control instruction to control data exchange between
the data register and the data line through the data bus, and to decide the ON and OFF of the first switch and the second
switch.

US Pat. No. 9,106,131

HIGH SIDE BUCK CONVERTERS AND CONTROL METHODS THEREOF

Chengdu Monolithic Power ...

1. A controller used in a high side buck converter, wherein the high side buck converter comprises a high side switching transistor
and a low side switching transistor, and is configured to provide an output voltage at an output terminal, the high side and
low side switching transistors are coupled together to form a switch node and the switch node is configured as the reference
ground of the controller, wherein the controller comprises:
a sensing window generator configured to generate a sensing window signal;
an error amplifier a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein
the first input terminal is configured to receive a feedback signal of a sensing signal indicating the output voltage, the
second input terminal is configured to receive a reference signal, the third input terminal is coupled to the sensing window
generator to receive the sensing window signal, the output terminal is configured to provide an error signal, and wherein
the error amplifier is enabled to amplify the difference between the reference signal and the feedback signal during a sensing
window determined by the sensing window signal, and is disabled out of the sensing window;

a first comparator coupled to the sensor and the error amplifier, wherein the first comparator is configured to compare the
feedback signal with the error signal, and to generate a first comparison signal; and

an on-time signal generator coupled to the first comparator, wherein the on-time generator is configured to generate an on-time
signal based on the first comparison signal, so as to control the high side and low side switching transistors;
wherein the sensing window generator comprises:
a third comparator having a first input terminal, a second input terminal and an output terminal, wherein the second input
terminal is configured to receive a reference voltage;

a first current source having an input terminal and an output terminal, wherein the input terminal is configured to receive
a supply voltage, the output terminal is coupled to the first input terminal of the third comparator;

a first capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the first input
terminal of the third comparator, the second terminal is coupled to the reference ground;

a first switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to
the first input terminal of the third comparator, the second terminal is coupled to the reference ground, and the control
terminal is coupled to the on-time signal generator to receive the on-time signal;

a fourth comparator having a first input terminal, a second input terminal and an output terminal, wherein the second input
terminal is configured to receive a reference voltage;

a second current source having an input terminal and an output terminal, wherein the input terminal is configured to receive
a supply voltage, the output terminal is coupled to the first input terminal of the fourth comparator;

a second capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the first input
terminal of the fourth comparator, the second terminal is coupled to the reference ground;

a second switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to
the first input terminal of the fourth comparator, the second terminal is coupled to the reference ground, and the control
terminal is coupled to the on-time signal generator to receive the on-time signal;

a NOT gate having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of
the fourth comparator; and

an AND gate having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal
is coupled to the output terminal of the third comparator, the second input terminal is coupled to the output terminal of
the NOT gate, and the output terminal is configured to provide the sensing window signal.

US Pat. No. 9,059,667

CLASS D AUDIO AMPLIFIER WITH NOISE SUPPRESSION AND THE METHOD THEREOF

Chengdu Monolithic Power ...

1. A class D audio amplifier with noise suppression, comprising:
an audio control circuit having a first input terminal configured to receive an input signal, a second input terminal configured
to receive a reference signal, and a switching terminal configured to provide a switching signal based on the input signal
and the reference signal;

an input capacitor coupled between the input signal and the first input terminal of the audio control circuit;
an inductor having a first terminal and a second terminal, the first terminal coupled to the switching terminal of the audio
control circuit;

an output capacitor having a first terminal coupled to the second terminal of the inductor, and a second terminal coupled
to a load; and

a noise suppression circuit having a first terminal coupled to the first input terminal of the audio control circuit, and
a second terminal coupled to the switching terminal of the audio control circuit, wherein the noise suppression circuit charges
the input capacitor and the output capacitor to reach a preset value;

wherein the noise suppression circuit charges the input capacitor and the output capacitor with a current that is initially
increasing, then constant, and then decreasing in magnitude.

US Pat. No. 9,201,102

AC SIGNAL DETECTOR AND THE METHOD THEREOF

Chengdu Monolithic Power ...

1. An AC signal detector, comprising:
a rectify circuit having a first input terminal and a second input terminal configured to receive an AC signal, and an output
terminal configured to provide a rectified signal based on the AC signal;

a detecting circuit having an input terminal coupled to the output terminal of the rectify circuit to receive the rectified
signal, and an output terminal configured to provide a square signal based on the rectified signal; and

an unplug indicate circuit having an input terminal coupled to the detecting circuit to receive the square signal, and an
output terminal configured to provide an unplug indicate signal based on the square signal.

US Pat. No. 9,081,397

CONSTANT ON TIME MULTI-PHASE SWITCHING CONVERTER AND CONTROL METHOD THEREOF

Chengdu Monolithic Power ...

1. A controller used in a multi-phase switching converter, wherein the multi-phase switching converter comprises a plurality
of switching circuits, each of the plurality of switching circuits having an output terminal, and the output terminals are
coupled together to provide an output voltage, the controller comprises:
a comparing circuit coupled to the output terminals of the plurality of switching circuits, wherein based on a reference signal
and the output voltage, the comparing circuit generates a comparison signal; and

a control circuit coupled to the comparing circuit to receive the comparison signal, wherein based on the comparison signal,
the control circuit generates a plurality of control signals to turn on the plurality of switching circuits successively;
wherein

when the on-time of a current switching circuit of the plurality of switching circuits is longer than the difference between
a first time threshold and a second time threshold, the control circuit can turn on a following switching circuit of the plurality
of switching circuits based on the comparison signal only after the time from the current switching circuit being turned on
reaches the first time threshold; and

when the on-time of the current switching circuit is shorter than the difference between the first time threshold and the
second time threshold, the control circuit can turn on the following switching circuit based on the comparison signal only
after the off-time of the current switching circuit reaches a second time threshold, wherein the first time threshold is longer
than the second time threshold.

US Pat. No. 9,660,534

CONTROL CIRCUIT FOR MULTIPHASE SWITCHING CONVERTER TO REDUCE OVERSHOOT AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A control circuit for a multiphase switching converter, the multiphase switching converter having a plurality of switching
circuits and an output terminal configured to provide an output voltage, the control circuit comprising:
a first comparison circuit configured to provide a comparison signal based on a reference signal and the output voltage;
an overshoot control circuit configured to provide an overshoot control signal based on the output voltage and an overshoot
threshold, wherein the overshoot threshold is larger than the reference signal; and

a switching control circuit configured to provide a plurality of switching control signals to control the plurality of switching
circuits based on the comparison signal and the overshoot control signal, wherein the switching control circuit is configured
to turn ON the plurality of switching circuits successively based on the comparison signal; wherein

when the overshoot control signal indicates that the output voltage is overshooting, the switching control circuit is configured
to turn OFF a current switching circuit; and wherein

when the overshoot control signal indicates that the output voltage recovers from overshooting, the switching control circuit
is configured to turn ON the current switching circuit again for a first time period, wherein a sum of the first time period
and a second time period equals a predetermined value, and wherein the second time period is a time period that the current
switching circuit maintains ON uninterruptedly before the output voltage is detected overshooting.

US Pat. No. 9,401,648

CURRENT LIMIT MODULE AND CONTROL MODULE FOR POWER CONVERTERS AND ASSOCIATED METHOD

Chengdu Monolithic Power ...

1. A current limit module for a power converter, wherein the power converter comprises a main switch and is configured to
convert an input voltage to an output voltage based on driving the main switch to switch on and off in response to a pulse
width modulated signal, and wherein a switching current flows through the main switch, and wherein the percentage of the on
time of the main switch in a switching cycle is referred to as a duty cycle, the current limit module comprising:
a threshold compensation circuit having a first compensation input terminal, a second compensation input terminal and a compensation
output terminal, wherein the first compensation input terminal is configured to receive a first current limit threshold indicative
of a maximum allowable value of a peak value of the switching current, and wherein the second compensation input terminal
is configured to receive a threshold compensation signal indicative of the duty cycle, and wherein the threshold compensation
circuit is configured to superpose the threshold compensation signal with the first current limit threshold to provide a second
current limit threshold at the compensation output terminal; and

a current limit comparison circuit having a first comparison input terminal, a second comparison input terminal and a comparison
output terminal, wherein the first comparison input terminal is configured to receive a second current sense signal indicative
of the switching current with ramp compensation, and wherein the second comparison input terminal is configured to receive
the second current limit threshold, and wherein the current limit comparison circuit is configured to compare the second current
sense signal with the second current limit threshold to generate a second comparison signal at the comparison output terminal,
and wherein the second comparison signal triggers the pulse width modulated signal to turn the main switch off when the second
current sense signal exceeds the second current limit threshold.

US Pat. No. 9,455,625

SWITCHING CONVERTER WITH SLOPE COMPENSATION CIRCUIT

Chengdu Monolithic Power ...

1. A slope compensation circuit, comprising:
a first voltage source, having a first terminal and a second terminal, wherein the first voltage source is configured to provide
a first voltage signal;

a first operation circuit, having a first terminal, a second terminal and an output terminal, configured to provide a current
control signal according to the first voltage signal and a second voltage signal;

a first switch, having a first terminal and a second terminal, wherein the first terminal of the first switch is coupled to
the first terminal of the first voltage source;

a first capacitor, having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled
to the second terminal of the first switch, and wherein the second terminal of the first capacitor is coupled to the second
terminal of the first voltage source;

a second switch, having a first terminal and a second terminal, wherein the first terminal of the second switch is coupled
to the first terminal of the first capacitor; and

a first controlled current source, having a first terminal, a second terminal and a control terminal, wherein the first terminal
of the first controlled current source is coupled to the second terminal of the second switch, and wherein the second terminal
of the first controlled current source is coupled to the second terminal of the first capacitor, and wherein the control terminal
of the first controlled current source is coupled to the output terminal of the first operation unit, and wherein the first
controlled current source is configured to provide a first current signal according to the current control signal.

US Pat. No. 9,431,845

SWITCHING CHARGER, THE CONTROL CIRCUIT AND THE CONTROL METHOD THEREOF

CHENGDU MONOLITHIC POWER ...

1. A switching charger, comprising:
a control circuit configured to provide a control signal;
a power stage having a high-side power switch and a low-side power switch coupled in series, the high-side power switch and
the low-side power switch turned ON and OFF alternatively by the control signal;

an inductor having a first terminal coupled to the connection of the high-side power switch and the low-side power switch,
and a second terminal coupled to a load; and

an output capacitor having a first terminal coupled to the second terminal of the inductor, and a second terminal coupled
to a reference ground;

a current sense circuit integrated to the control circuit, wherein the current sense circuit has a first input terminal coupled
to the high-side power switch, a second input terminal coupled to the low-side power switch, a first output terminal configured
to generate a high-side current sense signal indicating the current flowing through the high-side power switch, and a second
output terminal configured to generate a low-side current sense signal indicating the current flowing through the low-side
power switch;

wherein the control circuit comprises:
a feedback amplifier having a first input terminal configured to receive a feedback signal indicating the charging voltage,
a second input terminal configured to receive a feedback reference signal, and an output terminal configured to generate a
amplified feedback signal based on the feedback signal and the feedback reference signal;

a select circuit having a first input terminal configured to receive a current reference signal, a second input terminal coupled
to the feedback amplifier to receive the amplified feedback signal, and an output terminal configured to generate a current
control signal based on the current reference signal and the amplified feedback signal, wherein the current control signal
is the lower value of the current reference signal and the amplified feedback signal;

a hysteretic control circuit having a first input terminal coupled to the output terminal of the select circuit to receive
the current control signal, a second input terminal configured to receive the input voltage, a third input terminal configured
to receive the charging voltage, a fourth input terminal coupled to the output terminal of the control circuit to receive
the control signal, and a fifth input terminal configured to receive a frequency control signal having pulses at moment when
the high-side power switch is turned ON, wherein based on the current control signal, the input voltage, the charging voltage,
the control signal and the frequency control signal, the hysteretic control circuit provides a lower limit signal via a first
output terminal, and a higher limit signal via a second output terminal;

a comparison circuit having a first input terminal coupled to the first output terminal of the hysteretic control circuit
to receive the lower limit signal, a second input terminal coupled to the second output terminal of the hysteretic control
circuit to receive the higher limit signal, a third input terminal coupled to the first output terminal of the current sense
circuit to receive the high-side current sense signal, a fourth input terminal coupled to the second output terminal of the
current sense circuit to receive the low-side current sense signal, and based on the lower limit signal, the higher limit
signal, the high-side current sense signal and the low-side current sense signal, the comparison circuit provides a set signal
via a first output terminal, and a reset signal via a second output terminal; and

a logic circuit having a set terminal coupled to the comparison circuit to receive the set signal, a reset terminal coupled
to the comparison circuit to receive the reset signal, and an output terminal configured to generate the control signal based
on the set signal and the reset signal.

US Pat. No. 9,362,823

SWITCH-MODE POWER SUPPLY, CHARGING CURRENT SOURCE AND ASSOCIATED METHOD

Chengdu Monolithic Power ...

1. A switch-mode power supply comprising a converter, a controller and a charging current source, wherein the switch-mode
power supply is configured to convert an input voltage to an output voltage, and wherein the charging current source comprises:
a multi-functional pin, coupled to the input voltage or a system reference ground via a first resistor, wherein the multi-functional
pin outputs a frequency signal, and an initial value of the frequency signal is generated according to the input voltage or
a zero voltage on the system reference ground;

a logic circuit coupled to the multi-functional pin, wherein the logic circuit generates a logic control signal according
to the initial value of the frequency signal and an enable signal, and wherein the logic control signal is coupled to the
controller configured to indicate either of two operation modes of the controller;

a first current source coupled to the logic circuit and the multi-functional pin, wherein the first current source generates
a first output current according to the frequency signal, the enable signal and the logic control signal;

a second current source coupled to the logic circuit and the multi-functional pin, wherein the second current source generates
a second output current according to the frequency signal, the enable signal and the logic control signal; and

wherein the first output current is incorporated with the second output current to comprise a charging current provided to
the controller, wherein the charging current is proportional to the input voltage.

US Pat. No. 9,282,606

DIMMER COMPATIBLE LED DRIVING APPARATUS WITH BLEEDING CIRCUIT

Chengdu Monolithic Power ...

1. An LED driving apparatus comprising:
a rectifier bridge having an output terminal, wherein the rectifier bridge is configured to generate a DC bus voltage at the
output terminal;

a bus capacitor coupled between the output terminal of the rectifier bridge and a reference ground;
a tank element having a first terminal and a second terminal, wherein the first terminal is coupled to the output terminal
of the rectifier bridge;

a first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled
to the second terminal of the tank element;

a second transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled
to the second terminal of the first transistor, the second terminal is coupled to the reference ground;

a bleeding circuit coupled between the second terminal of the first transistor and the reference ground, wherein the bleeding
circuit is configured to provide a bleeding current for the bus capacitor;

a voltage sensing circuit coupled to the output terminal of the rectifier bridge, wherein the voltage sensing circuit generates
a voltage sensing signal indicative of the DC bus voltage;

a bleeding control circuit coupled to the voltage sensing circuit, wherein based on the voltage sensing signal, the bleeding
control circuit generates a control signal to control the bleeding circuit;

a free-wheeling switch coupled between the tank element and LEDs; and
an output capacitor coupled to the LEDs in parallel.

US Pat. No. 9,083,245

SWITCHING POWER SUPPLY WITH OPTIMIZED THD AND CONTROL METHOD THEREOF

Chengdu Monolithic Power ...

1. A switching power supply, comprising:
a switching circuit having a main switch and a tank element, wherein the switching circuit converts an input voltage into
an output voltage through the ON and OFF switching of the main switch;

a current sensing circuit coupled to the switching circuit, wherein the current sensing circuit senses the input current of
the switching circuit and generates a current sensing signal representative of the input current;

a preprocessing circuit coupled to the switching circuit to receive the input voltage and the output voltage, wherein based
on the input voltage and output voltage, the preprocessing circuit generates a first multiplication input signal;

a first multiplier coupled to the preprocessing circuit to receive the first multiplication input signal, wherein the first
multiplier multiplies the first multiplication input signal by a second multiplication input signal and generates a first
product signal, wherein the second multiplication input signal is a compensation signal related to the output voltage, the
output current or the output power of the switching circuit;

a first comparing circuit coupled to the current sensing circuit and the first multiplier to receive the current sensing signal
and the first product signal, wherein the first comparing circuit compares the current sensing signal with the first product
signal and generates a first comparison signal; and

a logic circuit coupled to the first comparing circuit to receive the first comparison signal, wherein the logic circuit turns
off the main switch when the current sensing signal is larger than the first product signal.

US Pat. No. 9,263,876

MULTI-PHASE SWITCHING CONVERTER WITH OVER CURRENT PROTECTION AND CONTROL METHOD THEREOF

Chengdu Monolithic Power ...

1. A controller used in a multi-phase switching converter, wherein the multi-phase switching converter comprises a plurality
of switching circuits with each of the switching circuits having an output terminal, and each of the output terminals are
coupled together to provide an output voltage to a load, the controller is configured to generate a plurality of control signals
to control the plurality of switching circuits, wherein
when an over current condition is detected in one of the plurality of switching circuits, the controller skips the current
switching circuit with the detected over current condition and successively turns on the remaining plurality of switching
circuits that have not yet been turned on and where an over current condition has not been detected.

US Pat. No. 9,219,468

FAILURE DETECTOR CIRCUIT AND ASSOCIATED METHOD

Chengdu Monolithic Power ...

1. A failure detector circuit for detecting status of a protected circuit, the failure detector circuit comprising:
an enabling signal generator, generating a periodic enabling signal which has an operating cycle, configured to indicate an
enable time in every operating cycle;

a comparator circuit, having an enabling terminal, two input terminals and an output terminal, wherein the enabling terminal
is configured to receive the enabling signal, and wherein the two input terminals are configured to respectively receive an
output signal from the protected circuit and a reference signal, and wherein the output terminal is configured to provide
a comparative result signal according to the enabling signal, the output signal and the reference signal; and

a delay circuit, receiving the comparative result signal and detecting the comparative result signal for a given delay period,
generating a delay signal according to the comparative result signal, wherein the given delay period is larger than the operating
cycle.

US Pat. No. 9,362,824

CONSTANT ON-TIME CONTROL SWITCHING CONVERTER WITH DC CALIBRATION AND CONTROL CIRCUIT AND METHOD THEREOF

Chengdu Monolithic Power ...

1. A control circuit of a switching converter, wherein the switching converter comprises a switching circuit providing an
output voltage, the control circuit comprises:
a DC calibration circuit having a first input terminal, a second input terminal and an output terminal, wherein the first
input terminal and the second input terminal are configured to respectively receive a reference voltage and a sample signal
representative of the output voltage, and wherein the DC calibration circuit generates a calibrated reference voltage at the
output terminal based on the reference voltage and the sample signal, and wherein the DC calibration circuit further comprises:

a first amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal
and the second input terminal are configured to respectively receive the reference voltage and the sample signal, and the
first amplifier amplifies the difference between the reference voltage and the sample signal and generates an error current
at the output terminal;

a second amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is electrically coupled to the output terminal of the first amplifier to receive the error current, and the output
terminal is electrically coupled to the first input terminal of the second amplifier and the output terminal of the DC calibration
circuit;

a first resistor electrically coupled between the first input terminal and the second input terminal of the second amplifier;
a capacitor electrically coupled between the second input terminal of the second amplifier and a reference ground;
a third amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal
of the third amplifier is electrically coupled to the output terminal of the second amplifier, the second input terminal of
the third amplifier is configured to receive a bias voltage, and the output terminal of the third amplifier is electrically
coupled to the output terminal of the DC calibration circuit; and

a second resistor electrically coupled between the output terminal of the third amplifier and the first input terminal of
the first amplifier;

a comparison circuit electrically coupled to the DC calibration circuit, wherein the comparison circuit compares the sample
signal with the calibrated reference voltage and generates a comparison signal;

an on-time control circuit configured to generate an on-time control signal; and
a logic circuit electrically coupled to the comparison circuit and the on-time control circuit, wherein based on the on-time
control signal and the comparison signal, the logic circuit generates a control signal to control the switching circuit.

US Pat. No. 9,467,039

POWER SUPPLY SYSTEM WITH RIPPLE SUPPRESSION CIRCUIT AND RIPPLE SUPPRESSION METHOD THEREOF

CHENGDU MONOLITHIC POWER ...

1. A ripple suppression circuit, comprising:
a filter circuit having a first input terminal and an output terminal, wherein the first input terminal is coupled to a signal
source to receive a ripple signal, wherein based on the ripple signal, the filter circuit provides a filter signal at the
output terminal, and wherein the filter signal is the sum of the average value of the ripple signal and a positive bias signal;

a follower circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is coupled to the signal source to receive the ripple signal, the second input terminal is coupled to the output
terminal of the filter circuit to receive the filter signal, wherein based on the ripple signal and the filter signal, the
follower circuit provides an output signal at the output terminal, and wherein the output signal at least partially follows
the filter signal.

US Pat. No. 9,496,792

CONTROLLER WITH THERMAL BALANCE AND CONTROL METHOD THEREOF FOR MULTI-PHASE SWITCHING CONVERTERS

CHENGDU MONOLITHIC POWER ...

1. A controller used in a multi-phase switching converter, wherein the multi-phase switching converter comprises a plurality
of switching circuits, the controller comprises:
a bias current generator having a plurality of input terminals and a plurality of output terminals, wherein the plurality
of input terminals are respectively coupled to the plurality of switching circuits to receive a plurality of phase temperature
signals representative of the temperature of the plurality of switching circuits, and wherein based on the plurality of phase
temperature signals and a temperature reference signal, the bias current generator generates a plurality of bias current signals
at the plurality of output terminals;

a temperature balance modulating circuit coupled to the plurality of switching circuits to receive a plurality of phase current
signals representative of the output current of the plurality of switching circuits and coupled to the bias current generator
to receive the plurality of bias current signals, wherein the temperature balance modulating circuit is configured to generate
a plurality of on time signals based on the plurality of phase current signals, the plurality of bias current signals, a current
reference signal and a predetermined on time signal, wherein the temperature balance modulating circuit comprises:

a plurality of add-subtraction arithmetic units with each of the add-subtraction arithmetic units having a first input terminal,
a second input terminal, a third input terminal and an output terminal, wherein the first input terminal is configured to
receive the current reference signal, the second input terminal is coupled to the corresponding output terminal of the bias
current generator to receive the corresponding bias current signal, the third input terminal is coupled to the corresponding
switching circuit to receive the corresponding phase current signal, and wherein the add-subtraction arithmetic unit subtracts
the phase current signal from the sum of the bias current signal and the current reference signal, and generates a current
error signal at the output terminal;

a plurality of proportional integrators with each of the proportional integrators having an input terminal and an output terminal,
wherein the input terminal is coupled to the output terminal of the corresponding add-subtraction arithmetic unit to receive
the current error signal, and wherein the proportional integrator proportionally integrates the current error signal, and
generates a bias on time signal at the output terminal;

a plurality of adders with each of the adders having a first input terminal, a second input terminal and an output terminal,
wherein the first input terminal is coupled to the output terminal of the corresponding proportional integrator to receive
the bias on time signal, the second input terminal is coupled to receive the predetermined on time signal, and wherein the
adder adds the bias on time signal to the predetermined on time signal, and generates an on time signal at the output terminal;
and

a logic circuit coupled to the temperature balance modulating circuit to receive the plurality of on time signals, wherein
based on the plurality of on time signals, the logic circuit generates a plurality of control signals to control the plurality
of switching circuits.

US Pat. No. 9,245,647

ONE-TIME PROGRAMMABLE MEMORY CELL AND CIRCUIT

Chengdu Monolithic Power ...

1. A One-Time Programmable (OTP) memory cell, comprising:
a memory module having a first terminal and a second terminal, wherein the memory module is configured to store data;
a write module having a first input terminal, a second input terminal, a first output terminal and a second output terminal,
wherein the write module is configured to write data into the memory module, and wherein the first input terminal of the write
module is configured to receive a first write signal, and wherein the second input terminal of the write module is configured
to receive a second write signal, and wherein the first output terminal of the write module is configured to provide a first
write-in signal to the first terminal of the memory module, and wherein the second output terminal of the write module is
configured to provide a second write-in signal to the second terminal of the memory module, and wherein the first write signal
and the second write signal are logic complementary, and wherein the first write-in signal and the second write-in signal
represent the data needed to store in the memory module, and wherein the first write-in signal and the second write-in signal
are logic complementary;

a read module having a first input terminal, a second input terminal, a third input terminal, a first output terminal and
a second output terminal, wherein the read module is configured to read out data from the memory module, and wherein the first
input terminal of the read module is coupled to the first terminal of the memory module, and wherein the second input terminal
of the read module is coupled to the second terminal of the memory module, and wherein the third input terminal is configured
to receive a read signal, and wherein the first output terminal of the read module is configured to provide a first read-out
signal, and wherein the second output terminal of the read module is configured to provide a second read-out signal wherein
the read signal is an analog signal, and wherein the first read-out signal and the second read-out signal represent data stored
in the memory module, and wherein the first read-out signal and the second read-out signal are logic complementary;

a load module having a first input terminal, a second input terminal, a first output terminal and a second output terminal,
wherein the first input terminal of the load module is configured to receive a first load signal, and wherein the second input
terminal of the load module is configured to receive a second load signal, and wherein the first output terminal of the load
module is configured to provide a first load out signal, and wherein the second output terminal of the load module is configured
to provide a second load out signal, and wherein the first load signal and the second load signal are logic complementary,
and wherein the first load out signal and the second load out signal are logic complementary;

a first latch module having a first input terminal, a second input terminal, a first output terminal and a second output terminal,
wherein the first input terminal of the first latch module is configured to receive the first read-out signal of the read
module and/or the first load out signal of the load module, and wherein the second input terminal of the first latch module
is configured to receive the second read-out signal of the read module and/or the second load out signal of the load module,
and wherein the first output terminal of the first latch module is coupled to a first output terminal of the OTP memory cell
to provide a first output signal of the OTP memory cell, and wherein the second output terminal of the first latch module
is coupled to a second output terminal of the OTP memory cell to provide a second output signal of the OTP memory cell, and
wherein the first output signal of the OTP memory cell and the second output terminal of the OTP memory cell are logic complementary;
and

a first multiplexer having a first input terminal, a second input terminal, a third input terminal, a first output terminal
and a second output terminal, wherein the first input terminal of the first multiplexer is configured to receive the first
output signal of the OTP memory circuit, and wherein the second input terminal of the first multiplexer is configured to receive
the second output signal of the OTP memory circuit, and wherein the third input terminal of the first multiplexer is configured
to receive a control signal, and wherein the control signal is an analog signal, and wherein the first output terminal of
the first multiplexer is configured to provide a first output signal as the first write signal, and wherein the second output
terminal of the first multiplexer is configured to provide a second output signal as the second write signal.

US Pat. No. 9,231,574

POWER CONVERTER, CLOCK MODULE AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A power converter, comprising:
an input port configured to receive an input voltage;
an output port configured to provide an output voltage;
a switch module comprising a main switch configured to switch on and off in response to a pulse width modulated signal to
convert the input voltage into the output voltage; and

a control module having a first control input terminal, a second control input terminal, a third control input terminal and
a first control output terminal, wherein the first control input terminal is configured to receive a first feedback signal
indicative of the output voltage, and wherein the second control input terminal is configured to receive a second feedback
signal indicative of a switching current flowing through the switch module, and wherein the third control input terminal is
configured to receive a reference signal indicative of a desired value of the output voltage, and wherein

the control module is configured to provide an off trigger signal based on the first feedback signal, the second feedback
signal and the reference signal; and wherein

the control module is further configured to monitor a deviation of the output voltage from the desired value of the output
voltage, and to compare the deviation with a first predetermined threshold window to generate a clock control signal, wherein
the clock control signal is configured to control the generation of a clock signal, and wherein

the control module is further configured to provide the pulse width modulated signal based on the off trigger signal and the
clock signal, wherein the pulse width modulated signal is configured to drive the main switch to switch on in response to
the clock signal, and wherein the pulse width modulated signal is configured to drive the main switch to switch off in response
to the off trigger signal.

US Pat. No. 9,312,771

SINGLE INDUCTOR MULTIPLE OUTPUT BUCK CONVERTER AND CONTROL METHOD THEREOF

Chengdu Monolithic Power ...

6. A control circuit used in a single inductor multiple output buck converter, wherein the single inductor multiple output
buck converter comprises an inductor having a first terminal and a second terminal, a first switch coupled between an input
voltage and the first terminal of the inductor, a second switch coupled between the first terminal of the inductor and a reference
ground, a third switch coupled between the second terminal of the inductor and a first output voltage, a fourth switch coupled
between the second terminal of the inductor and a second output voltage, a first capacitor coupled between the first output
voltage and the reference ground, and a second capacitor coupled between the second output voltage and the reference ground,
and wherein the control circuit comprises:
a first comparing circuit having a first input terminal, a second input terminal and an output terminal, wherein the first
input terminal is configured to receive a first feedback signal indicative of the first output voltage, the second input terminal
is configured to receive a first reference signal, and wherein the first comparing circuit compares the first feedback signal
with the first reference signal and generates a first comparison signal at the output terminal;

a second comparing circuit having a first input terminal, a second input terminal and an output terminal, wherein the first
input terminal is configured to receive a second feedback signal indicative of the second output voltage, the second input
terminal is configured to receive a second reference signal, and wherein the second comparing circuit compares the second
feedback signal with the second reference signal and generates a second comparison signal at the output terminal; and

a logic circuit coupled to the output terminals of the first comparing circuit and the second comparing circuit, wherein the
logic circuit detects which one of the first comparison signal and the second comparison signal is asserted first, and wherein
based on the detection result, the logic circuit generates a first driving signal, a second driving signal, a third driving
signal and a fourth driving signal to respectively control the first switch, second switch, third switch and fourth switch;
wherein

when the first comparison signal is asserted earlier than the second comparison signal, the logic circuit turns on the first
switch and the third switch, turns off the second switch and the fourth switch, wherein the logic circuit will turn off the
first switch and turn on the second switch once the on time of the first switch reaches a first time threshold;

when the second comparison signal is asserted earlier than the first comparison signal, the logic circuit turns on the first
switch and the fourth switch, turns off the second switch and the third switch, wherein the logic circuit will turn off the
first switch and turn on the second switch once the on time of the first switch reaches a second time threshold.

US Pat. No. 9,282,609

DIMMER COMPATIBLE LED DRIVING APPARATUS WITH ADJUSTABLE BLEEDING CURRENT

Chengdu Monolithic Power ...

1. A controller used in an LED driving apparatus, wherein the LED driving apparatus includes a rectifier bridge providing
a DC bus voltage at an output terminal, a bus capacitor coupled between the output terminal of the rectifier bridge and a
reference ground, a bleeding circuit configured to provide a bleeding current for the bus capacitor and a switching converter
configured to convert the DC bus voltage into a driving signal to drive an LED, and wherein the controller comprises:
a dimming mode detector configured to receive a voltage sensing signal indicative of the DC bus voltage, wherein based on
the voltage sensing signal, the dimming mode detector detects whether the LED driving apparatus is coupled to a leading edge
dimmer or a trailing edge dimmer, and generates a leading edge dimming mode signal and a trailing edge dimming mode signal;
and

a bleeding control circuit coupled to the dimming mode detector, wherein based on the voltage sensing signal, the leading
edge dimming mode signal and the trailing edge dimming mode signal, the bleeding control circuit generates a control signal
to control the bleeding circuit; wherein

if the LED driving apparatus is coupled to a leading edge dimmer, the bleeding circuit will provide a first bleeding current
when the voltage sensing signal becomes smaller than a first threshold voltage;

if the LED driving apparatus is coupled to a trailing edge dimmer, the bleeding circuit will provide a second bleeding current
when the voltage sensing signal becomes smaller than a second threshold voltage.

US Pat. No. 9,281,393

SUPER JUNCTION SEMICONDUCTOR DEVICE AND ASSOCIATED FABRICATION METHOD

Chengdu Monolithic Power ...

10. A method for forming a semiconductor device, comprising:
forming an epitaxy layer, wherein the epitaxy layer has a first conductivity type;
forming a plurality of deep wells in the epitaxy layer, wherein the deep wells have a second conductivity type; and
forming a plurality of trench gate MOSFET units, each of the plurality of trench gate MOSFET units formed in the top portion
of the epitaxy layer between two adjacent deep wells, wherein the top of the epitaxy layer serves as a body region, and wherein
the substrate serves as a drain region;

wherein forming each of the plurality of trench gate MOSFET units comprises forming a source region and a shallow trench gate,
and wherein the depth of the shallow trench gate is smaller than half of the distance between the two adjacent deep wells.

US Pat. No. 9,130,473

POWER FACTOR CORRECTION CIRCUIT, THE CONTROL CIRCUIT AND THE METHOD THEREOF

Chengdu Monolithic Power ...

1. A control circuit for a power factor correction circuit, the power factor correction circuit comprising at least a power
switch controlled by the control circuit to be ON and OFF to provide a regulated signal based on an input AC voltage, the
control circuit comprising:
a peak value sample-hold unit configured to receive a line voltage sense signal indicative of the input AC voltage, and to
generate a peak value detecting signal;

a clamp unit coupled to the peak value sample-hold unit to receive the peak value detecting signal, and to generate a clamp
signal;

a selecting unit having a first input terminal coupled to the clamp unit to receive the clamp signal, a second input terminal
configured to receive the line voltage sense signal, and an output terminal generating a peak current reference signal by
selecting the signal with the lower voltage between the clamp signal and the line voltage sense signal;

a current comparator having a first input terminal coupled to the output terminal of the selecting unit to receive the peak
current reference signal, a second input terminal configured to receive a current sense signal indicative of a current flowing
through the power switch, and an output terminal generating a current comparison signal based on the peak current reference
signal and the current sense signal; and

a controller having a first input terminal coupled to the output terminal of the current comparator to receive the current
comparison signal, a second input terminal configured to receive a feedback signal indicative of the regulated voltage, and
an output terminal generating a control signal to control the ON and OFF of the power switch.

US Pat. No. 9,118,258

SWITCHING POWER CONVERTER AND CONTROL METHOD THEREOF

Chengdu Monolithic Power ...

1. A switching power converter, comprising:
an input terminal configured to receive a first input voltage;
an output terminal configured to provide an output current to a load, wherein the output current has a peak value and an average
value;

a power switch;
a first loop coupled to the input terminal, wherein the first loop is configured to generate a first output signal based on
the first input voltage, and wherein the first output signal is proportional to the first input voltage in a first time period,
inversely proportional to the first input voltage in a second time period, and proportional to the first input voltage in
a third time period;

a second loop coupled to the output terminal, wherein the second loop is configured to generate a second output signal based
on the output current;

a multiplier coupled to the first loop and second loop, wherein the multiplier is configured to generate a multiplying signal
based on multiplying the first output signal with the second output signal; and

a driving circuit coupled to the multiplier, wherein the driving circuit is configured to generate a driving signal based
on the multiplying signal to control the power switch, so as to reduce the ratio between the peak value and the average value
of the output current.

US Pat. No. 9,379,630

CONTROL CIRCUIT FOR A SYNCHRONOUS RECTIFICATION CIRCUIT, LLC RESONANT CONVERTER AND ASSOCIATED METHOD

Chengdu Monolithic Power ...

1. A control circuit for a synchronous rectification circuit, wherein the synchronous rectification circuit has a first synchronous
rectifier and a second synchronous rectifier, and wherein each of the first synchronous rectifier and the second synchronous
rectifier has a drain, a source and a gate, the control circuit comprises:
a first comparing circuit having an input terminal and an output terminal, wherein the input terminal of the first comparing
circuit is configured to receive a first drain-source voltage signal of the first synchronous rectifier, and wherein the first
comparing circuit is configured to compare the first drain-source voltage signal with a threshold voltage and to provide a
first comparing signal at the output terminal;

a second comparing circuit having an input terminal and an output terminal, wherein the input terminal of the second comparing
circuit is configured to receive a second drain-source voltage signal of the second rectifier, and wherein the second comparing
circuit is configured to compare the second drain-source voltage signal with the threshold voltage and to provide a second
comparing signal at the output terminal;

a blanking circuit having a first input terminal, a second input terminal, a first output terminal and a second output terminal,
wherein the first input terminal of the blanking circuit is coupled to the output terminal of the first comparing circuit
for receiving the first comparing signal, and wherein the second input terminal of the blanking circuit is coupled to the
output terminal of the second comparing circuit for receiving the second comparing signal, and wherein the blanking circuit
is configured to conduct a logic operation to the first comparing signal and the second comparing signal so as to provide
a first blanking signal and a second blanking signal respectively at the first output terminal and the second output terminal,
and wherein the first blanking signal and the second blanking signal are logic complementary;

a first logic circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input
terminal of the first logic circuit is coupled to the output terminal of the first comparing circuit for receiving the first
comparing signal, and wherein the second input terminal of the first logic circuit is coupled to the first output terminal
of the blanking circuit for receiving the first blanking signal, and wherein the first logic circuit is configured to conduct
a logic operation to the first comparing signal and the first blanking signal so as to provide a first driving signal at the
output terminal of the first logic circuit, and wherein the first driving signal is coupled to the gate of the first synchronous
rectifier to control an on and off switching of the first synchronous rectifier; and

a second logic circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input
terminal of the second logic circuit is coupled to the output terminal of the second comparing circuit for receiving the second
comparing signal, and wherein the second input terminal of the second logic circuit is coupled to the second output terminal
of the blanking circuit for receiving the second blanking signal, and wherein the second logic circuit is configured to conduct
a logic operation to the second comparing signal and the second blanking signal so as to provide a second driving signal at
the output terminal of the second logic circuit, and wherein the second driving signal is coupled to the gate of the second
synchronous rectifier to control an on and off switching of the second synchronous rectifier.

US Pat. No. 9,391,516

SWITCHING CHARGER, THE CONTROL CIRCUIT AND THE CONTROL METHOD THEREOF

Chengdu Monolithic Power ...

1. A switching charger, comprising:
a control circuit configured to provide a control signal;
a power stage having a high-side power switch and a low-side power switch coupled in series, the high-side power switch and
the low-side power switch turned ON and OFF alternatively by the control signal;

an inductor having a first terminal coupled to a connection of the high-side power switch and the low-side power switch, and
a second terminal coupled to a load, a current flowing through the inductor being limited in a hysteretic window by the control
circuit, and the hysteretic window being adjusted according to an ON time of the control signal; and

an output capacitor having a first terminal coupled to the second terminal of the inductor, and a second terminal coupled
to a reference ground;

wherein the control circuit comprises:
a feedback amplifier having a first input terminal configured to receive a feedback signal indicating the charging voltage,
a second input terminal configured to receive a feedback reference signal, and an output terminal configured to generate an
amplified feedback signal based on the feedback signal and the feedback reference signal;

a select circuit having a first input terminal configured to receive a current reference signal, a second input terminal coupled
to the feedback amplifier to receive the amplified feedback signal, and an output terminal configured to generate a current
control signal based on the current reference signal and the amplified feedback signal, wherein the current control signal
is either the current reference signal or the amplified feedback signal whichever has the lower value;

a hysteretic control circuit having a first input terminal coupled to the output terminal of the select circuit to receive
the current control signal, a second input terminal configured to receive the input voltage, a third input terminal configured
to receive the charging voltage, a fourth input terminal coupled to the output terminal of the control circuit to receive
the control signal, and a fifth input terminal configured to receive a frequency control signal having pulses when the high-side
power switch is turned ON, wherein based on the current control signal, the input voltage, the charging voltage, the control
signal and the frequency control signal, the hysteretic control circuit provides a lower limit signal via a first output terminal,
and a higher limit signal via a second output terminal;

a comparison circuit having a first input terminal coupled to the first output terminal of the hysteretic control circuit
to receive the lower limit signal, a second input terminal coupled to the second output terminal of the hysteretic control
circuit to receive the higher limit signal, a third input terminal configured to receive a current sense signal indicating
a current flowing through the inductor, and based on the lower limit signal, the higher limit signal, and the current sense
signal, the comparison circuit provides a set signal via a first output terminal, and a reset signal via a second output terminal;
and

a logic circuit having a set terminal coupled to the comparison circuit to receive the set signal, a reset terminal coupled
to the comparison circuit to receive the reset signal, and an output terminal configured to generate the control signal based
on the set signal and the reset signal.

US Pat. No. 9,362,830

SWITCH MODE POWER SUPPLY, CONTROL CIRCUIT AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A control Integrated Circuit (IC) for controlling a switch mode power supply, the switch mode power supply comprises a
first switch having a control terminal, wherein the control IC comprising a reuse input pin, and when the first switch is
turned ON, the control IC is configured to receive a current sense signal via the reuse input pin, and when the first switch
is turned OFF, the control IC is configured to receive a voltage sense signal via the reuse input pin; wherein the control
IC further comprising:
a first protection unit, having a first input terminal, a second input terminal, and an output terminal, wherein the second
input terminal is configured to receive a first threshold signal, and the output terminal is configured to provide a first
protection signal based on the first threshold signal and a voltage at the first input terminal of the first protection unit;

a second protection unit, having a first input terminal, a second input terminal, and an output terminal, wherein the second
input terminal is configured to receive a second threshold signal, and the output terminal is configured to provide a second
protection signal based on the second threshold signal and a voltage at the first input terminal of the second protection
unit;

a driving control unit, having a first input terminal, a second input terminal, a third input terminal and an output terminal,
wherein the first input terminal is coupled to the output terminal of the first protection unit, the second input terminal
is coupled to the output terminal of the second protection unit, the third input terminal is configured to receive a driving
signal, and the output terminal is configured to provide a switching control signal to the control terminal of the first switch;
and

a single pole double throw switch, having a control terminal, a first terminal and a second terminal, wherein the control
terminal is coupled to the output terminal of the driving control unit, the first terminal is coupled to the reuse input pin,
and the second terminal is selectively coupled to the first protection unit and the second protection unit based on the switching
control signal; wherein

when the first switch is turned ON, the second terminal of the single pole double throw switch is coupled to the first input
terminal of the first protection unit, and the first protection unit is configured to provide the first protection signal
via comparing a voltage at the reuse input pin with the first threshold signal; and

when the first switch is turned OFF, the second terminal of the single pole double throw switch is coupled to the first input
terminal of the second protection unit, and the second protection unit is configured to provide the second protection signal
via comparing the voltage at the reuse input pin with the second threshold signal.

US Pat. No. 9,407,151

FLYBACK CONVERTER WITH CURRENT CONTROLLED LOW POWER MODE

Chengdu Monolithic Power ...

1. An isolated switching converter, comprising:
a transformer having a primary winding, a secondary winding and an auxiliary winding, wherein the primary winding is configured
to receive an input voltage, the secondary winding is coupled to provide an output voltage to a load;

a primary switch coupled to the primary winding;
a secondary switch coupled to the secondary winding;
a feedback circuit coupled to the auxiliary winding, wherein the feedback circuit is configured to generate a feedback signal
indicative of the output voltage;

a primary controller configured to generate a primary control signal to control the primary switch; and
a secondary controller configured to generate a secondary control signal to control the secondary switch; wherein
under normal operation, the primary controller controls the primary switch based on the feedback signal, the secondary controller
controls the secondary switch based on the status of the primary switch wherein the secondary switch is turned on after the
primary switch is off, and the secondary switch is turned off before the primary switch is on; and wherein

under light load condition, the secondary controller controls the secondary switch based on the output voltage wherein the
secondary switch is turned on to generate a negative secondary current flowing through the secondary winding and turned off
when the negative secondary current reaches a secondary current threshold, the primary controller turns on the primary switch
based on a negative primary current and turns off the primary switch when the primary current reaches a primary current threshold.

US Pat. No. 9,397,577

SWITCHING MODE POWER SUPPLIES WITH PRIMARY SIDE REGULATION AND ASSOCIATED METHODS OF CONTROL

Chengdu Monolithic Power ...

1. A switching mode power supply, comprising:
a transformer having a primary winding, a secondary winding and an auxiliary winding, wherein the secondary winding is coupled
to a load to provide an output voltage;

a primary switch coupled to the primary winding;
a secondary rectifying diode coupled to the secondary winding;
a secondary switch connected in parallel with the secondary rectifying diode;
a feedback circuit coupled to the auxiliary winding to receive a voltage across the auxiliary winding and configured to generate
a feedback signal based on the voltage across the auxiliary winding;

a primary controller coupled to the feedback circuit to receive the feedback signal and configured to generate a primary control
signal to control the primary switch;

a secondary controller configured to generate a secondary control signal to control the secondary switch based on a voltage
across the secondary switch, and wherein the primary controller turns ON the primary switch when the conduction of the secondary
switch is detected, the secondary controller comprises:

a hysteresis comparison circuit configured to compare the voltage across the secondary switch with a first secondary threshold
and a second secondary threshold and configured to generate a hysteresis comparison signal;

a secondary timer coupled to the hysteresis comparison circuit and configured to generate a secondary enable signal based
on the hysteresis comparison signal;

a first secondary comparator having an enable terminal, a first input terminal, a second input terminal and an output terminal,
wherein the enable terminal is coupled to the secondary timer to receive the secondary enable signal, the first input terminal
is configured to receive the voltage across the secondary switch, the second input terminal is configured to receive a third
secondary threshold, and wherein the first secondary comparator compares the voltage across the secondary switch with the
third secondary threshold under the control of the secondary enable signal and generates a first secondary comparison signal
at the output terminal; and

a secondary logic circuit coupled to the secondary timer and the first secondary comparator, wherein based on the first secondary
comparison signal and the secondary enable signal, the secondary logic generates the secondary control signal.

US Pat. No. 9,252,766

LOAD DETECTING CIRCUITS AND THE METHOD THEREOF

Chengdu Monolithic Power ...

1. A no-load detecting circuit for a switching mode power supply, comprising:
a variable resistance circuit coupled between the switching mode power supply and a load of the switching mode power supply,
wherein an equivalent resistance of the variable resistance circuit will vary depending on the status of the load of the switching
mode power supply; and

a first comparison circuit coupled to the variable resistance circuit to receive a voltage across the variable resistance
circuit, wherein based on the comparison of the voltage across the variable resistance circuit and a first threshold, the
first comparison circuit generates a no-load detecting signal indicative of the load status;

wherein the variable resistance circuit comprises:
a first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled
to the switching mode power supply, and the second terminal is coupled to the load; and

a second transistor having a first terminal, a second terminal and a control terminal, wherein the second transistor is coupled
in parallel to the first transistor;

and wherein the first transistor is ON and the second transistor is OFF under light load status, and the first transistor
and the second transistor are both ON under heavy load status; and

the first comparison circuit is coupled to the first transistor to receive a drain-source voltage of the first transistor,
wherein based on the comparison of the drain-source voltage of the first transistor and the first threshold, the first comparison
circuit generates the no-load detecting signal.

US Pat. No. 9,325,237

POWER SUPPLY WITH CHARGE PUMP AND CONTROL METHOD

Chengdu Monolithic Power ...

1. A charge pump used in a power supply providing driving signal to a load, comprising:
a first capacitor coupled to the load in parallel, wherein the first capacitor has a first terminal and a second terminal;
at least one flying capacitor, wherein each flying capacitor has a first terminal and a second terminal;
a second capacitor having a first terminal and a second terminal;
a switch array comprising a plurality of switches, wherein the switch array is coupled to the first capacitor, the second
capacitor and the at least one flying capacitor, and wherein the switch array receives the voltage across the first capacitor
and controls the charge and discharge of the at least one flying capacitor, so as to make the voltage across the second capacitor
be larger than the voltage across the first capacitor, wherein the switch array comprises a first group of switches and a
second group of switches, and wherein:

in a first state, the first group of switches are turned on and the second group of switches are turned off, the at least
one flying capacitor is charged by the voltage across the first capacitor;

in a second state, the first group of switches are turned off and the second group of switches are turned on, the voltage
across the second capacitor is increased to a sum of the voltage across the first capacitor and the voltage across the at
least one flying capacitor; and

the first group of switches comprises a second switch and a fourth switch, the second group of switches comprises a first
switch and a third switch, each switch has a first terminal and a second terminal, wherein the first terminal of the first
switch is coupled to the first terminal of the second capacitor, the second terminal of the first switch is coupled to the
first terminal of the second switch and the first terminal of a flying capacitor, the second terminal of the second switch
is coupled to the first terminal of the first capacitor and the first terminal of the third switch, the second terminal of
the third switch is coupled to the first terminal of the fourth switch and the second terminal of the flying capacitor, the
second terminal of the fourth switch is coupled to the second terminal of the first capacitor and the second terminal of the
second capacitor.

US Pat. No. 9,282,610

DIMMING MODE DETECTION METHOD USED IN LED DRIVING APPARATUS

Chengdu Monolithic Power ...

1. A dimming mode detection method used in an LED driving apparatus, wherein the LED driving apparatus includes a rectifier
bridge providing a DC bus voltage, a bus capacitor coupled between output terminals of the rectifier bridge, a bleeding circuit
configured to provide a bleeding current for the bus capacitor and a switching converter configured to convert the DC bus
voltage into a driving signal to drive an LED, and wherein the dimming mode detection method comprises:
powering on the LED driving apparatus;
sensing the DC bus voltage and generating a voltage sensing signal;
comparing a rising time during which the voltage sensing signal increases from a second threshold voltage to a first threshold
voltage with a first time threshold to detect whether the LED driving apparatus is connected to a leading edge dimmer, and
entering into a leading edge dimming mode if the LED driving apparatus is detected to be connected to a leading edge dimmer;

comparing a falling time during which the voltage sensing signal decreases from a third threshold voltage to a fourth threshold
voltage with a second time threshold to detect whether the LED driving apparatus is connected to a trailing edge dimmer, and
entering into a trailing edge dimming mode if the LED driving apparatus is detected to be connected to a trailing edge dimmer;
and

entering into a no dimming mode if the LED driving apparatus does not enter the leading edge dimming mode or the trailing
edge dimming mode in a predetermined time from the LED driving apparatus being powered on.

US Pat. No. 9,270,178

DIGITAL CONTROLLERS AND DIGITAL CONTROL METHODS OF MULTI-PHASE SWITCHING CONVERTERS

Chengdu Monolithic Power ...

1. A digital controller used in a multi-phase switching converter, wherein the multi-phase switching converter comprises a
plurality of switching circuits, the digital controller comprises:
an analog digital converting circuit coupled to the plurality of switching circuits, wherein the analog digital converting
circuit is configured to receive a plurality of current sensing signals representative of the output current of the plurality
of switching circuits, and to generate a plurality of digital phase current signals based on the plurality of current sensing
signals;

a current balance modulating circuit coupled to the analog digital converting circuit to receive the plurality of digital
phase current signals, wherein the current balance modulating circuit is configured to generate a plurality of on time signals
based on the plurality of digital phase current signals, a current reference signal and a predetermined on time signal; and

a logic circuit coupled to the current balance modulating circuit to receive the plurality of on time signals, wherein based
on the plurality of on time signals, the logic circuit generates a plurality of control signals to control the plurality of
switching circuits;

wherein the current balance modulating circuit comprises:
a plurality of subtracters with each of the subtracters having a first input terminal, a second input terminal and an output
terminal, wherein the first input terminal is configured to receive the current reference signal, the second input terminal
is coupled to the analog digital converting circuit to receive the corresponding digital phase current signal, and wherein
the subtracter subtracts the digital phase current signal from the current reference signal, and generates a current error
signal at the output terminal;

a plurality of proportional integrators with each of the proportional integrators having an input terminal and an output terminal,
wherein the input terminal is coupled to the output terminal of the corresponding subtracter to receive the current error
signal, and wherein the proportional integrator proportionally integrates the current error signal, and generates a first
bias signal at the output terminal;

a plurality of sigma-delta modulators with each of the sigma-delta modulators having an input terminal and an output terminal,
wherein the input terminal is coupled to the output terminal of the corresponding proportional integrator to receive the first
bias signal, and wherein the sigma-delta modulator conducts a sigma-delta modulation of the first bias signal, and generates
a second bias signal at the output terminal, wherein the first bias signal is a P-bit digital signal, the second bias signal
is a Q-bit digital signal, and P is larger than Q; and

a plurality of adders with each of the adders having a first input terminal, a second input terminal and an output terminal,
wherein the first input terminal is configured to receive the predetermined on time signal, the second input terminal is coupled
to the output terminal of the corresponding sigma-delta modulator to receive the second bias signal, and wherein the adder
adds the second bias signal to the predetermined on time signal, and generates the on time signal at the output terminal.

US Pat. No. 9,232,606

SWITCH-MODE POWER SUPPLY, CONTROL CIRCUIT AND ASSOCIATED DIMMING METHOD

Chengdu Monolithic Power ...

1. A control circuit for a switch-mode power supply, the switch-mode power supply having an input terminal configured to receive
an input signal and an output terminal configured to provide an output signal to a light-emitting device, wherein the switch-mode
power supply comprising a first switch, the first switch is turned ON or OFF by a control signal, and wherein the control
circuit comprising:
an error amplifier, having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is configured to receive a dimming signal, the second input terminal is configured to receive a feedback signal,
and the output terminal is configured to provide a compensation signal, and wherein the feedback signal is based on a current
flowing through the light-emitting device;

a minimum-off time control circuit, having an input terminal and an output terminal, wherein the input terminal is coupled
to the output terminal of the error amplifier to receive the compensation signal, and the output terminal is configured to
provide a minimum-off time control signal to adjust a minimum-off time period of the first switch based on the compensation
signal; and

a logic circuit, configured to provide the control signal based on the minimum-off time control signal.

US Pat. No. 9,606,566

TRANS-CONDUCTANCE REGULATION CIRCUIT, TRANS-CONDUCTANCE ERROR AMPLIFIER AND POWER CONVERTER

CHENGDU MONOLITHIC POWER ...

1. A trans-conductance regulation circuit for regulating a trans-conductance of a trans-conductance operational amplifier
in a power converter, wherein the power converter is configured to convert an input voltage into an output voltage, and wherein
the trans-conductance operational amplifier has a bias current input terminal configured to receive a bias current, and wherein
the trans-conductance is determined by a ratio of the bias current to a substantially constant thermal voltage; the trans-conductance
regulation circuit comprising:
a first input terminal configured to receive the output voltage of the power converter; and
a voltage to current conversion circuit configured to convert the output voltage to the bias current with a predetermined
conversion factor.

US Pat. No. 9,444,327

BOOST PFC CONVERTER, METHOD AND CONTROL CIRCUIT USED FOR BOOST PFC CONVERTER

CHENGDU MONOLITHIC POWER ...

1. A control circuit used in a boost PFC converter, the boost PFC converter is configured to receive an input signal to provide
an output signal, the boost PFC converter includes a rectifier, an energy storage component, a first power switch, a second
power switch and a zero crossing detector generating a zero crossing detecting signal indicative of a zero crossing condition
of a current flowing through the energy storage component, the control circuit comprising:
a peak holding circuit, configured to receive a current sense signal indicative of the current flowing through the energy
storage component, and to generate a peak holding signal indicative of the peak current flowing through the energy storage
component;

a saw-tooth wave generator, configured to generate a saw-tooth wave signal;
a first comparator, configured to receive the peak holding signal, the saw-tooth wave signal, and a reference voltage, to
generate a comparison signal by comparing the sum of the peak holding signal and the saw-tooth wave signal with the reference
voltage;

a logical unit, having a first input terminal coupled to the first comparator to receive the comparison signal, a second input
terminal configured to receive the zero crossing detecting signal, and an output terminal configured to generate a dead time
signal;

a logical NOR circuit, having a first input terminal coupled to the output terminal of the logical unit to receive the dead
time signal, a second input terminal configured to receive the zero crossing detecting signal, and an output terminal configured
to generate the set signal;

a voltage converting unit, configured to receive a fixed voltage and the dead time signal, to generate a converting voltage;
a voltage-current converter, coupled to the voltage converting unit to receive the converting voltage, and to generate a current
signal proportional to the converting voltage;

a first charge capacitor and a charge switch, parallel coupled between the voltage-current converter and the reference ground,
wherein the charge switch 94 has an opposite switching status to the first power switch;

an error amplifier, having a first input terminal configured to receive a feedback signal indicative of the output signal,
a second input terminal configured to receive a voltage reference signal, and an output terminal configured to generate a
compensation signal by amplifying and integrating the difference between the feedback signal and the voltage reference signal;

a second comparator, having a first input terminal configured to receive a voltage across the first charge capacitor, a second
input terminal coupled to the output terminal of the error amplifier to receive the compensation signal, and an output terminal
configured to generate the reset signal by comparing the voltage across the first charge capacitor with the compensation signal;
and

a logical circuit, having a set input terminal coupled to the logical NOR circuit to receive the set signal, a reset input
terminal coupled to the output terminal of the second comparator to receive the reset signal, and an output terminal configured
to generate a switch control signal to control the first power switch.

US Pat. No. 9,356,510

CONSTANT ON-TIME SWITCHING CONVERTER AND CONTROL METHOD THEREOF

Chengdu Monolithic Power ...

1. A control circuit for controlling a switching converter, the switching converter having at least one switch and an output
terminal configured to provide an output voltage, the control circuit comprising:
a slope compensation module having an output terminal configured to provide a slope compensation signal, wherein the slope
compensation signal increases when the at least one switch is turned OFF;

an output correction module having an output terminal configured to provide a voltage trim signal based on the slope compensation
signal; and

a control module having a first input terminal, a second input terminal, a third input terminal, a fourth input terminal,
and an output terminal, wherein the first input terminal is coupled to the output terminal of the output correction module
to receive the voltage trim signal, the second input terminal is coupled to the output terminal of the slope compensation
module to receive the slope compensation signal, the third input terminal is coupled to the output terminal of the switching
converter, the fourth input terminal is configured to receive a reference signal, and the output terminal is configured to
provide a control signal to control the at least one switch.

US Pat. No. 9,479,043

CONTROL CIRCUIT WITH SYNCHRONIZATION UNIT FOR SWITCHING CONVERTER AND ASSOCIATED CONTROL METHOD

CHENGDU MONOLITHIC POWER ...

1. A control circuit for a switching converter, the switching converter having a switch and an output terminal configured
to provide an output signal, and the control circuit comprising:
a comparison circuit, configured to provide a comparison signal based on a reference signal and the output signal of the switching
converter;

a synchronization unit, configured to receive a first clock signal, a second clock signal and the comparison signal, and configured
to provide a first synchronization signal and a second synchronization signal, wherein the first synchronization signal is
generated by synchronizing the comparison signal with the first clock signal, and the second synchronization signal is generated
by synchronizing the comparison signal with the second clock signal;

an ON-time control circuit, configured to provide an ON-time control signal to control an ON-time period of the switch; and
a logic unit, configured to receive the first synchronization signal, the second synchronization signal and the ON-time control
signal, and configured to provide a switching control signal based on the first synchronization signal, the second synchronization
signal and the ON-time control signal to control the switch, wherein the switch is turned ON based on the first synchronization
signal and the second synchronization signal, and the switch is turned OFF based on the ON-time control signal.

US Pat. No. 9,241,381

LED DRIVING CIRCUIT, CONTROL CIRCUIT AND ASSOCIATED CURRENT SENSING CIRCUIT

Chengdu Monolithic Power ...

1. A control circuit for a LED driving circuit, wherein the LED driving circuit comprises a switching circuit comprising at
least one switch and an inductive element, and wherein the switching circuit is configured to receive a DC voltage signal
for driving a plurality of LED, and to receive a control signal configured to control the at least one switch to switch on
and off so as to regulate an average current flowing through the plurality of LED; the control circuit comprising:
a sensing circuit coupled between the at least one switch and a logic ground, wherein the sensing circuit is configured to
sense a switching current signal flowing through the at least one switch, and to provide a first sensing signal, and wherein
the first sensing signal is indicative of the switching current signal;

an estimation circuit having an input terminal and an output terminal, wherein the input terminal of the estimation circuit
is coupled to the sensing circuit for receiving the first sensing signal; and wherein the estimation circuit is configured
to process the first sensing signal, and to provide a feedback signal at the output terminal, wherein the feedback signal
is indicative of the average current signal flowing through the plurality of LED;

an amplifying circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal of the amplifying circuit is coupled to the output terminal of the estimation circuit for receiving the feedback
signal; and wherein the second input terminal of the amplifying circuit is configured to receive a reference signal, wherein
the reference signal is indicative of a desired average current of the plurality of LED; and wherein the amplifying circuit
is configured to amplify the difference of the feedback signal and the reference signal, and to provide an error signal at
the output terminal;

a comparing circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal of the comparing circuit is coupled to the output terminal of the amplifying circuit for receiving the error signal;
and wherein the second input terminal of the comparing circuit is configured to receive the first sensing signal; and wherein
the comparing circuit is configured to compare the error signal with the first sensing signal, and to provide a comparing
signal at the output terminal; and wherein when the first sensing signal is larger than the error signal, the comparing signal
is configured to turn the at least one switch off; and

a zero-cross detection circuit having an input terminal and an output terminal, wherein the input terminal of the zero-cross
detection circuit is coupled to the switching circuit, and configured to receive a current signal flowing through the inductive
element so as to generate a second sensing signal, wherein the second sensing signal is indicative of the current signal flowing
through the inductive element; and wherein the zero-cross detection circuit is configured to compare the second sensing signal
with a zero-cross threshold, and to provide a zero-cross signal at the output terminal; and wherein when the second sensing
signal decreases to the zero-cross threshold, the zero-cross signal is configured to turn the at least one switch on.

US Pat. No. 10,021,754

TWO-CHANNEL LED DRIVER WITH SHORT CIRCUIT PROTECTION AND SHORT CIRCUIT PROTECTION METHOD FOR TWO-CHANNEL LED DRIVER

Chengdu Monolithic Power ...

1. A two-channel LED driver, comprising:a power converter, configured to provide a first drive voltage and a second drive voltage, to respectively drive a first channel LED and a second channel LED in response to an input voltage, the power converter including a main power switch, the first channel LED being dimmed by a first dimming switch, the second channel LED being dimmed by a second dimming switch, the first dimming switch and the second dimming switch being both controlled by a second dimming signal, and the second dimming switch being controlled to be turned on and off complementary with the first dimming switch;
a power control circuit, configured to generate a control signal to control the main power switch in response to a first dimming signal and a current sense signal indicative of a current flowing through the main power switch; and
a short process circuit, configured to monitor a short condition of the first channel LED and the second channel LED, wherein if one of the channels is shorted, the short process circuit is configured to control the corresponding dimming switch of the shorted channel LED to be kept ON.

US Pat. No. 9,525,358

RESONANT CONVERTER, CONTROL CIRCUIT AND ASSOCIATED CONTROL METHOD WITH ADAPTIVE DEAD-TIME ADJUSTMENT

CHENGDU MONOLITHIC POWER ...

1. A control circuit for a resonant converter, the resonant converter having a first switch, a second switch and a resonant
tank, the control circuit comprising:
a slope sensing circuit, configured to provide a slope signal based on a voltage variation at a common node of the first switch
and the second switch;

a capacitive mode judge circuit, configured to provide a mode signal based on a current flowing through the resonant tank
to indicate a working mode of the resonant converter, wherein the working mode of the resonant converter comprises a capacitive
mode and an inductive mode;

a slope judge circuit, configured to provide a slope judge signal based on the slope signal to indicate if the slope signal
is effective to indicate the voltage variation at the common node of the first switch and the second switch, wherein if the
slope signal is detected less than a first slope threshold within a predetermined time period after turning OFF the first
switch, the slope signal is judged effective, and if the slope signal is detected larger than a second slope threshold within
the predetermined time period after turning OFF the second switch, the slope signal is judged effective;

an oscillator, configured to provide a clock signal, wherein the second switch is turned OFF when the clock signal is at a
first status, and wherein the first switch is turned OFF when the clock signal is at a second status; and

a turn-ON control circuit, configured to adjust a first dead-time period and a second dead-time period based on the mode signal,
the slope judge signal, the slope signal, and the current flowing through the resonant tank, wherein the first dead-time period
is a time period from turning OFF the first switch to turning ON the second switch, and the second dead-time period is a time
period from turning OFF the second switch to turning ON the first switch, and wherein when the slope signal is judged effective,
the first dead-time period is adjusted to turn ON the second switch based on comparing the slope signal with a third slope
threshold, and the second dead-time period is adjusted to turn ON the first switch based on comparing the slope signal with
a fourth slope threshold.

US Pat. No. 9,215,769

LED BACKLIGHT DRIVER SYSTEM AND ASSOCIATED METHOD OF OPERATION

Chengdu Monolithic Power ...

1. A light-emitting diode (LED) driver system, comprising:
an isolated converter, having a primary side and a secondary side, wherein the primary side having a primary side switch,
and wherein the secondary side having a first output configured to provide an LED current to supply an LED string, and having
a second output configured to provide a bus voltage; and wherein

the isolated converter is configured to regulate the LED current only when a dimming signal is activated, and the isolated
converter is configured to regulate the bus voltage only when the dimming signal is deactivated.

US Pat. No. 9,608,519

SWITCHING CONVERTER WITH ADAPTIVE OFF TIME CONTROL AND THE METHOD THEREOF

Chengdu Monolithic Power ...

1. A switching converter with adaptive OFF time control, comprising:
a power stage comprising a main switch, the power stage being configured to convert an input voltage to an output voltage;
a current sense circuit coupled to the power stage to generate a current sense signal indicative of the current flowing through
the main switch;

an error amplifier having a first input terminal configured to receive a feedback signal indicative of the output voltage,
a second input terminal configured to receive a first reference signal, and an output terminal configured to generate a compensation
signal based on the feedback signal and the first reference signal;

a PWM comparator having a first input terminal coupled to the current sense circuit to receive the current sense signal, a
second input terminal coupled to the output terminal of the error amplifier to receive the compensation signal, and an output
terminal configured to generate a PWM signal based on the current sense signal and the compensation signal;

an OFF time controller having a first input terminal configured to receive the input voltage, a second input terminal configured
to receive the output voltage, and an output terminal configured to generate an OFF time control signal based on the input
voltage and the output voltage to control the OFF time of the main switch; and

a logic circuit having a first input terminal coupled to the output terminal of the PWM comparator to receive the PWM signal,
a second input terminal coupled to the output terminal of the OFF time controller to receive the OFF time control signal,
and an output terminal configured to output a switching signal based on the PWM signal and the OFF time control signal to
control the main switch.

US Pat. No. 9,525,342

POWER CONVERTER WITH PSEUDO-CONSTANT-ON-TIME CONTROL AND THE CONTROL CIRCUIT AND METHOD THEREOF

CHENGDU MONOLITHIC POWER ...

1. A control circuit for a power converter, wherein the power converter comprises a switching circuit comprising a main switch,
a freewheeling element and an inductor having a first terminal and a second terminal, and wherein the power converter is configured
to convert an input voltage into an output voltage, the control circuit comprises:
an on-time generating circuit configured to generate an on-time control signal;
a ramp compensation circuit configured to generate a ramp compensation signal, wherein the amplitude of the ramp compensation
signal is proportional to 1?D with a scaling factor, and wherein D represents the duty cycle of the main switch;

a ramp regulating circuit configured to generate a ramp regulating signal, wherein the amplitude of the ramp regulating signal
is proportional to D with the scaling factor;

a comparison circuit electrically coupled to the ramp compensation circuit and the ramp regulating circuit, wherein the comparison
circuit is configured to generate a comparison signal based on a feedback signal representative of the output voltage, a reference
signal and the sum of the ramp compensation signal and the ramp regulating signal; and

a logic circuit configured to generate a control signal based on the on-time control signal and the comparison signal to control
the main switch and the freewheeling element.

US Pat. No. 9,362,351

FIELD EFFECT TRANSISTOR, TERMINATION STRUCTURE AND ASSOCIATED METHOD FOR MANUFACTURING

Chengdu Monolithic Power ...

1. A field effect transistor, comprising:
a semiconductor layer of a first conductivity type, wherein the semiconductor layer has an active area and a termination area
outside of the active area;

a plurality of active transistor cells formed in the semiconductor layer in said active area, wherein each of the transistor
cells comprises a drain region of the first conductivity type, a source region of the first conductivity type, an active body
region of a second conductivity type and a gate region, and wherein the source region is located in the active body region
and laterally adjacent to both sides of the gate region;

a plurality of floating body regions of the second conductivity type disposed in the semiconductor layer in said termination
area; and

a plurality of termination cells disposed interleaving with the plurality of floating body regions in the termination area,
and arranged substantially in parallel from an inner side toward an outer side of the termination area; wherein

each of the termination cells comprises a termination trench opened from a top surface of said semiconductor layer and having
sidewalls and a bottom, wherein the termination trench includes a termination insulation layer lining the termination trench
sidewalls and bottom, and a termination conduction layer filling the termination trench; and wherein

the innermost termination cell among the plurality of termination cells isolates the floating body regions from the active
body regions so that the floating body regions have floating potentials; and wherein

the innermost termination cell is electrically coupled to the gate regions of the transistor cells while the rest of the termination
cells are electrically floating.

US Pat. No. 9,553,513

CONTROL CIRCUIT WITH CHOPPING AMPLIFIER FOR SWITCHING CONVERTER

CHENGDU MONOLITHIC POWER ...

1. A control circuit for a switching converter with at least a power switch, comprising:
a chopping amplifier having a first input terminal, a second input terminal, a control terminal and an output terminal, wherein
the first input terminal is configured to receive a reference signal, and wherein the second input terminal is configured
to receive a feedback signal representing an output voltage or a load current of the switching converter, and wherein the
control terminal is configured to receive a chopping control signal, and wherein based on the reference signal and the feedback
signal, the chopping amplifier is operable to generate an amplified error signal at the output terminal;

a sample-hold circuit having an input terminal, an output terminal and a control terminal, wherein the input terminal is coupled
to the output terminal of the chopping amplifier, and wherein the control terminal is configured to receive a sample-hold
control signal, and wherein the sample-hold circuit generates a sample-hold signal at the output terminal;

a first comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is coupled to the output terminal of the sample-hold circuit, and wherein the second input terminal is configured
to receive a current sensing signal representing a current flowing through the power switch, and wherein based on a comparison
result between the sample-hold signal and the current sensing signal, the first comparator generates a first logic signal
at the output terminal;

an oscillator, generating a clock signal; and
a logic circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal
is configured to receive the first logic signal, and wherein the second input terminal is configured to receive the clock
signal, and wherein based on the first logic signal and the clock signal, the logic circuit generates a switching signal at
the output terminal, and wherein the switching signal is configured to control the power switch.

US Pat. No. 9,265,110

LED POWER SUPPLY WITH SMALL DIMMING RATIO CONTROL AND CONTROL METHOD THEREOF

Chengdu Monolithic Power ...

1. A light emitting diode (LED) power supply comprising:
a converter having a power switch, the converter configured to generate an output voltage for supplying a LED load;
a LED dimming circuit having a dimming switch, the dimming switch being turned ON and OFF by a PWM dimming signal; and
a LED driving control circuit comprising:
a feedback circuit coupled to the LED load, the feedback circuit configured to generate a feedback signal indicative of the
output voltage;

an enabling circuit coupled to the feedback circuit, the enabling circuit configured to generate an enable signal according
to the feedback signal, a first reference signal and the PWM dimming signal; and

a feedback loop control circuit coupled to the feedback circuit and the enabling circuit, the feedback loop control circuit
configured to generate a control signal for controlling the power switch according to the feedback signal only when the enable
signal is in an active state;

when the feedback signal is higher than the first reference signal, the enable signal synchronizing with the PWM dimming signal,
and when the feedback signal is lower than the first reference signal, the duty cycle of the enable signal being higher than
the duty cycle of the PWM dimming signal.

US Pat. No. 9,065,348

ISOLATED SWITCHING MODE POWER SUPPLY AND THE METHOD THEREOF

Chengdu Monolithic Power ...

7. A method of controlling an isolated switching mode power supply, wherein the isolated switching mode power supply comprises
a transformer, a primary power switch and a secondary power switch, wherein the transformer has a primary winding, a secondary
winding and a third winding, and wherein the primary power switch is coupled to the primary winding and the secondary power
switch is coupled to the secondary winding, the method comprising:
generating a logical control signal based on a current sense signal indicative of a current flowing through the primary winding
and a frequency control signal indicative of the output voltage of the switching mode power supply;

generating a startup control signal based on the current sense signal;
generating a load detecting signal based on the voltage across the third winding, wherein the voltage across the third winding
indicates the output voltage of the switching mode power supply;

selecting the logic control signal or the startup control signal as a switching signal based on the load detecting signal;
and

turning ON and OFF the primary power switch based on the switching signal.

US Pat. No. 9,496,382

FIELD EFFECT TRANSISTOR, TERMINATION STRUCTURE AND ASSOCIATED METHOD FOR MANUFACTURING

CHENGDU MONOLITHIC POWER ...

1. A field effect transistor having an active area and a termination area outside of the active area, comprising: a semiconductor
layer of a first conductivity type; a plurality of active transistor cells formed in the semiconductor layer in said active
area, wherein each of the transistor cells comprises a drain region of the first conductivity type, a source region of the
first conductivity type, an active body region of a second conductivity type and a gate region, and wherein the source region
is located in the active body region and laterally adjacent to both sides of the gate region; a plurality of floating body
regions of the second conductivity type disposed in the semiconductor layer in said termination area; at least one gate runner
comprising a runner conduction layer filling a runner trench disposed in the semiconductor layer in said termination area
and electrically coupled to the gate region of the plurality of active transistor cells; and a plurality of termination cells
disposed interleaving with the plurality of floating body regions in the termination area, and arranged substantially in parallel
from an inner side toward an outer side of the termination area; wherein each of the termination cells comprises a termination
trench opened from a top surface of said semiconductor layer and having sidewalls and a bottom, wherein the termination trench
includes a termination insulation layer lining the termination trench sidewalls and bottom, a first conductive spacer and
a second conductive spacer located respectively against an inner sidewall and an outer sidewall among the termination trench
sidewalls and spaced apart from each other, and a dielectric layer filling the space between the first conductive spacer and
the second conductive spacer; and wherein each of the termination cells further comprises a guard ring region of the second
conductivity type located underneath the bottom of the termination trench in the semiconductor layer, wherein the runner trench
is connected to the innermost termination trench of the innermost termination cell among the plurality of termination cells,
and wherein the runner conduction layer is electrically connected to the first conductive spacer of the innermost termination
trench.

US Pat. No. 9,496,781

SOFT START CIRCUIT FOR SWITCHING CONVERTER AND ASSOCIATED SOFT START METHOD

CHENGDU MONOLITHIC POWER ...

9. A switching converter integrated on an integrated circuit, wherein the integrated circuit having a soft start pin, the
switching converter comprising:
an output terminal configured to provide an output voltage;
an error amplifier configured to receive a soft start reference signal, an output reference signal and an output feedback
signal indicative of the output voltage, wherein the error amplifier is configured to provide an error signal based on the
soft start reference signal, the output reference signal and the output feedback signal;

a slope compensation circuit configured to provide a slope signal;
a logic circuit coupled to the error amplifier and the slope compensation circuit to receive the error signal and the slope
signal, the logic circuit is configured to provide a switching control signal based on the error signal and the slope signal;

a switch configured to be turned ON and turned OFF by the switching control signal; and
a soft start circuit comprising:
a first current source configured to provide a first current;
an internal soft start capacitor coupled to the first current source, the internal soft start capacitor is charged by the
first current and is configured to provide an internal soft start voltage;

an amplifier circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is coupled to the internal soft start capacitor to receive the internal soft start voltage, the second input terminal
is configured to receive the soft start reference signal, and the output terminal is coupled to the soft start pin;

a bias current source comprising an output terminal configured to provide a bias current to the amplifier circuit; and
a buffer circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal
of the amplifier circuit, and the output terminal is configured to provide the soft start reference signal.

US Pat. No. 9,520,778

CONSTANT ON-TIME SWITCHING CONVERTERS WITH ULTRASONIC MODE DETERMINATION CIRCUIT AND CONTROL METHODS THEREOF

CHENGDU MONOLITHIC POWER ...

11. A constant on-time switching converter, comprising:
a switching circuit configured to convert an input voltage into an output voltage to drive a load, and wherein the switching
circuit comprises:

a high-side switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is configured
to receive the input voltage;

a low-side switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled
to the second terminal of the high-side switch, the second terminal is coupled to a reference ground;

an inductor having a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of
the high-side switch and the first terminal of the low-side switch, the second terminal is coupled to the load;

an output capacitor coupled between the second terminal of the inductor and the reference ground;
an on-time control circuit configured to generate an on-time control signal which is used to control the on-time of the high-side
switch;

an ultrasonic mode determination circuit configured to provide a flag signal indicating whether the switching converter enters
into an ultrasonic mode, wherein when the switching frequency of the switching circuit approaches an audible range, the switching
converter enters into the ultrasonic mode;

a slope compensation module coupled to the ultrasonic mode determination circuit to receive the flag signal and configured
to generate a slope compensation signal based on the flag signal;

a comparison circuit coupled to the slope compensation module and the switching circuit, wherein the comparison circuit compares
a feedback signal indicative of the output voltage of the switching circuit with a sum of a reference voltage and the slope
compensation signal, and generates a comparison signal; and

a logic circuit coupled to the on-time control circuit, the comparison circuit and the ultrasonic mode determination circuit,
wherein based on the on-time control signal, the comparison signal and the flag signal, the logic circuit generates a high-side
control signal to the control terminal of the high-side switch and a low-side control signal to the control terminal of the
low-side switch; wherein

when the switching converter enters into the ultrasonic mode, the low-side switch is turned ON by the logic circuit to discharge
the output capacitor until the feedback signal decreases to reach the sum of the reference voltage and the slope compensation
signal, and wherein the slope compensation signal has two parts: a normal slope compensation signal and an additional slope
compensation signal, wherein the additional slope compensation signal is generated during the discharge of the output capacitor
to eliminate the double pulses due to the ultrasonic mode and the value of the additional slope compensation signal increases
during the discharge of the output capacitor.

US Pat. No. 9,398,653

LED DRIVER, THE CONTROL CIRCUIT AND THE LED DRIVING METHOD

Chengdu Monolithic Power ...

1. A LED driver, comprising:
a first input port and a second input port, configured to receive an input AC voltage;
an output port, configured to provide a driving voltage for the LED;
a power stage, having a main power switch and a freewheel power switch;
an inductor, coupled between the power stage and the output port, wherein the inductor gains energy from the input AC voltage
and delivers the energy to the output port when the main power switch is ON and when the freewheel power switch is OFF, and
the inductor supplies energy to the output port via the freewheel power switch when the main power switch is OFF;

an output capacitor, coupled between the output port and a reference ground;
an error amplifier, having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is configured to receive a first reference voltage, the second input terminal is configured to receive a current
sense signal indicative of a current flowing through the inductor, and wherein the error amplifier generates an error amplified
signal by amplifying and integrating a difference between the first reference voltage and the current sense signal;

a set comparator, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal
is coupled to the error amplifier to receive the error amplified signal, the second input terminal is configured to receive
the current sense signal, and wherein based on the error amplified signal and the current sense signal, the set comparator
generates a set comparison signal at the output terminal;

a first timer, configured to generate a minimum OFF time signal;
a logical AND circuit, having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is coupled to the set comparator to receive the set comparison signal, the second input terminal is coupled to the
first timer to receive the minimum OFF time signal, and wherein based on the set comparison signal and the minimum OFF time
signal, the first logical AND circuit generates a set signal at the output terminal;

a reset comparator, having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is configured to receive a second reference voltage, the second input terminal is configured to receive the current
sense signal, wherein based on the second reference voltage and the current sense signal, the reset comparator generates a
reset comparison signal at the output terminal;

a second timer, configured to generate a maximum ON time signal;
a logical OR circuit, having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is coupled to the reset comparator to receive the reset comparison signal, the second input terminal is coupled to
the second timer to receive the maximum ON time signal, wherein based on the reset comparison signal and the maximum ON time
signal, the logical OR circuit generates a reset signal at the output terminal;

a RS flip flop, having a set input terminal, a reset input terminal and an output terminal, wherein the set input terminal
is coupled to the logical AND circuit to receive the set signal, the reset input terminal is coupled to the logical OR circuit
to receive the reset signal, wherein based on the set signal and the reset signal, the RS flip flop generates a control signal
at the output terminal; and

a driving circuit, coupled to the RS flip flop to receive the control signal to generate a driving signal, to control the
operation of the main power switch.

US Pat. No. 9,306,451

SWITCH MODE POWER SUPPLY CONTROL CIRCUIT TO REDUCE OVERSHOOT OF AN OUTPUT VOLTAGE

Chengdu Monolithic Power ...

1. A control circuit for controlling a switch mode power supply, the switch mode power supply having an output terminal configured
to provide an output voltage which is configured to regulate to an output target, the switch mode power supply comprises a
first switch having a control terminal, wherein the control circuit comprising:
a switching control unit, having an output terminal, wherein the output terminal is configured to provide a pulse signal based
on the output voltage and the output target;

an overshoot control unit, having an output terminal, wherein the output terminal is configured to provide an overshoot control
signal based on the output voltage and a first threshold voltage; and

a first logic unit, having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is coupled to the output terminal of the switching control unit to receive the pulse signal, the second input terminal
is coupled to the output terminal of the overshoot control unit to receive the overshoot control signal, and the output terminal
is configured to provide a switching control signal to the control terminal of the first switch based on the pulse signal
and the overshoot control signal; and wherein

the first switch is turned OFF when the overshoot control signal is in a first state, and the first switch is controlled based
on the pulse signal when the overshoot control signal is in a second state; wherein

when the output voltage increases to the first threshold voltage, the control circuit is configured to turn OFF the first
switch, and wherein the first threshold voltage is less than the output target.

US Pat. No. 9,236,796

CHARGE PUMP AND METHOD OF HAVING NEGATIVE OUTPUT VOLTAGE TRACKING POSITIVE OUTPUT VOLTAGE THEREOF

Chengdu Monolithic Power ...

1. A method of having a negative output voltage at a negative output terminal of a charge pump tracking a positive output
voltage at a positive output terminal of the charge pump, wherein the charge pump comprises a first switch, a second switch,
a third switch, a fourth switch, an inductor, a first output capacitor, a flying capacitor and a second output capacitor,
wherein:
the inductor having a first end and a second end, wherein the first end is coupled to an input terminal;
the first switch having a first end, a second end and a control end, wherein the first end of the first switch is coupled
to the second end of the inductor, and the second end of the first switch is coupled to a reference ground;

the second switch having a first end, a second end and a control end, wherein the first end of the second switch is coupled
to the second end of the inductor, and the second end of the second switch is coupled to the positive output terminal;

the first output capacitor having a first end and a second end, wherein the first end of the first output capacitor is coupled
to the second end of the second switch, and the second end of the first output capacitor is coupled to the reference ground;

the flying capacitor having a first end and a second end, wherein the first end of the flying capacitor is coupled to the
second end of the inductor;

the third switch having a first end, a second end and a control end, wherein the first end of the third switch is coupled
to the second end of the flying capacitor and the second end of the third switch is coupled to the negative output terminal;

the second output capacitor having a first end and a second end, wherein the first end of the second output capacitor is coupled
to the second end of the third switch, and the second end of the second output capacitor is coupled to the reference ground;
and

the fourth switch having a first end, a second end and a control end, wherein the first end of the fourth switch is coupled
to the second end of the flying capacitor and the second end of the fourth switch is coupled to the reference ground;

the method comprising selecting a serial resistance for the second switch in its ON state to be at least twice higher than
the serial resistance for each of the first switch, the third switch and the fourth switch in their ON states.

US Pat. No. 9,647,552

CONSTANT ON TIME SWITCHING CONVERTER WITH DC CALIBRATION

Chengdu Monolithic Power ...

1. A reference compensating circuit used in a COT control circuit, wherein the reference compensating circuit is configured
to generate a calibrated compensation reference signal at a compensation node, and wherein based on the calibrated compensation
reference signal, the COT control circuit is configured to control a switching converter to convert an input voltage into
an output voltage through turning a main switch and a freewheeling component on and off alternately, the reference compensating
circuit comprising:
an error amplifier configured to receive a reference signal and a feedback signal representative of the output voltage, and
to generate an error signal based on the feedback signal and the reference signal;

a first current sink coupled to the compensation node, wherein the first current sink is configured to receive the error signal
and to generate a first current based on the error signal, and wherein the first current flows out from the compensation node;

a resistor having a first terminal coupled to the reference signal, and a second terminal coupled to the compensation node;
a second current sink coupled to the compensation node to sink a second current from the compensation node when the main switch
is turned on;

a first current source coupled to the compensation node to source a third current into the compensation node; and
a compensation capacitor coupled between the compensation node and a ground.

US Pat. No. 9,093,909

SWITCHING MODE POWER SUPPLY AND THE METHOD THEREOF

Chengdu Monolithic Power ...

1. A switching mode power supply, comprising: an input port configured to receive an input voltage; an output port configured
to provide an output voltage to a load; an energy storage component and a power switches coupled between the input port and
the output port;
an error amplifier having a first input terminal configured to receive a feedback signal indicative of the output voltage,
a second input terminal configured to receive a reference signal, and an output terminal configured to generate an amplified
error signal based on the feedback signal and the reference signal;

an error comparator having a first input terminal configured to receive the amplified error signal, a second input terminal
configured to receive a first sawtooth signal, and an output terminal configured to generate a frequency control signal based
on the amplified error signal and the first sawtooth signal;

a peak current generator having an input terminal coupled to the output terminal of the error comparator to receive the frequency
control signal, and an output terminal configured to generate a peak current signal based on the frequency control signal,

wherein the value of the peak current signal is varying with a switching frequency of the switching mode power supply;
a peak current comparator having a first input terminal coupled to the output terminal of the peak current generator to receive
the peak current signal, a second input terminal configured to receive a current sense signal indicative of a current flowing
through the energy storage component, and an output terminal configured to generate a current limit signal based on the peak
current signal and the current sense signal; and

a logic circuit having a first input terminal coupled to the output terminal of the error comparator to receive the frequency
control signal, a second input terminal coupled to the output terminal of the peak current comparator to receive the current
limit signal, an output terminal configured to generate a switching signal to control the power switches based on the frequency
control signal and the current limit signal, and

an oscillator configured to generate a clock signal with a fixed frequency; a selector having a first input terminal coupled
to the output terminal of the error comparator to receive the frequency control signal, a second input terminal coupled to
the oscillator to receive the clock signal, and an output terminal configured to select the lower frequency value of between
the frequency control signal and the clock signal; a RS flip-flop having a set terminal coupled to the output terminal of
the selector, a reset terminal coupled to the output terminal of the peak current comparator to receive the current limit
signal, and an output terminal configured to generate the switching signal based on the output signal of the selector and
the current limit signal.

US Pat. No. 9,684,745

DIGITALLY CALIBRATED VOLTAGE REGULATORS FOR POWER MANAGEMENT

Monolithic Power Systems,...

1. A method of digitally calibrating a voltage regulator, the method comprising:
receiving, in a computer, a user requirement for a voltage regulator;
automatically determining an internal calibration setting for the voltage regulator to meet the user requirement;
simulating, in the computer, operation of the voltage regulator with the internal calibration setting;
after simulating the operation of the voltage regulator, providing the internal calibration setting from the computer to the
voltage regulator;

receiving the internal calibration setting in a calibration controller of the voltage regulator; and
calibrating the voltage regulator by applying digital calibration bits to an interface circuit of the voltage regulator in
accordance with the internal calibration setting.

US Pat. No. 9,608,510

SWITCHING REGULATOR AND THE METHOD THEREOF

CHENGDU MONOLITHIC POWER ...

1. A switching regulator, comprising:
an input port, configured to receive an input voltage;
an output port, configured to provide an output voltage;
a power converter, coupled between the input port and the output port, the power converter including an inductor, a main power
switch and a secondary power switch;

a current comparator, having a first input terminal configured to receive a voltage feed forward signal indicative of the
input voltage, a second input terminal coupled to the power converter to receive a current sense signal indicative of an inductor
current, and an output terminal configured to generate a reset signal based on the voltage feed forward signal and the current
sense signal;

a RS flip flop, having a reset terminal coupled to the output terminal of the current comparator to receive the reset signal,
to turn off the main power switch when the current sense signal reaches the voltage feed forward signal;

an over voltage comparator, having a first input terminal configured to receive the voltage feed forward signal, a second
input terminal configured to receive a reference wave signal, and an output terminal configured to generate an over voltage
detected signal based on the voltage feed forward signal and the reference wave signal; and

a controller, coupled to the over voltage comparator to receive the over voltage detected signal, to generate a control signal,
so as to execute over voltage protection when the switching regulator is in an over voltage condition.

US Pat. No. 9,595,885

ISOLATED SWITCHING MODE POWER SUPPLY AND THE METHOD THEREOF

CHENGDU MONOLITHIC POWER ...

1. An isolated switching mode power supply, comprising:
an input terminal configured to receive an input voltage;
an output terminal configured to provide an output voltage;
a transformer having a primary winding and a secondary winding respectively having a first terminal and a second terminal,
the first terminal of the primary winding being coupled to the input terminal to receive the input voltage;

a primary power switch having a first terminal coupled to the second terminal of the primary winding, a second terminal coupled
to a primary ground node and a control terminal;

a secondary power switch coupled between the first terminal of the secondary winding and the output terminal of the power
supply;

a secondary controller having a power terminal configured to receive the output voltage, a first feedback terminal configured
to receive a first feedback signal indicative of the output voltage and a coupling control terminal configured to generate
a frequency modulation signal based on the output voltage and the first feedback signal, wherein the frequency modulation
signal has pulses modulated based on the first feedback signal;

a coupled device having an input side coupled between the output terminal of the power supply and the coupling control terminal
to receive the output voltage and the frequency modulation signal, and an output side configured to provide a frequency control
signal based on the output voltage and the frequency modulation signal; and

a primary controller having a current sense terminal configured to receive a current sense signal indicative of a current
flowing through the primary winding, a frequency control terminal coupled to the output side of the coupled device to receive
the frequency control signal, a second feedback terminal configured to receive a second feedback signal indicative of the
output voltage, and an output terminal configured to provide a switching signal to the control terminal of the primary power
switch based on the current sense signal and the frequency control signal; wherein the primary controller comprises:

a current limit comparator having a first input terminal configured to receive the current sense signal, a second input terminal
configured to receive a peak current signal, and an output terminal configured to provide a current limit signal based on
the current sense signal and the peak current signal;

a logic circuit having a first input terminal coupled to the output side of the coupled device to receive the frequency control
signal, a second input terminal coupled to the output terminal of the current limit comparator to receive the current limit
signal, and an output terminal configured to provide a logic control signal based on the frequency control signal and the
current limit signal;

a load detecting circuit having a first input terminal configured to receive the second feedback signal, a second input terminal
configured to receive the switching signal and an output terminal configured to provide a load detecting signal based on the
second feedback signal and the switching signal;

a startup control circuit having an input terminal configured to receive the current sense signal and an output terminal configured
to provide a startup control signal based on the current sense signal; and

a selector having a first input terminal coupled to the output terminal of the startup control circuit to receive the startup
control signal, a second input terminal coupled to the output terminal of the logic circuit to receive the logic control signal,
a control terminal coupled to the output terminal of the load detecting circuit to receive the load detecting signal and an
output terminal configured to provide the startup control signal or logic control signal based on the load detecting signal;
wherein:

a frequency of the switching signal decreases as a load of the isolated switching mode power supply becomes light; and wherein
the frequency control signal has a first logical state and a second logical state, wherein a time period of the first logical
state of the frequency control signal is prolonged when the load of the isolated switching mode power supply changes from
heavy to light, and the second logical state of the frequency control signal evokes an “ON” operation of the primary power
switch.

US Pat. No. 9,590,608

BOOTSTRAP REFRESH CONTROL CIRCUIT, VOLTAGE CONVERTER AND ASSOCIATED METHOD

CHENGDU MONOLITHIC POWER ...

1. A bootstrap refresh control circuit for a voltage converter, wherein the voltage converter comprises a high side switch,
a low side switch and a bootstrap capacitor for providing a bootstrap voltage signal to supply a high side driver of the high
side switch, and wherein the voltage converter is configured to receive an input voltage at an input terminal and to provide
an output voltage at an output terminal based on driving the high side switch and the low side switch to switch on and off,
and wherein the bootstrap refresh control circuit comprising:
a bootstrap refresh module, wherein the bootstrap refresh module comprises a first comparing module having a first input terminal,
a second input terminal and an output terminal, and wherein the first input terminal of the first comparing module is configured
to receive the bootstrap voltage signal, the second input terminal of the first comparing module is configured to receive
a bootstrap refresh threshold, and the first comparing module is configured to compare the bootstrap voltage signal with the
bootstrap refresh threshold to provide a first comparing signal having a first logic state and a second logic state at the
output terminal, and wherein the first comparing signal has the first logic state when the bootstrap voltage signal is lower
than the bootstrap refresh threshold, and wherein the first comparing signal has the second logic state when the bootstrap
voltage signal is larger than the bootstrap refresh threshold; and

a voltage difference module having a first input terminal, a second input terminal and an output terminal, wherein the first
input terminal of the voltage difference module is configured to receive a feedback signal representing the output voltage
of the voltage converter, the second input terminal of the voltage difference module is configured to receive a reference
voltage signal representing a desired value of the output voltage of the voltage converter, the voltage difference module
is configured to compare the feedback signal with the reference voltage signal so as to provide a difference signal at the
output terminal; and wherein

when the first comparing signal has the first logic state, the bootstrap refresh module is configured to decrease the output
voltage of the voltage converter; and wherein when the feedback signal is smaller than the reference voltage signal, the bootstrap
refresh control circuit is configured to control the high side switch and the low side switch to switch on and off based on
the difference signal so as to charge the bootstrap capacitor for refreshing the bootstrap voltage signal.

US Pat. No. 9,653,992

CONSTANT ON-TIME SWITCHING CONVERTER WITH ADAPTIVE RAMP COMPENSATION AND CONTROL METHOD THEREOF

Chengdu Monolithic Power ...

1. A constant on-time controller used in a switching converter, wherein the switching converter includes a first switch, a
second switch, an inductor and an output capacitor, and is configured to convert an input voltage into an output voltage,
the controller comprises:
an on-time control circuit configured to generate an on-time control signal;
a ramp compensation generator configured to generate a compensation signal;
a comparing circuit coupled to the ramp compensation generator, wherein the comparing circuit compares the sum of the compensation
signal and a feedback signal indicative of the output voltage with a reference signal to generate a comparison signal;

a logic circuit coupled to the on-time control circuit and the comparing circuit, wherein based on the on-time control signal
and the comparison signal, the logic circuit generates a control signal with a duty cycle;

a driving circuit coupled to the logic circuit, wherein based on the control signal, the driving circuit generates a first
driving signal and a second driving signal to respectively drive the first switch and the second switch; and

a feed forward circuit configured to generate a compensation control signal based on the input voltage; wherein
the ramp compensation generator is coupled to the feed forward circuit and configured to adjust the compensation signal based
on the compensation control signal, so the amplitude of the compensation signal follows a critical value proportional to the
difference between the duty cycle and the square of the duty cycle.

US Pat. No. 9,385,601

SMPS WITH OUTPUT RIPPLE REDUCTION CONTROL AND METHOD THEREOF

Monolithic Power Systems ...

1. A switching mode power supply (SMPS) for converting an input voltage at an input terminal into an output voltage at an
output terminal, the SMPS comprising:
a switch having a control end;
an inductor coupled to the switch;
a zero current detection circuit coupled to the inductor, the zero current detection circuit configured to detect an inductor
current flowing through the inductor and provide a zero current detection signal, wherein the zero current detection signal
is in an effective state only when the inductor current is at zero;

a load judgment circuit coupled to the zero current detection circuit, the load judgment circuit configured to provide a plurality
of status signals based on a zero current duration during when the zero current detection signal is in the effective state
uninterruptedly; and

a control signal generating circuit coupled to the output terminal and the load judgment circuit, the control signal generating
circuit configured to provide a control signal which is coupled to the control end of the switch, wherein the control signal
transits from a first state to a second state when a feedback signal indicative of an output signal at the output terminal
satisfies a preset condition with a reference signal, and the control signal transits from the second state to the first state
after an on time of the switch, and wherein the on time is controlled based on the plurality of status signals.

US Pat. No. 9,608,509

SWITCHING CONVERTER WITH CONTROLLABLE RESTART DELAY AND ASSOCIATED CONTROL METHOD

CHENGDU MONOLITHIC POWER ...

1. A control circuit for controlling a switching converter, the switching converter having a first switch and an output terminal
configured to provide an output voltage, the control circuit comprising:
a voltage regulating circuit, configured to provide an auxiliary power supply voltage across a capacitor;
a switching control circuit, configured to provide a pulse signal based on a reference signal and a feedback signal representative
of the output voltage;

a first logic circuit, coupled to the switching control circuit, and wherein the first logic circuit is configured to provide
a switching control signal to a control terminal of the first switch based on a protection signal and the pulse signal; and

a restart delay circuit, coupled to the voltage regulating circuit, wherein the restart delay circuit is configured to provide
an enable signal based on the protection signal and the auxiliary power supply voltage, and wherein when the protection signal
is in a first state, the enable signal is configured to disable the voltage regulating circuit and the switching control circuit
until the auxiliary power supply voltage decreases to a first threshold; and wherein

the restart delay circuit further comprising:
an under-voltage detecting circuit, having a first input terminal, a second input terminal and an output terminal, wherein
the first input terminal is coupled to the voltage regulating circuit, and the second input terminal is configured to receive
the first threshold, and the output terminal is configured to provide a reset signal based on comparing the auxiliary power
supply voltage with the first threshold; and

a flip-flop, having a set terminal, a reset terminal and an output terminal, wherein the set terminal is configured to receive
the protection signal, the reset terminal is coupled to the output terminal of the under-voltage detecting circuit to receive
the reset signal, and the output terminal is configured to provide the enable signal based on the protection signal and the
reset signal.

US Pat. No. 9,472,943

OFFLINE POWER CONVERTER AND THE METHOD THEREOF

MONOLITHIC POWER SYSTEMS,...

1. An offline power converter, comprising:
an input port configured to receive an input voltage;
an output port configured to provide an output voltage;
a rectifier coupled to the input port to receive the input voltage, and to provide a rectified DC voltage based on the input
voltage;

a normally-on power device coupled to the rectifier to receive the rectified DC voltage, and to provide a clipped voltage
based on the rectified DC voltage;

a power switch having a first terminal, a second terminal and a control terminal, the first terminal being coupled to the
normally-on power device to receive the clipped voltage, the second terminal being coupled to the output port;

a first comparator having a first input terminal configured to receive a first threshold, a second input terminal configured
to receive a first sense signal indicative of the clipped voltage, and an output terminal configured to provide a first comparison
signal based on the first threshold and the first sense signal;

a second comparator having a first input terminal configured to receive a second threshold, a second input terminal configured
to receive a second sense signal indicative of the rectified DC voltage, and an output terminal configured to provide a second
comparison signal based on the second threshold and the second sense signal; and

a logic and drive unit having a first input terminal coupled to the output terminal of the first comparator to receive the
first comparison signal, a second input terminal coupled to the output terminal of the second comparator to receive the second
comparison signal, and an output terminal configured to provide a driving signal to the control terminal of the power switch,
the driving signal having a slow-sloping ramp down when the first sense signal goes higher than the first threshold, and having
a substantial vertical ramp down when the second sense signal goes higher than the second threshold.

US Pat. No. 9,401,659

HIGH VOLTAGE ANALOG SWITCH

Monolithic Power Systems,...

1. A high voltage analog switch comprising:
a first output switch comprising a first node coupled to a first end node of the high voltage analog switch and a second node
coupled to a first node of a second output switch, the first end node of the high voltage analog switch being coupled to receive
a high voltage transducer excitation signal, the first output switch including a clamp circuit that keeps the first output
switch open when the high voltage analog switch is OFF;

the second output switch comprising a second node coupled to a second end node of the high voltage analog switch, the second
end node of the high voltage analog switch being coupled to a piezoelectric transducer; and

a third output switch comprising a first node coupled to the second node of the first output switch and the first node of
the second output switch, the third output switch comprising a second node coupled to ground,

wherein the first and second output switches are closed and the third output switch is open to pass the high voltage transducer
excitation signal from the first end node to the second end node of the high voltage analog switch when the high voltage analog
switch is ON, and the first and second output switches are open and the third output switch is closed when the high voltage
analog switch is OFF,

wherein the first output switch comprises a first transistor and a second transistor forming an analog switch, and
the clamp circuit comprises a third transistor having a first terminal, a second terminal, and a gate, the first terminal
of the third transistor being coupled to a gate of the first transistor and a gate of the second transistor, the second terminal
of the third transistor being coupled to a source of the first transistor and a source of the second transistor, and the third
transistor is ON to shunt the gates and the sources of the first and second transistors together when the first output switch
is open.

US Pat. No. 9,577,514

PEAK SAMPLE CIRCUIT FOR AC VOLTAGE AND METHOD THEREOF

CHENGDU MONOLITHIC POWER ...

1. A peak sample circuit for AC voltage, the peak sample circuit comprising:
a rectifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal
and the second input terminal are coupled to receive an AC voltage, the rectifier rectifies the AC voltage and provides a
rectified signal at the output terminal;

a delay circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal
of the rectifier to receive the rectified signal, the delay circuit delays the rectified signal and provides a delayed rectified
signal at the output terminal;

a comparison circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is coupled to the output terminal of the rectifier to receive the rectified signal, the second input terminal is
coupled to the output terminal of the delay circuit to receive the delayed rectified signal, the comparison circuit compares
the rectified signal with the delayed rectified signal and provides a square signal at the output terminal; and

a sample output circuit has an input terminal, an output terminal and a control terminal, wherein the input terminal is coupled
to the output terminal of the rectifier to receive the rectified signal, the control terminal is coupled to the output terminal
of the comparison circuit to receive the square signal, the sample output circuit samples the rectified signal based on the
square signal and provides a peak sample signal representative of the peak value of the AC voltage at the output terminal.

US Pat. No. 9,634,572

SWITCHING MODE POWER SUPPLY AND THE CONTROLLER AND THE METHOD THEREOF

Chengdu Monolithic Power ...

1. A controller used in a switching mode power supply, the switching mode power supply having a power stage and a resonant
tank, the power stage including a first power switch and a second power switch coupled in series, and the resonant tank including
a resonant inductor and a resonant capacitor, the controller comprising:
a polarity evaluating circuit, configured to receive a clock signal and a current sense signal indicative of a current flowing
through the resonant inductor, wherein the polarity evaluating circuit generates a capacitive evaluated signal based on the
current sense signal and the clock signal;

a control and logic circuit, configured to receive the clock signal and the capacitive evaluated signal, to generate a first
logical signal and a second logical signal;

a logic delay circuit, coupled to the control and logic circuit to receive the first logical signal and the second logical
signal, wherein the logic delay circuit generates a first logical delayed signal and a second logical delayed signal based
on the first logical signal and the second logical signal; and

a driven circuit, coupled to the logical delay circuit to receive the first logical delayed signal and the second logical
delayed signal to generate a first driving signal and a second driving signal, to control the first power switch and the second
power switch, respectively.

US Pat. No. 9,608,516

BATTERY DISCHARGE CIRCUIT AND DISCHARGE METHOD WITH OVER DISCHARGE PROTECTION

CHENGDU MONOLITHIC POWER ...

1. A battery discharge circuit comprising:
a switching circuit coupled between a battery and a load, wherein the switching circuit is configured to receive a battery
voltage and provide an output signal to the load; and

a controller configured to generate a control signal to control the switching circuit, wherein when the battery voltage drops
below a first reference voltage, the controller adjusts the control signal to reduce a discharge current drawn by the switching
circuit from the battery, so as to regulate the battery voltage to be equal to the first reference voltage; wherein

the controller comprises:
a first error amplifying circuit configured to receive the battery voltage and the first reference voltage, wherein the first
error amplifying circuit generates a first compensation signal based on the difference between the battery voltage and the
first reference voltage;

a second error amplifying circuit configured to receive a second reference voltage and a feedback signal indicative of the
output signal,

wherein the second error amplifying circuit generates a second compensation signal based on the difference between the second
reference voltage and the feedback signal; and

a selection circuit coupled to the first error amplifying circuit and the second error amplifying circuit, wherein the selection
circuit selects the first compensation signal as a compensation signal when the battery voltage is lower than the first reference
voltage, and selects the second compensation signal as the compensation signal when the battery voltage is higher than the
first reference voltage; and

a PWM circuit coupled to the selection circuit to receive the compensation signal, wherein based on the compensation signal,
the PWM circuit generates the control signal to control the switching circuit.

US Pat. No. 9,473,027

VOLTAGE REGULATOR WITH HYBRID ADAPTIVE VOLTAGE POSITION AND CONTROL METHOD THEREOF

MONOLITHIC POWER SYSTEMS,...

1. A controller used in a voltage regulator with adaptive voltage position, wherein the voltage regulator is configured to
provide an output voltage and an output current, and comprises a resistor having a first terminal coupled to the output voltage
and a second terminal, the controller comprises:
a controllable current source coupled to the second terminal of the resistor, wherein the controllable current source is configured
to provide a main current proportional to the output current;

a current digital-analog converter configured to receive a digital signal and the output current, wherein based on the digital
signal and the output current, the current digital-analog provides a tuning current to the second terminal of the resistor
to vary the slope of the output voltage relative to the output current, and wherein the tuning current is proportional to
the output current and a function of the digital signal; and

an error amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is configured to receive a reference voltage, the second input terminal is coupled to the second terminal of the
resistor, and the output terminal is configured to provide a compensation signal to adjust the output voltage.

US Pat. No. 9,641,085

SWITCHING POWER CONVERTER, CLOCK MODULE, CONTROL CIRCUIT AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A clock module for providing a clock signal to a power converter, wherein the power converter has a startup procedure beginning
at the moment when the power converter is powered on and ending when an output voltage of the power converter arrives at a
desired steady state value, the clock module comprising:
a clock generator, having a clock control terminal and a clock output terminal, wherein the clock control terminal is configured
to receive a frequency regulation signal, and wherein the clock generator is configured to provide the clock signal at the
clock output terminal, and wherein the clock signal has a sequence of clock pulses and a clock frequency; and

a clock frequency modulator, having a modulator input terminal and a modulator output terminal, wherein the modulator input
terminal is configured to receive the clock signal, and wherein the clock frequency modulator is configured to perform a timing
based on the pulses of the clock signal and to provide the frequency regulation signal at the modulator output terminal based
on the timing, and wherein the frequency regulation signal is configured to set the clock frequency at a first predetermined
frequency at the moment when the power converter is powered on, and to regulate the clock frequency to increase from the first
predetermined frequency to a second predetermined frequency through a predetermined times of step type frequency increase
during the startup procedure.

US Pat. No. 9,634,570

MULTI-MODE POWER CONVERTER AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A multi-mode power converter comprising:
an input port;
an output port;
a switching terminal coupled to the input port through an inductive element;
a first transistor coupled between the switching terminal and a ground;
a second transistor and a third transistor coupled in series between the switching terminal and the output port; wherein
the multi-mode power converter has a boost operation mode and a buck operation mode; and wherein
in the boost operation mode, the second transistor is ON while the first transistor and the third transistor are switched
ON and OFF complementarily, or the second transistor and the third transistor are switched ON and OFF substantially simultaneously
while the first transistor and the third transistor are switched ON and OFF complementarily; and wherein

in the buck operation mode, the second transistor is ON while the first transistor and the third transistor are switched ON
and OFF complementarily, and wherein an on-resistance of the second transistor is regulated to ensure the multi-mode power
converter operates normally in the buck operation mode.

US Pat. No. 9,621,028

DIGITALLY CONTROLLED PFC CONVERTER WITH MULTIPLE DISCONTINUOUS MODES

CHENGDU MONOLITHIC POWER ...

1. A control method for controlling a power factor correction circuit, wherein the power factor correction circuit comprises
a switching circuit having an input terminal configured to receive an input voltage and an input current, and an output terminal
configured to provide an output voltage, the control method comprising:
providing a peak current sampling signal indicative of a maximum value of the input current;
providing an input voltage sampling signal indicative of the input voltage;
providing an output voltage sampling signal indicative of the output voltage;
providing a current reference signal based on the input voltage sampling signal, the output voltage sampling signal and a
voltage reference signal;

providing a turn ON delay time period based on the peak current sampling signal and the current reference signal;
providing a comparison signal via comparing the input current with an OFF current reference signal;
determining an operation mode of the switching circuit based on the input current and a switching frequency of the switching
circuit, wherein the operation mode comprises a continuous current mode, a first discontinuous current mode and a second discontinuous
current mode; and

turning ON the switching circuit based on the comparison signal, and turning OFF the switching circuit when an ON-time period
of the switching circuit equals a predetermined ON-time period; wherein

when the switching circuit works under the continuous current mode, turning ON the switching circuit when the input current
is less than the OFF current reference signal, and calculating the predetermined ON-time period based on the input voltage
sampling signal; wherein

and calculating the predetermined ON-time period based on the input voltage sampling signal; and wherein
when the switching circuit works under the second discontinuous current mode, turning ON the switching circuit after the turn
ON delay time period when the input current is less than the OFF current reference signal, and calculating the predetermined
ON-time period based on the input voltage sampling signal, the current reference signal and the peak current sampling signal.

US Pat. No. 9,577,520

POWER CONVERTER WITH BOOTSTRAP CIRCUIT

CHENGDU MONOLITHIC POWER ...

1. A bootstrap circuit for a power converter, wherein the power converter comprises a high side switch, a low side switch
and a bootstrap capacitor for providing a bootstrap voltage to supply a high side driver of the high side switch, and wherein
the bootstrap capacitor has a first terminal and a second terminal, and wherein the power converter is configured to receive
an input voltage and to provide an output voltage by means of turning the high side switch and the low side switch on and
off, the bootstrap circuit comprising:
a first charging circuit having an input terminal and an output terminal, wherein the input terminal is configured to receive
the input voltage, and wherein the output terminal is coupled to the first terminal of the bootstrap capacitor;

a first comparing circuit having a first input terminal, a second input terminal and an output terminal, wherein the first
input terminal is configured to receive the input voltage, and wherein the second input terminal is configured to receive
the output voltage, and further wherein based on a first threshold voltage and a voltage difference between the input voltage
and the output voltage, the first comparing circuit is configured to provide a comparing signal at the output terminal;

a boost circuit having an input terminal and an output terminal, wherein the input terminal is configured to receive the input
voltage or the output voltage, and wherein the output terminal is configured to provide a first high voltage; and

a second charging circuit having an input terminal, a control terminal and an output terminal, wherein the input terminal
is configured to receive the first high voltage, and wherein the output terminal is coupled to the first terminal of the bootstrap
capacitor, and wherein the control terminal is configured to receive the comparing signal, and wherein the second charging
circuit is configured to charge the bootstrap capacitor when the voltage difference between the input voltage and the output
voltage is smaller than the voltage threshold.

US Pat. No. 9,559,586

SWITCH MODE POWER SUPPLY, CONTROL CIRCUIT AND ASSOCIATED CONTROL METHOD

CHENGDU MONOLITHIC POWER ...

1. A control circuit to control a switch mode power supply, the switch mode power supply having a first switch with a control
terminal, an input terminal configured to receive an input voltage and an output terminal configured to provide an output
voltage, wherein the control circuit comprising:
a first comparison circuit, having a first input terminal, a second input terminal and an output terminal, wherein the first
input terminal of the first comparison circuit is configured to receive a feedback signal indicating the output voltage, the
second input terminal of the first comparison circuit is configured to receive a reference voltage, and the output terminal
of the first comparison circuit is configured to provide a setting signal;

an on-time control circuit, configured to receive the input voltage, the output voltage and a mode control signal and provide
an on-time control signal based on the input voltage, the output voltage and the mode control signal, wherein the on-time
control signal is configured to control an on-time period of the first switch; and

a logic circuit, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal
of the logic circuit is configured to receive the setting signal, the second input terminal of the logic circuit is configured
to receive the on-time control signal, and the output terminal of the logic circuit is configured to provide a switching control
signal to the control terminal of the first switch; and wherein

when the mode control signal is in a first state, the switch mode power supply is configured to work in a power saving mode,
the on-time period of the first switch is proportional to a first constant value to decrease a switching frequency of the
first switch to improve efficiency; and

when the mode control signal is in a second state, the switch mode power supply is configured to work in a normal mode, the
on-time period of the first switch is proportional to a second constant value to increase the switching frequency of the first
switch to improve load transient performance, wherein the first constant value is larger than the second constant value.

US Pat. No. 9,407,148

MULTI-PHASE SMPS WITH LOOP PHASE CLOCKS AND CONTROL METHOD THEREOF

Monolithic Power Systems,...

1. A multi-phase Switching Mode Power Supply (SMPS), comprising:
N switching circuits, each switching circuit comprising a switch, wherein the N switching circuits are coupled to an output
terminal configured to provide an output voltage for supplying a load, where N is a natural number greater than 1;

a setting signal generator having an input coupled to the output terminal and having an output configured to provide a setting
signal, wherein the setting signal is generated according to a feedback signal indicative of an output signal at the output
terminal;

a clock signal generator having an output configured to provide a system clock signal; and
a controller having a first input coupled to the output of the setting signal generator configured to receive the setting
signal, a second input coupled to the output of the clock signal generator configured to receive the system clock signal,
and N outputs configured to provide N switching control signals, wherein each of the respective switching control signals
is configured to control a corresponding switching circuit of the N switching circuits, and wherein the controller is configured
to generate N shifted phase clock signals according to the system clock signal, and wherein the N shifted phase clock signals
have the same frequency with the system clock signal and form a set of loop phase clocks, and further wherein the N switching
control signals are generated based on the setting signal and the N shifted phase clock signals, wherein when the setting
signal is in an effective state and a shifted phase clock signal of the N shifted phase clock signals transits from a first
state to a second state, a corresponding switching control signal of the N switching control signals transits from a first
logic state to a second logic state, and the corresponding switching control signal transits from the second logic state to
the first logic state after a time period.

US Pat. No. 9,312,773

BOOTSTRAP REFRESH CONTROL CIRCUIT, POWER CONVERTER AND ASSOCIATED METHOD

Monolithic Power Systems,...

1. A bootstrap refresh control circuit for a power converter, wherein the power converter comprises a high side switch, a
low side switch and a bootstrap capacitor for providing a bootstrap voltage to supply a high side driver of the high side
switch, and wherein the power converter is configured to receive an input voltage and to provide an output voltage and an
output current based on driving the high side switch and the low side switch to switch on and off, the bootstrap refresh control
circuit comprising:
a first comparison module having a first comparing input terminal, a second comparing input terminal and a first comparing
output terminal, wherein the first comparing input terminal is configured to receive the bootstrap voltage, the second comparing
input terminal is configured to receive a first threshold signal, and the first comparison module is configured to compare
the bootstrap voltage with the first threshold signal to provide a bootstrap refresh signal at the first comparing output
terminal; and

a control module having a first control input terminal configured to receive the bootstrap refresh signal, wherein the control
module is configured to regulate the on and off switching of the high side switch and the low side switch at least partially
based on the bootstrap refresh signal so as to control charging of the bootstrap capacitor, and wherein the control module
is configured to regulate the high side switch and the low side switch to switch on and off in complementary with a substantially
constant frequency when the bootstrap voltage is lower than the first threshold signal

further wherein
the bootstrap refresh signal has a first logic state when the bootstrap voltage is lower than the first threshold signal and
has a second logic state when the bootstrap voltage is higher than the first threshold signal; and wherein

the control module further has a second control input terminal configured to sense the output voltage, and a third control
input terminal configured to sense the output current; and wherein

the control module is configured to regulate the high side switch and the low side switch to switch on and off in complementary
with the substantially constant frequency in response to the first logic state of the bootstrap refresh signal, and is configured
to regulate the high side switch and the low side switch to switch on and off according to the output voltage and the output
current in response to the second logic state of the bootstrap refresh signal.

US Pat. No. 9,070,671

MICROELECTRONIC FLIP CHIP PACKAGES WITH SOLDER WETTING PADS AND ASSOCIATED METHODS OF MANUFACTURING

Monolithic Power Systems,...

13. A method for fabricating a semiconductor assembly, comprising:
forming an attachment area and a non-attachment area on a lead finger of a lead frame;
contacting an electrical coupler carried by a semiconductor die with the attachment area of the lead finger;
reflowing the electrical coupler while the electrical coupler is in contact with the attachment area of the lead finger; and
preventing the electrical coupler from migrating away from the attachment area toward the non-attachment area; and wherein:
the attachment area has a first wettability to the electrical coupler during reflow;
the non-attachment area has a second wettability to the electrical coupler during reflow; and
preventing the electrical coupler from migrating includes treating at least one of the attachment area and the non-attachment
area such that the second wettability is less than the first wettability for a target amount; and

the method further includes determining the target amount based on a target degree of migration of the electrical coupler
from the attachment area during reflow; and

preventing the electrical coupler from migrating includes at least one of (a) depositing silver (Ag) onto a first portion
of the lead finger or (b) oxidizing a second portion of the lead finger.

US Pat. No. 9,812,950

PFC CONTROL CIRCUIT, DIGITAL PFC CIRCUIT AND THE METHOD THEREOF

Chengdu Monolithic Power ...

1. A PFC control circuit used in a power converting system, the power converting system including an input capacitor, the
power converting system configured to receive an input line voltage and generate an output voltage by controlling a power
switch, the PFC control circuit comprising:
an analogue to digital unit, configured to receive a feed forward signal indicative of the input line voltage, to generate
a digital voltage signal;

a cycle calculating unit, configured to receive the digital voltage signal, to calculate a cycle of the input line voltage
to generate a cycle signal;

a compensation current generating unit, configured to receive the cycle signal to generate a compensation current, wherein
the compensation current is complementary to a current flowing through the input capacitor;

a reference current adjust unit, configured to receive the compensation current, to execute an operation on the compensation
current and an original reference current signal, to generate an adjusted reference current signal; and

a PFC controller, configured to receive the adjusted reference current signal and a current sense signal indicative of a current
flowing through the power switch, to generate a logical control signal to control the power switch;

wherein the cycle calculating unit comprises:
a peak detecting module, configured to receive the digital voltage signal to detect a peak value of the digital voltage signal,
and to generate a peak signal;

a threshold setting module, configured to receive the peak signal to generate a first threshold and a second threshold with
close voltage levels with each other, wherein both the first threshold and the second threshold are lower than the peak signal;

a threshold detecting module, configured to receive the first threshold and the second threshold, and configured to receive
the digital voltage signal, to generate a trig signal when the digital voltage signal at its right half cycle is between the
first threshold and the second threshold; and

a time counter module, configured to receive the trig signal to generate the cycle signal, wherein a time interval of successive
two beings between the first threshold and the second threshold of the digital voltage signal at its right half cycle is the
cycle of the input line voltage.

US Pat. No. 9,230,956

JUNCTION FIELD EFFECT TRANSISTORS AND ASSOCIATED FABRICATION METHODS

Chengdu Monolithic Power ...

1. A junction field effect transistor, comprising:
a semiconductor substrate of a first doping type, wherein the semiconductor substrate is configured as a drain region;
an epitaxial layer of the first doping type located on the semiconductor substrate;
a body region of a second doping type located in the epitaxial layer, wherein the second doping type is different from the
first doping type;

a source region of the first doping type located in the epitaxial layer;
a gate region of the second doping type located in the body region; and
a shielding layer of the second doping type located in the epitaxial layer, wherein the shielding layer is in a conductive
path formed between the source region and the drain region; and wherein

the shielding layer is in complementary pattern to the body region.

US Pat. No. 9,812,975

RESONANT CONVERTER WITH CAPACITIVE MODE CONTROL AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

8. A control circuit used for controlling a resonant converter, comprising:
a voltage sensing circuit, configured to sense an output voltage signal of the resonant converter to generate a feedback voltage
signal;

a current sensing circuit, configured to sense a current flowing through a resonant inductor of the resonant converter to
generate a current sense signal;

a mode judging circuit, configured to receive the current sense signal, and further configured to compare the current sense
signal with a zero-crossing threshold to generate a mode signal, wherein the mode signal is configured to judge whether the
resonant converter operates in an inductive mode or a capacitive mode; and

a frequency controller, configured to receive the mode signal and the feedback voltage signal, and further configured to generate
a high-side control signal and a low-side control signal respectively used for controlling a high-side switch and a low-side
switch of the resonant converter based on the feedback voltage signal and the mode signal, wherein the frequency controller
comprises a setting capacitor, and wherein the frequency controller further comprises N up thresholds and N low thresholds,
and wherein each of the N up thresholds is corresponding to each of the N low thresholds, and wherein each of the N up thresholds
is higher than each of the N low thresholds correspondingly, and wherein N is a positive integer and is larger than or equal
to 2, and wherein

when the resonant converter operates in the inductive mode, the frequency controller is configured to compare a setting voltage
signal across the setting capacitor with the largest one of the N up thresholds, and with the smallest one of the N low thresholds
in each operation cycle to generate the high-side control signal and the low-side control signal, wherein the operation cycle
comprises one or more switching cycles of the resonant converter, and wherein

when the resonant converter enters into the capacitive mode, the frequency controller is configured to compare the setting
voltage signal with each of the N up thresholds sequentially operation cycle by operation cycle, and with each of the N low
thresholds sequentially operation cycle by operation cycle to generate the high-side control signal and the low-side control
signal, and wherein

the frequency controller is further configured to change a switching frequency of the resonant converter by varying the N
up thresholds and the N low thresholds.

US Pat. No. 9,602,004

EFFICIENT CONTROL CIRCUIT FOR BUCK-BOOST CONVERTERS AND CONTROL METHOD THEREOF

CHENGDU MONOLITHIC POWER ...

7. A buck-boost converter comprising:
a first switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is configured
to receive an input voltage;

a second switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to
the second terminal of the first switch, the second terminal is grounded;

an inductor having a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of
the first switch and the first terminal of the second switch;

a third switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to
the second terminal of the inductor, the second terminal is grounded;

a fourth switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to
the second terminal of the inductor and the first terminal of the third switch, the second terminal is configured to provide
an output voltage;

an output capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal
of the fourth switch, the second switch is grounded;

a feedback circuit coupled to the second terminal of the fourth switch, wherein the feedback circuit is configured to generate
a feedback signal representative of the output voltage;

a logic control circuit coupled to the feedback circuit, wherein the logic control circuit is configured to generate a logic
control signal based on a reference signal and the feedback signal;

a pulse width increasing circuit coupled to the logic control circuit, wherein the pulse width increasing circuit is configured
to generate a sum control signal based on the logic control signal, and wherein the pulse width increasing circuit increases
the pulse width of the logic control signal by a first predetermined value to generate the pulse width of the sum control
signal;

a pulse width decreasing circuit coupled to the logic control circuit, wherein the pulse width decreasing circuit is configured
to generate a difference control signal based on the logic control signal, and wherein the pulse width decreasing circuit
decreases the pulse width of the logic control signal by a second predetermined value to generate the pulse width of the difference
control signal;

a first driving circuit coupled to the pulse width increasing circuit, wherein based on the sum control signal, the first
driving circuit generates a first driving signal and a second driving signal to respectively control the first switch and
the second switch; and

a second driving circuit coupled to the pulse width decreasing circuit, wherein based on the difference control signal, the
second driving circuit generates a third driving signal and a fourth driving signal to respectively control the third switch
and the fourth switch.

US Pat. No. 9,467,136

MONOLITHIC INTEGRATED CIRCUIT SWITCH DEVICE WITH OUTPUT CURRENT BALANCING FOR PARALLEL-CONNECTION

Monolithic Power Systems,...

1. An electrical circuit comprising:
a first monolithic integrated circuit (IC) switch device comprising a first pin, a second pin, and a power switch that connects
the first pin of the first monolithic IC switch device to the second pin of the first monolithic IC switch device through
the power switch of the first monolithic IC switch device when the electrical circuit is turned ON; and

a second monolithic IC switch device having a first pin, a second pin, and a power switch that connects the first pin of the
second monolithic IC switch device to the second pin of the second monolithic IC switch device through the power switch of
the second monolithic IC switch device when the electrical circuit is turned ON, the first pin of the second monolithic IC
switch device being connected to the first pin of the first monolithic IC switch device, the second pin of the second monolithic
IC switch device being connected to the second pin of the first monolithic IC switch device,

wherein the second monolithic IC switch device further comprises a current balancing circuit that controls the power switch
of the second monolithic IC switch device to reduce an output current of the second monolithic IC switch device when the output
current of the second monolithic IC switch device is greater than an average of output currents of monolithic IC switch devices
in the electrical circuit.

US Pat. No. 9,246,404

POWER CONVERTER WITH ACTIVE BLEEDING AND RAMP UP-DOWN DELAY AND THE METHOD THEREOF

Monolithic Power Systems,...

1. A power converter, comprising:
an input port configured to receive an input AC signal;
a rectifier coupled to the input port to receive the input AC signal, and based on the input AC signal, the rectifier provides
a rectified DC signal;

a storage port configured to provide a storage voltage;
a storage capacitor coupled between the storage port and a reference ground to store energy;
a first high voltage power device and a power switch device coupled in series between the rectifier and the storage port;
and

an active bleeding unit having a first input terminal, a second input terminal, a third input terminal and an output terminal,
wherein the first input terminal is coupled to the storage port to receive the storage voltage, the second input terminal
is configured to receive a voltage threshold, the third input terminal is coupled to a connection node of the rectifier and
the first high voltage power device, and the output terminal is coupled to the storage port, wherein when the storage voltage
falls to the voltage threshold, the active bleeding unit is turned on to pull down the rectified DC signal, and when the storage
voltage is above the voltage threshold, the active bleeding unit is in an off state, wherein the active bleeding unit includes
a comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal
is configured to receive the storage voltage, the second input terminal is configured to receive the voltage threshold, wherein
based on the storage voltage and the voltage threshold, the comparator generates a comparison signal at the output terminal
and the comparison signal is provided to a discharge switch.

US Pat. No. 9,219,146

HIGH VOLTAGE PMOS AND THE METHOD FOR FORMING THEREOF

Monolithic Power Systems,...

1. A high voltage PMOS, comprising:
a P-type substrate;
an N-buried layer (NBL) formed on the P-type substrate;
an epitaxy formed on the NBL;
a field oxide formed on the epitaxy;
a low voltage P-well formed in the epitaxy;
an N-type well region formed in the epitaxy;
a thick gate oxide formed on the low voltage P-well and the field oxide;
a thin gate oxide formed on the N-type well region, on the low voltage P-well and on the epitaxy;
a gate poly formed on the thin gate oxide and on the thick gate oxide;
an N-type highly doped region formed in the N-type well region, wherein the N-type highly doped region is adjacent to the
second P-type highly doped region;

a first P-type highly doped region formed in the low voltage P-well, wherein the first P-type highly doped region is adjacent
to the field oxide; and

a second P-type highly doped region formed in the N-type well region, wherein the second P-type highly doped region is adjacent
to the gate poly, and is tied to the N-type highly doped region electrically;

wherein the space between N-type well region and the low voltage P-well is in a range of 0.5 ?m˜1 ?m.

US Pat. No. 9,087,774

LDMOS DEVICE WITH SHORT CHANNEL AND ASSOCIATED FABRICATION METHOD

Monolithic Power Systems,...

9. A method of fabricating an LDMOS device, comprising:
forming a gate of the LDMOS device on a semiconductor substrate;
implanting dopants of a first conductivity type into a body region of the LDMOS device vertically, and implanting lightly
doped substances of a second conductivity type different from the first conductivity type by sharing the same mask with the
body region with a shallower junction than that of the body region;

performing a rapid thermal annealing process to form a short channel of the LDMOS device and at the meantime to activate the
lightly doped substances to form a lightly doped drain (LDD) region; and

forming a source region and a drain contact region of the LDMOS device, wherein the source region and the drain contact region
are of a second conductivity type different from the first conductivity type.

US Pat. No. 10,091,846

LED DRIVING SYSTEM AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A LED driving system, having an input terminal configured to receive an input voltage, a first output terminal configured to provide a first output voltage for a first LED array, and a second output terminal configured to provide a second output voltage for a second LED array, wherein each of the first LED array and the second LED array comprises multiple LED strings coupled in parallel, wherein each of the LED strings in the first LED array has a cathode terminal and an anode terminal, and each of the LED strings in the second LED array has a cathode terminal and an anode terminal, the LED driving system comprising:an energy storage component, having a first terminal and a second terminal, wherein the first terminal is coupled to the input terminal of the LED driving system to receive the input voltage;
a power switch, coupled between the second terminal of the energy storage component and a reference ground;
a first output switch, coupled between the second terminal of the energy storage component and the first output terminal of the LED driving system; and
a second output switch, coupled between the second terminal of the energy storage component and the second output terminal of the LED driving system; wherein
when the power switch is on, the energy storage component is configured to store energy, when the power switch is off, the energy storage component is configured to release energy to the first output terminal and the second output terminal of the LED driving system alternately, wherein according to a minimum value of voltages at the cathode terminals of the multiple LED strings in the first LED array, the LED driving system is configured to control a duty cycle of the first output switch to adjust the first output voltage, and according to a minimum value of voltages at the cathode terminals of the multiple LED strings in the second LED array, the LED driving system is configured to control a duty cycle of the power switch to adjust the second output voltage, wherein the second output voltage is larger than the first output voltage.

US Pat. No. 9,502,251

METHOD FOR FABRICATING LOW-COST ISOLATED RESURF LDMOS AND ASSOCIATED BCD MANUFACTURING PROCESS

MONOLITHIC POWER SYSTEMS,...

1. A method for fabricating a LDMOS device in a semiconductor substrate of a first doping type, comprising:
implanting a series of dopants into the semiconductor substrate using a first mask, and forming a first region of a second
doping type adjacent to the surface of the semiconductor substrate, a second region of the first doping type located beneath
the first region, and a third region of the second doping type located beneath the second region;

implanting dopants into the semiconductor substrate using a second mask, and forming a fourth region of the second doping
type adjacent to the first, second and third regions, wherein the fourth region extends from the surface of the semiconductor
substrate to approximately the same depth as the third region; and

implanting dopants into the first region using a third mask, and forming a first well of the first doping type.

US Pat. No. 9,231,121

HIGH VOLTAGE CIRCUIT LAYOUT STRUCTURE

Monolithic Power Systems,...

1. A high voltage circuit layout structure, comprising:
a P-type substrate;
a first N-type tub, a second N-type tub, and a third N-type tub formed on the P-type substrate, wherein the first N-type tub's
potential and the third N-type tub's potential follow relatively with the second N-type tub's potential;

a first P-type tub having a first width formed on the P-type substrate and formed between the first N-type tub and the second
N-type tub, the first width being dependent on the punch-through voltage requirement between the first N-type tub and the
second N-type tub;

a second P-type tub having a second width formed on the P-type substrate and formed between the second N-type tub and the
third N-type tub, the second width being dependent on the punch-through voltage requirement between the second N-type tub
and the third N-type tub; and

a metal layer contacted with the first N-type tub and the second N-type tub to form a first Schottky diode and a second Schottky
diode, and the said metal layer also contacted with the first P-type tub; wherein the first N-type tub and the second N-type
tub respectively has P-plus regions in their surfaces.

US Pat. No. 9,716,432

SWITCHING CONVERTER WITH CONSTANT ON-TIME CONTROLLER THEREOF

CHENGDU MONOLITHIC POWER ...

1. A control circuit for controlling a switching circuit, wherein the switching circuit comprises a switch, and the switching
circuit is configured to convert an input voltage into an output voltage, the control circuit comprises:
an on-time generating circuit configured to generate an on-time signal;
a ramp compensation circuit configured to generate a ramp compensation signal;
a DC calibration circuit configured to generate a DC calibration signal by sampling the ramp compensation signal during a
transition period when the switch transits from a first state into a second state and holding the sampled ramp compensation
signal until a next transition period;

a comparison circuit electrically coupled to the ramp compensation circuit and the DC calibration circuit, wherein the comparison
circuit is configured to generate a comparison signal based on a feedback signal representative of the output voltage, a reference
signal, the ramp compensation signal and the DC calibration signal; and

a logic circuit electrically coupled to the on-time generating circuit and the comparison circuit, wherein the logic circuit
is configured to generate a control signal to control the switching circuit based on the on-time signal and the comparison
signal.

US Pat. No. 9,711,975

POWER BANK CIRCUIT AND THE METHOD THEREOF

Chengdu Monolithic Power ...

1. A power bank circuit, comprising:
a high voltage port;
a low voltage port;
an intermediate port;
a first power switch, coupled between the high voltage port and the intermediate port;
a second power switch, coupled between the intermediate port and a reference ground;
an inductor, coupled between the low voltage port and the intermediate port;
a first capacitor, coupled between the high voltage port and the reference ground;
a second capacitor, coupled between the low voltage port and the reference ground; and
a controller, configured to receive: a high voltage sense signal indicative of a voltage at the high voltage port, a high
port current sense signal indicative of a current flowing through the high voltage port, a low voltage sense signal indicative
of a voltage at the low voltage port, a low port current sense signal indicative of a current flowing through the low voltage
port, and wherein the controller is configured to generate a first switch control signal and a second switch control signal
to control the operations of the first power switch and the second power switch, respectively.

US Pat. No. 9,184,651

CURRENT DETECTION AND EMULATION CIRCUIT, AND METHOD THEREOF

Monolithic Power Systems,...

1. A current detection circuit for detecting a current in a SMPS, wherein the SMPS having a first switch and a second switch,
the current equaling a first switch current flowing through the first switch when a PWM signal is in a first state and equaling
a second switch current flowing through the second switch when the PWM signal is in a second state different from the first
state, the current detection circuit comprising:
a current sensing circuit for sensing the second switch current, the current sensing circuit having a first input, a second
input and an output, wherein the first input of the current sensing circuit is coupled to a first end of the second switch,
the second input of the current sensing circuit is coupled to a second end of the second switch, and the output of the current
sensing circuit is configured to provide a current sensing signal indicative of the second switch current; and

a current emulation circuit having an input and an output, wherein the input of the current emulation circuit is configured
to receive the current sensing signal, and the output of the current emulation circuit is configured to provide a current
emulation signal, wherein the current emulation circuit provides a first current generated based on the current sensing signal
and provides a second current generated based on the first current, and further wherein the current emulation signal is generated
based on the first current and the second current; wherein

the current detection circuit is configured to provide a current detection signal indicative of the current in the SMPS, and
wherein the current detection signal is proportional to the current emulation signal with a predetermined proportion during
a first period, and the current detection signal is proportional to the current sensing signal with the same predetermined
proportion during a second period.

US Pat. No. 9,071,142

MULTI-PHASE SMPS WITH LOAD TRANSIENT CONTROL AND ASSOCIATED CONTROL METHOD

Monolithic Power Systems,...

1. A multi-phase SMPS, comprising:
N switching circuits coupled to an output node, each switching circuit comprising a switch, wherein the multi-phase SMPS is
configured to provide an output voltage at the output node to supply a load, where N is a natural number;

a plurality of comparing circuits, each comparing circuit having a first input, a second input and an output, wherein the
first input is coupled to a threshold voltage, wherein the second input is coupled to a same feedback signal of the output
voltage and wherein the output is configured to provide a load indication signal; and

a controller, comprising a plurality of inputs and N outputs, wherein each of the plurality of inputs is coupled to an output
of a corresponding comparing circuit to receive the respective load indication signal, wherein each of the N outputs is configured
to provide a control signal that is coupled to a control end of a corresponding switch, and wherein the controller is configured
to selectively turn on a plurality of switches simultaneously according to the load indication signals.

US Pat. No. 9,059,329

POWER DEVICE WITH INTEGRATED SCHOTTKY DIODE AND METHOD FOR MAKING THE SAME

Monolithic Power Systems,...

1. A power device, comprising: a semiconductor substrate; a power transistor formed in the semiconductor substrate, wherein
the power transistor comprises a drain region, a source region, a gate region, and a drain metal coupled to the drain region;
a trench-barrier formed in the drain region of the power transistor, wherein the trench-barrier comprises a first trench and
a second trench separated by a portion of the drain region; and wherein the first and the second trenches are filled with
a conductive material, and wherein the conductive material is separated from the drain region of the power transistor by a
dielectric material, and wherein the drain metal contacts the conductive material of the first and the second trenches; and
a Schottky diode formed between the first and the second trenches, wherein the Schottky diode has an anode comprising the
drain metal and a cathode comprising a portion of the drain region of the power transistor, and wherein the trench-barrier
is configured to block a reverse leakage current of the Schottky diode.

US Pat. No. 9,787,194

PRIMARY SIDE REGULATED ISOLATION VOLTAGE CONVERTER

Chengdu Monolithic Power ...

1. A primary side regulated isolation voltage converter, comprising:
a storage element having a primary winding, a secondary winding and a tertiary winding, wherein the tertiary winding is configured
to induct an output voltage signal of the isolation voltage converter to generate a voltage feedback signal;

a controllable switch, coupled to the primary winding, wherein an input voltage signal is converted to the output voltage
signal by switching the controllable switch on and off;

a control module, configured to determine whether the isolation voltage converter is in a light load state, and further configured
to receive the voltage feedback signal and to provide a first control signal based on the voltage feedback signal, wherein
the first control signal is active when the voltage feedback signal is smaller than a voltage reference signal;

a ripple control circuit, configured to sense ripples of the output voltage signal to generate a ripple signal when the isolation
voltage converter is in the light load state, and further configured to compare the ripple signal with a ripple threshold
to generate a second control signal, wherein when the ripple signal is larger than the ripple threshold, the second control
signal is active; and

a logic circuit, configured to receive the first control signal and the second control signal, and further configured to conduct
a logic operation of the first control signal and the second control signal to generate a third control signal, wherein the
third control signal is configured to turn the controllable switch on when either the first control signal or the second control
signal is active.

US Pat. No. 9,774,253

CONTROL CIRCUIT AND ASSOCIATED METHOD FOR SWITCHING CONVERTER

Chengdu Monolithic Power ...

1. A control circuit for a switching converter with at least a power switch, the control circuit comprising:
an ON signal generating circuit having a first input terminal, a second input terminal and an output terminal, wherein the
first input terminal is configured to receive a reference signal, and wherein the second input terminal is configured to receive
a feedback signal indicating an output voltage or a load current of the switching converter, and wherein based on a comparison
result between the reference signal and the feedback signal, the ON signal generating circuit provides an ON signal at the
output terminal, wherein the ON signal generating circuit comprises a first amplifier having a first input terminal, a second
input terminal and an output terminal, and wherein the first input terminal is utilized as the first input terminal of the
ON signal generating circuit, and wherein the second input terminal is utilized as the second input terminal of the ON signal
generating circuit, and wherein the ON signal generating circuit further comprises a first comparator having a first input
terminal, a second input terminal and an output terminal, and wherein the first input terminal is coupled to the output terminal
of the first amplifier, and wherein the second input terminal is coupled to the second input terminal of the first amplifier,
and wherein the output terminal is utilized as the output terminal of the ON signal generating circuit;

a current sensing circuit having an input terminal and an output terminal, wherein based on a current flowing through the
power switch, the current sensing circuit provides a current sensing signal;

an OFF signal generating circuit having a first input terminal, a second input terminal and an output terminal, wherein the
first input terminal is configured to receive an OFF threshold signal, and wherein the second input terminal is configured
to receive the current sensing signal, and wherein based on a comparison result between the OFF threshold signal and the current
sensing signal, the OFF signal generating circuit provides an OFF signal at the output terminal;

a logic circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal
is configured to receive the ON signal, and wherein the second input terminal is configured to receive the OFF signal, and
wherein based on the ON signal and the OFF signal, the logic circuit provides a switching signal at the output terminal, and
wherein the switching signal is configured to control the power switch; and

an OFF threshold generating circuit having an input terminal and an output terminal, wherein the input terminal is configured
to receive the switching signal, and wherein the output terminal is configured to provide the OFF threshold signal, and wherein
the OFF threshold generating circuit adjusts the OFF threshold signal based on a difference between a frequency of the switching
signal and a preset frequency, so as to make the frequency of the switching signal substantially equal or larger than the
preset frequency; wherein

the OFF threshold generating circuit further comprises a clamping circuit configured to set a maximum value for the OFF threshold
signal.

US Pat. No. 9,270,176

CONSTANT ON-TIME SWITCHING CONVERTER WITH INTERNAL RAMP COMPENSATION AND CONTROL METHOD THEREOF

Monolithic Power Systems,...

1. A controller used in a switching converter, wherein the switching converter comprises a main transistor and an inductor
coupled to the main transistor, and is configured to provide an output voltage, the controller comprises:
an on timer configured to generate an on-time control signal;
a ramp generator configured to generate a ramp signal;
a comparing circuit coupled to the ramp generator, wherein the comparing circuit generates a comparison signal based on the
ramp signal, a common mode voltage, a reference signal and a feedback signal indicative of the output voltage; and

a logic circuit coupled to the on timer and the comparing circuit, wherein based on the on-time control signal and the comparison
signal, the logic circuit generates a control signal to control the main transistor; wherein

the ramp generator comprises:
an adaptive current lock circuit having a first input terminal, a second input terminal, a third input terminal and an output
terminal, wherein the first input terminal is configured to receive the common mode voltage, the second input terminal is
coupled to the logic circuit to receive the control signal, the third input terminal is configured to receive the ramp signal,
and wherein based on the common mode voltage, the control signal and the ramp signal, the adaptive current lock circuit generates
a current control signal at the output terminal;

a first one-shot circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the logic
circuit to receive the control signal;

a controllable current source having a first terminal, a second terminal and a control terminal, wherein the first terminal
is configured to receive a power supply voltage, the control terminal is coupled to the output terminal of the adaptive current
lock circuit to receive the current control signal;

a first capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal
of the controllable current source and is configured to provide the ramp signal, the second terminal is coupled to a reference
ground;

a first resistor having a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal
of the first capacitor; and

a first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled
to the second terminal of the first resistor, the second terminal is coupled to the reference ground, and the control terminal
is coupled to the output terminal of the first one-shot circuit.

US Pat. No. 9,263,937

SHORT PROTECTION CIRCUIT FOR POWER SWITCH AND ASSOCIATED PROTECTION METHOD

Monolithic Power Systems,...

1. A short protection circuit for protecting a power switch, the power switch having a first end, a second end and a control
end, the short protection circuit having a first input, a second input and an output, wherein the first input of the short
protection circuit is coupled to the first end of the power switch, the second input of the short protection circuit is coupled
to the second end of the power switch, and the output of the short protection circuit is configured to provide a short protection
signal, the short protection circuit comprising a transistor, and wherein:
the transistor has a threshold voltage;
the short protection circuit is configured to compare a differential voltage between the first end of the power switch and
the second end of the power switch to the threshold voltage of the transistor only when the power switch is in an ON state;
wherein

when the differential voltage is higher than the threshold voltage, the short protection signal transits in an effective state
configured to turn off the power switch;

further comprising an enable circuit having a first input, a second input and an output, wherein the first input of the enable
circuit is coupled to the control end of the power switch configured to receive a gate control signal, the second input of
the enable circuit is configured to receive an on-control signal and the output of the enable circuit is configured to provide
an enable signal, wherein the enable signal transits into an effective state with a blanking time after the gate control signal
transits into an effective state and the enable signal transits into an ineffective state different from the effective state
of the enable signal when either the on-control signal transits into an ineffective state or the gate control signal transits
into an ineffective state, further wherein the effective state of the gate control signal is configured to turn on the power
switch, and each of the ineffective state of the on-control signal and the ineffective state of the gate control signal are
configured to turn off the power switch;

a comparator comprising an enable switch and the transistor, the comparator having a first input, a second input, a third
input and an output, wherein the first input of the comparator is coupled to the first end of the power switch, the second
input of the comparator is coupled to the second end of the power switch, the third input of the comparator is coupled to
the output of the enable circuit configured to receive the enable signal, and the output of the comparator is configured to
provide a comparing signal, and wherein when the enable signal is in the effective state of the enable signal, the enable
switch is turned on and the comparator is configured to compare the differential voltage of the power switch to the threshold
voltage of the transistor, and wherein when the differential voltage is higher than the threshold voltage, the comparing signal
is in an effective state, and when the differential voltage is lower than the threshold voltage, the comparing signal is in
an ineffective state, and further wherein when the enable signal is in the ineffective state of the enable signal, the enable
switch is turned off, and the comparing signal is in the ineffective state of the comparing signal; and

a latch having a first input, a second input and an output, wherein the first input of the latch is configured to receive
a POR signal, the second input of the latch is coupled to the output of the comparator configured to receive the comparing
signal, and the output of the latch is configured to provide the short protection signal, and wherein when the comparing signal
transits in the effective state of the comparing signal, the short protection signal transits in the effective state of the
short protection signal, and wherein when the POR signal transits in an effective state, the short protection signal transits
in an ineffective state different from the effective state of the short protection signal.

US Pat. No. 9,093,903

POWER CONVERTER WITH VOLTAGE WINDOW AND THE METHOD THEREOF

Monolithic Power Systems,...

1. A power converter, comprising:
an input port configured to receive an input AC signal;
a rectifier coupled to the input port to receive the input AC signal, and based on the input AC signal, the rectifier provides
a rectified DC signal;

a storage port configured to provide a storage voltage;
a storage capacitor coupled between the storage port and a reference ground to store energy;
a first high voltage power device coupled to the rectifier to receive the rectified DC signal, the first high voltage power
device comprising a depletion device having an inherent pinch-off voltage, the pinch-off voltage defining a voltage window
for the rectified DC signal;

a power switch device coupled in series with the first high voltage power device, wherein the first high voltage power device
together with the power switch device blocks or passes through the rectified DC signal to the storage port: when the rectified
DC signal is within the voltage window, the power switch device and the first high voltage power device pass through the rectified
DC signal to the storage port; when the rectified DC signal is outside the voltage window, the power switch device and the
first high voltage power device block the rectified DC signal to the storage port; and

a switch controller having a first input terminal coupled to a line voltage sense signal indicative of a voltage level of
the rectified DC signal, and wherein based on the line voltage sense signal, the switch controller provides a control signal
to the power switch device.

US Pat. No. 10,075,078

CONTROL CIRCUIT FOR MAINTAINING A SWITCHING FREQUENCY FOR CONSTANT ON TIME CONVERTER

Chengdu Monolithic Power ...

1. A control circuit for a switching power converter, comprising:an ON control signal generation module configured to receive a reference signal at a first input terminal, to receive a feedback signal indicative of an output voltage or an output current of the switching power converter at a second input terminal, and to compare the feedback signal with the reference signal to provide an ON control signal at an output terminal;
an OFF control signal generation module configured to generate an OFF control signal having an inactive logic state and an active logic state; and
a logic control module configured to receive the ON control signal and the OFF control signal, and further configured to provide a switch control signal based on the ON control signal and the OFF control signal to control an ON and OFF switching of a main switch in the switching power converter, wherein the switch control signal turn the main switch ON in response to the ON control signal and turn the main switch OFF in response to the active logic state of the OFF control signal; and wherein
the OFF control signal generation module is configured to charge a first capacitor in a predetermined constant time since the main switch is turned ON and to discharge the first capacitor after the predetermined constant time, and further configured to regulate an ON time of the main switch through regulating a change of the OFF control signal from the inactive logic state to the active logic state based on a first capacitor voltage across the first capacitor to maintain a switching frequency of the main switch substantially constant when an input voltage or the output current of the power converter is changed.

US Pat. No. 9,912,236

SOFT START SWITCHING POWER SUPPLY SYSTEM

Chengdu Monolithic Power ...

13. A control method for controlling switching power supply system, comprising:
generating a feedback signal according to an output voltage of the switching power supply system;
generating an error signal according to the feedback signal and a soft start signal when the soft start signal has smaller
amplitude than a first reference signal;

generating a triangle signal according to a switching signal and the output voltage and the soft start signal when the soft
start signal has smaller amplitude than a second reference signal; and

generating a constant on time control signal according to the triangle and the error signal, the constant on time control
signal controlling power switch in the switching power supply system;

wherein the triangle signal comprises a DC bias and wherein the DC bias is based on either the soft start signal or the second
reference signal.

US Pat. No. 9,837,899

POWER CONVERTER WITH IMPROVED LOAD TRANSIENT RESPONSE AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A power converter, comprising:
an input port configured to receive an input voltage;
an output port configured to provide an output voltage;
a switch module comprising a main switch configured to switch on and off in response to a driving signal to convert the input
voltage into the output voltage, a switching current flowing through the switch module during the on and off switching of
the switch module;

a pulse width modulation module configured to respectively receive a first feedback signal indicative of the output voltage,
a reference signal indicative of a desired value of the output voltage and a second feedback signal indicative of the switching
current, and to generate an off trigger signal based on the first feedback signal, the reference signal and the second feedback
signal;

a load transient response control module configured to detect a deviation of the output voltage from the desired value of
the output voltage, and to compare the deviation with a first threshold to generate a load response control signal;

a clock generation module, configured to provide a clock signal and to reset the clock signal in response to the load response
control signal when the deviation is lower than the first threshold; and

a logic control module configured to receive the off trigger signal, the load response control signal and the clock signal,
and to generate a pulse width modulated signal based on the off trigger signal and the clock signal, and further to generate
the driving signal based on the pulse width modulated signal and the load response control signal; wherein the logic control
module is further configured to trigger the driving signal to turn the main switch on in response to the clock signal, and
to trigger the driving signal to turn the main switch off in response to the off trigger signal; and wherein the logic control
module is further configured to maintain the driving signal to drive the main switch on during the period when the deviation
is lower than the first threshold in response to the load response control signal.

US Pat. No. 9,812,963

CURRENT DETECTION AND AVERAGING CIRCUIT FOR SWITCHING POWER SUPPLIES WITH A HALF-BRIDGE SWITCH CIRCUIT TOPOLOGY

Monolithic Power Systems,...

1. An electrical circuit comprising:
a half-bridge circuit comprising a high side switch and a low side switch;
an output inductor that is connected to a switch node that is connected to a terminal of the high side switch and a terminal
of the low side switch; and

a current detection circuit that samples and holds in a first capacitor a peak of an inductor current flowing through the
output inductor during an ON time of the low side switch, samples and holds in a second capacitor a valley of the inductor
current during the ON time of the low side switch, and generates a sense inductor current that is representative of the inductor
current by combining charges stored in the first and second capacitors during a turn OFF time of the low side switch.

US Pat. No. 9,780,651

CONTROL CIRCUIT AND ASSOCIATED METHOD FOR SWITCHING CONVERTER

Chengdu Monolithic Power ...

14. A control method for a switching converter, the switching converter having a high switch and a low side switch connected
in series, the control method comprising:
turning on the high side switch;
keeping the high side switch being turned on if a current through the high side switch is smaller than a first threshold when
a preset time of the high side switch ends;

turning off the high side switch and turning on the low side switch when the current through the high side switch rises up
above the first threshold; and

turning off the low side switch when a current through the low side switch falls down below a second threshold, wherein the
second threshold is smaller than the first threshold;

wherein the high side switch is turned on based on a comparison result of a feedback signal indicative of an output voltage
of the switching converter and an amplified error signal generated by amplifying an error between a reference signal and the
feedback signal.

US Pat. No. 10,256,727

MULTI-PHASE POWER SUPPLY WITH DC-DC CONVERTER INTEGRATED CIRCUITS HAVING CURRENT SHARING FUNCTION

Chengdu Monolithic Power ...

1. An interleaved multi-phase power supply, comprising:an input terminal, configured to receive an input voltage signal;
an output terminal, configured to provide an output voltage signal;
N DC-DC converter integrated circuits (ICs), coupled between the input terminal and the output terminal, wherein N is an integer larger than or equal to 2, and wherein each of the N DC-DC converter ICs comprises:
an input pin, coupled to the input terminal to receive the input voltage signal;
a switching pin, coupled to the output terminal;
a feedback pin, configured to receive a feedback voltage signal indicative of the output voltage signal, wherein an error voltage signal is generated based on the feedback voltage signal, and wherein the error voltage signal is indicative of a difference of the feedback voltage signal and a reference voltage signal;
a current sharing pin, wherein the current sharing pin of the respective N DC-DC converter ICs are connected together to generate an average voltage signal, and wherein the average voltage signal is indicative of an average of the N error voltage signals, and wherein the value of the average voltage signal is proportional to the average of the N error voltage signals;
a power stage, configured to convert the input voltage signal to a switching voltage signal on the switching pin; and
a mismatch voltage regulation module, coupled between the feedback pin and the current sharing pin, and configured to regulate the error voltage signal to be equal to the average of the N error voltage signals.

US Pat. No. 9,892,787

MULTI-TIME PROGRAMMABLE NON-VOLATILE MEMORY CELL AND ASSOCIATED CIRCUITS

Chengdu Monolithic Power ...

1. A multi-time programmable memory cell, comprising:
a differential multi-time programmable memory cell, comprising a memory module configured to store a data, the differential
multi-time programmable memory cell is configured to erase the data stored in the memory module via an erase operation, write
the data into the memory module via a write operation, read out the data stored in the memory module and provide a first balance
signal and a second balance signal accordingly via a read operation, and load a first load control signal and a second load
control signal and provide the first balance signal and the second balance signal via a load operation; and

a second-level latch cell, coupled to the differential multi-time programmable memory cell to receive the first balance signal
and the second balance signal, and the second-level latch cell is configured to provide an output signal based on the first
balance signal, the second balance signal, a first latch control signal and a second latch control signal; wherein

the second-level latch cell is configured to generate a sampled signal via sampling the first balance signal and the second
balance signal, and the second-level latch cell is configured to provide the output signal based on the sampled signal; and
wherein

the sampled signal is being stored during when the first latch control signal is at a first state and the second latch control
signal is at a second state, and the sampled signal is being held during when the first latch control signal is in the second
state and the second latch control signal is in the first state.

US Pat. No. 9,467,045

SMPS WITH ADAPTIVE COT CONTROL AND METHOD THEREOF

MONOLITHIC POWER SYSTEMS,...

1. A Switching Mode Power Supply (SMPS), comprising:
a switching circuit having an input terminal and an output terminal, the switching circuit comprising a switch and an inductor,
wherein the switching circuit regulates an output voltage at the output terminal based on an input voltage at the input terminal
by controlling a switching action of the switch; and

a controller configured to generate a switching control signal to control the switch, wherein the switching control signal
transits from a first state to a second state when an output signal at the output terminal satisfies a predetermined condition,
and the switching control signal transits from the second state to the first state after a period of time; wherein a switching
frequency of the switch and an inductor ripple current of the inductor are both configured to vary with the input voltage;

wherein the controller comprises:
an output regulation circuit configured to generate an output regulation signal based on the output signal;
an ON time control circuit configured to generate an ON time control signal, the ON time control circuit comprising:
a ramp signal generating circuit configured to generate a ramp signal based on the input voltage and the output voltage;
a reference signal generating circuit configured to generate a reference signal based on the output voltage; and
a comparing circuit having a first input configured to receive the ramp signal, a second input configured to receive the reference
signal, and an output configured to provide the ON time control signal based on the comparison between the ramp signal and
the reference signal; and

a logic circuit having a first input configured to receive the output regulation signal, a second input configured to receive
the ON time control signal, and an output configured to provide the switching control signal;

wherein the ramp signal generating circuit comprises:
a current generating circuit configured to generate a current signal that is proportional to the voltage difference between
the input voltage and the output voltage; and

a capacitor charged by the current signal when the switch is in an ON state, and
wherein the voltage across the capacitor forms the ramp signal.

US Pat. No. 9,159,795

HIGH SIDE DMOS AND THE METHOD FOR FORMING THEREOF

Monolithic Power Systems,...

1. A high side DMOS, comprising:
a substrate of a first doping type;
a buried layer of a second doping type formed in the substrate;
an epitaxial layer formed on the substrate;
a first well region of the second doping type formed in the epitaxial layer;
a second well region of the first doping type formed in the epitaxial layer, the second well region being adjacent to the
first well region;

a base region of the first doping type formed in the first well region, the base region and the first well region forming
a body-well junction;

a body pickup region of the first doping type formed in the base region;
a source pickup region of the second doping type formed in the base region, the source pickup region being adjacent to the
body pickup region;

a drain pickup region of the second doping type formed in the first well region;
a field oxide formed on the epitaxial layer;
a gate oxide formed on the epitaxial layer;
a thick gate oxide formed on part of the gate oxide, on part of the epitaxial layer and on part of the field oxide;
a gate poly formed on the field oxide, on the gate oxide and on the thick gate oxide, the gate poly comprising a termination
part and an ordinary part, the termination part including an active poly across the body-well junction, a first extended poly
on the gate oxide and on the thick gate oxide, and a second extended poly on the thick gate oxide and on the field oxide,
wherein the active poly, the first extended poly and the second extended poly are continuous and present as stair-field plate;

a source electrode contacted with the body pickup region and with the source pickup region;
a drain electrode contacted with the drain pickup region; and
a gate electrode contacted with the ordinary part of the gate poly.

US Pat. No. 9,059,633

ENERGY HARVEST SYSTEM AND THE METHOD THEREOF

Monolithic Power Systems,...

1. An energy harvest system, comprising:
an energy harvester configured to provide an AC source, the energy harvest having a first terminal and a second terminal;
a storage port configured to provide a storage voltage;
a first transistor coupled between the first terminal of the energy harvester and the storage port;
a second transistor coupled between the first terminal of the energy harvester and a reference ground;
a third transistor coupled between the second terminal of the energy harvester and the storage port;
a fourth transistor coupled between the second terminal of the energy harvester and the reference ground; and
a storage capacitor coupled between the storage port and the reference ground; wherein
the first transistor and the second transistor operate at relatively low switching frequency, while the third transistor and
the fourth transistor operate at relatively high switching frequency.

US Pat. No. 10,063,078

BUCK-BOOST BATTERY CHARGING CIRCUIT, CONTROL CIRCUIT AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

9. A battery charging circuit, comprising:an input port, configured to receive an input voltage;
an output port, configured to provide a system voltage;
a first switching circuit comprising a first switch and a second switch, the first switching circuit is coupled between the input port and a node;
a second switching circuit comprising a third switch and a fourth switch, the second switching circuit is coupled in parallel with the first switching circuit between the input port and the node;
a fifth switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the node, and the second terminal is coupled to a system ground;
a sixth switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the node, and the second terminal is coupled to the output port; and
a control circuit, configured to receive a plurality of feedback signals and provide a first switching control signal to control the first switching circuit, a second switching control signal to control the second switching circuit, a third switching control signal to the control terminal of the fifth switch, and a fourth switching control signal to the control terminal of the sixth switch; wherein
when the input voltage is higher than the system voltage, the first switching circuit and the second switching circuit are controlled in response to the plurality of feedback signals, the fifth switch maintains OFF, and the sixth switch maintains ON; and
when the input voltage is lower than the system voltage, at least one of the first switching circuit and the second switching circuit maintains ON, and the fifth switch and the sixth switch are controlled in response to the plurality of feedback signals.

US Pat. No. 9,891,648

SWITCHING CONVERTER WITH SMART FREQUENCY GENERATOR AND CONTROL METHOD THEREOF

Chengdu Monolithic Power ...

1. A switching converter, comprising:
a switching circuit having a main transistor, wherein the switching circuit is configured to convert an input voltage into
an output voltage;

a feedback circuit coupled to the switching circuit, wherein the feedback circuit is configured to generate a feedback signal
indicative of the output voltage;

a current sensing circuit configured to sense the current flowing through the main transistor and generate a current sensing
signal;

a clock generator configured to generate a clock signal;
an error amplifying circuit coupled to the feedback circuit, wherein based on the difference between a first reference voltage
and the feedback signal, the error amplifying circuit generates a compensation signal;

a comparing circuit coupled to the current sensing circuit and the error amplifying circuit, wherein the comparing circuit
compares the current sensing signal with the compensation signal and generates a reset signal; and

a control circuit coupled to the clock generator and the comparing circuit, wherein based on the clock signal and the reset
signal, the control circuit generates a control signal to control the main transistor; wherein

the clock generator is coupled to the control circuit to receive the control signal and detect whether the on-time of the
main transistor is smaller than a time threshold based on the control signal, and wherein if the on-time of the main transistor
is smaller than the time threshold, the clock generator will adjust the frequency of the clock signal to regulate the on-time
of the main transistor to be equal to the time threshold.

US Pat. No. 9,882,489

BUCK-BOOST CONVERTERS WITH RAMP COMPENSATION

Chengdu Monolithic Power ...

11. A buck-boost converter comprising:
a first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is configured
to receive an input voltage;

a second transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled
to the second terminal of the first transistor to form a first switching node, the second terminal is coupled to a reference
ground;

a third transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal is coupled
to the reference ground;

a fourth transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled
to the first terminal of the third transistor to form a second switching node, the second terminal is configured to provide
an output voltage;

an inductor coupled between the first switching node and the second switching node;
a feedback circuit configured to generate a feedback signal indicative of the output voltage;
a first filtering circuit configured to filter the voltage at the first switching node and generate a first ramp signal;
a second filtering circuit configured to filter the first ramp signal and generate a first average signal;
a third filtering circuit configured to filter the voltage at the second switching node and generate a second ramp signal;
a fourth filtering circuit configured to filter the second ramp signal and generate a second average signal;
a comparing circuit coupled to the first to fourth filtering circuits and configured to generate a set signal based on the
first ramp signal, the first average signal, the second ramp signal, the second average signal, a reference signal, and the
feedback signal;

a first on-time control circuit coupled to the comparing circuit, wherein based on the set signal, the first on-time control
circuit compares the on-time of the first transistor with a first time threshold and generates a first on-time control signal;

a second on-time control circuit coupled to the comparing circuit, wherein based on the set signal, the second on-time control
circuit compares the on-time of the third transistor with a second time threshold and generates a second on-time control signal;

a first logic circuit coupled to the comparing circuit and the first on-time control circuit, wherein based on the set signal
and the first on-time control signal, the first logic circuit generates a first control signal to control the first and second
transistors; and

a second logic circuit coupled to the comparing circuit and the second on-time control circuit, wherein based on the set signal
and the second on-time control signal, the second logic circuit generates a second control signal to control the third and
fourth transistors.

US Pat. No. 9,876,431

CONSTANT ON-TIME CONTROL METHOD USED IN BUCK-BOOST CONVERTERS

Chengdu Monolithic Power ...

1. A control method of a buck-boost converter, wherein the buck-boost converter converting an input voltage into an output
voltage includes a first transistor, a second transistor, a third transistor, a fourth transistor and an inductor, the control
method comprises:
sensing the output voltage and generating a feedback signal;
generating a compensation signal based on a reference signal and the feedback signal;
sensing the current flowing through the inductor and generating a current sensing signal;
comparing the current sensing signal with the compensation signal;
turning on the first and third transistors and turning off the second and fourth transistors when the current sensing signal
reduces to be lower than the compensation signal;

turning off the first transistor and turning on the second transistor when the on-time of the first transistor in one switching
period reaches a first time threshold; and

turning off the third transistor and turning on the fourth transistor when the on-time of the third transistor reaches a second
time threshold.

US Pat. No. 9,583,561

SCHOTTKY DIODES WITH MESH STYLE REGION AND ASSOCIATED METHODS

MONOLITHIC POWER SYSTEMS,...

1. A semiconductor device, comprising:
a semiconductor layer of a first doping type;
a guard ring region located in the semiconductor layer, wherein the guard ring region is of a second doping type, and wherein
the guard ring region comprises:

an outer guard ring; and
an inner mesh style region having a plurality of parallel open stripes configured to form a depletion region;
a metal Schottky contact located over the guard ring region; and
a cathode contact region having the first doping type located in the semiconductor layer and outside of the guard ring region.

US Pat. No. 10,075,075

BUCK-BOOST POWER CONVERTER AND ASSOCIATED MODE TRANSITION CONTROL MODULE

Chengdu Monolithic Power ...

1. A mode transition control module for regulating a buck-boost power converter to transit between a buck mode and a buck-boost mode and between the buck-boost mode and a boost mode, the mode transition control module comprising:a buck duty cycle sensing and comparison circuit configured to receive a first signal indicative of a buck duty cycle of the buck-boost power converter, and to compare the first signal with a first reference pulse signal having a pulse width indicative of a buck duty threshold to provide a first mode transition control signal; wherein the first mode transition control signal is configured to regulate the pulse width of the first reference pulse signal so that the buck duty threshold has a first hysteresis; and wherein when the buck duty cycle is larger than the buck duty threshold, the first mode transition control signal is configured to regulate the buck-boost power converter to transit from the buck mode to the buck-boost mode and meanwhile to decrease the pulse width of the first reference pulse signal to make the buck duty threshold to decrease to a second buck duty threshold with a decrement equals to the first hysteresis; and wherein when the buck duty cycle is smaller than the second buck duty threshold, the first mode transition control signal is configured to regulate the buck-boost power converter to transit from the buck-boost mode to the buck mode and meanwhile to to increase the pulse width of the first reference pulse signal to make the buck duty threshold to restore from the second buck duty threshold to the buck duty threshold; and
a boost duty cycle sensing and comparison circuit configured to receive a second signal indicative of a boost duty cycle of the buck-boost power converter, and to compare the second signal with a second reference pulse signal having a pulse width indicative of a boost duty threshold to provide a second mode transition control signal; wherein the second mode transition control signal is configured to regulate the pulse width of the second reference pulse signal so that the boost duty threshold has a second hysteresis; and wherein when the boost duty cycle is larger than the boost duty threshold, the second mode transition control signal is configured to regulate the buck-boost power converter to transit from the buck-boost mode to the boost mode, and meanwhile to decrease the pulse width of the second reference pulse signal to make the boost duty threshold to decrease to a second boost duty threshold with a decrement equals to the second hysteresis; and wherein when the boost duty cycle is smaller than the second boost duty threshold, the second mode transition control signal is further configured to regulate the buck-boost power converter to transit from the boost mode to the buck-boost mode, and meanwhile to increase the pulse width of the second reference pulse signal to make the boost duty threshold to restore from the second boost duty threshold to the boost duty threshold.

US Pat. No. 9,941,816

H-BRIDGE BIDIRECTIONAL CURRENT SENSING CIRCUIT

Chengdu Monolithic Power ...

1. A bidirectional current sensing circuit for sensing load current of an H-bridge circuit, wherein the H-bridge circuit comprises a first switch pair controlled by a first control signal and a second switch pair controlled by a second control signal, the H-bridge circuit is configured to drive a load by alternatively turning-ON and turning-OFF the first switch pair and the second switch pair, the bidirectional current sensing circuit comprising:a sensing resistor, having a first terminal coupled to the load, and a second terminal coupled to a reference ground;
a first amplifier, having a non-inverting terminal coupled to the first terminal of the sensing resistor through a first resistor, an inverting terminal coupled to the second terminal of the sensing resistor through a second resistor, a clock input terminal coupled to the first control signal, and an output terminal, wherein the first amplifier is configured to operate in one of an output mode and a zeroing mode based on the first control signal;
a second amplifier, having a non-inverting terminal coupled to the inverting terminal of the first amplifier, an inverting terminal coupled to the non-inverting terminal of the first amplifier, a clock input terminal coupled to the second control signal, and an output terminal, wherein the second amplifier is configured to operate in one of the output mode and the zeroing mode based on the second control signal; and
an output transistor, having a first terminal coupled to an output circuit to provide a current sensing signal indicating the load current, a second terminal electrically connected to the inverting terminal one of the first and second amplifiers operating in the output mode, and a control terminal electrically connected to the output terminal of the one of the first and second amplifiers operating in the output mode.

US Pat. No. 9,923,463

CONSTANT ON-TIME SWITCHING CONVERTER WITH REFERENCE VOLTAGE ADJUSTING CIRCUIT AND CONTROLLER THEREOF

Chengdu Monolithic Power ...

1. A constant on-time controller used in a switching converter, wherein the switching converter includes a switching circuit
having a main switch, the controller comprises:
an on-time control circuit configured to generate an on-time control signal which is used to control the on-time of the main
switch;

a comparing circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is coupled to receive a feedback signal indicative of the output voltage of the switching circuit, the second input
terminal is coupled to receive a reference voltage, wherein the comparing circuit compares the reference voltage and the feedback
signal and generates a comparison signal at the output terminal;

a logic circuit coupled to the on-time control circuit and the comparing circuit, wherein based on the on-time control signal
and the comparison signal, the logic circuit generates a control signal to control the main switch; and

a reference voltage adjusting circuit coupled to the logic circuit, wherein based on a basic reference voltage and the control
signal, the reference voltage adjusting circuit generates the reference voltage, wherein in each switching cycle of the switching
converter, the reference voltage is pulled down when the main switch is turned ON and increases with a slew rate until the
main switch is turned ON again in the next switching cycle or the reference voltage increases to a maximum value, wherein
the reference voltage adjusting circuit comprises:

a current source having a first terminal and a second terminal, wherein the first terminal is coupled to a power supply;
a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of
the current source, and the second terminal is coupled to ground;

a one-shot circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the logic circuit
to receive the control signal;

a transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the
first terminal of the capacitor, the second terminal is coupled to ground, the control terminal is coupled to the output terminal
of the one-shot circuit;

a diode having an anode and a cathode, wherein the anode is coupled to the first terminal of the capacitor, the cathode is
coupled to the basic reference voltage;

a first voltage-to-current converter having an input terminal and an output terminal, wherein the input terminal is coupled
to the first terminal of the capacitor, based on the voltage across the capacitor, the first voltage-to-current converter
generates a first current at the output terminal;

a first resistor having a first terminal and a second terminal, wherein the first terminal is coupled to the basic reference
voltage; and

a second resistor having a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal
of the first resistor and the output terminal of the first voltage-to-current converter, the second terminal is coupled to
ground.

US Pat. No. 9,917,584

VOLTAGE CONVERTER INTEGRATED CIRCUIT WITH AN INTEGRATED BOOTSTRAP CAPACITOR

Chengdu Monolithic Power ...

1. A bootstrap circuit for driving a high side switch of a voltage converter integrated circuit (IC), wherein the bootstrap
circuit is integrated into the voltage converter IC, the bootstrap circuit comprising:
a pre-charger, configured to provide a first bootstrap signal at an output terminal of the pre-charger to pre-charge a control
terminal of the high side switch;

a Low Drop Out linear regulator (LDO), coupled to an input terminal of the voltage converter IC to receive an input voltage
signal, and further configured to regulate the input voltage signal to provide a supply voltage signal at an output terminal
of the LDO;

a diode having an anode coupled to the output terminal of the LDO and the output terminal of the pre-charger, and a cathode;
and

a bootstrap capacitor having a first terminal coupled to the control terminal of the high side switch and the cathode of the
diode, and a second terminal coupled to a common connection of the high side switch and a low side switch of the voltage converter
IC, and wherein the bootstrap capacitor is configured to provide a second bootstrap signal at the first terminal of the bootstrap
capacitor to enhance the charge of the control terminal of the high side switch.

US Pat. No. 9,913,332

TWO-CHANNEL LED DRIVER AND THE CONTROL METHOD THEREOF

Chengdu Monolithic Power ...

1. A two-channel LED driver, comprising:
a power converter, configured to provide a drive current to drive a first channel LED and a second channel LED in response
to an input voltage, the power converter including a first winding and a main power switch;

a second winding, magnetically coupled to the first winding to provide a power supply voltage to power a wireless control
module;

an error amplifier, configured to generate a compensation signal in response to a reference signal and an equivalent output
current indicative of the drive current, the reference signal being controlled by a first dimming signal;

a control and drive circuit, configured to generate a control signal to control the main power switch in response to the compensation
signal;

a first dimming switch, coupled to the first channel LED to dim the first channel LED; and
a second dimming switch, coupled to the second channel LED to dim the second channel LED, the first dimming switch and the
second dimming switch being both controlled by a second dimming signal, and the second dimming switch being controlled to
be turned on and off complementary with the first dimming switch.

US Pat. No. 9,912,244

CONTROL METHOD AND CIRCUIT FOR RESONANT CONVERTERS WITH CAPACITIVE PROTECTION

Chengdu Monolithic Power ...

1. A control method used for a resonant converter, comprising:
sensing a current flowing through a resonant inductor of the resonant converter to generate a current sense signal;
determining whether the resonant converter operates in an inductive mode or in a capacitive mode based on the current sense
signal;

once the resonant converter enters into the capacitive mode, making the resonant converter to operate in a first control mode
to turn a high-side switch and a low-side switch of the resonant converter off for N switching cycles, wherein N is a positive
integer;

after the high-side switch and the low-side switch are turned off for N switching cycles, determining whether the current
sense signal is increased to a zero-crossing threshold during an ascent stage of the current sense signal, and determining
whether the current sense signal is decreased to the zero-crossing threshold during a descent stage of the current sense signal;

turning the high-side switch on once the current sense signal is increased to the zero-crossing threshold during the ascent
stage of the current sense signal; and

turning the low-side switch on once the current sense signal is decreased to the zero-crossing threshold during the descent
stage of the current sense signal.

US Pat. No. 9,882,405

BIDIRECTIONAL SWITCH CIRCUIT FOR POWER BANKS AND THE METHOD THEREOF

Chengdu Monolithic Power ...

1. A bidirectional switch circuit, comprising:
an inductor having a first terminal and a second terminal, wherein the first terminal is configured to receive a charge voltage,
and the second terminal is coupled to a switch node;

a low side power switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled
to the switch node, the second terminal is coupled to a ground reference, and the control terminal is configured to receive
a low side control signal;

a high side power switch set having a first terminal, a second terminal, a third terminal, a fourth terminal and a control
terminal, wherein the first terminal and the fourth terminal are coupled together to the switch node, the second terminal
is configured to receive a discharge voltage, the third terminal is configured to receive a larger one of the charge voltage
and the discharge voltage, and the control terminal is configured to receive a high side control signal; and

a control circuit configured to provide the high side control signal and the low side control signal respectively to the high
side power switch set and the low side power switch.

US Pat. No. 10,090,200

BIPOLAR JUNCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF

Chengdu Monolithic Power ...

1. A bipolar junction semiconductor device, comprising:a semiconductor substrate with a first conductive type;
a first buried layer formed in the semiconductor substrate, the first buried layer has a second conductive type opposite to the first conductive type;
a first epitaxial layer formed on the first buried layer, the first epitaxial layer has the first conductive type;
a second epitaxial layer formed on the first epitaxial layer, the second epitaxial layer has the first conductive type;
a PNP bipolar junction transistor (BJT) unit formed in the first and second epitaxial layers at a first active area;
a NPN BJT unit formed in the first and second epitaxial layers at a second active area; and
a first isolation structure having the second conductive type and formed in the first and second epitaxial layers at an isolation area, wherein the isolation area is located between the first active area and the second active area, the first isolation structure connected with the first buried layer forms an isolation barrier with the second conductive type.

US Pat. No. 10,050,615

OVER-VOLTAGE PROTECTION CIRCUIT AND ASSOCIATED METHOD

Chengdu Monolithic Power ...

1. An over-voltage protection circuit for a transistor switch, wherein the transistor switch has a control terminal, an input terminal receiving an input voltage and an output terminal providing an output voltage, the protection circuit comprises:an error detecting circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the transistor switch, and wherein the second input terminal is configured to receive a reference signal, and wherein based on the reference signal and the output voltage, the error detecting circuit provides an amplified error signal at the output terminal;
a dummy load circuit having a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to the output terminal of the error detecting circuit, and wherein the first terminal is coupled to the output terminal of the transistor switch, and wherein the second terminal is connected to ground, and wherein the dummy load circuit is configured to establish a conductive path between the output terminal of the transistor switch and ground if a voltage difference between the second terminal of the error detecting circuit and the first terminal of the error detecting circuit is smaller than a second value; and
a driving circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the error detecting circuit, and wherein the output terminal is coupled to the control terminal of the transistor switch, and wherein the driving circuit is configured to increase the on-resistance of the transistor switch if the voltage difference between the second terminal of the error detecting circuit and the first terminal of the error detecting circuit is smaller than a first value, and wherein the second value is larger than the first value.

US Pat. No. 10,020,734

AUTO CALIBRATION METHOD USED IN CONSTANT ON-TIME SWITCHING CONVERTER

Chengdu Monolithic Power ...

1. An auto calibration method used in switching converters with constant on-time control, wherein the switching converter is configured to convert an input voltage into an output voltage, and is configured to include a main transistor, an on-time control circuit determining the on-time of the main transistor, and a logic circuit driving the main transistor, the auto calibration method comprises:generating a periodical clock signal with a predetermined duty cycle;
providing a first voltage and a second voltage to the on-time control circuit to generate an on-time control signal based on the first and second voltage;
providing the clock signal and on-time control signal to the logic circuit to generate a switch control signal based on the clock signal and on-time control signal;
comparing the duty cycle of the switch control signal with the duty cycle of the clock signal to adjust a calibration code signal; and
adjusting circuit parameters of the on-time control circuit in accordance with the calibration code signal.

US Pat. No. 9,979,288

SWITCHING MODE POWER SUPPLY WITH ADAPTIVE FREQUENCY

Chengdu Monolithic Power ...

1. A controller for controlling a switching mode power supply (SMPS), wherein the SMPS comprises a switch with a minimum on time, and the SMPS converts an input voltage to an output voltage, the controller comprising:a clock circuit, configured to generate a clock signal to control the turn on moment of the switch, wherein when the required on time of the switch for converting the input voltage to a target output voltage is bigger than the minimum on time, the frequency of the clock signal is controlled to be a preset frequency, when the required on time of the switch is smaller than the minimum on time, the frequency of the clock signal is controlled to be positively correlated to the required on time of the switch;
an off signal generator, configured to generate an off signal to control the actual on time of the switch, wherein when the required on time of the switch is bigger than the minimum on time, the actual on time of the switch is controlled to be the required on time of the switch, when the required on time of the switch is smaller than the minimum on time, the actual on time of the switch is controlled to be the minimum on time; and
a logic circuit, coupled to the clock circuit and the off signal generator, wherein the logic circuit is configured to control the switching operation of the switch based on the clock signal and the off signal.

US Pat. No. 9,978,846

METHOD FOR FORMING STEPPED OXIDE ON A SUBSTRATE

Chengdu Monolithic Power ...

1. A method for forming a stepped oxide on a substrate, wherein the stepped oxide has a thicker portion with a first thickness and a thinner portion with a second thickness, comprising:forming a first pad oxide layer on the substrate;
forming a nitride layer on the first pad oxide layer;
forming a second pad oxide layer on the nitride layer;
forming a poly layer on the second pad oxide layer;
etching the poly layer to have an opening for forming a stepped oxide region;
isotropically etching to the second pad oxide layer to the nitride layer through the opening and to form a stepped trench;
isotropically etching the nitride layer to the first pad oxide layer through the opening to expand the stepped trench;
filling the stepped trench with a dielectric material to form a dielectric layer;
removing dielectric material deposited on the surface of the ploy layer;
removing the remaining poly layer;
removing the remaining second pad oxide layer;
removing the remaining nitride layer; and
removing the portion of the first pad oxide layer uncovered by the dielectric layer such that the remaining dielectric layer together with the remaining first pad oxide layer forms the stepped oxide.

US Pat. No. 9,941,781

MULTI-RAIL SWITCHING CONVERTER, CONTROL CIRCUIT AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A multi-rail switching converter, having an input port and a plurality of output ports configured to provide a plurality of output voltages, the multi-rail switching converter comprising:a plurality of switching circuits, each of the plurality of switching circuits having an input terminal coupled to the input port, and an output terminal coupled to one of the plurality of output ports, wherein one of the plurality of switching circuits is configured as a master switching circuit, and the rest of the plurality of switching circuits are configured as slave switching circuits;
a plurality of comparison circuits, configured to provide a plurality of set signals based on the plurality of output voltages and a plurality of reference signals;
a plurality of switching control circuits, configured to provide a plurality of switching control signals based on the plurality of set signals and a plurality of ON-time period control signals to control the plurality of switching circuits; and
an interleaving control circuit, configured to judge a phase zone of a corresponding slave switching circuit based on a switching control signal of the master switching circuit and a set signal of the corresponding slave switching circuit, and configured to adjust a turn-ON moment of the corresponding slave switching circuit based on the phase zone of the corresponding slave switching circuit; wherein
when the corresponding slave switching circuit is judged as in a leading phase zone, the turn-ON moment of the corresponding slave switching circuit is postponed by postponing the set signal of the corresponding slave switching circuit a set-delay time period; and wherein
when the corresponding slave switching circuit is judged as in a lagging phase zone, the turn-ON moment of the corresponding slave switching circuit is brought forward by calibrating a reference signal of the corresponding slave switching circuit.

US Pat. No. 9,912,145

BOOST CONVERTER WITH SHORT-CIRCUIT PROTECTION AND METHOD THEREOF

Chengdu Monolithic Power ...

1. A short-circuit protection method for a boost converter comprising a short-circuit protection switch and a switching circuit,
wherein the short-circuit protection switch is coupled between an input voltage and the switching circuit, and wherein the
switching circuit has a switch and is configured to provide an output voltage at an output terminal based on the input voltage,
the short-circuit protection method comprises:
turning on the switch and supplying a control voltage to gradually turn on the short-circuit protection switch when the boost
converter starts up;

detecting whether a current flowing through the switch is higher than a predetermined value;
turning off the switch and starting timing when the current flowing through the switch is higher than the predetermined value;
detecting whether the output terminal of the boost converter is shorted to a reference ground after a preset time period;
and

turning off the short-circuit protection switch when the output terminal of the boost converter is shorted to the reference
ground.

US Pat. No. 10,090,409

METHOD FOR FABRICATING LDMOS WITH SELF-ALIGNED BODY

Monolithic Power Systems,...

1. A method for fabricating an LDMOS device, comprising:forming a semiconductor substrate;
forming a dielectric layer atop the semiconductor substrate;
forming an electric conducting layer on the dielectric layer;
forming a first photoresist layer on the electric conducting layer;
patterning the first photoresist layer through a first mask to form a first opening;
etching the electric conducting layer through the first opening;
implanting dopants of a first doping type into the semiconductor substrate through the first opening, to form a first body region adjacent to the surface of the semiconductor substrate, and a second body region located beneath the first body region, wherein the semiconductor substrate laterally outside of the first opening is all covered by both the electric conducting layer and the first photoresist layer to block the implant of the dopants;
removing the first photoresist layer after the steps of etching and implanting through the first opening; and
etching the electric conducting layer using a second photoresist layer and a second mask after the first photoresist layer is removed.

US Pat. No. 9,998,022

CURRENT LIMIT PEAK REGULATION CIRCUIT FOR POWER CONVERTER WITH LOW STANDBY POWER DISSIPATION

Chengdu Monolithic Power ...

1. A current limit peak regulation circuit for regulating a current flowing through a main switch of a power converter, comprising:a first input terminal configured to receive a frequency indication signal indicative of a switching frequency of the power converter;
a second input terminal configured to receive a first reference signal indicative of a first predetermined frequency;
a third input terminal configured to receive a second reference signal indicative of a second predetermined frequency; and
an output terminal configured to provide a current limit threshold indicative of a maximum allowable peak current value of the current flowing through the main switch; wherein
the current limit peak regulation circuit is configured to generate the current limit threshold based on the frequency indication signal, the first reference signal and the second reference signal; and wherein
the current limit peak regulation circuit is further configured to adjust the current limit threshold to decrease with decrease in the switching frequency in a constant voltage mode of the power converter.

US Pat. No. 9,936,548

SMART LED DRIVER AND LED DRIVE METHOD

Chengdu Monolithic Power ...

1. A LED driver, comprising:a power converter, configured to provide a drive current to drive a load in response to an input voltage, the power converter including a first winding and a main power switch;
a second winding, magnetically coupled to the first winding to provide a first power supply voltage, the first power supply voltage being operable to power a wireless control module when a dimming signal is higher than a threshold signal;
a third winding, magnetically coupled to the first winding to provide a second power supply voltage, the second power supply voltage being operable to power the wireless control module when the dimming signal is lower than the threshold signal;
a first error amplifier, configured to generate a first compensation signal in response to a first reference signal and an equivalent output current indicative of the drive current, the first reference signal being controlled by the dimming signal;
a second error amplifier, configured to generate a second compensation signal in response to a second reference signal and the second power supply voltage; and
a control and drive circuit, configured to generate a control signal to control the main power switch in response to a compensation signal, the compensation signal being the first compensation signal when the dimming signal is higher than the threshold signal, and the compensation signal being the second compensation signal when the dimming signal is lower than the threshold signal.

US Pat. No. 9,787,196

FREQUENCY JITTERING CONTROL CIRCUIT AND THE METHOD THEREOF

Monolithic Power Systems,...

1. A frequency jittering control circuit used with a switching mode power supply having a power switch, comprising:
a peak current signal generating circuit, having an input terminal configured to receive an on trigger signal having a pulse
indicative of a beginning of an on time of the power switch, and an output terminal configured to provide a peak current signal
based on the on trigger signal;

a peak comparator, having a first input terminal coupled to the output terminal of the peak current signal generating circuit
to receive the peak current signal, a second input terminal configured to receive a current sense signal indicative of a current
flowing through the power switch, and an output terminal configured to provide a current control signal based on the peak
current signal and the current sense signal; and

a logic circuit, having a first input terminal configured to receive the on trigger signal, a second input terminal coupled
to the output terminal of the peak comparator to receive the current control signal, and an output terminal configured to
provide a power control signal based on the on trigger signal and the current control signal, wherein the power control signal
controls on and off of the power switch; wherein

the peak current signal is updated at the beginning of the on time of the power switch, and a value of the peak current signal
is determined by a length of a switching period before the beginning of the on time of the power switch.

US Pat. No. 9,945,691

MAGNETIC ANGULAR SENSING SYSTEM WITH SIDE-SHAFT MOUNTED SENSOR AND THE METHOD THEREOF

Monolithic Power Systems,...

1. A magnetic angular sensing system, comprising:a magnet magnetized radially on a plane of the magnet, the magnet having a magnetizing direction from a north pole to a south pole of the magnet, and wherein the north pole and the south pole are located respectively at two opposite ends of the plane, wherein the magnet is rotatable around an axis perpendicular to the plane; and
a magnetic angular sensor having a sensing plane in parallel to the axis and perpendicular to a radius between the axis and the magnetic angular sensor that is not coplanar with the plane of the magnet, and wherein the magnetic angular sensor is configured to sense an axial magnetic field component of a magnetic field vector generated by the magnet at a first detection direction of the sensing plane in parallel to the axis and to sense a tangential magnetic field component of the magnetic field vector at a second detection direction of the sensing plane orthogonal to the radius and the axis, the magnetic angular sensor is configured to provide an angle signal indicative of the angular position of the magnet, and wherein the angle signal is generated according to the axial magnetic field component and the tangential magnetic field component; wherein the magnetic angular sensor comprises:
a first hall effect device configured to sense the axial magnetic field component at the first detection direction, the first hall effect device comprising a first pair and a second pair of connectors;
a second hall effect device configured to sense the tangential magnetic field component at the second detection direction orthogonal to the radius and the axis, the second hall effect device comprising a first pair and a second pair of connectors;
a current source having an output configured to provide an electrical current;
a filtering unit having an input and an output, wherein the filtering unit has a fundamental frequency f corresponding to a period Tf=1/f;
a wiring unit having a plurality of nodes coupled to the output of the current source, the pairs of connectors of the first and second hall effect devices and the input of the filtering unit, the wiring unit configured to selectively couple one pair of connectors of each of the first hall effect device and the second hall effect device to the output of the current source configured to allow a current flowing through each of the first and second hall effect devices, and couple the other pair of connectors of each of the first and second hall effect devices to the input of the filtering unit configured to provide a first hall voltage signal;
a control unit configured to control the wiring unit; and
an output unit coupled to the output of the filtering unit and configured to provide the angle signal indicative of the angular position of the magnet.

US Pat. No. 9,660,516

SWITCHING CONTROLLER WITH REDUCED INDUCTOR PEAK-TO-PEAK RIPPLE CURRENT VARIATION

Monolithic Power Systems,...

1. A controller for controlling a switching circuit, wherein the switching circuit comprises a rectifier, and the switching
circuit is configured to provide an output voltage based on an input voltage, the controller comprises:
an over voltage protection circuit comprising:
an over voltage detection circuit configured to compare a feedback signal representative of the output voltage with an over
voltage threshold and to generate an over voltage detection signal based on a comparison result of comparing the feedback
signal with the over voltage threshold;

an over current detection circuit configured to compare a current sense signal representative of a current flowing through
the rectifier with an over current threshold and to generate an over current detection signal based on a comparison result
of comparing the current sense signal with the over current threshold; and

a timing circuit configured to generate a timing signal based on the over voltage detection signal and the over current detection
signal, wherein the timing signal is configured to control an off time of the rectifier so that the off time varies inversely
with the input voltage; and

a control circuit electrically coupled to the over voltage protection circuit and the switching circuit, wherein based on
the over current detection signal, the timing signal and the feedback signal, the control circuit generates a control signal
to control the rectifier.

US Pat. No. 10,254,314

CURRENT SENSING CIRCUIT AND INTEGRATED CIRCUIT FOR FOUR-SWITCH BUCK-BOOST CONVERTOR

Chengdu Monolithic Power ...

1. A current sensing circuit used for a buck-boost converter, wherein the buck-boost converter comprises a first high side switch and a first low side switch which are couple in series between an input voltage and a ground and a second high side switch and a second low side switch which are coupled in series between an output voltage and the ground, the current sensing circuit comprising:a first normally-ON transistor having a first terminal and a second terminal, wherein during a turn ON time of the first low side switch, the first terminal is coupled to the ground, and during a turn ON time of the second low side switch, the first terminal is coupled to a second switch node that is connected to a terminal of the second high side switch and a terminal of the second low side switch;
a second normally-ON transistor having a first terminal and a second terminal, wherein during the turn ON time of the first low side switch, the first terminal is coupled to a first switch node that is connected to a terminal of the first high side switch and a terminal of the first low side switch, and during the turn ON time of the second low side switch, the first terminal is coupled to the ground;
a first sensing circuit having a first input terminal coupled to the second terminal of the first normally-ON transistor, a second input terminal coupled to the second terminal of the second normally-ON transistor and an output terminal configured to provide a detection current; and
a second sensing circuit detecting an average value of the detection current and providing a current sensing signal in accordance with the average value of the detection current, wherein during the turn ON time of the first low side switch, the detection current represents a current flowing though the first low side switch, the current sensing signal represents an output current of the buck-boost converter, and during the turn ON time of the second low side switch, the detection current represents a current flowing though the second low side switch, the current sensing signal represents an input current of the buck-boost converter.

US Pat. No. 10,069,422

SYNCHRONOUS SWITCHING CONVERTER AND ASSOCIATED INTEGRATED SEMICONDUCTOR DEVICE

Chengdu Monolithic Power ...

1. An integrated semiconductor device utilized in synchronous switching converters, comprising:a first semiconductor component, comprising a first Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with a body diode, wherein the first MOSFET has a source, a drain and a gate; and
a second semiconductor component, coupled in parallel with the first semiconductor component, wherein the second semiconductor component comprises a diode with an anode and a cathode, wherein the anode of the diode is coupled to the source of the first MOSFET, the cathode of the diode is coupled to the drain of the first MOSFET, wherein a forward voltage of the diode is lower than a forward voltage of the body diode in the first MOSFET; wherein
cells of the second semiconductor component are configured to distribute among the first semiconductor component unevenly according to a distribution of a current flowing through the integrated semiconductor device.

US Pat. No. 9,998,009

SWITCH MODE POWER SUPPLY SUPPORTING BOTH A BI-DIRECTIONAL CONVERTER OF A FIRST CONFIGURATION AND THAT OF A SECOND CONFIGURATION

Monolithic Power Systems,...

1. A controller of a switch mode power supply (SMPS) having an input terminal to receive a power source and a bus terminal to provide a bus voltage to a downstream device, wherein the SMPS comprises a bi-directional converter comprising a storage capacitor and an inductor, the bi-directional converter is capable of being configured in at least a first configuration or a second configuration, and when the power source is provided, the SMPS operates in a charge state to store energy in the storage capacitor, and when a predetermined condition is satisfied, the SMPS operates in a release state to release energy from the storage capacitor to the downstream device, the controller comprising:a mode control module configured to receive a mode setting signal indicative of the configuration of the bi-directional converter and a state indication signal indicative of the state of the SMPS, wherein the mode control module is configured to generate a mode control signal in response to the mode setting signal and the state indication signal; and
a buck control module and a boost control module both coupled to the mode control module, wherein in response to the mode control signal 1) the buck control module is selected to control the bi-directional converter in the charge state and the boost control module is selected to control the bi-directional converter in the release state, or 2) the boost control module is selected to control the bi-direction converter in the charge state and the buck control module is selected to control the bi-directional converter in the release state.

US Pat. No. 9,893,146

LATERAL DMOS AND THE METHOD FOR FORMING THEREOF

Monolithic Power Systems,...

1. A semiconductor device, comprising:
a gate region formed on a top surface of the semiconductor device;
an N-type drain region comprising a drift region and a highly doped drain contact region formed in the drain region, the drain
contact region being at a first side of the gate region, the drift region including an upper sub-drift region, a middle sub-drift
region and a lower sub-drift region, the upper sub-drift region, the middle sub-drift region and the lower sub-drift region
being with different doping concentration with each other, and arranged vertically from the top surface of the semiconductor
device to a substrate of the semiconductor device, respectively, wherein the middle sub-drift region has the highest doping
concentration, and the doping concentration decreases both from the middle sub-drift region to the upper sub-drift region,
and from the middle sub-drift region to the lower sub-drift region; and

a P-type deep body region having an N-type highly doped source region and a P-type highly doped body contact region formed
therein, the body contact region and the majority portion of the source region being at a second side of the gate region.

US Pat. No. 9,893,170

MANUFACTURING METHOD OF SELECTIVELY ETCHED DMOS BODY PICKUP

Monolithic Power Systems,...

12. A manufacturing process of a LDMOS device, comprising:
forming a well region in a semiconductor substrate;
forming a gate oxidation layer above the well region;
depositing a polysilicon layer above the gate oxidation layer;
sequentially forming a gate seal layer, a silicon nitride layer and a first masking layer above the polysilicon layer, wherein
the first masking layer comprises at least one window to the surface of the silicon nitride layer;

etching the silicon nitride layer, the gate seal layer and the polysilicon layer under the window of the first masking layer
to expose a window for a body region in the well region;

implanting P type dopants into the well region through the window for the body region to form the body region in the well
region;

implanting N type dopants into the body region through the window for the body region to form a source layer, and removing
the first masking layer afterwards;

oxidizing side walls of the polysilicon layer;
forming spacers at the oxidized side walls of the polysilicon layer;
etching through the source layer through a window shaped by the spacers to form a source regions under the spacer;
implanting P type dopants into a etched region between the source regions to form a body pickup region;
etching away the silicon nitride layer and the spacers;
forming a second masking layer above the gate seal layer, wherein the second masking layer has windows at predetermined positions;
etching the gate seal layer and the polysilicon layer through the windows of the second masking layer to form a gate, and
removing the second masking layer afterwards;

forming a third masking layer above the gate seal layer and the gate oxidation layer, wherein the third masking layer comprise
at least one window for a drain pickup region; and

implanting N type dopants into the well region under the at least one window of the third masking layer to form the drain
pickup region, and removing the third masking layer afterwards.

US Pat. No. 9,837,999

ELECTRONIC DEVICE WITH SUBSTRATE CURRENT MANAGEMENT

Monolithic Power Systems,...

1. An electronic device, comprising:
a semiconductor substrate;
a Schottky diode, formed in the semiconductor substrate;
a parasitic PN diode, formed in the semiconductor substrate, wherein the parasitic PN diode and the Schottky diode are in
parallel;

an amplifying circuit, coupled between an anode and a cathode of the Schottky diode, configured to amplify a difference value
of the forward voltage of the Schottky diode and a reference signal, and further configured to provide an error signal, wherein
a value of the reference signal is larger than the forward conduction threshold voltage of the Schottky diode, and smaller
than the forward conduction threshold voltage of the parasitic PN diode; and

a transistor, configured to regulate the current flowing through the Schottky diode based on the error signal.

US Pat. No. 10,116,155

BATTERY CHARGING CIRCUIT WITH HIGH CAPACITY, CONTROL CIRCUIT AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A battery charging circuit, having an input terminal configured to receive an input voltage and an output terminal configured to provide a system voltage, the battery charging circuit comprising:a first switching circuit, having a first terminal and a second terminal, wherein the first switching circuit comprises a first switch, the first terminal of the first switching circuit is coupled to the input terminal of the battery charging circuit, the second terminal of the first switching circuit is coupled to the output terminal of the battery charging circuit;
a second switching circuit, comprising a second switch, wherein the second switching circuit and the first switching circuit are coupled in parallel between the input terminal and the output terminal of the battery charging circuit;
a plurality of feedback control loops, configured to provide a plurality of feedback control signals, wherein each feedback control loop receives a feedback signal, a ramp signal and a reference signal, wherein the plurality of feedback control signals are configured to turn off one of the first switching circuit and the second switching circuit;
a logic integrated circuit, coupled to the plurality of feedback control loops to receive the plurality of feedback control signals, and configured to provide a logic integrated signal based on the plurality of feedback control signals;
a frequency dividing circuit, coupled to the logic integrated circuit to receive the logic integrated signal, and configured to divide the logic integrated signal's pulse into two sequences orderly, wherein one sequence is configured to form a first frequency dividing signal, and the other sequence is configured to form a second frequency dividing signal;
a first duration control circuit, configured to receive a first duration control signal and configured to provide a first duration signal, wherein the first duration signal is adjustable in real-time;
a second duration control circuit, configured to receive a second duration control signal and configured to provide a second duration signal, wherein the second duration signal is adjustable in real-time;
a first logic circuit, configured to receive the first frequency dividing signal and the first duration signal, and configured to provide a first switching control signal to control the first switch of the first switching circuit, wherein the first logic circuit is configured to control an off moment of the first switch according to the first frequency dividing signal, and configured to control an off duration of the first switch according to the first duration signal; and
a second logic circuit, configured to receive the second frequency dividing signal and the second duration signal, and configured to provide a second switching control signal to control the second switch of the second switching circuit, wherein the second logic circuit is configured to control an off moment of the second switch according to the second frequency dividing signal, and configured to control an off duration of the second switch according to the second duration signal.

US Pat. No. 10,110,037

BATTERY CHARGING CIRCUIT, CONTROL CIRCUIT AND ASSOCIATED CONTROL METHOD

Chengdu Monolithic Power ...

1. A control circuit for a battery charging circuit, the battery charging circuit comprising a switching circuit having an inductor, the switching circuit has an input terminal configured to receive an input current and an output terminal configured to provide a system voltage, the output terminal of the switching circuit is further coupled to a battery to provide a charging current, the control circuit comprising:a charging current control loop, configured to receive a charging current feedback signal representative of the charging current, and configured to provide a compensation signal based on a differential between the charging current feedback signal and a charging current reference signal;
an amplitude limiting circuit, coupled to the charging current control loop to receive the compensation signal, and configured to provide an inductor current reference signal based on the compensation signal and a designed maximum input current level, wherein amplitude of the inductor current reference signal is limited based on the designed maximum input current level;
an inductor current control loop, configured to receive the inductor current reference signal and an inductor current feedback signal representative of an inductor current flowing through the inductor, and configured to provide a first loop control signal via comparing the inductor current feedback signal with the inductor current reference signal;
a system voltage control loop, configured to receive a system voltage feedback signal representative of the system voltage, and configured to provide a second loop control signal via comparing the system voltage feedback signal with a system voltage reference signal; and
a switching control circuit, configured to receive the first loop control signal and the second loop control signal, and configured to provide a control signal to control the switching circuit based on the first loop control signal and the second loop control signal.

US Pat. No. 10,003,255

VID-CONTROLLED VOLTAGE REGULATOR WITH AUDIBLE NOISE CORRECTION

Monolithic Power Systems,...

1. A method for correcting audible noise from a voltage regulator for supplying a voltage to a master device responsive to a VID indicated by a series of VID commands from the master device, the method comprising:receiving a VID command of the series of VID commands for changing the VID from a present value to a target value;
holding the VID at the present value if a VID difference between the present value and the target value is larger than a VID threshold, wherein the VID threshold is a non-negative number;
executing the VID command of the series of VID commands if a holding duration for holding the VID at the present value expires and no new VID command for changing the VID is received before the holding duration expires.

US Pat. No. 9,882,482

CURRENT SENSE CIRCUIT WITH ADAPTIVE COMMON MODE VOLTAGE ADJUST AND ASSOCIATED METHOD THEREOF

Monolithic Power Systems,...

1. A current sense circuit for sensing a target current flowing through a sensing resistor, wherein the sensing resistor having
a positive terminal and a negative terminal, the current sense circuit comprising:
a first operational amplifier, having a first input terminal, a second input terminal and an output terminal, wherein the
first input terminal is coupled to the positive terminal of the sensing resistor, and the second input terminal is coupled
to the negative terminal of the sensing resistor, and wherein the first input terminal and the second input terminal of the
first operational amplifier has a common mode voltage with respect to a reference ground;

a first transistor, having a first terminal, a second terminal and a control terminal, wherein the control terminal is coupled
to the output terminal of the first operational amplifier, the first terminal is coupled to the first input terminal of the
first operational amplifier, and the second terminal is coupled to the reference ground through a first resistor, wherein
the first transistor is configured to provide a first output voltage across the first resistor in response to the target current;
and

a common mode adjust circuit, having an input terminal, a first output terminal and a second output terminal, wherein the
input terminal is coupled to the output terminal of the first operational amplifier and the control terminal of the first
transistor, the first output terminal is coupled to the first input terminal of the first operational amplifier, and the second
output terminal is coupled to the second input terminal of the first operational amplifier, wherein the common mode adjust
circuit is configured to adaptively adjust the common mode voltage.

US Pat. No. 9,817,039

METHODS FOR SENSING CURRENT IN A SWITCHING REGULATOR

MONOLITHIC POWER SYSTEMS,...

1. A current sensing circuit, comprising:
a differential current sensing amplifier adapted for sensing a voltage drop across a main transistor, the differential current
sensing amplifier being adapted for providing a switched current output to a timing circuit;

the timing circuit, wherein the timing circuit is adapted for providing a timing signal to one or more switching current sample-and-hold
circuits based on a current waveform of the switched current output; and

the one or more switching current sample-and-hold circuits, each of the one or more switching current sample-and-hold circuits
being adapted for producing a continuous output current, wherein each of the switching current sample-and hold circuits comprises:

a first sample-and-hold loop, the first sample-and-hold loop being adapted for latching onto an average value of a sensing
inductor current provided by at least one sensing transistor; and

a second sample-and-hold loop, the second sample-and-hold loop being adapted for detecting the average value of the sensing
inductor current provided by the at least one sensing transistor.

US Pat. No. 9,779,827

VOLTAGE CONTROL CIRCUIT FOR MEMORY CELL AND THE METHOD THEREOF

Monolithic Power Systems,...

1. A voltage control circuit for a memory cell having a floating gate transistor and a capacitive device, comprising:
a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the first input
terminal is configured to receive a power supply voltage, the second input terminal is configured to receive a ground reference,
and wherein based on the power supply voltage and the ground reference, the first output terminal and the second output terminal
respectively provides a first voltage signal and a second voltage signal, and wherein a voltage value of the first voltage
signal is twice the power supply voltage, and a maximum of a voltage difference between the first voltage signal and the second
voltage signal is three times the power supply voltage;

a first voltage converting circuit configured to provide the first voltage signal; and
a second voltage converting circuit configured to provide the second voltage signal, wherein the second voltage converting
circuit comprises:

an output terminal configured to provide the second voltage signal;
a slope signal generator having a first input terminal, a second input terminal, a third input terminal and an output terminal,
wherein the first input terminal is configured to receive the power supply voltage, the second input terminal is configured
to receive the ground reference, the third input terminal is configured to receive an operation indicative signal, and wherein
based on the power supply voltage, the ground reference and the operation indicative signal, the output terminal provides
a slope signal, and wherein from a beginning of each write operation or from a beginning of each erase operation to the memory
cell, the slope signal rises from a voltage value of the ground reference to a voltage value of the power supply voltage,
and maintains the voltage value of the power supply voltage afterwards; and

a negative charge pump having a first input terminal, a second input terminal and an output terminal, wherein the first input
terminal is coupled to the slope signal generator to receive the slope signal, the second input terminal is configured to
receive the ground reference, and the output terminal is configured to provide a mirrored slope signal based on the slope
signal and the ground reference; wherein

when the operation indicative signal indicates the write operation to the memory cell, the slope signal is selected to be
the second voltage signal and is provided to the floating gate transistor; and

when the operation indicative signal indicates the erase operation to the memory cell, the mirrored slope signal is selected
to be the second voltage signal and is provided to the floating gate transistor.

US Pat. No. 9,621,383

DIGITAL ISOLATOR AND THE METHOD THEREOF

MONOLITHIC POWER SYSTEMS,...

16. A control method for controlling a digital isolator system, comprising:
determining if an input signal is in a first logic state, if yes, generating a first pair of buffered differential signals
based on the input signal, otherwise, disabling a transmitter side and setting the first pair of buffered differential signals
in a default idle state;

transmitting the first pair of buffered differential signals to a second pair of differential signals via an isolation barrier;
restoring the second pair of differential signals to a third pair of differential signals with valid logic level, wherein
the pattern of consecutive and alternating occurrences of the third pair of differential signals are detected for issuing
a reset signal;

determining if the output signal is in a second logic state, if yes, starting a timeout period to finally set the output signal
in a first logic state, otherwise, starting a timeout period to finally set the output signal in the second logic state;

detecting if active timing is finished, if yes, setting a receiver side into a sleep mode, otherwise, restoring the signals
to a third pair of differential signals with valid logic level, wherein the pattern of consecutive and alternating occurrences
of the third pair of differential signals are detected for issuing a reset signal; and

determining if the output signal is in a first logic state after the timeout period, if yes, starting a timeout period to
finally set the output signal in a second logic state, otherwise, setting a receiver side into the sleep mode.

US Pat. No. 9,590,503

SWITCHING CONVERTER AND ASSOCIATED DISCHARGE METHOD

MONOLITHIC POWER SYSTEMS,...

1. A switching converter, comprising: an input port, configured to receive an input voltage; an output port, configured to
provide an output voltage; a power stage, having an input terminal, an output terminal and a control terminal, wherein the
input terminal is coupled to the input port, and the output terminal is coupled to the output port; an energy stored circuit,
having an input terminal coupled to the input port to receive the input voltage and an output terminal configured to provide
a first bias voltage, wherein the first bias voltage maintains a predetermined time period after the input voltage becomes
less than a threshold signal; a power conversion circuit, having an input terminal and an output terminal, wherein the input
terminal is coupled to the input port to receive the input voltage, and the output terminal is configured to provide a second
bias voltage; and a control circuit, having a first input terminal, a second input terminal, a third input terminal, a fourth
input terminal and an output terminal, wherein the first input terminal is coupled to the output port, the second input terminal
is configured to receive a discharge control signal, the third input terminal is coupled to the output terminal of the energy
stored circuit to receive the first bias voltage, and the fourth input terminal is coupled to the output terminal of the power
conversion circuit to receive the second bias voltage, and the output terminal is coupled to the control terminal of the power
stage to provide a control signal based on the output voltage and a reference signal, wherein the control circuit is powered
by either the first bias voltage or the second bias voltage; and wherein the control circuit is configured to discharge the
output voltage based on the discharge control signal, when the input voltage is less than the threshold signal, the output
voltage is fully discharged to ground by the control circuit, wherein the control circuit further comprising: a discharge
switch, having a control terminal, wherein the discharge switch is configured to discharge the output voltage based on the
discharge control signal.

US Pat. No. 10,186,975

RESONANT CONVERTER WITH ADAPTIVE ON-TIME CONTROL AND THE METHOD THEREOF

Chengdu Monolithic Power ...

1. A resonant converter, comprising:an input power stage including a first power switch and a second power switch, configured to receive an input voltage;
an output power stage, coupled to the input power stage by way of a resonant net and a transformer, the output power stage configured to generate an output voltage; and
a control circuit, configured to control the input power stage and the output power stage, the control circuit comprising:
a comparison circuit, configured to generate a comparison signal in response to a voltage feedback signal indicative of the output voltage and a voltage reference signal, the comparison signal having a rising edge and a falling edge;
a logical circuit, configured to generate a pulse width signal in response to the comparison signal and an on-time signal, the pulse width signal having a rising edge and a falling edge; and
an on-time controller, configured to generate the on-time signal in response to the comparison signal and the pulse width signal, the on-time signal operable to decrease when the whole of the rising edge of the comparison signal is later than the whole of the falling edge of the pulse width signal, and to increase when the whole of the rising edge of the comparison signal is earlier than the whole of the falling edge of the pulse width signal.

US Pat. No. 9,998,005

SINGLE INDUCTOR DUAL OUTPUT VOLTAGE CONVERTER AND THE METHOD THEREOF

Monolithic Power Systems,...

1. A voltage converter having an inductor, an input port receiving an input voltage, a first output port providing a first output voltage, and a second output port providing a second output voltage, comprising:a first switch, coupled between the input port and a first terminal of the inductor;
a second switch, coupled between the first terminal of the inductor and a second output port;
a third switch, coupled between the second terminal of the inductor and the first output port; and
a fourth switch, coupled between the second terminal of the inductor and a ground reference; wherein
the first switch, the second switch, the third switch and the fourth switch are switched periodically during operation, and each switching period comprises a first time period, a second time period and a third time period in a consecutive order, and wherein:
during the first time period, the first switch and the fourth switch are turned on, whereas the second switch and the third switch are turned off;
during the second time period, the first switch and the third switch are turned on, whereas the second switch and the fourth switch are turned off; and
during the third time period, the second switch and the fourth switch are turned on, whereas the first switch and the third switch are turned off.

US Pat. No. 9,966,851

BUCK-BOOST CONVERTER, THE CONTROL CIRCUIT AND THE METHOD THEREOF

Monolithic Power Systems,...

3. A control circuit for a buck-boost converter, wherein the buck-boost converter comprises an input port receiving an input voltage, an output port providing an output voltage, a first power switch, a second power switch, a third power switch and a fourth power switch, the control circuit comprising:a mode select circuit configured to receive the input voltage and the output voltage, and based on the input voltage and the output voltage, the mode select circuit generates a buck enable signal, a boost enable signal and a buck-boost enable signal;
a mode control circuit configured to receive a feedback signal indicative of the output voltage, a reference signal, the buck enable signal, the boost enable signal and the buck-boost enable signal, and based on the feedback signal, the reference signal, the buck enable signal, the boost enable signal and the buck-boost enable signal, the mode control circuit generates a first buck control signal, a second buck control signal, a first boost control signal and a second boost control signal; and
a logic circuit configured to receive the first buck control signal, a second buck control signal, a first boost control signal and a second boost control signal, and based on the buck control signals and the boost control signals, the logic circuit generates a first switch control signal, a second switch control signal, a third switch control signal and a fourth switch control signal to respectively control the operation of the first power switch, the second power switch, the third power switch and the fourth power switch, so as to control the output voltage; wherein:
when the input voltage is in a range between the output voltage multiplied by K2 and the output voltage multiplied by K1, the buck-boost enable signal is valid, then the buck-boost converter works under buck-boost mode, wherein during each switching period, an on time period of the first power switch and an on time period of the third power switch are overlapped, but the on time period of the third power switch is shorter than the on time period of the first power switch, and wherein K1 and K2 are constant coefficients, and K1>1, 0 the mode control circuit comprises:
a feedback comparator, having a first input terminal configured to receive the reference signal, a second input terminal configured to receive the feedback signal indicative of the output voltage, and an output terminal configured to provide a set signal based on the reference signal and the feedback signal;
a first RS flip-flop having a reset terminal configured to receive a reset signal, a set terminal coupled to the output terminal of the feedback comparator to receive the set signal, and an output terminal configured to provide a feedback control signal based on the set signal and the reset signal;
a first enable logic circuit having a first input terminal coupled to the output terminal of the first RS flip-flop to receive the feedback control signal, a second input terminal configured to receive the buck enable signal, and an output terminal configured to provide a first buck control signal based on the feedback control signal and the buck enable signal;
a second enable logic circuit having a first input terminal coupled to the output terminal of the first RS flip-flop to receive the feedback control signal, a second input terminal configured to receive the boost enable signal, and an output terminal configured to provide a first boost control signal based on the feedback control signal and the boost enable signal;
a third enable logic circuit having a first input terminal coupled to the output terminal of the first RS flip-flop to receive the feedback control signal, a second input terminal configured to receive the buck-boost enable signal, and an output terminal configured to provide a second buck control signal based on the feedback control signal and the buck-boost enable signal;
a first constant on time circuit having an input terminal coupled to the output terminal of the first enable logic circuit to receive the first buck control signal, and an output terminal configured to provide a first buck reset signal based on the first buck control signal, wherein the first buck reset signal has a first constant on time period during each switching period of the buck-boost converter;
a second constant on time circuit having an input terminal coupled to the output terminal of the second enable logic circuit to receive the first boost control signal, and an output terminal configured to provide a first boost reset signal based on the first boost control signal, wherein the first boost reset signal has a second constant on time period during each switching period of the buck-boost converter;
a third constant on time circuit having an input terminal coupled to the output terminal of the third enable logic circuit to receive the second buck control signal, and an output terminal configured to provide a second buck reset signal based on the second buck control signal, wherein the second buck reset signal has a third constant on time period during each switching period of the buck-boost converter;
a delay circuit having an input terminal coupled to the output terminal of the third enable logic circuit to receive the second buck control signal, and an output terminal configured to provide a delay signal being delayed for a preset time length compared to the second buck control signal;
a second RS flip-flop having a set terminal coupled to the output terminal of the delay circuit to receive the delay signal, and an output terminal configured to provide a second boost control signal;
a fourth constant on time circuit having an input terminal coupled to the output terminal of the second RS flip-flop to receive the second boost control signal, and an output terminal configured to provide a second boost reset signal based on the second boost control signal, wherein the second boost reset signal has a fourth constant on time period during each switching period of the buck-boost converter; and
a reset logic circuit having a first input terminal coupled to the output terminal of the first constant on time circuit to receive the first buck reset signal, a second input terminal coupled to the output terminal of the second constant on time circuit to receive the first boost reset signal, a third input terminal coupled to the output terminal of the constant on time circuit to receive the second buck reset signal, and an output terminal configured to provide the reset signal based on the first buck reset signal, the second buck reset signal and the first boost reset signal; wherein
the second RS flip-flop further has a reset terminal coupled to the output terminal of the fourth constant on time circuit to receive the second boost reset signal.

US Pat. No. 9,935,176

METHOD FOR FABRICATING LDMOS USING CMP TECHNOLOGY

Monolithic Power Systems,...

10. A manufacturing process of a LDMOS device, comprising:forming a well region in a semiconductor substrate;
forming a gate oxidation layer above the well region;
depositing a polysilicon layer above the gate oxidation layer;
sequentially forming a gate seal layer, a silicon nitride layer and a first masking layer above the polysilicon layer, wherein the first masking layer comprises at least a window to the surface of the silicon nitride layer;
etching the silicon nitride layer, the gate seal layer and the polysilicon layer under the window of the first masking layer to expose a window for a body region in the well region;
implanting P type dopants into the well region under the window for the body region to form the body region in the well region, and removing the first masking layer later;
oxidizing side walls of the polysilicon layer in a window of the polysilicon layer which is formed after etching;
forming spacers at the oxidized side walls of the polysilicon layer;
filling the window between the spacers with polysilicon to forming a polysilicon block;
performing chemical mechanical polishing to expose the spacers between the polysilicon block and the side walls of the polysilicon layer;
etching away the silicon nitride layer and the spacers to expose windows for source regions;
implanting N type dopants into the well region under the windows for source regions to forming source region;
etching away the polysilicon block;
forming a second masking layer above the gate seal layer, wherein the second masking layer has windows at predetermined positions;
etching the gate seal layer and the polysilicon layer through the windows of the second masking layer to form a gate, and removing the second masking layer later;
forming a third masking layer above the gate and the gate oxidation layer, wherein the third masking layer comprises windows for drain pickup regions; and
implanting N type dopants into the well region under the windows of the third masking layer to form the drain pickup regions, and removing the third masking layer later.

US Pat. No. 9,912,240

HIGHLY SCALABLE MULTIPHASE POWER SUPPLY WITH CONSTANT ON-TIME DC-DC CONVERTERS

Monolithic Power Systems,...

1. A multiphase power supply comprising:
a first constant ON-time (COT) DC-DC converter integrated circuit (IC) that is configured to generate a first synchronization
signal, output the first synchronization signal at a first pin, and propagate a second synchronization signal at a second
pin;

a second COT DC-DC converter IC that is configured to receive the first synchronization signal at a first pin, receive the
second synchronization signal at a second pin, and propagate the second synchronization signal at a third pin, the second
COT DC-DC converter IC being configured to turn ON with the first COT DC-DC converter IC in synchronization with the first
and second synchronization signals;

a third COT DC-DC converter IC that is configured to receive the first synchronization signal at a first pin, receive the
second synchronization signal at a second pin, and propagate the second synchronization signal at a third pin; and

a fourth COT DC-DC converter IC that is configured to receive the first synchronization signal at a first pin, receive the
second synchronization signal at a second pin, and propagate the second synchronization signal at a third pin, the fourth
COT DC-DC converter IC being configured to turn ON with the third COT DC-DC converter IC in synchronization with the first
and second synchronization signals,

wherein the first pin of the first COT DC-DC converter IC is connected to the first pin of the second COT DC-DC converter
IC and to the first pin of the fourth DC-DC converter IC through a first buffer.

US Pat. No. 9,871,508

SMART SWITCH FOR CONNECTING AN INPUT POWER SUPPLY TO A LOAD

Monolithic Power Systems,...

7. A method comprising:
receiving an input power supply at a first pin of a monolithic integrated circuit (IC) switch device;
coupling the input power supply at the first pin to a second pin of the monolithic IC switch device by way of a power switch
in the monolithic IC switch device;

receiving an enable signal at a fourth pin of the monolithic IC switch device to enable or disable the power switch;
outputting a first current indicator signal that is indicative of an output current of the monolithic IC switch device at
a sixth pin of the monolithic IC switch device; and

outputting a second current indicator signal that is indicative of the output current of the monolithic IC switch device at
a seventh pin of the monolithic IC switch device.

US Pat. No. 9,780,640

MULTI-PHASE VOLTAGE CONVERTER WITH FAULT INSTRUCTION CIRCUIT

Monolithic Power Systems,...

1. A switching circuit used in a voltage converter, the switching circuit comprising:
a first pin, the switching circuit is configured to output a disable signal through the first pin, wherein the switching circuit
is turned off once the disable signal is in an active state, and wherein the disable signal is in the active state when one
or more faults occur in the switching circuit; and

a second pin, when the disable signal is in an inactive state, the switching circuit is configured to receive a control signal
through the second pin to control the switching circuit; and when the disable signal is in the active state, the switching
circuit is configured to output an instruction signal through the second pin, wherein the instruction signal is configured
to represent each of the one or more faults with a particular value.

US Pat. No. 9,734,917

CURRENT BALANCE CIRCUIT AND THE METHOD THEREOF

Monolithic Power Systems,...

1. A current balance circuit for a power management device having a first current channel and a second current channel, comprising:
a first terminal coupled to an input terminal of the first current channel;
a second terminal coupled to an input terminal of the second current channel;
a third terminal coupled to an output terminal of the first current channel; and
a fourth terminal coupled to an output terminal of the second current channel;
a first current sense circuit having an input terminal coupled to the input terminal of the first current channel to detect
a current flowing through the first current channel, and an output terminal configured to provide a first current sense signal
indicative of the current flowing through the first current channel; wherein

the current balance circuit draws current from the second current channel to the first current channel based on the first
current sense signal.