US Pat. No. 9,159,677

METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES

Micron Technology, Inc., ...

1. A method of forming a semiconductor device structure comprising forming at least one distributed Bragg reflector comprising
at least three dielectric materials having different refractive indices than one another on an upper surface of a gate structure
of a transistor and on an upper surface of an electrically insulative material laterally surrounding the gate structure, the
at least one distributed Bragg reflector configured to substantially reflect therefrom radiation within a predetermined wavelength
range and to substantially transmit therethrough radiation within a different predetermined wavelength range.

US Pat. No. 9,489,302

CONTROL ARRANGEMENTS AND METHODS FOR ACCESSING BLOCK ORIENTED NONVOLATILE MEMORY

Micron Technology, Inc., ...

1. A memory system for digital data communication with a host device to provide data storage capacity for the host device,
said memory system comprising:
at least one module including a nonvolatile memory section that is made up of a plurality of memory devices that are distinct
from one another and the module includes a bit density function to assign a storage density to each memory device such that
one group of the memory devices is configured to store data at a high storage density and another group of the memory devices
is configured to store data at a low storage density, where the high storage density is greater than the low storage density,
and the module independently performs the bit density setting function for the nonvolatile memory section of only that module
based on one or more module input parameters; and

a controller configured for said digital data communication with the host device and further configured for module digital
data communication with the module such that any data flowing to and from the module passes through the controller.

US Pat. No. 9,282,646

INTERPOSED SUBSTRATE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. An interposed substrate comprising:
an insulating material layer having an upper surface and a lower surface opposite to each other, and a plurality of first
through holes and a plurality of second through holes, wherein the first through holes and the second through holes penetrate
through the insulating material layer, and a diameter of each of the first through holes is smaller than a diameter of each
of the second through holes;

a plurality of conductive pillars respectively disposed within the first through holes of the insulating material layer, wherein
each conductive pillar has a top surface and a bottom surface opposite to each other, and the top surface of each conductive
pillar and the upper surface of the insulating material layer are coplanar;

a patterned conductor layer disposed within the second through holes of the insulating material layer, wherein the conductive
pillars are separated from each other and stacked on the patterned conductor layer, and a bottom surface of the patterned
conductor layer and the lower surface of the insulating material layer are not aligned; and

a dielectric layer disposed on the upper surface of the insulating material layer, wherein the dielectric layer directly covers
the upper surface of the insulating material layer and the top surfaces of the conductive pillars.

US Pat. No. 9,161,454

ELECTRICAL DEVICE PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

Unimicron Technology Corp...

1. An electrical device package structure comprising:
a dielectric layer having a first surface, a second surface opposite to the first surface, a first caving pattern disposed
on the first surface and caved into the first surface, at least one second caving pattern disposed on the second surface and
caved into the second surface and at least one through hole extended from the first caving pattern to the second caving pattern;

an electrical device embedded in the dielectric layer and having at least one electrode and the electrode exposing the second
caving pattern;

a first conductive pattern filled in the first caving pattern;
a second conductive pattern filled in the second caving pattern and connected with the electrode of the electrical device;
a conductive via filled in the through hole and connected with the first conductive pattern and the second conductive pattern;
a first solder mask disposed on the first surface and the first conductive pattern of the dielectric layer, and exposing portions
of the first conductive pattern, wherein a surface of the electrical device directly contacted with the first solder mask
and a surface of the first conductive pattern directly contacted with the first solder mask are located in a single plane;
and

a second solder mask disposed on the second surface and the second conductive pattern of the dielectric layer, and exposing
portions of the second conductive pattern.

US Pat. No. 9,131,614

METHOD OF MANUFACTURING AN EMBEDDED WIRING BOARD

UNIMICRON TECHNOLOGY CORP...

1. A method for manufacturing an embedded wiring board, comprising:
providing an activating insulation layer (210) comprising a plurality of catalyst particles (216) substantially evenly distributed in a high molecular weight compound (218), wherein the activating insulating layer has a first wiring layer (220a) exposedly embedded in a lower surface thereof;

forming an intaglio pattern on a upper surface of the activating insulating layer and at least one blind via that partially
exposes the first wiring layer through the intaglio pattern, wherein some of the catalyst particles are activated and exposed
in the intaglio pattern and the blind via;

dipping the activating insulation layer in a first chemical plating solution for forming a solid conductive pillar in the
blind via through electroless plating; and

dipping the activating insulation layer in a second chemical plating solution after forming the solid conductive pillar for
forming a second wiring layer (230) in the intaglio pattern through electroless plating,

wherein solutes of the first chemical plating solution and the second chemical plating solution are different.

US Pat. No. 9,166,579

METHODS AND APPARATUSES FOR SHIFTING DATA SIGNALS TO MATCH COMMAND SIGNAL DELAY

Micron Technology, Inc., ...

1. An apparatus, comprising:
a clock generation circuit configured to receive an input clock signal and generate a plurality of clock signals based, at
least in part, on the input clock signal;

a delay path coupled to the clock generation circuit and configured to receive the input clock signal and the plurality of
clock signals, the delay path further configured to receive a data signal and delay the data signal based, at least in part,
on the input clock signal and each of the plurality of clock signals; and

a driver coupled to the delay path and configured to receive the delayed data signal, the driver further configured to provide
the delayed data signal to a bus,

wherein the delay path comprises a plurality of latches coupled in series, each latch of the plurality of latches configured
to receive one of the plurality of clock signals.

US Pat. No. 9,237,643

CIRCUIT BOARD STRUCTURE

Unimicron Technology Corp...

1. A circuit board structure, comprising:
a core layer with surface material thereof being dielectric material, having a first surface and a corresponding second surface;
a fine circuit pattern, embedded in the first surface of the core layer;
a patterned conductive layer, disposed on the second surface of the core layer and protrudes from the second surface of the
core layer;

at least a conductive through via penetrating the core layer and connecting the fine circuit pattern to the patterned conductive
layer, wherein the conductive through via has a shape of hollow cylinder or solid cylinder; and

a first solder mask, disposed on the first surface of the dielectric layer and the fine circuit pattern, wherein the fine
circuit pattern has at least a first joint pad, and the first solder mask exposes the first joint pad.

US Pat. No. 9,084,379

PROCESS FOR FABRICATING WIRING BOARD

UNIMICRON TECHNOLOGY CORP...

1. A process for fabricating a wiring board, comprising:
forming a first wiring carrying substrate including a first carry substrate and a first wiring layer disposed on the first
carry substrate;

forming at least a first blind via in the first wiring carrying substrate, wherein the first blind via extends from the first
wiring layer into the first carry substrate;

laminating the first wiring carrying substrate to a second wiring carrying substrate via an insulation layer, wherein the
second wiring carrying substrate includes a second carry substrate and a second wiring layer disposed on the second carry
substrate, the insulation layer is disposed between the first wiring layer and the second wiring layer, and full fills the
first blind via;

removing a part of the first carry substrate and a part of the second carry substrate to expose the insulation layer in the
first blind via;

removing a part of the insulation layer in the first blind via to form a hole extending from the first wiring layer to the
second wiring layer;

forming a conductive pillar in the hole, wherein the conductive pillar is connected between the first wiring layer and the
second wiring layer; and

removing the remained first carry substrate and the remained second carry substrate.

US Pat. No. 9,370,099

MANUFACTURING METHOD OF CONNECTOR

UNIMICRON TECHNOLOGY CORP...

1. A manufacturing method of connector, comprising the following steps:
providing a substrate layer and forming a first metal layer on the substrate layer;
patterning the first metal layer to form a wiring layer;
forming a dielectric layer on the wiring layer, wherein the dielectric layer is formed with at least one via hole to partially
expose the wiring layer and a conductive structure arranged on the inner wall of the at least one via hole and electrically
connected to the wiring layer;

forming a first protective layer on the dielectric layer and at least one cantilever structure between the first protective
layer and the dielectric layer, wherein the at least one cantilever structure is electrically connected to the wiring layer
via the conductive structure; and

removing the substrate layer.

US Pat. No. 9,408,313

PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A packaging substrate, comprising:
a substrate body having a first surface and a second surface opposite to the first surface, the first surface having a plurality
of first conductive pads thereon, and the second surface having a die attach area and a peripheral area surrounding the die
attach area, the die attach area having a plurality of second conductive pads embedded therein, wherein top surfaces of the
second conductive pads are exposed from the second surface, and the die attach area of the second surface is fully exposed;
and

a plurality of conductive pillars correspondingly disposed on the second conductive pads and having first ends and opposite
second ends, wherein the first ends are level with the second surface of the substrate body, and the first ends have a width
bigger than a width of the second ends.

US Pat. No. 9,095,083

MANUFACTURING METHOD FOR MULTI-LAYER CIRCUIT BOARD

Unimicron Technology Corp...

1. A manufacturing method for a multi-layer circuit board, comprising:
providing a substrate having a first via penetrating the substrate;
forming a first patterned circuit layer on a surface of the substrate by using the first via as an alignment target, and the
first patterned circuit layer including a first concentric-circle pattern surrounding the first via;

forming a first stacking layer on the surface and covering the first patterned circuit layer, and the first stacking layer
including a first dielectric layer and a first circuit layer covering the first dielectric layer;

forming a first through hole, and the first through hole penetrating regions where an inner diameter of a first concentric
circle from a center of the first concentric-circle pattern is orthogonally projected on the first stacking layer and the
substrate;

forming a second stacking layer on the first stacking layer, and the second stacking layer including a second dielectric layer
and a second circuit layer covering the second dielectric layer; and

forming a second through hole, and the second through hole penetrating regions where an inner diameter of a second concentric
circle from the center of the first concentric-circle pattern is orthogonally projected on the second stacking layer, the
first stacking layer and the substrate.

US Pat. No. 9,074,051

DIANHYDRIDE MONOMER HAVING SIDE CHAIN, POLYIMIDE COMPOUND HAVING SIDE CHAIN AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A dianhydride monomer having side chain, comprising the formula is listed as formula (I) below:

wherein R is a cycloalkane group with at least one tertiary carbon atom.

US Pat. No. 9,179,549

PACKAGING SUBSTRATE HAVING EMBEDDED PASSIVE COMPONENT AND FABRICATION METHOD THEREOF

Unimicron Technology Corp...

1. A packaging substrate having at least an embedded passive component, comprising:
a core board having at least a cavity;
a single-material dielectric layer unit having an upper surface and a lower surface, and encapsulating the core board and
filling the cavity of the core board;

a plurality of positioning pads embedded in the lower surface of the dielectric layer unit;
at least a passive component having upper and lower surfaces each having a plurality of electrode pads disposed thereon, the
passive component being embedded in the dielectric layer unit so as to be received in the cavity of the core board at a position
corresponding to the positioning pads;

a first wiring layer disposed on the upper surface of the dielectric layer unit and electrically connected to the electrode
pads of the upper surface of the passive component through a plurality of first conductive vias; and

a second wiring layer disposed on the lower surface of the dielectric layer unit and electrically connected to the electrode
pads of the lower surface of the passive component through a plurality of second conductive vias,

wherein the second conductive vias penetrate the positioning pads, respectively, and
the dielectric layer unit encapsulates the positioning pads and the passive component.

US Pat. No. 9,320,143

TOUCH MEMBER AND METHOD OF MANUFACTURING THE SAME

Unimicron Technology Corp...

1. A wiring board comprising:
a substrate having opposing first and second surfaces, the substrate having at least one through-via passing through the substrate
from the first surface to the second surface;

a first conductor layer formed on the first surface;
a second conductor layer formed on the second surface; and
a through-via conductor formed in the through-via for electrically connecting to the first conductor layer and the second
conductor layer;

wherein the through-via has a first depressed portion exposed in the first surface, a second depressed portion exposed in
the second surface, and a cylindrical tunnel portion having a substantially constant internal diameter between the first depressed
portion and the second depressed portion for connecting the first depressed portion and the second depressed portion,

wherein the first depressed portion and the second depressed portion are non-coaxial, and the internal diameter of the tunnel
portion is less than a diameter of the first depressed portion in the first surface and a diameter of the second depressed
portion in the second surface;

wherein a bore axis of the first depressed portion and a bore axis of the second depressed portion slant toward each other
at an angle, which is in a range of 5 to 70 degrees, said bore axis of the second depressed portion is substantially perpendicular
to said second surface of said substrate; and

wherein the first depressed portion has a first opening in the first surface, the second depressed portion has a second opening
in the second surface, and a vertical projection of a center point of the first opening on the second surface and a center
point of the second opening are offset from each other by a distance in a range of 5 micrometer to 40 micrometers.

US Pat. No. 9,510,464

MANUFACTURING METHOD OF CIRCUIT BOARD

Unimicron Technology Corp...

1. A manufacturing method of a circuit board, comprising:
providing a circuit substrate having a first surface and at least a first circuit;
forming a dielectric layer on the circuit substrate, the dielectric layer having a second surface and covering the first surface
and the at least a first circuit;

irradiating the dielectric layer by a laser beam to form a first intaglio pattern, a second intaglio pattern, and at least
a blind via extending from the second surface of the dielectric layer to the at least a first circuit of the circuit substrate;

forming a first conductive layer in the first intaglio pattern, the second intaglio pattern, and the at least a blind via,
wherein the first conductive layer fills the first intaglio pattern and is disposed on an inner wall of the second intaglio
pattern and an inner wall of the at least a blind via, and an entire volume of the first intaglio pattern is full of the first
conductive layer;

forming a barrier layer in the second intaglio pattern and the at least a blind via, the barrier layer covering the first
conductive layer;

forming a second conductive layer in the second intaglio pattern and the at least a blind via, the second conductive layer
covering the barrier layer; and

removing parts of the second conductive layer, parts of the barrier layer, and parts of the first conductive layer until the
second surface of the dielectric layer is exposed to form a patterned circuit structure, the patterned circuit structure being
located in the first intaglio pattern, the second intaglio pattern, and the at least a blind via and being electrically connected
to the at least a first circuit of the circuit substrate.

US Pat. No. 9,045,597

POLYIMIDE COMPOUND HAVING SIDE CHAIN AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A manufacturing method of polyimide compound having side chain, comprising:
(A) dissolving diamine monomer (a) and dianhydride monomer (b) into cresol by stirring under anhydrous condition to form polyamic
acid compound (c) solution,

wherein the general formula of diamine monomer (a) is shown as formula (V) below:

wherein the general formula of dianhydride monomer (b) is shown as formula (X) below:

wherein the general formula of polyamic acid compound (c) is shown as formula(XII) below

wherein R and R? comprises aromatic hydrocarbon or alicyclic hydrocarbon,
wherein the reaction temperature is 20 to 30, the reaction time is 6 to 7 hours;
(B) adding 5-10 drops of isoquinoline into polyamic acid compound solution, and heating refluxing the solution to form polyimide
compound solution,

wherein the reaction temperature is 100 to 200, the reaction time is 8 to 12 hours; and
(C) cooling polyimide compound (d) solution and adding polyimide compound solution (d) into ethanol to precipitate out solid
polyimide compound (d),

wherein the general formula of polyimide compound (d) is shown as formula (I) below:

(D) heating refluxing solid polyimide compound (d) and ethanol,
wherein the reaction temperature is 70 to 80, the reaction time is 4 to 6 hours.

US Pat. No. 9,380,706

METHOD OF MANUFACTURING A SUBSTRATE STRIP WITH WIRING

Unimicron Technology Corp...

1. A manufacturing method for a substrate strip with a wiring, comprising:
cutting a substrate panel to form a plurality of separated wiring blocks, wherein each of the wiring blocks comprises at least
one wiring board unit, and each of the wiring board units comprises an insulating layer and a wiring layer disposed on the
insulating layer;

testing the wiring blocks to determine whether the wiring blocks are normal or abnormal;
establishing an adhesive layer on a carrying substrate, the adhesive layer having a composition that generates an stronger
adhesion force with respect to the carrying substrate than with respect to the insulating layer; and

after the step of testing the wiring blocks, selectively disposing the normal wiring blocks on the adhesive layer, wherein
the adhesive layer is arranged between the disposed normal wiring blocks and the carrying substrate, wherein the adhesive
layer adheres to and directly contacts the wiring layer of each of the normal wiring blocks so that the wiring layer is embedded
in the adhesive layer and when the adhesive layer is separated from the normal wiring blocks, the adhesive layer is maintained
in contact with on the carrying substrate.

US Pat. No. 9,084,342

MANUFACTURING METHOD OF CIRCUIT BOARD

Unimicron Technology Corp...

1. A manufacturing method of a circuit board, comprising:
providing a substrate, wherein the substrate has a pre-removing area, and the substrate comprises:
a first dielectric layer;
a first laser resistant structure, disposed on a first surface of the first dielectric layer and located at a periphery of
the pre-removing area;

a second dielectric layer, disposed on the first dielectric layer and covering the first laser resistant structure;
a circuit layer, disposed on a second surface of the second dielectric layer, wherein a portion of the circuit layer is extended
from outside of the pre-removing area into the pre-removing area;

a second laser resistant structure, disposed on the second surface, located at the periphery of the pre-removing area, and
insulated from the circuit layer, wherein there is at least one gap between the second laser resistant structure and the circuit
layer, and a vertical projection of the gap on the first surface overlaps the first laser resistant structure;

a third dielectric layer, disposed on the second dielectric layer, and covering the circuit layer and the second laser resistant
structure;

performing a laser machining process to etch the third dielectric layer located at the periphery of the pre-removing area;
removing a portion of the third dielectric layer located within the pre-removing area; and
performing an etching process or a mechanical processing to remove the second laser resistant structure.

US Pat. No. 9,288,917

MANUFACTURING METHOD FOR MULTI-LAYER CIRCUIT BOARD

Unimicron Technology Corp...

1. A method for manufacturing a multi-layer circuit board, comprising:
providing a substrate, the substrate comprising two surfaces opposite to each other and a first via connecting the surfaces;
forming a first patterned circuit layer on each of the surfaces by using the first via as an alignment target, wherein each
of the first patterned circuit layers comprises a first concentric-circle pattern surrounding the first via;

forming a first stacking layer on each of the surfaces, the first stacking layer comprising a first dielectric layer and a
first circuit layer covering the first dielectric layer;

forming a first through hole, the first through hole penetrating regions of the first stacking layers and the substrate where
an inner diameter of a first concentric circle from a center of the first concentric-circle pattern is orthogonally projected
on;

forming a second stacking layer on each of the first stacking layers, each of the second stacking layers comprising a second
dielectric layer and a second circuit layer covering the second dielectric layer; and

forming a second through hole penetrating regions of the second stacking layers, the first stacking layers, and the substrate
where an inner diameter of a second concentric circle from the center of the first concentric-circle pattern is orthogonally
projected.

US Pat. No. 9,374,896

PACKAGING CARRIER AND MANUFACTURING METHOD THEREOF AND CHIP PACKAGE STRUCTURE

Unimicron Technology Corp...

1. A packaging carrier, comprising: an interposer, having a first surface and a second surface opposite to each other, and
a plurality of first pads and second pads located on the first surface and the second surface, respectively;
a dielectric layer, having a third surface and a fourth surface opposite to each other, wherein the interposer is embedded
in the dielectric layer, the second surface of the interposer is not covered by the fourth surface of the dielectric layer
and has a height difference with the fourth surface; and

a built-up structure, disposed on the third surface of the dielectric layer and electrically connected to the first pads of
the interposer, wherein the built-up structure only comprises a first circuit layer, at least an insulating layer, at least
a second circuit layer, a plurality of first conductive vias and a plurality of second conductive vias, the first circuit
layer is disposed on the third surface of the dielectric layer, and the first circuit layer is electrically connected to the
first pads of the interposer through the first conductive vias, the insulating layer covers the first circuit layer and the
third surface of the dielectric layer, the second circuit layer is disposed on a surface of the insulating lager relatively
away from the third surface, the second conductive vias penetrate the insulating layer and electrically connect the first
circuit layer and the second circuit layer, and the dielectric layer only covers a portion of the built-up structure by the
third surface of the dielectric layer; wherein the interposer comprises a plurality of through vias, and each through via
is filled with a conductive material and electrically connects the corresponding first pad and the corresponding second pad;
and wherein the interposer comprises a first interposer layer, a second interposer layer and a third interposer layer, the
first interposer layer is located between the second interposer layer and the third interposer layer, and the through vias
at least comprises a plurality of first through vias passing through the first interposer layer and filled with the conductive
material, two surfaces opposite to each other of the first interposer layer are aligned with two ends of each of the first
through vias filled with the conductive material, and the second interposer layer and the third interposer layer respectively
have the first surface and the second surface, and a material of the first interposer layer comprises silicon, glass or ceramic;

materials of the second interposer layer and the third interposer layer are selected from glass, ceramic, polyimide (PI),
polybenzoxazole (PBO) fiber, bis-benzocyclobuten (BCB), silicones, acrylates or epoxy.

US Pat. No. 9,485,874

PACKAGE SUBSTRATE HAVING PHOTO-SENSITIVE DIELECTRIC LAYER AND METHOD OF FABRICATING THE SAME

Industrial Technology Res...

1. A package substrate, comprising:
an interposer having a first side and a second side opposite to the first side;
at least one conductive through via penetrating from the first side to the second side;
a redistribution layer formed on the first side and electrically connected to the conductive through via;
a photo-sensitive dielectric layer formed on the second side of the interposer;
a molding layer formed to encapsulate the interposer, wherein a bottom surface of the molding layer is aligned with an end
of the conductive through via, and the photo-sensitive dielectric layer directly covers the molding layer and the interposer;
and

at least one conductive via formed in the photo-sensitive dielectric layer and electrically connected to the conductive through
via, wherein the conductive via is in direct physical and electrical contact with the conductive through via,

wherein the photo-sensitive dielectric layer is photo-sensitive polyimide (PSPI).

US Pat. No. 9,460,992

PACKAGING SUBSTRATE HAVING A THROUGH-HOLED INTERPOSER

Unimicron Technology Corp...

1. A packaging substrate, comprising:
an interposer having opposing first and second surfaces and a plurality of conductive gels interconnecting the first surface
and the second surface, wherein each of the conductive gels has opposing first and second ends, such that the first end protrudes
from the first surface of the interposer, and a circuit redistribution structure is disposed on the second surface of the
interposer and electrically connected to the second ends of the conductive gels;

an encapsulating layer that encapsulates and is in direct contact with side surfaces and the first surface of the interposer;
and

a circuit built-up structure disposed on the encapsulating layer above the first surface of the interposer and electrically
connected to the first ends of the conductive gels.

US Pat. No. 9,159,713

OPTO-ELECTRONIC CIRCUIT BOARD AND METHOD FOR ASSEMBLING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. An optical component, comprising:
a base comprising a first via, a second via, a first surface, and a second surface opposite the first surface, wherein the
first via and the second via respectively penetrate the base from the first surface to the second surface;

a waveguide layer disposed on the first surface and comprising a bottom cladding layer, a top cladding layer, and a core layer
which is clad between the bottom cladding layer and the top cladding layer;

an emitting portion disposed at a side of the waveguide layer;
the emitting portion comprising:
a first inserting portion inserting into the first via;
a first light-guide hole aligning with the core layer of the waveguide layer, wherein the first inserting portion and the
first light-guide hole are one integral unit;

a first reflective layer disposed on an inner surface of the first light-guide hole; and
a light emitter aligning with the first light-guide hole and providing an optical signal entering to the core layer through
the first light-guide hole; and

a receiving portion disposed at the other side of the waveguide layer the receiving portion comprising:
a second inserting portion inserting into the second via;
a second light-guide hole aligning with the core layer of the waveguide layer, wherein the second inserting portion and the
second light-guide hole are one integral unit;

a second reflective layer disposed on an inner surface of the second light-guide hole; and
a light receiver aligning with the second light-guide hole, wherein the optical signal passes through the core layer and enters
the light receiver via the second light-guide hole.

US Pat. No. 9,247,631

METHOD FOR FABRICATING HEAT DISSIPATION SUBSTRATE

Unimicron Technology Corp...

1. A method for fabricating a heat dissipation substrate comprising:
providing a first composite board, wherein the first composite board comprises two metal conductive layers and a resin carrier,
wherein the resin carrier is positioned between the two metal conductive layers;

laminating second and third composite boards outside the two metal conductive layers, wherein each of the second and third
composite boards comprises an insulation layer and a thin metal layer, wherein the insulation layers are positioned between
the two metal conductive layers and the thin metal layers of the second and third composite boards;

thickening each of the thin metal layers; and
removing the resin carrier for forming first and second substrates, wherein each of said metal conductive layer forms a first
conductive layer and each of said thin metal layers becomes thicker to form a metal layer in each of the first and second
substrates, and wherein the metal layer is thicker than the first conductive layer in each of the first and second substrates;
and

in each of the first and second substrates, removing part of the metal layer for forming a metal bulk;
providing an adhesive layer, wherein the adhesive layer comprises an opening, and wherein the opening corresponds to the metal
bulk;

providing a second conductive layer;
laminating the second conductive layer, the adhesive layer, and the substrate, wherein the adhesive layer is positioned above
the substrate, and wherein the second conductive layer is above the adhesive layer;

forming a hole in the insulation layer and the first conductive layer, wherein the hole is positioned under the metal bulk;
and

forming a third conductive layer in the hole.

US Pat. No. 9,431,890

APPARATUSES AND METHODS FOR CONVERTING SINGLE INPUT VOLTAGE REGULATORS TO DUAL INPUT VOLTAGE REGULATORS

Micron Technology, Inc., ...

1. An apparatus comprising:
a control circuit configured to receive an enable signal and provide a control signal, a value of the control signal based
on the enable signal;

a high side circuit configured to receive first power at a first input and second power at a second input, the high side circuit
further configured to selectively provide one of the first or the second power to a node based on the value of the control
signal,

wherein the high side circuit comprises:
a first high side switching circuit having a first switching element, the first high side switching circuit configured to
provide the first power to the node responsive to the control signal having a first value; and

a second high side switching circuit having a second switching element and a third switching element coupled in series to
the second switching element, the second high side switching circuit configured to provide the second power to the node responsive
to the control signal having a second value;

a low side circuit configured to selectively provide a reference to the node responsive to the enable signal; and
a filter coupled to the node and configured to provide output power responsive to input received at the node.

US Pat. No. 9,253,898

RIGID FLEX BOARD MODULE AND THE MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A rigid flex board module, comprising:
a rigid flex circuit board, comprising:
a flexible circuit board including a bending portion and a jointing portion connected to the bending portion;
a first rigid circuit board disposed on the jointing portion and exposing the bending portion, and the first rigid circuit
board electrically connected to the flexible circuit board; and

a first adhesive layer connected between the first rigid circuit board and the jointing portion;
a high-density interconnected circuit board arranged in and electrically connected to the first rigid circuit board, wherein
the total number of layers of high-density interconnected circuit board is larger than the total number of layers of the flexible
circuit board;

at least one pair of multi-layer circuit layers respectively configured at two sides of the rigid flex circuit board and two
sides of the high-density interconnected circuit board; and

a plurality of conductive posts electrically connected to the pair of multi-layer circuit layers, the high-density interconnected
circuit board, and the first rigid circuit board.

US Pat. No. 9,281,402

METHODS OF FABRICATING FIN STRUCTURES

Micron Technology, Inc., ...

17. A device, comprising:
a transistor, comprising:
a substrate;
a double fin structure recessed below an upper surface of the substrate, wherein the double fin structure comprises a first
fin, a second fin, and a channel formed therebetween, and wherein the first fin and the second fin of the double fin structure
extends substantially upwardly from a second surface of the substrate; and

a gate deposited on the double tin structure.

US Pat. No. 9,176,800

MEMORY REFRESH METHODS AND APPARATUSES

Micron Technology, Inc., ...

1. A method, comprising:
checking a portion of non-volatile memory of a non-volatile memory device for errors in response to the memory device being
powered on, wherein a different portion of the memory is checked for errors in response to each power on;

checking additional portions of the memory for errors, during operation of the memory, after a predetermined number of pages
of the memory have been read wherein the predetermined number of pages is a total number of pages accumulated over a plurality
of power cycles; and

reprogramming corrected data to the memory if errors are found.

US Pat. No. 9,484,223

CORELESS PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A method of fabricating a coreless packaging substrate, comprising the steps of:
providing a carrier board having a plurality of electrical pads formed thereon;
forming a circuit buildup structure on the carrier board and the electrical pads, the circuit buildup structure having at
least a dielectric layer, at least a wiring layer formed on the at least a dielectric layer, and a plurality of conductive
elements formed in the dielectric layer and electrically connected to the at least a wiring layer, wherein the electrical
pads are embedded in a lowermost one of the at least a dielectric layer, so as for part of the conductive elements to be electrically
connected with the electrical pads;

forming a plurality of metal bumps on an uppermost one of the at least a wiring layer;
forming a dielectric passivation layer on an uppermost one of the at least a dielectric layer and the uppermost one of the
at least a wiring layer for covering the metal bumps;

removing a part of the dielectric passivation layer and a part of each of the metal bumps for each of the metal bumps to be
formed by a metal column portion and a wing portion integrally connected to the metal column portion, and for an entire top
surface of the wing portion of each of the metal bumps to be exposed from the dielectric passivation layer, so as for a semiconductor
chip to be electrically connected to the exposed wing portions of the metal bumps; and

removing the carrier board for exposing the electrical pads from the lowermost one of the at least a dielectric layer.

US Pat. No. 9,484,224

METHOD OF FABRICATING A CIRCUIT BOARD STRUCTURE

Unimicron Technology Corp...

1. A fabrication method of a circuit board structure, comprising the steps of:
providing a carrying board having a first and an opposite second surface and having at least one through cavity formed therein;
placing a semiconductor chip in the through cavity of the carrying board, wherein the semiconductor chip has an active surface
and an opposite inactive surface, and the active surface has a plurality of electrode pads thereon;

filling with an adhesive material in a gap between the through cavity of the carrying board and the semiconductor chip to
fix in position the semiconductor chip in the through cavity, wherein a surface of the adhesive material is flush with the
inactive surface of the semiconductor chip and the second surface;

forming a reinforcing layer on the second surface of the carrying board and the inactive surface of the semiconductor chip,
wherein the reinforcing layer is made of a thermoplastic resin different from a material of the carrying board; and

forming an opening in the reinforcing layer to expose a portion of the inactive surface of the semiconductor chip, wherein
a portion of the reinforcing layer is formed on the inactive surface of the semiconductor chip.

US Pat. No. 9,258,908

SUBSTRATE STRUCTURE HAVING COMPONENT-DISPOSING AREA AND MANUFACTURING PROCESS THEREOF

Unimicron Technology Corp...

1. A substrate structure having a component-disposing area, comprising:
a core layer, comprising a first surface, a patterned metallic layer and a component-disposing area, wherein the patterned
metallic layer is disposed on the first surface and comprises a plurality of pads and the pads are located within the component-disposing
area;

a first dielectric-layer, disposed on the core layer and comprising a plurality of openings respectively exposing the pads;
a laser-resistant metallic pattern, disposed on and directly contacting the first dielectric layer and surrounding a projection
area of the first dielectric-layer which the component-disposing area orthogonally projected on; and

a second dielectric layer, disposed on the first dielectric layer and covering the laser-resistant metallic pattern, wherein
the second dielectric layer comprises a component-disposing cavity corresponding to the projection area, penetrating through
the second dielectric layer and communicated with the openings to expose the pads, and the component-disposing cavity exposing
a part of the laser-resistant metallic pattern surrounding the projection area.

US Pat. No. 9,240,547

MAGNETIC TUNNEL JUNCTIONS AND METHODS OF FORMING MAGNETIC TUNNEL JUNCTIONS

Micron Technology, Inc., ...

1. A method of forming a line of magnetic tunnel junctions, comprising:
forming magnetic recording material over a substrate, non-magnetic material over the recording material, and magnetic reference
material over the non-magnetic material; the substrate comprising alternating outer regions of reactant source material and
insulator material along at least one cross-section; the reactant source material comprising a reactant that will react with
the recording material to form dielectric material when subjected to a set of temperature and pressure conditions;

patterning the reference material into a longitudinally elongated line passing over the alternating outer regions; and
subjecting the recording material to the set of temperature and pressure conditions to react with the reactant of the reactant
source material to form regions of the dielectric material which longitudinally alternate with the recording material along
the line and to form magnetic tunnel junctions along the line which individually comprise the recording material, the non-magnetic
material, and the reference material that are longitudinally between the dielectric material regions.

US Pat. No. 9,099,442

CONDUCTIVE INTERCONNECT STRUCTURES INCORPORATING NEGATIVE THERMAL EXPANSION MATERIALS AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS

Micron Technology, Inc., ...

1. A semiconductor device, comprising:
a substrate having an opening extending at least partially through the substrate;
a conductive material partially filling the opening; and
a negative thermal expansion (NTE) material also partially filling the opening,
wherein the conductive material is disposed between the substrate and the NTE material.

US Pat. No. 9,313,902

CONDUCTIVE STRUCTURES FOR MICROFEATURE DEVICES AND METHODS FOR FABRICATING MICROFEATURE DEVICES

Micron Technology, Inc., ...

1. A method for fabricating interposer devices having substrates, the method comprising:
forming a plurality of conductive sections on a first side of a first interposer substrate in a first pattern;
forming a plurality of conductive sections on a first side of a second interposer substrate in a second pattern different
than the first pattern, wherein the second interposer substrate is separate and discrete from the first interposer substrate;
and

constructing a plurality of conductive lines on both the first interposer substrate and the second interposer substrate, wherein
the first interposer substrate and the second interposer substrate have the same predetermined arrangement of conductive lines,

wherein the plurality of conductive lines are formed either before or after forming the conductive sections in the first pattern
and/or forming the conductive sections in the second pattern on the first and second interposer substrates, respectively,

wherein the conductive lines at the first side of the first interposer substrate are positioned to be directly electrically
coupled to corresponding connectors on a first microelectronic die to which the first interposer substrate will be attached,
and

wherein the conductive lines at the first side of the second interposer substrate are positioned to be directly electrically
coupled to corresponding connectors on a second microelectronic die to which the second interposer substrate will be attached,
wherein the first interposer substrate remains separate and discrete from the second interposer substrate before and after
constructing the plurality of conductive lines.

US Pat. No. 9,247,654

CARRIER SUBSTRATE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A carrier substrate, comprising:
a dielectric layer having a first surface and a second surface opposite to each other and a plurality of blind vias;
a first circuit layer embedded in the first surface of the dielectric layer and having an upper surface and a lower surface
opposite to each other, the upper surface exposed from the first surface of the dielectric layer, wherein the blind vias extend
from the second surface to the first circuit layer and expose a portion of the lower surface of the first circuit layer;

an insulation layer having a third surface and a fourth surface opposite to each other and disposed on the first surface of
the dielectric layer through the fourth surface and covers a portion of the upper surface of the first circuit layer, the
insulation layer having a plurality of first openings extending from the third surface to the fourth surface, wherein the
first openings expose another portion of the upper surface of the first circuit layer, an aperture of each first opening is
increased gradually from the third surface to the fourth surface, and the apertures of the first openings on the fourth surface
are greater than a width of the exposed first circuit layer;

a plurality of conductive blocks respectively disposed in the first openings of the insulation layer and connected with another
portion of the upper surface of the first circuit layer exposed by the first openings; and

a first conductive structure disposed on the second surface of the dielectric layer and comprising a plurality of conductive
vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.

US Pat. No. 9,198,303

MANUFACTURING METHOD FOR MULTI-LAYER CIRCUIT BOARD

Unimicron Technology Corp...

1. A manufacturing method for a multi-layer circuit board, comprising:
compressing two core layers to form a substrate having two surfaces opposite to each other;
forming a first via connecting through the two surfaces;
forming a first patterned circuit layer on each of the two surfaces by using the first via as an alignment target, and the
first patterned circuit layer including a first concentric-circle pattern surrounding the first via;

forming a first stacking layer on each of the two surfaces, and the first stacking layer including a first dielectric layer
and a first circuit layer covering the first dielectric layer;

forming a first through hole, and the first through hole penetrating regions where an inner diameter of a first concentric
circle from a center of the first concentric-circle pattern is orthogonally projected on the first stacking layers and the
substrate;

forming a second stacking layer on each of the first stacking layers, and the second stacking layer including a second dielectric
layer and a second circuit layer covering the second dielectric layer; and

forming a second through hole, and the second through hole penetrating regions where an inner diameter of a second concentric
circle from the center of the first concentric-circle pattern is orthogonally projected on the second stacking layers, the
first stacking layers and the substrate.

US Pat. No. 9,491,865

CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A circuit board with a heat-recovery function, comprising:
a substrate having a top surface and a bottom surface which are opposite to each other;
a heat-storing device embedded in the substrate and connected to a processor for performing heat exchange with the processor;
and

a thermoelectric device embedded in the substrate, comprising:
a first metal-junction surface connected to the heat-storing device for performing heat exchange with the heat-storing device;
and

a second metal-junction surface joined with the first metal-junction surface, wherein the thermoelectric device generates
an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface,
wherein the substrate further comprises:

a first recess disposed at the top surface of the substrate, wherein the thermoelectric device is located in the first recess;
a second recess disposed at the bottom surface of the substrate, wherein the heat-storing device is located in the second
recess, the first recess and the second recess are opposite to each other, and at least one portion of the substrate is located
between the heat-storing device and the thermoelectric device;

at least one first via disposed at the portion of the substrate between the heat-storing device and the thermoelectric device;
and

a first heat-conducting pillar disposed in the first via, wherein the heat-storing device performs heat exchange with the
thermoelectric device through the first heat-conducting pillar.

US Pat. No. 9,491,871

CARRIER SUBSTRATE

Unimicron Technology Corp...

1. A carrier substrate, comprising:
a dielectric layer having a first surface and a second surface opposite to each other and a plurality of blind vias;
a first circuit layer embedded in the first surface of the dielectric layer and having an upper surface and a lower surface
opposite to each other, the upper surface exposed from the first surface of the dielectric layer, wherein the blind vias extend
from the second surface to the first circuit layer and expose a portion of the lower surface of the first circuit layer;

an insulation layer having a third surface and a fourth surface opposite to each other and disposed on the first surface of
the dielectric layer through the fourth surface and covers a portion of the upper surface of the first circuit layer, the
insulation layer having a plurality of first openings extending from the third surface to the fourth surface, wherein the
first openings expose another portion of the upper surface of the first circuit layer, an aperture of each first opening is
increased gradually from the third surface to the fourth surface, and the apertures of the first openings on the fourth surface
are greater than a width of the exposed first circuit layer;

a plurality of conductive blocks respectively disposed in the first openings of the insulation layer and connected with another
portion of the upper surface of the first circuit layer exposed by the first openings, wherein a top surface of each of the
conductive blocks is higher than the third surface of the insulation layer; and

a first conductive structure disposed on the second surface of the dielectric layer and comprising a plurality of conductive
vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.

US Pat. No. 9,370,107

EMBEDDED COMPONENT STRUCTURE AND PROCESS THEREOF

Unimicron Technology Corp...

1. An embedded component structure, comprising: a wiring board having a front side, a reverse side opposite to the front side,
an opening and an interconnection layer, wherein the opening penetrates the wiring board and connects the front side and the
reverse side, and the interconnection layer is located on the front side and extends toward the opening; a component having
an active surface, a back surface opposite to the active surface, and a working area located on the active surface, wherein
the active surface is bonded to the interconnection layer, wherein the interconnection layer has a plurality of leads extending
to the opening, the component has a plurality of bonding pads located on the active surface, and the bonding pads are connected
to the leads through a plurality of conductive bumps respectively, wherein the component is located in the opening, and the
active surface and the front side of the wiring board face in a same direction; and an encapsulant filled inside the opening,
covering the component and exposing the working area.

US Pat. No. 9,485,863

CARRIER AND METHOD FOR FABRICATING CORELESS PACKAGING SUBSTRATE

Unimicron Technology Corp...

1. A carrier, comprising:
a metal board; and
a metal layer formed on at least one surface of the metal board, wherein a bonding force between the metal layer and the metal
board in a central region is less than that in a peripheral region.

US Pat. No. 9,420,690

CONNECTOR

Unimicron Technology Corp...

1. A connector comprising:
a wiring layer;
a dielectric layer disposed on the wiring layer, wherein the dielectric layer has at least one via hole to partially expose
the wiring layer;

a conductive structure disposed on the inner wall of the via hole of the dielectric layer and electrically connected to the
wiring layer;

a first protective layer disposed on the dielectric layer; and
at least one cantilever structure disposed between the first protective layer and the dielectric layer, wherein the cantilever
structure is electrically connected to the wiring layer through the conductive structure.

US Pat. No. 9,184,520

ELECTRICAL CONNECTOR

Unimicron Technology Corp...

1. An electrical connector, suitable for contacting a contact and comprising:
a base, having a recess;
an elastic terminal, connected to the base and extending to the recess, wherein the elastic terminal has a fixed end and a
free end, the fixed end is connected to the base, and the free end is located at the recess and is curved; and

a contact protrusion, connected to the elastic terminal and located at the free end, wherein when the contact moves towards
the recess, the contact is capable of pushing the elastic terminal to bend towards a bottom surface of the recess so that
the free end leans against the bottom surface of the recess.

US Pat. No. 9,553,082

PROCESS FOR IMPROVING CRITICAL DIMENSION UNIFORMITY OF INTEGRATED CIRCUIT ARRAYS

Micron Technology, Inc., ...

1. An intermediate structure of an integrated circuit, comprising:
a substrate comprising a target layer on the substrate and a hard mask layer on the substrate over the target layer, the substrate
comprising a repeating pattern of lines and spaces there-between on the substrate over the hard mask layer; and

a mask on the substrate over the repeating pattern of lines and spaces there-between and over the hard mask layer, the mask
comprising a plurality of spaced-apart array regions having a peripheral region between immediately laterally-adjacent of
the spaced-apart array

regions, the repeating pattern of the lines and the spaces there-between spanning across the immediately laterally-adjacent
spaced-apart array regions and across the peripheral region that is between the immediately laterally-adjacent spaced-apart
array regions.

US Pat. No. 9,368,442

METHOD FOR MANUFACTURING AN INTERPOSER, INTERPOSER AND CHIP PACKAGE STRUCTURE

Unimicron Technology Corp...

1. A method of manufacturing an interposer, comprising:
providing a substrate, wherein the substrate has a first surface, a second surface opposite to the first surface, and a plurality
of blind vias recessed into the first surface;

filling the blind vias with a plurality of conductive beads, so that each of the blind vias has the plurality of conductive
beads, wherein each of the conductive beads comprises a metal ball and a solder layer enclosing the metal ball;

melting the solder layers, so as to form a plurality of solder posts in the blind vias, wherein the metal balls are inlaid
in the corresponding solder posts, and each of the solder posts and the metal balls inlaid therein construct a conductive
through via;

planarizing the first surface of the substrate, such that a first end, close to the first surface, of each of the conductive
through vias is flush with the first surface of the substrate;

removing a portion of the substrate from the second surface of the substrate till a second end, close to the second surface,
of each of the conductive through vias is exposed to the second surface of the substrate and is flush with the second surface
of the substrate;

after the first surface of the substrate is planarized, manufacturing a first redistribution layer at the first surface of
the substrate, wherein the first redistribution layer is electrically connected to the first end of each of the conductive
through vias; and

after the portion of the substrate is removed from the second surface of the substrate, manufacturing a second redistribution
layer at the second surface of the substrate, wherein the second redistribution layer is electrically connected to the second
end of each of the conductive through vias.

US Pat. No. 9,348,433

OPTICAL TOUCH SENSING STRUCTURE

Unimicron Technology Corp...

1. An optical touch sensing structure, comprising:
a transparent substrate; and
a plurality of optical particles with metallic composition, disposed on the transparent substrate, wherein when an infrared
is incident on each of the optical particles with metallic composition, the infrared is reflected by each of the optical particles
with metallic composition;

a transparent adhesive layer, disposed on the transparent substrate, wherein a refractive index of the transparent adhesive
layer is identical or similar to a refractive index of the transparent substrate, and the optical particles with metallic
composition are fixed on the transparent substrate by the transparent adhesive layer, the transparent adhesive layer completely
covers the transparent substrate and the optical particles with metallic composition are distributed in the transparent adhesive
layer;

a plurality of light absorbing portions, disposed on the transparent adhesive layer and exposing a portion of the transparent
adhesive layer; and

a transparent protective layer, disposed on the transparent adhesive layer and covering the light absorbing portions and the
portion of the transparent adhesive layer exposed by light absorbing portions, wherein a refractive index of the transparent
protective layer is identical or similar to the refractive index of the transparent substrate and identical or similar to
the refractive index of the transparent adhesive layer.

US Pat. No. 9,307,651

FABRICATING PROCESS OF EMBEDDED CIRCUIT STRUCTURE

Unimicron Technology Corp...

1. A fabricating process for an embedded circuit structure, comprising:
providing a core panel;
forming at least one through hole in the core panel, the through hole penetrating the entire thickness of the core panel;
forming a first indent pattern on a first major surface of the core panel;
forming a second indent pattern on a second major surface of the core panel, the second major surface being opposite to the
first major surface of the core panel;

electroplating a conductive material into the through hole, the first indent pattern and the second indent pattern, so as
to form a conductive channel in the through hole, a first circuit pattern in the first indent pattern, and a second circuit
pattern in the second indent pattern, wherein portions of the first circuit pattern exceed the first major surface, portions
of the second circuit pattern exceed the second major surface, and the electroplating process includes performing a chemical
electroplating process at first and then performing an electrolysis electroplating process; and

removing the portions of the first circuit pattern, which exceed the first major surface, for planarizing the first circuit
pattern to be level with the first major surface of the core panel, and removing the portions of the second circuit pattern,
which exceed the second major surface, for planarizing the second circuit pattern to be level with the second major surface
of the core panel.

US Pat. No. 9,105,330

MEMORY DEVICES CONFIGURED TO APPLY DIFFERENT WEIGHTS TO DIFFERENT STRINGS OF MEMORY CELLS COUPLED TO A DATA LINE AND METHODS

Micron Technology, Inc., ...

20. A method of operating a memory device, comprising:
setting a first resistor, coupled in series with a first string of memory cells, to a first resistance, wherein the first
string of memory cells stores a first bit of data;

setting a second resistor, coupled in series with a second string of memory cells, to a second resistance different than the
first resistance, wherein the first and second strings of memory cells are coupled to a common data line, and wherein the
second string of memory cells stores a second bit of data;

comparing the first bit of the data to a first bit of input data input into the memory device; and
comparing the second bit of the data to a second bit of the input data.

US Pat. No. 9,377,596

OPTICAL-ELECTRO CIRCUIT BOARD, OPTICAL COMPONENT AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. An optical component comprising:
a multi-layer substrate comprising at least one dielectric layer, at least two circuit layers, and two through holes passing
through the at least one dielectric layer, the at least two circuit layers being located on two opposite surfaces of the at
least one dielectric layer;

an optical waveguide element located on a surface of the multi-layer substrate and between the through holes; and
two optical-electro assemblies respectively inserted into the corresponding through holes and correspondingly located at two
opposite ends of the optical waveguide element, each of the optical-electro assemblies comprises an insertion element comprising
an insertion portion, and the insertion portion is inserted into the corresponding through hole, wherein one of the optical-electro
assemblies transforms an electrical signal into a light beam and provides the light beam to the optical waveguide element,
and other one of the optical-electro assemblies receives the light beam transmitted from the optical waveguide element and
transforms the light beam into another electrical signal.

US Pat. No. 9,324,664

EMBEDDED CHIP PACKAGE STRUCTURE

Unimicron Technology Corp...

1. An embedded chip package structure, comprising:
a core layer, wherein the core layer includes a first surface, a second surface opposite to the first surface and a chip container
passing through the first surface and the second surface;

a chip, disposed in the chip container, wherein the chip includes an active surface and a protrusion and a top surface of
the protrusion is a portion of the active surface;

a first circuit layer, disposed on the first surface and electrically connected to the core layer and the chip, wherein the
first circuit layer has a through hole, and a width of the through hole is smaller than a width of the chip container, so
that the first circuit layer covers the chip except the protrusion, wherein the protrusion of the chip extends into the through
hole and is located within the through hole, and the top surface of the protrusion is exposed to receive an external signal,
and a size of a projection of the through hole on the first surface is substantially equivalent to a size of a projection
of the protrusion on the first surface; and

a second circuit layer, disposed on the second surface and electrically connected to the core layer.

US Pat. No. 9,111,818

PACKAGING SUBSTRATE

Unimicron Technology Corp...

1. A packaging substrate, comprising:
a substrate body having a plurality of conductive pads disposed on a surface thereof;
an insulating protective layer formed on the surface of the substrate body and having openings for the conductive pads to
be exposed therefrom; and

conductive pillars disposed on end surfaces of the conductive pads exposed from the openings and having first ends, opposite
second ends, and side surfaces adjacent to the first ends and the second ends, the first ends being closer than the second
ends from the conductive pads, and the first ends having a width bigger than a width of the second ends, wherein the side
surfaces are arc concave toward centers of the conductive pillars.

US Pat. No. 9,102,121

SUBSTRATES AND METHODS OF FORMING A PATTERN ON A SUBSTRATE

Micron Technology, Inc., ...

1. A method of forming a pattern on a substrate, the pattern comprising a repeating pattern region and a pattern-interrupting
region adjacent to the repeating pattern region, comprising:
forming a pattern-interrupting region mask elevationally over underlying substrate material, the pattern-interrupting region
mask comprising masking material, the masking material of the pattern-interrupting region mask forming a raised masking feature
within the pattern-interrupting region, none of the masking material of the pattern-interrupting region mask being within
the repeating pattern region;

forming a repeating pattern region mask elevationally over the pattern-interrupting region mask, the repeating pattern region
mask comprising multiple raised masking features that are elevationally over the raised masking feature of the pattern-interrupting
region mask within the pattern interrupting region and multiple raised masking features that are not elevationally over the
raised masking feature of the pattern-interrupting region mask within a repeating pattern region, the repeating pattern region
being different from and everywhere laterally of the pattern-interrupting region, the repeating pattern region and the pattern-interrupting
region being immediately laterally adjacent one another; and

using the pattern-interrupting region mask and the repeating pattern region mask as a combination mask in forming the pattern
into the underlying substrate material on which the combination mask is received.

US Pat. No. 9,609,746

CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A manufacturing method of a circuit board structure, comprising:
providing an inner circuit structure, wherein the inner circuit structure comprises a core layer having an upper surface and
a lower surface opposite to each other, a first patterned circuit layer disposed on the upper surface, a second patterned
circuit layer disposed on the lower surface, and a conductive through hole connecting the first patterned circuit layer and
the second patterned circuit layer;

forming a metal pillar on a portion of the first patterned circuit layer;
performing a build-up process to press a first build-up circuit structure on the first patterned circuit layer, wherein the
first build-up circuit structure at least comprises an inner dielectric layer, and the inner dielectric layer directly covers
the upper surface of the core layer and the first patterned circuit layer;

using a contact distance detector to detect an upper surface of the metal pillar relatively far away the first patterned circuit
layer; and

using the upper surface of the metal pillar to serve as a depth reference surface, performing a hole drilling process on the
first build-up circuit structure to remove a portion of the first build-up circuit structure and at least a portion of the
metal pillar so as to form a cavity extending from a first surface of the first build-up circuit structure relatively far
way the inner circuit structure to a portion of the inner dielectric layer, wherein the cavity exposes an inner surface of
the inner dielectric layer, and the inner dielectric layer has an opening connecting the cavity and exposing a portion of
the first patterned circuit layer, a hole diameter of the opening is smaller than a hole diameter of the cavity, and a height
difference is in between an inner surface of the inner dielectric layer exposed by the cavity and a top surface of the first
patterned circuit layer exposed by the opening.

US Pat. No. 9,418,848

METHODS OF FORMING PATTERNS WITH A MASK FORMED UTILIZING A BRUSH LAYER

Micron Technology, Inc., ...

1. A method of forming a pattern, comprising:
forming a first mask over a material, the first mask having features extending therein and defining a first pattern; the first
pattern having a first level of uniformity across a distribution of the features; the features within such distribution all
being of similar size;

forming a brush layer across the first mask and within the features to narrow the features and create a second mask from the
first mask; the second mask having a second level of uniformity across the narrowed features which is greater than the first
level of uniformity;

transferring a pattern from the second mask into the material; and
wherein the features of the first mask are distributed amongst two or more different shapes with one of the shapes being substantially
circular and another being substantially diamond, and wherein the brush layer alleviates differences between such shapes.

US Pat. No. 9,355,718

METALLIZATION SCHEME FOR INTEGRATED CIRCUIT

Micron Technology, Inc., ...

1. An integrated circuit having a memory array, comprising:
a first driver region comprising a plurality of first parallel conductive lines formed at a first vertical metal level and
extending in a first direction, wherein first drivers are formed below the first vertical metal level within the first driver
region; and

a second driver region laterally bordering the first driver region and comprising a plurality of second parallel conductive
lines formed at the first vertical metal level and extending in a second direction crossing the first direction, wherein second
drivers are formed below the first vertical metal level within the second driver region,

wherein the first drivers are configured to drive first electrode lines of the memory array and the second drivers are configured
to drive second electrode lines of the memory array, the first and second electrode lines extending in different directions.

US Pat. No. 9,564,222

COMMAND SIGNAL MANAGEMENT IN INTEGRATED CIRCUIT DEVICES

Micron Technology, Inc., ...

1. A method of operating an integrated circuit device, comprising:
performing an operation on the integrated circuit device responsive, at least in part, to a logic level of a command signal
line received at control circuitry of the integrated circuit device;

generating an output signal having a logic level indicating whether the operation is being performed;
logically combining the logic level of the output signal with the logic level of the command signal line to generate a command
signal to the control circuitry of the integrated circuit device having the logic level of the command signal line when the
output signal has a logic level indicting that the operation is not being performed, and having a particular logic level when
the output signal has a logic level indicating that the operation is being performed.

US Pat. No. 9,385,056

PACKAGING SUBSTRATE HAVING EMBEDDED INTERPOSER AND FABRICATION METHOD THEREOF

Unimicron Technology Corp...

1. A fabrication method of a packaging substrate having an embedded interposer, comprising the steps of:
preparing a multi-layer interconnect base plate having opposite third and fourth surfaces, wherein the third surface has a
plurality of first conductive terminals disposed thereon;

forming a built-up structure on the third surface of the multi-layer interconnect base plate;
removing a portion of the built-up structure through a laser so as to form a cavity and expose the plurality of first conductive
terminals from the cavity, thereby providing a carrier having opposite top and bottom surfaces, wherein the carrier comprises
the multi-layer interconnect base plate and the built-up structure having a recess, the recess is formed on the top surface
of the carrier and the plurality of first conductive terminals are formed on the recess, and a plurality of second conductive
terminals are formed on the bottom surface of the carrier for electrically connecting the carrier and an external electronic
device; and

disposing in the recess an interposer having opposite first and second surfaces and a plurality of conductive through vias
penetrating the first and second surfaces, wherein a first conductive pad is formed on an end of each of the conductive through
vias exposed from the first surface, and a second conductive pad is formed on the other end of each of the conductive through
vias exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals.

US Pat. No. 9,210,815

METHOD OF MANUFACTURING EMBEDDED WIRING BOARD

Unimicron Technology Corp...

1. A manufacturing method of an embedded wiring board, comprising:
providing an insulation layer and a lower wiring layer, wherein the insulation layer includes a polymeric material, the insulation
layer is provided with an upper surface and a lower surface opposite to the upper surface, the lower wiring layer is located
at the lower surface and includes a lower pad which is embedded in the lower surface;

distributing a plural catalyst grains in the polymeric material;
forming a groove and an engraved pattern on the upper surface, wherein a depth of the groove relative to the upper surface
is larger than a depth of the engraved pattern relative to the upper surface;

fondling a blind via on a bottom surface of the groove to expose the lower pad;
exposing and activating some catalyst grains in the groove, the engraved pattern, and the blind via;
forming an upper wiring layer in the engraved pattern;
forming a first conductive pillar in the groove; and forming a second conductive pillar in the blind via, wherein the second
conductive pillar is connected between the first conductive pillar and the lower pad.

US Pat. No. 9,070,616

METHOD OF FABRICATING PACKAGING SUBSTRATE

Unimicron Technology Corp...

1. A method of fabricating a packaging substrate, comprising:
providing a carrier board having two opposite surfaces, on which a plurality of first conductive pads disposed for semiconductor
chips to be disposed on the first respective conductive pads;

forming first metal bumps on the first conductive pads, each of the first metal bumps having a first end and an opposite second
end, wherein the second end is disposed on one of the first conductive pads;

covering the surfaces of the carrier board, the first conductive pads and the first metal bumps with a first dielectric layer
that has a plurality of first intaglios for exposing top and side surfaces of the first ends of the first metal bumps, respectively;

forming a conductive seedlayer on the first dielectric layer and the first ends of the first metal bumps;
forming a metal layer on the conductive seedlayer;
removing a portion of the metal layer and the conductive seedlayer that is over a top surface of the first dielectric layer,
and forming a first circuit layer in the first intaglios;

forming a built-up structure on the first circuit layer and the first dielectric layer, an outermost layer of the built-up
structure having second conductive pads for an external electronic device to be disposed on the second conductive pads; and

removing the carrier board.

US Pat. No. 9,430,385

MOVEABLE LOCKED LINES IN A MULTI-LEVEL CACHE

Micron Technology, Inc., ...

1. A method comprising:
attaching a lock indication property to a cache line in a first level cache in a processor, the first cache line included
in a multi-level cache hierarchy that comprises the first level cache and a second level cache, and setting the lock indication
property to indicate that the cache line is unavailable for eviction from the multi-level cache hierarchy upon a cache miss;

evicting the cache line from the first level of the multi-level cache hierarchy to the second level cache of the multi-level
cache hierarchy;

moving the cache line from the second level cache to another level cache including the first level cache responsive to identifying
that the cache line moves from the second level cache to the other cache; and

transferring the lock indication property attached to the cache line from the first level cache to the second level cache
in the processor responsive to an eviction of the cache line from the first level cache to the second level cache, wherein
the attaching, the evicting, the moving, and the transferring are performed by the processor.

US Pat. No. 9,391,092

CIRCUIT STRUCTURES, MEMORY CIRCUITRY, AND METHODS

Micron Technology, Inc., ...

1. A circuit structure, comprising:
a substrate comprising an array region and a peripheral region; the substrate in the array and peripheral regions comprising
insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor
material over the conductive material; the array region comprising vertical circuit devices comprising the second semiconductor
material, the peripheral region comprising horizontal circuit devices comprising the second semiconductor material, amorphous
material in the array region between the insulator material and the conductive material, the amorphous material in the array
region being directly against the conductive material;

the horizontal circuit devices in the peripheral region individually comprising a floating body comprising the second semiconductor
material, the conductive material in the peripheral region being under and electrically coupled to the second semiconductor
material of the floating bodies;

conductive straps in the array region under the vertical circuit devices, the conductive straps comprising the conductive
material and individually being electrically coupled to a plurality of the vertical circuit devices in the array region; and

the second semiconductor material in the peripheral region comprising a PMOS region, the PMOS region comprising first dopant
concentration n-type material and second dopant concentration n-type material, the second dopant concentration being higher
than the first dopant concentration, the second dopant concentration n-type material being laterally discontinuous across
the floating body of the horizontal circuit devices in the PMOS region.

US Pat. No. 9,257,379

CORELESS PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME

Unimicron Technology Corp...

1. A coreless packaging substrate, comprising:
a circuit buildup structure having at least a dielectric layer, at least a wiring layer formed on the at least a dielectric
layer, and a plurality of conductive elements formed in the dielectric layer and electrically connected to the at least a
wiring layer;

a plurality of electrical pads embedded in a lowermost one of the at least a dielectric layer for electrically connecting
part of the conductive elements, wherein the electrical pads are exposed from a surface of the lowermost one of the at least
a dielectric layer;

a plurality of copper bumps formed on an uppermost one of the at least a wiring layer, and each having a copper column portion
and a copper wing portion integrally formed on the copper column portion, wherein the copper wing portion of each of the copper
bumps is greater in diameter than the copper column portion; and

a dielectric passivation layer formed on an uppermost one of the at least a dielectric layer, the uppermost one of the at
least a wiring layer, and the copper bumps, with an entire top surface of the copper wing portion of each of the copper bumps
exposed from the dielectric passivation layer,

wherein the exposed top surface of the copper wing portion of each of the copper bumps directly contacts and is electrically
connected with solder bumps of a semiconductor chip,

the dielectric passivation layer is the same in width as the uppermost one of the at least a dielectric layer, and
the copper bumps are free from protruding from the dielectric passivation layer.

US Pat. No. 9,478,502

DEVICE IDENTIFICATION ASSIGNMENT AND TOTAL DEVICE NUMBER DETECTION

Micron Technology, Inc., ...

1. An apparatus comprising N multiple dice in a stacked device, the apparatus comprising:
an assignment device included in each of at least N?1 of the N multiple dice in the stacked device to generate a sequence
of unique device identification (ID) values for at least the N?1 dice, the assignment device to operate on an input provided
by a prior one of the N multiple dice for at least the N?1 dice and generate, as an output, one of the sequence of unique
device identification (ID) values for the N multiple dice, a first of the N multiple dice not requiring a separate, external
device to generate a first in the sequence of unique device ID values, each of the N multiple dice being addressable dice;
and

an evaluation device in at least a plurality of the N multiple dice to detect a total number of the dice in the stack.

US Pat. No. 9,433,108

METHOD OF FABRICATING A CIRCUIT BOARD STRUCTURE HAVING AN EMBEDDED ELECTRONIC ELEMENT

Unimicron Technology Corp...

1. A method for fabricating a circuit board structure having at least an embedded electronic element, comprising the steps
of:
providing a substrate having opposite first and second surfaces and embedding at least an electronic element in the substrate,
wherein the electronic element has a first active surface having a plurality of first electrode pads and a second active surface
opposite to the first active surface and having a plurality of second electrode pads, the first active surface and the first
electrode pads of the electronic element being exposed from the first surface of the substrate;

forming a plurality of first conductive bumps on the first electrode pads of the electronic element; and
after the plurality of first conductive bumps are formed on the first electrode pads of the electronic element, covering the
first surface of the substrate and the first active surface of the electronic element with a first dielectric layer and a
first metal layer stacked on the first dielectric layer, wherein the first conductive bumps penetrate the first dielectric
layer so as to be in contact with the first metal layer.

US Pat. No. 9,412,472

DETERMINING SOFT DATA FROM A HARD READ

Micron Technology, Inc., ...

1. A method for determining soft data from a hard read, comprising:
determining a probability of a voltage, Vt, read from a memory cell given each of a number (NL) of state voltage distributions (VL) in the memory cell; and

computing a log-likelihood ratio (LLR) for each digit in a data value corresponding to each of the NL state voltage distributions (VL) in the memory cell based, at least partially, on a ratio of a sum of conditional probabilities of a bth digit of an Lth state being a first value versus a second value,

wherein a sign of the LLR is determined from a hard read of the memory cell.

US Pat. No. 9,230,899

PACKAGING SUBSTRATE HAVING A HOLDER, METHOD OF FABRICATING THE PACKAGING SUBSTRATE, PACKAGE STRUCTURE HAVING A HOLDER, AND METHOD OF FABRICATING THE PACKAGE STRUCTURE

Unimicron Technology Corp...

1. A packaging substrate, comprising:
a holder including an insulating layer, copper layers formed on opposite sides of the insulating layer, a dielectric layer
formed on one of the copper layers, a first metal stripping layer formed on the dielectric layer, and a second metal stripping
layer attached to the first metal stripping layer, wherein the first metal stripping layer and the second metal stripping
layer are full-sheeted and separable from each other;

a plurality of first conductive pads formed on the second metal stripping layer;
a core layer formed on the second metal stripping layer and the first conductive pads and having a first surface and a second
surface opposite to the first surface, wherein the first conductive pads are embedded in the first surface of the core layer;

a circuit layer formed on the second surface of the core layer and having a plurality of conductive vias formed in the core
layer and electrically connected to the first conductive pads, the circuit layer having a plurality of second conductive pads;
and

an insulating protection layer formed on and being in direct contact with the second surface of the core layer and the circuit
layer and having a plurality of openings, from which the second conductive pads are correspondingly exposed.

US Pat. No. 9,129,870

PACKAGE STRUCTURE HAVING EMBEDDED ELECTRONIC COMPONENT

Unimicron Technology Corp...

1. A package structure having an embedded electronic component, comprising:
a carrier having a cavity penetrating therethrough and a metal layer disposed at one side of the carrier for covering one
end of the cavity;

a semiconductor chip having opposite active and non-active surfaces and received in the cavity of the carrier with its non-active
surface attached to the metal layer, wherein the active surface of the semiconductor chip has a plurality of electrode pads
formed thereon, and each of the electrode pads has a solder bump disposed thereon;

a dielectric layer formed on the carrier and the semiconductor chip for encapsulating the solder bumps and filling up a spacing
between the semiconductor chip and the cavity of the carrier;

a wiring layer formed on the dielectric layer and having a plurality of conductive pads and a plurality of conductive vias
formed in the dielectric layer for electrically connecting the solder bumps; and

an insulating protection layer formed on the dielectric layer and the wiring layer and having a plurality of openings formed
therein for exposing the conductive pads.

US Pat. No. 9,076,528

APPARATUS INCLUDING MEMORY MANAGEMENT CONTROL CIRCUITRY AND RELATED METHODS FOR ALLOCATION OF A WRITE BLOCK CLUSTER

Micron Technology, Inc., ...

1. An apparatus, comprising:
non-volatile memory control circuitry including a plurality of channel control circuits, wherein each of the plurality of
channel control circuits is configured to be coupled to a respective number of logical units (LUNs) that each include a plurality
of blocks; and

memory management circuitry coupled to the non-volatile memory control circuitry and configured to:
allocate a write block cluster for host writes such that blocks of the write block cluster are written in a particular sequence
of LUNs, wherein the write block cluster is based on an information width of a host bus and a protocol of the host bus, and
wherein the write block cluster comprises one of the plurality of blocks from fewer than all of the LUNs; and

allocate a remainder of the plurality of blocks from the LUNs for wear leveling operations; and
temporarily deallocate at least one of the allocated LUNs from wear leveling operations at least partially in response to
the particular sequence of LUNs indicating that the at least one of the allocated LUNs is within a threshold number of LUNs
of being next in the particular sequence of LUNs for a host write, wherein the threshold number is associated with a wear
leveling read operation, a wear leveling write operation, or an erase operation.

US Pat. No. 9,514,629

VEHICLE DOOR OPENING WARNING SYSTEM AND VEHICLE DOOR OPENING WARNING METHOD

Unimicron Technology Corp...

1. A vehicle door opening warning system, comprising:
a control unit, disposed at a door of a vehicle;
a projection unit, disposed at the door and electrically coupled to the control unit; and
a detection unit, disposed outside of the vehicle, electrically coupled to the control unit, and producing a signal when the
detection unit detects a moving object existing within 5 to 30 meters of the vehicle, wherein the control unit receives the
signal and controls the projection unit to project a warning message according to the signal, wherein the projection unit
comprises:

a steering element; and
a projection lens, rotatably disposed at the door through the steering element, to turn the projection lens towards a predetermined
projection area for projecting the warning message onto the predetermined projection area.

US Pat. No. 9,444,046

THREE DIMENSIONAL MEMORY ARRAY ARCHITECTURE

Micron Technology, Inc., ...

1. A method of forming a memory array, comprising:
forming a stack comprising a plurality of first conductive lines separated from one another by insulation material;
forming a plurality of self-aligned vias through the stack between the plurality of first conductive lines;
forming cell select material within the plurality of vias;
forming storage element material within the plurality of vias;
forming a conductive extension within one of the plurality of vias; and
forming second conductive lines substantially perpendicular to the first conductive lines and the conductive extension,
wherein the conductive extension is coupled to the second conductive lines as an extension thereof.

US Pat. No. 9,340,003

MANUFACTURING METHOD OF CIRCUIT BOARD

Unimicron Technology Corp...

1. A manufacturing method of a circuit board, comprising:
providing a first core layer, a second core material layer, and a central dielectric material layer, wherein the first core
layer comprises a core dielectric layer and a core circuit layer, the core circuit layer is disposed on the core dielectric
layer and has a laser resistant pattern, the laser resistant pattern is located at a boundary of the pre-removing area, the
laser resistant pattern is a portion of the core circuit layer and is physically independent from the rest of the core circuit
layer, the second core material layer is disposed on the first core layer, and the central dielectric material layer is disposed
between the first core layer and the second core material layer;

pressing the first core layer, the second core material layer, and the central dielectric material layer to form a composite
circuit structure, wherein a pre-removing area is defined on the composite circuit structure, and at least a portion of the
core circuit layer is located within the pre-removing area;

removing a portion of the central dielectric material layer located at the boundary of the pre-removing area and a portion
of the second core material layer located at the boundary of the pre-removing area by laser etching; and

removing a portion of the central dielectric material layer located within the pre-removing area and a portion of the second
core material layer located within the pre-removing area to form a central dielectric layer and a second core layer.

US Pat. No. 9,230,895

PACKAGE SUBSTRATE AND FABRICATION METHOD THEREOF

Unimicron Technology Corp...

1. A fabrication method of a plurality of single-wiring-layer package substrates, comprising the steps of:
providing a carrier board having two opposite surfaces each having a first metal layer and a second metal layer sequentially
formed thereon;

forming a separate wiring layer on each of the second metal layers by electroplating, wherein each of the formed wiring layers
comprises solder pads, conductive pads, and circuit wires electrically connecting the solder pads and the conductive pads;

forming dielectric layers on the second metal layers and the wiring layers;
removing portions of the dielectric layers on the wiring layers so as to expose one surface of each of the wiring layers;
removing the carrier board and the first metal layers;
removing the second metal layers so as to expose the other surfaces of the wiring layers;
after the carrier board, the first metal layers, and the second metal layers are removed, forming on one surface of each of
the dielectric layers a first insulating protection layer to cover the dielectric layer and the corresponding wiring layer
to form the plurality of single-wiring-layer package substrates, and forming a plurality of first openings in the first insulating
protection layer for exposing the conductive pads, respectively; and

forming on the other surface of each of the dielectric layers a second insulating protection layer to cover the dielectric
layer and the corresponding wiring layer, and forming a plurality of second openings in the second insulating protection layer
for exposing the solder pads, respectively.

US Pat. No. 9,335,470

OPTO-ELECTRONIC CIRCUIT BOARD AND METHOD FOR ASSEMBLING THE SAME

UNIMICRON TECHNOLOGY CORP...

5. An opto-electronic circuit board, comprising:
a circuit substrate comprising:
a first circuit layer;
a first cavity disposed on the first circuit layer;
a second cavity disposed on the first circuit layer and at a side of the first cavity; and
a third cavity disposed on the first circuit layer and at a side of the first cavity opposite the second cavity;
a waveguide disposed in the first cavity and comprising:
a base disposed on the first circuit layer;
a bottom cladding layer disposed on the base;
a top cladding layer disposed on the bottom cladding layer; and
a core layer which is clad between the bottom cladding layer and the top cladding layer;
an emitting component disposed in the second cavity, wherein the emitting component comprises:
a first inserting portion inserting into the second cavity;
a first light-guide hole aligning with the core layer of the waveguide;
a first conductive layer disposed on a surface of the emitting component and opposite the waveguide with connecting to the
first circuit layer; and

a light emitter disposed on the first circuit layer, wherein the light emitter provides an optic signal aligning with the
first light-guide such that the optic signal enters to the core layer through the first light-guide hole; and

a receiving component disposed in the third cavity, wherein the receiving component comprises:
a second inserting portion inserting into the third cavity;
a second light-guide hole aligning with the core layer of the waveguide;
a second conductive layer disposed on a surface of the receiving component and opposite the waveguide with connecting to the
first circuit layer; and

a light receiver disposed on the second conductive layer and aligning with the second light-guide hole for receiving the optic
signal, wherein the optic signal passes through the core layer and enters the light receiver via the second light-guide hole.

US Pat. No. 9,295,159

METHOD FOR FABRICATING PACKAGING SUBSTRATE WITH EMBEDDED SEMICONDUCTOR COMPONENT

Unimicron Technology Corp...

1. A method for fabricating a packaging substrate with an embedded semiconductor chip, comprising the steps of:
providing a carrier board and forming an assisting layer with a plurality of apertures on the carrier board, the apertures
being filled with a filling material;

providing the semiconductor chip having an active surface with a plurality of electrode pads thereon and an opposite inactive
surface;

forming a plurality of bumps on the electrode pads, respectively, wherein the bumps correspond in position to the apertures,
respectively, and are attached to the filling material in the apertures, thereby allowing the semiconductor chip to be coupled
to the assisting layer;

filling an adhesive member between the assisting layer and the semiconductor chip so as to encapsulate the bumps and the electrode
pads;

forming a first dielectric layer on the assisting layer so as to encapsulate the semiconductor chip, the first dielectric
layer having a first surface for coupling to the assisting layer and an opposite second surface;

removing the carrier board for exposing the assisting layer;
removing the filling material and the bumps so as to form vias; and
forming in each of the vias a first conductive via for electrical connection with a corresponding one of the electrode pads.

US Pat. No. 9,232,665

METHOD OF FABRICATING PACKAGING SUBSTRATE HAVING A PASSIVE ELEMENT EMBEDDED THEREIN

Unimicron Technology Corp...

1. A method of fabricating a packaging substrate having a passive element embedded therein, comprising:
providing a carrier board having two surfaces, each of which has a release film and a metal layer sequentially;
forming positioning pads on the metal layers;
encapsulating the metal layers disposed on the two surfaces of the carrier board with a first thermalplastic dielectric layer;
providing at least a passive element having a plurality of electrode pads formed on an upper surface and a lower surface of
the passive element, and disposing the at least a passive element on the first thermalplastic dielectric layer, with the positioning
pads as positioning sites;

providing a second thermalplastic dielectric layer that is stacked above the first thermalplastic dielectric layer and the
at least a passive element;

heating and compressing the first and second thermalplastic dielectric layers, to form two dielectric layer units, each of
which has top and bottom surfaces, wherein the at least a passive element is embedded in the dielectric layer unit, and the
positioning pads are embedded in the bottom surface of the dielectric layer unit;

removing the carrier board and the release film, so as to separate the two dielectric layer units; and
forming first and second circuit layers on the top and bottom surfaces of the dielectric layer units, wherein the first circuit
layer is formed with a plurality of first conductive vias electrically connected to the electrode pads formed on the upper
surface of the at least a passive element, and the second circuit layer is formed with a plurality of second conductive vias
electrically connected to the electrode pads disposed on the lower surface of the at least a passive element.

US Pat. No. 9,224,683

METHOD OF FABRICATING PACKAGING SUBSTRATE HAVING A THROUGH-HOLED INTERPOSER

Unimicron Technology Corp...

1. A method of fabricating a packaging substrate, comprising:
providing at least a board body having opposing first and second surfaces and a protection layer formed on the first surface;
forming a plurality of through holes interconnecting the first surface and the second surface of the board body and extending
to the protection layer;

forming in the through holes a plurality of conductive gels each having opposing first and second ends;
forming on the second surface of the board body a circuit redistribution structure electrically connected to the second ends
of the conductive gels, so as to form an interposer plate including a plurality of interposers;

separating the interposer plate to obtain the plurality of interposers and removing the protection layer, to allow the first
ends of the conductive gels to protrude from the first surface of each of the interposers;

forming a encapsulating layer that encapsulates a periphery and the first surface of each of the interposers; and
forming on the encapsulating layer above the first surfaces of the interposers a circuit built-up structure electrically connected
to the first ends of the conductive gels.

US Pat. No. 9,093,459

PACKAGE STRUCTURE HAVING A SEMICONDUCTOR COMPONENT EMBEDDED THEREIN AND METHOD OF FABRICATING THE SAME

Unimicron Technology Corp...

1. A package structure having a semiconductor component embedded therein, comprising:
a first dielectric layer having a first surface and a second surface opposing the first surface;
a semiconductor chip embedded in the first dielectric layer in a manner that the semiconductor chip protrudes from the second
surface of the first dielectric layer, and having an active surface and an inactive surface opposing the active surface, in
which electrode pads are formed on the active surface and in the first dielectric layer, the inactive surface and a part of
a side surface adjacent the inactive surface protrude from the second surface of the first dielectric layer and are exposed
from the second surface of the first dielectric layer, and the inactive surface is higher than the second surface of the first
dielectric layer and exposed to outside;

a first circuit layer formed on the first surface of the first dielectric layer, with a plurality of first conductive vias
formed in the first dielectric layer for electrically connecting to the first circuit layer to the electrode pads;

a built-up structure formed on the first surface of the first dielectric layer and the first circuit layer; and
an insulating protective layer formed on the built-up structure, with a plurality of through holes formed in the insulating
protective layer for exposing a part of a surface of the built-up structure.

US Pat. No. 9,357,659

PACKAGING SUBSTRATE HAVING EMBEDDED THROUGH-VIA INTERPOSER

Unimicron Technology Corp...

1. A packaging substrate having an embedded through-via interposer, comprising:
an encapsulant layer having opposite first and second surfaces;
a through-via interposer embedded in the encapsulant layer and having opposite first and second sides and a plurality of conductive
through-vias in communication with the first and second sides, wherein each of the conductive through-vias has a first end
surface on the first side of the through-via interposer and a second end surface on the second side of the through-via interposer,
and the second side of the through-via interposer is flush with the second end surfaces of the conductive through-vias and
the second surface of the encapsulant layer;

a redistribution layer embedded in the encapsulant layer and formed on the first side of the through-via interposer and the
first end surfaces of the conductive through-vias so as to electrically connect with the first end surfaces of the conductive
through-vias, wherein the outermost layer of the redistribution layer has electrode pads, and wherein the encapsulant layer
covers the electrode pads; and

a built-up structure formed on the second surface of the encapsulant layer, the second side of the through-via interposer
and the second end surfaces of the conductive through-vias, and having at least a dielectric layer, a circuit layer embedded
in the dielectric layer and a plurality of conductive vias formed in the dielectric layer for electrically connecting with
the circuit layer, wherein portions of the conductive vias electrically connect with the second end surfaces of the conductive
through-vias, respectively.

US Pat. No. 9,337,136

METHOD OF FABRICATING A THROUGH-HOLED INTERPOSER

Unimicron Technology Corp...

1. A method of fabricating a through-holed interposer, comprising:
providing a board body having opposing first and second surfaces and first and second protection layers formed on the first
and second surfaces, respectively;

forming a plurality of through holes connecting the first surface and the second surface of the board body and extending to
the first protection layer;

forming in each of the through holes a conductive gel having opposing first and second ends;
removing the first protection layer, to allow the first end of the conductive gel to protrude from the first surface of the
board body;

forming a surface treatment layer on the first end of the conductive gel, wherein the surface treatment layer is in direct
contact with the first end of the conductive gel;

forming on the first surface of the board body and the first end of the conductive gel a first circuit redistribution structure
electrically connected to the first end of the conductive gel; and

removing the second protection layer to expose the second end of the conductive gel from the second surface of the board body.

US Pat. No. 9,362,140

PACKAGE STACK DEVICE AND FABRICATION METHOD THEREOF

Unimicron Technology Corp...

1. A package stack device, comprising:
a first package structure, comprising:
a first substrate having a first surface with a plurality of first metal posts formed thereon and a second surface opposite
to the first surface, wherein the first metal posts are copper posts, and the second surface of the first substrate has a
plurality of ball pads for mounting solder balls; and

a first electronic element disposed on the first surface of the first substrate and electrically connected to the first substrate,
wherein the first electronic element is an active component and/or a passive component, and the first electronic element is
electrically connected to the first substrate through wire bonding or in a flip-chip manner; a second package structure, comprising:

a second substrate having a third surface and a fourth surface opposite to the third surface, wherein the fourth surface has
a plurality of second metal posts which are connected to the first metal posts, respectively, so as for the second package
structure to be stacked on the first package structure, and wherein a width of end surfaces of the first metal posts is different
from a width of end surfaces of the second metal posts, the second metal posts are copper posts, and a solder material is
formed between each of the first metal posts and the corresponding second metal post; and

a second electronic element disposed on the third surface of the second substrate and electrically connected to the second
substrate; and

an encapsulant formed between the first surface of the first substrate and the fourth surface of the second substrate to encapsulate
the first electronic element, the first metal posts, and the second metal posts.

US Pat. No. 9,280,456

MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS

Micron Technology, Inc., ...

1. A method for operating a memory, comprising:
receiving an m unit data pattern to be stored in a group of N memory cells, each memory cell of the group being programmable
to L program states, wherein L is a number of program states used to store m/N units of data per memory cell;

assigning a particular one of a number of program state combinations of the group of N memory cells of the group of N memory
cells to a corresponding m unit data pattern according to a cost-based mapping;

wherein the cost-based mapping includes an associated cell frame having a length N and wherein the cost-based mapping comprises:
an index corresponding to each one of the respective number of program state combinations; and
a total cost corresponding to each one of the respective number of program state combinations, and wherein the total cost
is a sum of costs corresponding to the respective program states of the respective number of program state combinations, with
each of the L program states having a different cost corresponding thereto;

wherein, for those of the number of program state combinations having a same total cost, the index corresponding to the respective
program state combinations is based on a cost comparison between program states associated with a first portion of the cell
frame and program states associated with a second portion of the cell frame.

US Pat. No. 9,735,200

SELECT DEVICE FOR MEMORY CELL APPLICATIONS

Micron Technology, Inc., ...

1. A method of forming a memory cell of an array of memory cells, the method comprising:
forming a select device, wherein the select device includes:
a first electrode having a particular geometry;
a semiconductor material;
a second electrode having the particular geometry; and
an insulator material formed on sidewalls of the first electrode, the semiconductor material, and the second electrode; and
forming a storage element in series with the select device and the voltage buffer.

US Pat. No. 9,111,948

METHOD OF FABRICATING SEMICONDUCTOR PACKAGE STRUCTURE

Unimicron Technology Corp...

1. A fabrication method of a semiconductor package structure, comprising:
providing a carrier board having a first adhesive layer formed on a surface thereof, and, a plurality of semiconductor chips,
each of which has an active surface and an opposite inactive surface, a plurality of electrode pads formed on the active surface,
and a plurality of metal humps disposed on the electrode pads, respectively;

adhering the semiconductor chips to the first adhesive layer through the active surfaces thereof;
forming an encapsulant on the first adhesive layer to encapsulate the semiconductor chips;
providing a metal foil having a plurality of metal posts disposed on a surface thereof, and attaching the metal foil to the
encapsulant through the surface thereof such that the metal posts penetrate the encapsulant and extend to the inactive surfaces
of the semiconductor chips;

removing the carrier board and the first adhesive layer;
forming a dielectric layer on the encapsulant and the semiconductor chips, wherein the dielectric layer has a plurality of
patterned intaglios for exposing the metal bumps, respectively;

forming a wiring layer in the patterned intaglios of the dielectric layer such that the wiring layer is electrically connected
to the metal bumps;

forming an insulating protective layer on the dielectric layer and the wiring layer, wherein the insulating protective layer
has a plurality of openings for exposing portions of the wiring layer;

removing portions of the metal foil to form dicing lines such that the metal foil is separated corresponding to the semiconductor
chips; and

cutting the encapsulant, the dielectric layer and the insulating protective layer along the dicing lines of the metal foil
such that a plurality of semiconductor package structures are formed.

US Pat. No. 9,581,774

OPTICAL-ELECTRO CIRCUIT BOARD

Unimicron Technology Corp...

1. An optical-electro circuit board comprising:
a multi-layer circuit board comprising a plurality of circuit layers and a plurality of dielectric layers between the circuit
layers and having a groove extending from a surface of the multi-layer circuit board into the circuit layers;

an optical component arranged in an upside down manner and assembled into the groove of the multi-layer circuit board, the
optical component comprising:

a multi-layer substrate comprising at least one dielectric layer, at least two circuit layers, and two through holes passing
through the at least one dielectric layer, the at least two circuit layers being located on two opposite surfaces of the at
least one dielectric layer;

an optical waveguide element located on a surface of the multi-layer substrate and between the through holes, the optical
waveguide element facing a bottom of the groove; and

two optical-electro assemblies respectively inserted into the corresponding through holes and correspondingly located at two
opposite ends of the optical waveguide element, wherein one of the optical-electro assemblies transforms an electrical signal
into a light beam and provides the light beam to the optical waveguide element, and the other one of the optical-electro assemblies
receives the light beam transmitted from the optical waveguide element and transforms the light beam into another electrical
signal; and

two chips located outside the groove and electrically connected to the corresponding optical-electro assemblies, respectively,
wherein one of the chips provides the electrical signal to the corresponding optical-electro assembly, and the other one of
the chips receives the electrical signal transmitted from the other corresponding optical-electro assembly.

US Pat. No. 9,578,742

CIRCUIT BOARD STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A circuit board structure, comprising:
a first circuit layer;
a first dielectric layer disposed on the first circuit layer, wherein the first dielectric layer has at least one first hole
exposing a portion of the first circuit layer;

a second dielectric layer disposed on the first circuit layer and the first dielectric layer, wherein the second dielectric
layer has at least one trench and at least one second hole disposed in the first hole, the second hole exposing the first
circuit layer, the trench exposing the first dielectric layer;

a second circuit layer disposed in the trench; and
a conductive via disposed in the second hole without contacting the first hole, wherein a diameter of the second hole is smaller
than a diameter of the first hole, and the conductive via has a bottom surface, a top surface, and a side surface connecting
the bottom surface and the top surface.

US Pat. No. 9,635,757

CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A circuit board, comprising:
a dielectric substrate;
a circuit pattern disposed on the dielectric substrate; and
a dielectric layer, disposed on the dielectric substrate, covering the circuit pattern, and comprising a dielectric matrix
and a mesh-shaped fiber structure disposed in the dielectric matrix, wherein there is no mesh-shaped fiber structure on a
portion of the dielectric substrate exposed by the circuit pattern.

US Pat. No. 9,661,761

CARRIER SUBSTRATE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A carrier substrate, comprising:
an insulation layer having a first surface and a second surface relative to each other and a plurality of first openings extending
from the first surface to the second surface, wherein an aperture of each of the first openings gradually increases from the
first surface of the insulation layer towards the second surface;

a plurality of conductive towers disposed on the first surface of the insulation layer, each of the conductive towers having
a top surface and a bottom surface relative to each other, and a diameter of each of the conductive towers gradually increasing
from the top surface towards the bottom surface, wherein the conductive towers comprise a plurality of first conductive towers
and a plurality of second conductive towers surrounding the first conductive towers, and a diameter of the second conductive
towers is greater than a diameter of the first conductive towers, wherein all portions of a side surface of each of the conductive
towers are completely exposed; and

a circuit structure layer disposed on the second surface of the insulation layer and comprising at least one dielectric layer,
at least two circuit layers and a plurality of conductive vias, wherein the dielectric layer and the circuit layers are alternately
stacked, one of the circuit layers is disposed on the second surface of the insulation layer, the conductive vias comprise
a plurality of first conductive vias extending from the circuit layers, disposed in the first openings and extending to the
conductive towers, the conductive vias further comprise a plurality of second conductive vias passing through the dielectric
layer and electrically connecting the circuit layers, a diameter of the first conductive vias gradually increases from the
first surface of the insulation ayer towards the second surface, each of the second conductive towers correspondingly connects
to at least two of the first conductive vias, and each of the first conductive towers correspondingly connects to one of the
first conductive vias, wherein an interface exists between the first conductive vias and the first conductive towers as well
as the second conductive towers, and cross-sectional profiles of the first conductive towers and the second conductive towers
are concave shaped, and cross-sectional profiles of the first conductive vias are flat shaped.

US Pat. No. 9,281,241

METHODS FOR FORMING INTERCONNECTS IN MICROELECTRONIC WORKPIECES AND MICROELECTRONIC WORKPIECES FORMED USING SUCH METHODS

Micron Technology, Inc., ...

1. A method of processing a microelectronic workpiece including a semiconductor substrate having a plurality of microelectronic
dies, the individual dies including integrated circuitry and a terminal electrically coupled to the integrated circuitry,
the method comprising:
forming a first opening in the substrate from a back side of the substrate toward a front side of the substrate and in alignment
with the terminal, the first opening having a generally annular cross-sectional profile and separating an island of substrate
material from the substrate;

depositing an insulating material into at least a portion of the first opening, wherein depositing an insulating material
comprises at least generally filling the first opening with the insulating material and covering the entire back side of the
substrate with the insulating material;

removing at least approximately all the insulating material from the back side of the substrate outside the first opening;
applying a photosensitive polymer material directly onto the back side of the substrate;
forming a second opening in the photosensitive polymer material, wherein the second opening has a diameter less than a diameter
of the first opening, and wherein a wall of the second opening is aligned with at least a portion of the insulating material
within the first opening; and

removing the island of substrate material after depositing the insulating material and forming a third opening aligned with
at least a portion of the terminal, wherein the third opening does not extend completely through the terminal.

US Pat. No. 9,559,045

PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Unimicron Technology Corp...

1. A package structure, comprising:
a circuit board, wherein the circuit board comprises a build-up structure, second contact pads and a solder mask layer, and
the second contact pads are disposed between the build-up structure and the solder mask layer;

a supporting structure, disposed in the circuit board, wherein the supporting structure comprises a vertical supporting structure;
a first heat dissipation structure, disposed in the circuit board and between the build-up structure and the second contact
pads, wherein the first heat dissipation structure is electrically connected to the vertical supporting structure to form
an inverted U-shape structure;

a plurality of first contact pads, disposed on the circuit board;
at least one chip, disposed on one portion of the first contact pads; and
a plurality of metal pillars, disposed on the other portion of the first contact pads, wherein the metal pillars surround
the chip.

US Pat. No. 9,860,980

CIRCUIT BOARD ELEMENT

UNIMICRON TECHNOLOGY CORP...

1. A circuit board element, comprising:
a glass substrate having an edge;
a first dielectric layer disposed on the glass substrate and having a central region and an edge region, wherein the edge
region is in contact with the edge of the glass substrate, and a thickness of the central region is greater than a thickness
of the edge region;

a first patterned metal layer disposed on the glass substrate and in the central region of the first dielectric layer; and
an insulating protective layer disposed on the first patterned metal layer and the central region of the first dielectric
layer, wherein the central region of the first dielectric layer has a first side surface, the insulating protective layer
has a second side surface, and the first side surface is connected to the second side surface, and an extending line of the
first side surface and the second side surface intersects the glass substrate.

US Pat. No. 9,281,309

CROSS-HAIR CELL WORDLINE FORMATION

Micron Technology, Inc., ...

1. An access device, comprising:
a first fin and a second fin separated by trench having a first sidewall and a second sidewall;
a conductor disposed in the trench on each of the first sidewall and the second sidewall; and
a first overhanging spacer formed above the conductor on the first sidewall of the trench and a second overhanging spacer
formed on the second sidewall of the trench, wherein each of the overhanging spacers is thicker than the conductor in a direction
perpendicular from the first sidewall.

US Pat. No. 9,275,728

MEMORY CELLS, NON-VOLATILE MEMORY ARRAYS, METHODS OF OPERATING MEMORY CELLS, METHODS OF WRITING TO AND WRITING FROM A MEMORY CELL, AND METHODS OF PROGRAMMING A MEMORY CELL

Micron Technology, Inc., ...

1. A method of programming a memory cell comprising a pair of opposing conductive electrodes having resistance switchable
material received there-between, comprising:
applying an electric field through the resistance switchable material in a prevailingly laterally oriented direction to cause
mobile dopants within the resistance switchable material to move laterally toward or away from one of opposing lateral edges
of the resistance switchable material to change resistance between the pair of electrodes, the opposing conductive electrodes
of the pair being pulled to substantially the same voltage during said applying.

US Pat. No. 9,263,128

METHODS AND APPARATUSES FOR PROGRAMMING MEMORY CELLS

MICRON TECHNOLOGY, INC., ...

9. A memory device, comprising:
a memory controller configured to perform a programming operation to program a target memory cell, wherein the programming
operation comprises:

applying a programming signal to the target memory cell,
wherein the programming signal comprises a parameter which depends on a time value indicative of a most recent programming
time, and

wherein the most recent programming time is a time when a most recent programming operation was performed upon a reference
memory cell.

US Pat. No. 9,123,423

PROGRAMMING OPERATIONS IN A MEMORY DEVICE

Micron Technology, Inc., ...

1. A method for programming a memory cell, the method comprising:
storing target data into latches associated with the memory cell wherein the target data is one of data to be programmed or
data representative of a minimum programmed threshold voltage;

biasing a control gate of the memory cell with a programming pulse to program the target data; and
performing a program verify operation on the memory cell.

US Pat. No. 9,686,866

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A package structure comprising:
a circuit substrate comprising:
at least one core layer having a disposition area, a bent area surrounding the disposition area, and an upper surface and
a lower surface opposite to each other;

a build-up structure arranged on the core layer and located in the disposition area, the build-up structure comprising at
least three patterned circuit layers, at least two dielectric layers and a plurality of conductive through holes, wherein
the patterned circuit layers and the dielectric layers are alternately stacked, and the conductive through holes are electrically
connected to every two adjacent patterned circuit layers; and

a plurality of circuit pads arranged on the lower surface of the core layer and located in the bent area;
at least one electronic component embedded in at least one of the dielectric layers and located in the disposition area, wherein
the electronic component is electrically connected to one of the patterned circuit layers through a portion of the conductive
through holes; and

a connecting slot having a bottom portion, a plurality of sidewall portions connecting the bottom portion, and a plurality
of connecting pads located on the sidewall portions, wherein the circuit substrate is assembled to the bottom portion, and
the circuit pads are electrically connected to the connecting pads through the bent area of the core layer bent relative to
the disposition area.

US Pat. No. 9,230,978

SEMICONDUCTOR CONSTRUCTIONS AND NAND UNIT CELLS

Micron Technology, Inc., ...

10. A semiconductor construction, comprising:
a plurality of vertical columns comprising semiconductor material extending upwardly from a semiconductor substrate, the vertical
columns comprising alternating n-type and p-type doped layers of the semiconductor material, each vertical column spaced from
one another and comprising vertical sidewalls;

vertically stacked layers comprising electrically insulative material alternating with electrically conductive material, the
vertically stacked layers positioned between the vertical columns, a bottommost vertically stacked layer of electrically conductive
material comprising a control gate for a selecting device; and

an insulative material configuration between the vertical columns and the vertically stacked layers, the insulative material
configuration extending vertically along the vertical sidewalls of the vertical columns and along the control gate for the
selecting device.

US Pat. No. 9,293,342

PATTERNED BASES, AND PATTERNING METHODS

Micron Technology, Inc., ...

1. A method of patterning a base, comprising:
forming first masking features over a first region of the base, and forming second masking features over a second region of
the base; the first and second masking features comprising carbon-containing material and silicon oxynitride; the base being
a semiconductor base;

forming a covering over the second masking features while leaving the first masking features exposed;
removing silicon oxynitride from the first masking features while the second masking features are covered by said covering;
forming spacers along sidewalls of the first masking features;
removing the covering and the carbon-containing material of the first masking features while leaving the second masking features
remaining over the second region and while leaving the spacers remaining over the first region; and

transferring patterns of the spacers and second masking features into one or more materials of the base to pattern said one
or more materials.

US Pat. No. 9,646,852

MANUFACTURING PROCESS FOR SUBSTRATE STRUCTURE HAVING COMPONENT-DISPOSING AREA

Unimicron Technology Corp...

1. A process for a substrate having a component-disposing area, comprising:
providing a core layer, which comprises a first surface, a metallic layer and a component-disposing area, wherein the metallic
layer is disposed on the first surface;

patterning the metallic layer to form a patterned metallic layer, wherein the patterned metallic layer comprises a plurality
of pads located in the component-disposing area;

forming a first dielectric layer on the first surface, wherein the first dielectric layer covers the patterned metallic layer;
forming a laser-resistant metallic pattern on the first dielectric layer, wherein the laser-resistant metallic pattern surrounds
a projection area of the first dielectric layer which the component-disposing area is orthogonally projected on;

disposing a release film on the projection area of the first dielectric layer, wherein the release film covers a portion of
the laser-resistant metallic pattern within the projection area;

forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers the release film
and the laser-resistant metallic pattern;

forming a first open hole and a plurality of second open holes, wherein the first open hole surrounds the projection area
and penetrates through the second dielectric layer and extends to the laser-resistant metallic pattern, and the second open
holes respectively penetrate through the second dielectric layer and extend to the pads; and

making the release film separated from the first dielectric layer to form a component-disposing cavity.

US Pat. No. 9,281,466

MEMORY CELLS, SEMICONDUCTOR STRUCTURES, SEMICONDUCTOR DEVICES, AND METHODS OF FABRICATION

Micron Technology, Inc., ...

1. A memory cell, comprising:
a magnetic cell core comprising:
a magnetic region comprising a depleted magnetic material formed from a precursor magnetic material comprising at least one
diffusive species and at least one other species, the depleted magnetic material comprising the at least one other species;

another magnetic region;
an oxide region between the magnetic region and the another magnetic region; and
an amorphous region proximate to the magnetic region, the amorphous region formed from a precursor trap material comprising
at least one attracter species having at least one trap site and a chemical affinity for the at least one diffusive species
that is higher than a chemical affinity of the at least one other species for the at least one diffusive species, the amorphous
region comprising the at least one attracter species bonded to the at least one diffusive species from the precursor magnetic
material.

US Pat. No. 9,860,984

CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A manufacturing method of a circuit board structure, comprising:
providing an inner circuit structure, the inner circuit structure comprises a core layer having an upper surface and a lower
surface opposite to each other, a first patterned circuit layer disposed on the upper surface, a second patterned circuit
layer disposed on the lower surface and a conductive through hole connecting the first patterned circuit layer and the second
patterned circuit layer;

forming a metal pillar on a pad of the first patterned circuit layer;
performing a build-up process, to press a first build-up circuit structure on the first patterned circuit layer, wherein the
first build-up circuit structure at least comprises an inner dielectric layer, and the inner dielectric layer directly covers
the upper surface of the core layer and the first patterned circuit layer;

using a contact distance detector to detect an upper surface of the metal pillar relatively far away from the first patterned
circuit layer; and

using the upper surface of the metal pillar to serve as a depth reference surface, performing a hole drilling process on the
first build-up circuit structure, to remove a portion of the first build-up circuit structure and the whole metal pillar,
or remove a portion of the first build-up circuit structure and a portion of the metal pillar, so as to form a cavity extending
from a first surface of the first build-up circuit structure relatively far away from the inner circuit structure to a portion
of the inner dielectric, wherein the cavity exposes an inner surface of the inner dielectric layer, and the inner dielectric
layer has an opening connecting to the cavity, the pad is located in the opening, and a hole diameter of the opening is smaller
than a hole diameter of the cavity, and an inner surface of the inner dielectric layer exposed by the cavity and a top surface
of the pad are coplanar or have a height difference.

US Pat. No. 9,883,598

CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A method for a circuit board having a heat-recovery function, comprising:
forming at least one first via at a single-layer dielectric layer and disposing at least one first heat-conducting pillar
in the first via;

building up a plurality of buildup-dielectric layers from the single-layer dielectric layer to form a substrate;
respectively forming a first recess and a second recess on two opposite surfaces of the substrate, wherein the single-layer
dielectric layer is between the first recess and the second recess;

disposing a thermoelectric device into the first recess for embedding the thermoelectric device in the substrate, wherein
the thermoelectric device is connected to the first heat-conducting pillar;

forming at least one second via at a heat-storing device and filling the second via with at least one second heat-conducting
pillar such that the heat-storing device is penetrated by the second heat-conducting pillar;

disposing a processor on the heat-storing device, wherein the processor is connected to and in contact with the second heat-conducting
pillar; and

disposing the heat-storing device and the processor into the second recess for embedding the heat-storing device in the substrate,
wherein the heat-storing device is between the processor and the thermoelectric device.

US Pat. No. 9,854,671

CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A circuit board, comprising:
a substrate having a top surface and a bottom surface;
a first magnetic structure disposed on the top surface of the substrate;
a first dielectric layer covering the substrate and the first magnetic structure; and
an inductive coil comprising:
a first interconnect disposed on the first dielectric layer;
a second interconnect disposed on the bottom surface of the substrate; and
a plurality of conductive pillars connecting the first interconnect and the second interconnect, wherein the first interconnect,
the second interconnect and the conductive pillars form a helical structure surrounding the first magnetic structure.

US Pat. No. 9,806,050

METHOD OF FABRICATING PACKAGE STRUCTURE

Unimicron Technology Corp...

1. A method of fabricating a package structure having a semiconductor component embedded therein, comprising:
providing a core board having two opposing surfaces on which two carrier layers are formed;
forming on the carrier layers two metal layers having openings for exposing a part of surfaces of the carrier layers;
disposing on the carrier layers in the openings semiconductor chips having active surfaces and inactive surfaces opposing
the active surfaces, with electrode pads disposed on the active surfaces, the semiconductor chips combining with the carrier
layers in the openings by means of the inactive surfaces;

forming on the metal layers and the semiconductor chips first dielectric layers that have exposed first surfaces and second
surfaces combined with the metal layers;

forming first circuit layers on the first surfaces of the first dielectric layers, and forming in the first dielectric layers
a plurality of first conductive vias electrically connected to the first circuit layers and the electrode pads;

forming built-up structures on the first surfaces of the first dielectric layers and the first circuit layers;
forming insulating protective layers on the built-up structures, and forming in the insulating protective layers a plurality
of cavities for exposing a part of surfaces of the built-up structures; and

removing the core board, so as to expose the carrier layers.

US Pat. No. 9,739,963

MANUFACTURING METHOD OF OPTICAL COMPONENT

Unimicron Technology Corp...

1. A manufacturing method of an optical component, comprising:
providing a multi-layer substrate comprising at least one dielectric layer, at least two circuit layers, and two through holes
passing through the at least one dielectric layer, the at least two circuit layers being located on two opposite surfaces
of the at least one dielectric layer;

forming an optical waveguide element on a surface of the multi-layer substrate and between the through holes; and
forming two optical-electro assemblies in the corresponding through holes, the optical-electro assemblies being correspondingly
located at two opposite ends of the optical waveguide element, each of the optical-electro assemblies being formed with an
optical-electro element and an insertion element having a conductive layer disposed thereon, and the conductive layer of each
optical-electro assembly being located between a sidewall of the corresponding through hole and the insertion element of each
optical-electro assembly and being electrically connected to the optical-electro element of each optical-electro assembly.

US Pat. No. 9,913,418

PROCESS OF AN EMBEDDED COMPONENT STRUCTURE

Unimicron Technology Corp...

1. A process of an embedded component structure, comprising:
providing a wiring board, wherein electrical function of the wiring board is normal, the wiring board has a front side, a
reverse side opposite to the front side, an opening and an interconnection layer, the opening penetrates the wiring board
and connects the front side and the reverse side, and the interconnection layer is located on the front side and extends toward
the opening;

bonding a component to the wiring board, wherein electrical function of the component is normal, the component has an active
surface, a back surface opposite to the active surface, and a working area located on the active surface, the active surface
is bonded to the interconnection layer, the component is located in the opening, and the active surface and the front side
of the wiring board face in a same direction; and

filling an encapsulant into the opening, so as to cover at least the back surface and a portion of the active surface of the
component and expose the working area, wherein a portion of the encapsulant located on the back surface of the component is
flush with the reverse side of the wiring board.

US Pat. No. 9,781,843

METHOD OF FABRICATING PACKAGING SUBSTRATE HAVING EMBEDDED THROUGH-VIA INTERPOSER

Unimicron Technology Corp...

1. A method of fabricating a packaging substrate having an embedded through-via interposer, comprising the steps of:
providing a through-via interposer having opposite first and second sides and a plurality of conductive through-vias in communication
with the first and second sides, wherein each of the conductive through-vias has a first end surface on the first side of
the through-via interposer and a second end surface on the second side of the through-via interposer, and the second end surfaces
of the conductive through-vias protrude below the second side of the through-via interposer to serve as conductive bumps;

forming a redistribution layer on the first side of the through-via interposer and the first end surfaces of the conductive
through-vias such that the redistribution layer electrically connect with the first end surfaces of the conductive through-vias,
wherein an outermost layer of the redistribution layer has electrode pads;

forming an encapsulant layer to encapsulate and embed the through-via interposer, wherein the encapsulant layer has opposite
first and second surfaces, the second side of the through-via interposer is exposed from the second surface of the encapsulant
layer, the conductive bumps protrude below the second surface of the encapsulant layer, and the encapsulant layer covers the
redistribution layer and the electrode pads;

forming a built-up structure on the second surface of the encapsulant layer, the second side of the through-via interposer
and the conductive bumps, wherein the built-up structure has at least a dielectric layer, a circuit layer formed on the dielectric
layer, and a plurality of conductive vias formed in the dielectric layer for electrically connecting with the circuit layer,
wherein portions of the conductive vias electrically connect with the conductive bumps, respectively, and

decreasing a thickness of the encapsulant layer from the first surface of the encapsulant layer so as to expose the electrode
pads from the first surface of the encapsulant layer.

US Pat. No. 9,805,875

CAPACITOR AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A capacitor, comprising:
a porous substrate having a plurality of holes;
an electrolyte composition located in the holes of the porous substrate, the electrolyte composition comprising an electrolyte
solution and a nano carbon material dispersed in the electrolyte solution; and

a pair of electrodes respectively located on two opposite surfaces of the porous substrate.

US Pat. No. 9,148,172

DATA COMPRESSION AND MANAGEMENT

Micron Technology, Inc., ...

1. A method for operating a memory, the method comprising:
receiving a number of data segments corresponding to a managed unit amount of data;
determining a respective compressibility of each of the number of data segments;
compressing each of the number of data segments in accordance with its respective determined compressibility;
forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of
data segments corresponding to the managed unit amount of data;

wherein forming the compressed managed unit includes determining a compression value for the compressed managed unit, the
compression value indicating an amount of space allotted to each of the compressed and/or uncompressed data segments; and

wherein determining the compression value includes:
determining a compression level for each data segment of the number of data segments, the compression level indicating the
respective compressibility of the respective data segments; and

determining a least compressible of the number of data segments of the compressed managed unit;
allotting a same amount of space within the compressed managed unit to each of the compressed and/or uncompressed data segments
such that the amount of space allotted to each of the compressed and/or uncompressed data segments is independent of a size
of the respective compressed and/or uncompressed data segment, wherein the same amount of space allotted to each of the compressed
and/or uncompressed data segments is an uppermost compressed segment size corresponding to the determined compression level
of the least compressible of the number of data segments; and

forming a page of data that comprises at least the compressed managed unit.

US Pat. No. 9,286,161

MEMORY SYSTEM AND METHOD USING PARTIAL ECC TO ACHIEVE LOW POWER REFRESH AND FAST ACCESS TO DATA

Micron Technology, Inc., ...

1. A method comprising:
while in a first mode:
refreshing a first set of memory cells of an array of a semiconductor device at a first rate, wherein a first type of data
is stored in the first set of memory cells;

refreshing a second set of memory cells of the array at a second rate that is greater than the first rate, wherein a second
type of data is stored in the second set of memory cells; and

correcting errors in the first type of data stored at the first set of the memory cells; and
while in a second mode:
refreshing the first set of memory cells and the second set of memory cells at the second rate.

US Pat. No. 9,195,406

OPERATION MANAGEMENT IN A MEMORY DEVICE

Micron Technology, Inc., ...

1. A method of operating a memory device, the method comprising:
performing a first memory operation within a first time frame associated with the first memory operation;
if a length of time to perform a first portion of a second memory operation is deemed to be less than or equal to a length
of time between completion of the first memory operation and expiration of the first time frame, performing the first portion
of the second memory operation subsequent to completing the first memory device operation and within the first time frame;

updating a status corresponding to the second memory operation responsive to performing the first portion of the second memory
operation;

performing a third memory operation within a second time frame associated with the third memory operation and subsequent to
the first time frame; and

if a length of time to perform a second portion of the second memory operation is deemed to be less than or equal to a length
of time between completion of the third memory operation and expiration of the second time frame, performing the second portion
of the second memory operation subsequent to completing the third memory device operation and within the second time frame.

US Pat. No. 9,859,130

MANUFACTURING METHOD OF INTERPOSED SUBSTRATE

Unimicron Technology Corp...

1. A manufacturing method of an interposed substrate comprising:
providing a metal carrier;
forming a photoresist layer on the metal carrier, wherein the photoresist layer has a plurality of openings, and a portion
of the metal carrier is exposed by the openings;

forming a plurality of metal passivation pads in the plurality of openings of the photoresist layer, wherein the plurality
of metal passivation pads cover the portion of the metal carrier exposed by the plurality of openings;

forming a plurality of conductive pillars in the plurality of openings of the photoresist layer, wherein the plurality of
conductive pillars are respectively stacked on the plurality of metal passivation pads, and a thickness of each of the plurality
of conductive pillars is at least twice the thickness of each of the plurality of metal passivation pads;

removing the photoresist layer to expose another portion of the metal carrier;
forming an insulating material layer on the metal carrier, wherein the insulating material layer covers the another portion
of the metal carrier and encapsulates the plurality of conductive pillars and the plurality of metal passivation pads; and

removing the metal carrier to expose a lower surface opposite to an upper surface of the insulating material layer.

US Pat. No. 9,831,103

MANUFACTURING METHOD OF INTERPOSED SUBSTRATE

Unimicron Technology Corp...

1. A manufacturing method of an interposed substrate comprising:
forming a metal-stacked layer, wherein the metal-stacked layer comprises a first metal layer, an etching stop layer and a
second metal layer, the etching stop layer is disposed between the first metal layer and the second metal layer, and a thickness
of the second metal layer is greater than a thickness of the first metal layer;

forming a patterned conductor layer on the first metal layer, wherein the patterned conductor layer exposes a portion of the
first metal layer;

forming a plurality of conductive pillars on the patterned conductor layer, wherein the conductive pillars are separated from
each other and stacked on a portion of the patterned conductor layer;

forming an insulating material layer on the metal-stacked layer, the insulating material layer having an upper surface and
a lower surface opposite to each other, wherein the insulating material layer covers the portion of the first metal layer
and encapsulates the conductive pillars and the other portion of the patterned conductor layer;

forming a dielectric layer on the insulating material layer, wherein the dielectric layer covers the upper surface of the
insulating material layer and a top surface of each conductive pillar; and

removing the metal-stacked layer to expose the lower surface of the insulating material layer and a bottom surface of the
patterned conductor layer.

US Pat. No. 9,775,246

CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A circuit board, comprising:
a substrate, having a first surface and a first circuit layer, wherein the first surface has a chip disposing area and an
electrical connection area, and the first circuit layer is embedded in the first surface;

a photo imageable dielectric layer, disposed on the electrical connection area and having a plurality of openings, wherein
the openings expose parts of the first circuit layer, and the photo imageable dielectric layer exposes the chip disposing
area; and

a plurality of conductive bumps, respectively disposed at the openings, and connected to the first circuit layer, wherein
the photo imageable dielectric layer covers at least a part of a side surface of each of the conductive bumps.

US Pat. No. 9,281,471

PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS

Micron Technology, Inc., ...

1. A method for fabricating a memory stack, the method comprising:
forming the memory stack out of a plurality of elements;
forming an adhesion species on at least one sidewall of the memory stack using a plasma doping process; and
forming a sidewall liner on the at least one sidewall of the memory stack such that the adhesion species intermixes with an
element of the memory stack and the sidewall liner.

US Pat. No. 9,883,579

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A package structure, comprising:
a circuit substrate, comprising:
a core layer having a first surface and a second surface opposite to each other;
a plurality of electronic devices embedded in the core layer, wherein each of the electronic devices has an active surface
and a back surface opposite to each other, and the active surfaces of two adjacent electronic devices respectively face the
first surface and the second surface of the core layer; and

a conducting unit disposed on the first surface and the second surface of the core layer and extended to the electronic devices
and electrically connected to the electronic devices;

a first build-up circuit structure disposed on the first surface of the core layer and having at least one first opening;
a second build-up circuit structure disposed on the second surface of the core layer and having at least one second opening,
wherein the first opening and the second opening expose a portion of the conducting unit; and

a plurality of piezoelectric heat dissipation units disposed on the conducting unit exposed by the first opening and the second
opening and respectively corresponding to the active surfaces of the electronic devices, wherein the piezoelectric heat dissipation
units are electrically connected to the conducting unit exposed by the first opening and the second opening.

US Pat. No. 9,691,699

CIRCUIT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Unimicron Technology Corp...

1. A method for manufacturing a circuit structure, comprising:
forming two patterned circuit layers on a core layer, wherein the patterned circuit layers are located respectively on two
opposite surfaces of the core layer;

forming a patterned insulating layer respectively on each of the patterned circuit layers, wherein the patterned insulating
layers respectively expose a portion of the patterned circuit layers;

providing two support plates respectively bonded on the patterned insulating layers wherein each of the support plates, each
of the patterned insulating layers and each of the patterned circuit layers define a plurality of air gaps; and

after providing the two support plates, removing the core layer so as to expose an upper surface of each of the patterned
circuit layers and a top surface of each of the patterned insulating layers, wherein the upper surface of each of the patterned
circuit layers is aligned with the top surface of each of the patterned insulating layers.

US Pat. No. 9,130,793

CONSTANT DELAY ZERO STANDBY DIFFERENTIAL LOGIC RECEIVER AND METHOD

Micron Technology, Inc., ...

1. A receiver circuit comprising a first pass circuit having at least two transistors, the at least two transistors having
respective gate terminals connected together and to a first node of a differential transmission line and respective source
terminals connected together and to a second node of the differential transmission line, an output of the first pass circuit
connected to respective drain terminals and providing a first output signal.

US Pat. No. 9,832,873

CIRCUIT BOARD STRUCTURE

Unimicron Technology Corp...

1. A circuit board structure, comprising:
an inner circuit structure, comprising a core layer having an upper surface and a lower surface opposite to each other, a
first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface,
and a conductive through hole connecting the first patterned circuit layer and the second patterned circuit layer; and

a first build-up circuit structure, disposed on the upper surface of the core layer and covering the first patterned circuit
layer, wherein the first build-up circuit structure at least has a cavity and an inner dielectric layer, the cavity exposes
a portion of the inner dielectric layer, and the inner dielectric layer directly covers the upper surface of the core layer
and the first patterned circuit layer, the inner dielectric layer has a first portion with a first thickness, and a second
portion with a second thickness exposed by the cavity, wherein the second thickness is thinner than the first thickness, the
inner dielectric layer has an opening connecting the cavity and exposing a portion of the first patterned circuit layer, a
hole diameter of the opening is smaller than a hole diameter of the cavity, and a top surface of the first patterned circuit
layer exposed by the opening is not higher than an inner surface of the inner dielectric layer exposed by the cavity.

US Pat. No. 9,269,450

METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES

Micron Technology, Inc., ...

1. A method for operating a device, comprising:
determining a quantity of a number of memory cells having a threshold voltage greater than a particular voltage;
wherein the quantity is determined by performing a sense operation on the number of memory cells using the particular voltage;
and

adjusting a sensing voltage used to determine a state of the number of memory cells based, at least partially, on a comparison
of the determined quantity to a stored value, wherein the stored value corresponds to a quantity of the number of memory cells
programmed to a threshold voltage within a threshold voltage distribution corresponding to a programmed state of the number
of memory cells.

US Pat. No. 9,281,682

APPARATUSES AND METHOD FOR OVER-VOLTAGE EVENT PROTECTION

Micron Technology, Inc., ...

1. An apparatus, comprising:
a thyristor coupled to a node and configured to discharge current associated with an over-voltage event at the node, wherein
the over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor;

a first transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage; and
a second transistor coupled to the first transistor, wherein the second transistor is a lateral BJT merged with the first
transistor and wherein the first transistor and the second transistor share at least two conductive regions.

US Pat. No. 9,123,409

MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE

Micron Technology, Inc., ...

1. A hierarchical memory device, comprising:
a Phase Change Memory (PCM) array;
multiple interfaces having different memory formats, the multiple interfaces including a NAND interface and a mass storage
device interface;

at least one processor core to perform multi-core NAND management and autonomous computing functions, the NAND management
functions being configured to adjust data input/output between the NAND interface and a buffer memory coupled to the NAND
interface based on extracted control and operational information including received command sets and addresses of memory devices
coupled to the hierarchical memory device, the at least one processor further to interpret the received command sets and issue
memory commands; and

at least one input port and a plurality of output ports such that the hierarchical memory device is simultaneously connectable
in both a daisy-chain hierarchy and a hierarchical tree structure with other hierarchical memory devices and to switch traffic
between the at least one input port and one of the plurality of output ports to reduce round-trip latency to a lowest layer
of the hierarchical tree structure, the plurality of output ports configured to communicatively couple to at least one NAND
memory external to the hierarchical memory device, the NAND interface configured to control communications between the PCM
array and the at least one NAND memory such that the PCM array can cache data received from the at least one NAND memory,
the at least one input port and the plurality of output ports being configurable by the at least one processor core.

US Pat. No. 9,287,240

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH THERMAL SPACERS AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A semiconductor die assembly, comprising:
a thermally conductive casing having a sidewall, wherein thermally conductive casing defines a cavity;
a stack of first semiconductor dies within the cavity;
a second semiconductor die mechanically and electrically coupled to the stack of first dies, the second semiconductor die
having a face facing the toward the stack of first semiconductor dies, wherein the sidewall of the thermally conductive casing
is attached directly to the face of the second semiconductor die by a thermal adhesive;

a package substrate carrying the second semiconductor die; and
a thermal spacer disposed between the package substrate and the thermally conductive casing, wherein the thermal spacer includes
a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically
coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.

US Pat. No. 9,859,159

INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. An interconnection structure, comprising:
a substrate having a first surface and a second surface opposite to each other;
a conductive through via disposed in the substrate and extended from the first surface beyond the second surface;
a dielectric layer disposed on the substrate, wherein the dielectric layer has an opening exposing a portion of the conductive
through via, and a top surface of the conductive through via protrudes from a bottom surface of the opening; and

a conductive layer disposed in the opening and in contact with the top surface and a portion of a side surface of the conductive
through via, wherein the conductive layer comprises a seed layer and a conductive material layer, and top surfaces of the
seed layer and the conductive material layer are respectively aligned with a top surface of the dielectric layer.

US Pat. No. 9,281,037

MEMORY DEVICE COMMAND DECODING SYSTEM AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME

Micron Technology, Inc., ...

1. A method of decoding received command signals in a memory device, the method comprising:
decoding the received command signals in combination with at least one address signal provided to a memory address node at
a first clock edge of a clock signal to generate a plurality of memory control signals,

wherein the received command signals in combination with the at least one address signal provided to the memory address node
at the first clock edge of the clock signal represents a memory command, and

wherein a plurality of commands are grouped together and assigned a same combination of command signals, the plurality of
commands differentiated from each other by the at least one address signal provided to the memory address node.

US Pat. No. 9,112,138

METHODS OF FORMING RESISTIVE MEMORY ELEMENTS

Micron Technology, Inc., ...

1. A method of forming a resistive memory element, comprising:
forming an oxide material extending continuously over a first electrode;
exposing the oxide material to a decoupled plasma nitridation process to form a treated oxide material extending continuously
over the first electrode, the treated oxide material comprising at least one of a hafnium oxy-nitride, a hafnium silicon oxy-nitride,
a zirconium oxy-nitride, a zirconium silicon oxy-nitride, a titanium oxy-nitride, a titanium silicon oxy-nitride, a tantalum
oxy-nitride, a tantalum silicon oxy-nitride, a niobium oxy-nitride, a niobium silicon oxy-nitride, a vanadium oxy-nitride,
a vanadium silicon oxy-nitride, a tungsten oxy-nitride, a tungsten silicon oxy-nitride, a molybdenum oxy-nitride, a molybdenum
silicon oxy-nitride, a chromium oxy-nitride, and a chromium silicon oxy-nitride; and

forming a second electrode on the treated oxide material.

US Pat. No. 9,293,191

APPARATUSES AND METHODS FOR MULTI-MEMORY ARRAY ACCESSES

Micron Technology, Inc., ...

1. An apparatus, comprising:
a pair of input/output lines;
a first array coupled to the pair of input/output lines, the first array configured to provide data to and receive data from
the pair of input/output lines;

an access block coupled to the pair of input/output lines, the access block configured to access a second array responsive
to memory access control signals directed to the second array, wherein the access block is configured provide data between
the second array and the pair of input/output lines responsive to the access of the second array, wherein the access block
comprises a write driver configured to provide write data received via the pair of input/output lines to a second pair of
input/output lines coupled to the second array.

US Pat. No. 9,130,164

RESISTIVE RANDOM ACCESS MEMORY DEVICES, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES

MICRON TECHNOLOGY, INC., ...

8. A semiconductor device structure, comprising:
a first insulator material over a substrate;
a first electrode over the first insulator material;
a second insulator material over the first electrode;
a metal-doped chalcogenide material within an opening in the second insulator material, the metal-doped chalcogenide material
substantially free of carbon, nitrogen, and silicon, and comprising germanium, sulfur, and a metal;

a chalcogenide material comprising germanium sulfide over the metal-doped chalcogenide material; and
a second electrode over the chalcogenide material.

US Pat. No. 9,236,270

HIGH RESOLUTION PRINTING TECHNIQUE

MICRON TECHNOLOGY, INC., ...

1. A method for semiconductor processing, comprising:
forming a self-assembling monolayer over a semiconductor substrate;
directly contacting the monolayer with an array of spaced-apart tips attached to probes, wherein directly contacting converts
a chemical species in the monolayer to an other chemical species;

selectively removing one of the chemical species or the other chemical species to form a pattern in the monolayer.

US Pat. No. 9,230,658

METHOD OF STORING DATA ON A FLASH MEMORY DEVICE

MICRON TECHNOLOGY, INC., ...

1. A method of arranging data within a block of a non-volatile memory device, wherein the block comprises word lines each
electrically coupled to memory cells configured to store data, the word lines comprising one or more first end word lines,
one or more second end word lines, and intermediate word lines between the first and second end word lines, wherein the first
end word lines and second end word lines are disposed at opposing ends of the block, the method comprising:
programming the memory cells electrically coupled to the intermediate word lines; and
programming the memory cells electrically coupled to the one or more first end word lines and the memory cells electrically
coupled to the one or more second end word lines,

wherein, when less than the entire memory block is programmed with data during operation of the non-volatile memory device,
data is programmed to the memory cells electrically coupled to the intermediate word lines more frequently than to the memory
cells electrically coupled to the one or more first end word lines and more frequently than to the memory cells electrically
coupled to the one or more second end word lines.

US Pat. No. 9,306,165

REPLACEMENT MATERIALS PROCESSES FOR FORMING CROSS POINT MEMORY

MICRON TECHNOLOGY, INC., ...

1. A method of forming a memory cell, comprising:
providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower
conductive line; and

forming a chalcogenide line extending in the first direction by selectively removing sacrificial material of the sacrificial
line and replacing the removed sacrificial material with a stack of materials including a chalcogenide material and another
material.

US Pat. No. 9,237,629

ORGANIC EL DISPLAY PANEL FOR REDUCING RESISTANCE OF ELECTRODE LINES

MICRON TECHNOLOGY LICENSI...

1. An organic EL display comprising:
a substrate having an EL region;
an anode on the EL region of the substrate;
a first supplementary electrode coupled to a portion of the anode;
an insulating layer provided in regions other than the EL region;
a second supplementary electrode on the insulating layer;
an organic EL layer on the EL region;
a cathode on the organic EL layer; and
a plurality of pads on the substrate at a location adjacent an outermost one of the anodes, wherein:
the anode includes at least indium tin oxide (ITO), and the first supplementary electrode includes at least Ag,
the insulating layer includes a first projection part and a second projection part, the first projection part projecting between
adjacent ones of the pads, and the second projection part being at a corner area of the EL region and extending from a first
side of the EL region toward an interior area of the EL region and extending from a second side of the EL region toward the
interior area of the EL region, and

the second supplementary electrode includes a first supplementary projection part and a second supplementary projection part,
the first supplementary projection part being on the first projection part of the insulating layer, and the second supplementary
projection part being on the second projection part of the insulating layer at the corner area of the EL region.

US Pat. No. 9,136,017

SHORT-CHECKING METHODS

Micron Technology, Inc., ...

28. A memory device, comprising:
an array of memory cells; and
a controller coupled to the array of memory cells;
wherein the controller is configured to cause a data line to be charged to an initial voltage while activating a memory cell
coupled to the data line;

wherein the controller is configured to cause the data line to be allowed to float after the data line is charged to the initial
voltage and while continuing to activate the memory cell;

wherein the controller is configured to cause a resulting voltage on the data line to be sensed after a certain time; and
wherein the controller is configured to determine whether a short exists in response to a level of the resulting voltage.

US Pat. No. 9,111,798

MEMORY WITH CARBON-CONTAINING SILICON CHANNEL

Micron Technology, Inc., ...

1. A memory, comprising:
a first memory cell; and
a second memory cell formed over the first memory cell;
wherein each of the first memory cell and the second memory cell comprises:
a channel region comprising silicon and carbon;
a control gate; and
a dielectric stack between the channel region and the control gate;
wherein a carbon concentration of the channel region of the second memory cell is less than a carbon concentration of the
channel region of the first memory cell.

US Pat. No. 9,974,166

CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A circuit board, comprising:a substrate, having a first surface and a second surface opposite to each other;
a patterned circuit layer, embedded in the first surface, and a line width of the patterned circuit layer gradually reducing from the first surface towards the second surface;
a patterned photo-imaginable dielectric layer, embedded in the substrate corresponding to the patterned circuit layer; and
a first surface finish layer, exposed on the second surface and only covering a bottom surface of a part of the patterned circuit layer.

US Pat. No. 9,425,190

TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE

MICRON TECHNOLOGY, INC., ...

1. A direct injection semiconductor memory device comprising:
a first region coupled to a bit line;
a second region coupled to a source line;
a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating
and disposed between the first region and the second region, wherein the first region, the body region, the second region
are arranged in a sequential contiguous manner; and

a substrate coupled to a carrier injection line, wherein the second region is disposed directly on the substrate, and wherein
the body region is disposed directly on the second region opposite the substrate.

US Pat. No. 9,318,699

RESISTIVE MEMORY CELL STRUCTURES AND METHODS

Micron Technology, Inc., ...

1. A method of forming an array of resistive memory cells, the method comprising:
forming a first number of resistive memory cells in a first region of the array and a second number of resistive memory cells
in a second region of the array; and

modifying an electrothermal property of a resistance variable material in at least one of the first region of the array and
the second region of the array,

wherein modifying the electrothermal property of the resistance variable material in the at least one of the first and second
regions includes thermal activation to modify the electrothermal properties of the resistance variable material in the first
and second regions of the array.

US Pat. No. 9,318,199

PARTIAL PAGE MEMORY OPERATIONS

Micron Technology, Inc., ...

1. An apparatus comprising a memory block, the memory block comprising:
strings of memory cells formed in a plurality of tiers;
access lines shared by the strings, each access line coupled to the memory cells corresponding to a respective tier of the
plurality of tiers, the memory cells corresponding to at least a portion of the respective tier comprising a respective page
of a plurality of pages; and

data lines shared by the strings, the data lines comprising a plurality of subsets of data lines, each subset of data lines
being mapped into a respective partial page of a plurality of partial pages of the respective page, each partial page independently
selectable from other partial pages within the respective page, wherein a particular page of the plurality of pages includes
a first partial page and a second partial page, memory cells corresponding to the first partial page are coupled to a particular
access line of the access line via a first string driver, and memory cells corresponding to the second partial page are coupled
to the particular access line via a second string driver.

US Pat. No. 9,310,552

METHODS AND APPARATUS PROVIDING THERMAL ISOLATION OF PHOTONIC DEVICES

Micron Technology, Inc., ...

1. An integrated structure comprising:
a substrate having an upper surface;
a first trench formed in the upper surface of the substrate;
a device formation region over the upper surface of the substrate;
a first temperature-sensitive photonic device formed in the device formation region;
a waveguide formed in the device formation region and separated from the trench by a portion of the substrate;
a heating device formed in the device formation region for heating the first temperature-sensitive photonic device, wherein
the heating device is located over the first trench; and

a first thermal isolation region formed under the heating device, wherein the first thermal isolation region is located in
the first trench, such that the first thermal isolation region is provided in the upper surface of the substrate, and wherein
the first thermal isolation region reduces dissipation of heat from the heating device into the substrate.

US Pat. No. 9,184,377

RESISTANCE VARIABLE MEMORY CELL STRUCTURES AND METHODS

Micron Technology, Inc., ...

1. An array of resistance variable memory cells, comprising:
a first resistance variable memory cell comprising a number of resistance variable materials in a super-lattice structure;
and

a second resistance variable memory cell comprising the number of resistance variable materials in a homogeneous structure.

US Pat. No. 9,159,375

SELECTIVELY CONDUCTING DEVICES, DIODE CONSTRUCTIONS, METHODS OF FORMING DIODES AND METHODS OF CURRENT MODULATION

Micron Technology, Inc., ...

1. A selectively conducting device comprising:
a first electrode comprising a first metal-comprising material having a first work function;
a second electrode comprising a second metal comprising material comprising a second work function, the first and second work
functions being non-equivalent; and

a plurality of at least three stacked un-doped dielectric materials between the first and second electrodes being configured
to conduct current from the first electrode to the second electrode when a first voltage is applied across the first electrode
and the second electrode and being configured to inhibit current from flowing from the second electrode to the first electrode
when a second voltage having a polarity opposite that of a polarity of the first voltage is applied across the first electrode
and the second electrode, each of the plurality of at least three stacked un-doped dielectric materials having a barrier height
that is higher than the first and the second work functions, the plurality of at least three stacked un-doped dielectric materials
having a barrier height greater than both a work function of the first metal and a work function of the second metal, the
plurality of at least three stacked un-doped dielectric materials being physically arranged between the first electrode and
the second electrode in order of increasing barrier height, a first dielectric material of the plurality of at least three
stacked un-doped dielectric materials nearest the second electrode having the lowest barrier height of the plurality of at
least three stacked un-doped dielectric materials and a second material of the plurality of at least three stacked un-doped
dielectric materials nearest the first electrode having the highest barrier height of the plurality of at least three stacked
un-doped dielectric materials.

US Pat. No. 9,159,662

SEMICONDUCTOR STRUCTURES HAVING ADHESION PROMOTING LAYER IN CAVITIES

Micron Technology, Inc., ...

1. A semiconductor structure comprising:
a substrate;
a dielectric layer over the substrate;
a cavity formed in the dielectric layer, the cavity having a bottom portion and an upper sidewall portion;
a conformal lining in the cavity, the conformal lining covering the bottom portion of the cavity while leaving the upper sidewall
portion of the cavity uncovered by the conformal lining, wherein the conformal lining includes a metal;

a conformal nucleation layer over the conformal lining that leaves the upper sidewall portion of the cavity uncovered by the
conformal nucleation layer, wherein the conformal nucleation layer includes a metal; and

a cavity filling material having a top surface that extends over and across the cavity,
wherein the cavity filling material is a single layer that directly contacts the upper sidewall portion and the conformal
nucleation layer.

US Pat. No. 9,116,837

PINNING CONTENT IN NONVOLATILE MEMORY

Micron Technology, Inc., ...

1. A method comprising:
displaying at a graphical user interface (GUI) hit statistics and miss statistics corresponding to pinnable sectors that may
be pinned or unpinned by a user in a non-volatile memory (NVM) drive, wherein hit statistics correspond to pinned sectors
in the NVM drive and miss statistics correspond to sectors not pinned in the NVM drive;

receiving a list of files selected by the user to be pinned or unpinned in the NVM drive, wherein the list of files is selected
by the user after displaying the hit statistics and miss statistics;

mapping the list of files to a list of disk sectors that are to be pinned or unpinned in the NVM drive; and
pinning or unpinning the pinnable sectors in the NVM drive corresponding to the list of disk sectors.

US Pat. No. 10,123,418

CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A circuit board structure, comprising:an insulating layer, comprising a first conductive through hole, a first surface, and a second surface opposite to the first surface, the first conductive through hole penetrating the insulating layer to connect the first surface and the second surface;
a first dielectric layer, disposed on the first surface;
a first inductor, disposed on the first surface of the insulating layer and electrically connecting the first conductive through hole, the first inductor comprising a first conductive coil and a first magnetic flux axis, wherein the first conductive coil in a solenoid form penetrates the first dielectric layer, and a direction of the first magnetic flux axis is substantially parallel to the first surface;
a second dielectric layer disposed on the second surface; and
a second inductor, located on the second surface of the insulating layer and electrically connecting the first conductive through hole, the second inductor comprising a second conductive coil and a second magnetic flux axis, wherein the second conductive coil in a solenoid form penetrates the second dielectric layer, and a direction of the second magnetic flux axis is substantially parallel to the second surface.

US Pat. No. 9,449,652

SYSTEMS AND DEVICES INCLUDING MULTI-TRANSISTOR CELLS AND METHODS OF USING, MAKING, AND OPERATING THE SAME

Micron Technology, Inc., ...

1. A device, comprising:
a plurality of data cells, wherein each data cell comprises:
a first transistor comprising:
a column gate; and
a first channel;
a second transistor comprising:
a row gate, wherein the row gate crosses over the column gate, under the column gate, or both;
a source disposed near a distal end of a first leg;
a drain disposed near a distal end of a second leg, wherein the column gate extends between the first leg and the second leg;
a second channel, wherein the second channel of the second transistor is connected to the first channel of the first transistor;
and

a data element connected to the source or the drain.

US Pat. No. 9,306,518

VOLTAGE REGULATORS, AMPLIFIERS, MEMORY DEVICES AND METHODS

Micron Technology, Inc., ...

14. A circuit, comprising:
an amplifier circuit to provide an output voltage based, at least in part, on a feedback signal; and
a feedback path to provide the feedback signal, the feedback path configured to isolate an upstream node of the feedback path
from a downstream node of the feedback path, wherein the isolation is in one direction.

US Pat. No. 9,159,383

SIGNAL MANAGEMENT IN A MEMORY DEVICE

Micron Technology, Inc., ...

1. A method of operating a memory device having an array of memory cells, the method comprising:
performing a first memory device operation on the array of memory cells responsive to control circuitry of the memory device
receiving a first command signal from an interface of the memory device; and

inhibiting a second command signal from being received by the control circuitry prior to the control circuitry completing
the first memory device operation.

US Pat. No. 9,159,731

METHODS OF FORMING CAPACITORS AND SEMICONDUCTOR DEVICES INCLUDING A RUTILE TITANIUM DIOXIDE MATERIAL

Micron Technology, Inc., ...

1. A method of forming a capacitor, comprising:
forming a titanium nitride material within at least one aperture defined by a support material;
forming a ruthenium material over the titanium nitride material within the at least one aperture;
forming a first conductive material over the ruthenium material within the at least one aperture;
oxidizing the titanium nitride material to a titanium dioxide material; and
forming a second conductive material over a surface of the titanium dioxide material.

US Pat. No. 10,026,680

SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

Micron Technology, Inc., ...

1. A method for fabricating a semiconductor device, comprising:forming a first redistribution layer (RDL) structure on a polish stop material on a first carrier;
subjecting the first RDL structure and the first carrier to a first singulation process to separate individual interconnect components from one another;
rearranging and mounting the individual interconnect components onto a second carrier;
forming a molding compound covering the individual interconnect components;
removing the second carrier to expose a surface of the first RDL structure of each of the individual interconnect components;
forming a second RDL structure on the exposed surface of the first RDL structure and on the molding compound;
forming first connecting elements on the second RDL structure;
bonding the first connecting elements to a third carrier;
grinding the molding compound and the first carrier;
completely removing a remaining portion of the first carrier to form a recess to expose the polish stop material;
polishing the molding compound such that a top surface of the polish stop material is coplanar with a top surface of the molding compound;
forming openings in the polish stop material; and
forming second connecting elements in the openings respectively.

US Pat. No. 9,900,997

MANUFACTURING METHOD OF A RIGID FLEX BOARD MODULE

Unimicron Technology Corp...

1. A manufacturing method for a rigid flex board module, comprising:
providing a rigid flex initial substrate including a flexible circuit board, a pair of release layers, a first rigid substrate,
and a first insulating layer;

wherein the flexible circuit board having a bending portion and a jointing portion connected to the bending portion, the pair
of release layers respectively disposed on two sides of the flexible circuit board covering the bending portion, the first
rigid substrate arranged above the flexible circuit board and the pair of release layers, the first rigid substrate covering
the bending portion and the jointing portion, and the first insulating layer connected between the first rigid substrate and
the flexible circuit board;

forming a pair of first openings on the rigid flex initial substrate to expose the bending portion;
forming a second opening through the rigid flex initial substrate, the first rigid substrate and the first insulating layer;
disposing a high-density interconnected circuit layer in the second opening;
forming a pair of multi-layer circuit layers on two sides of the rigid flex initial substrate and covering two sides of the
high-density interconnected circuit layer and the rigid flex initial substrate; and

forming a plurality of conductive posts such that the multi-layer circuit layers, the high-density interconnected circuit
layer, and the rigid flex initial substrate are electrically connected to each other.

US Pat. No. 9,305,938

METHODS OF FABRICATING INTEGRATED STRUCTURES, AND METHODS OF FORMING VERTICALLY-STACKED MEMORY CELLS

Micron Technology, Inc., ...

5. A method of forming vertically-stacked memory cells, comprising:
forming a metal-containing material over a stack of alternating silicon dioxide levels and conductively-doped silicon levels;
forming a first opening to extend through the metal-containing material and the stack;
forming cavities extending into the conductively-doped silicon levels along sidewalls of the first opening;
forming charge-blocking dielectric and charge-storage structures within the cavities; a second opening remaining after forming
the charge-blocking dielectric and the charge-storage structures, the second opening having sidewalls extending along the
metal-containing material and the charge-storage structures;

lining the sidewalls of the second opening with gate dielectric; and
forming channel material within the lined second opening.

US Pat. No. 9,299,405

METHODS FOR SENSING MEMORY ELEMENTS IN SEMICONDUCTOR DEVICES

Micron Technology, Inc., ...

15. A device, comprising:
a delta-sigma modulator configured to:
receive an analog input signal from a sensed memory element;
generate a feedback signal;
integrate a difference between the analog input signal and the feedback signal to produce an integrated difference; and
exercise feedback control over the integrated difference.

US Pat. No. 9,281,073

METHODS OF OPERATING A MEMORY DEVICE HAVING A BURIED BOOSTING PLATE

Micron Technology, Inc., ...

1. A method of operating a memory device, the memory device comprising at least one memory cell being on a semiconductor material,
the semiconductor material being over a dielectric material, the method comprising:
biasing a boosting plate under the dielectric material to a non-ground voltage level as one step of operating the memory cell.

US Pat. No. 9,275,701

APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY

Micron Technology, Inc., ...

1. An apparatus, comprising:
an array of memory cells; and
sensing circuitry comprising:
a first latch coupled to a sense line of the array; and
a second latch coupled to the first latch, wherein the sensing circuitry is configured to accumulate, in the second latch,
a result of a first operation phase of a logical operation and a number of intermediate operation phases of the logical operation
without performing a sense line address access;

wherein the first operation phase comprises sensing a memory cell coupled to the sense line, and wherein the number of intermediate
operation phases comprise sensing a respective number of different memory cells coupled to the sense line.

US Pat. No. 9,117,998

NONVOLATILE MEMORY CELLS AND METHODS OF FORMING NONVOLATILE MEMORY CELLS

Micron Technology, Inc., ...

1. A nonvolatile memory cell comprising:
a first electrode, a second electrode, and a programmable region between the first and second electrodes;
the first electrode comprising a first current conductive material and a second current conductive material different in composition
from the first current conductive material, the first and second current conductive materials being within an opening in a
dielectric material, all of the second current conductive material being within the opening in the dielectric material, the
second current conductive material having a first portion laterally surrounded by the first current conductive material and
a second portion projecting elevationally outward from the first current conductive material and from the first portion, the
second portion having vertical sidewalls all of which are within the opening in the dielectric material and having a top surface,
the programmable region being directly against the top surface and directly against the vertical sidewalls of the second portion
of the projecting second current conductive material; and the second portion of second current conductive material comprising
a neck projecting elevationally outward from the first portion, the first portion comprising a pair of second conductive material
shoulders that are laterally inward of the first current conductive material.

US Pat. No. 9,306,579

OUTPUT DRIVER ROBUST TO DATA DEPENDENT NOISE

Micron Technology, Inc., ...

1. A method, comprising:
receiving, using a first controller of a first driver circuit in a memory device, a first data segment from a first sub-pre-pre-driver
of the first driver circuit;

receiving, using the first controller, a second data segment from a first sub-pre-driver of the first driver circuit, wherein
the first sub-pre-pre-driver and the first sub-pre-driver sequentially amplify a first sequence of data before transmission
by the first driver circuit;

receiving, using the first controller, a third data segment from a second sub-pre-pre-driver of a second driver circuit of
the memory device;

receiving, using the first controller, a fourth data segment from a second sub-pre-driver of the second driver circuit, wherein
the second sub-pre-pre-driver and the second sub-pre-driver sequentially amplify a second sequence of data before transmission
by the second driver circuit;

predicting, using the first controller, a degree to which data dependent noise is expected to delay transmission of the first
sequence of data, the second sequence of data, or both in a plurality of transmission lines based at least in part on the
first data segment, the second data segment, the third data segment, and the fourth data segment; and

adjusting, using the first controller, a first operational parameter of the first driver circuit used to transmit the first
sequence of data based on the degree.

US Pat. No. 9,298,437

UNROLLING QUANTIFICATIONS TO CONTROL IN-DEGREE AND/OR OUT-DEGREE OF AUTOMATON

Micron Technology, Inc., ...

1. A machine-readable medium that is not a transitory propagating signal, the machine readable medium including instructions
that, when executed by a machine, cause the machine to preform operations comprising:
identifying a quantification in a regular expression of source code;
rewriting the quantification to be implemented by at least one of a counter state machine element of a target device or a
set of general purpose state machine elements;

identifying portions of the rewritten quantification that can be implemented by the counter state machine element;
determining whether the target device has an available counter state machine element for the identified portions; and
unrolling the identified portions if there is no available counter state machine element and assigning the identified portions
to the available counter state machine element otherwise.

US Pat. No. 9,287,502

RESISTANCE VARIABLE MEMORY CELL STRUCTURES AND METHODS

Micron Technology, Inc., ...

1. A method of forming a memory cell, comprising:
forming a memory cell material on a first electrode, wherein the memory cell material is formed on a wall of a via and on
the first electrode;

forming a first dielectric material on the memory cell material;
removing a portion of the first dielectric material such that a portion of the memory cell material is exposed;
forming a second electrode on a first exposed portion of the memory cell material and a third electrode on a second exposed
portion of the memory cell material; and

forming a spacer material on at least a portion of the second electrode and on at least a portion of the first dielectric
material; and

forming a first and a second memory cell structure by:
removing at least a portion of the spacer material between the second and the third electrodes;
removing at least a portion of the first dielectric material within the via; and
removing at least a portion of the memory cell material formed on the first electrode.

US Pat. No. 9,281,066

DYNAMICALLY CONFIGURABLE MLC STATE ASSIGNMENT

Micron Technology, Inc., ...

1. A memory device, comprising:
a plurality of memory cells comprising a page of memory cells at each of first and second locations within the memory device,
wherein each memory cell of each page is configured to store data comprising an upper page and a lower page; and

control circuitry;
wherein the control circuitry is configured to determine whether data is to be read from one of the upper page or the lower
page at the first location upon generation of an internal command; and

wherein the control circuitry is configured to determine whether data read from the one of the upper page or the lower page
at the first location that is to be programmed into the lower page at the second location should be inverted using an inversion
operation before programming the data read from the one of the upper page or the lower page at the first location into the
lower page at the second location.

US Pat. No. 9,263,341

METHODS OF FORMING TRANSISTORS

Micron Technology, Inc., ...

1. A method of forming a transistor, comprising:
forming a pair of spaced-apart openings extending into semiconductor material, the openings having wide lower regions beneath
narrow upper regions;

forming gate dielectric material along sidewalls of the openings;
forming gate material within the openings and over regions of the semiconductor material between the openings;
forming insulative material down the center of each opening and entirely through the gate material; the insulative material
splitting the gate material within each opening into two isolated portions; a segment of gate material extending from one
of the openings to the other, and wrapping around a pillar of the semiconductor material between the openings; said segment
being a gate of a transistor; and

forming source/drain regions on opposing sides of the gate.

US Pat. No. 9,257,430

SEMICONDUCTOR CONSTRUCTION FORMING METHODS

Micron Technology, Inc., ...

1. A semiconductor construction forming method comprising:
providing a substrate;
forming a first semiconductor material over the substrate, a second semiconductor material over the first semiconductor material,
a third semiconductor material over the second semiconductor material, and a fourth semiconductor material over the third
semiconductor material wherein the first and second semiconductor materials comprise different dopants relative to one another
and the third and fourth semiconductor materials comprise different dopants relative to one another;

etching a first trench extending entirely through the fourth semiconductor material and partially through the third semiconductor
material;

depositing an insulative material on a sidewall of the trench, the insulative material being in contact with the first semiconductor
material and the second semiconductor material;

etching a second trench extending from a bottom surface of the first trench entirely through the third semiconductor material
and partially through the second semiconductor material;

depositing a metal on a sidewall of the second trench, the metal being in contact with the insulative material, the third
semiconductor material, and the second semiconductor material;

reacting the metal with the third semiconductor material and the second semiconductor material so that a first portion of
the third semiconductor material and a second portion of the second semiconductor material comprise a metal silicide, the
first portion and the second portion being below the insulative material; and

wherein the first and second semiconductor materials together form a first diode, the third and fourth semiconductor materials
together form a second diode, and wherein the first and second portions form a conductive electrode between the first diode
and the second diode.

US Pat. No. 9,190,144

MEMORY DEVICE ARCHITECTURE

MICRON TECHNOLOGY, INC., ...

1. A memory device, comprising:
an array of memory cells; and
a plurality of row drivers and a plurality of column drivers distributed within a footprint of the array of memory cells,
the row drivers and column drivers being distributed across the footprint in a plurality of disjointed row driver regions
and disjointed column driver regions.

US Pat. No. 9,184,159

SIMPLIFIED PITCH DOUBLING PROCESS FLOW

MICRON TECHNOLOGY, INC., ...

1. A partially formed integrated circuit, comprising:
a substrate;
a plurality of mandrels overlying the substrate, each mandrel having a long dimension and a short dimension as seen in a top-down
view;

a plurality of spacer loops disposed at sidewalls of the mandrels;
a hard mask layer disposed on a same level as the spacer loops; and
a mask disposed directly over the hard mask layer and ends of the spacer loops disposed at sidewalls of the mandrels, while
leaving mid-sections of the spacer loops exposed, wherein the mid-sections are disposed between opposing ends of each spacer
loop, and wherein each mid-section comprises a spacer portion immediately adjacent a midpoint of the long dimension of the
mandrels.

US Pat. No. 9,159,921

RESISTIVE MEMORY CELL

Micron Technology, Inc., ...

1. A method of forming a resistive memory cell, comprising:
forming a first dielectric region between two electrodes;
forming a barrier dielectric region on the first dielectric region; and
forming a second dielectric region on the barrier dielectric region,
wherein the barrier dielectric region includes a material having a slower oxygen diffusion rate and/or is a grain-boundary
disruptor relative to the first and second dielectric regions and forming the barrier dielectric region includes forming a
crystalline barrier dielectric region adjacent an amorphous first or second dielectric region, and wherein forming the barrier
dielectric region includes forming an amorphous barrier dielectric region adjacent a crystalline first or second dielectric
region.

US Pat. No. 9,153,451

METHOD OF FORMING A PLANAR SURFACE FOR A SEMICONDUCTOR DEVICE STRUCTURE, AND RELATED METHODS OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE

Micron Technology, Inc., ...

1. A method of forming a planar surface for a semiconductor device structure, comprising:
forming a particle film comprising discrete particles on a non-planar surface of a material comprising at least one elevated
region and at least one recessed region, the discrete particles attached at least to a surface of the at least one recessed
region of the material without use of a binder material, adjacent particles of the discrete particles in contact with one
another; and

performing at least one chemical-mechanical polishing process to remove the particle film and the at least one elevated region
of the material while retaining the at least one recessed region of the material.

US Pat. No. 9,129,684

DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE

Micron Technology, Inc., ...

1. A memory device, comprising:
an array of memory cells; and
a controller coupled to the array of memory cells;
wherein the controller is configured to determine a program window after a portion of a particular programming operation performed
on the memory device is performed and before a subsequent portion of the particular programming operation performed on the
memory device is performed;

wherein the controller is configured to determine the program window responsive to an amount of program disturb experienced
by a particular state of a memory cell; and

wherein the controller is configured to perform the subsequent portion of the particular programming operation performed on
the memory device using the determined program window.

US Pat. No. 9,479,361

METHOD AND APPARATUS FOR SELECTING AN OPERATING MODE BASED ON A DETERMINATION OF THE AVAILABILITY OF INTERNAL CLOCK SIGNALS

Micron Technology, Inc., ...

1. A method comprising:
receiving a control signal to operate a memory device in power down state associated with an asynchronous mode of operation
for on-die termination (ODT) circuitry;

determining a sufficiency of clock signals for a synchronous mode of operation when a clock pulse occurs in a first input
clock signal based on a rising edge of an external clock signal or a second input clock signal based on a failing edge of
the external clock signal during half of a clock period of the external clock signal;

determining an insufficiency of clock signals for a synchronous mode of operation when no clock pulses occur for both the
first input clock signal and the second input clock signal during one clock period of the external clock signal;

if the determining indicates sufficiency of clock signals, operating the memory device in the power down state using the synchronous
mode of operation; and

if the determining indicates insufficiency of clock signals, operating the memory device in the power down state using the
asynchronous mode of operation.

US Pat. No. 9,318,430

STACK OF HORIZONTALLY EXTENDING AND VERTICALLY OVERLAPPING FEATURES, METHODS OF FORMING CIRCUITRY COMPONENTS, AND METHODS OF FORMING AN ARRAY OF MEMORY CELLS

Micron Technology, Inc., ...

1. A method of forming an array of cross-point memory cells, comprising:
forming a stack of horizontally extending and vertically overlapping dielectric features, the stack comprising a primary portion
and an end portion, at least some of the dielectric features extending farther in the horizontal direction in the end portion
moving deeper into the stack in the end portion;

forming openings through the dielectric features in the primary portion and in the end portion;
lining the openings with first material;
lining the first material-lined openings with programmable material;
filling remaining volume of the first and programmable material-lined openings with conductive material;
forming horizontally elongated trenches through the dielectric features to form horizontally elongated and vertically overlapping
dielectric lines from dielectric material of the dielectric features, the dielectric lines individually extending from the
primary portion into the end portion and individually laterally about sides of both the openings in the primary and end portions;

removing at least some of sacrificial material that is elevationally between the dielectric lines in the primary and end portions
laterally between the trenches selectively relative to the dielectric lines and the first material lining in the openings;

after removing at least a portion of the sacrificial material, removing at least a portion of the first material that is elevationally
between the dielectric lines to expose laterally outer sidewalls of the programmable material that is elevationally between
the dielectric lines; and

replacing at least a portion of the sacrificial material with conductor material that is in electrical connection with the
laterally outers sidewalls of the programmable material and to comprise vertically spaced horizontal conductive lines; individual
ones of the cross-point memory cells comprising crossing ones of the horizontal conductive lines in the primary portion and
conductive material in the openings in the primary portion having the programmable material there-between.

US Pat. No. 9,281,062

SYSTEMS, AND DEVICES, AND METHODS FOR PROGRAMMING A RESISTIVE MEMORY CELL

MICRON TECHNOLOGY, INC., ...

1. A method, comprising:
providing a multi-level memory cell having more than two possible programmed states;
selecting parameters for a quench period of a programming pulse based upon a desired programmed state for the memory cell;
and

applying the programming pulse to the memory cell to program the memory cell to the desired programmed state.

US Pat. No. 9,276,081

METHODS OF FORMING DIODES

Micron Technology, Inc., ...

1. A method of forming a diode, comprising:
forming a patterned insulative material over a base, the patterned insulative material having at least one opening extending
therethrough to the base;

forming electrically conductive material as a liner within the at least one opening;
etching the liner to form two or more projections extending upwardly from the base, said projections being spaced from one
another by at least one gap that extends to an upper surface of the base;

depositing one or more layers across the projections and within the at least one gap to form the first electrode of the diode;
and

forming a second electrode over said one or more layers to form the diode.

US Pat. No. 9,235,134

LENS HEATING COMPENSATION IN PHOTOLITHOGRAPHY

Micron Technology, Inc., ...

1. A photolithographic apparatus, comprising an optical path configured to:
provide a first diffraction pattern to a portion of an optical system, wherein the first diffraction pattern is configured
to expose a semiconductor article and induce a thermal gradient in the portion;

provide a second diffraction pattern to the portion of the optical system after providing the first diffraction pattern, wherein
the semiconductor article is not exposed to the second diffraction pattern and the second diffraction pattern is configured
to reduce the thermal gradient in the portion, and

wherein the optical path comprises an illumination source that includes a micro-electromechanical micro-mirror array that
is configurable to provide, in conjunction with a reticle, both the first diffraction pattern and the second diffraction pattern.

US Pat. No. 9,224,430

DEVICES, METHODS, AND SYSTEMS SUPPORTING ON UNIT TERMINATION

Micron Technology, Inc., ...

1. A method of operating a system, comprising:
adjusting, by a controller of the system, a timing mode associated with a number of memory devices of the system, wherein:
each of the number of memory devices includes a number of memory units;
a memory unit of each respective memory device includes a termination circuitry and a termination matrix, wherein the termination
circuitry includes a number of different selectable resistors and the termination matrix includes a number of resistance values
associated with the termination circuitry for a number of different timing modes associated with the memory devices, and wherein
each of the number of resistance values in the termination matrix represents a different timing mode;

a memory unit of each respective memory device does not include termination circuitry;
adjusting, by the memory unit in at least one of the memory devices that includes the termination circuitry and the termination
matrix, the termination circuitry based, at least partially, on the adjustment of the timing mode associated with the memory
device, the adjustment of the timing mode including an adjustment of at least one of an input/output speed associated with
the number of memory devices, a clock frequency associated with the number of memory devices, and a bus speed associated with
a bus of the number of memory devices, wherein adjusting the termination circuitry includes adjusting the resistance value
associated with the resistors of the termination circuitry, such that the adjusted resistance value is a minimum resistance
value that permits the number of devices to operate at an input/output speed of the adjusted timing mode;

monitoring, by the termination circuitry, commands provided across the bus;
activating, by the termination circuitry, upon detection of a particular command to perform a termination function;
de-activating, by the termination circuitry, upon performing the termination function; and
controlling, by the controller, access across a number of memory channels coupled to the respective number of memory devices
via the bus.

US Pat. No. 9,224,798

CAPACITOR FORMING METHODS

Micron Technology, Inc., ...

1. A capacitor forming method comprising:
forming an electrically conductive support material over a substrate, the support material comprising from about 55 to about
70 at % carbon; about 5 at % or less of one or more of nitrogen, oxygen, sulfur, metals, and semimetals; and from about 25
to 40 at % hydrogen;

forming an opening into the support material;
after forming the opening, forming a first capacitor electrode in the opening; and
forming a dielectric over the first capacitor electrode and forming a second capacitor electrode over the dielectric.

US Pat. No. 9,196,313

STACKED DEVICE IDENTIFICATION ASSIGNMENT

Micron Technology, Inc., ...

1. An apparatus comprising:
a first die including a first via going through the first die, and a second via going through the first die;
a second die arranged in a stack with the first die, the second die including a third via going through the second die, and
a fourth via going through the second die, wherein the first via and the fourth via are substantially aligned in a direction
perpendicular to the stack, and the second via and the third via are substantially aligned in a direction perpendicular to
the stack; and

conductive joints outside the first die and the second die and between the first die and the second die, wherein one of the
conductive joints is coupled to the second via and the third via, and none of the conductive joints is coupled to the first
via and the fourth via.

US Pat. No. 9,888,574

APPARATUS AND METHODS FOR VIA CONNECTION WITH REDUCED VIA CURRENTS

Micron Technology, Inc., ...

1. An apparatus comprising:
a printed circuit board (PCB); and
an electronic component mounted on the PCB, the electronic component comprising at least one pin,
wherein the PCB comprises:
a multi-level plane structure comprising first, second and third planes, wherein the first plane includes a first conductive
region, the second plane includes a second conductive region, and the third plane includes a third conductive region,

wherein the first, second and third planes are disposed at different levels from one another,
wherein the first conductive region includes a first portion projecting from a part of the first conductive region, a second
portion and a third portion between the first and second portions, wherein the second conductive region includes fourth and
fifth portions corresponding respectively to the second and third portions of the first conductive region, and wherein the
third conductive region includes a sixth portion corresponding to the fourth portion of the second conductive region;

a first conductive via forming a first electrical path between the third portion of the first conductive region and the fifth
portion of the second conductive region without an intervention of the third conductive region;

a second conductive via forming a second electrical path between the second portion of the first conductive region and one
of the fourth portion of the second conductive region and the sixth portion of the third conductive region; and

a third conductive via forming a third electrical path between the fourth portion of the second conductive region and the
sixth portion of the third conductive region, and

wherein the at least one pin of the electronic component is coupled to the first portion of the first conductive region.

US Pat. No. 9,355,730

MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS

Micron Technology, Inc., ...

1. An apparatus, comprising:
a plurality (G) of memory cells; and
a packing component configured to:
map each one of a plurality (2N) of data patterns to a respective one of 2N program state combinations corresponding to the G memory cells in accordance with a mapping constellation comprising at least
a first shell of constellation mapping points and a second shell of constellation mapping points;

wherein the G memory cells are configured to store N/G units of data per memory cell.

US Pat. No. 9,177,614

APPARATUSES AND METHODS INCLUDING MEMORY WITH TOP AND BOTTOM DATA LINES

Micron Technology, Inc., ...

1. An apparatus comprising:
a first data line located on a first level of the apparatus;
a second data line located on a second level of the apparatus;
a first memory cell string coupled to the first data line;
a first source coupled to the first memory cell string;
a second memory cell string coupled to the second data line; and
a second source coupled to the second memory cell string, wherein the first and second sources are located in different levels
of the apparatus.