US Pat. No. 9,335,376

TEST ARCHITECTURE FOR CHARACTERIZING INTERCONNECTS IN STACKED DESIGNS

Mentor Graphics Corporati...

1. An integrated circuit to be fabricated on a first die, comprising:
a plurality of interconnection elements for communicating with another integrated circuit to be fabricated on a second die,
the first die and the second die being stacked with one on top of the other or the first die and the second die being mounted
on a same substrate;

a plurality of boundary scan cells coupled to the plurality of interconnection elements, wherein each of the plurality of
boundary scan cells can be configured to operate as, based on control signals, a conventional boundary scan cell or any bit
of an asynchronous counter; and

control circuitry that supplies the control signals.

US Pat. No. 9,047,434

CLUSTERING FOR PROCESSING OF CIRCUIT DESIGN DATA

Mentor Graphics Corporati...

1. A method of partitioning portions of a circuit design for an electronic design automation process, comprising:
generating one or more initial clusters of nodes from the circuit design by employing a computing system to
identify one or more critical paths in the circuit design that do not meet specified timing requirements,
select one or more nodes in the critical paths that have timing violations, and
grow the initial clusters of nodes from the selected nodes, wherein each initial cluster of nodes includes at least one node
having a timing violation exceeding a threshold value and having a logical connection to at least another node in the initial
cluster of nodes;

employing a computing system to create one or more final clusters of nodes from the initial clusters of nodes based upon processing
weight values for processing the final clusters of nodes according to the electronic design automation process; and

employing a computing system to partition the circuit design according to the final clusters of nodes.

US Pat. No. 9,117,044

HIERARCHICAL VERIFICATION OF CLOCK DOMAIN CROSSINGS

Mentor Graphics Corporati...

1. One or more computer-readable devices, having computer executable instructions for performing hierarchical verification
of a device design, the computer executable instructions enabling a computer to perform a set of predetermined operations
comprising:
accessing a device design having a plurality of hardware blocks;
designating hardware blocks having more than one clock domain for a clock domain crossing verification;
forming a block-level group from designated hardware blocks;
employing a computer to perform a block-level clock domain crossing verification process on the block-level group, the block-level
clock domain crossing verification process generating a plurality of block-level interface models;

employing the computer to perform a top-level clock domain crossing verification process to be performed on the device design
based in part upon the block-level interface models; and

saving results of the top-level clock domain crossing verification process to a memory storage location.

US Pat. No. 9,443,051

GENERATING ROOT CAUSE CANDIDATES FOR YIELD ANALYSIS

Mentor Graphics Corporati...

1. A method comprising:
by using a computer:
identifying points of interest by searching for disruptions and/or discontinuities of features in a layout design, the points
of interest representing locations of potential critical features;

determining at least one region of interest for one or more of the points of interest;
extracting one or more properties from the at least one region of interest, the one or more properties representing at least
one pattern characteristic of the at least one region of interest;

generating diagnosis reports by testing one or more devices comprising an integrated circuit fabricated according to the layout
design, the testing indicating one or more of the devices as being failing devices; and

analyzing the diagnosis reports of the failing devices fabricated according to the layout design based at least on the one
or more properties to identify probable root causes.

US Pat. No. 9,250,287

ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES

Mentor Graphics Corporati...

1. A method, comprising:
by a computer:
receiving a file storing circuit design information for a circuit-under-test; and
generating circuit design information for a test circuit configured to test the circuit-under-test, the test circuit comprising:
a plurality of scan chain groups, each scan chain group comprising one or more scan chains and one or more corresponding scan
chain group outputs;

a plurality of comparator circuits, each comparator circuit comprising a comparator input and a comparator output;
an encoder circuit comprising a plurality of encoder inputs and an encoder output, wherein the encoder inputs are coupled
to respective comparator outputs; and

a plurality of compactors, each compactor comprising an XOR or XNOR tree configured to compact test response values output
from the scan chain group outputs of a respective one of the scan chain groups, each compactor further comprising two or more
compactor inputs coupled to the scan chain group outputs of the respective one of the scan chain groups and further comprising
a compactor output coupled to the comparator input of a respective comparator, the encoder circuit being configured to detect
more than two error values output from the compactor outputs.

US Pat. No. 9,197,197

DUTY CYCLE PROTECTION CIRCUIT

STMICROELECTRONICS SA, M...

1. A duty cycle protection circuit comprising:
a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition
of a second clock signal in response to a first clock transition of said first clock signal; and

reset circuitry coupled to said input line and adapted to generate a second clock transition of said second clock signal by
resetting said first synchronous device a time delay after said first clock transition of said first clock signal;

said reset circuitry comprising a delay element adapted to provide a delayed version of said second clock signal, and pulse
generation circuitry coupled to said delay element;

said pulse generation circuitry comprising a logic gate having first and second inputs coupled to the delay element;
said first input being adapted to directly receive the delayed version of said second clock signal, and said second input
being adapted to directly receive an inverted version of the delayed version of said second clock signal;

said pulse generation circuitry adapted to generate a pulse for resetting said first synchronous device based on said first
clock transition of said first clock signal.

US Pat. No. 9,372,946

DEFECT INJECTION FOR TRANSISTOR-LEVEL FAULT SIMULATION

Mentor Graphics Corporati...

1. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors
to perform a method, the method comprising:
selecting a circuit element in a circuit netlist of a circuit for defect injection;
determining a defect based on whether the circuit element is a design-intent circuit element or a parasitic circuit element,
including determining that the circuit netlist includes at least one design-intent subcircuit netlist but no corresponding
physical-implementation subcircuit netlist, and thus considering passive circuit elements in the at least one design-intent
subcircuit netlist as design-intent circuit elements except those having values less than a pre-determined value for each
type of circuit elements;

injecting the defect into the circuit netlist; and
simulating the circuit.

US Pat. No. 9,057,762

FAULTY CHAINS IDENTIFICATION WITHOUT MASKING CHAIN PATTERNS

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:
identifying no-failing-bits output channels of a compactor based on output data of a test, the no-failing-bits output channels
outputting no failing bits during the test;

identifying good scan chains based on scan chains associated with the no-failing-bits output channels; and
analyzing bits outputted from failing-bits output channels per clock cycle to identify one or more suspected faulty scan chains
from scan chains other than the good scan chains, each of the failing-bits output channels outputting at least one failing
bit during the test, each of the one or more suspected faulty scan chains solely explaining failing bits outputted from all
output channels in the failing-bits output channels that are associated with the each of the one or more suspected faulty
scan chains for at least one clock cycle.

US Pat. No. 9,384,167

FORMAL VERIFICATION OF BOOTH MULTIPLIERS

Mentor Graphics Corporati...

1. A computer-implemented formal verification method, comprising:
by a computing device,
receiving a specification of an n×n-bit multiplier circuit;
performing a direct model checking operation for a M×n-bit multiplier circuit, where M performing a series of model checking operations for multiplier circuits that are incrementally larger than the M×n-bit multiplier
circuit; and

outputting a verification result of the n×n-bit multiplier circuit specification based on the direct modeling checking operation
and the series of model checking operations.

US Pat. No. 9,135,103

HYBRID MEMORY FAILURE BITMAP CLASSIFICATION

Mentor Graphics Corporati...

1. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors
to perform a method, the method comprising:
receiving a memory failure bitmap;
classifying, based on a rule-based classification method, failure patterns in the memory failure bitmap that can be identified
with the rule-based classification method, the rule-based classification method employing rules that comprise rules for global
failure pattern classification;

classifying, based on an artificial neural network method, failure patterns in the memory failure bitmap that cannot be identified
based on the rule-based classification method, wherein the failure patterns in the memory failure bitmap that cannot be identified
based on the rule-based classification method are local failure patterns; and

storing classification results for the memory failure bitmap.

US Pat. No. 9,304,881

TRACE ROUTING NETWORK

Mentor Graphics Corporati...

1. A hardware emulator apparatus, comprising:
a configurable interconnect circuit configured to, dependent on an emulation cycle, selectively connect one or more sets of
data lines from data capture output connections of at least one configurable physical block to one or more scan chain input
lines.

US Pat. No. 9,244,125

DYNAMIC DESIGN PARTITIONING FOR SCAN CHAIN DIAGNOSIS

Mentor Graphics Corporati...

1. One or more non-transitory processor-readable storage devices storing computer-executable instructions for causing one
or more processors to perform a method, the method comprising:
combining fan-out cones for scan cells of one or more faulty scan chains of a circuit design to derive a forward-tracing cone;
combining fan-in cones for scan cells of the one or more faulty scan chains and for failing observation points of the circuit
design to derive a backward-tracing cone, the failing observation points comprising scan cells of good scan chains and primary
outputs that capture failing bits according to a test failure file; and

generating a chain diagnosis sub-circuit for the test failure file by determining an intersection of the forward-tracing cone
and the backward-tracing cone.

US Pat. No. 9,330,228

GENERATING GUIDING PATTERNS FOR DIRECTED SELF-ASSEMBLY

Mentor Graphics Corporati...

1. One or more processor-readable storage devices storing computer-executable instructions for causing one or more processors
to perform a method, the method comprising:
A: constructing a guiding pattern for a via-type feature group based on seeding positions, wherein the via-type feature group
comprises two or more via-type features in a layout design and the seeding positions are initially derived from targeted locations
of the two or more via-type features;

B: determining a potential energy function for the guiding pattern, wherein the potential energy function is at least a two-dimensional
function and comprises a first portion representing interactions between via-type features in the via-type feature group and
a second portion representing wall effects of the guiding pattern;

C: computing simulated locations of the two or more via-type features based on the potential energy function;
D: changing the seeding positions based on differences between the simulated locations and the targeted locations; and
F: repeating operations A through D until one of one or more termination conditions is met.

US Pat. No. 9,165,099

ADAPTIVE CLOCK MANAGEMENT IN EMULATION

Mentor Graphics Corporati...

1. A method, comprising:
synthesizing, using a programmable computer, logic that can generate a clock suspension request signal based on activity status
information of an emulator with one or more emulator resources;

synthesizing, using a programmable computer, logic that can generate a clock suspension allowance signal based on slack information
related to speed constraints of one or more clock signals associated with one or more dynamic targets of the emulator; and

synthesizing, using a programmable computer, logic that can generate a clock suspension signal for enabling temporary suspensions
of design clock signals in the emulator based on the clock suspension request signal and the clock suspension allowance signal.

US Pat. No. 9,111,067

GROUPING LAYOUT FEATURES FOR DIRECTED SELF ASSEMBLY

Mentor Graphics Corporati...

1. One or more processor-readable storage device storing computer-executable instructions for causing one or more processors
to perform a method, the method comprising:
receiving information of a layout design;
separating via-type features in the layout design into via-type feature groups and isolated via-type features, a criterion
for deciding whether a via-type feature is an isolated via-type feature or belongs to a via-type feature group being distance
between the via-type feature and via-type features neighboring the via-type feature; and

analyzing the via-type feature groups to determine whether the via-type feature groups are DSA (Directed-Self-Assembly)-compliant,
wherein the analyzing comprises:

determining distorted areas for the via-type feature groups, a distorted area being an area not covered or covered twice by
DSA shells of two neighboring via-type features; and

comparing the distorted areas with predetermined threshold value(s).

US Pat. No. 9,335,377

TEST-PER-CLOCK BASED ON DYNAMICALLY-PARTITIONED RECONFIGURABLE SCAN CHAINS

Mentor Graphics Corporati...

1. An integrated circuit, comprising:
scan chains, each of the scan chains reconfigurable to operate, based on a control signal, in one of at least three modes,
a shifting-launching mode, a capturing-compacting-shifting mode and a mission mode, a scan chain in the capturing-compacting-shifting
mode shifting out one bit of previously compacted test response data while compacting remaining bits of the previously compacted
test response data with a currently-captured test response to form currently compacted test response data.

US Pat. No. 9,135,376

INPUT SPACE REDUCTION FOR VERIFICATION TEST SET GENERATION

Mentor Graphics Corporati...

1. A method comprising:
identifying multiple subspaces of a set of input vectors of a design;
running a numerical solver on the multiple subspaces previously identified, the numerical solver determining if any solution
to a set of input constraints exists in the multiple subspaces; and

searching, in hierarchical stages, the multiple subspaces for unique input vectors that satisfy the set of input constraints,
the searching using a different seed for each of the hierarchical stages, and the searching excluding at least a portion of
at least one of the multiple subspaces based upon the numerical solver determining that no solution to the set of input constraints
exists in the at least one of the multiple subspaces.

US Pat. No. 9,134,370

CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES

Mentor Graphics Corporati...

1. A circuit, comprising:
a parallel-in serial-out register; and
a decompressor comprising a phase shifter and a linear feedback shift register (LFSR), the LFSR being coupled between an output
of the register and an input of the phase shifter,

the parallel-in serial-out register being configured to load compressed test pattern bits in parallel and apply the compressed
test pattern bits serially to the LFSR of the decompressor, and

the decompressor being configured to decompress the compressed test pattern bits into decompressed test pattern bits.

US Pat. No. 9,391,794

GENERATING WORST CASE TEST SEQUENCES FOR NON-LINEARLY DRIVEN CHANNELS

Mentor Graphics Corporati...

1. An apparatus comprising at least one non-transitory computer-readable memory device storing instructions configured to
cause one or more processing devices to perform operations comprising:
determining multiple receive waveforms capable of being output from a channel of an electrical system in response to corresponding
drive waveforms input to the channel;

generating a set of test bit sequences, each test bit sequence correlated to a plurality of the receive waveforms based, at
least in part, on bit sequences capable of being utilized by a driver to generate the drive waveforms; and

selecting a test bit sequence from the set of test bit sequences based, at least in part, on characteristics of the receive
waveforms correlated to the test bit sequences; and

driving the channel of the electrical system with a test drive waveform generated by the driver in response to the selected
test bit sequence, wherein the test receive waveform output from the channel in response to test drive waveform input to the
channel indicates a signal integrity of the channel.

US Pat. No. 9,355,201

DENSITY-BASED INTEGRATED CIRCUIT DESIGN ADJUSTMENT

Mentor Graphics Corporati...

1. One or more computer-readable media storing computer-executable instructions when executed by a computer cause the computer
to perform a method, the method comprising:
deriving a local density value for one or more geometric elements in at least a portion of a layout design for an integrated
circuit; and

modifying the shape of one or more of the geometric elements while maintaining the local density value across the one or more
geometric elements in the at least a portion of the layout design.

US Pat. No. 9,305,126

SWITCHING ACTIVITY REDUCTION THROUGH RETIMING

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:
computing switching activity values at output ports of circuit elements of a circuit design based on switching activity values
at input ports of the circuit elements and scaling factors associated with the circuit elements, the scaling factors representing
effects of signal changes at the input ports on signal changes at the output ports, the computing comprising calculating weighted
sums of the switching activity values at the input ports of each of the circuit elements using the scaling factors as relative
weights;

identifying one or more regions of the circuit design for retiming based on the switching activity values at the output ports
of the circuit elements; and

determining retiming location information for the one or more regions based on the switching activity values at the output
ports of the circuit elements, the retiming location information comprising information of one or more circuit nodes for placing
circuit state elements to reduce switching activity in each of the one or more regions.

US Pat. No. 9,230,054

HIGH-FREQUENCY VLSI INTERCONNECT AND INTENTIONAL INDUCTOR IMPEDANCE EXTRACTION IN THE PRESENCE OF A MULTI-LAYER CONDUCTIVE SUBSTRATE

Mentor Graphics Corporati...

1. One or more computer-readable memory or storage devices storing computer-executable instructions which when executed by
a computer cause the computer to perform a method, the method comprising:
receiving layout information indicative of at least signal-wire segments in a circuit design and substrate profile information
indicative of electrical characteristics of a substrate over which the circuit design is to be implemented;

performing impedance extraction using the layout information and the substrate profile information, wherein the impedance
extraction generates a plurality of impedance values for the signal-wire segments and wherein the substrate is not represented
by a plurality of filaments during the impedance extraction; and

generating a representation of electrical characteristics of the circuit design, the representation comprising the impedance
values.

US Pat. No. 9,081,588

EXECUTION TIME PROFILING FOR INTERPRETED PROGRAMMING LANGUAGES

Mentor Graphics Corporati...

1. A method comprising:
executing, by a computing device, software that (a) is written in a first programming language, (b) calls one or more native
interpretive functions that interpret one or more non-native functions written in a second programming language different
from the first programming language to enable the computing device to execute the one or more non-native functions, and (c)
calls one or more native functions written in the first programming language for execution by the computing device, wherein
each of the one or more native interpretive functions is written in the first programming language; and

profiling execution of the software by:
identifying, based on execution of the one or more native interpretive functions, which of the one or more non-native functions
is interpreted by the one or more native interpretive functions, resulting in an identified non-native function,

obtaining profile information that describes one or more characteristics of how the identified non-native function executed
on the computing device,

identifying which of the one or more native functions is being executed, resulting in an identified native function, and
obtaining additional profile information that describes one or more characteristics of how the identified native function
executed on the computing device.

US Pat. No. 9,335,374

DYNAMIC SHIFT FOR TEST PATTERN COMPRESSION

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:
generating compressed test patterns for a design of an integrated circuit, wherein the integrated circuit comprises:
a decompressor configurable to decompress the compressed test patterns,
a compactor configurable to compact test response data, and
scan chains coupled to outputs of the decompressor and to inputs of the compactor, each of scan chains in the circuit design
being divided into a plurality of segments, and

wherein the generating comprises:
adding one or more non-shift clock cycles to one or more segments in the plurality of segments to help derive the compressed
test patterns, the one or more non-shift clock cycles being additional clock cycles that the decompressor uses to generate
bits for scan cells in the one or more segments of the scan chains; and

storing the compressed test patterns and information related to the added one or more non-shift clock cycles.

US Pat. No. 9,323,161

SOURCE OPTIMIZATION BY ASSIGNING PIXEL INTENSITIES FOR DIFFRACTIVE OPTICAL ELEMENT USING MATHEMATICAL RELATIONSHIP

Mentor Graphics Corporati...

1. A computer-readable storage medium storing a sequence of instructions that when executed by a computer causes the computer
to perform a method, the method comprising:
selecting a pattern of features in a layout database to be created on a wafer, wherein the selecting comprises determining
that the pattern of layout features in the layout database occurs in an array;

defining a mathematical relationship between one or more pixel intensities produced by a diffractive optical element and the
selected pattern of features; and

assigning pixel intensities for the diffractive optical element using the mathematical relationship, the pixel intensities
being calculated to produce an image of the selected pattern of features on the wafer with greater image fidelity than other
features in the layout database.

US Pat. No. 9,275,179

SINGLE EVENT UPSET MITIGATION FOR ELECTRONIC DESIGN SYNTHESIS

Mentor Graphics Corporati...

1. A method comprising:
retrieving, from one or more memory, timing data for a plurality of signal paths within a circuit design;
determining, based on the timing data, that the circuit design does not meet a predetermined single event upset susceptibility
requirement;

generating a modified circuit design by adding, in response to the determining, one or more delays to the plurality of signal
paths, wherein the adding of the one or more delays comprises reducing a strength of a driver on one of the plurality of signal
paths, adding a buffer in the one of the plurality of signal paths, or a combination thereof; and

storing the modified circuit design to the one or more memory.

US Pat. No. 9,262,557

MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING

Mentor Graphics Corporati...

1. A method for determining a performance rating of a formal verification tool, the method comprising:
by a computer, determining a proof radius indicative of an amount of analysis performed for a property of a circuit without
finding a counter-example for the property when using the formal verification tool to formally verify the property until a
predetermined limit is met;

by the computer, determining a performance rating for the formal verification tool, wherein the performance rating is based
at least in part on the proof radius; and

displaying the performance rating;
wherein the predetermined limit is based at least in part on a predetermined budget of processing time that elapses during
the formally verifying or on a reaching a proof radius limit during the formally verifying.

US Pat. No. 9,189,582

PROGRAMMABLE PATTERN AWARE VOLTAGE ANALYSIS

Mentor Graphics Corporati...

1. A method comprising:
matching, by a computing system, a set of components in a circuit design to a design pattern representing a voltage-transition
device;

determining, by the computing system, a magnitude of an output voltage for the set of components in the circuit design based,
at least in part, on a configuration of the voltage-transition device represented by the design pattern that matched the set
of components; and

modifying, by the computing system, the circuit design to include the magnitude of the output voltage for the set of components.
US Pat. No. 9,134,616

GENERALIZATION OF SHOT DEFINITIONS FOR MASK AND WAFER WRITING TOOLS

Mentor Graphics Corporati...

1. A method of writing patterns onto a substrate, comprising
projecting a beam of radiation through only a portion of at least one aperture onto a substrate; and
arranging the beam of radiation relative to the at least one aperture to form a plurality of images on the substrate, such
that at least a portion of the images have compound-trapezoidal concave shapes.

US Pat. No. 9,088,522

TEST SCHEDULING WITH PATTERN-INDEPENDENT TEST ACCESS MECHANISM

Mentor Graphics Corporati...

1. A method of test scheduling, comprising:
receiving test data for testing a plurality of cores in a circuit and information of TAM (test access mechanism) for the circuit,
the information of TAM comprising information of an input switching network that connects circuit input channels to core input
channels for each of the plurality of cores, and information of an output switching network that connects circuit output channels
to core output channels for each of the plurality of cores;

encoding the test data to derive compressed test patterns that require small numbers of the core input channels, each of the
compressed test patterns being associated with one or more cores in the plurality of cores and with core input channel requirement
information;

determining core output channel requirement information for each of the compressed test patterns;
grouping the compressed test patterns into test pattern classes based on cores associated with each of the compressed test
patterns, the core input channel requirement information and the core output channel requirement information; and

allocating, based on the information of TAM, test application time slots and the circuit input channels which deliver the
test pattern classes to the plurality of cores and the circuit output channels which collect test response data for the test
pattern classes.

US Pat. No. 9,323,632

MONITORING PHYSICAL PARAMETERS IN AN EMULATION ENVIRONMENT

Mentor Graphics Corporati...

1. A method of monitoring an emulation environment used to emulate an Integrated Circuit design, comprising:
emulating the Integrated Circuit design in an emulator, the emulator including multiple printed circuit boards housed in an
emulator chassis, wherein emulating the Integrated Circuit includes mimicking the Integrated Circuit design using programmable
logic;

receiving temperature information associated with one or more of the printed circuit boards, wherein each printed circuit
board has two or more temperature sensors, a temperature sensor being positioned at a hotter point and a temperature sensor
being positioned at a colder point of each printed circuit board;

receiving a selection of a first printed circuit board of the one or more printed circuit boards;
displaying a user interface including the received temperature information for the first printed circuit board, wherein the
user interface is a graphical user interface wherein the received temperature information comprises a current temperature
at the hotter point and colder point of each printed circuit board, wherein the two or more temperature sensors of each printed
circuit board are located at predetermined positions and wherein displaying the temperature information includes displaying
temperature information at the predetermined positions, wherein the temperature information includes a maximum and minimum
temperature at each predetermined position; and

receiving a selection of a second printed circuit board of the one or more printed circuit boards and displaying the user
interface including the received temperature information for the second printed circuit board, while no longer displaying
the temperature information for the first printed circuit board.

US Pat. No. 9,292,643

MASK CREATION WITH HIERARCHY MANAGEMENT USING COVER CELLS

Mentor Graphics Corporati...

1. A method, comprising:
designating a cell in a hierarchical description as a cover cell, the hierarchical description representing hierarchical relationships
between cells of an integrated circuit layout; and

by a computer, redefining the hierarchical description, wherein:
the redefining reduces the hierarchical depth of at least a portion of the hierarchical description to be no greater than
a predetermined depth limit, and

the redefining comprises incorporating data from one or more noncover cells into the cover cell.

US Pat. No. 9,134,374

CIRCUIT AND METHOD FOR MEASURING DELAYS BETWEEN EDGES OF SIGNALS OF A CIRCUIT

Mentor Graphics Corporati...

1. A circuit for measuring a signal delay between an edge of a first alternating signal supplied to a first node of a circuit-under-test
(CUT) and an edge of a second alternating signal supplied to a second node of the CUT, the first and second alternating signals
being synchronous to a first clock, the circuit comprising:
means for capturing, controlled by a first capture clock, first samples of signals associated with the first and second alternating
signals, the first capture clock's sampling instants being synchronous to a second clock and having a timing skew included
in a signal delay measurement, the second clock being coherent to the first clock;

means for capturing, controlled by a second capture clock, second samples of the first samples, the second capture clock's
sampling instants being synchronous to the second clock and having a timing skew not included in the signal delay measurement;
and

means for conveying the second samples via a shift register to a plurality of modulo counters.

US Pat. No. 9,110,138

FAULT DICTIONARY BASED SCAN CHAIN FAILURE DIAGNOSIS

Mentor Graphics Corporati...

1. A method of generating a fault dictionary to determine faulty scan cells in a scan chain, comprising:
by a computer:
receiving a description of an integrated circuit that includes combinational and sequential logic that can be tested by applying
test patterns to the sequential logic and reading scan chain outputs;

for one or more scan cells in scan chains, determining respective lists of failures that will be observed at the scan chain
outputs when each of the one or more scan cells has a defined fault; and

storing a fault dictionary representative of the respective lists of failures for each of the one or more scan cells.

US Pat. No. 9,086,454

TIMING-AWARE TEST GENERATION AND FAULT SIMULATION

Mentor Graphics Corporati...

1. A method of generating test patterns for testing an integrated circuit, comprising:
identifying a fault that is detected by a test pattern by simulating a response of an integrated circuit design to the test
pattern in the presence of the fault and identifying one or more paths that are sensitized by the test pattern and that detect
the fault;

determining that the identified fault is to be removed from a fault list, the determination being based at least in part on
a relative difference between actual slack and static slack of the shortest sensitized path detecting the identified fault,
wherein the actual slack is determined by actual path delay through the shortest sensitized path detecting the fault and the
static slack is determined by static path delay through the shortest sensitized path detecting the fault;

modifying the fault list by removing the identified fault; and
storing the modified fault list.

US Pat. No. 9,389,944

TEST ACCESS ARCHITECTURE FOR MULTI-DIE CIRCUITS

Mentor Graphics Corporati...

1. A die comprising test circuitry for testing the die, interconnections between the die and an adjacent die when the die
is stacked, or both the die and interconnections, the test circuitry comprising:
a first input port configured to receive test stimuli and test control instructions;
a first output port configured to send test responses, test stimuli and test control instructions, the first input port and
the first output port being located at a first side of the die, wherein there is a data signal path within the die between
the first input port and the first output port;

a second input port configured to receive test responses, test stimuli, and test control instructions from another die, wherein
there is a data signal path within the die between the second input port and the first output port;

a second output port configured to send test stimuli and test control instructions to the another die, the second input port
and the second output port being located at a second side of the die, wherein there is a data signal path within the die between
the first input port and the second output port;

a third input port configured to receive one or more test control signals; and
test control circuitry, the test control circuitry accepting the one or more test control signals and producing a block/unblock
signal derived from the one or more test control signals, the test control circuitry accepting data from either the first
input port or the second input port depending on the block/unblock signal.

US Pat. No. 9,086,459

DETECTION AND DIAGNOSIS OF SCAN CELL INTERNAL DEFECTS

Mentor Graphics Corporati...

1. A method of scan cell internal defect diagnosis, comprising:
identifying a failing scan chain;
determining an upper bound and a lower bound of candidate scan cells in the failing scan chain; and
identifying one or more scan cell internal fault candidates in the candidate scan cells based on a failure log and failing
scan test patterns associated with the failure log, wherein the one or more scan cell internal fault candidates are for one
or more static scan cell internal defects that exhibit static defect behavior but that do not behave as stuck-at faults and
also do not behave as transition faults, wherein the static scan cell internal defect is a resistive short or open, and wherein
the static defect behavior is characterized by a faulty output value being consistently output from a scan cell output for
a respective combination of input values at scan cell inputs, the faulty output value being 0 for at least one combination
of input values and being 1 for at least another combination of input values.

US Pat. No. 9,075,944

SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN

Mentor Graphics Corporati...

1. A method, comprising:
by a processor:
calculating planes of focus for exposure for one or more tiles of a modeled wafer that best fits modeled surface height data
for a predetermined number of values within a slit;

calculating distances of each of the tiles within the slit to each of the calculated planes along an axis of illumination;
calculating an average focus offset from the calculated distances; and
identifying tiles with an average focus offset that is outside of a certain specification range which is related to a depth
of focus for the lithography process.

US Pat. No. 9,323,873

MODELLING AND SIMULATION METHOD

Mentor Graphics Corporati...

1. A method for modelling and simulating a system using an event based simulation system, the method comprising:
storing a plurality of models each representing a component of the system;
storing current status information for each model;
generating a plurality of events affecting the current status of at least one model of the plurality of models;
simulating behaviour of the system by processing the plurality of events affecting the current status of the at least one
model;

adding a first item during simulation to a plurality of items of a sensitivity list of a user interface based on receiving
information that a user added the first item to a display window of the user interface, the first item and the plurality of
items of the sensitivity list corresponding to status information of respective models;

storing historical information for the plurality of items of the sensitivity list, the historical information comprising a
time queue entry for a respective item of the plurality of items of the sensitivity list, the time queue entry comprising
functional relationships and interface relationships of the respective item;

outputting a graphical view of the time queue entries for the plurality of items of the sensitivity list to the user by the
user interface, wherein the user interface is modelled by the event based simulation system as a further component of the
system, and the user interface is scheduled for update based on the simulation changing the current status information of
any item on the sensitivity list; and

removing a second item during simulation from the plurality of items of the sensitivity list of the user interface based on
receiving information that the user removed the second item from the display window of the user interface.

US Pat. No. 9,384,107

IMPROPER VOLTAGE LEVEL DETECTION IN EMULATION SYSTEMS

Mentor Graphics Corporati...

1. An emulator apparatus comprising:
an emulator including a plurality of configurable logic blocks for emulating a design for an integrated circuit;
a signal line connecting the emulator to a hardware component;
a voltage level detector connected to the signal line, the voltage level detector configured to detect whether a voltage level
of a signal transmitted on the signal line is within a first predetermined range or within a second predetermined range, the
voltage level detector including an output indicating when a voltage level of a signal transmitted on the signal line is outside
of the first predetermined range and outside of the second predetermined range, the voltage level detector comprising:

a first set of resistors;
a first operational amplifier including an inverting input connected to an output of the first set of resistors and a non-inverting
input connected to the signal line;

a second set of resistors;
a second operational amplifier including a non-inverting input connected to an output of the second set of resistors and an
inverting input connected to the signal line; and

an exclusive-or gate including a first input connected to an output of the first operational amplifier and a second input
connected to an output of the second operational amplifier, the output of the exclusive-or gate being the output of the voltage
level detector; and

a sampling circuit configured to sample the output of the voltage level detector at a user specified clock.

US Pat. No. 9,336,107

DYNAMIC DESIGN PARTITIONING FOR DIAGNOSIS

Mentor Graphics Corporati...

1. One or more processor-readable storage device storing computer-executable instructions for causing one or more processors
to perform a method, the method comprising:
with the one or more processors,
receiving information of a circuit design for one or more integrated circuit devices and failure information of the one or
more integrated circuit devices generated by applying test patterns to the one or more integrated circuit devices;

extracting a sub-circuit from the circuit design based on the failure information, the sub-circuit comprising one or more
portions of the circuit design that include one or more defects in the one or more integrated circuit devices; and

performing fault diagnosis on the sub-circuit to generate diagnosis data based on the test patterns and the failure information,
wherein performing the fault diagnosis comprises generating a first set of defect suspects based on path tracing, and generating
a second set of defect suspects based on the first set of defect suspects and failing pattern validation; and

outputting the diagnosis data.

US Pat. No. 9,330,226

MODELING SUBSTRATE NOISE COUPLING FOR CIRCUIT SIMULATION

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:
clustering two or more neighboring substrate contacts;
combining the two or more neighboring substrate contacts into one equivalent substrate contact by calculating a position for
the equivalent substrate contact;

modeling electrical impedance between a first substrate contact and a second substrate contact in the presence of the equivalent
substrate contact based on one of a horizontal impedance model and an L-shaped impedance model, wherein the first substrate
contact, the second substrate contact and the two or more neighboring substrate contacts are substrate contacts in a layout
design and/or particular areas of the layout design, and

wherein the horizontal impedance model models electrical impedance for the first substrate contact and the second substrate
contact in the presence of the equivalent substrate contact positioned on a line that passes through the first substrate contact
and the second substrate contact, and

wherein the L-shaped impedance model models electrical impedance for the first substrate contact and the second substrate
contact in the presence of the equivalent substrate contact positioned on a line that passes through one of the first substrate
contact and the second substrate contact and is perpendicular to a line passing through the first substrate contact and the
second substrate contact;

performing circuit simulation on a circuit associated with the layout design, wherein the circuit includes a parasitic element
having the electrical impedance; and

fabricating an integrated circuit based upon the layout design.

US Pat. No. 9,310,831

MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS

Mentor Graphics Corporati...

1. A method comprising:
placing, by a computing device, a clock tree in a circuit design, wherein the clock tree is configured to distribute a clock
signal to sink pins in the circuit design;

measuring, by the computing device, multiple clock skew values in the circuit design, wherein each clock skew value is measured
with the clock tree having a different respective set of clock tree timing variation parameters; and

performing, by the computing device, an adjustment of the clock tree in the circuit design based, at least in part, on the
multiple clock skew values with the clock tree having different respective sets of clock tree timing parameters, wherein the
adjustment of the clock tree alters placement of at least one clock tree node in the clock tree.

US Pat. No. 9,262,567

RESOURCE MAPPING IN A HARDWARE EMULATION ENVIRONMENT

Mentor Graphics Corporati...

1. A method, comprising:
receiving a request to load an integrated circuit design to a hardware emulator;
determining that one or more resources of the hardware emulator are unavailable to load the integrated circuit design; and
in response to the determination that the one or more resources are unavailable, remapping the integrated circuit design into
one or more alternative resources of the hardware emulator that are available.

US Pat. No. 9,183,330

ESTIMATION OF POWER AND THERMAL PROFILES

Mentor Graphics Corporati...

1. A method of power and thermal profile estimation, comprising:
by a computing system:
receiving information of a netlist for a circuit design and information of a group of devices;
identifying the group of devices in the netlist based on the information of the group of devices;
retrieving a current value for one or more devices in the group of devices from a lookup table;
determining power consumption information for the group of devices based in part on the retrieved current value; and
associating the power consumption information with layout location information for the group of devices.

US Pat. No. 9,507,902

SIMULTANEOUS MULTI-LAYER FILL GENERATION

Mentor Graphics Corporati...

1. A method of optimizing a pattern density in a circuit layout design, comprising:
(a) employing a computer to generate a first fill region in a first layer of a circuit layout design;
(b) employing a computer to generate a second fill region in a second layer of the circuit layout design, the second layer
being different than the first layer;

(c) employing a computer to generate a pattern of representations of a multilayer fill structure, the representations including
a representation of a first section of the multilayer fill structure to be inserted into the first fill region, and
a representation of a second section of the multilayer fill structure to be inserted into the second fill region;
(d) employing a computer to determine a target density for a window of the circuit layout design, the window including a first
portion in the first layer of the circuit layout design and a second portion in the second layer of the circuit layout design;

(e) selecting representations of the multilayer fill structure from the pattern to be added to the circuit layout design,
for changing a density for the window to approach the determined target density; and

(f) adding the selected representations of the multilayer fill structure to the circuit layout design.

US Pat. No. 9,389,945

TEST ACCESS ARCHITECTURE FOR STACKED DIES

Mentor Graphics Corporati...

1. A die comprising test circuitry for testing the die, interconnections between the die and an adjacent die when the die
is stacked, or both the die and interconnections, the test circuitry comprising:
a first input port configured to receive test stimuli and test control instructions;
a first output port configured to send test responses, test stimuli and test control instructions, the first input port and
the first output port being located at a first side of the die, wherein there is a data signal path within the die between
the first input port and the first output port;

a second input port configured to receive test responses, test stimuli, and test control instructions from another die, wherein
there is a data signal path within the die between the second input port and the first output port;

a second output port configured to send test stimuli and test control instructions to the another die, the second input port
and the second output port being located at a second side of the die, wherein there is a data signal path within the die between
the first input port and the second output port; and

test access interface circuitry, the test access interface circuitry accepting data from either the first input port or the
second input port depending on an input selection signal.

US Pat. No. 9,262,574

VOLTAGE-RELATED ANALYSIS OF LAYOUT DESIGN DATA

Mentor Graphics Corporati...

1. One or more processor-readable storage device storing computer-executable instructions for causing one or more processors
to perform a method, the method comprising:
generating, using the one or more processors, voltage association data objects for drawn layers in a net of a layout design,
each of the voltage association data objects being generated for one of the drawn layers;

collecting, using the one or more processors, a voltage value or range of voltage values for each geometric element of the
net, wherein the net comprises two or more geometric elements;

associating, using the one or more processors, the voltage values or ranges of voltage values collected for each of the geometric
elements of the net with the voltage association data objects; and

searching, using the one or more processors, the voltage association data objects according to a predetermined criterion to
determine whether at least one of the geometric elements of the net matches the predetermined criterion without searching
voltage values of the geometric elements of the net themselves.

US Pat. No. 9,135,391

DETERMINATION OF ELECTROMIGRATION SUSCEPTIBILITY BASED ON HYDROSTATIC STRESS ANALYSIS

Mentor Graphics Corporati...

1. One or more processor-readable storage device storing computer-executable instructions for causing one or more processors
to perform a method, the method comprising:
analyzing a circuit design to determine voltages of nodes in an interconnect tree, the interconnect tree comprising continuously
connected geometric elements of a conductive material confined by diffusion blocking ends to one layer of a layout design
for the circuit design, the nodes comprising locations where electron flows change directions, diverge, converge or reach
diffusion blocking ends such as vias, the circuit design containing parasitic resistance information for the interconnect
tree;

determining, based on the voltages of the nodes, current density values and current directions for segments of the interconnect
tree, each of the segments being a part of the interconnect tree confined by a pair of neighboring nodes in the nodes;

computing, based on the current density values and the current directions, hydrostatic stress values for the nodes under a
state that assumes a steady-state condition, no voids being nucleated and conservation of the conductive material within the
interconnect tree, the steady-state condition being a condition of no atomic fluxes in the interconnect tree; and

determining electromigration susceptibility of the interconnect tree based on the hydrostatic stress values.

US Pat. No. 9,407,573

BANDWIDTH CONTROL IN A CONTROLLER AREA NETWORK (CAN)

Mentor Graphics Corporati...

1. A method comprising:
utilizing, by a computing system, a controller area network (CAN) design to identify periodic messages and sporadic messages
capable of being generated and transmitted on a shared bus by a control node described in the CAN design; and

assigning, by the computing system, placeholders to a schedule table of the control node to define a message transmission
schedule for the control node, wherein the placeholders include a periodic message placeholder configured to identify a specific
one of the periodic messages and reserve bandwidth on the shared bus for transmission of the identified periodic message,
and wherein the placeholders include a sporadic message placeholder configured to identify a group of the sporadic messages
and configured to reserve bandwidth on the shared bus for transmission of any one of the sporadic messages in the identified
group.

US Pat. No. 9,214,208

NOR-OR DECODER

Mentor Graphics Corporati...

1. A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false, comprising:
a pre-charge circuit configured to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic
NOR node and pre-charged dynamic OR node to float, wherein the pre-charge circuit allows the pre-charged dynamic NOR node
and the pre-charged dynamic OR node to float upon assertion of a clock signal;

a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address
bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein each switch is configured to turn on only if its corresponding address bit is false;

a (n+1)th switch coupling the dynamic NOR node to the ground; and
a (n+2)th switch coupled between the dynamic NOR node and the ground and arranged in parallel with the plurality of switches,
the (n+2)th switch being driven by a delayed version of the clock signal.

US Pat. No. 9,361,422

FRAGMENTATION POINT AND SIMULATION SITE ADJUSTMENT FOR RESOLUTION ENHANCEMENT TECHNIQUES

Mentor Graphics Corporati...

1. A method of defining a number of features to be created via a photolithographic process, the method comprising:
with a computer,
reading at least a portion of a layout data file defining the features to be created,
estimating a number of image intensities at one or more simulation sites around each feature by estimating each of the image
intensities at a first value of a process condition and at a second, different value of the process condition for the photolithographic
process,

calculating an image intensity gradient vector at one or more of the simulation sites,
dividing each feature into a number of edge fragments, and
determining a layout correction for an edge fragment based on a combination of the estimates of the image intensities under
the first value and the second value of the process condition and the image intensity gradient vector, wherein the layout
correction can be used in manufacturing a mask or reticle for fabricating the features with the photolithographic process.

US Pat. No. 9,418,195

LAYOUT CONTENT ANALYSIS FOR SOURCE MASK OPTIMIZATION ACCELERATION

Mentor Graphics Corporati...

1. A computer implemented method comprising:
identifying a layout design for a mask;
partitioning the layout design into a plurality of layout sections;
selecting a reference point in each of the layout sections;
identifying layout sections that have similar geometric shapes relative to the reference point;
consolidating the plurality of layout sections into a plurality of pattern groups based upon the identified layout sections
that have similar geometric shapes;

identifying (a) an optical lithographic system, (b) a set of optical lithographic tolerance parameters, and (c) a representative
layout section for each of the pattern groups;

using a computer system to generate a simulated printed image corresponding to each of the representative layout sections
using the optical lithographical system;

determining which of the simulated printed images do not fall within the optical lithographic tolerance parameters;
optimizing the layout design of the mask by modifying the layout sections whose simulated images do not fall within the optical
lithographic tolerance parameters such that the mask falls within the image tolerance parameters; and

fabricating the mask according to the optimized layout design.

US Pat. No. 9,400,860

MULTI-FPGA PROTOTYPING OF AN ASIC CIRCUIT

Mentor Graphics Corporati...

1. A method of designing a prototype comprising several programmable chips for modelling a logic design comprising a hierarchy
of logic modules communicating with one another, the method comprising:
creating a new hierarchy of logic modules on the basis of the hierarchy of the logic modules of the logic design by flattening
the modules that cannot be preserved according to design constraints;

partitioning the new hierarchy of logic modules into regions each comprising one or more programmable chips while minimizing:
inter-region communications in a manner correlated with the physical connections available between each pair of programmable
chips; and

a number of traversal(s) of programmable chips of a critical combinatorial path; and
establishing a routing of the signals between programmable chips by using the physical resources available.

US Pat. No. 9,378,327

CANONICAL FORMS OF LAYOUT PATTERNS

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:
transforming coordinates of vertices of geometric elements in a window of a layout design into new coordinates of the vertices,
wherein the coordinates of vertices do not comprise clipped coordinates and the transforming comprises:

performing a translation on the coordinates of vertices based on differences between maximum and minimum X coordinate values
of the vertices and between maximum and minimum Y coordinate values of the vertices (the clipped coordinate values not considered);
and

determining a canonical form of the geometric elements based on a sum of X coordinate values of the new coordinates of the
vertices and a sum of Y coordinate values of the new coordinates of the vertices.

US Pat. No. 9,501,589

IDENTIFICATION OF POWER SENSITIVE SCAN CELLS

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:
computing signal probability values for signal lines in a circuit design, wherein the signal lines comprise signal lines associated
with scan cells in the circuit design;

computing toggling probability values based on the signal probability values, wherein the toggling probability values comprise
toggling rate values for the scan cells;

computing toggling rate reduction values based on the toggling probability values, wherein the toggling rate reduction values
comprise toggling rate reduction values for the scan cells;

identifying scan cells having high toggling rate reduction values; and
inserting logic configured to freeze parallel outputs of the identified scan cells during a scan shift process into the circuit
design.

US Pat. No. 9,477,805

LOGICAL EQUIVALENCY CHECK WITH DYNAMIC MODE CHANGE

Mentor Graphics Corporati...

1. A method comprising:
identifying, by a computing system, matched register pairs, each having one register in a first circuit design and one register
in a second circuit design;

determining, by the computing system in a combinational equivalence check mode, a portion of combinational logic, corresponding
to a first matched register pair, in the first circuit design is not equivalent to a portion of combinational logic, corresponding
to the first matched register pair, in the second circuit design;

switching the computing system from the combinational equivalence check mode to a sequential equivalence check mode;
sequentially expanding, by the computing system in the sequential equivalence check mode, the portions of the combinational
logic in the first circuit design and the second circuit design by coupling the portions of the combinational logic corresponding
to the first matched register pair to combinational logic corresponding to a second matched register pair; and

determining, by the computing system, whether the expanded portion of the combinational logic in the first circuit design
is equivalent to the expanded portion of the combinational logic in the second circuit design.

US Pat. No. 9,097,755

GENERATING TRANSMISSION-CODE COMPLIANT TEST SEQUENCES

Mentor Graphics Corporati...

1. A method comprising:
sampling, by a computing system, a response of a circuit channel to an input pulse;
nonrandomly determining, by the computing system, a sequence of code words configured to comply with a transmission code for
the circuit channel by:

dividing the sampled pulse response for the circuit channel into bit groups,
identifying possible code word types for the bit groups of the divided sampled pulse response, and
selecting one of the possible code word types for each bit group to include in the sequence of code words based, at least
in part, on the sampled pulse response of the circuit channel; and

transmitting, by the computing system, the sequence of code words as input on the circuit channel, which causes the output
voltage of the circuit channel to be reduced during a time period in which the circuit channel outputs a logic high value.

US Pat. No. 9,087,167

PREDICTION OF CIRCUIT PERFORMANCE VARIATIONS DUE TO DEVICE MISMATCH

Mentor Graphics Corporati...

1. One or more processor-readable storage media storing computer-executable instructions for causing one or more processors
to perform a method, the method comprising:
receiving a circuit description of a circuit design that comprises circuit elements and information of circuit element parameters
for the circuit elements;

performing circuit simulation using the circuit description and the information of circuit element parameters to generate
circuit simulation results;

computing sensitivity information based on the circuit simulation results;
computing, based on the circuit simulation results, current/charge deviations caused by individual circuit element parameter
variations;

determining steady-state mismatch effect information based on the sensitivity information and the current/charge deviations;
and

outputting the steady-state mismatch effect information.

US Pat. No. 9,465,898

LOOP HANDLING IN A WORD-LEVEL NETLIST

Mentor Graphics Corporati...

1. A method comprising:
detecting, by a computing system, a presence of a combinational loop in a word-level netlist representation of a circuit design
by identifying a portion of the word-level netlist having at least one characteristic associated with the combinational loop,
translating the identified portion of the word-level netlist into a bit-level circuit representation, and utilizing the bit-level
circuit representation to determine the identified portion of the word-level netlist includes the combinational loop; and

modifying, by the computing system, the word-level netlist corresponding to the detected presence of the combinational loop.

US Pat. No. 9,459,890

CONTROLLING REAL TIME DURING EMBEDDED SYSTEM DEVELOPMENT

Mentor Graphics Corporati...

1. A method, comprising:
generating a real-time clock signal; and
triggering tasks defined by an embedded software application with the real-time clock signal, the tasks comprising sets of
individual instructions,

wherein the embedded software application is executed by an embedded processor with a real-time operating system (RTOS),
wherein the real-time clock signal is controllable independent of a processor clock signal driving the embedded processor
to individually execute individual instructions such that the real-time clock signal operates without interrupting the processor
clock signal and has a different time base than the processor clock signal,

wherein the processor clock signal is derived from a source that is separate and different from a source of the real-time
clock signal;

wherein the embedded processor is part of an embedded system, and
wherein the source for the processor clock signal is a crystal oscillator located on the embedded system separate from the
embedded processor.

US Pat. No. 9,448,481

GENERALIZATION OF SHOT DEFINITIONS FOR MASK AND WAFER WRITING TOOLS

Mentor Graphics Corporati...

1. A method of writing patterns onto a substrate, comprising:
obtaining a set of microdevice design data;
fracturing the set of microdevice design data into conventional shapes;
filtering non-rectangular trapezoids from the fractured set of microdevice design data;
identifying adjacent pairs of rectangular shapes;
combining adjacent pairs of rectangular shapes into pattern segments;
projecting a beam of radiation through at least one aperture onto a substrate; and
arranging the beam of radiation relative to the at least one aperture to form a plurality of images on the substrate according
to the pattern segments, such that:

at least a portion of the images have compound-trapezoidal concave shapes; and
the plurality of images forms a pattern made up of convex trapezoidal shapes.

US Pat. No. 9,444,970

APPARATUS AND METHOD FOR MAGNIFYING AN IMAGE

Mentor Graphics Corporati...

1. An apparatus for magnifying an image, the apparatus comprising:
means for presenting a visible image portion of the image;
magnification means arranged to magnify part of the image to form a magnified image portion and unmagnified image portions,
said magnified and unmagnified image portions together containing all the image information contained within the image;

wherein at least part of the magnified image portion and a visible part of the unmagnified image portions are within the visible
image portion and the magnified image portion does not obscure the unmagnified image portions as a result of shifting the
visible part of the unmagnified image portions relative to the magnified image portion, wherein non-visible portions outside
of the visible image portion are also shifted relative to the magnified image portion by the same amount as the visible part
of the unmagnified image portions, and the non-visible portions are not presented by the means for presenting the visible
image portion of the image;

wherein the visible part of the unmagnified image portions comprises a first unmagnified image portion and a second unmagnified
image portion, and further wherein the first unmagnified image portion is shifted in a first dimension and wherein the second
unmagnified image portion is shifted in a second dimension so that at least one gap is created between the first unmagnified
image portion shifted in the first dimension and the second unmagnified image portion shifted in the second dimension, wherein
no gap existed between the first unmagnified image portion and the second unmagnified image portion before the first unmagnified
image portion and the second unmagnified image portion are shifted; and

wherein the image comprises a time line.

US Pat. No. 9,435,840

DETERMINING WORST-CASE BIT PATTERNS BASED UPON DATA-DEPENDENT JITTER

Mentor Graphics Corporati...

1. A method comprising:
measuring data-dependent jitter capable of being introduced to a channel by a transmitter of the channel, and measuring, by
a receiver of the channel, a step response associated with the channel generated in response to a bit transition by the transmitter;

deriving, by a computing system, a sequence pattern for input into the channel based, at least in part, on the data-dependent
jitter and the step response associated with the channel; and

determining, by the computing system, a bit error rate for the channel based, at least in part, on the sequence pattern.

US Pat. No. 9,377,508

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

Mentor Graphics Corporati...

1. A method, comprising:
generating mask data indicating patterns of unknown states for which to mask test responses received from scan cells in an
integrated circuit;

storing the mask data in a memory of the integrated circuit;
providing a selector configured to mask test responses produced by the scan cells based on the stored mask data, thereby producing
masked test responses, the selector comprising:

a shadow register configured to capture and save one or more outputs of a ring generator for more than one clock cycle, and
logic for determining whether to load the shadow register with the outputs of the ring generator based on control information
merged with the stored mask data; and

providing a test response compactor configured to receive the masked test responses.

US Pat. No. 9,361,424

INTEGRATED CIRCUIT LAYOUT DESIGN METHODOLOGY WITH PROCESS VARIATION BANDS

Mentor Graphics Corporati...

1. A method of verifying that an integrated circuit layout is manufacturable, comprising:
designating a set of criteria that specifies when a layout is “LFD-clean”;
reading at least portions of two or more integrated circuit layouts from a computer-readable storage medium;
evaluating the two or more integrated circuit layouts under the two or more simulated process conditions and comparing the
results to the designated criteria;

ranking the integrated circuit layouts or portions thereof according to the criteria; and
displaying the ranking to a user.

US Pat. No. 9,347,993

TEST GENERATION FOR TEST-PER-CLOCK

Mentor Graphics Corporati...

1. A method for generating a test pattern for testing an electronic circuit, comprising:
by at least one processor of a computer, generating a plurality of test cubes for testing the electronic circuit;
by the at least one processor of the computer, selecting, from the plurality of test cubes, a first test cube to be applied
by one or more scan chains of the electronic circuit during the testing;

by the at least one processor of the computer, merging the first test cube with one or more test cubes in the plurality of
test cubes that are compatible with the first test cube to generate a second test cube to be applied by the one or more scan
chains of the electronic circuit during the testing;

by the at least one processor of the computer, shifting the second test cube by one bit along a shift direction of the one
or more scan chains in the electronic circuit to generate a third test cube, such that the last bit of the second test cube
along the shift direction is the second to last bit of the third test cube along the shift direction; and

by the at least one processor of the computer, merging the third test cube with one or more test cubes in the plurality of
test cubes that are compatible with the third test cube to generate a fourth test cube to be applied by the one or more scan
chains of the electronic circuit during the testing, wherein at least one of the one or more test cubes that is compatible
with the third test cube is not compatible with the first or second test cubes.

US Pat. No. 9,483,594

RESET VERIFICATION

Mentor Graphics Corporati...

1. A method comprising:
detecting, by a computing system, reset functionality in a circuit design by locating sources of reset signals configured
to prompt reset of resettable components in the circuit design and analyzing the circuit design to identify reset information
corresponding to characteristics of the reset signals;

identifying, by the computing system, a portion of the circuit design having a set of the resettable components; and
determining, by the computing system, the portion of the circuit design includes an error corresponding to the set of the
resettable components based, at least in part, on the reset functionality in the circuit design.

US Pat. No. 9,558,308

COMPILER FOR CLOSED-LOOP 1×N VLSI DESIGN

MENTOR GRAPHICS CORPORATI...

1. A method, comprising:
inputting, by a computing device, a behavioral representation of a design for an integrated circuit, wherein the behavioral
representation comprises a register transfer level (RTL) description of a 1×N building block;

generating, by the computing device, a physical design representation based on the behavioral representation, wherein the
physical design representation comprises one of a flat netlist, a hierarchical netlist, or a flattened netlist; and

generating, by the computing device and via a 1×N compiler, a gate-level representation of the integrated circuit design based
on the physical design representation, wherein the generating comprises converting the physical design representation into
one or more 1×N building blocks and compiling the 1×N building blocks, via the 1×N compiler, into the gate-level representation.

US Pat. No. 9,222,978

TWO-DIMENSIONAL SCAN ARCHITECTURE

Mentor Graphics Corporati...

8. A circuit comprising a two-dimensional scan cell network, the two-dimensional scan cell network comprising:
at least one primary input scan cell comprising an input coupled to receive a value from at least one primary input; and
at least one core scan cell comprising an input coupled to an output of a multiplexer, the multiplexer having inputs coupled
directly to outputs of two or more other scan cells in the two-dimensional scan cell network, wherein the two or more other
scan cells comprise: (a) primary input scan cells of the at least one primary input scan cell; or (b) a primary input scan
cell of the least one primary input scan cell and another core scan cell in the two-dimensional scan cell network;

wherein the two-dimensional scan cell network is arranged such that at least one selection signal at the at least one primary
input causes a test pattern to be shifted along one of at least two available scan paths, wherein the at least two available
scan paths are selectable by the at least one selection signal, wherein the at least two available scan paths comprise a first
set of scan paths and a second set of scan paths, and wherein the second set of scan paths comprises quasi-diagonal scan paths,
reverse scan paths, or orthogonal scan paths and shares at least one scan cell with the first set of scan paths.

US Pat. No. 9,734,274

SYSTEM DESIGN MANAGEMENT

Mentor Graphics Corporati...

1. A method comprising:
identifying, by a computing system, relationships between objects in a meta model based, at least in part, on attributes included
in the objects in the meta model, wherein the meta model is configured to describe an electronic system using the objects
and the attributes, wherein the objects correspond to different portions of the electronic system, and wherein the attributes
define characteristics of the objects for design data corresponding to the different portions of the electronic system to
conform;

developing, by a computing system, a hierarchy of the objects based, at least in part, on the identified relationships between
the objects in the meta model; and

generating, by the computing system, a graphical presentation of the meta model that includes the objects arranged in the
graphical presentation based on the hierarchy of the objects, wherein the graphical presentation of the meta model includes
connections between a plurality of the objects having common attributes based on the hierarchy of the objects.

US Pat. No. 9,582,625

TEST BENCH TRANSACTION SYNCHRONIZATION IN A DEBUGGING ENVIRONMENT

Mentor Graphics Corporati...

1. A method comprising:
simulating, by a computing system, a circuit design with a test bench to generate a simulated output for the circuit design
and to generate a simulation log storing messages corresponding to operation of the test bench during the simulation of the
circuit design;

parsing, by the computing system, the simulation log to identify which of the messages in the simulation log correspond to
test bench transactions based, at least in part, on types of the messages in the simulation log and formats for the test bench
transactions; and

synchronizing, by the computing system, the simulated output for the circuit design with the test bench transactions identified
from the simulation log that prompted the generation of the simulated output for the circuit design.

US Pat. No. 9,576,092

SYNTHESIS USING MULTIPLE SYNTHESIS ENGINE CONFIGURATIONS

Mentor Graphics Corporati...

1. One or more tangible non-transitory computer-readable storage media storing computer-executable instructions, which when
executed by a computer, cause the computer to perform a computer-implemented synthesis method comprising:
performing a first synthesis run on a high-level description of a circuit design by synthesizing the high-level description
with a first synthesis engine configuration in order to generate a lower-level description and one or more performance reports;
and

subsequent to the first synthesis run:
a) identifying one or more sections of the high-level description to be synthesized in a second synthesis run with a second
synthesis engine configuration that is different than the first synthesis engine configuration in order to generate a second
lower-level description, wherein said identifying comprises evaluating at least one of the high-level description or the one
or more performance reports according to one or more criteria, and generating indications of the identified one or more sections,
wherein the one or more criteria comprise at least one of estimated timing behavior, area, or power consumption of the at
least two lower-level descriptions; and

b) performing the second synthesis run on the identified one or more sections of the high-level description with the second
synthesis engine configuration,

wherein at least one of the first synthesis run or the second synthesis run is performed by a remote computing resource.

US Pat. No. 9,459,523

PATTERN OPTICAL SIMILARITY DETERMINATION

Mentor Graphics Corporati...

1. A method comprising calibrating, with at least one processor of a computer, an optical proximity correction process for
modifying microcircuit designs, the calibrating of the optical proximity correction process including:
simulating a lithography process of a first set of layout features and a second set of layout features using a lithography
model, wherein the lithography model is expressed as a plurality of functions that indicate light intensity on an image plane,
wherein the simulating produces a first plurality of values representing respective contributions of the plurality of functions
to imaging the first set of layout features and produces a second plurality of values representing respective contributions
of the plurality of functions to imaging the second set of layout features;

determining optical similarity values between the first set of layout features and the second set of layout features based
on the first plurality of values and the second plurality of values; and

calibrating, based on the optical similarity values, parameters of the lithography model.

US Pat. No. 9,747,397

MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS

Mentor Graphics Corporati...

1. A method comprising:
determining, by a computing device, one or more clusters of sink pins of circuit elements in a circuit design;
placing, by the computing device, clock tree nodes of a clock tree for the circuit design within the one or more clusters;
determining, by the computing device, multiple sets of clock tree timing variation parameters for the placed clock tree nodes
within the one or more clusters;

measuring, by the computing device, multiple delays from a root node of the clock tree to the sink pins within the one or
more clusters, wherein the multiple delays are measured for the multiple sets of clock tree timing variation parameters, respectively;

determining, by the computing device, skews for the one or more clusters using the delays measured for the multiple sets of
clock tree timing variation parameters; and

reducing, by the computing device, clock tree skew across the multiple sets of clock tree timing variation parameters using
the multiple measured delays and skews.

US Pat. No. 9,652,581

DIRECTED SELF-ASSEMBLY-AWARE LAYOUT DECOMPOSITION FOR MULTIPLE PATTERNING

Mentor Graphics Corporati...

1. One or more non-transitory computer-readable media storing computer-executable instructions configured to, when executed,
cause one or more computing devices to:
generate a nodal graph for at least a portion of a layout for an integrated circuit design, wherein the nodal graph comprises
a plurality of nodes that represent features in the portion of the layout for the integrated circuit design, wherein each
of the plurality of nodes is directly connected to another node by a first type of edge or a second type of edge, wherein
the first type of edge is used to connect a first set of two nodes from the plurality of nodes if the first set of two nodes
represents features that must be assigned to different masks, and wherein the second type of edge is used to connect a second
set of two nodes from the plurality of nodes if the second set of two nodes represents features that are to be grouped together
for directed self-assembly (DSA) lithography or be assigned to different masks;

identify a plurality of node groups based on the nodal graph, wherein each of the plurality of node groups comprises two or
more nodes that are connected to each other via one or more first edges of the first type of edge, and wherein each of the
plurality of node groups is connected to one or more other groups from the plurality of node groups based on one or more second
edges of the second type of edge;

assign, based on the plurality of node groups, each node in the nodal graph to one of a plurality of masks used for multiple
patterning lithography such that directly-connected nodes within a node group are assigned to different masks from each other;

convert, after assigning each node in the nodal graph to one of the plurality of masks, at least one of the one or more second
edges into the first type of edge; and

generate, after converting the at least one of the one or more second edges into the first type of edge, one or more guiding
patterns based on the nodal graph.

US Pat. No. 9,568,552

LOGIC BUILT-IN SELF-TEST WITH HIGH TEST COVERAGE AND LOW SWITCHING ACTIVITY

Mentor Graphics Corporati...

1. A method, comprising:
shifting a low-toggling pseudo-random test pattern into scan chains, the low-toggling pseudo-random test pattern being generated
by low-toggling pseudo-random test pattern generation circuitry, low-toggling pseudo-random test patterns generated by the
low-toggling pseudo-random test pattern generation circuitry causing switching activity during scan shift cycles lower than
pseudo-random test patterns generated by a pseudo-random pattern generator;

modifying a plurality of bits in the low-toggling pseudo-random test pattern based on a background test pattern stored in
background scan chains to form a weighted pseudo-random test pattern; and

launching the weighted pseudo-random test pattern to test a circuit-under-test.

US Pat. No. 9,619,598

INPUT SPACE REDUCTION FOR VERIFICATION TEST SET GENERATION

Mentor Graphics Corporati...

1. A method comprising:
executing, by a computer system, a first process that performs a solving operation to determine if any input vector within
a set of input vectors satisfy an input constraint;

executing, by the computer system, in parallel with execution of the first process, a second process that performs a searching
operation to search for unique input vectors that satisfy the input constraint;

aborting the solving operation on the set based on a determination that at least one unique input vector has been found by
the searching operation to satisfy the input constraint; and

applying, as part of a process for verifying an electronic circuit design of an electronic circuit that is to be fabricated
or manufactured, the at least one unique input vector to the electronic circuit design.

US Pat. No. 9,747,398

MANAGING AND CONTROLLING THE USE OF HARDWARE RESOURCES ON INTEGRATED CIRCUITS

Mentor Graphics Corporati...

1. An RTL synthesis system, comprising:
a database comprising data indicative of available hardware resources in one or more types of previously fabricated field
programmable gate arrays (“FPGAs”);

memory storing a register-transfer-level (“RTL”) description of a circuit to be implemented in a selected one of the FPGAs;
and

a graphical user interface that allows a user to view how one or more operator instances defined by the RTL description are
assigned to be implemented by the available hardware resources of the selected one of the FPGAs and displays to the user how
many of the available hardware resources in the selected one of the FPGAs remain available after accounting for the assignments
prior to synthesis of the RTL description into a gate-level netlist.

US Pat. No. 9,729,317

OPTICAL PHYSICAL UNCLONEABLE FUNCTION

Mentor Graphics Corporati...

1. A method comprising:
generating, by an optical physical uncloneable function (PUF) device in an electronic device, at least a portion of a key
in response to received light, wherein the optical physical uncloneable function device includes multiple wave guides, each
of the wave guides to propagate the light in a different predetermined optical path defined prior to manufacture of the electronic
device, and wherein the at least the portion of the key has a value corresponding to which of the optical paths the light
traversed based, at least in part, on optical characteristics of the optical physical uncloneable function device set during
the manufacture of the electronic device;

receiving, by a security controller, at least the portion of the key from the optical physical uncloneable function device
interconnected with the security controller in the electronic device; and

initiating, by the security controller a security action through the interconnection when the key matches an expected key
in the security controller.

US Pat. No. 9,740,506

AUTOMATING INTERACTIONS WITH SOFTWARE USER INTERFACES

Mentor Graphics Corporati...

1. A computer-implemented method comprising:
determining a target object in a graphical user interface (GUI) for a software application input action based upon socially
identifying information of the target object, the socially identifying information describing the target objects relationship
to one or more peer objects of a same type as the target object and/or descendent objects in the GUI and comprising:

a type of the target object's parent,
a rank of the target object relative to the one or more peer objects of the same type as the target object, wherein the rank
indicates a location of the target object in the GUI relative to the one or more peer objects of the same type as the target
object, and

a location of a label of the target object, wherein the label is separate from the target object and the location of the label
describes a position of the label in the GUI relative to the target object; and

applying the input action to the target object.

US Pat. No. 9,857,421

DYNAMIC DESIGN PARTITIONING FOR DIAGNOSIS

Mentor Graphics Corporati...

1. One or more processor-readable storage device storing computer-executable instructions for causing one or more processors
to perform a method, the method comprising:
with the one or more processors,
receiving failure information for one or more integrated circuit devices, the failure information resulting from test patterns
being applied to the one or more integrated circuit devices;

extracting a sub-circuit from a circuit design for the one or more integrated circuit devices based on the failure information,
the sub-circuit comprising one or more portions of the circuit design that include one or more defects in the one or more
integrated circuit devices, wherein the extracting comprises combining fan-in cones of failing observation points and adding
fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points, wherein
the one or more passing observation points are selected based on one or more relationships with the failing observation points,
wherein the one or more relationships are represented by shared gate ratios;

performing fault diagnosis on the sub-circuit to generate diagnosis data based on the test patterns and the failure information;
and

outputting the diagnosis data.

US Pat. No. 9,689,918

TEST ACCESS ARCHITECTURE FOR STACKED MEMORY AND LOGIC DIES

Mentor Graphics Corporati...

1. A stack of dies, comprising:
a memory die, comprising:
memory interface circuitry comprising, a memory boundary scan register (MBSR) serial input port, a MBSR serial output port
and a plurality of MBSR control signal input ports; and

a logic die, comprising:
a first input port configured to receive test stimuli and test control instructions;
a first output port configured to send test responses, test stimuli and test control instructions, the first input port and
the first output port being located at a first side of the logic die, wherein there is a data signal path within the logic
die between the first input port and the first output port;

a second input port being connected to the MBSR serial output port, wherein there is a data signal path within the logic die
between the second input port and the first output port;

a second output port being connected to the MBSR serial input port, wherein there is a data signal path within the logic die
between the first input port and the second output port;

a plurality of MBSR control signal output ports being connected to the plurality of MBSR control signal input ports, wherein
the plurality of MBSR control signal output ports, the second input port and the second output port are located at a second
side of the logic die, and

test access interface circuitry for testing interconnections between the logic die and the memory die, the test access interface
circuitry comprising a MBSR controller supplying MBSR control signals to the plurality of MBSR control signal output ports,
wherein the MBSR controller comprises a multiplexer for switching between a functional mode and a test mode, wherein the test
mode allows the test stimuli to be transmitted via the second output port to the MBSR serial input port.

US Pat. No. 9,811,615

SIMULTANEOUS RETARGETING OF LAYOUT FEATURES BASED ON PROCESS WINDOW SIMULATION

Mentor Graphics Corporati...

1. One or more non-transitory computer-readable media storing computer-executable instructions which, when executed, cause
one or more processors to perform a method, the method comprising:
performing a process window simulation on a layout design to generate process window information, the layout design corresponding
to at least a portion of an integrated circuit, and the process window information comprising predicted print positions of
layout features computed under various process conditions;

determining retargeted print positions for a plurality of edge fragments in the layout design based on minimizing a combined
change of targeted print positions for the plurality of edge fragments under constraints on changes of the targeted print
positions for the plurality of edge fragments, the constraints being represented based on the process window information and
specification limits for printed layout features;

determining edge placement errors of the plurality of edge fragments based on the retargeted print positions;
determining adjustment amounts of the plurality of edge fragments based on the edge placement errors;
adjusting positions of the plurality of edge fragments by the adjustment amounts; and
performing optical proximity correction using the adjusted positions of the plurality of edge fragments and the retargeted
print positions.

US Pat. No. 10,567,556

COMMUNICATION CIRCUITRY IN AN ELECTRONIC CONTROL UNIT

Mentor Graphics Corporati...

1. A method comprising:parsing, by communication circuitry, an instruction including an identifier of a type of signal exchanged through a vehicle communication network and including a command associated with exchange of a signal value corresponding to the type of the signal;
identifying, based on the type of the signal from the instruction, a packet having a section allocated for the signal value corresponding to the type of the signal;
identifying, based on the type of the signal from the instruction, signal characteristics for the signal value including at least one of a position of the signal value in the packet or a size of the signal value; and
performing, by communication circuitry, packet operations on the section of the packet allocated for the signal value based, at least in part, on the command included in the instruction and the signal characteristics for the signal value.

US Pat. No. 10,133,557

MODIFYING CODE TO REDUCE REDUNDANT OR UNNECESSARY POWER USAGE

Mentor Graphics Corporati...

1. A computer-implemented method for reducing power usage of a device, comprising:inputting, by computing hardware, original source code for an application;
analyzing a situation where batching is possible by identifying, from one or more instruction sequences of the original source code, library function calls that corresponds to radio requests;
estimating a power gain from batching together two or more portions of the original source code library function calls that request operation of one or more power-consuming hardware components, wherein the estimating comprises computing a minimum or average time period between execution of the two or more of the portions of the original source code library function calls, analyzing power state transitions of the radio request, and comparing the cost of the power state transitions with savings due to idle inactivity time of the power-consuming hardware components; and
modifying, by the computing hardware, the original source code so that the two or more portions of the original source code are batched together removing instances of redundant power cycling, thereby creating modified source code from which the one or more power-consuming hardware components are operated in a more power efficient manner.

US Pat. No. 10,089,432

RULE-CHECK WAIVER

Mentor Graphics Corporati...

1. A method of waiving design errors, comprising:by a computing device:
receiving layout design data for a layout design;
receiving at least one waiver region identification item for identifying regions of layout design data in which one or more detected design errors are to be designated as false errors to be waived from being reported during physical verification;
employing the at least one waiver region identification item to identify regions in the received layout design data; and
modifying the received layout design data to include waiver items associated with the identified waiver regions;
designating the identified regions of the received layout design data as waiver regions in which the one or more detected design errors are to be designated as false errors.

US Pat. No. 9,811,617

REGRESSION NEAREST NEIGHBOR ANALYSIS FOR STATISTICAL FUNCTIONAL COVERAGE

Mentor Graphics Corporati...

1. A method comprising:
defining, by a computing system, coverage for system level functionality of a circuit design as a set of system level coverage
points, each corresponding to a different portion of system level functionality of the circuit design, wherein at least a
portion of the circuit design is provided for subsequent design and manufacturing of electronic devices;

generating, by the computing system, a matrix having multiple nodes corresponding to the system level coverage points in the
set, wherein the nodes are arranged in the matrix based on characteristics of the different portions of the system level functionality
corresponding to the system level coverage points;

simulating, by the computing system, the circuit design with one or more regressions;
populating, by the computing system, the nodes of the matrix with indications of events performed during the simulation; and
utilizing, by the computing system, the matrix to identify holes in the coverage for system level functionality of the circuit
design based on a distribution of the indications populated in the matrix.

US Pat. No. 9,996,651

MASK CREATION WITH HIERARCHY MANAGEMENT USING COVER CELLS

Mentor Graphics Corporati...

20. A system comprising:a hierarchical layout database storing data for a hierarchical description representing an integrated circuit layout;
one or more processors configured to receive layout data from the hierarchical database; and
one or more computer-readable storage media storing computer-readable instructions that when executed with the processors, cause the system to perform a method, the instructions comprising:
instructions that cause the system to designate a cover cell in the hierarchical description;
instructions that cause the system to duplicate the cover cell in the memory or the hierarchical layout database, thereby producing a duplicate cover cell;
instructions that cause the system to replace one or more but not all placements of the cover cell in the hierarchical description with the duplicate cover cell; and
instructions that cause the system to redefine at least a portion of the hierarchical description to have at least one fewer level of hierarchy by expanding either the cover cell or the duplicate cover cell, but not both, in the hierarchical description.

US Pat. No. 9,977,080

GENERATING TEST SETS FOR DIAGNOSING SCAN CHAIN FAILURES

Mentor Graphics Corporati...

1. One or more computer-readable media storing a set of test patterns and a set of instructions which, when executed by a tester, causes the tester to test an integrated circuit by:for each of a plurality of test patterns from the set of test patterns:
serially loading each test pattern of the plurality of test patterns into scan chains of the integrated circuit including a faulty scan chain of the integrated circuit; and
capturing a corresponding test response, for each serially loaded test pattern, from system logic of the integrated circuit during a capture phase, wherein the captured corresponding test response is associated with one or more possible faulty scan cells of the faulty scan chain;
wherein the plurality of test patterns have test pattern values selected to isolate a scan chain defect in the faulty scan chain to a single faulty scan cell in the faulty scan chain;
the captured test responses for the plurality of serially loaded test patterns differentiating among the possible faulty scan cells; and
through successive differentiation, identifying the single faulty scan cell in the faulty scan chain.

US Pat. No. 9,684,760

MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING

Mentor Graphics Corporati...

1. A method, comprising:
by a computer, analyzing the behavior of a circuit starting from a seed state for a first number of cycles of operation, wherein
the analyzing comprises verifying a property of the circuit based at least in part on the value of a first proof radius variable
using a first formal verification tool, the first proof radius variable being indicative of an amount of analysis performed
for the property of the circuit without finding a counter-example for the property;

by the computer, analyzing the behavior of the circuit starting from the seed state for a second number of cycles of operation,
wherein the analyzing comprises verifying a property of the circuit based at least in part on the value of a second proof
radius variable using a second formal verification tool, the second proof radius variable being indicative of an amount of
analysis performed for the property of the circuit without finding a counter-example for the property; and

by the computer, comparing the first proof radius and the second proof radius to determine a relative performance of the first
and second formal verification tools.

US Pat. No. 10,120,029

LOW POWER TESTING BASED ON DYNAMIC GROUPING OF SCAN

Mentor Graphics Corporati...

1. An integrated circuit, comprising:a test stimulus source;
a controller;
a plurality of scan chains; and
a grouping and selection unit having inputs coupled to the test stimulus source and the controller and having outputs coupled to the plurality of scan chains, wherein the grouping and selection unit is configured to dynamically group scan chains in the plurality of scan chains into a plurality of scan chain groups on a cycle-by-cycle basis, a scan-chain-segment-by-scan-chain-segment basis, or a test-pattern-by-test-pattern basis based on control signals received from the controller, wherein the plurality of scan chain groups formed at one shift clock cycle differ from the plurality of scan chain groups formed at least at one other shift clock cycle, and to selectively output either original values in a test pattern outputted by the test stimulus source or a constant value to each scan chain group in the plurality of scan chain groups based on the control signals received from the controller, wherein the constant value replaces the original values in the test pattern directed to at least one but not all of the plurality of scan chain groups during at least a set of continuous shift clock cycles while shifting the test pattern into the plurality of scan chain groups.

US Pat. No. 9,983,914

MEMORY CORRUPTION PROTECTION BY TRACING MEMORY

Mentor Graphics Corporati...

1. A method comprising:requesting, by a memory verification tool implemented by a computing system, that an operating system implemented by the computing system allocate a virtual address space to the memory verification tool, wherein the virtual address space is designated for use by an application implemented by the computing system;
utilizing, by the memory verification tool implemented by the computing system, the virtual address space to form a memory pool having multiple protectable slots available for allocation to the application;
intercepting, by the memory verification tool implemented by the computing system, a memory allocation request issued by the application to the operating system of the computing system; and
allocating, by the memory verification tool implemented by the computing system, at least one of the protectable slots in the memory pool to the application in response to the intercepted memory allocation request.

US Pat. No. 9,898,388

NON-INTRUSIVE SOFTWARE VERIFICATION

Mentor Graphics Corporati...

7. A system comprising:
a memory system configured to store computer-executable instructions; and
a computing system which, in response to execution of the computer-executable instructions, is configured to:
simulate an embedded system including a processor capable of executing embedded software;
translate source code for the embedded software into a software image configured as a native instruction set for the processor
in the embedded system, which generates debug information corresponding to the software image;

compile the software image corresponding to the embedded software into a format capable of execution by the computing system;
select, based on the debug information corresponding to the software image, one or more scripts from a plurality of scripts;
insert the one or more scripts into the compiled software image at locations determined based, at least in part, on the debug
information corresponding to the software image; and

execute the compiled software image and the one or more scripts, wherein the execution of the compiled software image simulates
execution of the embedded software by the processor in the simulated embedded system, and wherein the execution of the one
or more scripts configures the computing system to gather information corresponding to execution of the embedded software.

US Pat. No. 9,824,169

REGRESSION SIGNATURE FOR STATISTICAL FUNCTIONAL COVERAGE

Mentor Graphics Corporati...

1. A method comprising:
capturing, by a computing system, events performed during a simulation of a circuit design with a regression, wherein at least
a portion of the circuit design is provided for subsequent design and manufacturing of electronic devices;

identifying, by the computing system, that one or more combinations of the captured events correspond to one or more system
level coverage points for system level functionality of the circuit design;

populating, by the computing system, nodes of a matrix with indications that the identified combinations of the captured events
covered the system level coverage points for the system level functionality of the circuit design, wherein each node in the
matrix correspond to a different combination of the events capable of occurring during the simulation; and

utilizing, by the computing system, the indications in the matrix to determine whether the system level functionality covered
by the combinations of the captured events was previously uncovered for the circuit design.

US Pat. No. 9,778,316

MULTI-STAGE TEST RESPONSE COMPACTORS

Mentor Graphics Corporati...

1. An apparatus for compacting test responses of a circuit-under-test, the apparatus comprising:
a spatial compactor comprising a plurality of compactor inputs and a compactor output;
error detection logic coupled to the compactor output and having an error detection logic output, the error detection logic
being configured to detect whether a test response bit output from the compactor output is an expected test response bit;

masking logic coupled to the error detection logic output, the masking logic having a masking logic output; and
a shift register comprising a plurality of shift register inputs and a register output, one of the shift register inputs being
coupled to the masking logic output, the shift register being operable to load bits in parallel through the shift register
inputs and to output the bits through the register output.

US Pat. No. 9,946,823

DYNAMIC CONTROL OF DESIGN CLOCK GENERATION IN EMULATION

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer emulation system, comprising:searching for clock-enabling logic along clock signal paths of a specific clock signal in a circuit design;
identifying, based on the clock-enabling logic, one or more clock-enabling functions that determine whether the specific clock signal passes the clock-enabling logic;
determining, based on the one or more clock-enabling functions, clock status logic that generates a clock status signal indicating whether the specific clock signal is disabled for a period of time in the circuit design; and
emulating the circuit design with the computer emulation system, the emulating including accelerating, in response to the clock status signal indicating that the specific clock signal is disabled, generation of an active clock signal during the period of time.

US Pat. No. 9,720,041

SCAN-BASED TEST ARCHITECTURE FOR INTERCONNECTS IN STACKED DESIGNS

Mentor Graphics Corporati...

21. A method comprising:
receiving, by a first input of a mixing device of an integrated circuit, data from a through-silicon via of the integrated
circuit;

receiving, by a second input of the mixing device, data from an output of a first scan cell, wherein a scan chain of the integrated
circuit comprises the first scan cell and a second scan cell;

combining, by the mixing device, the data from the through-silicon via and the data from the output of the first scan cell;
providing, via an output of the mixing device, data resulting from the combining to selection circuitry of the integrated
circuit; and

selecting, by the selection circuitry, in accordance with a control signal, between providing an input of the second scan
cell with the data from the output of the first scan cell or the data resulting from the combining.

US Pat. No. 9,569,572

SELECTIVELY LOADING DESIGN DATA FOR LOGICAL EQUIVALENCY CHECK

Mentor Graphics Corporati...

1. A method comprising:
generating, by a computing system, a module hierarchy for modules in a circuit design;
selectively parsing, by the computing system, a subset of the modules in the circuit design based, at least in part, on the
generated module hierarchy for the modules in the circuit design; and

utilizing, by the computing system, the parsed subset of the modules to determine logical equivalence of the circuit design
with at least another circuit design.

US Pat. No. 9,984,193

SYSTEM TO COMBAT DESIGN-TIME VULNERABILITY

Mentor Graphics Corporati...

1. A method comprising:incorporating, by a computing system, a security co-processor into a circuit design modeling an electronic device;
configuring, by the computing system, the security co-processor to monitor messages on an interconnect transmitted by an electronic component in the electronic device; and
loading, by the computing system, one or more rules defining permissibility of the monitored messages on the interconnect in the electronic device, wherein the security co-processor is configured to utilize the rules to identify the monitored messages on the interconnect correspond to an unauthorized operation performed by the electronic component in the electronic device.

US Pat. No. 10,089,425

RESOURCE MAPPING IN A HARDWARE EMULATION ENVIRONMENT

MENTOR GRAPHICS CORPORATI...

1. A method, comprising:receiving a request to load an integrated circuit design to a hardware emulator, wherein the request comprises a resource identifier indicating a first set of one or more printed circuit boards of the hardware emulator;
determining that a printed circuit board in the first set of one or more printed circuit boards is unavailable;
determining a second set of one or more printed circuit boards corresponding to the integrated circuit design, wherein the second set of one or more printed circuit boards is available; and
modifying the resource identifier to indicate the second set of one or more printed circuit boards.

US Pat. No. 9,048,941

CHARACTERISTIC RESPONSE EXTRACTION FOR NON-LINEAR TRANSMIT CHANNELS

Mentor Graphics Corporati...

1. A method comprising:
identifying which bit transitions in a test input to a channel in an electronic device are capable of introducing non-linearity
on the channel;

determining, by a computing system, a characteristic response that models non-linear characteristics of the channel, wherein
the characteristic response includes a first component corresponding to the non-linear characteristics of the channel and
a second component corresponding to linear characteristics of the channel, and wherein determining the characteristic response
of the channel comprises deriving the first component of the characteristic response based, at least in part, on the identified
bit transitions in the test input to the channel and a measured test output from the channel in response to the test input;
and

predicting, by the computing system, signal integrity associated with the channel based, at least in part, on the characteristic
response of the channel.

US Pat. No. 10,289,872

SECURE MECHANISM FOR FINITE PROVISIONING OF AN INTEGRATED CIRCUIT

Mentor Graphics Corporati...

1. A method comprising:configuring security circuitry of an electronic system to enable active circuitry in the electronic system for an authorized number of times based on a key code in an enrollment message received by the security circuitry, wherein the enrollment message includes an enablement quantity configured to identify the authorized number of times the security circuitry is capable of enabling the active circuitry in the electronic system;
detecting, by the security circuitry, an enablement event associated with the electronic system;
in response to the detection of the enablement event, determining, by the security circuitry, a number of times the security circuitry has previously enabled the active circuitry; and
generating, by the security circuitry, enablement signals when the determined number of times the security circuitry has previously enabled the active circuitry is fewer than the authorized number of times, wherein the active circuitry is configured to be enabled to perform operations in response to the enablement signals from the security circuitry.

US Pat. No. 9,910,943

DISTRIBUTED STATE AND DATA FUNCTIONAL COVERAGE

Mentor Graphics Corporati...

1. A method comprising:
correlating, by a computing system, transactions captured during simulation of a circuit design to distributed states for
multiple components in the circuit design, wherein the distributed states for the multiple components correspond to operational
states of the multiple components while the multiple components are functionally-interrelated during the simulation of the
circuit design;

identifying, by the computing system, at least a portion of the distributed states for the multiple components correspond
to system level coverage events; and

generating, by the computing system, a graphical presentation to illustrate the portion of the distributed states for the
multiple components in the circuit design that correspond to system level coverage events.

US Pat. No. 9,817,934

MULTI-FPGA PROTOTYPING OF AN ASIC CIRCUIT

Mentor Graphics Corporati...

1. A method of generating configuration data for a prototype, the prototype comprising a plurality of programmable devices
interconnected by a plurality of physical tracks, the method comprising:
receiving, using a computer, a logic design for implementation on the prototype, the logic design comprising a hierarchy of
interconnected logic modules;

creating, using the computer, a new hierarchy of logic modules comprising a group of logic modules preserved from the received
logic design and flattened logic corresponding to logic modules from the received logic design that are flattened;

partitioning, using the computer, the new hierarchy of logic modules into regions, each region comprising one or more programmable
chips, while reducing a cost function based on a number of multiplexed signals of a critical combinatorial path and an amount
of inter-region communications on the physical tracks connecting the programmable devices; and

generating, using the computer, the configuration data for the prototype, the configuration data comprising routing assignments
among the programmable devices using the physical tracks of the prototype.

US Pat. No. 9,714,981

TEST-PER-CLOCK BASED ON DYNAMICALLY-PARTITIONED RECONFIGURABLE SCAN CHAINS

Mentor Graphics Corporati...

1. A method, comprising:
shifting test stimuli into a first portion of a plurality of scan chains in a circuit one bit per scan chain to form a new
test pattern;

applying the new test pattern to the circuit;
shifting out previously compacted test response data stored in a second portion of the plurality of scan chains one bit per
scan chain;

compacting a test response corresponding to the new test pattern with the previously compacted test response data to generate
newly compacted test response data in the second portion of the plurality of scan chains; and

repeating the above operations for a predetermined number of times.

US Pat. No. 9,619,600

THIRD PARTY COMPONENT DEBUGGING FOR INTEGRATED CIRCUIT DESIGN

Mentor Graphics Corporati...

1. A computer-readable storage having instructions thereon for being executed by a processor to perform a method, the method
comprising:
generating a verification model that represents an electronic design including a proprietary component and one or more design
components coupled to the proprietary component, wherein generating the verification model includes inserting an instrumentation
component between the proprietary component and the design components so that the proprietary component is coupled to both
the design components and the instrumentation component and so that the instrumentation component captures signals passing
between the proprietary component and the design components, and wherein the electronic design is a design of an electronic
circuit;

implementing the verification model using a verification tool;
determining a state of the verification model at a first point in time of a verification process applied to the implemented
verification model by the verification tool;

determining one or more signal values on one or more signal lines that interconnect the proprietary component with the design
components from the first point during the verification process until a second point in time during the verification process;
and

generating a reference model for the electronic design from the verification model.

US Pat. No. 10,025,602

PRELINKED EMBEDDING

Mentor Graphics Corporati...

1. A method comprising:parsing, by a computing system, a first available read-only memory address and a first available writable memory address from a root-kernel image;
identifying, by the computing system, exported symbols of the root-kernel image;
pre-linking, by the computing system, one or more dynamically-linkable executable modules against the exported symbols of the root-kernel image to generate pre-linked executable modules;
inserting, by the computing system, the pre-linked executable modules into the root-kernel image, which embeds the pre-linked executable modules in the root-kernel image to generate a pre-linked embedded root-kernel image; and
loading, by the computing system, a first portion of the pre-linked embedded root-kernel image into a read-only portion of a memory in an embedded system based on the read-only memory address, and loading a second portion of the pre-linked embedded root-kernel image into a writable portion of the memory in the embedded system based on the writable memory address, wherein at least one processing device in the embedded system is configured to execute the embedded pre-linked executable modules directly from the memory.

US Pat. No. 9,836,043

HARNESS SUB-ASSEMBLY RATIONALIZATION

Mentor Graphics Corporati...

1. A method comprising:
generating, by a computing system in response to execution of instructions, a structured bill of materials for a wire harness
described in a harness design;

utilizing, by the computing system in response to execution of the instructions, a parameterized signature generated based,
at least in part, on a variable parameter corresponding to a physical characteristic for a first sub-assembly in the structured
bill of materials for the wire harness to identify a second sub-assembly stored in a library accessible by the computing system;
and

substituting, by the computing system in response to execution of the instructions, the first sub-assembly in the structured
bill of materials for the wire harness with the second sub-assembly.

US Pat. No. 9,836,569

LEAKAGE REDUCTION USING STRESS-ENHANCING FILLER CELLS

Mentor Graphics Corporati...

1. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors
to perform a method, the method comprising:
determining an optimization zone in a row of cells on a layout design, the optimization zone being a portion of the row of
cells between two consecutive fixed cells, the optimization zone comprising unfixed cells and one or more filler cells, the
fixed cells being functional cells of which positions cannot be changed, and the unfixed cells being functional cells of which
positions can be changed; and

inserting stress-increasing filler cells into the optimization zone to replace some or all of the one or more filler cells
while cell placement of the optimization zone is adjusted based on a leakage reduction analysis;

wherein the layout design describes an integrated circuit device or micro-electromechanical system (MEMS) device to be manufactured.

US Pat. No. 9,651,622

ISOMETRIC TEST COMPRESSION WITH LOW TOGGLING ACTIVITY

Mentor Graphics Corporati...

1. A method comprising:
for each of a plurality of faults, determining, by one or more computing devices, a plurality of probability values associated
with observing a fault along a plurality of propagation paths of a circuit design;

generating, by the one or more computing devices, a plurality of residual test cubes by at least, for each of the plurality
of faults, generating a corresponding residual test cube for the fault based on determining that one or more from the plurality
of probability values are above a predefined threshold; and

generating, by the one or more computing devices, test templates based on merging the plurality of residual test cubes.

US Pat. No. 9,664,739

CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES

Mentor Graphics Corporati...

1. A system, comprising:
a circuit comprising a decompressor, the decompressor comprising a linear feedback shift register (LFSR); and
automatic testing equipment located external to the circuit,
wherein the decompressor is configured to load compressed test pattern data from an output of the automatic testing equipment
through an input logic gate of the LFSR, the input logic gate of the LFSR being configured to receive the compressed test
pattern data and logically combine the compressed test pattern data with data stored within the LFSR concurrently as the decompressor
outputs decompressed test pattern data.

US Pat. No. 10,120,019

AUTOMATED METHOD FOR ANALYZING A BOARD HAVING A PLURALITY OF FPGA COMPONENTS

Mentor Graphics Corporati...

1. An automated method for developing a multi-FPGA prototype of an application-specific integrated circuit (ASIC), wherein the multi-FPGA prototype is implemented on an electronic board having a plurality of FPGA-type programmable chips (FPGAs) including a first FPGA and a second FPGA, the method comprising:segmenting a netlist of the ASIC according to a number of the plurality FPGAs;
constructing a synchronization graph having a plurality of edges which correspond to communication paths of the netlist from respective originating sequential cells to respective destination sequential cells;
in at least one case where a subset of the communication paths being communicated between the first and second FPGAs exceeds a number of physical connections between the first and second FPGAs on the electronic board:
determining travel times of each of the subset of the communication paths for respective signals by combining:
a first intra-FPGA travel time corresponding to time required to perform one or more logical operations within the first FPGA on the respective signal;
an inter-FPGA travel time for an inter-chip portion of the each communication path between the first FPGA to the second FPGA; and
a second intra-FPGA travel time corresponding to time required to perform one or more logical operations within the second FPGA on the respective signal;
integrating one or more serializers and one or more deserializers into the first and second FPGAs to multiplex selected ones of the subset of communication paths, wherein one or more of the selected communication paths have lower travel time and higher degree of multiplexing than one or more non-selected communication paths of the subset of communication paths; and
configuring the electronic board to implement the ASIC netlist and the integrated serializer(s) and deserializer(s).

US Pat. No. 10,019,337

CLASS OBJECT HANDLE TRACKING

Mentor Graphics Corporati...

1. A method comprising:identifying, by a computing system, locations in source code of a test bench that correspond to memory pointers for class objects capable of generation during simulation of the test bench and a circuit design;
inserting, by the computing system, handle tracking code at the locations in the test bench that were identified as corresponding to the memory pointers for the class objects;
generating, by the computing system, handle occupancies corresponding to the memory pointers for the class objects in response to execution of the handle tracking code during the simulation of the test bench and the circuit design;
synchronizing, by the computing system, the handle occupancies with portions of source code in the test bench based on the identified locations; and
prompting, by the computing system, presentation in a debug window of the handle occupancies, and presentation of the portions of source code in the test bench associated with the handle occupancies based on the synchronization.

US Pat. No. 9,898,562

DISTRIBUTED STATE AND DATA FUNCTIONAL COVERAGE

Mentor Graphics Corporati...

1. A method comprising:
simulating, by a computing system, a circuit design with test stimulus from a test bench;
identifying, by the computing system, multiple components in the circuit design that became functionally-interrelated during
the simulation of the circuit design based, at least in part, on data transactions generated during the simulation of the
circuit design; and

correlating, by the computing system, information captured during simulation that corresponds to the identified components
while the identified components were functionally-interrelated during the simulation of the circuit design, wherein the correlated
information is configured to identify at least one distributed state coverage event for the test bench.

US Pat. No. 9,898,563

MODELING MEMORY IN EMULATION BASED ON CACHE

Mentor Graphics Corporati...

1. A system comprising:
one or more computing devices configured to model a main memory that is to be accessed by a first circuit design under test;
and

an emulator configured to:
communicate with the one or more computing devices;
emulate the first circuit design under test;
emulate a cache memory that provides a subset of data stored by the main memory;
perform a part of an emulation process for emulating the first circuit design under test; and
during the part of the emulation process, update one or more stored values in the cache memory to synchronize the subset of
the data between the cache memory and the main memory.

US Pat. No. 9,857,693

LITHOGRAPHY MODEL CALIBRATION VIA CACHE-BASED NICHING GENETIC ALGORITHMS

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:
dividing a set of original model candidates into groups of original model candidates, the original model candidates being
derived based on a lithography model for a component of a lithographic process and having different sets of values of model
parameters of the lithography model;

generating child model candidates by performing crossover on each of the groups of original model candidates without mutation;
deriving a set of new model candidates from the original model candidates and the child model candidates, wherein the deriving
comprises:

selecting a group of new model candidates from each of the groups of the original model candidates and the child model candidates
for the each of the groups of original model candidates based on an objective function, the group of new model candidates
having a size equal to that of the each of the groups of the original model candidates,

further selecting, from the each of the groups of the original model candidates and the child model candidates for the each
of the groups of original model candidates, an additional new model candidate based on the objective function if adding the
additional new model candidate increases overall diversity based on a similarity function and a predetermined condition, and

removing one or more new model candidates based on the objective function to keep a number of the new model candidates in
each of niches from exceeding a maximum number, the niches being determined based on the similarity function;

repeating the dividing, the generating and the deriving by replacing the set of original model candidates with the set of
new model candidates until one of one or more predefined conditions is satisfied to obtain a set of final model candidates;
and

reporting one or more final model candidates in the set of final model candidates based on the objective function and the
niches, from which one final model candidate is to be selected as a calibrated lithography model for simulating the lithographic
process.

US Pat. No. 9,836,556

OPTICAL PROXIMITY CORRECTION FOR DIRECTED-SELF-ASSEMBLY GUIDING PATTERNS

Mentor Graphics Corporati...

1. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors
to perform a method, the method comprising:
determining predicted print errors for two or more via-type features based on a predicted guiding pattern for the two or more
via-type features, a target guiding pattern for the two or more via-type features, and correlation information between a plurality
of guiding pattern parameters and location and size parameters for the two or more via-type features, wherein the predicted
guiding pattern is derived based on an initial mask pattern for photomask fabrication and the correlation information comprises
a template error enhancement factor (TEEF); and

adjusting the initial mask pattern to generate a new mask pattern based on the predicted print errors for the two or more
via-type features and the correlation information.

US Pat. No. 9,785,736

CONNECTIVITY-AWARE LAYOUT DATA REDUCTION FOR DESIGN VERIFICATION

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:
identifying a plurality of circuit elements represented in a circuit design model, wherein the circuit design model comprises
netlist information and layout data, and the plurality of circuit elements comprises one or more electrostatic discharge (ESD)
protection elements, one or more input/output (I/O) pads, one or more power supply pads, or any combination thereof;

identifying pin-pairs corresponding to the plurality of circuit elements, wherein the pin-pairs comprise coupled pins;
determining, based on the pin-pairs, one or more nets and one or more cells, wherein at least one of the one or more cells
comprises at least a portion of one or more power supply grids on metal layers;

selecting, based on the one or more nets and the one or more cells, one or more layout geometric elements in the circuit design
model; and

performing, based on the one or more layout geometric elements, a verification operation on the circuit design model.

US Pat. No. 9,727,668

DELTA RETIMING IN LOGIC SIMULATION

Mentor Graphics Corporati...

1. A method comprising:
storing, in a memory, description data representing a simulation model of a system including logic gates interconnected by
signals, wherein the logic gates and the signals have corresponding delta delay cycles ordered to occur in a sequence within
a computer simulated time cycle of the system without advancing the computer simulated time cycle; and

transforming, by a computer, the description data stored in the memory to include a modification that reduces an amount of
the corresponding delta delay cycles in the simulation model of the system, while preserving, within the computer simulated
time cycle, logic values propagated through the logic gates and on the signals, and reduces a projected number of calculations
for performing a computer simulation of the system, thereby reducing a projected simulation time for performing the computer
simulation.

US Pat. No. 9,703,917

IDENTIFICATION OF HIGH IMPEDANCE NODES IN A CIRCUIT DESIGN

Mentor Graphics Corporati...

1. A method comprising:
adding, by a computing system, a noise source to a node in a circuit design;
setting the noise source to a threshold voltage that distinguishes a first set of high impedance nodes from a second set of
high impedance nodes;

computing a value of a voltage at the node;
comparing the value of the voltage at the node to the threshold voltage; and
determining, based on the comparing, whether the node is in the first set of high impedance nodes or the second set of high
impedance nodes.

US Pat. No. 9,673,819

METASTABILITY GLITCH DETECTION

Mentor Graphics Corporati...

1. A system comprising:
a sampling circuit configured to sample an output of a storage element;
a mono-shot circuit configured to monitor the output of the storage element and to generate a pulse when the monitored output
of the storage element differs from the sampled output;

a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch
signal in response to the pulse from the mono-shot circuit; and

an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the
drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.

US Pat. No. 9,477,806

SYSTEM-LEVEL ANALYSIS WITH TRANSACTIONS FROM PROTOCOL PROBES

Mentor Graphics Corporati...

1. A method comprising:
identifying, by a computing system, first transaction data corresponding to a first protocol implemented by an electronic
device, wherein the first transaction data is responsive to test stimulus provided in a verification environment;

identifying, by the computing system, second transaction data corresponding to a second protocol implemented by the electronic
device, wherein the second transaction data is responsive to the test stimulus provided in the verification environment;

correlating, by the computing system and based at least in part on the test stimulus, the first transaction data to the second
transaction data to form correlated transaction data; and

determining, by the computing system and based at least in part on the correlated transaction data, one or more system-level
functions, of the electronic device, covered by the test stimulus.

US Pat. No. 10,716,216

PIXELIZED THERMAL CONDUCTIVITY DETERMINATION FOR PRINTED CIRCUIT BOARDS

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:receiving data of a printed circuit board;
creating a pixelized representation for a conductor layer of the printed circuit board based on the data of a printed circuit board, the pixelized representation having two types of pixels: conductor pixels and dielectric pixels;
analyzing the pixelized representation to identify conductor paths in a direction, the conductor paths being formed by some or all of the conductor pixels;
analyzing the pixelized representation to separate the conductor pixels into net pixels and isolated pixels, the net pixels being pixels on at least one of the conductor paths, and the isolated pixels being pixels on none of the conductor paths;
computing an effective thermal conductivity property value in the direction for a section or a whole of the conductor layer based on a number of the isolated pixels, a number of the net pixels and a number of total pixels in the section or the whole of the conductor layer; and
storing the effective thermal conductivity property value on a non-transitory computer-readable medium.

US Pat. No. 10,067,425

CORRECTING EUV CROSSTALK EFFECTS FOR LITHOGRAPHY SIMULATION

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:receiving layout data for one or more layout designs;
determining isolated mask feature component diffraction signals associated with individual isolated layout feature components in the one or more layout designs based on a component-based mask diffraction modeling method;
determining mask feature component diffraction signals based on the isolated mask feature component diffraction signals, the layout data, and predetermined crosstalk signals, wherein the predetermined crosstalk signals are differences between first isolated mask feature diffraction signals for an isolated layout feature computed using an electromagnetic field solver and second isolated mask feature diffraction signals for the isolated layout feature determined using the component-based mask diffraction modeling method;
processing the one or more layout designs based on the mask feature component diffraction signals; and
storing results of the processed one or more layout designs in a tangible medium.

US Pat. No. 10,013,523

FULL-CHIP ASSESSMENT OF TIME-DEPENDENT DIELECTRIC BREAKDOWN

Mentor Graphics Corporati...

1. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:analyzing a layout design to identify matching patterns that match a pre-calculated pattern in a pattern database, each of pre-calculated patterns in the pattern database having a time-to-failure characteristic value pre-computed based on a model of electric current path generation and evolution, the model of electric current path generation and evolution assuming field-based hopping conductivity of current carriers; and
determining time-to-failure characteristic values for the matching patterns based on the pre-computed time-to-failure characteristic values and electric attributes of geometric elements in each of the matching patterns.

US Pat. No. 9,933,485

DETERMINISTIC BUILT-IN SELF-TEST BASED ON COMPRESSED TEST PATTERNS STORED ON CHIP AND THEIR DERIVATIVES

Mentor Graphics Corporati...

1. A system, comprising:a decompressor configured at least to decompress one of compressed test patterns stored on chip for a predetermined number of times; and
a controller configured at least to output a control signal based on control data stored on chip, outputs of the decompressor being inverted at one or more scan shift clock cycles based on the control signal which enables the system to output the predetermined number of test patterns based on the one of compressed test patterns, wherein the one or more scan shift clock cycles are different for each of the predetermined number of test patterns.

US Pat. No. 9,928,317

ADDITIVE DESIGN OF HEAT SINKS

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:A: determining, using the computer, a location on a heat sink base based on a simulation of a structure in a cooling environment and a predetermined criterion, the structure comprising the heat sink base and a heat source;
B: adding, using the computer, an object to the location to form a new structure;
C: simulating, using the computer, the new structure to determine thermal performance of the new structure; and
D: repeating, using the computer, operations B and C until a predetermined condition regarding design space is met, wherein the repeating comprises:
if the thermal performance of the new structure meets a predetermined condition regarding thermal performance, replacing, using the computer, the location with a new location determined for the new structure based on the simulating and the predetermined criterion for operation B; and
if the thermal performance of the new structure does not meet the predetermined condition regarding thermal performance, removing, using the computer, the added object, designating the location as a location not eligible for the adding, and replacing, using the computer, the location with a new location for the structure selected from locations eligible for the adding based on the predetermined criterion for operation B.

US Pat. No. 9,805,156

SELECTIVE PARASITIC EXTRACTION

Mentor Graphics Corporati...

1. A method comprising:
determining, by a computing system, locations of nets in a physical layout of a circuit design;
identifying, by the computing system, a plurality of areas in the physical layout according to a space filling curve that
defines each of the plurality of areas in a sequential order, wherein each of the plurality of areas includes one or more
of the plurality of areas previously defined in the sequential order;

sequentially extracting, by the computing system in each of the plurality of areas, nets that are encapsulated within a respective
area of the plurality of areas, wherein the nets correspond to electrical paths between pins in the physical layout of the
circuit design;

generating, by the computing system, electrical representations of the sequentially extracted nets; and
generating, by the computing system, a netlist for the circuit design that includes the electrical representations generated
from the sequentially extracted nets.

US Pat. No. 9,773,085

SYSTEM DESIGN MANAGEMENT

Mentor Graphics Corporati...

1. A method comprising:
generating, by a computing system, a meta model having a plurality of objects with assigned attributes defining characteristics
for a system-level design of an electronic system, wherein the meta-model includes one or more conditional action statements
associated with the attributes;

correlating, by the computing system, electronic design data generated by a plurality of electronic design automation tools
to the objects in the meta model;

comparing, by the computing system, a condition in at least one of the conditional action statements to the electronic design
data correlated to the objects in the meta model; and

selectively performing, by the computing system, one or more actions defined in the conditional action statements based, at
least in part, on the comparison of the condition to the electronic design data correlated data to the objects in the meta
model.

US Pat. No. 9,734,273

SYSTEM DESIGN MANAGEMENT

Mentor Graphics Corporati...

1. A method comprising:
generating, by a computing system, a framework for a system-level design of an electronic system, wherein the framework for
the system-level design includes a plurality of objects corresponding to a plurality of different portions of the system-level
design, and wherein each of the objects is assigned one or more attributes configured to define one or more characteristics
for design data expected to be correlated with at least one of the portions of the system-level design;

correlating, by the computing system, a plurality of design components in a plurality of electronic circuit designs generated
by a plurality of electronic design automation tools to the objects corresponding to the different portions of the system-level
design;

comparing, by the computing system, the design components in the electronic circuit designs to the characteristics for the
design data defined by the attributes of the objects correlated to the design components in the electronic circuit designs;
and

determining, by the computing system, whether the electronic circuit designs are congruent with the system-level design based,
at least in part, on the comparison of the design components in the electronic circuit designs to the characteristics for
the design data defined by the attributes of the objects in the framework for the system-level design.

US Pat. No. 9,720,040

TIMING-AWARE TEST GENERATION AND FAULT SIMULATION

Mentor Graphics Corporati...

1. A method of generating test patterns for testing an integrated circuit, comprising:
simulating a response of an integrated circuit design to a test pattern in the absence of any faults in the integrated circuit
design;

identifying paths sensitized by the test pattern by backward tracing from the observation points of the integrated circuit
design and analyzing sensitization conditions in the integrated circuit design, the sensitization conditions including reconvergent
path sensitization conditions;

identifying a fault detected by the test pattern by simulating a response of the integrated circuit design to the test pattern
in the presence of the fault and determining that one or more of the identified paths detect the fault;

determining a path delay for the one or more paths that detect the fault; and
storing the path delay.

US Pat. No. 9,703,916

STREAMING, AT-SPEED DEBUG AND VALIDATION ARCHITECTURE

Mentor Graphics Corporati...

1. A method comprising:
incorporating, by a computing system, a validation system into a circuit design, wherein the validation system includes multiple
validation devices configured to monitor at least a portion of an electronic device described in the circuit design, and wherein
the validation devices are arranged in a serial pipelined configuration with each of the validation devices configured to
transmit signals on each of a plurality of communication buses;

identifying, by the computing system, trace signals associated with the electronic device to route to the validation system;
and

configuring, by the computing system over one of the communication buses in the serial pipelined configuration, the validation
system to detect one or more conditional events from one or more trigger signals routed to the validation system from the
electronic device, wherein the validation system is configured to transmit at least one of the trace signals associated with
the electronic device, over another one of the communication buses in the serial pipelined configuration, for debugging in
response to a detection of at least of the conditional events.

US Pat. No. 9,607,122

TIMING DRIVEN CLOCK TREE SYNTHESIS

Mentor Graphics Corporati...

1. A method comprising:
determining, by a computing system, data arrival timing and clock arrival timing at multiple clock-driven circuits in a circuit
design describing at least a portion of an electronic device; and

performing, by the computing system, clock tree synthesis (CTS) on the circuit design, which synthesizes an unbalanced clock
tree for the circuit design and utilizes the data arrival timing relative to the clock arrival timing at the multiple clock-driven
circuits to initially balance the unbalanced clock tree for the circuit design, wherein the initial balancing of the unbalanced
clock tree alters a clock signal path in the unbalanced clock tree to provide a clock signal to each of the multiple clock-driven
circuits with a new clock arrival timing that is synchronized with the data arrival timing for the multiple clock-driven circuits,
and wherein the electronic device is capable of being manufactured based, at least in part, on the circuit design.

US Pat. No. 10,237,097

WORST CASE EYE FOR MULTI-LEVEL PULSE AMPLITUDE MODULATED LINKS

Mentor Graphics Corporati...

1. A method comprising:characterizing a channel of an electronic device capable of communicating signals encoding data in more than two value levels, wherein the characterization of the channel identifies multiple step responses of the channel, each step response corresponding to a transition between a plurality of the value levels;
determining, by a computing system, distribution boundaries of the signals at each of the value levels by deriving, for each of the value levels, voltages of the signals capable of being communicated on the channel based, at least in part, on the step responses of the channel, and identifying a maximum voltage and a minimum voltage of the signals for each of the value levels based on the derived voltages of the signals, wherein the distribution boundaries correspond to the maximum voltage and the minimum voltage of the signals at each of the value levels; and
predicting, by the computing system, a signal integrity of the channel based, at least in part, on the distribution boundaries of the signals at each of the value levels.

US Pat. No. 10,127,343

CIRCUIT DESIGN LAYOUT IN MULTIPLE SYNCHRONOUS REPRESENTATIONS

Mentor Graphics Corporati...

1. A method comprising:receiving, by a printed circuit board layout tool implemented with a computing system, a mechanical design from a mechanical system, wherein the mechanical design describes a physical structure of a product to include an electronic device comprising a printed circuit board coupled with one or more components;
generating, by the printed circuit board layout tool implemented with the computing system, a design rule describing a physical limitation for the electronic device based on a mechanical constraint in the mechanical design;
altering, by the printed circuit board layout tool implemented with the computing system, a first layout representation for a circuit design describing the electronic device;
automatically augmenting, by the printed circuit board layout tool implemented with the computing system, a second layout representation for the circuit design in response to the alteration of the first layout representation for the circuit design describing the electronic device, which synchronizes the second layout representation for the circuit design describing the electronic device with the first layout representation for the circuit design describing the electronic device; and
in response to the alteration of the first layout representation for the circuit design describing the electronic device, automatically performing, by the printed circuit board layout tool implemented with the computing system, at least one design rule check to compare the augmented second layout representation for the circuit design describing the electronic device with the physical limitation for the electronic device described in the design rule, wherein the electronic device, when manufactured utilizing at least one of the first layout representation for the circuit design or the second layout representation for the circuit design, is configured for inclusion in the product.

US Pat. No. 10,049,442

VIDEO INSPECTION SYSTEM WITH AUGMENTED DISPLAY CONTENT

Mentor Graphics Corporati...

1. A method comprising:capturing an image of a printed circuit board (PCB) assembly;
synchronizing, by a computing system, at least a portion of a layout design of the PCB assembly with the image of the PCB assembly;
analyzing, by the computing system, the image of the PCB assembly to recognize that a rework tool points to a selected portion of the PCB assembly; and
augmenting, by the computing system, the image of the PCB assembly corresponding to the selected portion of the PCB assembly pointed to by the rework tool to include the portion of the layout design of the PCB assembly based, at least in part, on the synchronization of the image of the PCB assembly and the portion of the layout design of the PCB assembly.

US Pat. No. 9,990,452

LOW POWER CORRUPTION OF MEMORY IN EMULATION

Mentor Graphics Corporati...

1. A method comprising:configuring an emulator to emulate a circuit design that is associated with a main memory, wherein the main memory is being modeled by one or more computing devices in communication with the emulator;
configuring the emulator to emulate a cache memory that provides a subset of data stored by the main memory;
performing, using the emulator, a part of an emulation process for emulating the circuit design; and
during the part of the emulation process;
updating stored values in the cache memory to synchronize the subset of the data between the cache memory and the main memory,
responsive to determining that a power domain associated with the main memory is powered down, setting one or more values in the cache memory to indicate that the subset of data is corrupted, and
based on determining that the circuit design is to perform a first read or write operation to the main memory, accessing the cache memory and determining whether the one or more values indicate that the subset of the data is corrupted.

US Pat. No. 9,886,178

USER INTERFACES

Mentor Graphics Corporati...

1. A method of processing image data, the method being carried out in an electronic device, the device having processing circuitry,
memory and a display device, the method comprising:
performing a transformation operation on a first image data of at least one two-dimensional graphical component to generate
second image data, the second image data defining, for the at least one graphical component, a modified form of the graphical
component;

performing a second operation comprising: determining whether a first graphical component that is in modified form intersects
with a concurrently displayed second graphical component that is in modified form; and, if they are intersecting, determining
whether to merge the first and second intersecting graphical components, based on a sum of areas of the first and second intersecting
graphical components; and

subsequent to the second operation and based on a determination that at least one of the first and second graphical components
comprises a dirty region, displaying, using said second image data, the modified form of the first graphical component,

wherein the at least one graphical component has the appearance of having a component of dimension perpendicular the plane
of the display device.

US Pat. No. 9,881,113

LAYOUT SYNTHESIS OF A THREE-DIMENSIONAL MECHANICAL SYSTEM DESIGN

Mentor Graphics Corporati...

1. A method comprising:
importing, by a computing system implementing an electronic design system, a three-dimensional mechanical model from a mechanical
design system, wherein the three-dimensional mechanical model includes a folded representation of a substrate having a curved
surface;

utilizing, by the computing system, the curved surface of the substrate in the three-dimensional mechanical model to identify
one or more bends in the folded representation of the substrate included in the three-dimensional mechanical model; and

generating, by the computing system, a two-dimensional layout representation of the substrate for the electronic design system
for placement of electronic components and electrical connections by unfolding the one or more bends in the folded representation
of the substrate into the two-dimensional layout representation of the substrate.

US Pat. No. 9,767,237

TARGET CAPTURE AND REPLAY IN EMULATION

Mentor Graphics Corporati...

1. A method comprising:
performing, using an emulator that is coupled to one or more targets and that is associated with a clock for infrastructure
of the emulator and a clock for a circuit design under test by the emulator, a part of an emulation process;

during the performing of the part of the emulation process:
capturing, while running the clock for the infrastructure of the emulator and the clock for the circuit design, one or more
input signals that are being communicated to the emulator from the one or more targets,

communicating, while running the clock for the infrastructure of the emulator and the clock for the circuit design, the one
or more input signals out of the emulator, and

storing the one or more input signals in one or more processor-readable media;
decoupling the emulator from the one or more targets;
repeating, after the decoupling, the part of the emulation process; and
during the repeating of the part of the emulation process, communicating, while running the clock for the infrastructure of
the emulator and the clock for the circuit design, the one or more input signals to the emulator from the one or more processor-readable
media.

US Pat. No. 9,703,579

DEBUG ENVIRONMENT FOR A MULTI USER HARDWARE ASSISTED VERIFICATION SYSTEM

Mentor Graphics Corporati...

1. An emulation environment for debugging an electronic design concurrently emulated with other electronic designs, the emulation
environment comprising:
an emulation system including an emulator including configurable hardware and connection structure to interconnect the configurable
hardware, the emulator configurable to implement multiple electronic designs, emulated simultaneously using the configurable
hardware, as a combined model of the multiple electronic designs, an emulation clock manager configured to maintain independent
clocks for the multiple electronic designs, and a virtual model link configured to facilitate message traffic with the emulator;

an emulation trace module configured to capture trace data from a selected one or more of the multiple electronic designs
during operation of the emulator; and

a model state module comprising memory circuitry within the emulator configured to capture state data corresponding to a selected
one or more of the multiple electronic designs during operation of the emulator.

US Pat. No. 9,626,474

EXPANDED CANONICAL FORMS OF LAYOUT PATTERNS

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:
transforming coordinates of vertices of geometric elements in a window of a layout design into new coordinates of the vertices,
wherein the coordinates of vertices do not comprise clipped coordinates and the transforming comprises:

performing a translation on the coordinates of vertices based on differences between maximum and minimum X coordinate values
of the vertices and between maximum and minimum Y coordinate values of the vertices, wherein the clipped coordinate values
are not considered; and

determining canonical form coordinates of the vertices for a plurality of windows based on a sum of X coordinate values of
the new coordinates of the vertices and a sum of Y coordinate values of the new coordinates of the vertices, the plurality
of windows comprising the window, being centered in the same location as the window, and having different sizes.

US Pat. No. 10,509,073

TIMING-AWARE TEST GENERATION AND FAULT SIMULATION

Mentor Graphics Corporati...

1. A method of generating test patterns for testing an integrated circuit, comprising:identifying a fault that is detected by a test pattern by simulating a response of an integrated circuit design to the test pattern in the presence of the fault and identifying one or more paths that are sensitized by the test pattern and that detect the fault;
computing a static path delay for a selected sensitized path through the identified fault;
determining whether a criterion based at least in part on the static path delay is met for the identified fault;
modifying a fault list by removing the identified fault if the criterion is met; and
storing the modified fault list,
wherein either:
(a) the selected sensitized path is the longest sensitized path, and the act of determining whether the criterion is met comprises determining whether:
where PDfs is the static path delay through the longest sensitized path for the fault f, TTC is the test clock period, and ? is a real number between 0 and 1; or(b) wherein the selected sensitized path is the shortest sensitized path, and the act of determining whether the criterion is met comprises determining whether:
where HPDfs is the static path delay through the shortest sensitized path for the fault f, TTC is the test clock period, and ? is a real number between 0 and 1.

US Pat. No. 10,348,509

TOLERANT OF ABSOLUTE OFFSETS PHYSICAL UNCLONABLE FUNCTION DEVICE

Mentor Graphics Corporati...

1. A method comprising:sampling a physical unclonable function unit in a physical unclonable function device to identify a plurality of outputs;
determining a width of a distribution of values corresponding to the sampled outputs;
setting a scale for the physical unclonable function unit based, at least in part, on the width of the distribution of values corresponding to the sampled outputs;
identifying a transform for the physical unclonable function unit based, at least in part, on the scale for the physical unclonable function unit;
configuring the physical unclonable function device to perform the transform on a future output of the physical unclonable function unit, wherein the physical unclonable function device is configured to generate an identifier based, at least in part, on a result of performance of the transform on the future output of the physical unclonable function unit;
when the result of the performance of the transform on the future output of the physical unclonable function unit corresponds to a multi-bit value, identifying a different transform to perform on the multi-bit result, which reduces the multi-bit value to a single bit; and
configuring the physical unclonable function device to perform the different transform on the multi-bit result, wherein the physical unclonable function device is configured to generate an identifier based, at least in part, on a result of the different transform on the multi-bit result.

US Pat. No. 10,133,803

COVERAGE DATA INTERCHANGE

Mentor Graphics Corporati...

1. A method comprising:extracting, by a computing system, coverage data from a source database with application program interface (API) routines specific to the source database;
classifying, by the computing system, the coverage data according to a Unified Coverage Interoperability Standard (UCIS)-compliant format by identifying objects in the extracted coverage data, determining coverage data types for the identified objects based on the API routines specific to the source database utilized to extract the coverage data, and transferring the extracted coverage data corresponding to the identified objects with exchange routines selected based on the coverage data types;
utilizing, by the computing system, the classification of the coverage data to identify corresponding API routines specific to a target database; and
writing, by the computing system, the coverage data to the target database with the identified API routines.

US Pat. No. 9,959,379

HYBRID COMPILATION FOR FPGA PROTOTYPING

Mentor Graphics Corporati...

1. One or more computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:generating, based on an original RTL (register-transfer level) design for a circuit design, an initial FPGA-mapped netlist and a generic RTL design, the generic RTL design being functionally equivalent to the initial FPGA-mapped netlist and maintaining one-to-one correspondence to the initial FPGA-mapped netlist in terms of design hierarchy for at least a part of the circuit design;
partitioning, based on the initial FPGA-mapped netlist, the circuit design into design partitions for implementing the circuit design across a plurality of FPGA chips, each of the design partitions corresponding to a partition of the generic RTL design and to a partition of the initial FPGA-mapped netlist; and
generating final FPGA-mapped netlists based on the design partitions, wherein the design partitions are represented by the partitions of the generic RTL design, or some of the design partitions are represented by the partitions of the generic RTL design and each of the rest of the design partitions is represented by a combination of the generic RTL design and the initial FPGA-mapped netlist.

US Pat. No. 9,940,428

HIERARCHICAL FILL IN A DESIGN LAYOUT

Mentor Graphics Corporati...

1. A method comprising:receiving, by a computing system, a circuit design layout and a captured hierarchy of the circuit design layout, wherein the captured hierarchy was generated by a downstream design rule check tool, and wherein the captured hierarchy categorizes design data in the circuit design layout into multiple cells having a hierarchical organization;
identifying, by the computing system, multiple portions of the circuit design layout from the cells in the captured hierarchy; and
modifying, by the computing system, the circuit design layout by performing separate fill operations on the portions of the circuit design layout identified from the cells in the captured hierarchy, wherein the fill operations add fill structures to the portions of the circuit design layout, wherein the downstream design rule check tool performs design rule checking operations after the modification of the circuit design layout with the addition of the fill structures.

US Pat. No. 9,915,702

CHANNEL SHARING FOR TESTING CIRCUITS HAVING NON-IDENTICAL CORES

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:
generating compressed test patterns for a plurality of circuit blocks comprising identical and non-identical circuit blocks,
wherein the plurality of circuit blocks are components of a circuit design, each of the plurality of circuit blocks comprises
a decompressor configured to decompress the compressed test patterns and a compactor configured to compact test response data,
and the generating comprises determining control data for each of non-identical circuit blocks in the plurality of circuit
blocks, the control data further being for control data input channels that are respectively dedicated to each of the non-identical
circuit blocks and that are separate and different from each other, wherein a plurality of the identical circuit blocks in
the plurality of circuit blocks share the same control data input channel; and

storing the compressed test patterns and the control data.

US Pat. No. 9,874,606

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

Mentor Graphics Corporati...

1. One or more non-transitory machine-readable storage media storing computer-readable instructions that when executed by
a computer, cause the computer to perform a method, the instructions comprising:
instructions for generating mask data indicating patterns of unknown states for which to mask test responses received from
scan cells in an integrated circuit;

instructions for storing the mask data in a memory of the integrated circuit;
instructions for providing a selector configured to mask test responses produced by the scan cells based on the stored mask
data, thereby producing masked test responses; and

instructions for providing a test response compactor configured to receive the masked test responses.

US Pat. No. 9,817,932

RECOGNIZING AND UTILIZING CIRCUIT TOPOLOGY IN AN ELECTRONIC CIRCUIT DESIGN

Mentor Graphics Corporati...

1. A method comprising:
analyzing, by a computing system, a schematic circuit design describing an electronic device to recognize that a subset of
transistors of the electronic device has a pre-defined circuit topology;

identifying, by the computing system, development information for the transistors in the recognized circuit topology;
comparing, by the computing system, verification criteria in the development information to results of functional verification
of the electronic device described by the schematic circuit design to determine whether the transistors in the recognized
circuit topology meet design specifications; and

generating a physical design layout from a netlist converted from the schematic circuit design after the design specifications
are met for the transistors in the recognized circuit topology.

US Pat. No. 9,740,804

CHIP-SCALE ELECTROTHERMAL ANALYSIS

Mentor Graphics Corporati...

1. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors
to perform a method, the method comprising:
extracting effective thermal conductance and effective thermal capacity for each region of a plurality of regions of a layout
design, the layout design corresponding to at least a portion of an integrated circuit, and the effective thermal conductance
for a region in a metal layer being determined based at least on density information of metal interconnect lines within the
region and having components dependent on directions of the metal interconnect lines;

constructing a thermal circuit based on the effective thermal conductance, the effective thermal capacity, and heat information
of thermal nodes, the heat information of thermal nodes determined based on an electrical simulation on the integrated circuit;
and

performing a thermal simulation on the thermal circuit to determine temperature information of the thermal nodes;
wherein the effective thermal capacity is determined based on mechanical property information, the mechanical property information
comprising Young's modulus, Poisson factors, thermal expansion coefficients, or any combination thereof.

US Pat. No. 9,720,859

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONDITIONALLY ELIMINATING A MEMORY READ REQUEST

Mentor Graphics Corporati...

1. A computer program product embodied on a non-transitory computer readable medium, comprising:
computer code for examining a netlist describing a circuit design to determine that a memory read request for a read address
in a memory is an unnecessary memory read request by detecting that a result of the memory read request is already available
at an output of the memory, and no write to the read address of the memory read request has occurred since a previous memory
read request for the read address in the memory; and

computer code for conditionally eliminating the memory read request, based on the determination.

US Pat. No. 9,703,922

FRAGMENTATION POINT AND SIMULATION SITE ADJUSTMENT FOR RESOLUTION ENHANCEMENT TECHNIQUES

Mentor Graphics Corporati...

1. A method of preparing a layout data file defining features to be created via a photolithographic process for optical and
process correction, comprising:
reading at least a portion of a layout file defining one or more features to be created;
fragmenting the features into a number of edge fragments;
defining initial simulation sites for one or more of the edge fragments;
estimating an image intensity at the initial simulation sites;
adding additional sample points to one or more of the simulation sites dependent on the estimated image intensity;
recalculating image intensities at at least one of the additional sample points;
determining how to move one or more edges for a resolution enhancement technique based on the recalculated image intensities;
and

fabricating a mask or reticle using a stored layout data file comprising at least one of the moved edges or providing the
stored layout data file comprising at least one of the moved edges to a manufacturing facility for fabricating photolithographic
masks or reticles.

US Pat. No. 10,509,072

TEST APPLICATION TIME REDUCTION USING CAPTURE-PER-CYCLE TEST POINTS

Mentor Graphics Corporati...

1. A system, comprising:scan chains for testing a circuit in a test mode, the scan chains comprising:
a plurality of regular scan chains, the plurality of regular scan chains being scan chains configurable to shift in test stimuli, to capture test responses, and to shift out the captured test responses in the test mode, and
one or more capture-per-cycle scan chains, the one or more capture-per-cycle scan chains being scan chains configurable to capture test responses at observation sites (observation points) selected for testing the circuit during scan shift operations in the test mode, each of the one or more capture-per-cycle scan chains comprising:
scan cells, and
signal-combining devices, each of the signal-combining devices being inserted between two neighboring scan cells in the scan cells, wherein:
each of the signal-combining devices comprises an XOR logic gate and a logic gate,
inputs of the logic gate are respectively connected to one of the observation sites and to a test point enable signal (TPE),
an output of the logic gate is connected to an input of the XOR logic gate,
an output of each of the signal-combining devices is connected to a data input of a first neighboring scan cell,
a first input of the each of the signal-combining devices is connected to an output of a second neighboring scan cell, and
no outputs of the scan cells drive any logic of the circuit in the test mode.

US Pat. No. 10,496,779

GENERATING ROOT CAUSE CANDIDATES FOR YIELD ANALYSIS

Mentor Graphics Corporati...

1. A method comprising:by using a computer:
receiving diagnosis reports generated by testing one or more devices comprising an integrated circuit fabricated according to a layout design;
determining regions of interest for points of interest, the points of interest representing locations of potential critical features in the layout design;
extracting one or more quantitative properties from the regions of interest;
identifying probable root causes for failing devices fabricated according to the layout design by analyzing diagnosis reports of the failing devices and the one or more quantitative properties; and
increasing a manufacturing yield of devices fabricated according to the layout design based on the identified probable root causes.

US Pat. No. 10,325,055

SIGNAL INTEGRITY DELAY UTILIZING A WINDOW BUMP-BASED AGGRESSOR ALIGNMENT SCHEME

Mentor Graphics Corporati...

1. A method comprising:determining, by a computing system, a timing window for reception of a signal propagated through a victim channel in a circuit design;
generating, by the computing system, an aggressor window bump for each aggressor channel capable of inducing a noise bump on the victim channel, wherein each aggressor window bump corresponds to a superimposition of a corresponding noise bump over a range of different potential arrival times on the victim channel for the corresponding noise bump, wherein the noise bumps correspond to voltage waveforms capable of being induced on the victim channel by the aggressor channels;
selecting, by the computing system, a temporal alignment for switching of the signal received on the victim channel and switching of one or more of the noise bumps based, at least in part, on one or more of the aggressor window bumps;
simulating, by the computing system, the circuit design with the switching of the signal received on the victim channel and the switching one or more of the noise bumps initially set in the temporal alignment to determine a delta delay corresponding to the timing window for the signal propagated through the victim channel; and
utilizing, by the computing system, the delta delay corresponding to the timing window for the signal to determine whether the victim channel operates within a timing constraint associated with the circuit design.

US Pat. No. 10,055,533

VISUALIZATION OF ANALYSIS PROCESS PARAMETERS FOR LAYOUT-BASED CHECKS

Mentor Graphics Corporati...

1. A computer-implemented method, comprising:determining analysis process parameters of a circuit analysis process for layout design data describing a layout design of a circuit, wherein the analysis process parameters are associated with representative sources being used in the circuit analysis process;
recording one or more of the analysis process parameters by storing circuit analysis information associated with the one or more analysis process parameters; and
modifying the layout design data to provide one or more markers to visually identify one or more of the analysis process parameters.

US Pat. No. 9,977,856

INTEGRATED CIRCUIT LAYOUT DESIGN METHODOLOGY WITH PROCESS VARIATION BANDS

Mentor Graphics Corporati...

1. A method, comprising:verifying an integrated circuit layout by:
generating representations of a plurality of variations in edge placement that are likely to occur in a particular circuit layer during manufacturing under respective, process conditions;
extracting electrical properties that will be associated with a circuit manufactured with these variations; and
evaluating electrical timing parameters of the circuit manufactured with these variations; and
following successful verification of the integrated circuit layout, forwarding the integrated circuit layout to a mask writing tool for production of one or more masks or reticles.

US Pat. No. 9,887,884

CLOUD SERVICES PLATFORM

Mentor Graphics Corporati...

1. A system, comprising:
one or more cloud-based central servers; and
a plurality of edge nodes in communication with the one or more cloud-based central servers via the Internet, each of the
edge nodes comprising an edge node processor for executing edge node software services, each of the edge nodes being further
coupled to and configured to control different respective sets of two or more non-internet-enabled peripheral devices;

wherein the one or more cloud-based central servers are configured to provide web services over the Internet to a mobile device,
the web services including a downloadable application, wherein the downloadable application is configured to operate on the
mobile device to provide a single unified user interface on the mobile device operative to control the two or more peripheral
devices coupled to and configured to be controlled by at least two respective ones of the plurality of edge nodes; and

wherein the downloadable application is a first application, and wherein the one or more cloud-based central servers are configured
to provide a second application, wherein the second application is accessible by the mobile device and provides a second single
unified user interface on the mobile device operative to control a different set of two or more peripheral devices controlled
by a different set of at least two respective edge nodes among the plurality of edge nodes.

US Pat. No. 10,558,185

MAP BUILDING WITH SENSOR MEASUREMENTS

Mentor Graphics Corporati...

1. A method comprising:when a vehicle is without an external reference utilized to detect a location of the vehicle relative to map data, tracking, by a computing system in the vehicle, movement of the vehicle from the detected location of the vehicle based, at least in part, on vehicle movement measurements and sensor measurement data populated in an environmental model, and generating, by the computing system in a map building mode, new map data from the sensor measurement data and the tracked movement of the vehicle;
exiting, by the computing system, the map building mode by directing the vehicle to move towards an area having the map data; and
in response to reacquiring the external reference in the area having the map data, aligning, by the computing system, the sensor measurement data utilized to track the movement of the vehicle to a global coordinate field associated with the map data, and populating, by the computing system, the new map data into the map data based, at least in part, on the alignment of the tracked movement of the vehicle to the global coordinate field associated with the map data, wherein a control system for the vehicle is configured to control operation of the vehicle based, at least in part, on the modified map data.

US Pat. No. 10,430,538

TEST CAPABILITY-BASED PRINTED CIRCUIT BOARD ASSEMBLY DESIGN

Mentor Graphics Corporati...

1. A method comprising:identifying, by a schematic capture tool implemented with a computing system, parts representing electronic components available for use in a printed circuit board assembly;
selecting, by the schematic capture tool, a subset of the parts representing the electronic components based, at least in part, on physical test capabilities of a manufacturer for the printed circuit board assembly; and
generating, by the schematic capture tool, a logical design for the printed circuit board assembly, wherein the logical design includes a netlist and a parts list having one or more of the parts from the selected subset of the parts, and wherein the printed circuit board assembly, when manufactured based on the logical design, includes one or more electronic components corresponding to the selected subset of the parts in the logical design.

US Pat. No. 10,311,197

PRESERVING HIERARCHY AND COLORING UNIFORMITY IN MULTI-PATTERNING LAYOUT DESIGN

Mentor Graphics Corporati...

8. A non-transitory machine-readable medium storing instructions that, when executed by a processor, causes a computing system to:seed sampling markers on selected geometric elements of multiple patterning clusters in layout design data that represents an integrated circuit, including by, for a common cell placed at multiple instances in the layout design data:
placing an instance of a given sampling marker on the same geometric element in each instance of the common cell;
determine patterning scores for each of the multiple patterning clusters respectively, including by:
assigning a given color for each of the sampling markers seeded in the multiple patterning clusters;
selecting multiple color arrangements for the multiple patterning clusters;
determining multiple color values for each instance of the sampling markers, each respective color value for one of the multiple color arrangements; and
for each given patterning cluster of the multiple clusters:
determining multiple patterning scores for the given patterning cluster, each patterning score applicable to a given color arrangement and determined as a function of color values determined for each instance of the sampling markers in the given patterning cluster for the given color arrangement; and
color the layout design data by applying a selected one of the multiple color arrangements to each given patterning cluster of the multiple patterning clusters, the applied color arrangement selected based on the multiple patterning scores determined for the given patterning cluster,
wherein the colored layout design data supports manufacture of complementary lithographic masks according to the coloring applied to the colored layout design data.

US Pat. No. 10,255,396

GRAPHICAL ANALYSIS OF COMPLEX CLOCK TREES

Mentor Graphics Corporati...

1. A method comprising:synthesizing, by a computing system, a clock tree in a layout design of an integrated circuit based, at least in part, on timing constraints for the integrated circuit;
selecting, by the computing system, a portion of the clock tree to present in a schematic connectivity presentation;
generating, by the computing system, the schematic connectivity presentation of the clock tree that includes the selected portion of the clock tree, which is coupled to at least one compacted representation of other portions of the clock tree in the schematic connectivity presentation of the clock tree;
extracting, by the computing system, one or more clock tree circuits from the compacted representation based, at least in part, on a retained hierarchical connectivity of the other portions of the clock tree in the compacted representation; and
modifying, by the computing system, the schematic connectivity presentation of the clock tree to include the extracted clock tree circuits coupled to a modified-version of the compacted representation that excludes the extracted clock tree circuits.

US Pat. No. 10,228,970

DOMAIN BOUNDING FOR SYMMETRIC MULTIPROCESSING SYSTEMS

MENTOR GRAPHICS CORPORATI...

1. A computer-implemented method for bounding the processing domain in a symmetric multiprocessing system, the method comprising:identifying a symmetric multiprocessing system, the symmetric multiprocessing system including a plurality of processing units;
identifying a plurality of tasks to be scheduled for execution by the symmetric multiprocessing system;
initially loading all of the plurality of tasks to be scheduled into a symmetric multiprocessing task queue;
forming a computationally bound task queue;
moving selected ones of the plurality of tasks to be scheduled to the computationally bound task queue;
bounding the processing domain for the computationally bound task queue, the method act for bounding comprising linking the computationally bound task queue to a linked subset of the plurality of processing units such that the linked subset of the plurality of processing units only executes tasks moved to the computationally bound task queue and does not execute other tasks that have not been moved to the computationally bound task queue;
assigning tasks in the computationally bound task queue to execute on processing units in the processing domain bounded for the computationally bound task queue; and
assigning tasks in the symmetric multiprocessing task queue to execute on processing units not in the processing domain bounded for the computationally bound task queue.

US Pat. No. 10,210,302

ELECTROSTATIC DAMAGE PROTECTION CIRCUITRY VERIFICATION

Mentor Graphics Corporati...

1. A computer-implemented method of identifying interconnect lines represented in a circuit design that exceed a maximum impedance component value, comprising:creating an analysis window for the circuit design based upon characteristics of the interconnect lines and the maximum impedance component value;
identifying interconnect lines that extend from a center of the analysis window to or beyond a perimeter of the analysis window;
based upon identified interconnect lines, determining which interconnect lines within the analysis window have an impedance component value that must exceed the maximum impedance component value and which interconnect lines have an impedance component value that may exceed the maximum impedance component value; and
determining the specific impedance component value for the interconnect lines having an impedance component value that may exceed the maximum impedance component value.

US Pat. No. 10,146,897

MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS

Mentor Graphics Corporati...

1. One or more computer-readable memory devices storing computer-readable instructions that, when executed by one or more processors of a computing device, cause the computing device to perform operations, the operations comprising:creating one or more clusters of sink pins for circuit elements in a circuit design, wherein the clustered sink pins are designed to be connected to a clock tree of the circuit design;
placing clock tree nodes of the clock tree within the one or more clusters and connecting the sink pins to the clock tree nodes, such that sink pins within a cluster are connected to a clock tree node placed within the cluster;
determining multiple sets of clock tree timing variation parameters for the placed clock tree nodes within the one or more clusters;
measuring multiple timing delays from a root node of the clock tree to the sink pins within the one or more clusters, wherein the multiple timing delays are measured for the multiple sets of clock tree timing variation parameters, respectively;
determining clock skews for the one or more clusters based on the multiple delays measured for the multiple sets of clock tree timing variation parameters; and
modifying the clock tree by reducing clock skew across the multiple sets of clock tree timing variation parameters for the one or more clusters using the multiple measured timing delays and clock skews.

US Pat. No. 10,120,024

MULTI-STAGE TEST RESPONSE COMPACTORS

Mentor Graphics Corporati...

1. An apparatus for compacting test responses of a circuit-under-test, the apparatus comprising:a first compactor comprising a plurality of first-compactor inputs and a first-compactor output;
a register comprising a register input and a plurality of register outputs, the register input being coupled to the first-compactor output, the register being operable to load test response bits through the register input and to output the test response bits in parallel through the plurality of register outputs;
a second compactor comprising a plurality of second-compactor inputs and a second-compactor output, the plurality of second-compactor inputs being coupled to the plurality of register outputs, the second compactor being a spatial compactor;
a first set of masking logic coupled to the plurality of first-compactor inputs;
a second set of masking logic coupled between the plurality of register outputs and the plurality of second-compactor inputs; and
selection logic having one or more selection-logic inputs and a plurality of selection-logic outputs, the plurality of selection-logic outputs being coupled to respective inputs of the first set of masking logic and respective inputs of the second set of masking logic, the selection logic being operable to selectively control the first set of masking logic and the second set of masking logic in response to one or more masking instruction bits received at the one or more selection-logic inputs.

US Pat. No. 9,798,226

PATTERN OPTICAL SIMILARITY DETERMINATION

Mentor Graphics Corporati...

1. A method comprising:
simulating a lithography process of a first set of layout features and a second set of layout features using a lithography
model, wherein the lithography model is expressed as a plurality of functions that indicate light intensity on an image plane,
wherein the simulating produces a first plurality of values representing respective contributions of the plurality of functions
to imaging the first set of layout features and produces a second plurality of values representing respective contributions
of the plurality of functions to imaging the second set of layout features;

determining optical similarity values between the first set of layout features and the second set of layout features based
on the first plurality of values and the second plurality of values wherein each of the optical similarity values indicate
a degree of similarity between one or more layout features in the first set of layout features and one or more layout features
in the second set of layout features; and

changing the first set of layout features based on the optical similarity values.

US Pat. No. 10,657,217

LATENCY TEST IN NETWORKING SYSTEM-ON-CHIP VERIFICATION

Mentor Graphics Corporati...

1. A method, comprising:associating, by a hardware model of interface circuitry implemented in a reconfigurable hardware modeling device, arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, the arrival time information of a particular message including information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is delivered to the hardware model of the circuit design, wherein the associating arrival time information with messages comprises inserting the arrival time information of each of the messages in a metadata field of or a data field of the each of the messages or in special messages;
associating, by the hardware model of the interface circuitry, latency information with the messages when the messages are dispatched by the hardware model of the circuit design, the latency information being determined based on the model time reference and the arrival time information; and
sending the messages and the latency information to a traffic analysis device.

US Pat. No. 10,546,082

RESISTOR NETWORK REDUCTION FOR FULL-CHIP SIMULATION OF CURRENT DENSITY

Mentor Graphics Corporati...

1. One or more non-transitory computer-readable media storing computer-executable instructions, the computer-executable instructions which, when executed by one or more processors, cause the one or more processors to perform a method, the method comprising:performing a simulation to determine current data of parasitic resistors in one or more parasitic resistance networks in power supply circuitry of a circuit design by injecting a current into each one of the one or more parasitic resistance networks, the current being injected at one or more current source nodes and being drained at one or more current drain nodes, the one or more current source nodes and the one or more current drain nodes being selected from nodes of the power supply circuitry that are connected to said each one of the one or more parasitic resistance networks, the nodes of the power supply circuitry comprising pins of circuit devices in or connected to the power supply circuitry, power supply pads (power/ground), or both;
determining one or more reduced parasitic resistance networks for the one or more parasitic resistance networks by removing non-current carrying parasitic resistors from the one or more parasitic resistance networks, wherein the non-current carrying parasitic resistors are determined based on the current data and a predetermined threshold current value;
performing a full-circuit simulation using the one or more reduced parasitic resistance networks to obtain current density information;
performing a circuit design verification of the circuit design based on the current density information; and
reporting results of the circuit design verification.

US Pat. No. 10,496,783

CONTEXT-AWARE PATTERN MATCHING FOR LAYOUT PROCESSING

Mentor Graphics Corporati...

1. One or more non-transitory computer-readable media storing computer-executable instructions, the computer-executable instructions, when executed, causing one or more processors to perform a method, the method comprising:receiving a circuit design, circuit components of the circuit design being associated with geometric elements of a layout design;
analyzing the circuit design to identity circuit components of interest;
extracting reference layout patterns from the layout design that are associated with the circuit components of interest, and storing the extracted reference layout patterns in a reference pattern library;
performing pattern matching to identify layout patterns that match the reference layout patterns;
processing the layout patterns; and
reporting results of the processing.

US Pat. No. 10,381,287

HEAT SINK INTERFACE FOR A DEVICE

Mentor Graphics Corporati...

1. A system comprising:a device disposed on a substrate;
a heat sink disposed on the substrate over the device to form a cavity, wherein the heat sink includes a first opening to allow a fluid to enter the cavity, wherein the cavity is configured to hold the fluid between the heat sink and the device, the fluid to absorb heat emitted by the device and transfer at least a portion of the absorbed heat to the heat sink;
a relief plug disposed in the first opening formed in the heat sink, wherein the relief plug includes a conduit configured to allow the fluid to enter the cavity through the first opening in the heat sink; and
a bleed plug disposed in a second opening formed in the heat sink, wherein the bleed plug is configured to allow removal of gas from the cavity through the bleed plug and the second opening in the heat sink.

US Pat. No. 10,372,870

HOMOTOPY OPTIMIZED PARASITIC EXTRACTION

Mentor Graphics Corporati...

1. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:receiving layout design data of an integrated circuit comprising a plurality of nets, each net being a connected group of equipotential interconnects and comprising a set of geometrical elements;
computing a first signature of a first net of the nets based on contour-related information;
obtaining a second signature of a second net of the nets;
determining that the following conditions are true:
the first signature matches a first precomputed signature of a first precomputed net;
the second signature matches a second precomputed signature of a second precomputed net; and
relative location information of the first and second nets matches relative location information of the first and second precomputed nets;
responsive to the determining, assigning a precomputed parasitic capacitance value to the first net; and
forwarding the layout design data, with the precomputed parasitic capacitance value assigned to the first net, to an electronic design automation tool for physical verification.

US Pat. No. 10,657,207

INTER-CELL BRIDGE DEFECT DIAGNOSIS

Mentor Graphics Corporati...

1. A method, executed by at least one processor of a computer, comprising:performing failing test pattern simulations to determine initial defect suspects based on injecting faults to defect candidate sites, the defect candidate sites determined based on test responses, the test responses obtained by applying test patterns to a circuit for testing, and the test responses comprising failing bits;
determining initial inter-cell bridge suspects from cells in the initial defect suspects based on layout information and electrical information of the circuit, the determining comprising identifying pairs of neighboring cells based on the layout information, the electrical information of the circuit comprising cell internal signal information which is obtained based on transistor-level circuit simulations or switch-level circuit simulations; and
performing passing test pattern simulations to determine inter-cell bridge suspects from the initial inter-cell bridge suspects.