US Pat. No. 10,873,909

FREQUENCY DIVISION MULTIPLE ACCESS (FDMA) SUPPORT FOR WAKEUP RADIO (WUR) OPERATION

Marvell Asia Pte, Ltd., ...

1. A method, comprising:generating, at a first communication device, multiple wakeup frames, respective ones of the multiple wakeup frames for transmission to respective ones of multiple second communication devices;
generating, at the first communication device, a wakeup packet to include the multiple wakeup frames for transmission in respective particular wakeup radio (WUR) operating channels of respective ones of the multiple second communication devices, the respective WUR operating channels determined by previous negotiation between the first communication device and respective ones of the multiple second communication devices; and
transmitting, by the first communication device, the wakeup packet to prompt respective one or more second communication devices, among the multiple second communication devices, to transition from a low power state to an active state, including, prior to transmission of the wakeup packet, puncturing a portion of the wakeup packet, the portion corresponding to a component channel, among a plurality of component channels of an operating channel of the first communication device, that is determined by the first communication device to be busy.

US Pat. No. 10,588,165

METHODS AND DEVICES FOR COMMUNICATING IN A WIRELESS NETWORK WITH MULTIPLE VIRTUAL ACCESS POINTS

Marvell Asia Pte, Ltd., ...

1. A method, comprising:determining, at an access point (AP) device, a plurality of respective first identifiers of a plurality of respective basic service sets (BSSs) corresponding to a plurality of respective virtual APs implemented by the AP device;
broadcasting, with the AP device, an indication of the plurality of respective first identifiers of the plurality of respective BSSs so that client devices among a plurality of client devices of the plurality of virtual APs are made aware of all of the first identifiers of the plurality of respective BSSs;
indicating to one or more client devices among the plurality of client devices, with the AP device, a single second identifier that corresponds to all of the virtual APs in the plurality of virtual APs, wherein the single second identifier is to be included in one or more physical layer (PHY) preambles of one or more multi-user transmissions that each include data corresponding to multiple virtual APs; and
receiving, with the AP device from a particular client device among the plurality of client devices, an uplink (UL) transmission as part of a UL orthogonal frequency division multiple access (OFDMA) physical layer (PHY) data unit that includes data corresponding to multiple virtual APs, wherein the UL transmission includes data for a first virtual AP having a first identifier that is different from the single second identifier, and wherein the UL transmission includes a PHY preamble with a field set to the single second identifier.

US Pat. No. 10,660,105

SYSTEMS AND METHODS FOR MULTI-USER OPERATION WITH DUPLEX MEDIUM ACCESS CONTROL

Marvell Asia Pte, Ltd., ...

1. A method for establishing multi-user operation with duplex medium access control in a wireless local area network, the method comprising:transmitting, from an access point, a trigger frame to one or more client stations in a wireless local area network;
in response to transmitting the trigger frame, receiving, at the access point, one or more uplink data packets from the one or more client stations;
determining, at the access point, by decoding each uplink data packet of the one or more uplink packets, whether any of the one or more client stations support duplex operation; and
transmitting, from the access point, a downlink data packet configured in a multi-user data format to at least one destined client station determined to support duplex operation while simultaneously receiving the one or more uplink data packets from the one or more client stations.

US Pat. No. 10,635,474

SYSTEMS AND METHODS FOR VIRTIO BASED OPTIMIZATION OF DATA PACKET PATHS BETWEEN A VIRTUAL MACHINE AND A NETWORK DEVICE FOR LIVE VIRTUAL MACHINE MIGRATION

Marvell Asia Pte, Ltd., ...

1. A system to support virtual I/O (virtio)-based data packet receiving (Rx) path optimization for live virtual machine (VM) migration, comprising:a host having a VM running on it and in communication with a network device, and the host is configured to
accept a packet received at a virtual function (VF) network driver of the network device, wherein the packet is to be provided to the VM along a data packet receiving (Rx) path;
obtain which Rx buffers of a Rx virtio memory ring (Rx vring) of a memory of the VM are associated with the VF network driver requesting for the Rx vring via a vhost-net module, wherein the vhost-net module is a kernel-level backend module configured to utilize a zero-copy mechanism provided by Linux kernel of the host to avoid copying the packet to a macvtap module for data transmission along the data packet Rx path, wherein the macvtap module is a device driver configured to provide a socket that the vhost-net module polls to receive the packets or use send calls to send the packets;
save the packet to the Rx vring under direct memory access (DMA) while bypassing the macvtap module entirely;
perform Rx processing on the packet received in the Rx vring.

US Pat. No. 10,656,256

RANGING MEASUREMENTS IN WIRELESS COMMUNICATION SYSTEMS

Marvell Asia Pte, Ltd., ...

1. A method for performing ranging measurements in a wireless network, the method comprising:receiving, at a first communication device during a service period (SP) for a ranging measurement signal exchange between the first communication device and one or more second communication devices, respective first null data packets (NDPs) from the one or more second communication devices, the respective first NDPs omitting data portions;
transmitting, from the first communication device during the SP, respective second NDPs to the one or more second communication devices after the reception of the respective first NDPs, the respective second NDPs omitting data portions; and
one or both of
i) transmitting, from the first communication device during the SP, respective first ranging measurement feedback packets to the one or more second communication devices, the respective first ranging measurement feedback packet transmitted to a particular second communication device including at least a) an indication corresponding to a time t2 at which the respective first NDP was received from the particular second communication device and b) an indication corresponding to a time t3 at which the respective second NDP was transmitted to the particular second communication device to allow the particular second communication device to determine a time-of-flight between the first communication device and the particular second communication device, and
ii) receiving, at the first communication device during the SP, respective second ranging measurement feedback packets from the one or more second communication devices, the respective second ranging measurement feedback packet from a particular second communication device including at least a) an indication corresponding to a time t1 at which the respective first NDP was transmitted by the particular second communication device, and b) an indication corresponding to a time t4 at which the respective second NDP was received by the particular second communication device to allow the first communication device to determine a time-of-flight between the first communication device and the particular second communication device;
transmitting, by the first communication device at a beginning of the SP, a polling data unit to the one or more second communication devices to prompt the one or more second communication devices to be ready to transmit the respective first NDPs to the first communication device and to transmit respective poll response frames to the first communication device a short interframe space (SIFS) time period after reception of the polling data unit;
transmitting, from the first communication device, a trigger frame to the one or more second communication devices a SIFS time period after reception of the respective poll response frames to cause simultaneous transmission of the respective first NDPs, wherein the respective first NDPs are transmitted by the one or more second communication devices a SIFS time period after reception of the trigger frame; and
transmitting the respective first ranging measurement feedback packets to the one or more second communication devices, wherein transmitting the respective first ranging measurement feedback packets comprises transmitting the respective first ranging measurement feedback packets a SIFS time period after transmitting the respective second NDPs.

US Pat. No. 10,601,542

FLEXIBLE DATA TRANSMISSION SCHEME ADAPTIVE TO COMMUNICATION CHANNEL QUALITY

Marvell Asia Pte, LTD., ...

1. An Ethernet transceiver comprising:an Ethernet transmit circuit to transmit data organized into a given transport frame structure, the transmit circuit including
a symbol modulator to modulate a first group of symbols in accordance with a selectable data modulation scheme;
a transmitter coupled to the symbol modulator to transmit the first group of symbols over an Ethernet link at a selected symbol rate;
wherein the selected symbol rate and the selected data modulation scheme cooperate to produce a specified data rate from a selection of data rates, the specified data rate based on a power metric.

US Pat. No. 10,659,064

PHASE LOCK LOOP CIRCUITS AND METHODS INCLUDING MULTIPLEXED SELECTION OF FEEDBACK LOOP OUTPUTS OF MULTIPLE PHASE INTERPOLATORS

Marvell Asia Pte, Ltd., ...

1. A phase lock loop circuit comprising:a phase frequency detector to (i) compare a phase of a reference clock signal to a phase of a frequency divided output signal, and (ii) generate an error signal based on the comparison;
a voltage controlled oscillator to, based on the error signal, generate a phase lock loop output signal and a plurality of output clock signals;
a phase interpolator to phase interpolate the plurality of output clock signals to generate an interpolator output signal;
a clock signal selector to select one of the plurality of output clock signals;
a selection module to
receive the interpolator output signal and the one of the plurality of output clock signals, and
generate a selection signal based on (i) a state of the interpolator output signal, and (ii) a state of the selected one of the plurality of output clock signals;
a multiplexer to, based on the selection signal, select the interpolator output signal or the selected one of the plurality of output clock signals; and
a divider to frequency divide an output of the multiplexer to provide the frequency divided output signal.

US Pat. No. 10,986,639

ORTHOGONAL FREQUENCY DIVISION MULTIPLE ACCESS FOR WIRELESS LOCAL AREA NETWORK

Marvell Asia Pte, Ltd., ...

1. A method for wireless transmission, the method comprising:assigning, at a first communication device, multiple orthogonal frequency division multiplexing (OFDM) tone blocks for transmitting data to one or more other communication devices, including assigning a first OFDM tone block and a second OFDM tone block that is separated in frequency from the first OFDM tone block by a frequency gap, the first OFDM tone block and second OFDM tone block being assigned for transmitting data to a second communication device, wherein the first OFDM tone block has a first frequency bandwidth and the second OFDM tone block has a second frequency bandwidth that is different than the first frequency bandwidth;
generating, at the first communication device, an OFDM physical layer (PHY) data unit for transmission to the one or more other communication devices, including i) generating a first frequency portion of the OFDM PHY data unit that corresponds to the first OFDM tone block, and ii) generating a second frequency portion of the OFDM PHY data unit that corresponds to the second OFDM tone block, the second frequency portion of the OFDM PHY data unit being separated in frequency from the first frequency portion by the frequency gap, wherein the first frequency portion of the OFDM PHY data unit has the first frequency bandwidth and the second frequency portion of the OFDM PHY data unit has the second frequency bandwidth; and
transmitting, by the first communication device, the OFDM PHY data unit, the transmission of the OFDM PHY data unit including zero transmission power in the frequency gap.

US Pat. No. 10,713,411

PHOTOLITHOGRAPHY MASK DESIGN-RULE CHECK ASSISTANCE

MARVELL ASIA PTE, LTD., ...

1. A computer-implemented method comprising:performing, by a computer processor of a computing device, a design-rule check on a photolithography-mask design file, the design-rule check comparing, to a set of design rules, geometric dimensions of a feature to be rendered onto a photolithography mask using the photolithography-mask design file;
determining, by the computer processor and responsive to performing the design-rule check, a violation of a rule contained within the set of design rules;
presenting, by the computer processor and via a display of the computing device, a list of one or more user-selectable solutions applicable to resolving the determined violation;
receiving, by the computer processor, a user input indicating a user-selected solution from the list of one or more user-selectable solutions;
resolving, by the computer processor, the violation of the rule contained within the set of design rules by updating the photolithography-mask design file, wherein updating the photolithography mask design file comprises adjusting the feature in accordance with the user-selected solution; and
outputting, by the computer processor, the updated photolithography-mask design file, the updated photolithography-mask design file enabling rendering of the feature onto the photolithography mask in conformance with the rule.

US Pat. No. 10,715,171

VOLTAGE-MODE DAC DRIVER WITH PARALLEL OUTPUT RESISTANCE TUNING

Marvell Asia Pte., LTD, ...

1. A voltage-mode digital-to-analog converter (DAC), comprising:input circuitry to receive a digital word of N bits;
an array of output impedance units disposed in parallel;
wherein a configurably selectable number of the output impedance units are activated to produce a desired aggregate output impedance; and
wherein the configurably selectable number is free to be a number different than N.

US Pat. No. 10,993,243

SYSTEMS AND METHODS FOR UPLINK POWER CONTROL AND RATE ADAPTATION WITHIN A WIRELESS LOCAL AREA NETWORK (WLAN)

Marvell Asia Pte, Ltd., ...

1. A method for communicating in a wireless local area network (WLAN) comprising:setting, at the AP, an uplink target received signal strength information (RSSI) for each of the plurality of STAs, wherein the uplink target RSSI for each STA is set to be within a predetermined range relative to the uplink target RSSIs for the other STAs;
transmitting, from the AP to each of the plurality of STAs, a respective trigger frame containing an assigned modulation and coding scheme (MCS) and the uplink target RSSI for the assigned MCS; and
receiving, at the AP, a respective uplink frame transmitted to the AP by each respective STA at a respective one of the determined uplink target RSSIs included in the respective trigger frame.

US Pat. No. 10,764,198

METHOD TO LIMIT PACKET FETCHING WITH UNCERTAIN PACKET SIZES TO CONTROL LINE RATE

MARVELL ASIA PTE, LTD., ...

1. A method comprising:issuing a request to load an ingress packet, the request including a memory reference to the ingress packet loaded from at least one source of ingress packets, the ingress packet having an unknown size prior to being loaded, the request based on a network scheduler indicating availability of bandwidth from the at least one source of ingress packets, the availability being based on at least the average size of packets received by the source of ingress packets prior to issuing the request;
responsive to loading the ingress packet, retrieving a size of the ingress packet;
updating the average size of the ingress packets based on a size of the ingress packet loaded; and
reconciling the availability of bandwidth indicated by the network scheduler based on the size of the ingress packet loaded.

US Pat. No. 10,652,844

PAGING AUTO-ACKNOWLEDGEMENT

MARVELL ASIA PTE. LTD., ...

1. An apparatus, comprising:a transceiver;
auto-ACK logic for establishing a connection between the transceiver and a slave device based on a channel hopping sequence, the auto-ACK logic configured to, according to a protocol:
cause the transceiver to transmit, on a first channel, a synchronization packet to the slave device, where the synchronization packet specifies a second channel on which a subsequent packet will be transmitted to the slave device and where the second channel is defined by the channel hopping sequence;
wherein the protocol specifies that the slave device is to send an acknowledgement to the synchronization packet on the first channel prior to switching to the second channel and based on the acknowledgement being received by the transceiver, i) cause the transceiver to transmit the subsequent packet to the slave device on the second channel and ii) receive a response to the subsequent packet on the second channel to establish the connection between the transceiver and the slave device based on the channel hopping sequence; and
when i) predetermined automatic acknowledgement criteria are met, and ii) no acknowledgment to the synchronization packet has been received by the transceiver on the first channel from the slave device, cause the transceiver to
transmit the subsequent packet to the slave device on the second channel specified by the synchronization packet transmitted on the first channel, wherein the predetermined automatic acknowledgement criteria specify that the transceiver is to automatically switch from the first channel to the second channel specified by the synchronization packet transmitted on the first channel for transmitting the subsequent packet in response to a predetermined number of transmissions of the synchronization packet having occurred over the first channel without the transceiver having received the acknowledgement to the synchronization packet from the slave device, and
based on transmission of the subsequent packet on the second channel, receive the response to the subsequent packet from the slave device on the second channel to establish the connection between the transceiver and the slave device on the second channel based on the channel hopping sequence.

US Pat. No. 10,952,216

WIRELESS LOCAL AREA NETWORK MANAGEMENT

Marvell Asia Pte, Ltd., ...

1. A method for announcing presence of a wireless communication network managed by an access point configured for operating according to at least a first communication protocol, the method comprising:generating, at the access point, a management communication frame that includes information indicating network parameters of the wireless communication network, wherein the management communication frame includes information announcing an operating channel of the wireless communication network and identifying at least one primary component channel within the operating channel, the operating channel including i) the at least one primary component channel used at least for transmitting management information for the wireless communication network to client stations already associated with the access point and ii) at least one scanning channel specified, by the first communication protocol, to be used for client stations not associated with the access point to discover the access point;
generating, at the access point, a physical layer data unit to include the management communication frame; and
transmitting, by the access point, the physical layer data unit in the at least one scanning channel to allow discovery of the wireless communication network by client stations that are not associated with the access point.

US Pat. No. 10,772,056

WAKEUP RADIO (WUR) PACKET PREAMBLE DESIGN

Marvell Asia Pte, Ltd., ...

1. A method, performed by a first communication device, for transmitting a wakeup packet, the method comprising:determining, at a first communication device, a data rate for a wakeup packet body of the wakeup packet;
selecting, at the first communication device, a sync portion for the wakeup packet from a set of multiple candidate sync portions based on the determined data rate, wherein the multiple candidate sync portions in the set are configured to indicate respective data rates, and wherein each candidate sync portion comprises a respective plurality of on-off keying-modulated (OOK-modulated) sync symbols;
generating, at the first communication device, a first portion of the wakeup packet, wherein the first portion of the wakeup packet corresponds to a wireless local area network (WLAN) legacy preamble of the wakeup packet, and wherein the first portion spans a first frequency bandwidth;
generating, at the first communication device, a second portion of the wakeup packet, wherein the second portion of the wakeup packet spans a second bandwidth that is less than the first bandwidth, and wherein:
generating the second portion of the wakeup packet includes i) generating the selected sync portion to indicate to the second communication device the determined data rate of the wakeup packet body, and ii) generating the wakeup packet body according to the determined data rate, wherein generating the selected sync portion includes selecting each sync symbol in the selected sync portion from a set including a) a non-zero energy sequence and b) a zero energy sequence to enable the second communication device to:
detect the sync portion based on i) one or more respective autocorrelations, generated at the second communication device, between expected adjacent sync symbols corresponding to the non-zero energy sequence and ii) one or more energy levels, measured at the second communication device, of expected sync symbols corresponding to the zero energy sequence, and
determine a symbol timing using the one or more respective autocorrelations; and
transmitting, by the first communication device, the wakeup packet.

US Pat. No. 10,642,767

EFFICIENT SIGNALING SCHEME FOR HIGH-SPEED ULTRA SHORT REACH INTERFACES

Marvell Asia Pte, LTD, S...

1. A multi-chip module (MCM), comprising:a chip substrate;
a first integrated circuit (IC) chip disposed on the substrate, the first IC chip including first transceiver circuitry including a first input/output (I/O) port, the first I/O port configured to exhibit a first termination impedance exceeding 100 ohms;
a second integrated circuit (IC) chip disposed on the substrate and packaged with the first IC chip to form a single IC chip package, the second IC chip including second transceiver circuitry including a second input/output (I/O) port; the second I/O port configured to exhibit a second termination impedance exceeding 100 ohms;
a wired signaling channel coupled differentially between the first I/O port and the second I/O port, the wired signaling channel defining an ultra short reach channel having a trace length of less than one inch; and
wherein the first I/O port, the second I/O port, and the wired signaling channel cooperate to form a simultaneous bidirectional serial link between the first IC chip and the second IC chip, the simultaneous bidirectional serial link to simultaneously transfer transmit and receive signals between the first IC chip and the second IC chip.

US Pat. No. 10,966,227

WIFI MULTI-BAND COMMUNICATION

Marvell Asia Pte, Ltd., ...

1. A method for wireless local area network (WLAN) communication by a first WLAN communication device, the method comprising:generating, at the first WLAN communication device, a plurality of first media access control (MAC) data units intended for a plurality of second WLAN communication devices;
transmitting, from the first WLAN communication device, the plurality of first MAC data units to the plurality of second WLAN communication devices via a first WLAN communication channel having a first radio frequency (RF) bandwidth, the plurality of first MAC data units simultaneously transmitted as part of a first multi-user transmission;
generating, at the first WLAN communication device, a second MAC data unit having a trigger frame configured to prompt a second multi-user transmission by the plurality of second WLAN communication devices that includes acknowledgment information regarding the plurality of first MAC data units;
transmitting, from the first WLAN communication device, the second MAC data unit to the plurality of second WLAN communication devices via a second WLAN communication channel having a second RF bandwidth that does not overlap the first RF bandwidth; and
receiving, at the first WLAN communication device, a second multi-user transmission from the plurality of second communication devices via the second WLAN communication channel, the second multi-user transmission including i) the acknowledgment information regarding the plurality of first MAC data units, and ii) simultaneous transmissions from the plurality of second WLAN communication devices within the second WLAN communication channel.

US Pat. No. 10,769,098

METHODS AND SYSTEMS FOR ACCESSING HOST MEMORY THROUGH NON-VOLATILE MEMORY OVER FABRIC BRIDGING WITH DIRECT TARGET ACCESS

Marvell Asia Pte, Ltd., ...

1. A method for accessing a host memory through non-volatile memory over fabric bridging with direct target access, the method comprising:receiving, at a memory interface unit, from a remote direct memory access (RDMA) interface and via a network fabric, a first memory access command compliant with a first non-volatile memory interface protocol that was encapsulated at the RDMA interface, without modifying the first memory access command, in a first network packet
compliant with a second non-volatile memory interface protocol different from the first non-volatile memory interface protocol;
unwrapping, by the memory interface unit, the first network packet to obtain the encapsulated first memory access command compliant with the first non-volatile memory interface protocol;
storing the first memory access command, as obtained from the first network packet, in a work queue using address bits of the work queue as a pre-determined index of the first memory access command; and
sending the first memory access command, as obtained from the first network packet, from the work queue based on the pre-set index to a first target storage device.

US Pat. No. 10,651,827

APPARATUS AND METHOD FOR ACTIVATING CIRCUITS

MARVELL ASIA PTE, LTD., ...

1. An apparatus, comprising:a first clock generator configured to generate a first clock, wherein the first clock drives a first circuit to:
(i) receive audio data corresponding to an audio input, and
(ii) determine whether an energy level of the audio data exceeds a predetermined threshold;
a second clock generator configured to generate a second clock, wherein the second clock drives a second circuit to determine whether the audio data matches a predetermined pattern, wherein the second clock generator is activated when the first circuit determines that the energy level of the audio data exceeds the predetermined threshold, and wherein a frequency of the first clock is lower than a frequency of the second clock; and
a third circuit with a frequency of a third clock greater than the frequency of the second clock that is activated when the second circuit determines that the audio data matches the predetermined pattern.

US Pat. No. 10,623,533

METHODS AND APPARATUS FOR GENERATION OF PHYSICAL LAYER PROTOCOL DATA UNITS

Marvell Asia Pte, Ltd., ...

1. A method, performed at a first communication device, for transmitting a physical layer (PHY) protocol data unit (PPDU), the method comprising:receiving an initiating PPDU from a second communication device, the initiating PPDU having a PHY header that indicates a first PPDU format of the initiating PPDU, wherein the initiating PPDU includes one or more fields that indicate one or both of i) whether the second communication device is capable of processing PPDUs that conform to a non-legacy communication protocol, and ii) whether the second communication device neighbors any third communication devices that are not capable of processing PPDUs that conform to the non-legacy communication protocol, and wherein the one or more fields of the initiating PPDU indicate a second PPDU format of a responding PPDU to be transmitted in response to the initiating PPDU;
generating the responding PPDU using the second PPDU format; and
transmitting the responding PPDU in response to the initiating PPDU.

US Pat. No. 10,966,200

PUNCTURED OPERATING CHANNELS IN WLAN

Marvell Asia Pte, Ltd., ...

1. A method for establishing an operating channel for a wireless local area network (WLAN), the method comprising:determining, at a first communication device, an overall bandwidth of the operating channel, wherein the overall bandwidth spans a plurality of sub-channels;
determining, at the first communication device, that one or more sub-channels within the overall bandwidth will not be used for the operating channel;
generating, at the first communication device, a first packet that includes i) a first subfield that indicates the overall bandwidth of the operating channel, and ii) a second subfield that indicates the one or more sub-channels within the overall bandwidth that will not be used for the operating channel;
transmitting, by the first communication device, the first packet to inform one or more other communication devices in the WLAN of the operating channel for the WLAN, the operating channel having the overall bandwidth, wherein the indicated one or more sub-channels within the overall bandwidth are not to be used;
generating, at the first communication device, a request-to-send (RTS) frame;
after transmitting the first packet, transmitting, by the first communication device, the RTS frame to a second communication device via the operating channel, including not transmitting in the one or more sub-channels that are not used for the operating channel, wherein the second communication device is from among the one or more other communication devices;
receiving, at the first communication device, a clear-to-send (CTS) frame from the second communication device via only a subset of sub-channels via which the RTS frame was transmitted, the CTS frame responsive to the RTS frame; and
after receiving the CTS frame, transmitting, by the first communication device, a second packet to the second communication device via the only the subset of sub-channels via which the CTS frame was received.

US Pat. No. 10,869,345

SYSTEMS AND METHODS FOR PROVISIONING DEVICES FOR WLAN

Marvell Asia Pte, Ltd., ...

1. A method of joining an apparatus to a wireless local area network (WLAN) served by an access point (AP), the method comprising:generating, at a wireless network interface of the apparatus, a beacon frame that includes a service set identifier (SSID) corresponding to the apparatus and different from an SSID corresponding to the WLAN served by the AP;
transmitting, with the wireless network interface of the apparatus and to a client station of the WLAN, the beacon frame outside of the WLAN to prompt the client station of the WLAN to transmit network security information corresponding to the WLAN to the wireless network interface so that the wireless network interface can use the network security information to wirelessly connect the wireless network interface to the AP as part of the WLAN;
wirelessly receiving, at the wireless network interface and from the client station, one or more frames transmitted from the client station of the WLAN in response to the beacon frame, the one or more frames having been transmitted outside of the WLAN, wherein the one or more frames include the network security information corresponding to the WLAN;
extracting, from the one or more frames received from the client station, the network security information corresponding to the WLAN using at least one of i) the wireless network interface of the apparatus and ii) a processor of the apparatus; and
wirelessly associating, at the wireless network interface of the apparatus, with the AP as part of the WLAN using the network security information extracted from the one or more frames received from the client station.

US Pat. No. 10,771,100

METHOD AND APPARATUS FOR EFFICIENT FAST RETRAINING OF ETHERNET TRANSCEIVERS

Marvell Asia Pte., LTD., ...

1. A method of operation for an Ethernet transceiver, the method comprising:entering a fast retrain sequence of steps, the fast retrain sequence of steps including
transferring two-level symbols to a link partner without transferring Tomlinson-Harashima Precoder (THP) coefficient information; and
directly following transferring of the two-level symbols, transferring multi-level symbols to the link partner, the multi-level symbols having greater than two symbol levels.

US Pat. No. 10,771,126

UPLINK MULTI-USER MULTIPLE INPUT MULTIPLE OUTPUT FOR WIRELESS LOCAL AREA NETWORK

Marvell Asia Pte, Ltd., ...

1. A method, comprising:transmitting, by a first communication device, a polling communication frame that is configured to trigger a plurality of second communication devices to transmit respective feedback information that indicates respective amounts of data that the respective second communication devices have to transmit to the first communication device, wherein the polling communication frame includes a duration field that is set to indicate a transmit opportunity period (TXOP) of the first communication device, the TXOP including the polling communication frame and indicating a period during which an uplink multi-user transmission is to occur;
receiving, at the first communication device, the respective feedback information from the plurality of second communication devices during the TXOP;
based on the respective feedback information, selecting, at the first communication device, a group of second communication devices that are to transmit simultaneously during the TXOP as part of the uplink multi-user transmission;
transmitting, by the first communication device, a trigger communication frame during the TXOP to trigger the group of second communication devices to transmit simultaneously as part of the uplink multi-user transmission; and
receiving, at the first communication device, the uplink multi-user transmission during the TXOP, wherein the uplink multi-user transmission is responsive to trigger communication frame and includes respective simultaneous individual transmissions from respective second communication devices among the group of second communication devices.

US Pat. No. 10,754,409

ENERGY EFFICIENT ETHERNET WITH MULTIPLE LOW-POWER MODES

Marvell Asia Pte., LTD., ...

1. An Ethernet transceiver, comprising:transceiver circuitry including transmit circuitry, receive circuitry, and adaptive filters;
wherein the transceiver circuitry is configurable to operate in one of two low-power modes, including
a first low-power mode including update operations for the adaptive filters, and
a second low-power mode including turning off at least one of the transmit circuitry and the receive circuitry, and omitting update operations for the adaptive filters.

US Pat. No. 10,747,541

MANAGING PREDICTOR SELECTION FOR BRANCH PREDICTION

Marvell Asia Pte, Ltd., ...

1. An integrated circuit comprising:at least one processor executing instructions in a pipeline, the instructions including branch instructions;
storage accessible to the pipeline for storing branch prediction information characterizing results of branch instructions previously executed by the processor;
first circuitry configured to provide a predicted branch result, for at least some branch instructions, based on a selected predictor of a plurality of predictors; and
second circuitry configured to provide an actual branch result based on an executed branch instruction, and to update the branch prediction information based on the actual branch result;
wherein the plurality of predictors include:
a first predictor that determines the predicted branch result based on at least a portion of the branch prediction information;
a second predictor that provides a first constant branch result value as the predicted branch result for all virtual addresses of branch instructions for which the predicted branch result is being provided.

US Pat. No. 10,732,684

METHOD AND APPARATUS FOR MANAGING GLOBAL CHIP POWER ON A MULTICORE SYSTEM ON CHIP

MARVELL ASIA PTE, LTD., ...

1. A method for controlling power consumption in a multi-core processor chip, the method comprising:accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip, the multiple core processors arranged in a serial configuration, the accumulating including causing at least one core processor of the multiple core processors to update a cumulative sum of power estimates to produce an updated cumulative sum and forward the updated cumulative sum to one other core processor or to the controller, based on a location of the at least one core processor within the serial configuration;
determining a cumulative power estimate based at least in part on the one or more power estimates accumulated;
determining a global power threshold based on the cumulative power estimate determined; and
causing power consumption at each core processor to be controlled based on the global power threshold determined.

US Pat. No. 10,680,949

SYSTEMS AND METHODS FOR IMPLEMENTING A TIME-STAMPED CONTROLLER AREA NETWORK (CAN) BUS MESSAGE

Marvell Asia Pte, Ltd., ...

1. A method for a transmitting a Controller Area Network (“CAN”) message, comprising:receiving a CAN message at a network bridge that bridges the CAN to an Ethernet network;
in response to receiving the CAN message at the network bridge, generating a time stamp indicative of a time at which the CAN message was received;
encapsulating the time stamp and the CAN message into an Ethernet frame; and
transmitting the Ethernet frame containing the encapsulated time stamp and CAN message over the Ethernet network.

US Pat. No. 10,673,321

CHARGE PUMP CIRCUIT WITH BUILT-IN-RETRY

Marvell Asia Pte., Ltd., ...

1. An integrated circuit device comprising:a charge pump;
a bandgap reference generator electrically connected to the charge pump; and
a multiplexor electrically connected to the bandgap reference generator and the charge pump,
wherein the multiplexor has a first input that is configured to receive voltage levels of a voltage-boosted clock signal being output by the charge pump to the bandgap reference generator,
wherein the multiplexor has a first output that is configured to output either: a retry signal, based on the voltage levels being output by the charge pump being below a voltage threshold; or a pump signal, based on the voltage levels being output by the charge pump not being below the voltage threshold,
wherein the charge pump is configured to output voltage to the bandgap reference generator based on receipt of the pump signal, and the charge pump is configured to not output voltage to the bandgap reference generator based on receipt of the retry signal, and
wherein the multiplexor is configured to precharge the charge pump by connecting a boosted output node of the charge pump to a first voltage source based on receipt of the retry signal.

US Pat. No. 10,651,974

METHOD AND APPARATUS FOR UPDATING ERROR DETECTION INFORMATION IN PACKETS

Marvell Asia Pte, Ltd., ...

11. A method, comprising:receiving, at a network device, a packet having i) a first field that is to be updated by the network device, and ii) a second field that includes current error detection information corresponding to content of the packet, the content including the first field;
determining, at the network device, an update value that is to be added to a current value of the first field to generate a new value of the first field;
generating, at the network device, new error detection information using the current error detection information and the update value, and without using the current value of the first field;
modifying, at the network device, the second field to include the new error detection information; and
modifying, at the network device, the first field to include the new value.

US Pat. No. 10,620,236

MULTI-TEST TYPE PROBE CARD AND CORRESPONDING TESTING SYSTEM FOR PARALLEL TESTING OF DIES VIA MULTIPLE TEST SITES

Marvell Asia Pte, Ltd., ...

1. A probe card for testing a plurality of dies of a substrate during a wafer sort process, the probe card comprising:a printed circuit board; and
a first test site arranged to connect respectively to a selected one of the plurality of dies during a test cycle, wherein the first test site comprises
a first pin connecting band connected to the printed circuit board, and
a first pin set connected to the first pin connecting band of the first test site, wherein the first pin set includes a pin configuration for a testing device to perform a first type of test on a first die, wherein the first test site includes pins in the first pin set and no other pins, wherein a number of pins in the first pin set is less than a number of pins used to perform a second type of test on the first die, and wherein the second type of test is performed at a slower processing speed than the first type of test.

US Pat. No. 10,879,578

MM-WAVE WAVEGUIDE WITH AN ELECTRICALLY-INSULATING CORE HAVING AN ELECTRICALLY-CONDUCTIVE TRANSMISSION LINE DISPOSED INSIDE THE CORE

MARVELL ASIA PTE, LTD., ...

2. A waveguide, comprising:a core comprising an electrically-insulating material that is transmissive at millimeter-wave frequencies, the core configured to receive a millimeter-wave signal at a first end of the waveguide, and to guide the millimeter-wave signal to a second end of the waveguide;
an electrically-conductive transmission line, which comprises a pair of metallic conductor lines disposed inside the core along a central axis of the waveguide, the electrically-conductive transmission line configured to conduct an electrical signal between the first end of the waveguide and the second end of the waveguide, in parallel with the millimeter-wave signal guided in the core; and
an electrically-conductive tube, disposed along the central axis of the waveguide, which is configured to enclose the pair of metallic conductor lines and to separate the pair of metallic conductors from the core.

US Pat. No. 10,798,108

APPARATUS AND METHOD FOR A MULTI-ENTITY SECURE SOFTWARE TRANSFER

Marvell Asia Pte, Ltd., ...

1. A method for a multi-entity secure software transfer, comprising:configuring a first communication interface controller at a first hardware entity and a second communication interface controller at a second hardware entity to disallow all external access to the respective first hardware entity and the second hardware entity except a communication link configuration access;
establishing a communication link between the first hardware entity and the second hardware entity subsequent to the configuring;
receiving the secure software at the first hardware entity from the second hardware entity via the communication link;
writing the secure software to a temporary storage at the first hardware entity;
copying the secure software from the temporary storage to a secure storage at the first hardware entity;
retrieving from a non-volatile storage at the first hardware entity a public key; and
authenticating the secure software in the secure storage using the public key.

US Pat. No. 10,785,169

PROTOCOL INDEPENDENT PROGRAMMABLE SWITCH (PIPS) FOR SOFTWARE DEFINED DATA CENTER NETWORKS

MARVELL ASIA PTE, LTD., ...

1. A switch microchip for a software-defined network, the microchip comprising:a programmable parser that parses desired packet context data from headers of a plurality of incoming packets, wherein the headers are recognized by the parser based on a software-defined parse graph of the parser including a plurality of paths;
one or more dynamically reconfigurable lookup memories having a plurality of tables, wherein the lookup memories are configured as a logical overlay such that the scaling and width of a portion of the lookup memories allocated to each of the paths is software-defined by a user; and
a non-transitory computer-readable memory storing a programmable counter block used for counting operations of a plurality of lookup and decision engines, wherein the operations that are counted by the counter block are software-defined by the user.

US Pat. No. 10,771,077

HYBRID RETURN-TO-ZERO VOLTAGE-MODE DAC DRIVER

Marvell Asia Pte., LTD, ...

1. A voltage-mode digital-to-analog converter (DAC), comprising:multiple bit processing circuits to generate an output voltage responsive to a binary input, each of the multiple bit processing circuits including
a first switch circuit to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time, the first output load having a value proportional to a scaling value d,
a second switch circuit to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time, the second output load having a value corresponding to the first output load, and
wherein the first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to a relationship (1-d).

US Pat. No. 10,763,997

ACTION FRAME TO INDICATE CHANGE IN BLOCK ACKNOWLEDGMENT PROCEDURE

Marvell Asia Pte., Ltd., ...

1. A method, comprising:generating, at a first communication device, a media access control (MAC) frame that includes i) an indication of a change in a block acknowledgment (BA) session that was previously established between the first communication device and a second communication device, and ii) at least one of a) an updated number of buffers parameter indicating a reduced number of buffers available for the BA session and b) an updated inactivity timeout parameter value associated with the BA session;
transmitting, by the first communication device, the MAC frame to the second communication device, wherein the MAC frame is configured to cause the second communication device to adopt the change in the BA session in response to receiving the MAC frame; and
adopting, at the first communication device, the change in the BA session.

US Pat. No. 10,734,016

PULSE-BASED WRITING FOR MAGNETIC STORAGE MEDIA

MARVELL ASIA PTE, LTD., ...

1. A method comprising:determining that a string of data bits having a same polarity corresponds to a magnet longer than a threshold associated with a magnetic media writer;
inserting, into the string of data bits, at least one transition to a polarity opposite to the same polarity of the string of data bits; and
transmitting, to the magnetic media writer, the string of data bits including the at least one transition to cause a write head of the magnetic media writer to pulse while writing the magnet corresponding to the string of bits.

US Pat. No. 10,735,048

NETWORK SWITCH APPARATUS AND METHODS FOR GLOBAL ALIEN CROSSTALK CHARACTERIZATION, DIAGNOSTICS AND NETWORK OPTIMIZATION

Marvell Asia Pte, LTD, S...

1. An Ethernet network switch comprising:network switch circuitry including
multiple Ethernet ports, each port including local Ethernet transceiver circuitry forming one end of an respective Ethernet link of multiple Ethernet links;
control logic to, when the network switch circuitry is connected to multiple network devices via respective Ethernet links, 1) initiate a diagnostic mode of operation, 2) while in the diagnostic mode of operation, control at least two of the multiple Ethernet links in an aggressor and victim relationship to perform respective link training sequences to detect a measured parameter associated with alien crosstalk, the alien crosstalk comprising noise from an aggressor Ethernet link to a victim Ethernet link and noise that is external to respective ones of the at least two of the multiple Ethernet links and 3) operate in a data transfer mode of operation with the multiple Ethernet ports operating in a normal networking state.

US Pat. No. 10,735,350

SYSTEMS AND METHODS FOR PROVIDING A COMPATIBLE BACKPLANE OPERATION MECHANISM FOR 2.5-GIGABIT HIGH-SPEED ETHERNET

Marvell Asia Pte, Ltd., ...

1. A method for providing a 2.5-gigabit high-speed Ethernet interface, the method comprising:receiving, at a physical layer of an Ethernet link, input data including a first sequence-ordered set in compliance with a 2.5-Gigabit physical coding sublayer intermediate interface (2.5GPII) protocol;
aligning the input data into four parallel outputs of data in compliance with the 2.5GPII protocol;
decoding the four parallel outputs of data in compliance with the 2.5GPII protocol to an output containing a second ordered set in compliance with 10-gigabit media-independent interface (XGMII) protocol; and
transmitting the output to an XGMII or logical interface of the Ethernet link.

US Pat. No. 10,681,038

SYSTEMS AND METHODS FOR EFFICIENT PASSWORD BASED PUBLIC KEY AUTHENTICATION

Marvell Asia Pte, Ltd., ...

1. A method for efficient password based public key authentication between a first user device and a second user device, the method comprising:receiving a shared password by a first user device;
generating a first hash value of the shared password by the first user device;
generating, at the first user device, a first value, wherein the first value is composed of at least:
a product of the first hash value and a first unique security constant associated with the first user device; and
a first random value generated using data from a generator element;
generating, at the first user device, a first blind public key associated with the first user device, wherein the first blind public key is generated using a first public key; and
concurrently sending the first value and the first blind public key to the second user device for authentication;
receiving the first value and the first blind public key at the second user device;
combining, at the second user device, a second random value and the first public key to generate a second blind public key; and
comparing, at the second user device, the second blind public key and the received first blind public key to verify the identity of the first user device.

US Pat. No. 10,681,578

METHOD AND APPARATUS FOR PERFORMING A FINE TIMING MEASUREMENT IN A WIRELESS NETWORK

Marvell Asia Pte., Ltd., ...

1. A first wireless communication device in a wireless network including the first wireless communication device and a second wireless communication device, the first wireless communication device comprising:a timing module to provide a timing synchronization function (TSF) time, wherein values of the TSF time correspond to a common time shared between the first wireless communication device and the second wireless communication device; and
a fine timing measurement module to
transmit a first request to perform a fine timing measurement to determine a distance between the first wireless communication device and the second wireless communication device, wherein the first request includes a first value of the TSF time at which to start a burst period of the fine timing measurement, and wherein the first value is determined in accordance with the TSF time provided by the timing module,
receive a first response as transmitted from the second wireless communication device in response to the first request, wherein the first response includes the first value of the TSF time, and
transmit a second request to start the burst period of the fine timing measurement at the first value of the TSF time as included in the first request.

US Pat. No. 10,651,135

TAMPER DETECTION FOR A CHIP PACKAGE

MARVELL ASIA PTE, LTD., ...

1. A structure comprising:a lead frame with a die attach paddle, a plurality of outer lead fingers, and a plurality of inner lead fingers located between the outer lead fingers and the die attach paddle;
a chip attached to the die attach paddle, the chip including a surface having an outer boundary, a first plurality of bond pads arranged in a first plurality of rows proximate to the outer boundary, and a second plurality of bond pads that are interior of the outer boundary relative to the first plurality of bond pads, the first plurality of bond pads located on the surface of the chip between the second plurality of bond pads and the outer boundary of the chip, the second plurality of bond pads arranged in a second plurality of rows, and each of the second plurality of rows angled relative to one of the first plurality of rows toward a center of the surface of the chip;
a first plurality of wires each having a first end coupled to one of the outer lead fingers and a second end coupled to one of the second plurality of bond pads;
a tamper detection circuit coupled with the first plurality of wires; and
a second plurality of wires extending from the inner lead fingers to the first plurality of bond pads on the chip, the second plurality of wires located between the lead frame and the first plurality of wires.

US Pat. No. 10,886,994

LOW COMPLEXITY BEAMFORMING WITH COMPRESSED FEEDBACK

Marvell Asia Pte, Ltd., ...

1. A method for providing beamforming information in a communication channel, the method comprising:calculating, at a first communication device, an initial matrix from an estimate of the communication channel;
performing, at the first communication device, a matrix decomposition of the initial matrix to decompose the initial matrix into a plurality of decomposition matrices, wherein performing the matrix decomposition comprises determining angles for rotation operations performed on the initial matrix as part of decomposing the initial matrix, and wherein determining angles for rotation operations performed on the initial matrix comprises:
determining first angles for first rotation operations performed on rows of the initial matrix as part of performing the matrix decomposition, and
determining second angles for second rotation operations performed on columns of the initial matrix as part of performing the matrix decomposition;
determining, at the first communication device, compressed feedback using the angles that were determined as part of decomposing the initial matrix into the plurality of decomposition matrices, including using i) the first angles that were determined as part of decomposing the initial matrix into the beamforming steering matrix, and ii) the second angles that were determined as part of decomposing the initial matrix into the beamforming steering matrix, wherein the compressed feedback is a compressed representation of a beamforming steering matrix corresponding to the estimate of the communication; and
transmitting, by the first communication device, the compressed feedback to a second communication device to enable the second communication device to beamform at least one subsequent transmission to the first communication device.

US Pat. No. 10,868,580

ETHERNET LINK TRANSMIT POWER METHOD BASED ON ALIEN CROSSTALK FEEDBACK

Marvell Asia Pte., LTD., ...

1. A method of operating an Ethernet transceiver comprising:initializing the Ethernet transceiver during a training mode of operation by
transmitting training data to a link partner over at least one Ethernet link at a first data rate and at a first transmit power level;
adjusting the data rate and/or transmit power level to an adjusted second data rate and/or second transmit power level based on alien crosstalk feedback indicative of alien crosstalk effects to at least one crosstalk-coupled Ethernet link that exhibits crosstalk caused by the transmitting; and
initiating operation of the Ethernet transceiver in a normal data transfer mode of operation utilizing the adjusted second data rate and/or adjusted second transmit power level.

US Pat. No. 10,826,726

MULTI-RADIO DEVICE AND METHOD OF OPERATION THEREOF

Marvell Asia Pte, Ltd., ...

1. A wireless device comprising:a first analog radio module;
a first medium access control module configured to control access to a digital network via the first analog radio module;
a first baseband module configured to convert between analog signals at the first analog radio module and digital signals at the first medium access control module;
a second analog radio module;
a second medium access control module configured to control access to a digital network via the second analog radio module;
a second baseband module configured to convert between analog signals at the second analog radio module and digital signals at the second medium access control module; and
circuitry configured to selectably coordinate the first and second medium access control modules to create a single-channel configuration for utilization by the wireless device to transmit and receive radio signals over a wireless interface, by setting the first analog radio module and the second analog radio module to operate on a common frequency, and by commonly controlling the first and second baseband modules to convert common packets between analog and digital signals transmitted to or received from respective medium access control modules.

US Pat. No. 10,810,011

IMPLEMENTING 128-BIT SIMD OPERATIONS ON A 64-BIT DATAPATH

Marvell Asia Pte, Ltd., ...

1. A method of implementing a processor architecture, the method comprising:provisioning the processor with operands of a first size and a datapath of a second size that is different than the first size; and
given a first array of registers and a second array of registers, each register of the first array and the second array being of the second size and comprised in a register file, selecting, by at least one multiplexer comprised in the register file, in response to receiving select values, one of a first register and a second register from the first array and the second array, respectively, to perform operations of the first size on the datapath of the second size, wherein the first register and the second register correspond to each other, and wherein the selecting the one of the first register and the second register is based on a clock cycle of the processor relative to an instruction received.

US Pat. No. 10,784,250

SUB-DEVICE FIELD-EFFECT TRANSISTOR ARCHITECTURE FOR INTEGRATED CIRCUITS

MARVELL ASIA PTE, LTD., ...

1. A method of forming an integrated field-effect transistor (FET) of FET sub-devices, the method comprising:forming a substrate for the integrated FET;
forming, on the substrate, a first set of the FET sub-devices, a first FET sub-device of the first set of the FET sub-devices coupled to a drain terminal of the integrated FET; and
forming, on the substrate, a second set of the FET sub-devices, a second FET sub-device of the second set of the FET sub-devices coupled to a source terminal of the integrated FET,
wherein (i) the first set of the FET sub-devices is formed on an interior portion of substrate area on which the integrated FET is formed and (ii) the second set of the FET sub-devices is formed proximate a perimeter of the substrate area on which the integrated FET is formed.

US Pat. No. 10,761,737

METHOD AND APPARATUS FOR CACHING DATA IN AN SOLID STATE DISK (SSD) OF A HYBRID DRIVE THAT INCLUDES THE SSD AND A HARD DISK DRIVE (HDD)

MARVELL ASIA PTE, LTD., ...

1. A hybrid drive comprising:a storage system, wherein the storage system includes
a hard disk drive having a first data storage capacity, the hard disk drive including a data caching portion and a data storage portion, the data caching portion having a lower track density than the data storage portion; and
a solid state disk having a second data storage capacity, wherein the second data storage capacity of the solid state disk is lower than the first data storage capacity of the hard disk drive;
a host interface configured to be in communication with a host processor, the host processor including one or more levels of cache; and
a disk controller coupled to the storage system, wherein the disk controller is configured to access the solid state disk as a final level of cache prior to the disk controller accessing the hard disk drive,
wherein in response to the host interface receiving a request for data that is not cached in the one or more levels of cache of the host processor, the disk controller is configured to determine first whether the data requested by the host processor is cached in the solid state disk being the final level of cache, and
(i) retrieve, in response to determining the data requested by the host processor is cached in the solid state disk, the data requested by the host processor from the solid state disk,
(ii) retrieve, in response to determining the data requested by the host processor is not cached in the solid state disk and is cached in the data caching portion of the hard disk drive, the data requested by the host processor from the data caching portion of the hard disk drive; and
(iii) retrieve, in response to determining the data requested by the host processor is not cached in the solid state disk and is not cached in the data caching portion of the hard disk drive, the data requested by the host processor from the data storage portion of the hard disk drive.

US Pat. No. 10,764,855

SYNCHRONIZING CLOCKS IN A WIRELESS NETWORK

Marvell Asia Pte, Ltd., ...

1. A method of synchronizing a first timer at a first communication device with a second timer at a second communication device, wherein the first timer comprises a least significant portion and a most significant portion, and wherein the second timer comprises a least significant portion and a most significant portion, the method comprising:receiving, at the first communication device, a packet that includes a timestamp, wherein the packet is from the second communication device, wherein the timestamp corresponds to the least significant portion of the second timer of the second communication device, and wherein the packet does not include any bits of the most significant portion of the second timer;
determining, at the first communication device, whether a most significant bit of the least significant portion of the first timer is different than a most significant bit of the timestamp;
at least when the most significant bit of the least significant portion of the first timer is different than the most significant bit of the timestamp, determining, at the first communication device, a mathematical difference between i) the least significant portion of the first timer and ii) the timestamp;
when the most significant bit of the least significant portion of the first timer is different than the most significant bit of the timestamp, selectively adjusting, at the first communication device, the most significant portion of the first timer based on the mathematical difference between i) the least significant portion of the first timer and ii) the timestamp; and
using, at the first communication device, the timestamp to set the least significant portion of the first timer.

US Pat. No. 10,756,613

CONTROLLING CURRENT FLOW BETWEEN NODES WITH ADJUSTABLE BACK-GATE VOLTAGE

Marvell Asia Pte, Ltd., ...

1. A circuit structure comprising:a first transistor having a gate terminal, a source terminal, a drain terminal, and a back-gate terminal electrically coupled to an adjustable voltage source, wherein the gate terminal of the first transistor is electrically coupled to a first node having a first bias voltage; and
a second transistor having a gate terminal, a source terminal electrically coupled to the drain terminal of the first transistor, a drain terminal, and a back-gate terminal electrically connected to the adjustable voltage source, wherein the gate terminal of the second transistor is electrically coupled to a second node having a second bias voltage, and wherein the adjustable voltage source is selectable between a first voltage and a second voltage to control a threshold voltage of the first transistor and a threshold voltage of the second transistor,
wherein the first transistor and the second transistor each include a fully depleted semiconductor on insulator (FDSOI) channel region positioned laterally between the source terminal and the drain terminal of the first or second transistor.

US Pat. No. 10,959,229

MEDIUM PROTECTION IN WIRELESS LOCAL AREA NETWORKS

Marvell Asia Pte, Ltd, S...

1. A method for transmitting multiple data units in a communication channel, the method comprising:generating, at a communication device, a first data unit to be transmitted during a transmit opportunity (TXOP) obtained by the communication device, the first data unit generated to span a first bandwidth;
transmitting, by the communication device, the first data unit during the TXOP to at least one other communication device;
determining, at the communication device based on respective values of TXOP duration fields included in respective physical layer (PHY) preambles of one or more data units previously transmitted during the TXOP, whether a second bandwidth of a second data unit to be transmitted during the TXOP by the communication device can be greater than the first bandwidth of the first data unit transmitted during the TXOP by the communication device;
in response to determining that the second bandwidth of the second data unit transmitted during the TXOP can be greater than the first bandwidth of the first data unit transmitted during the TXOP, generating, at the communication device, the second data unit to span the second bandwidth greater than the first bandwidth; and
transmitting, by the communication device, the second data unit during the TXOP.

US Pat. No. 10,839,931

ZERO TEST TIME MEMORY USING BACKGROUND BUILT-IN SELF-TEST

MARVELL ASIA PTE, LTD., ...

1. A method, comprising:performing a functional write operation;
updating data of a test storage cache (TSC) when the functional write operation collides with a word under test (WUT);
performing a testing idle cycle when there is no collision between the functional write operation and the WUT;
testing a built-in self-test word under test (BIST WUT) with at least one pattern;
writing back the data from the TSC to the WUT after testing the BIST WUT;
verifying the data which is written back to the WUT;
removing a pointer of a translation lookaside buffer (TLB) to allow direct address mapping to the WUT after verifying the data which is written back to the WUT; and
incrementing a word address counter to test another word after removing the pointer,
wherein the testing the BIST WUT with at least one pattern occurs at a read/write port of a memory.

US Pat. No. 10,824,433

ARRAY-BASED INFERENCE ENGINE FOR MACHINE LEARNING

Marvell Asia Pte, Ltd., ...

1. An array-based inference engine configured to perform a machine learning (ML) operation on an input data stream, comprising:a plurality of processing tiles arranged in a two-dimensional array of a plurality of rows and a plurality of columns, wherein each processing tile of the plurality of processing tiles comprises at least one or more of
an on-chip memory (OCM) configured to
load and maintain data from the input data stream for local access by components in the each processing tile;
maintain and output result of the ML operation performed by the each processing tile as an output data stream;
a first processing unit (POD) configured to perform a dense and/or regular computation task of the ML operation on the data in the OCM; and
a second processing unit/element (PE) configured to perform a sparse and/or irregular computation task of the ML operation on the data in the OCM and/or from the POD,
the plurality of processing tiles are organized into a plurality of processing blocks, and wherein the OCMs of the plurality of processing tiles in the same processing block are configured to support aligned-reads, wherein data allocated and maintained in the OCMs are retrieved directly by the corresponding PODs and/or PEs in the processing tiles via at least one read port in each of the OCMs.

US Pat. No. 10,784,871

CLOCKING ARCHITECTURE FOR DVFS WITH LOW-FREQUENCY DLL LOCKING

MARVELL ASIA PTE, LTD., ...

1. A circuit for dynamic voltage frequency scaling (DVFS) on a chip, the circuit comprising:a delay-locked loop (DLL) including a fixed delay line path with a first insertion delay and a variable delay line path with a second insertion delay; and
a clock generator configured to source a DLL input clock to the fixed and variable delay line paths at a start-up frequency prior to a run-time frequency, the start-up frequency lower relative to a target frequency for the chip, the run-time frequency configured based on DVFS, following release of the chip from reset, the chip configured to be released from reset with the DLL locked at the start-up frequency, enabling the second insertion delay to match the first insertion delay with the DLL locked at the start-up frequency.

US Pat. No. 10,771,498

VALIDATING DE-AUTHENTICATION REQUESTS

Marvell Asia Pte., Ltd., ...

1. An apparatus for validating a de-authentication request, the apparatus comprising:a wireless controller configured to receive the de-authentication request and determine whether the de-authentication request is invalid based on the wireless controller's receipt of two or more responses to a timing request sent by the wireless controller in response to the de-authentication request, wherein only one response is expected, and wherein the two or more responses include an address of a first station, and at least one response of the two or more responses to the timing request includes a confirmation of transmitting the de-authentication request, the confirmation received from one of the first station or a second station, and at least one response of the two or more responses to the timing request includes a denial of transmitting the de-authentication request, the denial received (i) from the first station if the confirmation is received from second station or (ii) from the second station if the confirmation is received from the first station.

US Pat. No. 10,748,635

DYNAMIC POWER ANALYSIS WITH PER-MEMORY INSTANCE ACTIVITY CUSTOMIZATION

Marvell Asia Pte, Ltd., ...

1. A device comprising:a built-in-self-test (BIST) circuit configured to (i) run a BIST pattern of a BIST in a loop mode on a memory, wherein the BIST pattern is customized for activity factors of a customer application of the memory, wherein the activity factors correspond to a programmable number of operations to perform during the BIST of the memory, and (ii) measure a dynamic power level of a power supply while running the BIST pattern in the loop mode on the memory,
wherein the activity factors include a read activity factor, a write activity factor, and a search activity factor, which correspond respectively to a read operation, a write operation, and a search operation; and
a read activity register, a write activity register, and a search activity register, which are disposed outside the BIST circuit and used to store the activity factors.

US Pat. No. 10,673,561

HIGH-SPEED ETHERNET CODING

Marvell Asia Pte, LTD, S...

1. A BASE-T Ethernet transceiver comprising:a BASE-T Ethernet transmit circuit including
a BASE-T Ethernet data framing module including
an input interface to receive Ethernet block data bits,
a first forward error correction (FEC) encoder coupled to the input interface to encode at least a first portion of the data bits to generate first error check bits, and
a second FEC encoder comprising a Reed-Solomon encoder coupled to the input interface to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits; and
a symbol mapper including logic to modulate the Ethernet block data bits in accordance with a selected modulation.

US Pat. No. 10,666,682

SYSTEMS AND METHODS FOR ALLOWING FLEXIBLE CHIP CONFIGURATION BY EXTERNAL ENTITY WHILE MAINTAINING SECURED BOOT ENVIRONMENT

Marvell Asia Pte, Ltd., ...

1. A system to support flexible chip configuration while maintaining a secured boot environment, comprising:an external baseboard management controller (BMC) of a network chip configured to:
directly access a plurality of registers of the network chip in order to configure one or more networking ports designated for communication with the external BMC without violating secure areas of the network chip;
establish a data path to access a management software of a platform of the network chip over a network through the networking ports of the network chip;
said network chip configured to:
provide and designate the one or more networking ports for communication with the external BMC;
receive and transmit data packets between the external BMC and the management software through the designated networking ports over the network along the data path.

US Pat. No. 10,983,576

METHOD AND APPARATUS FOR MANAGING GLOBAL CHIP POWER ON A MULTICORE SYSTEM ON CHIP

MARVELL ASIA PTE, LTD., ...

20. A method for controlling power consumption in a multi-core processor chip, the method comprising:at a controller within the multi-core processor chip, accumulating one or more power estimates associated with multiple core processors within the multi-core processor chip, the multiple core processors arranged in a configuration, the accumulating based on the configuration;
determining a cumulative power estimate based at least in part on the one or more power estimates accumulated;
determining a global power threshold based on the cumulative power estimate determined; and
causing power consumption at each core processor to be controlled based on the global power threshold determined.

US Pat. No. 10,985,801

ETHERNET LINK TRANSMIT POWER METHOD BASED ON ON-CHIP DETECTED ALIEN CROSSTALK FEEDBACK

Marvell Asia Pte., LTD., ...

1. A method of operating an Ethernet transceiver comprising:initializing the Ethernet transceiver during a training mode of operation by
monitoring background link operating characteristics with on-chip circuitry during a non-data-transfer interval to establish a baseline alien crosstalk value;
transmitting training data at a first transmit power level and first data rate to a link partner during a data transfer interval;
monitoring the link with the on-chip circuitry during the data transfer interval to detect feedback indicating alien crosstalk effects to neighboring Ethernet links due to the transmitting;
adjusting the first data rate and/or first transmit power level to an adjusted second data rate and/or second transmit power level based on the feedback; and
initiating operation of the Ethernet transceiver in a normal data transfer mode of operation utilizing the adjusted second data rate and/or transmit power level.

US Pat. No. 10,984,822

PULSE-BASED WRITING FOR MAGNETIC STORAGE MEDIA

Marvell Asia PTE, Ltd., ...

1. A method comprising:determining that a string of data bits having a same polarity corresponds to a magnet formed on a magnetic storage media having a length that is longer than a magnet length threshold associated with a magnetic media writer;
asserting, in response to the determining, a signal to continue an application of write current to a write head of the magnetic media writer after a pulse of write current is applied to the write head to initiate writing of the magnet that corresponds to the string of data bits to the magnetic storage media;
maintaining, based on the signal that is asserted, the application of the write current to the write head to continue the writing of the magnet that corresponds to the string of data bits; and
deasserting, based on the length of the magnet, the signal to enable the application of the write current to the write head to terminate prior to a subsequent pulse of write current of an opposite polarity.

US Pat. No. 10,977,176

PREFETCHING DATA TO REDUCE CACHE MISSES

Marvell Asia Pte, Ltd., ...

1. A computer-implemented method of prefetching data into a cache, the computer-implemented method comprising:accessing an entry in memory, wherein the entry is selected using information associated with a first memory request comprising a first virtual address, and wherein the entry comprises first data comprising at least a portion of a second virtual address and also comprises second data comprising at least a portion of a third virtual address;
comparing an arithmetic difference between the first data and the second data with arithmetic differences between a corresponding portion of the first virtual address and the first data and the second data respectively; and
if a result of said comparing is true, determining a fourth virtual address by adding the arithmetic difference between the first data and the second data to the first virtual address and then prefetching the data at the fourth virtual address into the cache.

US Pat. No. 10,971,187

CONSTANT-DENSITY WRITING FOR MAGNETIC STORAGE MEDIA

Marvell Asia PTE, Ltd., ...

1. A method for constant-density writing to magnetic storage media, the method comprising:accepting write data from a host, the write data having an initial bit period associated with a period of a clock signal, the period of the clock signal being fixed according to an angular velocity of a disk of the magnetic storage media;
determining respective bit periods for ones of multiple concentric tracks of a disk of magnetic storage media, each bit period of the respective bit periods associated with a particular concentric track of the multiple concentric tracks, the respective bit periods representing periods of time that vary based on respective radiuses of the multiple concentric tracks; the respective bit periods being configured to maintain a particular bit density across the multiple concentric tracks;
selecting, for the write data, a concentric track from among the multiple concentric tracks, the concentric track being associated with a bit period of the respective bit periods;
prior to writing along the concentric track, generating phase-delayed write data by delaying transitions between bits of the write data according to the bit period associated with the concentric track, the delaying of the transitions being effective to cause bits of the phase-delayed write data to have the bit period associated with the concentric track, the bit period associated with the concentric track being different than the initial bit period associated with the clock signal; and
writing the bits of the phase-delayed write data along the concentric track such that the concentric track has the particular bit density.

US Pat. No. 10,971,996

CHARGE PUMP CIRCUIT WITH INTERNAL PRE-CHARGE CONFIGURATION

Marvell Asia Pte., Ltd., ...

1. A charge pump circuit, comprising:a charge pump configured to
increase a voltage of an input signal to generate a voltage-boosted input signal,
output the voltage-boosted input signal in response to a determination that the voltage-boosted input signal is greater than or equal to a threshold, and
connect the charge pump to a supply voltage that is different from the input signal to pre-charge the charge pump (i) in response to a determination that the voltage-boosted input signal is less than the threshold and (ii) prior to a repeated attempt to increase the voltage of the input signal; and
a bandgap reference generator configured to
receive the voltage-boosted input signal, and
output, based on the voltage-boosted input signal, a voltage reference signal to a device that operates in accordance with the supply voltage.

US Pat. No. 10,959,243

SYSTEMS AND METHODS FOR PROVIDING RESOURCE SIGNALING WITHIN A WIRELESS LOCAL AREA NETWORK (WLAN)

Marvell Asia Pte, Ltd., ...

1. A method for providing resource unit signaling with reduced data bits in a wireless local area network, the method comprising:determining whether bandwidth of a resource unit for transmitting a data frame is greater than an allowed bandwidth; and
in response to determining that the bandwidth of the resource unit is greater than the allowed bandwidth:
virtually dividing the resource unit into a plurality of channels,
grouping channels in the plurality of channels into two half-portions of the plurality of channels,
for each half-portion of the plurality of channels, configuring a signal field-B (SIGB) portion of the data frame to indicate a subset of client stations spatially multiplexed on the resource unit, and
transmitting the data frame including the configured SIGB portions.

US Pat. No. 10,958,504

SYSTEMS AND METHODS FOR OPERATIONS, ADMINISTRATION AND MAINTENANCE (OAM) IN THE PHYSICAL CODING SUBLAYER (PCS)

Marvell Asia Pte, Ltd., ...

1. A method for operation, administration and maintenance (OAM) of data message transmission, the method comprising:embedding a data message loaded in a transmit register of a transmitter as an out-of-band message with physical code sublayer modulation; and
transmitting, to a receiver, the out-of-band message on a physical code sublayer of a physical layer of a link between the transmitter and the receiver.

US Pat. No. 10,929,778

ADDRESS INTERLEAVING FOR MACHINE LEARNING

Marvell Asia Pte, Ltd., ...

1. A system to support a machine learning (ML) operation, comprising:a memory configured to store data;
an array-based inference engine comprising a plurality of processing tiles arranged in a two-dimensional array of a plurality of rows and a plurality of columns, wherein each processing tile comprises at least one or more of
an on-chip memory (OCM) configured to load and maintain data for local access by components in the processing tile; and
one or more processing units configured to perform one or more computation tasks of the ML operation on data in the OCM by executing a set of task instructions; and
a data streaming engine configured to stream data between the memory and the OCMs of the processing tiles of the inference engine, wherein the data streaming engine is configured to interleave an address associated with a memory access transaction for accessing the memory, wherein a subset of bits of the interleaved address is used to determine an appropriate communication channel through which to access the memory.

US Pat. No. 10,901,868

SYSTEMS AND METHODS FOR ERROR RECOVERY IN NAND MEMORY OPERATIONS

Marvell Asia Pte, Ltd., ...

1. A method for error recovery in NAND memory operations, the method comprising:receiving, from a host system, program data having a plurality of program data elements to be written to a NAND memory;
sending the program data to an internal buffer memory and an external buffer memory in parallel;
obtaining a first alert indicative of a first NAND operation error of a first failed program data element;
in response to the first alert, determining a memory address within the external buffer memory, at which a copy of the first failed program data element was previously buffered, based on information identifying the first failed program data element from the first alert;
retrieving the copy of the failed program data element from the external buffer memory based on the determined memory address; and
sending the copy of the first failed program data element to the NAND memory to recover the first NAND operation error.

US Pat. No. 10,892,880

METHOD AND APPARATUS FOR ASYMMETRIC ETHERNET

Marvell Asia Pte., LTD, ...

1. A transceiver integrated circuit (IC) of a BASE-T Ethernet communication system, comprising:a plurality of BASE-T Ethernet transceivers having multiple transmit circuits and multiple receive circuits for coupling to corresponding multiple twisted-pair copper channels;
wherein a first group of one or more of the transmit circuits collectively transmits a first amount of data during a first time interval;
wherein a second group of one or more of the receiver circuits collectively receives a second amount of data that is different from the first amount of data during the first time interval;
wherein after transmitting the first amount of data, the first group of one or more of the transmit circuits is configured,
in a low-power mode, transmit refresh signals during a refresh period of a first time interval, ones of the refresh signals including real data encoded into a sequence of 128 bit values.

US Pat. No. 10,890,644

ANGLE-OF-ARRIVAL PROCESSING IN MULTI-ANTENNA MULTI-CHANNEL SHORT-RANGE WIRELESS SYSTEM

Marvell Asia Pte, Ltd., ...

1. A method for determining, at a receiver in a short-range wireless system having a first plurality of channels and a second plurality of receiving antennas, an angle-of-arrival of a signal from a transmitter in the short-range wireless system, the method comprising:receiving, at at least two of the second plurality of receiving antennas, the signal on one of the first plurality of channels;
determining a phase difference between the signal as received at each of the at least two of the second plurality of receiving antennas;
removing a local oscillator phase value from the phase difference to provide an adjusted phase difference, including determining an angle using signals from multiple channels; and
determining, from the adjusted phase difference, the angle-of-arrival of the signal.

US Pat. No. 10,887,837

WAKEUP RADIO PACKET WITH NEIGHBOR ACCESS POINT INFORMATION

Marvell Asia Pte, Ltd., ...

1. A method, performed by a first communication device, for transmitting a wireless local area network (WLAN) packet to a WLAN network interface device of a second communication device, wherein the second communication device includes a separate wakeup radio (WUR) coupled to the WLAN network interface device, the method comprising:generating, at the first communication device, the WLAN packet to include a WUR identifier associated with a neighbor communication device, wherein the WUR identifier is usable by the WUR of the second communication device to identify WUR packets transmitted by the neighbor communication device, wherein the neighbor communication device is different from the first communication device; and
transmitting, at the first communication device, the WLAN packet to the WLAN network interface device of the second communication device.

US Pat. No. 10,880,855

NULL DATA PACKET (NDP) RANGING MEASUREMENT FEEDBACK

Marvell Asia Pte, Ltd., ...

1. A method, comprising:determining, at a first communication device, which one or more types of feedback information, from among a plurality of types of feedback information associated with a range measurement exchange session, a second communication device is to provide to the first communication device in a feedback packet transmitted as part of a particular ranging measurement exchange in the range measurement exchange session;
transmitting, by the first communication device to the second communication device, one or more indications of the determined one or more types of feedback information that the second communication device is to provide to the first communication device in the feedback packet; and
performing, at the first communication device, the particular range measurement exchange in the range measurement exchange session, including i) transmitting, in the particular range measurement exchange, a null data packet announcement (NDPA) frame to the second communication device, ii) transmitting, in the particular range measurement exchange, a first null data packet (NDP) to the second communication device a short interframe space (SIFS) time period after the transmission of the NDPA frame, iii) determining a delay time period for delaying transmission of a trigger frame to ensure that the second communication device will have a sufficient amount of time to prepare the feedback information using the first NDP, iv) transmitting, during in the particular range measurement exchange, the trigger frame from the first communication device to the second communication device the delay time period after the transmission of the first NDP to cause the second communication device to transmit the feedback packet a SIFS time period after receiving the trigger frame, v) receiving the feedback packet having the determined one or more types of feedback information, the feedback information having been prepared using the first NDP, from the second communication device in response to the trigger frame, and vi) determining a time of flight between the first communication device and the second communication device.

US Pat. No. 10,873,379

SYSTEMS AND METHODS FOR PERFORMING IMPLICIT SOUNDING IN MULTI-USER MULTIPLE INPUT MULTIPLE OUTPUT (MU-MIMO) SYSTEMS

Marvell Asia Pte, Ltd., ...

1. A method for performing beamforming in a multiple-user-multiple-input-multiple-output (MUMIMO) system, the method comprising:receiving, at an MUMIMO access point, an MUMIMO packet from a station of a plurality of stations, wherein the MUMIMO access point has a first number of antennas, and wherein the station has a second number of antennas less than the first number of antennas;
obtaining, from the MUMIMO packet, uplink channel state information representing an uplink channel between the station and the MUMIMO access point, the uplink channel including signals transmitted from the station using the second number of antennas;
computing, based on the uplink channel state information, downlink channel state information representing a downlink channel between the MUMIMO access point and the station, the downlink channel including signals transmitted from the MUMIMO access point using the first number of antennas; and
transmitting data from the MUMIMO access point to the plurality of stations using the first number of antennas based on the downlink channel state information.

US Pat. No. 10,866,811

ARCHITECTURE FOR DENSE OPERATIONS IN MACHINE LEARNING INFERENCE ENGINE

Marvell Asia Pte, Ltd., ...

1. A processing unit of an inference engine for machine learning (ML), comprising:a first bank of registers configured to receive a first stream of data associated with a first matrix data, and wherein the first matrix data is read into the first bank of registers only once;
a second bank of registers configured to receive a second stream of data associated with a second matrix data, and wherein the second matrix data is read into the second bank of registers only once;
a matrix multiplication block configured to perform a multiplication operation based on data received from the first bank of registers and the second bank of registers and output results of the multiplication operation as an output matrix,
wherein each register of the first bank of registers associated with a row of the first matrix stays the same while columns of the second bank of registers associated with the second matrix are fed into the matrix multiplication block one column at a time and multiplied by the each register the first bank of registers associated with the row of the first matrix to generate a partial result of the multiplication operation, wherein each register of the second bank of registers is associated with a column of the second matrix;
wherein, at the same time, each register of the second bank of registers associated with a column of the second matrix stays the same while rows of the first bank of registers associated with the first matrix are fed into the matrix multiplication block one row at a time to be multiplied by the each register of the second bank of registers associated with the column of the second matrix to generate another partial result of the multiplication operation; and
a third bank of registers configured to receive and accumulate the partial results of the multiplication operation from the matrix multiplication block until the multiplication operation is complete.

US Pat. No. 10,838,719

CARRY CHAIN FOR SIMD OPERATIONS

Marvell Asia Pte, Ltd, S...

1. A method for performing an operation on operands, each operand including elements of a selectable size, the method comprising:determining a mask based on a selected size of an element, wherein said determining the mask includes setting a sequence of a plurality of bits of the mask based on the selected size of the element, and wherein bits of the mask correspond to an operation performed on portions of the operands;
selecting, at a subject multiplexer of a plurality of multiplexers, based on a bit, of the plurality of bits of the mask, associated with the subject multiplexer, between carrying a partial result of the operation performed on corresponding first portions of a first operand and a second operand into a next operation and carrying an a priori carry-in into the next operation, wherein a value of the a priori carry-in depends on the operation, the next operation being performed on corresponding second portions of the first operand and the second operand based on the selection; and
storing, in a memory, a result formed from outputs of the operation and the next operation.

US Pat. No. 10,826,649

WIFI RECEIVER ARCHITECTURE

Marvell Asia Pte, Ltd., ...

1. A method, comprising:determining, at a communication device, that a data rate of a data packet exceeds a threshold;
in response to determining that the data rate exceeds the threshold, lowering a processing speed of an equalizer device of the communication device to prevent a buffer from overflowing, wherein the buffer stores outputs generated by the equalizer device;
processing, by a forward error correction code decoder device of the communication device, outputs of the equalizer device corresponding to the data packet to generate decoded information corresponding to the data packet; and
transmitting, by the communication device, an acknowledgment packet to acknowledge the data packet, wherein transmission of the acknowledgment packet begins within a required time period after an end of the data packet, wherein the required time period is defined by a communication protocol.

US Pat. No. 10,817,300

MANAGING COMMIT ORDER FOR AN EXTERNAL INSTRUCTION RELATIVE TO TWO UNISSUED QUEUED INSTRUCTIONS

Marvell Asia Pte, Ltd., ...

1. An integrated circuit comprising:at least a first processor core executing instructions in a pipeline configured for out-of-order issuing of instructions;
translation circuitry configured for handling translation of virtual addresses to physical addresses, the handling including:
storing translations between virtual addresses and physical addresses in a translation lookaside buffer, and
invalidating at least one translation lookaside buffer entry in the translation lookaside buffer before an associated synchronization operation is committed by a commit stage, based at least in part on an external instruction received from outside the first processor core; and
instruction management circuitry configured for managing external instructions received from outside the first processor core, the managing including:
updating issue status information for each of a plurality of instructions stored in an instruction queue,
maintaining an indication of a program order for the plurality of instructions as they are stored in the instruction queue,
processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, the identified instructions including a first queued instruction and a second queued instruction, wherein the first queued instruction is an unissued instruction that is adjacent to an issued instruction in the program order, with no later instructions in the program order having been issued, and the second queued instruction is an unissued instruction that is adjacent to an issued instruction in the program order, with all earlier instructions in the program order having been issued, and
inserting an instruction for performing an operation associated with the first external instruction into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.

US Pat. No. 10,803,890

REDUCING OFFSET OF A DIFFERENTIAL SIGNAL OUTPUT BY A CAPACITIVE COUPLING STAGE OF A HARD DISK DRIVE PREAMPLIFIER

Marvell Asia Pte., Ltd., ...

1. A preamplifier comprising:an input stage; and
a capacitive coupling stage,
wherein the input stage is arranged to receive a differential signal from a magnetic resistor (MR) which indicates a magnetic field sensed on a magnetic disk of a hard disk drive (HDD) when the preamplifier is powered on from an off state to an on state, and
wherein the capacitive coupling stage includes
one or more inputs arranged to receive the differential signal from the input stage,
a filter comprising a first resistor, a second resistor, a first capacitor, and a second capacitor,
an amplifier comprising a first input and a second input, wherein the first capacitor is coupled to the first input and the second capacitor is coupled to the second input,
a first switch and a second switch in parallel with respective resistors, the first switch and the second switch being closed to short the first resistor and the second resistor when the preamplifier is powered on from the off state to the on state and to ground the first input and the second input of the amplifier,
a switch control arranged to determine that an offset of the differential signal has settled and to open the first switch and the second switch based on the determination to cause the first resistor and the second resistor to not be shorted and to not ground the first input and the second input of the amplifier, and
an output arranged to provide a filtered and amplified differential signal.

US Pat. No. 10,796,220

SYSTEMS AND METHODS FOR VECTORIZED FFT FOR MULTI-DIMENSIONAL CONVOLUTION OPERATIONS

Marvell Asia Pte, Ltd., ...

1. A hardware-based programmable deep learning processor (DLP), comprising:an on-system memory (OSM) and one or more controllers configured to access a plurality of external memory resources via direct memory access (DMA);
a plurality of programmable tensor engines configured to perform a plurality of convolution operations by applying one or more kernels on multi-dimensional input data to generate deep learning processing results for pattern recognition and classification based on a neural network, wherein each of the plurality of tensor engines further comprises:
a data engine configured to prefetch the multi-dimensional input data and/or the kernels from the OSM and/or the external memory resources for the convolution operations;
one or more vector processing engines each configured to:
vectorize the multi-dimensional input data at each layer of the neural network to generate a plurality of vectors;
perform multi-dimensional fast Fourier transform (FFT) on the generated vectors and/or the kernels to create output for the convolution operations;
a programmable CPU having its own instruction cache and data cache configured to store a plurality of instructions from a host and the retrieved data from the OSM and/or the external memory resources, respectively.

US Pat. No. 10,775,429

TESTING MONOLITHIC THREE DIMENSIONAL INTEGRATED CIRCUITS

Marvell Asia Pte., Ltd., ...

11. A structure, comprising:a first functional layer having a top surface and a bottom surface, the first functional layer comprising:
first functional components of an integrated circuit (IC), and
first test scan chains connected to the first functional components, the first test scan chains having first input and output connections;
a first inter-layer dielectric (ILD) layer having a top surface and a bottom surface, the bottom surface of the first ILD layer being connected to the top surface of the first functional layer;
a test layer having a top surface and a bottom surface, the bottom surface of the test layer being connected to the top surface of the first ILD layer;
a second ILD layer having a top surface and a bottom surface, the bottom surface of the second ILD layer being connected to the top surface of the test layer;
a second functional layer having a top surface and a bottom surface, the bottom surface of the second functional layer being connected to the top surface of the second ILD layer, the second functional layer comprising:
second functional components of the IC, and
second test scan chains connected to the second functional components, the second test scan chains having second input and output connections;
a third ILD layer having a top surface and a bottom surface, the bottom surface of the third ILD layer being connected to the top surface of the second functional layer and having connections to a testing module,
the test layer comprising:
an interface register controlling signals from the testing module to one of the first test scan chains and the second test scan chains,
an instruction register connected to the interface register, the instruction register processing testing instructions from the testing module,
a test access point (TAP) controller connected to the interface register and the instruction register,
a first multiplexer having data inputs and control inputs comprising a data input from the interface register and a control input from the instruction register, and
a second multiplexer having data inputs and control inputs comprising a first data input from the instruction register and a second data input from an output of the first multiplexer and a control input from the TAP controller; and
inter-layer vias connecting the testing module to the first test scan chains and the second test scan chains through the interface register of the test layer.

US Pat. No. 10,770,100

BALANCED CURRENT MIRRORS FOR BIASING A MAGNETIC RESISTOR IN A HARD DISK DRIVE

Marvell Asia Pte, Ltd., ...

1. A bias circuit comprising:a closed loop gain stage arranged to determine a difference between a first current in a first branch circuit and a second current in a second branch circuit, wherein the first branch circuit and the second branch circuit are coupled to respective terminals of a magnetic resistor (MR); and
a first set of current mirrors and a second set of current mirrors which are balanced, the first set of current mirrors arranged to provide a source current to one of the terminals of the MR and the second set of current mirrors arranged to provide a sink current to another of the terminals of the MR to reduce the difference between the first current and the second current and provide a constant voltage bias to the MR based on a voltage of a voltage source.

US Pat. No. 10,754,967

SECURE INTERRUPT HANDLING BETWEEN SECURITY ZONES

Marvell Asia Pte, Ltd., ...

1. A non-transitory computer-storage medium including instructions that when executed by a processor cause the processor to:in response to receiving an interrupt request from a requesting application executing on the processor in a non-secure processing zone comprising a first virtual machine having a first operating system kernel, tunnel the interrupt request into a secure processing zone comprising a second virtual machine having a second operating system kernel, wherein the interrupt request is a request to utilize one or more secure assets that are maintained within the secure processing zone, said tunneling including context switching from the non-secure processing zone to the secure processing zone, said context switching including halting execution of the requesting application and storing an execution state of the processor;
in response to receiving within the secure processing zone the interrupt request from the non-secure processing zone, issuing, within the secure processing zone, a secure interrupt request to a trusted application that is registered to handle the secure interrupt request, wherein the trusted application is configured to execute when the processor is operating in the secure processing zone in response to said context switching, wherein issuing the secure interrupt request includes identifying the trusted application by determining, within the secure processing zone, which trusted application of a plurality of trusted applications that are registered in a lookup table is registered to handle the secure interrupt request, binding the trusted application to the secure interrupt request in response to the trusted application being installed, and wherein the lookup table correlates different secure interrupt requests with trusted applications that are associated with one or more secure assets; and
service the secure interrupt request by executing the trusted application within the secure processing zone to interact with one or more of the secure assets to fulfill the interrupt request.

US Pat. No. 10,700,699

VOLTAGE-MODE DAC DRIVER WITH PROGRAMMABLE MODE OUTPUT UNITS

Marvell Asia Pte, LTD, S...

1. A digital-to-analog converter (DAC), comprising:input circuitry to receive a digital word of N bits;
an array of N bit processing units disposed in parallel;
wherein each of the N bit processing units comprises
first switch circuitry to generate a first output state based on a first value of a received one of the N bits;
second switch circuitry to generate a second output state based on a second value of the received one of the N bits; and
selectively enabled third switch circuitry to generate, when enabled, a conditional third output state and to cooperate with the first switch circuitry and the second switch circuitry to define a tri-state DAC configuration, the first switch circuitry and the second switch circuitry forming a dual-state DAC configuration when the selectively enabled third switch circuitry is disabled.

US Pat. No. 10,964,357

SKEWED SENSE AMPLIFIER FOR SINGLE-ENDED SENSING

Marvell Asia Pte., Ltd., ...

1. A memory circuit comprising:an integrated pair of memory banks comprising:
a first memory bank comprising a first memory array with first read bitlines; and
a second memory bank comprising a second memory array with second read bitlines, wherein the first memory bank and the second memory bank are alternately and selectively operable such that at any given time one of the first memory bank and the second memory bank is an active memory bank with an active memory array and a different one of the first memory bank and the second memory bank is an inactive memory bank with an inactive memory array; and
a sensing circuit between and connected to the first memory array and the second memory array and comprising skewed sense amplifiers for performing sensing processes during single-ended read operations,
wherein each skewed sense amplifier is configured to receive a data input on data input/output node from a read bitline in the active memory array and a reference input on a reference input/output node from a corresponding read bitline in the inactive memory array and to process the data input and the reference input to determine a stored data value within a selected memory cell that is connected to the read bitline in the active memory array,
wherein each skewed sense amplifier includes (i) two or more first transistors connected in series between the data input/output node and a first terminal, and (ii) one of more second transistors connected in series between the reference input/output node and the first terminal, and
wherein a quantity of the two or more first transistors is greater than a quantity of the one or more second transistors.

US Pat. No. 10,956,202

METHODS AND SYSTEMS FOR TRACKING A VIRTUAL MEMORY OF A VIRTUAL MACHINE

Marvell Asia Pte, Ltd., ...

1. A method comprising:updating by a device, a data structure at a memory for tracking writes to a virtual memory used by a virtual machine executed by a processor to write data to a physical storage device, the device interfacing with the processor to write the data;
in response to a first query request, providing by the device a first list of dirty pages indicating data written using the virtual memory;
detecting by the device a last entry in the first list of dirty pages;
in response to a second query request, providing a second list of dirty pages by the device indicating data that was written to the virtual memory after the last entry; and
providing by the device, a number of dirty pages within the data structure and access to the data structure, after being instructed to stop tracking writes to the virtual memory.

US Pat. No. 10,949,168

COMPRESSING LIKE-MAGNITUDE PARTIAL PRODUCTS IN MULTIPLY ACCUMULATION

Marvell Asia Pte, Ltd., ...

1. A method of operating a processor to generate a summation of multiple multiplications, the method comprising:accessing, by an input interface of an arithmetic logic unit (ALU) of said processor, operands of N pairs of multiplicand and multiplier in binary values;
generating, by a multiply accumulator of said ALU, M partial products for each pair in said N pairs, wherein each of said M partial products of said pair is generated by multiplying a respective digit in a multiplier of said pair with a multiplicand of said pair, wherein said multiplier comprises M digits, and wherein N and M are integers greater than one;
generating, by said multiply accumulator, M summed partial products, wherein each of said M summed partial products is generated by summing partial products across said N pairs that result from a same digit position in N multipliers of said N pairs; and
generating, by said multiply accumulator, a resultant value representing a summed product of said N pairs of multiplicand and multiplier, wherein said generating said resultant value comprises:
adding said M summed partial products; and
adding an aggregated fixup value with said M summed partial products, wherein said aggregated fixup value corresponds to a correction value for all negative partial products of said N pairs.

US Pat. No. 10,930,315

ERROR CORRECTION FOR STORAGE DEVICES

Marvell Asia Pte., Ltd., ...

1. A method for performing error recovery for data stored on a first shingled magnetic recording (SMR) track of a storage device, the method comprising:receiving a request to read the data from the first shingled magnetic recording (SMR) track of the storage device;
identifying a plurality of sectors of the first shingled magnetic recording (SMR) track to be read in response to the request;
reading (i) the data from the plurality of sectors of the first shingled magnetic recording (SMR track, and (ii) parity data;
based on the data read from the plurality of sectors, determining whether any of the plurality of sectors corresponds to a failed sector;
responsive to any of the plurality of sectors corresponding to a failed sector,
recovering a portion of the data from the failed sector of the first shingled magnetic recording (SMR) track using (i) the parity data and (ii) portions of the data stored in remaining ones of the plurality of sectors; and
while recovering the portion of the data from the failed sector of the first shingled magnetic recording (SMR) track, reading data from a second shingled magnetic recording (SMR) track of the storage device.

US Pat. No. 10,891,136

DATA TRANSMISSION BETWEEN MEMORY AND ON CHIP MEMORY OF INFERENCE ENGINE FOR MACHINE LEARNING VIA A SINGLE DATA GATHERING INSTRUCTION

Marvell Asia Pte, Ltd., ...

1. A system to support data gathering for a machine learning (ML) operation, comprising:a memory unit configured to maintain data for the ML operation, wherein the memory unit includes a plurality of memory blocks each accessible via a memory address;
an inference engine comprising a plurality of processing tiles, wherein each processing tile comprises at least:
an on-chip memory (OCM) configured to load and maintain data for local access by components in the processing tile; and
one or more processing units configured to perform one or more computation tasks of the ML operation on the data in the OCM;
a core configured to
program components of the plurality of processing tiles of the inference engine by translating one or more commands from a host into a set of programming instructions for the ML operation according to an instruction set architecture (ISA) designed for data processing in a data-path; and
specify one or more processing tiles via a programming instruction, wherein the programming instruction identifies the one or more OCMs of the one or more processing tiles to have data written into;
a programmable processor configured to stream data between the memory unit and the OCMs of the plurality of processing tiles of the inference engine wherein the programmable processor is configured to perform a data gathering operation via a single data gathering instruction of the ISA to
gather data from one or more memory blocks of the plurality of memory blocks of the memory unit for the ML operation at the same time; and
write the gathered data into the OCM of each of the specified one or more processing tiles for the one or more processing units of the specified one or more processing tiles to perform the one or more computation tasks of the ML operation.

US Pat. No. 10,892,032

WRITE AND READ COMMON LEVELING FOR 4-BIT WIDE DRAMS

Marvell Asia Pte, Ltd., ...

1. An integrated circuit, comprising:memory control logic configured to generate a first strobe signal associated with a first set of bits of data, and further configured to generate a second strobe signal associated with a second set of bits of said data;
write leveling logic configured to obtain a write leveling setting based on feedback of said first set of bits from a memory storage device of a plurality of memory storage devices; and
deskew control logic configured to, while said write leveling logic is anchored at said write leveling setting, obtain a first deskew setting thereof based on feedback of said second set of bits from a memory storage device of said plurality of memory storage devices.

US Pat. No. 10,879,912

DIGITAL PHASE LOCKED LOOP SYSTEM

MARVELL ASIA PTE, LTD., ...

1. A system comprising:a phase locked loop (PLL) circuit comprising:
a time-to-digital converter (TDC) configured to compare a reference clock signal to a feedback clock signal to generate an error signal;
a filter configured to generate a control signal based on the error signal;
a digitally controlled oscillator (DCO) configured to generate an output clock signal based on the control signal;
a multiplexer configured to provide the control signal or a preset value to the DCO based on a preset enable signal, wherein the preset value is determined based on a linearized two-point approximation of DCO characteristics between two frequency end-points of a frequency range that includes a desired output frequency of the output clock signal; and
a divider circuit configured to generate the feedback clock signal from the output clock signal based on ratio values; and
a control circuit coupled to the PLL circuit, the control circuit configured to:
receive data for the desired output frequency of the output clock signal;
determine first gain coefficients and second gain coefficients for the filter, the preset value for the DCO, and the ratio values for the divider circuit based on the data;
provide the preset enable signal to the multiplexer, the preset value to the DCO, the first gain coefficients to the filter, and the ratio values to the divider circuit while the PLL circuit operates in an open-loop configuration;
subsequently operate the PLL circuit in a closed-loop configuration by connecting the filter to the DCO to provide the control signal to the DCO; and
provide the second gain coefficients to the filter in response to detecting a phase lock of the PLL circuit operating in the closed-loop configuration.

US Pat. No. 10,879,928

SCALING OF LOG-LIKELIHOOD RATIOS (LLR) BASED ON LONG TRAINING FIELD (LTF)

MARVELL ASIA PTE, LTD., ...

1. A receiver for receiving a signal comprising a training field and a payload over a communication channel, the receiver comprising:a channel estimator, configured to estimate values of a parameter of the communication channel based on the training field of the received signal, wherein the training field is modulated using a first modulation scheme, and wherein the payload is modulated using a second modulation scheme that is different from the first modulation scheme;
a scaling factor calculator, configured to calculate a scaling factor based on the values of the parameter of the communication channel, and to apply to the scaling factor a correction that depends on the first modulation scheme and on the second modulation scheme;
a metric calculator, configured to calculate soft decoding metrics for use in decoding data carried by the payload of the received signal, including scaling the soft decoding metrics by the scaling factor; and
a decoder, configured to decode the data carried by the payload of the received signal using the scaled soft decoding metrics.

US Pat. No. 10,873,323

SYSTEMS AND METHODS FOR CALIBRATING IMPEDANCE OF A LOW POWER VOLTAGE-MODE TRANSMITTER DRIVER

Marvell Asia Pte, Ltd., ...

1. A low-power transmitter for transmitting digital signals from an integrated chip, the transmitter comprising:a voltage-mode transmitter driver comprised of a plurality of driver slices, wherein each driver slice includes:
an up-cell comprising a first resistor and a first transistor, wherein the up-cell is connected to a voltage source and an output end of the voltage-mode transmitter driver; and
a down-cell comprising a second resistor, a second transistor, and a third transistor, wherein the down-cell is connected to the output end of the voltage-mode transmitter driver and a ground;
a replica circuit comprising a replica of the up-cell and a replica of the down-cell; and
a calibration circuit configured to drive the replica circuit to a desired impedance by adjusting a first gate voltage applied to a first transistor of the replica of the up-cell to be equal to a calibrated first gate voltage and adjusting a second gate voltage applied to a third transistor of the replica of the down-cell to be equal to a calibrated second gate voltage; and
a bias generator configured to:
receive the calibrated first gate voltage and the calibrated second gate voltage from the calibration circuit; and
apply the calibrated first gate voltage to the first transistor and to the second transistor of each of the plurality of driver slices and apply the calibrated second gate voltage to the third transistor of each of the plurality of driver slices.

US Pat. No. 10,873,365

ALIEN CROSSTALK CANCELLATION FOR A MULTIPORT ETHERNET SYSTEM

Marvell Asia Pte., LTD., ...

1. An Ethernet circuit comprising:a first Ethernet port including a first transceiver physical layer circuit (PHY) having a first plurality of channels to transceive first data via a first Ethernet link, the first plurality of channels including respective first transmitters in the first Ethernet port;
a second Ethernet port different from the first Ethernet port and including a second transceiver PHY having a second plurality of channels to transceive second data independent of the first data via a second Ethernet link that is independent of the first Ethernet link, the second plurality of channels including respective second transmitters in the second Ethernet port, wherein at least one of the second plurality of channels is electromagnetically coupled to at least one of the first plurality of channels to establish an alien far-end crosstalk (AFEXT) path, the AFEXT path exposing the first plurality of channels to AFEXT noise that is external to the first plurality of channels; and
pre-cancellation AFEXT filter circuitry coupled between at least one first transmitter input of the first Ethernet port and at least one second transmitter input of the second Ethernet port, the AFEXT filter circuitry configured to cancel the AFEXT noise at the first and second transmitters of the first and second Ethernet ports.

US Pat. No. 10,873,407

TRANSMITTER TUNING USING RECEIVER GRADIENT

Marvell Asia Pte, Ltd., ...

1. A circuit, comprising:a receiver configured to receive a signal from a transmitter;
a monitor configured to measure properties of the signal and generate a figure of merit (FOM) for the signal, the FOM indicating a measure of signal-to-noise;
a controller configured to:
compare the FOM against a record of previous FOMs and corresponding previous transmitter tap values, the transmitter tap value indicating settings of a transmitter equalizer of the transmitter during transmission of the signal;
determine a differential between the FOM and a plurality of the previous FOMs; and
in response to the differential being positive, select a subsequent tap value from a subset of potential tap values; and
an interface configured to send the subsequent tap value to the transmitter for adjustment of the transmitter equalizer.

US Pat. No. 10,840,912

HIERARCHICAL STATISTICALLY MULTIPLEXED COUNTERS AND A METHOD THEREOF

MARVELL ASIA PTE, LTD., ...

1. A method of updating a counter in a counter architecture that includes a hierarchy of levels of statistically multiplexed counters, the method comprising:determining a number of the hierarchy of levels having a corresponding row of the counter in the hierarchy of levels that overflows;
determining a highest level of the number of the hierarchy of levels that is the highest in the hierarchy; and
processing the highest level and each level of the hierarchy of levels below the highest level of the number using a first routine and processing a remainder of the hierarchy of the levels not a part of the number using a second routine.

US Pat. No. 10,831,582

SYSTEMS AND METHODS FOR AN ERROR LOGGING MECHANISM AT CONTROLLER AREA NETWORK BUSES

Marvell Asia Pte, Ltd., ...

1. A method for an error logging mechanism operated with controller area network (CAN) buses within an Ethernet network, the method comprising:receiving, at an Ethernet bridge and from a first CAN controller connected to a first CAN bus, a first interrupt request indicative of a first error condition that occurs at the first CAN bus;
in response to the first interrupt request, servicing, by an Ethernet bridge coupled to the first CAN controller, the first interrupt request by retrieving, from a first error register at the first CAN controller, information relating to the first error condition;
encapsulating at the Ethernet bridge the information relating to the first error condition in a first frame in compliance with a layer 2 transport protocol for time-sensitive applications; and
sending, via an Ethernet switch, the encapsulated first frame to an error logging device installed at a location remote to the first CAN bus.

US Pat. No. 10,824,783

APPROACH FOR LOGIC SIGNAL GROUPING AND RTL GENERATION USING XML

Marvell Asia Pte, Ltd., ...

1. A method, performed by a processor, for generating a register transfer level (RTL) description using logical signal grouping, the method comprising:generating a plurality of logical interface definitions, wherein the plurality of logical interface definitions define signals from an output module to an input module and comprise an interface rule;
defining a data structure in a structured document, wherein the data structure comprises a first set of logical interfaces, and wherein the structured document is used to define the logical signal grouping for each logical interface of the first set of logical interfaces;
executing an expansion script to generate a first RTL description using the structured document, wherein the first RTL description comprises a plurality of RTL modules that communicate using the plurality of logical interface definitions, wherein the first RTL description is populated based on the plurality of logical interface definitions, the interface rule, the logical signal grouping defined in the structured document, and the data structure, and wherein the generated first RTL description facilitates reuse of physical components of an integrated circuit (IC) without implementing physical changes to the physical components to accommodate different placements, routings, and orientations;
modifying a first logical interface from the first set of logical interfaces of the data structure to automatically generate a second RTL description based on the expansion script using the data structure defined in the structured document;
assigning a default value to a first output of a first RTL module of the plurality of RTL modules and testing a second RTL module of the plurality of RTL modules using the first output, wherein the assigning the default value comprises assigning a default value to a logical interface, related to the first RTL module, in the structured document; and
generating objects and sequence items based on the logical signal grouping, wherein the generated objects and the generated sequence items are to be used for error testing and use of drivers and monitors.

US Pat. No. 10,826,146

NETWORKING SYSTEM COMPRISING A WAVEGUIDE THAT CONNECTS A TRANSMITTER TO A RECEIVER, WHERE THE WAVEGUIDE INCLUDES A GUIDING ARRAY HAVING A PERIODIC ARRAY OF CONDUCTIVE ELEMENTS

MARVELL ASIA PTE, LTD., ...

2. A networking system, comprising:a transmitter, configured to generate a millimeter-wave signal carrying data;
a waveguide that is transmissive at millimeter-wave frequencies, the waveguide configured to receive the millimeter-wave signal from the transmitter, and to guide the millimeter-wave signal from the transmitter to a downstream location by having a dielectric constant that varies over a transversal cross-section of the waveguide in accordance with a predefined profile;
a guiding adapter inserted between sections of the waveguide, the adapter comprising (i) an adapter body, and (ii) a guiding array comprising electrically-conductive elements that are disposed at periodic intervals along the adapter body for guiding the millimeter-wave signal along the adapter body; and
a receiver, at the downstream location, configured to receive the millimeter-wave signal guided by the waveguide, and to extract the data carried by the received millimeter-wave signal.

US Pat. No. 10,826,489

SELECTION CIRCUIT

Marvell Asia Pte, Ltd., ...

1. A voltage selection comprising:a first device and a second device connected to output an output signal, wherein the voltage selection circuit is configured to output a higher voltage of a first supply voltage and a second supply voltage through one of the first device and the second device, and wherein a voltage difference between the first supply voltage and the second supply voltage is less than a threshold voltage; and
a third device comprising an NWELL having a same voltage potential as the output signal.

US Pat. No. 10,812,244

ACKNOWLEDGMENT OF UPLINK ORTHOGONAL FREQUENCY DIVISION MULTIPLE ACCESS TRANSMISSION

Marvell Asia Pte, Ltd., ...

1. A method for communicating in a wireless communication network, the method comprising:receiving, at the first communication device, an uplink orthogonal frequency multiple access (OFDMA) transmission, wherein the uplink OFDMA transmission includes respective data units from multiple second communication devices, wherein the respective data units include respective indications of respective acknowledgment policies corresponding to the respective data units, wherein a first acknowledgement policy among the respective acknowledgment policies indicates that a first data unit, among the respective data units, is to be acknowledged prior to any subsequent transmission from any of the multiple second communication devices, and wherein a second acknowledgement policy among the respective acknowledgment policies indicates that a second data unit, among the respective data units, is to be acknowledged only after the corresponding second communication device has transmitted a subsequent data unit in a subsequent uplink OFDMA transmission;
generating, at the first communication device, an acknowledgment physical layer (PHY) data unit to acknowledge at least the first data unit and the second data unit; and
transmitting, with the first communication device, the acknowledgment PHY data unit in a downlink transmission to acknowledge at least the first data unit and the second data unit, including one of:
i) transmitting the downlink transmission prior to any subsequent transmission from any of the multiple second communication devices, or
ii) transmitting the downlink transmission only after receiving the subsequent uplink OFDMA transmission.

US Pat. No. 10,782,907

METHOD AND SYSTEM FOR RECONFIGURABLE PARALLEL LOOKUPS USING MULTIPLE SHARED MEMORIES

MARVELL ASIA PTE, LTD., ...

1. A system on-chip comprising:a pool of T×M shared memories are grouped into T tiles;
M index converters for each of N lookup paths; and
N output result collectors, wherein the system is configured to perform N parallel lookups against the pool of T×M shared memories along the N lookup paths, wherein N, T and M are positive integer values,
wherein the system is configured to support the N parallel lookups using the pool of shared memories.

US Pat. No. 10,776,119

COMBINED CONDITIONAL BRANCH AND INDIRECT BRANCH TARGET PREDICTOR

MARVELL ASIA PTE, LTD., ...

1. A branch predictor circuit comprising:a combined predictor table configured to store at least one tagged conditional branch prediction in combination with at least one tagged indirect branch target prediction, the at least one tagged indirect branch target prediction configured to include a predicted partial target address of a complete target address, the complete target address associated with an indirect branch instruction of a processor; and
prediction logic configured to use the predicted partial target address to produce a predicted complete target address of the complete target address for use by the processor prior to execution of the indirect branch instruction.

US Pat. No. 10,747,543

MANAGING TRACE INFORMATION STORAGE USING PIPELINE INSTRUCTION INSERTION AND FILTERING

Marvell Asia Pte, Ltd., ...

1. An integrated circuit comprising:at least a first processor core executing instructions in a pipeline, wherein at least some of the instructions are each associated with corresponding trace information that characterizes execution of that instruction in the pipeline; and
control circuitry configured to manage a flow of a predetermined type of store instructions through a subset of contiguous stages of the pipeline that includes at least one memory access stage, wherein the managing includes:
receiving a signal to store a portion of the trace information,
stalling a stage before the subset of contiguous stages of the pipeline,
inserting a store instruction of the predetermined type into a stage at the beginning of the subset of contiguous stages of the pipeline to enable the store instruction of the predetermined type to reach the memory access stage at which an operand of the store instruction of the predetermined type including the portion of the trace information is sent out of the pipeline, and
filtering the store instruction of the predetermined type from a stage of the subset of contiguous stages of the pipeline that occurs earlier in the pipeline than a stage in which trace information is generated.

US Pat. No. 10,742,262

METHOD AND SYSTEM FOR ETHERNET ACTIVE-PAIR DETECTION

Marvell Asia Pte. Ltd., ...

1. A method of signaling between Ethernet transceiver link partners along a link, the link including between one to four twisted pair channels, the method comprising:in an offline mode of operation,
autonegotiating between the link partners during an autonegotiation sequence;
discovering a number of active pairs out of the one to four pairs of twisted pair channels, the discovering including
transmitting a discovery signal from a transmit end of the link on the active pairs,
detecting the transmitted discovery signal at a receive end of the link, the detecting including measuring a power parameter associated with the discovery signal and comparing the measured power parameter to an expected power parameter, the number of active pairs based on a result of the comparing, and
identifying the active pairs based on the detecting;
training the link active pairs to train transceiver operating parameters with a training sequence of symbols; and
in an online mode of operation,
operating the link in a data transfer mode utilizing at least one of the identified active pairs.

US Pat. No. 10,740,256

RE-ORDERING BUFFER FOR A DIGITAL MULTI-PROCESSOR SYSTEM WITH CONFIGURABLE, SCALABLE, DISTRIBUTED JOB MANAGER

Marvell Asia Pte, Ltd., ...

1. An apparatus for reordering out-of-order information provided by one or more memories into correct order, comprising:a free pool buffer comprising a first logical memory structure;
a deadlock avoidance buffer comprising a second logical memory structure; and
a controller communicatively coupled to the free pool buffer and the deadlock avoidance buffer.

US Pat. No. 10,735,236

SYSTEMS AND METHODS TO REDUCE PEAK TO AVERAGE POWER RATIO FOR DUAL SUB-CARRIER MODULATED TRANSMISSIONS IN A WIRELESS NETWORK

MARVELL ASIA PTE, LTD., ...

1. A system comprising:a modulator to (i) modulate data using a first modulation scheme and dual sub-carrier modulation, wherein the dual sub-carrier modulation modulates the same information on a pair of subcarriers, and (ii) generate modulated symbols for transmission on a plurality of subcarriers;
a repetition module to repeat the modulated symbols from a first half of the plurality of subcarriers to a second half of the plurality of subcarriers; and
a phase rotation module to rotate phase of the modulated symbols on selected subcarriers of the second half of the plurality of subcarriers,
wherein the selected subcarriers of the second half of the plurality of subcarriers include all of the second half of the plurality of subcarriers.

US Pat. No. 10,734,334

COAXIAL-INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR COMPONENT

MARVELL ASIA PTE, LTD., ...

1. A semiconductor component comprising:a packaging substrate having complementary signal and ground traces that are formed at separate conductive layers of the packaging substrate;
an integrated-circuit (IC) die having complementary signal and ground pads; and
a coaxial-interconnect structure, the coaxial-interconnect structure being configured to electrically couple the complementary signal and ground pads of the IC die to the complementary signal and ground traces of the packaging substrate, wherein at least two elements of the coaxial-interconnect structure are deposited onto the complementary signal and ground pads of the IC die, the elements of the coaxial-interconnect structure comprising:
a signal core elongated about an axis that is (i) orthogonal to a plane of the IC die that contains the signal and ground pads and (ii) orthogonal to a plane of the packaging substrate that contains the corresponding signal and ground traces;
a ground shield elongated about the axis and disposed such that the ground shield encloses a perimeter of the signal core; and
an insulator disposed between the signal core and the ground shield.

US Pat. No. 10,616,001

FLEXIBLE PROCESSOR OF A PORT EXTENDER DEVICE

Marvell Asia Pte, Ltd., ...

1. A method for egress processing packets in a network device, the method comprising:identifying, with a first stage engine implemented in hardware, a particular set of computer-readable instructions, for a particular packet, the particular set of computer-readable instructions being identified from among a plurality of sets of computer-readable instructions stored in a memory, respective ones of the plurality of sets of computer-readable instructions being for performing different sets of egress processing operations with respect to different packets;
generating, with the first stage engine implemented in hardware, metadata to be used for performing egress processing operations with respect to the particular packet, the metadata including a template populated with header information according to a particular format of a forwarding tag to be inserted into a header of the particular packet; and
executing, with a second stage processor configured to execute computer-readable instructions stored in the memory, the particular set of computer-readable instructions, identified by the first stage engine, to perform the corresponding set of egress processing with respect to the particular packet, the corresponding set of egress processing operations including inserting the forwarding tag populated with the header information into the header of the particular packet.

US Pat. No. 10,998,941

MULTI-BAND TRANSMISSION SYSTEM

Marvell Asia Pte, Ltd., ...

1. An apparatus, comprising:a network interface device including:
a separator circuit configured to separate data into a plurality of frequency bands, wherein
each frequency band has an associated symbol time,
each associated symbol time is a whole multiple of one half of a smallest symbol time of all of the frequency bands to facilitate synchronized transmission of symbols over the plurality of frequency bands, and
wherein the network interface device further includes:
i) a first multiple input, multiple output (MIMO) processing circuit configured to multiplex the data into a plurality of spatial channels, and
ii) a first analog front end circuit configured to, for each spatial channel of the plurality of spatial channels,
combine data in the plurality of frequency bands, including combining data in a first frequency band with data in a second frequency band different from the first frequency band, into a respective combined signal for simultaneous transmission over the plurality of frequency bands, and
transmit the combined signal via a transmission medium, wherein transmission of symbols in the first frequency band is synchronized with transmission of symbols in the second frequency band.

US Pat. No. 10,998,953

GROUP ADDRESSING FOR BEAMFORMING TRAINING

Marvell Asia Pte, Ltd., ...

1. A method for performing beamforming training in a wireless communication network, the method comprising:generating, at a first communication device, a beamforming training initiator packet for transmission in the wireless communication network, the beamforming training initiator packet indicating a start of a beamforming training session, the beamforming training initiator packet generated to include a plurality of fields that respectively and individually identify multiple second communication devices that are to process beamforming training packets transmitted by the first communication device during the beamforming training session;
transmitting, by the first communication device, the beamforming training initiator packet; and
after transmitting the beamforming training initiator packet, transmitting, by the first communication device, a plurality of beamforming training packets during the beamforming training session.

US Pat. No. 10,996,957

SYSTEM AND METHOD FOR INSTRUCTION MAPPING IN AN OUT-OF-ORDER PROCESSOR

MARVELL ASIA PTE, LTD., ...

1. A system for instruction mapping in an out-of-order (OoO) processor, the system comprising:a mapper configured to map instructions by mapping integer and floating-point (FP) architectural registers (ARs) of the instructions to integer and FP physical registers (PRs) of the OoO processor, respectively, based on integer mapper state and FP mapper state of the mapper, respectively, and to record, via at least one FP present indicator, presence of FP ARs used as destinations in the instructions; and
integer circuitry and FP snapshot circuitry, the mapper further configured to copy, periodically, the integer mapper state to the integer snapshot circuitry and to copy intermittently, based on the at least one FP present indicator, the FP mapper state to the FP snapshot circuitry.

US Pat. No. 10,998,001

INTERLEAVER FOR DISTRIBUTED SECTOR STORAGE

Marvell Asia Pte, Ltd., ...

1. A method of storing data in a plurality of groups of logical data sectors, each respective group of logical data sectors including a respective number of logical data sectors, across a plurality of contiguous data tracks of a data storage medium, the method comprising:defining a plurality of interleaver patterns, each interleaver pattern including a sector interleaving pattern specifying a respective order in which segments of respective ones of the logical data sectors are spread across physical data sectors of a respective one of the plurality of contiguous data tracks;
selecting, for each respective group of logical data sectors, a respective interleaver pattern from the plurality of interleaver patterns; and
writing data from each respective group of logical data sectors to one of the data tracks in the plurality of contiguous data tracks using the selected respective interleaver pattern, each respective group of logical data sectors being written to its respective data track using a different one of the plurality of interleaver patterns from any other group of logical data sectors written to a data track adjacent to the respective data track.

US Pat. No. 10,996,738

SYSTEM AND METHOD FOR COMPENSATING FOR A DROOP EVENT

Marvell Asia Pte, Ltd., ...

1. A system comprising:a droop detection circuitry configured to determine whether a droop event has occurred by determining a half cycle of a clocking signal using a first plurality of delay elements, wherein the droop detection circuitry is further configured to output a signal indicating whether the droop event has occurred;
a second plurality of delay elements, wherein each delay element of the second plurality of delay elements responsive to the signal indicating that the droop event has occurred is configured to receive the clocking signal and further configured to delay the clocking signal to form an output clocking signal; and
a controller configured to select a rising edge from the output clocking signal of a delay element of the second plurality of delay elements and wherein the controller is further configured to select a falling edge from the output clocking signal of another delay element of the second plurality of delay elements to form a modified clocking signal.

US Pat. No. 10,997,510

ARCHITECTURE TO SUPPORT TANH AND SIGMOID OPERATIONS FOR INFERENCE ACCELERATION IN MACHINE LEARNING

Marvell Asia Pte, Ltd., ...

1. A processing unit to support inference acceleration for machine learning (ML), comprising:an inline post processing unit configured to
accept and maintain one or more lookup tables for performing a tanh and/or sigmoid operation;
accept data from a set of registers configured to maintain output from a processing block instead of streaming the data from an on-chip memory (OCM);
perform the tanh and/or sigmoid operation on each element of the data from the processing block on a per-element basis via the one or more lookup tables;
stream post processing result of the per-element tanh and/or sigmoid operation back to the OCM after the tanh and/or sigmoid operation is complete.

US Pat. No. 10,999,049

PHASE AND FREQUENCY CONTROL FOR CLOCK-DATA RECOVERY

Marvell Asia Pte, Ltd., ...

1. A method of controlling at least one of phase and free-running frequency of an injection-locked oscillator in a clock-data recovery circuit, the method comprising:reducing contribution of inter-symbol interference to a measurement of phase error in an input data signal, by detecting occurrence of a first data pattern in the input data signal, the first data pattern being indicative of saturation of inter-symbol interference in the input data signal and, upon detecting occurrence of saturation of inter-symbol interference in the input data signal, as indicated by the first data pattern:
measuring the input data signal at a first clock edge to determine a first data phase measurement value, and
measuring the input data signal at clock centers immediately preceding and immediately following the first clock edge to determine second and third data phase measurement values; and
based on first predetermined relationships among the first, second and third data phase measurement values, determining a phase error component other than phase error caused by inter-symbol interference and adjusting a variable data path delay to correct the phase error component other than phase error caused by inter-symbol interference.

US Pat. No. 10,999,124

RAPID RATE ADAPTATION IN NBASE-T ETHERNET

Marvell Asia Pte, LTD., ...

1. A method for fast link recovery for an Ethernet link, the method comprising:operating the Ethernet link at a first data rate using an adaptive filter having first filter coefficients based on the first data rate;
detecting a drop in link quality on the Ethernet link;
performing a first fast retrain sequence to improve the link quality; and
if the first fast retrain sequence fails to recover the link quality, reducing the first data rate to a reduced data rate, and performing a second fast retrain sequence including low-pass filtering the first filter coefficients to obtain filtered coefficients and subsampling the filtered coefficients to generate updated filter coefficients for the adaptive filter.

US Pat. No. 10,997,077

INCREASING THE LOOKAHEAD AMOUNT FOR PREFETCHING

Marvell Asia Pte, Ltd., ...

1. A computer-implemented method of prefetching, the computer-implemented method comprising:in response to a memory request to load data from a second virtual address, accessing a data structure comprising a plurality of entries, each entry of the plurality of entries associated with a respective prefetch;
determining whether the memory request corresponds to any entry in the data structure, the entry comprising a first virtual address and a prefetch stride;
when the memory request corresponds to an entry in the data structure, incrementing a value of a counter associated with the entry and then determining whether the value of the counter satisfies a threshold; and
issuing a first prefetch request comprising the second virtual address incremented by the prefetch stride and also comprising a lookahead amount, wherein the lookahead amount is a first lookahead amount if the value of the counter does not satisfy the threshold, wherein the lookahead amount is a second lookahead amount if the value of the counter satisfies the threshold, and wherein the second lookahead amount is greater than the first lookahead amount.

US Pat. No. 10,998,910

METHOD AND APPARATUS FOR CONTROLLING CLOCK CYCLE TIME

MARVELL ASIA PTE, LTD., ...

1. A circuit comprising:an agile ring oscillator (ARO) including at least one instance of a first ring oscillator (RO) and a second RO, the first and second ring oscillators configured to generate high and low phases, respectively, of cycles of an output clock used to clock at least one other circuit; and
an ARO controller configured to (i) control durations of the high and low phases, independently, via first and second control words output to the ARO, respectively, and (ii) in a present cycle of the output clock, effect a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle.

US Pat. No. 10,985,156

ELECTROSTATIC DISCHARGE CLAMP WITH REDUCED OFF-STATE POWER CONSUMPTION

Marvell Asia Pte., Ltd., ...

1. An electrostatic discharge (ESD) protection circuit comprising:one or more inverters connected to a timing circuit, wherein a first one of the one or more inverters receives, as an input signal, a first output signal from the timing circuit;
a first transistor that receives (i) a second output signal from a last of the one or more inverters and (ii) the first output signal from the timing circuit;
a second transistor, wherein a gate of the second transistor is connected to an output of the first transistor, in series; and
a negative voltage source that outputs a voltage separate from the output of the first transistor to the gate of the second transistor; and
a resistor directly connected between the negative voltage source and the gate of the second transistor.

US Pat. No. 10,977,199

MODIFYING NVME PHYSICAL REGION PAGE LIST POINTERS AND DATA POINTERS TO FACILITATE ROUTING OF PCIE MEMORY REQUESTS

Marvell Asia Pte, Ltd., ...

1. A method comprising:receiving at a non-volatile memory express switch a first command from a host of a storage system, wherein the first command comprises a first physical region page entry and a second physical region page entry and conforms to a non-volatile memory express standard, wherein the first physical region page entry includes a first data pointer, and wherein the second physical region page entry includes a second data pointer or a list pointer;
modifying the first physical region page entry with a host identifier of the host;
determining content to include in the second physical region page entry based on whether the second physical region page entry includes the second data pointer or the list pointer;
modifying the second physical region page entry to include the determined content;
sending, from the non-volatile memory express switch to a solid state drive, a second command with a plurality of entries, wherein the plurality of entries include the modified first physical region page entry and the modified second physical region page entry;
receiving a memory request from the solid state drive at the non-volatile memory express switch, wherein the memory request comprises the plurality of entries; and
routing the memory request from the non-volatile memory express switch to the host based on the host identifier in the memory request.

US Pat. No. 10,978,592

SYSTEMS AND METHODS FOR FORMING FINFET ANALOG DESIGNS HAVING A MODULAR MEMORY-LIKE LAYOUT

Marvell Asia Pte., Ltd., ...

1. A method of forming a fin field effect transistor (finFET), the method comprising:providing a semiconductor substrate including at east one fin feature;
forming a diffusion layer on the semiconductor substrate, wherein the at least one fin feature extends through the diffusion layer;
forming a gate layer on the diffusion layer and the at least one fin feature;
splitting the gate layer into a split gate structure including a first gate region, a second gate region, and a gap separating the first gate region and the second gate region;
doping the gate layer;
doping the diffusion layer to form a plurality of source/drain regions, wherein the plurality of source/drain regions includes a source/drain region in the gap between the first gate region and the second gate region; and
injecting dopants into the diffusion layer to form a diffusion region having a plurality of pocket dopant regions, wherein the plurality of pocket dopant regions includes at least one pocket dopant region in the gap between the first gate region and the second gate region.

US Pat. No. 10,978,143

MULTI-PORT HIGH PERFORMANCE MEMORY

Marvell Asia Pte, Ltd., ...

1. A memory circuit comprising:a memory bitcell comprising a single ended read port and configured to store a bit of data;
a timer circuit configured to receive a clock signal and generate two successive pulses during a single cycle of the clock signal and, based on the two successive pulses, generate first control signals to enable asynchronous reading of the single ended read port during the single cycle of the clock signal; and
a read circuit connected to the single ended read port of the memory bitcell the read circuit being configured to, based on the first control signals, perform two successive reads of the single ended read port during the single cycle of the clock signal and output respective states of the memory bitcell read during the two successive reads of the single ended read port.

US Pat. No. 10,979,688

MATCHING MERIT VALUE BASED STEREO VISION MATCHING INCLUDING DISPARITY REFINEMENT

Marvell Asia Pte, Ltd., ...

1. A system comprising:one or more memories configured to store (i) first pixel data corresponding to a first image frame, and (ii) second pixel data corresponding to a second image frame; and
a control module configured to
perform stereo vision matching comprising
accessing the first pixel data and the second pixel data,
determining initial disparity values, wherein the initial disparity values indicate differences between (i) the first pixel data and (ii) the second pixel data,
determining cost aggregation values based on the initial disparity values,
determining a plurality of matching merit values for the first pixel data based on the cost aggregation values,
based on the plurality of matching merit values, determining first histogram aggregation values for first pixels of the first image frame, and
refining the initial disparity values based on the first histogram aggregation values; and
estimate a depth of a feature or an object based on the refined disparity values.

US Pat. No. 10,972,293

ADAPTIVE ENERGY EFFICIENT ETHERNET

Marvell Asia Pte., LTD., ...

1. An Ethernet transceiver, comprising:transceiver circuitry including:
receiver circuitry to receive refresh signals from a link partner during a low-power idle mode of operation, each refresh signal having a refresh period and a quiet period, wherein the quiet period is interposed between successive refresh signals,
signal quality detection circuitry to, during the low-power idle mode, determine a measure of signal quality associated with the received refresh signals, and
circuitry to communicate to the link partner a signal based on the measure of signal quality of the received refresh signals for adjusting at least one of the refresh period or the quiet period.

US Pat. No. 10,970,080

SYSTEMS AND METHODS FOR PROGRAMMABLE HARDWARE ARCHITECTURE FOR MACHINE LEARNING

Marvell Asia Pte, Ltd., ...

1. A programmable hardware system for machine learning (ML), comprising:a memory configured to receive data from a host to be analyzed and/or inferred via machine learning;
a core configured to receive a plurality of commands from the host and wherein the core is further configured to coordinate components in the system to perform a ML operation on the data, wherein said core is further configured to interpret and divide the plurality of commands received from the host into a first set of commands selected from the plurality of commands for dense operations, a second set of commands selected from the plurality of commands for irregular operations of the ML operation, and a third set of commands selected from the plurality of commands for operations other than dense and irregular operations, wherein the core is further configured to provide the first and the second set of commands via an instruction-streaming engine;
a dense operation engine configured to execute the first set of commands received from the host to perform the dense operations of the ML operation;
an irregular operation engine configured to execute the second set of commands received from the host to perform the irregular operations of the ML operation;
a general processor configured to execute the third set of commands received from the host to perform the operations other than dense and irregular operations of the ML operation;
said instruction-streaming engine coupled to the core, a data streaming engine, the dense operation engine, and the irregular operation engine, wherein the instruction-streaming engine is configured to stream a first set of programming instructions associated with the first and the second set of commands to the dense and the irregular operation engines; and
said data steaming engine coupled to the dense and irregular operation engines and configured to generate one or more streams of data from the memory to be analyzed and/or inferred by the dense and irregular operation engines; and
said dense and irregular operation engines configured to
receive the data and the first set of programming instructions from the data streaming engine and the instruction-streaming engine, respectively; and
perform the first and second set of commands by executing the first set of programming instructions to analyze the streams of data received from the data streaming engine.

US Pat. No. 10,964,362

THREE-PORT MEMORY CELL AND ARRAY FOR IN-MEMORY COMPUTING

Marvell Asia Pte, Ltd., ...

1. A memory cell comprising:a first storage node configured to store a bit of data;
a first read pass-gate transistor and a first read pull-down transistor connected in series between a common read bitline and a first voltage rail, wherein a gate of the first read pass-gate transistor is connected to a first read wordline, and wherein a gate of the first read pull-down transistor is connected to the first storage node;
a second storage node configured to store a one's complement of the bit of data;
a second read pass-gate transistor and a second read pull-down transistor connected in series between the common read bitline and the first voltage rail, wherein a gate of the second read pass-gate transistor is connected to a second read wordline, and wherein a gate of the second read pull-down transistor is connected to the second storage node;
a capacitor connected to the common read bitline and controlling a discharge rate of the common read bitline to prevent a voltage level on the common read bitline from fully discharging to a ground reference voltage level during stepping down of the voltage level on the common read bitline;
a first write pass-gate transistor connected to the first storage node; and
a second write pass-gate transistor connected to the second storage node,
wherein a gate of the first write pass-gate transistor and a gate of the second write pass-gate transistor are connected to a same write wordline for concurrent write access to the first storage node and the second storage node.

US Pat. No. 10,951,523

PORT EXTENDER WITH LOCAL SWITCHING

Marvell Asia Pte, Ltd., ...

1. A port extender for use in a switching system comprising a controlling switch and one or more other port extenders, the port extender comprising:at least one local upstream port coupled to the controlling switch directly or via another port extender;
a plurality of local downstream ports; and
a packet processor coupled to the at least one local upstream port and the plurality of local downstream ports, the packet processor including, or being coupled to, a forwarding database that is populated with entries indicating associations between i) respective network addresses corresponding to devices coupled to local downstream ports of the port extender a) directly or b) via one or more other port extenders downstream from the port extender, and ii) respective local downstream ports of the port extender, wherein the forwarding database excludes entries corresponding to network addresses corresponding to devices coupled directly, or via another port extender upstream from the port extender, to the at least one local upstream port of the port extender, wherein the packet processor is configured to:
for at least some network address/port associations in the forwarding database,
determine whether a particular packet was received i) via a port that is one of the local downlink ports of the port extender or ii) via the at least one uplink port of the port extender, and
when it is determined, at the port extender, that the particular packet was received via a port that is one of the local downstream ports of the port extender and not via the at least one uplink port of the port extender, a) learn a first association between i) a network address associated with the particular packet and ii) the corresponding local downstream port at which the particular packet was received at the port extender and b) if the particular packet was received by the port extender from another port extender among the one or more other port extenders downstream from the port extender, additionally learn at least a second association between i) the network address associated with the particular packet and ii) a port at which the particular packet was first received by the switching system, and
for a first packet i) received via one of the local downstream ports, and ii) having a destination network address in the forwarding database, forward the first packet to a different local downstream port indicated by the forwarding database, and
for a second packet i) received via one of the local downstream ports, and ii) having a destination network address not in the forwarding database, forward the second packet to the at least one local upstream port.

US Pat. No. 10,950,325

MEMORY BUILT-IN SELF TEST ERROR CORRECTING CODE (MBIST ECC) FOR LOW VOLTAGE MEMORIES

Marvell Asia Pte., Ltd., ...

1. A memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory, the MBIST circuit comprising:a scratchpad module configured to store failures for the plurality of patterns of the sliding window,
wherein the scratchpad module is configured to compare a row of an incoming cell failure of the plurality of patterns of the sliding window with a row of previously stored failures to (i) determine whether the incoming failure is a single cell failure for the single wordline and (ii) determine whether the incoming failure is a multi-cell failure for the single wordline; and
a repair module configured to selectively repair both the single cell failure and the multi-cell failure, wherein the repair module is configured to (i) in response to the scratchpad module determining that the incoming cell failure is the multi-cell failure, repair the multi-cell failure and (ii) in response to the scratchpad module determining that the incoming cell failure is the single cell failure, leave the single cell failure unrepaired,
wherein the MBIST circuit is configured to complete repair of multi-cell failures in the memory and clear the scratchpad module to leave any single cell failures in the memory unrepaired.

US Pat. No. 10,943,615

DIFFERENTIAL INTERFACE TRANSMISSION OF FLY-HEIGHT CONTROL DATA

MARVELL ASIA PTE, LTD., ...

1. A method for controlling fly-height of a read/write (RW) head, the method comprising:in response to a servo gate signal, applying an FHC mode signal; and
in response to the FHC mode signal, transmitting FHC data over a differential interface to a preamplifier disposed in a head-disk assembly;
wherein the transmitting FHC data over the differential interface comprises, in response to the FHC mode signal, transmitting the FHC data from a RW channel to the preamplifier through a first differential interface port; and
in response to the FHC mode signal, transmitting a clock signal that is synchronized with the FHC data from the RW channel to the preamplifier through a second differential interface port, wherein the first differential interface port and the second differential interface port each include differential signaling circuitry within the RW channel and the preamplifier.

US Pat. No. 10,929,760

ARCHITECTURE FOR TABLE-BASED MATHEMATICAL OPERATIONS FOR INFERENCE ACCELERATION IN MACHINE LEARNING

Marvell Asia Pte, Ltd., ...

1. A processing unit to support inference acceleration for machine learning (ML), comprising:an inline post processing unit configured to
accept and maintain one or more lookup tables for performing each of one or more non-linear mathematical operations;
accept data from a set of registers maintaining a final output from a processing block instead of streaming the data from an on-chip memory (OCM);
divide the one or more non-linear mathematical operations into multiple sections, where each section is represented by a curve that is extrapolated based on a specific lookup table;
determine a value of the one or more non-linear mathematical operations by referencing the specific lookup table for each section of the multiple sections associated with an input value to perform the one or more non-linear mathematical operations on elements of the data from the processing block;
stream post processing result of the one or more non-linear mathematical operations back to the OCM after the one or more non-linear mathematical operations are complete.

US Pat. No. 10,929,779

ARCHITECTURE TO SUPPORT SYNCHRONIZATION BETWEEN CORE AND INFERENCE ENGINE FOR MACHINE LEARNING

Marvell Asia Pte, Ltd., ...

1. A system to support a machine learning (ML) operation, comprising:a core configured to receive and interpret one or more commands from a host into a set of instructions for the ML operation;
a memory unit configured to maintain data for the ML operation;
an inference engine comprising one or more processing tiles, wherein each processing tile comprises at least one or more of
an on-chip memory (OCM) configured to load and maintain data for local access by components in the processing tile;
one or more processing units configured to perform one or more computation tasks of the ML operation on the data in the OCM by executing the set of instructions;
an instruction streaming engine configured to
distribute the set of instructions to corresponding processing tiles of the inference engine to control their operations, wherein each instruction of the set of instruction is associated with a color and wherein instructions with a same color are distributed to a subset of the one or more processing tiles via a tile mask;
synchronize data communication between the memory unit and the inference engine, wherein the synchronization ensures that the one or more processing tiles receive a correct data to perform tasks on the correct data, and wherein the synchronization ensures coherence of data shared and distributed among the core and the OCMs of the inference engine.

US Pat. No. 10,928,505

NULL DATA PACKET (NDP) ANNOUNCEMENT FRAME AND TRIGGER FRAME FOR NDP RANGING

Marvell Asia Pte, Ltd., ...

13. An apparatus, comprising:a network interface device associated with a first communication device, wherein the network interface device includes one or more integrated circuits (ICs), and wherein the network interface device is configured to:
receive a null data packet (NDP) announcement (NDPA) frame, wherein the NDPA frame is from a second communication device and indicates that the second communication device will transmit an NDP transmission after transmitting the NDPA frame, and wherein the NDPA frame includes at least one of a) an indicator of whether the first communication device is to provide angle of arrival information in a feedback packet as part of a ranging measurement exchange session, and b) an indicator of whether the first communication device is to provide angle of departure information in the feedback packet,
process the NDPA frame, including processing information in the NDPA frame to determine that the NDPA frame is part of the ranging measurement exchange session and to determine at least one of i) whether the first communication device is to provide angle of arrival information in the feedback packet, and ii) whether the first communication device is to provide angle of departure information in the feedback packet, using the at least one of a) the indicator of whether the first communication device is to provide angle of arrival information in the feedback packet, and b) the indicator of whether the first communication device is to provide angle of departure information in the feedback packet,
receive a first NDP after receiving the NDPA frame as part of the ranging measurement exchange session,
transmit a second NDP to the second communication device as part of the ranging measurement exchange session,
generate the feedback packet to include feedback information regarding the ranging measurement exchange session, including generating the feedback information in the feedback packet to be consistent with the at least one of a) the indicator of whether the first communication device is to provide angle of arrival information in the feedback packet, and b) the indicator of whether the first communication device is to provide angle of departure information in the feedback packet, and
transmit the feedback packet to the second communication device as part of the ranging measurement exchange session.

US Pat. No. 10,928,870

APPARATUS AND METHODS FOR TEMPERATURE-BASED MEMORY MANAGEMENT

Marvell Asia PTE, Ltd.

1. A method comprising:receiving, from multiple temperature sensors of a memory block, respective indications of temperature at different locations of the memory block, each of the multiple temperature sensors disposed (i) between respective storage cells of the memory block and (ii) at one of the different locations, the memory block operating in accordance with a frequency of a clock signal;
generating, based on the respective indications of temperature at the different locations of the memory block, a temperature map of respective temperatures of multiple areas of the memory block;
comparing the respective temperatures of the multiple areas of the memory block with a temperature threshold associated with the memory block;
determining a number of areas of the memory block having a respective temperature that exceeds the temperature threshold; and
altering, based on the number of areas of the memory block having a respective temperature that exceeds the temperature threshold, the frequency of the clock signal by which the memory block operates to change power consumption of the memory block.

US Pat. No. 10,924,300

VIRTUAL CONTROLLER AREA NETWORK

Marvell Asia Pte, Ltd., ...

1. A virtual controller area network system, comprising:a plurality of electronic control units (ECU) nodes, wherein each of the plurality of ECU nodes employ a shared message identification format for use by the plurality of ECU nodes to identify messages transferred among ECUs that are disposed on a same controller area network (CAN);
a plurality of physical CAN buses, wherein a respective CAN bus identifier is assigned to the plurality of physical CAN buses and wherein a first CAN bus identifier identifies two or more different physical CAN buses, among the plurality of physical CAN buses, that are designated as members of a same virtual CAN system;
two or more CAN controllers respectively coupled to subsets of the plurality of physical CAN buses, wherein a first subset of physical CAN buses is coupled to first and second CAN controllers to define a first virtual CAN and a second subset of CAN buses is coupled to at least one of the CAN controllers to define a second virtual CAN that is different from the first virtual CAN; and
an Ethernet backbone connecting at least to the two or more CAN controllers, the Ethernet backbone configured to generate an Ethernet frame containing: (i) a CAN message and (ii) a message ID for the CAN message, the Ethernet backbone being further configured to broadcast the Ethernet frame among ECU nodes coupled to the physical CAN buses in the first virtual CAN, without broadcasting the frame among ECU nodes coupled to different physical CAN buses in the second virtual CAN, based on the CAN bus identifier to identify the virtual CAN in which to broadcast the message.

US Pat. No. 10,916,270

TWO DIMENSIONAL MAGNETIC RECORDING (TDMR) OFF-TRACK PERFORMANCE IMPROVEMENT

MARVELL ASIA PTE, LTD., ...

1. A two-dimensional magnetic recording (TDMR) system including a first read head and a second read head, each of the first read head and the second read head being configured to read data from one or more tracks of a magnetic medium, the TDMR system comprising:a first finite impulse response (FIR) filter configured to process data read from one of the one or more tracks of the magnetic medium by the first read head using first filter tap values, wherein the first filter tap values are determined a priori independently of the second read head and based on the first read head being positioned on one of the one or more tracks of the magnetic medium;
a second FIR filter configured to process data read from one of the one or more tracks of the magnetic medium by the second read head using second filter tap values, wherein the second filter tap values are determined a priori independently of the first read head and based on the second read head being positioned on one of the one or more tracks of the magnetic medium; and
a read channel module configured to generate an output based on outputs of the first and second FIR filters.

US Pat. No. 10,911,037

SYSTEMS AND METHODS FOR PHASE SYNCHRONIZATION OF LOCAL OSCILLATOR PATHS IN OSCILLATOR-OPERATED CIRCUITS

Marvell Asia Pte, Ltd., ...

1. A system for phase synchronization in local oscillator paths, the system comprising:a transceiver comprising a plurality of circuits, the transceiver being configured to concurrently transmit or receive a plurality of signals;
wherein each circuit includes:
an oscillator configured to generate an oscillator clock signal;
a counter configured to generate a counter output signal in response to the oscillator clock signal controlling the counter; and
a plurality of phase-locked loop circuits coupled to the counter, each of the plurality of phase-locked loop circuits being configured to receive the counter output signal as a synchronization clock for the plurality of phase-locked loop circuits and to generate a respective output signal having rising edges aligned according to the counter output signal;
the transceiver further comprising:
a reset component coupled to the plurality of circuits, wherein the reset component is configured to send a same reset signal to the counter to synchronize a respective phase of the oscillator clock of each of the plurality of signals based on the respective counter output signal, wherein a counter time stamp captured in the respective counter output signal is independent of a reset of the plurality of phase-locked loop circuits.

US Pat. No. 10,901,018

SYSTEM AND METHOD FOR DROOP DETECTION

Marvell Asia Pte, Ltd., ...

1. A system comprising:a first plurality of inverters configured to receive an input clock signal, wherein the inverters of the first plurality of inverters are coupled in series to one another, and wherein each inverter is configured to receive an input signal and output an inverted and delayed version of the input signal;
a plurality of flipflops, wherein each flipflop of the first plurality of flipflops is coupled to respective output of inverter of the first plurality of inverters;
a second plurality of inverters, wherein the second plurality of inverters is coupled to output of every other flipflop of the plurality of flipflops;
an edge transition detector coupled to the plurality of flip-flops, wherein the edge transition detector is configured to detect the input clock signal transitioning from one value to another value through the first plurality of inverters;
a circuitry configured to determine a number of inverters of the first plurality of inverters wherein the input clock signal propagates through the number of inverters prior to the input clock signal transitioning; and
a processor configured to determine whether a droop event has occurred based on the number of inverters.

US Pat. No. 10,892,087

ON-CHIP INDUCTORS

MARVELL ASIA PTE, LTD., ...

1. An integrated circuit (IC) chip with an on-chip transformer, comprising:a primary inductor configured to have a first-primary coil portion formed of a first patterned metal trace disposed in a first metal layer and a second-primary coil portion formed of a second patterned metal trace disposed in a second metal layer;
a secondary inductor configured to have a first-secondary coil portion formed of a third patterned metal trace that interleaves with the first patterned metal trace in the first metal layer and a second-secondary coil portion formed of a fourth patterned metal trace that interleaves with the second patterned metal trace in the second metal layer;
a first via structure directly contacting the first-primary coil portion formed of the first patterned metal trace in the first metal layer and the second-primary coil portion formed of the second patterned metal trace in the second metal layer; and
a second via structure directly contacting the first-secondary coil portion formed of the third patterned metal trace in the first metal layer and the second-secondary coil portion formed of the fourth patterned metal trace in the second metal layer.

US Pat. No. 10,880,991

APPARATUS AND METHODS FOR ENHANCING SIGNALING BANDWIDTH IN AN INTEGRATED CIRCUIT PACKAGE

Marvell Asia Pte, Ltd., ...

1. An electronic device having an integrated circuit disposed in a surface mount package, comprising:a first pin of the integrated circuit configured to couple the integrated circuit to a first terminal disposed on a circuit board, the first pin defining a first connector of a first differential connector pair in the surface mount integrated circuit package for transferring differential signals from the integrated circuit to the circuit board;
a second pin of the integrated circuit configured to couple the integrated circuit to a second terminal disposed on the circuit board, the second pin defining a second connector of the first differential connector pair in the surface mount integrated circuit package, wherein the second pin is disposed adjacent to the first pin; and
an isolation stud disposed between respective distal ends of the first pin and the second pin, relative to the integrated circuit, the isolation stud being disconnected from the integrated circuit and configured to enlarge a gap between the first pin and the second pin relative to respective gaps of other pins coupling the electronic device to the circuit board.

US Pat. No. 10,872,173

SECURE LOW-LATENCY CHIP-TO-CHIP COMMUNICATION

Marvell Asia Pte, Ltd., ...

1. A circuit, comprising:a first processor block configured to transform initial data into encrypted data using a cipher, the first processor block including:
a first registry configured to store a first key and a first set of parameters;
a first crypto circuit configured to generate a cipher digit stream from the first key and the first set of parameters, the first crypto circuit including a plurality of stages, each stage generating a subset of the cipher digit stream at a distinct clock cycle; and
an encryption circuit configured to generate the encrypted data by applying the cipher digit stream to the initial data;
a second processor block configured to transform the encrypted data into decrypted data, the decrypted data corresponding to the initial data, the second processor block including:
a second registry configured to store a second key and a second set of parameters;
a second crypto circuit configured to generate the cipher digit stream from the second key and the second set of parameters;
a decryption circuit configured to generate the decrypted data by applying the cipher digit stream to the encrypted data; and
a bus connecting the first processor block and the second processor block, the first processor block being configured to forward the encrypted data to the second processor block via the bus.

US Pat. No. 10,840,892

FULLY DIGITAL, STATIC, TRUE SINGLE-PHASE CLOCK (TSPC) FLIP-FLOP

MARVELL ASIA PTE, LTD., ...

1. A flip-flop comprising:a primary latch; and
a secondary latch connected to the primary latch, wherein the primary latch and the secondary latch each comprise a multi-stage input driver and wherein each multi-stage input driver comprises:
a control stage comprising:
multiple transistors connected in series; and
a control node at a junction between two transistors of the multiple transistors, wherein gates of the two transistors receive an input signal and a clock signal, respectively, such that logic states of first and second control signals at the control nodes of the primary and secondary latches, respectively, depend on the respective input signal and the clock signal; and
a storage stage comprising:
two additional transistors directly connected in series; and
a storage node at a junction between the two additional transistors,
wherein a gate of one of the two additional transistors of the storage stage of the secondary latch receives the second control signal such that a logic state of a stored bit signal at the storage node of the secondary latch depends on the second control signal; and
wherein gates of the two additional transistors of the storage stage of the primary latch receive the first control signal such that a logic state of a stored bit signal at the storage node of the primary latch depends on the first control signal.

US Pat. No. 10,832,716

ZONE SELF SERVO WRITING WITH SYNCHRONIZED PARALLEL CLOCKS

MARVELL ASIA PTE, LTD., ...

1. A storage device comprising:a first phase lock loop (PLL) and a second PLL in parallel,
the first PLL configured to receive a reference clock input and a first input and configured to output a first clock signal;
the second PLL configured to receive the reference clock input and a second input and configured to output a second clock signal;
a synchronization logic connected to output a first frequency multiplier and a frequency offset as the first input to the first PLL and connected to output a second frequency multiplier and the frequency offset as the second input to the second PLL, wherein the synchronization logic is configured to synchronize output to the first PLL with output to the second PLL; and
a controller configured with program code executable by the controller to cause the storage device to write concentric servo tracks on a machine-readable medium at successively increasing clock frequencies while using the second clock signal for position feedback.

US Pat. No. 10,834,674

TRAINING SEQUENCES FOR HIGH EFFICIENCY WIRELESS LOCAL AREA NETWORKS

Marvell Asia Pte., Ltd., ...

1. A method for communicating in a high efficiency (HE) wireless local area network (WLAN), the method comprising:determining that a transmission mode of a transmitting device for transmitting a long training field (LTF) sequence is an orthogonal frequency division multiple access (OFDMA) mode;
in response to the determination that the transmission mode is the OFDMA mode, performing each of
(i) determining a target resource unit (RU) sequence for a smallest RU for the OFDMA mode,
(ii) selecting, from a plurality of candidate training sequences and in accordance with a desired peak-to-average power ratio (PAPR) value, a target training sequence for the LTF sequence, wherein the plurality of candidate training sequences is based at least in part on the target RU sequence, wherein each of the candidate training sequences includes a first number of base sequences and a second number of floating sequences, and wherein the first number of base sequences and the second number of floating sequences are determined based on a transmission bandwidth and a tone spacing, and
(iii) masking the target training sequence by muting specified tones of the target training sequence, wherein muting the specified tones includes transmitting null tones in locations of the specified tones;
assigning the masked target training sequence to the transmitting device to be transmitted in the LTF; and
transmitting the LTF including the masked target training sequence.

US Pat. No. 10,827,428

SYSTEMS AND METHODS FOR MANAGING BASIC SERVICE SETS THROUGH WAKEUP FRAMES IN A LOW POWER WIRELESS NETWORK

Marvell Asia Pte, Ltd., ...

1. A method for transmitting a wake-up request frame to low power devices to announce a management frame of basic service set (BSS) information in a wireless local area network, the method comprising:receiving, at a wireless access point, data including BSS operation information for transmission in a management frame to one or more lower power wireless devices;
determining whether the BSS operation information includes an update;
in response to determining that the BSS operation information includes an update:
generating a wake-up request frame containing at least one field indicative of the BSS operation information update based on a type of the management frame, and
transmitting the wake-up request frame to the one or more lower power wireless devices to turn on respective one or more wireless receivers at the one or more low power wireless devices prior to transmitting the BSS operation information in a management frame to the one or more lower power wireless devices.

US Pat. No. 10,797,728

SYSTEMS AND METHODS FOR DIVERSITY BIT-FLIPPING DECODING OF LOW-DENSITY PARITY-CHECK CODES

Marvell Asia Pte, Ltd., ...

1. A method for decoding an LDPC codeword, the method comprising:performing, using a processing circuitry comprising at least one decoder, a first iteration of decoding the LDPC codeword using a first decoding technique comprising first instructions to produce a first decoding output;
determining, whether the LDPC codeword has been decoded;
in response to determining that the LDPC codeword has not been decoded:
calculating a first syndrome weight of the first decoding output;
computing a difference between the first syndrome weight of the first decoding output and an original syndrome weight of the LDPC codeword;
comparing the computed difference between the first syndrome weight and the original syndrome weight to a threshold syndrome weight;
in response to determining that the computed difference between the first syndrome weight and the original syndrome weight is greater than the threshold syndrome weight:
decoding, using the processing circuitry, the LDPC codeword using a second decoding technique, comprising second instructions different from the first instructions of the first decoding technique, to produce a second decoding output;
in response to determining that the computed difference between the first syndrome weight and the original syndrome weight is less than the threshold syndrome weight:
performing a second iteration of decoding the LDPC codeword using the first decoding technique.

US Pat. No. 10,784,167

ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMICONDUCTOR SUBSTRATES

MARVELL ASIA PTE, LTD., ...

1. An apparatus comprising:a substrate having a surface that includes a planar portion and a fin feature that extends from the surface of the substrate in a direction that is perpendicular to the planar portion of the surface;
a dielectric layer formed over the planar portion of the surface of the substrate that extends outward from the fin feature of the substrate;
a first region of polycrystalline silicon formed over a first portion of the fin feature of the substrate;
a second region of polycrystalline silicon formed over a second portion of the fin feature of the substrate;
a gap formed through the fin feature, the gap formed between the first region of polycrystalline silicon and the second region of polycrystalline silicon;
a first spacer region formed between the first region of polycrystalline silicon and the gap formed through the fin feature, the first spacer region formed of a first dielectric material and over the fin feature, a bottom surface of the first spacer region formed over the fin feature and having a portion that is coplanar with a top surface the dielectric layer;
a second spacer region formed between the second region of polycrystalline silicon and the gap formed through the fin feature, the second spacer region formed of the first dielectric material and over the fin feature, a bottom surface of the second spacer region formed over the fin feature and having a portion that is coplanar with the top surface of the dielectric layer; and
an isolation component formed in the gap formed through the fin feature and between the first spacer region and the second spacer region, wherein:
the isolation component is formed from one or more other dielectric materials that fill (i) the gap formed through the fin feature of the substrate and (ii) a volume of space between the first spacer region and the second spacer region,
the isolation component is formed adjacent to at least one of the first spacer region or the second spacer region without another component being disposed between the isolation component and the at least one of the first spacer region or the second spacer region, and
the one or more dielectric materials of the isolation component comprise at least a second dielectric material having a dielectric constant that is less than a dielectric constant of the dielectric layer formed over the planar portion of the surface of the substrate.

US Pat. No. 10,782,896

LOCAL INSTRUCTION ORDERING BASED ON MEMORY DOMAINS

Marvell Asia Pte, Ltd., ...

1. A method for managing an observed order of instructions in a computing system, the method comprising:executing a plurality of instructions at a first plurality of processing elements in the computing system, the executing including
issuing at least a first instruction of the plurality of instructions at a first processing element, the first instruction being configured to access memory associated with a second plurality of processing elements in the computing system; and
issuing a second instruction of the plurality of instructions at the first processing element, the second instruction causing the first processing element to pause issuance of further instructions for accessing memory in a first memory domain of a plurality of memory domains in the computing system until the first processing element receives one or more first acknowledgements that at least the first instruction of the plurality of instructions has reached a first location in circuitry of the first plurality of processing elements;
wherein the second instruction is specified as being associated with the first memory domain of the plurality of memory domains in the computing system; and
wherein the first processing element receives a second acknowledgement that at least the first instruction of the plurality of instructions has reached a second location in circuitry of the second plurality of processing elements.