US Pat. No. 9,510,414

LIGHT EMITTING DIODE DRIVING CIRCUIT AND LIGHTING APPARATUS HAVING THE SAME

Magnachip Semiconductor, ...

1. A light emitting diode (LED) driving circuit comprising:
a flicker elimination unit configured to perform a flicker removal for LED modules; and
a driving control unit configured to pause the flicker removal in response to receiving an AC input voltage through a Triode
for Alternating Current (TRIAC) dimmer.

US Pat. No. 9,357,611

LIGHT EMITTING DIODE DRIVER APPARATUS

Magnachip Semiconductor, ...

1. A light emitting diode (LED) driver apparatus, comprising:
a pulse-width modulation (PWM) signal generator configured to generate a PWM signal according to a reference voltage;
a DC-DC converter configured to provide a driving voltage to LED arrays based on the generated PWM signal;
a LED driver configured to drive the LED arrays through output ports; and
a detector configured to detect whether the LED arrays are operatively connected to the corresponding output ports based on
respective voltages of the output ports being different from a preset amount of voltage.

US Pat. No. 9,111,959

SEMICONDUCTOR DEVICE AND MANUFACTURE METHOD THEREOF

MagnaChip Semiconductor, ...

1. A semiconductor device, comprising:
a well region disposed in a substrate;
a gate disposed on the substrate;
a halo region disposed in a channel region under the gate; and
a source LDD region and a drain LDD region disposed on opposite sides of the halo region,
wherein the halo region is spaced apart from the source LDD region and the drain LDD region, and is disposed substantially
at a center of the channel region under the gate.

US Pat. No. 9,502,555

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

Magnachip Semiconductor, ...

1. A semiconductor device comprising:
a substrate comprising a trench;
a first electrode disposed on a bottom of the trench;
a second electrode disposed on the first electrode, a first insulating layer being disposed between the first electrode and
the second electrode;

a first contact arranged to contact with an extension of the first electrode; and
a second contact arranged to contact with an extension of the second electrode,
wherein the extension of the first electrode extends in a first direction of the substrate, and the extension of the second
electrode extends in a second direction of the substrate, the second direction being perpendicular to the first direction.

US Pat. No. 9,532,432

LED DRIVER APPARATUS

Magnachip Semiconductor, ...

1. A light emitting diode (LED) driver apparatus, comprising:
a pulse width modulation (PWM) signal generation unit configured to generate a PWM signal using an oscillator having a preset
frequency;

a direct current (DC)-DC converter configured to provide a driving voltage to an LED array using the generated PWM signal;
an LED driving unit configured to drive the LED array using a dimming signal; and
a synchronization unit configured to reset a clock signal of the oscillator by synchronizing the oscillator to restart at
a point in which a feedback voltage of the LED array is equal to or less than a preset first reference voltage.

US Pat. No. 9,106,127

CHARGE PUMP APPARATUS AND CHARGE PUMPING METHOD

MagnaChip Semiconductor, ...

1. A charge pump circuit, comprising:
a plurality of capacitors configured to perform a charge pumping operation to generate a boosted voltage by boosting an input
voltage in accordance with a boosting mode;

a switch controller configured to generate one or more switch control signals according to boosting mode information, the
generated switch control signals being configured according to the boosting mode information to provide an initialization
period during which a voltage level charged in one or more of the plurality of capacitors is changed according to a new boosting
mode, the initialization period being provided prior to generation of a new boosted voltage by boosting the input voltage
in accordance with the new boosting mode, the new boosting mode corresponding to a change in the boosting mode information
occurring during the charge pumping operation; and

a plurality of switches configured to control the plurality of capacitors according to the generated switch control signals.

US Pat. No. 9,603,220

LED DRIVER APPARATUS

Magnachip Semiconductor, ...

1. A light-emitting diode (LED) driver apparatus comprising:
a comparison voltage generating unit configured to
measure a feedback voltage of an LED array,
generate a first target voltage and a second target voltage;
selectively output, to a comparator, the measured feedback voltage or, in response to generation of a signal to stop a boosting
operation of a DC-DC converter, the second target voltage, wherein the comparator is configured to compare the first target
voltage with the selectively output measured feedback voltage or second target voltage to obtain a comparison voltage; and

supply the comparison voltage to a pulse width modulation (PWM) signal generating unit,
wherein the generation of signal to stop a boosting operation of the DC-DC converter begins in response to receiving an indication
that a driving voltage for the LED array is higher than or equal to a first reference voltage, and ends in response to the
measured feedback voltage being less than or equal to the second target voltage.

US Pat. No. 9,135,870

SOURCE DRIVER, CONTROLLER, AND METHOD FOR DRIVING SOURCE DRIVER

Magnachip Semiconductor L...

1. A source driver, comprising:
a controller configured to:
receive a start pulse signal, and
generate and output an internal start pulse signal in response to the start pulse signal not being received;
a shift register configured to:
receive video data,
store the video data, and
output the video data in response to the outputted start pulse signal being received by the shift register;
a digital-to-analog converter (DAC) configured to:
convert the video data output from the shift register into an analog voltage signal, and
output the analog voltage signal; and
an output buffer configured to:
buffer the analog voltage signal output from the DAC, and
output the buffered analog voltage signal.

US Pat. No. 9,472,614

SUPER JUNCTION SEMICONDUCTOR DEVICE

Magnachip Semiconductor, ...

1. A super junction semiconductor device comprising:
a cell area and a junction termination area disposed on a substrate; and
a transition area disposed between the cell area and the junction termination area,
wherein the cell area, the junction termination area, and the transition area each include at least one unit cell, the unit
cell comprising a N-type pillar region and adjacent to a P-type pillar region,

wherein the unit cells are disposed adjacent to each other such that the corresponding N-type pillar regions and the P-type
pillar regions alternate through the cell area, the junction termination area and the transition area, and

wherein an average width of a unit cell in the transition area is smaller than an average width of a unit cell in the cell
area and the junction termination area.

US Pat. No. 9,173,260

PWM SIGNAL GENERATING CIRCUIT FOR DC-DC CONVERTER USING DIMMING SIGNAL AND LED DRIVER CIRCUIT USING THE SAME IN DIGITAL PWM METHOD HAVING FIXED PHASE MODE

MAGNACHIP SEMICONDUCTOR, ...

14. A method of generating a pulse-width modulation (PWM) signal for a direct current to direct current (DC-DC) converter
based on a dimming signal, the method comprising:
generating a dimming signal;
generating a synchronized dimming signal by synchronizing the dimming signal to a clock signal; and
generating the PWM signal having a rising edge in response to the clock signal having a falling edge while the synchronized
dimming signal is on.

US Pat. No. 9,105,605

SEMICONDUCTOR DEVICE

MagnaChip Semiconductor, ...

1. A semiconductor device, comprising:
a plurality of trench transistors in an active region; and
an interconnection disposed in an edge region,
wherein the interconnection is configured to transfer a voltage to the plurality of trench transistors;
the edge region comprises a substrate, a first insulating layer, a first electrode, a second insulating layer, and a second
electrode, disposed in that order; and

the edge region further comprises a LOCOS layer disposed between the substrate and the first electrode.

US Pat. No. 9,425,690

CURRENT CONTROLLING MODE DIRECT CURRENT (DC)-DC CONVERTER

Magnachip Semiconductor, ...

1. A direct current (DC)-DC converter, comprising:
a first comparator configured to receive a first input voltage and a second input voltage and to output a first output signal;
a second comparator configured to receive a reference voltage configured to indicate mode switching and the second input voltage
and to output a second output signal, wherein the second input voltage is based on a sensing signal and a ramp signal; and

a first logic element configured to output a reset signal based upon a determination that both the first output signal and
the second output signal are applied to the first logic element, wherein the reset signal is configured to turn off a gate.

US Pat. No. 9,111,994

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

MAGNACHIP SEMICONDUCTOR, ...

1. A method of fabricating a semiconductor device, the method comprising:
forming a multi-depth trench in a semiconductor substrate, the forming of the multi-depth trench comprising:
forming a shallow trench; and
forming a deep trench arranged below the shallow trench;
depositing a first dielectric material into a partial area of the multi-depth trench comprising the shallow trench and the
deep trench, the deposited first dielectric material forming a slope in the shallow trench that extends upward from a corner
where a horizontal bottom surface of the shallow trench and a vertical sidewall of the deep trench meets, the slope being
inclined with respect to the horizontal bottom surface of the shallow trench; and

depositing a second dielectric material into areas of the multi-depth trench in which the first dielectric material is absent.

US Pat. No. 9,438,121

POWER CONVERTER FOR REDUCING STANDBY POWER CONSUMPTION

Magnachip Semiconductor, ...

1. A power converter, comprising:
a rectifier configured to rectify AC power into DC power;
a transformer configured to output power by converting a voltage of DC power rectified by the rectifier;
a Pulse Width Modulation (PWM) control module configured to control an output power by switching a power switching device
connected to the transformer;

a first external switch configured to provide a disable signal, with one side of the first external switch connected to a
VCC pin of the PWM control module and the other side of the first external switch connected to a DIS pin of the PWM control
module;

a first capacitor that is connected in parallel to the one side of the first external switch and to a ground; a second external
switch configured to provide an enable signal, with one side of the second external switch connected to the DIS pin of the
PWM control module and the other side of the second external switch connected to the ground; and a second capacitor that is
connected in parallel to the one side of the second external switch and to the ground.

US Pat. No. 9,117,412

MEMORY DEVICE WITH ONE-TIME PROGRAMMABLE FUNCTION, AND DISPLAY DRIVER IC AND DISPLAY DEVICE WITH THE SAME

Magnachip Semiconductor, ...

1. A display driver integrated chip (IC) comprising:
a built-in internal voltage generating unit configured to receive an external voltage to generate an internal voltage;
a built-in memory device having a one-time programmable function, wherein the memory device is connected to the internal voltage
generating unit through a built-in first internal interconnection for receiving the internal voltage generated from the internal
voltage generating unit as a writing voltage to operate upon writing operation; and

a built-in first pad connected to the internal voltage generating unit and configured to output the internal voltage of the
internal voltage generating unit,

wherein the built-in internal voltage generating unit, the built-in memory device, the built-in first internal interconnection,
and the built-in first pad exist within the display driver IC.

US Pat. No. 9,332,649

FLEXIBLE PRINTED CIRCUIT BOARD FOR PACKAGING SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME

Magnachip Semiconductor, ...

1. A flexible circuit board, comprising:
a base film;
a plurality of input line patterns, a plurality of output line patterns, and a plurality of dummy patterns on a first surface
of the base film; and

a ground pattern on a second surface of the base film and electrically connected with one of the plurality of dummy patterns,
wherein the plurality of dummy patterns are formed between each of the plurality of input line patterns or between each of
the plurality of output line patterns.

US Pat. No. 9,431,309

METHOD FOR WAFER LEVEL RELIABILITY

Magnachip Semiconductor, ...

1. A method for ensuring wafer level reliability, the method comprising:
forming a gate oxide layer having a thickness of less than 50 Å on a semiconductor substrate;
forming a PMOS element having a channel length of less than 0.13 ?m on the semiconductor substrate;
forming a high voltage NMOS element on a semiconductor substrate;
assessing substrate hot carrier injection (sub-HCI) for the high voltage NMOS element; and
assessing hot carrier injection (HCI) for the PMOS element.

US Pat. No. 9,578,766

COVER OPENING DETECTION USING HALL SENSOR

Magnachip Semiconductor, ...

1. A display terminal comprising:
a first body having a front surface and a back surface;
a second body coupled to the first body via a joint, the second body being configured to substantially reach the back surface
of the first body when the second body is opened; and,

a Hall sensor disposed in the first body, the Hall sensor comprising a magnetic field sensing surface and being configured
to directly sense a magnetic field generated by a magnet disposed in the second body,

wherein the magnetic field substantially vertically passes the magnetic field sensing surface of the Hall sensor;
wherein the magnetic field sensing surface is disposed at a slope with respect to the front surface of the first body;
wherein an angle of opening between the second body and the front surface of the first body ranges between approximately 0
degree and approximately 360 degrees;

wherein the Hall sensor comprises a Hall element disposed on a semiconductor substrate;
wherein the Hall element is configured to sense a first magnetic field in response to the second body covering the front surface
of the first body, and a second magnetic field in response to the second body reaching the back surface of the first body;
and

wherein a direction of the first sensed magnetic field is substantially opposite to a direction of the second sensed magnetic
field.

US Pat. No. 9,490,692

CIRCUIT AND METHOD OF CORRECTING A POWER FACTOR FOR AC DIRECT LIGHTING APPARATUS

MagnaChip Semiconductor, ...

1. A power factor correcting circuit for an AC direct lighting apparatus, the circuit comprising:
a valley signal generating unit that receives a full-wave rectified AC input voltage signal, and compares an internal reference
voltage signal and the AC input voltage signal to generate a valley signal;

a reference voltage control unit that receives the valley signal, counts clock cycles of a clock signal to detect a frequency
of the AC input voltage signal, and determines a frequency of a drive current to control a reference voltage signal based
on the frequency of the drive current; and

a reference voltage control clock generating unit that generates a pulse width modulation (PWM) signal associated with a pulse
width of the reference voltage signal, and generates a reference voltage control clock signal based on the PWM signal and
the reference voltage signal.

US Pat. No. 9,502,257

NON-VOLATILE MEMORY DEVICE HAVING ASYMMETRICAL CONTROL GATES SURROUNDING A FLOATING GATE AND MANUFACTURING METHOD THEREOF

Magnachip Semiconductor, ...

1. A non-volatile memory device, the device comprising:
a floating gate insulating layer disposed on a substrate;
a floating gate insulated from the substrate by the floating gate insulating layer;
a first dielectric region formed perpendicular to the floating gate insulating layer on a first sidewall of the floating gate;
a second dielectric region formed perpendicular to the floating gate insulating layer on a second sidewall of the floating
gate;

a first control gate at a side of the first dielectric region on the first sidewall of the floating gate distal from the floating
gate; and

a second control gate at a side of the second dielectric region on the second sidewall of the floating gate distal from the
floating gate,

wherein the first control gate and the second control gate are in contact with each other, a second width of the second control
gate is wider than a first width of the first control gate, and the first width extends perpendicularly from the side of the
first dielectric region in a direction that is opposite to a direction in which the second width extends from the side of
the second dielectric region and is parallel to a direction of a channel.

US Pat. No. 9,401,401

SEMICONDUCTOR DEVICE

Magnachip Semiconductor, ...

1. A semiconductor device comprising:
a source region disposed apart from a drain region;
a first body region surrounding the source region;
a deep well region disposed below the drain region;
a buried region having conductivity opposite that of the deep well region formed within the deep well region; and
a second body region disposed below the first body region,
wherein a bottom surface of the second body region forms a discontinuous step with a bottom surface of the deep well region
such that deep well region is deeper than the second body region,

wherein the first body region has a different conductivity type from the second body region, and
wherein at least one dip is disposed at the bottom surface of the second body region.

US Pat. No. 9,105,721

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

MAGNACHIP SEMICONDUCTOR, ...

1. A semiconductor device, comprising:
a substrate;
a first well region formed by being doped in a first location on a surface of the substrate;
a second well region formed by being doped in a different type from the first well region in a second location on a surface
of the substrate;

an overlapping region between the first well region and the second well region where the first well region and the second
well region substantially coexist;

a gate insulating layer formed on a surface of the first and the second well regions and on a surface of the overlapping region;
a gate electrode formed on the insulating layer;
a source region formed on an upper portion of the first well region; and
a drain region formed on an upper portion of the second well region,
wherein a net doping concentration in the overlapping region gradually decreases from a boundary between the first well region
and the overlapping region to a boundary between the second well region and the overlapping region, and a ratio of a length
of the first well region overlapping the gate electrode to a length of the gate electrode ranges between 80% and 96%.

US Pat. No. 9,642,197

CIRCUIT FOR COMPENSATING BIPOLAR JUNCTION TRANSISTOR BASE CURRENT AND LED DRIVING APPARATUS HAVING THE SAME

Magnachip Semiconductor, ...

1. A circuit for compensating a bipolar junction transistor (BJT) base current, the circuit comprising:
a mirror element configured to mirror the BJT base current; and
an amplifier comprising a first p-type metal-oxide-semiconductor (PMOS) transistor being directly connected to a base of the
BJT, the first PMOS transistor being directly coupled to the mirror element to induce a mirror current into the mirror element,

wherein the mirror element is a second PMOS transistor.

US Pat. No. 9,419,206

MAGNETIC SENSOR AND METHOD OF FABRICATING THE SAME

MagnaChip Semiconductor, ...

1. A magnetic sensor, comprising:
hall elements disposed in a substrate;
a protection layer disposed above the hall elements;
a seed layer disposed above the protection layer and hall elements; and
an integrated magnetic concentrator (IMC) disposed above the seed layer, wherein
the seed layer has an elevated portion that protrudes from an upper surface of the seed layer in a direction substantially
normal to an upper surface of the substrate, and

the IMC has an elevated portion that protrudes from an upper surface of the IMC in the direction substantially normal to the
upper surface of the substrate.

US Pat. No. 9,099,300

INSULATOR, CAPACITOR WITH THE SAME AND FABRICATION METHOD THEREOF, AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Magnachip Semiconductor, ...

1. An insulator, comprising:
a laminate structure in which two or more aluminum oxide (Al2O3) layers and two or more hafnium oxide (HfO2) layers are laminated alternately in an iterative manner and a bottom layer and a top layer are formed of the same material,
the two or more hafnium oxide (HfO2) layers not crystallized, and the aluminum oxide (Al2O3) layers in the laminate structure each having the same thickness, the total thickness of the aluminum oxide (Al2O3) layers being smaller than the total thickness of the hafnium oxide (HfO2) layers in the laminate structure,

wherein an upper surface of the bottom layer has a greater surface area than an upper surface of the top layer such that a
portion of the bottom layer extends outside the top layer;

an upper surface of at least one layer of the two or more aluminum oxide (Al2O3) layers and the two or more hafnium oxide (HfO2) layers has a substantially equal surface area as the upper surface of the top layer; and

an upper surface of at least one other layer of the two or more aluminum oxide (Al2O3) layers and the two or more hafnium oxide (HfO2) layers has a substantially equal surface area as the upper surface of the bottom layer, such that a portion of the laminate
structure disposed on the bottom layer outside the top layer has a thickness that is less than a portion of the laminate structure
covered with the top layer.

US Pat. No. 9,609,705

SWITCHING CONTROL CIRCUIT, LIGHT APPARATUS COMPRISING THE SAME AND SWITCHING CONTROL METHOD

MagnaChip Semiconductor, ...

1. A switching control circuit, comprising:
a switching trigger unit that receives a sensing voltage representing a driving current during a first driving current section
and a second driving current section, wherein the switching trigger unit provides a first switching trigger signal based on
the sensing voltage in the second driving current section;

an off-time control unit that provides a second switching trigger signal in the first driving current section to control a
maximum off-time of a driving switching element; and

a switching control unit that turns on the driving switching element based on the first switching trigger signal or the second
switching trigger signal.

US Pat. No. 9,521,719

CIRCUIT FOR DRIVING LIGHTING APPARATUS AND METHOD THEREOF

MagnaChip Semiconductor, ...

1. A circuit for driving a lighting apparatus, comprising:
a valley signal generator configured to generate a valley signal based on an input voltage;
an input voltage determining unit configured to determine whether the input voltage corresponds to a direct current (DC) voltage
or a full-wave rectified AC voltage based on the valley signal;

an AC voltage simulation unit configured to generate a virtual valley signal when the input voltage is a DC voltage; and
a switching device controller configured to control a switching device used to drive an LED module based on a result of the
determination by the input voltage determining unit and at least one of the valley signal and the virtual valley signal.

US Pat. No. 9,099,557

SEMICONDUCTOR DEVICE

MAGNACHIP SEMICONDUCTOR, ...

1. A semiconductor device, comprising:
a well region formed in a substrate;
a gate electrode formed over the well region;
a first body region having a channel region formed in the well region and having an opposite conductive type to the well region
and partially overlapping the gate electrode;

a second body region having a channel extension region formed in the well region and being spaced apart from the first body
region and having an opposite conductive type to the well region and fully overlapping the gate electrode,

wherein the well region comprises a first region and a second region,
wherein the first region and the second region are spaced apart from each other and overlap the gate electrode,
wherein the second body region is disposed between the first region and the second region.

US Pat. No. 9,094,003

BUFFERING CIRCUIT, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHODS THEREOF

Magnachip Semiconductor L...

1. A semiconductor device, comprising:
a data buffering unit configured to:
receive input data comprising (N*M) number of bits, wherein:
N represents an even-number from among integers greater than 0, and
M represents an integer greater than 0; and
buffer the input data into:
even-number data in a serial form, the even-number data comprising {(N/2)*M} bits, corresponding to a positive clock; and
odd-number data in a serial form, the odd-number data comprising {(N/2)*M} bits, corresponding to a negative clock; and
a serial/parallel conversion unit configured to generate N output data in a parallel form as the even-number and odd-number
data are received and converted into a parallel form by N bits, the even-number and odd-number data each comprising M bits
in a serial form, respectively.

US Pat. No. 9,496,135

EPITAXIAL SILICON WAFER AND METHOD FOR FABRICATING THE SAME

Magnachip Semiconductor, ...

1. An epitaxial silicon wafer comprising:
a doped bulk wafer;
a first inter-layer formed directly on the doped bulk wafer;
a first epitaxial layer formed directly on the first inter-layer, the first epitaxial layer having a doping concentration
higher than that of the doped bulk wafer;

a second inter-layer formed directly on the first epitaxial layer; and
a second epitaxial layer formed directly on the second inter-layer, and the second epitaxial layer having a doping concentration
less than that of the first epitaxial layer,

wherein the bulk wafer, the first inter-layer, the first epitaxial layer, the second inter-layer, and the second epitaxial
layer have a same conductivity type,

wherein both the first inter-layer and the second inter-layer have a different concentration from the first epitaxial layer
and the second epitaxial layer, and

wherein both the first inter-layer and the second inter-layer have a concentration higher than that of the doped bulk wafer.

US Pat. No. 9,577,055

SEMICONDUCTOR DEVICE HAVING A MINIMIZED REGION OF SHEILD ELECTRODE AND GATE ELECTRODE OVERLAP

Magnachip Semiconductor, ...

1. A semiconductor device comprising:
a substrate that comprises a trench;
a first insulating film that is formed at a bottom and a side wall of the trench;
a first electrode that is arranged at a bottom region of the trench;
a second insulating film, formed on the first electrode, comprising a groove, wherein a part of the first electrode is exposed
by the groove, and the second insulating film does not extend to at least a portion of the side of the part of the first electrode
that is exposed by the groove;

a second electrode, formed on the second insulating film, also comprising the groove;
a first contact portion that is connected with the part of the first electrode; and
a second contact portion that is connected with the second electrode.

US Pat. No. 9,576,991

PHOTO SENSOR MODULE

Magnachip Semiconductor, ...

1. A photo sensor module comprising:
a semiconductor substrate;
a field oxide layer, disposed on the semiconductor substrate;
a photo sensor comprising a photo diode formed on the field oxide layer; and
an insulator film disposed on the field oxide layer and the photosensor;
wherein a part of the insulator film is removed and a part of the photo diode is exposed to outside.

US Pat. No. 9,263,450

OTP MEMORY CELL AND FABRICATING METHOD THEREOF

Magnachip Semiconductor, ...

1. A one-time programmable (OTP) memory cell comprising:
a well of a first conductivity type;
a gate insulating layer formed on the well and including first and second fuse regions;
a gate electrode of a second conductivity type formed on the gate insulating layer, the second conductivity type being opposite
in electric charge to the first conductivity type;

a junction region of the second conductivity type formed in the well and arranged to surround the first and second fuse regions;
and

an isolation layer formed in the well between the first fuse region and the second fuse region.

US Pat. No. 9,236,470

SEMICONDUCTOR POWER DEVICE AND METHOD OF FABRICATING THE SAME

MagnaChip Semiconductor, ...

1. A semiconductor power device comprising:
a first conductivity type semiconductor substrate;
an epitaxial layer formed on the semiconductor substrate;
a second conductivity type well formed in the semiconductor;
a drain region formed in the well;
an oxide layer that insulates a gate region from the drain region;
a first conductivity type buried layer formed in the well;
a second conductivity type drift region surrounding the buried layer along at least a lateral side and a bottom side of the
buried layer, the drift region disposed in the well; and

a second conductivity type TOP region formed between the buried layer and the oxide layer.

US Pat. No. 9,502,975

SWITCH CONTROL CIRCUIT, SWITCH CONTROL METHOD AND CONVERTER USING THE SAME

Magnachip Semiconductor, ...

1. A switch control circuit for controlling a current control switch of a power supply, the power supply comprising a load,
an inductor and the current control switch that are series-coupled to an input power, the switch control circuit comprising:
a current measuring unit configured to measure a current flowing into the load;
a current integral unit configured to integrate the measured current;
a comparison unit configured to compare the integrated current value and a reference value; and
a control unit that is coupled to the current control switch, the control unit being configured to turn off the current control
switch in response to the integrated current value being substantially same as the reference value and to turn on the current
control switch in response to a predefined off-time having elapsed from a time when the current control switch is turned off.

US Pat. No. 9,082,328

MULTI-FUNCTIONAL INTEGRATED CIRCUIT AND SOURCE DRIVER HAVING THE SAME

Magnachip Semiconductor, ...

1. An integrated circuit (IC) chip, comprising:
a first high-voltage transistor configured to pre-charge a predetermined node, in response to a first control signal;
a decoding unit configured to decode input signals, and to output a decoded signal to the node;
a second high-voltage transistor configured to transfer an output of the decoding unit to the node, in response to a second
control signal; and

a latch unit configured to latch a signal at the node,
wherein the decoding unit includes low-voltage transistors, coupled in series between a first supply voltage terminal and
the second high-voltage transistor.

US Pat. No. 9,123,769

POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Magnachip Semiconductor, ...

1. A method of fabricating a power semiconductor device, the method comprising:
forming a first epitaxial layer on a substrate;
forming a second epitaxial layer on the first epitaxial layer;
entirely removing the substrate to expose the first epitaxial layer after the second epitaxial layer is formed on the first
epitaxial layer;

grinding a rear side of the first epitaxial layer so that a partial thickness of the first epitaxial layer remains; and
forming a trench in the second epitaxial layer,
wherein the first epitaxial layer has a higher doping concentration than the second epitaxial layer.

US Pat. No. 9,070,680

CHIP ON FILM TYPE SEMICONDUCTOR PACKAGE

MagnaChip Semiconductor, ...

1. A chip on film (COF) type semiconductor package, comprising:
a film;
a plurality of leads formed on a surface of the film;
a chip adhered to ends of the leads;
an underfill layer filled within a space between the chip and the leads; and
a heat dissipation layer adhered to an other surface of the film, the heat dissipation layer comprising:
a graphite material layer comprising a graphite film that has a multi-layered structure in which a plurality of graphite thin
films is laminated;

a protection layer formed on a surface of the graphite material layer to cover the graphite material layer; and
an adhesion layer formed on an other surface of the graphite material layer to adhere the heat dissipation layer to the other
surface of the film.

US Pat. No. 9,523,744

SENSING APPARATUS USING A PLURALITY OF HALL SENSORS

Magnachip Semiconductor, ...

1. A sensing apparatus, comprising:
a first sensor unit comprising a sensor formed on a first X,Y plane; and
a second sensor unit comprising another sensor formed on a second plane,
wherein the another sensor of the second sensor unit is displaced from the first sensor in a Z axis direction, and
wherein each sensor of the first and the second sensor units is a Hall sensor comprising a Hall device which comprises;
a conductive type sensing region configured to detect a change in a magnetic field;
first and third electrodes that face each other along a first line and are configured to provide a measured current on the
sensing region; and

second and fourth electrodes that are arranged to face each other along a second line that is perpendicular to the first line
and are configured to measure a change in voltage.

US Pat. No. 9,384,854

COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) ANALOG SWITCH CIRCUIT

Magnachip Semiconductor, ...

1. A Complementary Metal-Oxide-Semiconductor (CMOS) analog switch, comprising:
a first Metal-Oxide-Semiconductor Field Effect Transistor (MOS) configured to receive a supply voltage and switch in response
to an externally-applied control signal; and

at least two voltage extractors configured to extract a drain-side and a source-side voltage of the first MOS in response
to a turning on of the first MOS, and configured to bias the extracted voltage to a substrate node of the first MOS,

wherein each of the voltage extractors comprises at least two MOS that are of the same type, and each of the voltage extractors
is connected to a gate terminal of the first MOS and either a drain terminal or a source terminal of the first MOS, and the
at least two MOS are configured to cross gate nodes and drain nodes that are connected to the gate terminal and either the
drain terminal or the source terminal of the first MOS, respectively.

US Pat. No. 9,184,304

MULTI-SOURCE JFET DEVICE

Magnachip Semiconductor, ...

1. A junction field-effect transistor (JFET) device, comprising:
a drain region;
a junction gate region surrounding the drain region; and
a plurality of source regions surrounding the junction gate region.

US Pat. No. 9,105,684

ISOLATION STRUCTURE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHOD FOR FABRICATING THE ISOLATION STRUCTURE

Magnachip Semiconductor, ...

1. A method for fabricating an isolation structure of a semiconductor device, the method comprising:
forming a deep trench by etching a substrate a plurality of times;
forming a first oxide layer along an inner side of the deep trench and then annealing the first oxide layer;
forming a second oxide layer on the first oxide layer and then annealing the second oxide layer;
filling a portion of an inside of the deep trench on the second oxide layer with a filler;
etching such that upper portions of the first and second oxide layers are recessed downward the deep trench;
etching the filler so that the filler exists on only part of the inside of the deep trench; and
forming an additional oxide layer on the first oxide layer, the second oxide layer and the filler.

US Pat. No. 9,537,387

REFERENCE SIGNAL GENERATING CIRCUIT AND METHOD USING A SAMPLED INPUT SIGNAL AND A REFERENCE CLOCK SIGNAL, AND POWER FACTOR COMPENSATION APPARATUS HAVING THE SAME

Magnachip Semiconductor, ...

1. A reference signal generating circuit for generating a reference signal based on an input signal for power factor compensation
of a power converter, the reference signal generating circuit comprising:
a detector configured to sample the input signal according to a reference clock signal and to detect a maximum input signal
to hold;

a phase measuring unit configured to measure a phase of the sampled input signal based on the sampled input signal and the
detected maximum input signal; and

a reference signal generating unit configured to generate a reference signal having a specific value in response to the measured
phase, wherein the reference signal generating unit is configured to sample and to hold the generated reference voltage based
on the reference clock signal to output the reference signal.

US Pat. No. 9,219,148

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

MagnaChip Semiconductor, ...

1. A semiconductor device, comprising:
a semiconductor substrate comprising a trench formed therein;
a bottom electrode formed inside the trench;
a top electrode formed inside the trench and above the bottom electrode; and
an insulating layer separating the top electrode from the bottom electrode,
wherein the insulating layer has an uneven upper surface, and an additional depression having a shape of a key hole with a
substantially vertical sidewall is formed in the uneven upper surface;

the top electrode has an uneven lower surface; and
the uneven lower surface of the top electrode comprises a curved surface with a protrusion in a center portion of the trench
that protrudes toward the bottom electrode to fill the additional depression having the shape of the key hole.

US Pat. No. 9,391,137

POWER SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Magnachip Semiconductor, ...

1. A power semiconductor device comprising:
a substrate;
a trench structure situated in the substrate and comprising first trenches and dummy trenches formed adjacent to the first
trenches;

a first well region of a second conductivity type situated between the first trenches;
a base region of a first conductivity type situated on the first well region;
a source region of the second conductivity type and a first contact region of the first conductivity type situated in the
base region;

gate insulating layers situated in the first trenches and the dummy trenches;
gate electrodes situated on the gate insulating layers;
a field stop layer situated below the base region;
a collector layer and a drain electrode situated below the field stop layer; and
a dummy cell region situated between the first trenches and the dummy trenches,
wherein the dummy cell region has no channel region.

US Pat. No. 9,596,723

PWM SIGNAL GENERATING CIRCUIT FOR DC-DC CONVERTER USING DIMMING SIGNAL AND LED DRIVING CIRCUIT HAVING THE SAME IN DIRECT DIGITAL DIMMING METHOD

Magnachip Semiconductor, ...

1. A pulse width modulation (PWM) signal generating circuit, comprising:
a signal extending circuit configured to
receive an input dimming signal, wherein the input dimming signal comprises a plurality of pulses alternately having an on-period
and off-period, and

generate an extended dimming signal, wherein the extended dimming signal has, for each on-period of the input dimming signal,
an on-period exceeding the on-period of the input dimming signal;

an oscillator configured to generate a clock signal not synchronized with the input dimming signal; and
a signal generating circuit configured to generate a PWM signal pulse for each on-period of the extended dimming signal, in
response to the clock signal having a falling edge during the on-period of the extended dimming signal.

US Pat. No. 9,190,469

SUPER JUNCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

MagnaChip Semiconductor, ...

1. A super junction semiconductor device comprising:
an n-type semiconductor region disposed in a substrate;
two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel
to a surface of the substrate;

a p-type body region disposed on at least one of the p-type semiconductor regions; and
a source region disposed in the p-type body region,
wherein a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions are implanted with
an n-type dopant.

US Pat. No. 9,594,041

CAPACITIVE HUMIDITY SENSOR

Magnachip Semiconductor, ...

1. A capacitive humidity sensor, comprising:
an upper electrode disposed on a first plane comprising
first electrodes;
discrete second electrodes disposed on the first plane and between each of a pair of adjacent first electrodes; and
a humidity sensitive layer disposed between each of a pair of adjacent second electrodes.

US Pat. No. 9,099,554

SEMICONDUCTOR DEVICE WITH LOW ON RESISTANCE AND METHOD FOR FABRICATING THE SAME

MagnaChip Semiconductor, ...

9. A method for fabricating a semiconductor device comprising a trench having an upper trench part and a lower trench part,
the method comprising:
forming a first trench in a substrate by using a hard mask material layer;
forming an oxide layer along an exposed surface of the first trench;
forming a nitride layer on the oxide layer inside the first trench and along an exposed surface of the hard mask material
layer;

etching the oxide layer along a bottom surface of the first trench to expose the bottom surface while leaving at least a portion
of the oxide layer along a side surface of the first trench;

etching the substrate beneath the exposed bottom surface of the first trench to form the lower trench part of the trench;
and

removing the oxide layer along the side surface of the first trench to form the upper trench part of the trench, the upper
trench part being wider than a lower trench part in width.

US Pat. No. 9,601,453

SEMICONDUCTOR PACKAGE

Magnachip Semiconductor, ...

1. A semiconductor package comprising:
a monolithic type first die comprising a driver circuit and a low-side output power device connected to the driver circuit;
a second die disposed above the first die, the second die comprising a high-side output power device;
a first connection unit connecting a top of the first die and a bottom of the second die; and
a second connection unit disposed on the second die.

US Pat. No. 9,281,075

MEMORY PROGRAMMING METHOD AND APPARATUS

Magnachip Semiconductor, ...

1. A memory programming apparatus comprising:
a memory reader configured to read a read data in a plurality of cells related with an address of a programmable memory; and
a memory writer configured to
record a write data on the plurality of cells,
compare the write data with the read data,
generate a re-writing pattern,
correct at least one mismatch cell among the plurality of cells, and
generate a mask data based on the read data to generate the re-writing pattern.

US Pat. No. 9,253,834

LED DRIVER CIRCUIT HAVING A SENSING UNIT

Magnachip Semiconductor, ...

1. An LED driving circuit, comprising:
an input unit configured to receive a dimming signal to drive an LED array;
a DC-DC converter, comprising a power transistor, configured to perform a switching operation, wherein the DC-DC converter
is configured to use the switching operation to provide an output voltage to the LED array;

a PWM signal generating unit configured to provide a PWM signal to the power transistor to adjust power of the LED array;
an LED driving unit configured to use the dimming signal to drive the LED array; and
a sensing unit configured to sense a degradation of the power transistor.

US Pat. No. 9,281,836

SWITCHING NOISE RESISTANT INTEGRATING ANALOG-DIGITAL CONVERTER

Magnachip Semiconductor, ...

1. An integrating analog-digital converter comprising:
an input unit configured to receive an input voltage and a predetermined reference voltage;
a differential amplifier configured to receive and amplify a differential input voltage based on the input voltage that is
outputted through an output terminal of the input unit;

a comparator configured to compare a differential output voltage that is outputted from the differential amplifier; and
a control logic unit configured to output a counted digital output value, in accordance with a result of the comparator, as
a final output value.

US Pat. No. 9,257,304

METHOD OF MANUFACTURING NON-VOLATILE MEMORY DEVICE

Magnachip Semiconductor, ...

1. A method of manufacturing a non-volatile memory device, comprising:
providing a substrate comprising a logic area and a cell area;
forming a floating gate on the cell area;
depositing a first conductive film and a protective film on the substrate;
patterning the protective film;
depositing a hard mask layer on the first conductive film and the patterned protective film;
patterning the hard mask layer;
forming a logic gate on the logic area using the patterned hard mask layer;
exposing a surface of the first conductive film in the cell area; and
forming a control gate on the cell area.

US Pat. No. 9,595,590

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Magnachip Semiconductor, ...

1. A semiconductor device comprising:
a substrate;
a well region of a first conductivity type disposed in the substrate;
an extended drain junction region disposed in the well region of a first conductivity type;
a source region disposed in the well region;
a drain region disposed in the extended drain junction region;
a shallow trench isolation region disposed adjacent to the drain region; and
a stepped gate oxide layer disposed on the extended drain junction region comprising a thin gate insulating layer and a thick
gate insulating layer, the thick gate insulating layer being disposed closer to the drain region than the thin gate insulating
layer;

a gate electrode disposed above the stepped gate oxide layer;
wherein the gate electrode is positioned to overlap an entire length of the thick gate insulating layer that overlaps the
extended drain junction region,

wherein the extended drain junction region overlaps with a portion of the thick gate insulating layer and a portion of the
thin gate insulating layer,

wherein the extended drain junction region extends laterally to a portion of the well region from the drain region, and
wherein the well region of the first conductivity type is disposed to have a depth deeper than a depth of the shallow trench
isolation region.

US Pat. No. 9,543,939

TRIGGER CIRCUIT AND LIGHT APPARATUS COMPRISING THE SAME

Magnachip Semiconductor, ...

1. A trigger circuit, comprising:
a high voltage protector configured to scale down a first voltage according to an internal voltage to output a second voltage
having a lower level than the first voltage;

a switching trigger configured to detect that the outputted second voltage falls below a certain voltage level to provide
a switching trigger signal; and

a switching controller configured to provide a switching control signal for turning on a driving switching element in response
to receiving the switching trigger signal.

US Pat. No. 9,245,997

METHOD OF FABRICATING A LDMOS DEVICE HAVING A FIRST WELL DEPTH LESS THAN A SECOND WELL DEPTH

Magnachip Semiconductor, ...

16. A method of fabricating a semiconductor device, the method comprising:
forming a first deep well, a second deep well, and a boundary groove configured to partially separate the first deep well
from the second deep well, all in a substrate,

wherein a depth of the first deep well is less than a depth of the second deep well,
wherein the first deep well is in direct contact with the substrate,
wherein a bottom surface of the first deep well includes a non-boundary groove,
wherein a bottom surface of the second deep well is substantially planar, and
wherein a first depth from a peak of the boundary groove to a top surface of the first deep well is less than a second depth
from a peak of the non-boundary groove to the top surface of the first deep well, and both the first and second depths are
less than a depth from a bottom surface of the first deep well to the top surface of the first deep well;

forming a body region inside the first deep well, wherein a conductivity type of the body region is different from a conductivity
type of the first deep well;

forming a drain region inside the second deep well; and
forming a source region inside the body region;
wherein a region proximate to the boundary groove has a lower dopant concentration than other regions of the first deep well
and the second deep well.

US Pat. No. 9,202,886

METHOD FOR FABRICATING A SCHOTTKY DIODE INCLUDING A GUARD RING OVERLAPPING AN INSOLATION LAYER

MAGNACHIP SEMICONDUCTOR, ...

1. A method for fabricating a Schottky diode, comprising:
forming an isolation layer in a substrate in which a deep well of a second conductive type is formed;
forming a well region of a second conductive type in the deep well along an outer sidewall of the isolation layer to be located
at one side of the isolation layer;

forming a guard ring of a first conductive type in the deep well along the outer sidewall of the isolation layer to be located
at an opposite side of the isolation layer in such a manner that a part of the guard ring overlaps the isolation layer; and

forming an anode electrode over the substrate to be coupled to the deep well and the guard ring and simultaneously forming
a cathode electrode coupled to the well region over the substrate,

wherein an impurity doping concentration of the well region is reduced in a depth direction from a surface of the substrate,
wherein the forming of the well region comprises:
forming an ion implantation mask over the substrate to expose the deep well of an outer side of the isolation layer;
forming a first impurity region in the deep well by ion implanting a second conductive type impurity by using the ion implantation
mask as an ion implantation barrier;

forming a second impurity region on an upper portion of the first impurity region by ion-implanting the second conductive
type impurity by using the ion implantation mask as an ion implantation barrier, the second impurity region having an impurity
doping concentration higher than an impurity doping concentration of the first impurity region; and forming a third impurity
region on an upper portion of the second impurity region by ion-implanting the second conductive type impurity by using the
ion implantation mask as an ion implantation barrier, the third impurity region having an impurity doping concentration higher
than an impurity doping concentration of the second impurity region.

US Pat. No. 9,396,985

ELEMENT ISOLATION STRUCTURE OF SEMICONDUCTOR AND METHOD FOR FORMING THE SAME

MAGNACHIP SEMICONDUCTOR, ...

1. A method for forming an element isolation structure of a semiconductor device comprising:
providing a semiconductor substrate having a top surface;
forming a first hard mask on the semiconductor substrate;
exposing the top surface of the semiconductor substrate by patterning the first hard mask, thereby forming a first opening
with a first width, wherein no trench in the substrate is formed;

forming a second hard mask on the exposed top surface of the semiconductor substrate;
forming a deep trench region in the semiconductor substrate by patterning the second hard mask and the semiconductor substrate;
removing the patterned second hard mask;
forming a shallow trench region overlapped with the deep trench region by etching the semiconductor substrate through the
first opening with the first width;

forming a side wall film and a first element isolation film in the deep trench region and the shallow trench region;
selectively removing the first element isolation film and the sidewall film in the shallow trench region such that a bottom
surface of the shallow trench region is exposed, thereby forming a sidewall film pattern and a first element isolation film
pattern within the deep trench region;

forming an oxide on the entire surface of the substrate including the shallow trench region; and
forming a second element isolation film pattern contacted with the first element isolation film pattern by patterning the
oxide.

US Pat. No. 9,379,187

VERTICALLY-CONDUCTING TRENCH MOSFET

MagnaChip Semiconductor, ...

7. A semiconductor device comprising:
a trench disposed within a substrate, the trench comprising an upper trench part that is wider than a lower trench part in
width;

a gate disposed in the trench;
an interlayer insulating layer pattern disposed above the gate in the trench;
a source region disposed within the substrate and contacting a sidewall of the upper trench part;
a body region disposed below the source region in the substrate; and
a contact trench disposed above the body region and filled with a conductive material.

US Pat. No. 9,595,966

LEVEL SHIFTER AND NON-VOLATILE MEMORY DEVICE USING THE SAME

Magnachip Semiconductor, ...

1. A level shifter, comprising:
a first level shifter configured to output an intermediate signal as a selected one of a high voltage from a power supply
terminal and a first low voltage, wherein the high voltage is a first positive supply voltage or a positive voltage and the
first low voltage is a first negative supply voltage, to an intermediate signal node and output the not selected one of the
high voltage and the first low voltage to an inverted intermediate signal node; and

a second level shifter configured to output the high voltage, based on the intermediate signal, through one of an output terminal
and an inverted output terminal, and output a second low voltage through the other one of the output terminal and the inverted
output terminal,

wherein the second low voltage is a second negative supply voltage or a negative voltage, and
wherein the second level shifter comprises a P-type transistor with a body connected to the intermediate signal node or the
inverted intermediate signal node.

US Pat. No. 9,281,202

NONVOLATILE MEMORY CELL AND METHOD FOR FABRICATING THE SAME

MagnaChip Semiconductor, ...

1. A nonvolatile memory cell, comprising:
a drain region formed in a substrate;
a source region formed in the substrate to be separated from the drain region;
a floating gate formed over the substrate between the drain region and the source region;
a lightly doped drain region or a drift region formed in the substrate in a direction that the source region is formed;
a dielectric layer formed on sidewalls of the floating gate, the dielectric layer comprising a first surface disposed between
the source region and the floating gate and a second surface disposed between the drain region and the floating gate;

a control gate formed on the first surface of the dielectric layer on a side of the floating gate facing the source region;
and

a halo region formed in the substrate between the drain region and the floating gate.

US Pat. No. 9,431,389

ESD TRANSISTOR FOR HIGH VOLTAGE AND ESD PROTECTION CIRCUIT THEREOF

MagnaChip Semiconductor, ...

1. An ESD transistor, comprising:
a collector region disposed on a surface of a substrate;
a sink region disposed vertically below the collector region;
a buried layer protruding horizontally further than the sink region under the sink region;
an emitter region spaced apart from a base contact region in a base region; and
a first insulating film disposed between the emitter region and the base contact region,
wherein the ESD transistor is a bipolar junction transistor.

US Pat. No. 9,082,475

NONVOLATILE MEMORY DEVICE

Magnachip Semiconductor, ...

1. A nonvolatile memory device, comprising:
unit cells comprising an e-fuse and an input unit configured to provide the e-fuse with a write voltage during a writing operation
of the nonvolatile memory device;

a read current supply unit which provides a read voltage to the unit cells during reading operation of the nonvolatile memory
device;

an operation control unit configured to select a unit cell from the unit cells to perform reading and writing operations;
a reference voltage generating unit configured to voltage-divide the read voltage using series-connected resistors and generate
a reference voltage based on the voltage-divided read voltage; and

a sensing unit configured to compare a size of a voltage through an e-fuse of the selected unit cell based on the read voltage
with the reference voltage, and sense data of the e-fuse of the selected unit cell, wherein the e-fuse is configured to store
1-bit information and the unit cells comprise

a first switching device configured to selectively output the read voltage to the e-fuse of the unit cells,
a second switching device configured to enable an electric current to flow through the e-fuse of the unit cells according
to the read voltage, and

a third switching device configured to enable electric current to flow through the e-fuse according to the write voltage.

US Pat. No. 9,299,919

HALL SENSOR WITH IMPROVED DOPING PROFILE

Magnachip Semiconductor, ...

1. A Hall sensor comprising:
a semiconductor substrate;
a sensing region formed on the substrate;
an isolation region formed on the sensing region; and
a high concentration doping region formed on an upper portion of the sensing region,
wherein a maximum doping concentration region is formed at a predetermined depth with respect to the substrate surface and
the maximum doping concentration region is under the high concentration doping region.

US Pat. No. 9,373,591

SEMICONDUCTOR DEVICE FOR PREVENTING CRACK IN PAD REGION AND FABRICATING METHOD THEREOF

Magnachip Semiconductor, ...

1. A semiconductor device, comprising:
a lower pad;
an upper pad which is formed above the lower pad;
an insulation layer which is formed between the lower pad and the upper pad;
a Via net for electrically connecting the lower pad and the upper pad in the insulation layer, the Via net having a net shape
in which a unit grid comprising a conductive metal is connected with its adjacent unit grids comprising a conductive metal
to form a conductive metal net structure in a plan view;

a plurality of Via holes in the unit grid of the Via net for electrically connecting the lower pad and the upper pad, a first
Via hole among the plurality of Via holes being disposed in a center of the unit grid,

wherein proportions of conductive metal forming the Via net and the plurality of Via holes in each unit grid of the Via net
are from approximately 10% to 75% of entire area of each unit grid.

US Pat. No. 9,219,057

ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME

MagnaChip Semiconductor, ...

1. An electrostatic discharge (ESD) protection device, comprising:
a substrate with a top surface;
a gate electrode over the substrate;
a drain region disposed adjacent to the gate electrode;
a source region disposed adjacent to the gate electrode;
first and second doping regions formed in the substrate exposed at both sides of the gate electrode, the first and second
doping regions having the same conductivity type and being aligned with sidewalls of the gate electrode;

a third doping region formed in the second doping region and doped with an opposite conductivity type to that of the second
doping region;

fourth and fifth doping regions spaced apart from the gate electrode and provided in the substrate exposed at both sides of
the gate electrode, the fourth and fifth doping regions having the same conductivity type as the first and second doping regions;

a silicide blocking layer in direct contact with the gate electrode,
wherein the second doping region and the fifth doping region are disposed in the drain region,
wherein the first doping region and the fourth doping region are disposed in the source region,
wherein the third doping region is disposed in the drain region and the third doping region is not disposed in the source
region such that the drain region is asymmetric with respect to the source region,

wherein the second doping region has a first depth with reference to the top surface and an entire region of the third doping
region has a second depth with reference to the top surface which is substantially the same as the first depth, and

wherein the third doping region is in direct contact with the fifth doping region.

US Pat. No. 9,271,369

LED DRIVER APPARATUS

Magnachip Semiconductor, ...

1. A Light Emitting Diode (LED) driving apparatus, comprising:
an input unit configured to receive a dimming signal;
an extension unit configured to extend an ON time of the dimming signal;
an LED driving unit configured to drive an LED array using the extended dimming signal; and
a detection unit configured to detect a degradation of the LED array by measuring a forward voltage between the LED array
and the LED driving unit,

wherein the detection unit is configured to detect the degradation by measuring the forward voltage at a time of a declining
edge of the dimming signal.

US Pat. No. 9,178,423

RAMP CIRCUIT AND DIRECT CURRENT (DC)-DC CONVERTER THEREOF

Magnachip Semiconductor, ...

1. A ramp circuit, comprising:
a first amplifier configured to receive a first voltage corresponding to an output voltage;
a second amplifier configured to receive a second voltage corresponding to an input voltage;
a resistor provided between output terminals of the first amplifier and the second amplifier;
a current mirror unit configured to copy a current value that flows in the resistor; and
an output unit configured to control a current output from the current mirror unit into a capacitor to output a ramp signal
through an output terminal of the output unit.

US Pat. No. 9,368,389

SEMICONDUCTOR DEVICE WITH VOIDS WITHIN SILICON-ON-INSULATOR (SOI) STRUCTURE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE

Magnachip Semiconductor, ...

1. A semiconductor device with voids within a silicon-on-insulator (SOI) structure comprising:
a semiconductor substrate;
an insulating layer disposed on the substrate;
a silicon-on-insulator (SOI) layer disposed on the insulating layer;
a device isolation layer and an active area disposed within the SOI layer;
a void disposed within the insulating layer; and
a sealing insulating layer or film sealing an opening of the void.

US Pat. No. 9,362,207

METAL WIRING OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Magnachip Semiconductor, ...

1. A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device
comprising a low voltage applying region adjacent to a high voltage applying region, the metal wiring comprising:
an isolator region;
a first lower metal layer electrically connected to the semiconductor component;
a first upper metal layer configured to be electrically connected to an external power supply;
a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer,
each of the plurality of inter-metal dielectric layers comprising at least one contact plug formed in a via trench for providing
an electrical connection between the first lower metal layer and the first upper metal layer; and

a plurality of etching stop layers deposited on each of the plurality of inter-metal dielectric layers,
wherein the plurality of inter-metal dielectric layers are each a continuous multilayer oxide film formed between adjacent
etching stop layers or between the first upper or lower metal layer and its respective adjacent etching stop layer,

wherein the plurality of inter-metal dielectric layers are each a multilayer oxide film comprising a plurality of alternating
tensile stress oxide layers and compressive stress oxide layers.

US Pat. No. 9,362,224

ELECTRICAL FUSE AND METHOD OF FABRICATING THE SAME

Magnachip Semiconductor, ...

1. An electrical fuse, comprising:
an anode formed on a substrate;
a cathode formed on the substrate;
a fuse link connecting the anode and the cathode to each other;
a first contact formed on the anode; and
a second contact formed on the cathode and arranged closer to the fuse link than the first contact,
wherein the second contact is arranged closer to an edge of the cathode proximal to the fuse link than an edge of the cathode
distal to the fuse link, and

wherein an area defined by virtual extension of the fuse link, extending from the edge of the cathode distal to the fuse link
to an edge of the anode distal to the fuse link, has no contact formed thereon.

US Pat. No. 9,281,395

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Magnachip Semiconductor, ...

14. A method of fabricating a semiconductor device, comprising:
forming an N type well region and a P type well region in a substrate;
forming a first gate insulating layer on a first portion of the P type well region and the N type well region;
forming a second gate insulating layer on a second portion of the P type well region, the second gate insulating layer having
a smaller thickness than the first gate insulating layer;

forming a gate electrode over the first gate insulating layer and the second gate insulating layer;
forming device isolation layers in the N type well region and the P type well region;
forming a drain region in the N type well region and a source region in the P type well region; and
forming a well pick-up region spaced apart from the source region by the device isolation layer.

US Pat. No. 9,362,158

OTP MEMORY CELL AND FABRICATING METHOD THEREOF

MAGNACHIP SEMICONDUCTOR, ...

1. A method for forming a one-time programmable (OTP) memory cell, the method comprising:
forming an isolation layer in a first conductivity type well;
forming a gate insulating layer and a gate electrode on the well,
wherein the gate insulating layer comprises a capacitor region, a first fuse projection region, and a second fuse projection
region; and

exposing an upper portion of the well to ions of a second conductivity type to form a junction region that surrounds the first
fuse projection region and the second fuse projection region,

wherein the isolation layer is formed in the well between the first fuse projection region and the second fuse projection
region.

US Pat. No. 9,455,629

CURRENT COMPENSATION CIRCUIT AND LIGHT APPARATUS COMPRISING THE SAME

Magnachip Semiconductor, ...

1. A current compensation circuit, comprising:
a current compensator configured to perform a charging or a discharging of a capacitive element according to whether a sensing
voltage is less than or greater than a certain voltage and to delay a turn-off point of a driving switching element until
a corresponding discharging quantity is identical to a corresponding charging quantity; and

a switching controller configured to provide a switching control signal at the delayed turn-off point of the driving switching
element.

US Pat. No. 9,076,778

SEMICONDUCTOR PACKAGE

MagnaChip Semiconductor, ...

1. A semiconductor package, comprising:
a monolithic die;
a driving circuit, a low-side output power device, and a high-side output power device disposed in the monolithic die; and
an upper electrode and a lower electrode disposed above and below the monolithic die, the lower electrode electrically connected
to a power ground,

wherein the low-side output power device comprises a bottom-source type lateral double diffused metal oxide semiconductor
(LDMOS).

US Pat. No. 9,621,038

SWITCH CONTROL CIRCUIT AND CONVERTER USING THE SAME

Magnachip Semiconductor, ...

22. A Continuous Current Mode (CCM) operation converter comprising:
a load that is series-coupled to input power;
an inductor that is series-coupled to the load;
a current control switch that is series-coupled to the inductor to control a current flowing into the load;
a freewheeling diode that is parallel-coupled to the load and the series-coupled inductor; and
a switch control circuit configured to control the current control switch,
wherein the switch control circuit comprises
a sensing unit configured to measure a current flowing into the load,
a folder unit configured to fold a sensing signal related to the measured current based on a first reference voltage to generate
first and second folder output signals based on the first reference voltage, the first and second folder output signals being
symmetric to each other,

a comparison unit configured to perform an AND logical operation on a comparison result and a folder signal and to output
the AND operation result, the comparison result being generated by comparing the generated first and second folder output
signals and the folder signal being generated by comparing the sensing signal and the first reference voltage, and

a control unit configured to control an operation of the current control switch according to a comparison result of the comparison
unit.

US Pat. No. 9,496,703

LEAKAGE CURRENT DETECTION CIRCUIT, LIGHT APPARATUS COMPRISING THE SAME AND LEAKAGE CURRENT DETECTION METHOD

MagnaChip Semiconductor, ...

1. A leakage current detection circuit, comprising:
a driving voltage detection unit configured to detect a cut-off point of a driving voltage controlled through a driving voltage
switch;

a leakage current detection unit configured to detect a leakage current of the driving voltage switch after cutting off the
driving voltage, and further configured to generate a leakage detection signal when the driving voltage related to the leakage
current exceeds a reference detection voltage; and

a driving voltage control unit configured to turn off the driving voltage switch at the cut-off point of the driving voltage,
and further configured to maintain the driving voltage switch in an off state when the leakage detection signal is received.

US Pat. No. 9,496,335

SUPER JUNCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Magnachip Semiconductor, ...

1. A method of forming a super junction semiconductor device, the method comprising: forming a first epitaxial layer of first
conductivity type above a substrate;
forming first pillar regions of second conductivity type by doping two or more areas of the first epitaxial layer with a second
conductivity type dopant; and

forming an ion implantation region by doping the first pillar regions and the first epitaxial layer with a first conductivity
type dopant; and

forming a second epitaxial layer and second pillar regions above the first epitaxial layer and the first pillar regions.

US Pat. No. 9,455,248

SEMICONDUCTOR DEVICE WITH SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF

Magnachip Semiconductor, ...

1. A semiconductor device having a schottky diode, the semiconductor device comprising:
an epitaxial layer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first
conductivity type arranged in that order;

a gate trench extending from the source layer to a part of the epitaxial layer;
a body trench formed at a predetermined distance from the gate trench and extending from the source layer to a part of the
epitaxial layer;

a barrier metal formed along an inner wall of the body trench;
a source metal formed on the barrier metal; and
a guard ring of the second conductivity type contacting the barrier metal and formed in the epitaxial layer, and
wherein a bottom surface of the body trench is in direct contact with the epitaxial layer, such that the bottom surface of
the body trench forms a schottky contact with the epitaxial layer, and a portion of the guard ring is formed below a junction
between the body layer and the epitaxial layer.

US Pat. No. 9,659,667

CIRCUIT FOR READING ONE TIME PROGRAMMABLE MEMORY

MagnaChip Semiconductor, ...

1. A circuit for reading a one time programmable (OTP) memory, comprising:
a controller that receives a read input signal and generates a read delay signal, a read voltage signal, and a read latch
signal;

a read voltage generator that generates a read voltage based on the read voltage signal and outputs the read voltage to a
detecting node;

an OTP memory unit cell comprising a first electrode connected to the detecting node;
a first detecting unit that determines a voltage at the detecting node;
a determining unit that delays an output signal from the first detecting unit based on the read delay signal; and
a latch unit that latches an output signal from the determining unit during a first delay time at a falling edge of the read
input signal based on the read latch signal.

US Pat. No. 9,612,134

METHOD OF SENSING SLIDING BY HALL SENSOR AND SENSING SYSTEM USING THE SAME

Magnachip Semiconductor, ...

1. A method of sensing, by a sensor, a movement in a first direction, comprising:
arranging a first Hall element displaced in the first direction from a second Hall element;
arranging a magnetic field source configured to generate a magnetic field;
measuring the magnetic field at each of the first and second Hall elements; and
comparing a strength of the magnetic field measured at the first Hall element to a strength of the magnetic field measured
at the second Hall element; and

determining whether the movement occurs,
wherein the arranging of the first and the second Hall elements comprises arranging the first and second Hall elements on
a first body,

wherein the arranging of the magnetic field source comprises arranging the magnetic field source on a second body,
wherein the determining whether the movement occurs comprises determining whether the second body moves in the first direction
relative to the first body, and

wherein the first body comprises a terminal comprising a sensor chip.

US Pat. No. 9,571,614

APPARATUS USING HALL SENSOR

Magnachip Semiconductor, ...

1. An apparatus comprising:
a display screen positioned in a main body;
a cover unit configured to cover the display screen;
a magnet disposed in or on the cover unit; and
a Hall sensor positioned in the main body, the Hall sensor comprising a plurality of Hall elements positioned such that an
axis passing through two of the plurality of Hall elements is substantially perpendicular to the display screen,

wherein each of the two of the plurality of Hall elements is configured to measure a magnetic field of the magnet.

US Pat. No. 9,558,992

METAL WIRING OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Magnachip Semiconductor, ...

1. A method of forming a metal wiring in a semiconductor device, the method comprising:
forming an insulation layer and a first lower metal layer above a semiconductor component;
forming a plurality of inter-metal dielectric layers comprising at least one contact plug above the first lower metal layer;
forming a first upper metal layer on the plurality of inter-metal dielectric layers; and
forming a plurality of etching stop layers deposited on each of the plurality of inter-metal dielectric layers,
wherein the plurality of inter-metal dielectric layers are each a continuous multilayer oxide film formed between adjacent
etching stop layers or between the first upper or lower metal layer and its respective adjacent etching stop layer,

wherein the plurality of inter-metal dielectric layers are each a multilayer oxide film comprising a plurality of alternating
tensile stress oxide layers and compressive stress oxide layers,

wherein the plurality of inter-metal dielectric layers extends from a low voltage applying region of the semiconductor device
to a high voltage applying region, and forms an isolator region in the high voltage applying region, and

wherein the first lower metal layer is electrically connected to the semiconductor component in the low voltage applying region.

US Pat. No. 9,947,786

SEMICONDUCTOR STRUCTURE HAVING A JUNCTION FIELD EFFECT TRANSISTOR AND A HIGH VOLTAGE TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

Magnachip Semiconductor, ...

1. A semiconductor device comprising:a high voltage transistor and a junction field effect transistor (JFET) formed on a substrate, wherein
the JFET comprises
a first conductivity type deep-well region comprising a diffusion region located on the substrate,
a second conductivity type buried impurity layer located on the first conductivity type deep-well region,
a first conductivity type common drain region located on the first conductivity type deep-well region,
a first conductivity type first source region located on the first conductivity type deep-well region,
a second conductivity type pick-up region formed on the substrate, and
an insulating layer formed on the substrate between the first conductivity type common drain region and the first conductivity type first source region, wherein
the diffusion region has an impurity concentration that is lower than other portions of the first conductivity type deep-well region.

US Pat. No. 10,231,302

POWER FACTOR CORRECTION CONTROL CIRCUIT AND DRIVING METHOD THEREOF

MAGNACHIP SEMICONDUCTOR, ...

1. A circuit for adjusting a frequency of an AC (Alternating Current) direct lighting apparatus, comprising:a reference voltage generation unit that receives a dimming voltage having a first frequency and a first voltage range, and generates a reference voltage having a second voltage range;
a sensing section determining unit that generates first and second section reference voltages based on the reference voltage, and determines a driving current sensing section based on the first and second section reference voltages; and
a driving signal generation unit that generates a switching device driving signal having a second frequency during the driving current sensing section, wherein the second frequency is determined based on a duration of the driving current sensing section, and wherein the second frequency has a fixed switching frequency regardless of a change of the reference voltage.

US Pat. No. 9,735,288

ONE TIME PROGRAMMABLE NON-VOLATILE MEMORY DEVICE

Magnachip Semiconductor, ...

1. A one-time programmable non-volatile memory device, comprising:
a first conductivity type well region located in a semiconductor substrate;
a selection gate electrode and a floating gate electrode located on the substrate;
a first doped region located between the selection gate electrode and the floating gate electrode, the first doped region
overlapping with the floating gate electrode and the selection gate electrode;

a second conductivity type source region located on one side of the selection gate electrode; and
a second conductivity type drain region located on one side of the floating gate electrode, wherein
a depth of the drain region has a shallower depth than that of the first doped region with respect to a top surface of the
substrate.

US Pat. No. 9,961,742

MULTI-CHANNEL LED DRIVER WITH OVERHEATING PROTECTION CAPABILITIES

Magnachip Semiconductor, ...

1. An apparatus to drive a multi-channel light emitting diode (LED) array, comprising:a circuit connected to an LED string and comprising
a switching transistor comprising a first terminal and a second terminal,
an error amplifier connected to the switching transistor and configured to control current flowing through the LED string to have a target magnitude, and
an overheating protection circuit connected to the switching transistor and configured to regulate current flowing through the switching transistor to have a magnitude less than or equal to the target magnitude by providing a current dividing path between the first and second terminals, wherein the overheating protection circuit comprises a comparator configured to compare a voltage at the second terminal to a trigger level voltage to control current flow through the current dividing path.

US Pat. No. 9,888,552

DETECTING CIRCUIT FOR SHORT OF LED ARRAY AND LED DRIVING APPARATUS USING THE SAME

Magnachip Semiconductor, ...

1. A detection circuit to detect a short in LED arrays, the detection circuit comprising:
a voltage measuring unit configured to measure respective feedback voltages of the LED arrays, and to output a first feedback
voltage;

a short detecting unit configured to detect the short in the LED arrays, by using the measured feedback voltages; and
a detection control unit configured to control the short detecting unit to stop the detection of the short in each of the
LED arrays, in response to the first feedback voltage exceeding a first preset reference voltage and to control the short
detecting unit to perform the detection of the short, in response to the first feedback voltage being below a second preset
reference voltage, the second preset reference voltage being below the first preset reference voltage.

US Pat. No. 10,062,616

METHOD OF MANUFACTURING A CMOS TRANSISTOR

Magnachip Semiconductor, ...

1. A method to manufacture a complementary metal-oxide-semiconductor (CMOS) transistor, comprising:forming a gate insulating film on a semiconductor substrate;
forming a first gate electrode pattern on the gate insulating film in an n-type metal-oxide-semiconductor (NMOS) transistor area;
forming a second gate electrode pattern on the gate insulating film in a p-type metal-oxide-semiconductor (PMOS) transistor area;
forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern in the PMOS transistor area;
performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type lightly doped drain (LDD) region in the PMOS transistor area using the first photoresist pattern, wherein the performing of the first ion injection process comprises performing ion injection through the exposed second gate electrode pattern in the PMOS transistor area;
removing the first photoresist pattern;
forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern in the NMOS transistor area;
performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region in the NMOS transistor area using the second photoresist pattern, wherein the performing of the second ion injection process comprises performing ion injection through the exposed first gate electrode pattern in the NMOS transistor area;
removing the second photoresist pattern; and
forming sidewall spacers at sidewalls of the first and second gate electrode patterns.

US Pat. No. 9,635,746

DETECTING CIRCUIT FOR OPEN OF LED ARRAY AND LED DRIVER APPARATUS USING THE SAME

Magnachip Semiconductor, ...

1. A detecting circuit to detect whether an LED array is open, the detecting circuit comprising:
a resistance unit operatively connected in series to the LED array;
a first switching unit configured to be turned on when a voltage of the resistance unit is greater than or equal to a predetermined
voltage level;

a second switching unit configured to be turned on in response to the first switching unit being turned on, and
an output unit configured to produce an output indicative of whether the LED array is open, based on the first switching unit
or the second switching unit.

US Pat. No. 10,038,056

METHOD FOR FABRICATING OF CELL PITCH REDUCED SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

MagnaChip Semiconductor, ...

1. A method for fabricating a semiconductor device, comprising:forming a plurality of trenches at a predetermined cell pitch in an upper surface portion of a substrate;
forming a first insulation film on the substrate;
forming a gate electrode within each trench, wherein the gate electrode partially fills each trench from a bottom portion thereof;
forming a first conductivity type region in the upper surface portion of the substrate between the trenches;
forming a second conductivity type region in the upper surface portion of the substrate between the trench and the first conductivity type region;
forming a second insulation film that covers the gate electrode within each trench, wherein an upper surface of the second insulation film is positioned lower than an upper surface of the substrate; and
forming a source metal layer on the second insulation film, the source metal layer electrically connected to the first conductivity type region and the second conductivity type region,
wherein the substrate comprises an active region and a termination region, and the plurality of trenches are formed in the active region.

US Pat. No. 9,755,067

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Magnachip Semiconductor, ...

1. A semiconductor device, comprising:
a lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) device formed in a first region of the
semiconductor device; and

a complementary MOS (CMOS) device formed in a second region of the semiconductor device,
wherein the LDMOS device comprises:
a P type well region and an N type well region formed in a substrate;
a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region;
a gate electrode formed on the gate insulating layer;
a P type well pick-up region formed in the P type well region;
a drain region formed in the N type well region; and
a field relief oxide layer formed in the N type well region between the gate electrode and the drain region,
wherein the P type well region of the LDMOS device and a P type well region of the CMOS device have substantially the same
depth, and the N type well region of the LDMOS device and an N type well region of the CMOS device have substantially the
same depth.

US Pat. No. 9,741,844

LATERAL DOUBLE-DIFFUSED MOS TRANSISTOR HAVING DEEPER DRAIN REGION THAN SOURCE REGION

Magnachip Semiconductor, ...

1. A semiconductor power device, comprising:
a first well region having a first conductivity type disposed in a substrate having a second conductivity type opposite the
first conductivity type;

a gate overlapping the first well region, and vertically separated from the first well region by an insulating layer;
a source region disposed at a first side of the gate;
a buried layer having the second conductivity type disposed laterally in the first well region, wherein the buried layer is
vertically separated from the insulating layer by at least a portion of the first well region;

a drain region having the first conductivity type disposed on a second side of the gate laterally opposite the first side,
and contacting the buried layer to form a p-n junction between the drain region and the buried layer;

a body region having the second conductivity type disposed in the substrate at the first side of the gate;
a body contact region contacting the body region; and
a first isolation region disposed between the body contact region and the source region,
wherein the drain region has a depth greater than the source region and is spaced apart from the substrate by the first well
region,

wherein the source region is disposed in the body region, the body region having a depth shallower than the drain region.

US Pat. No. 10,074,644

INTEGRATED SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE FOR REDUCING NOISE

Magnachip Semiconductor, ...

1. An integrated semiconductor device, comprising:a first transistor and a second transistor sensitive to noise formed on a semiconductor substrate; and
an isolation structure located adjacent to the transistors, comprising
deep trenches,
trapping regions formed between the deep trenches, and
trench bottom doping regions formed on an end of each of the deep trenches,
wherein each of the trapping regions comprises
a buried layer,
a well region formed on the buried layer, and
a highly doped region formed on the well region.

US Pat. No. 9,698,258

SEMICONDUCTOR DEVICE

Magnachip Semiconductor, ...

1. A semiconductor device comprising:
a deep well region located on a semiconductor substrate;
a second conductivity type drift region and a first conductivity type body region in contact with each other and located on
the deep well region;

a second conductivity type drain region located on the drift region;
a second conductivity type source region located on the body region;
a gate insulating layer comprising
a first gate insulating layer arranged near the source region, and
a second gate insulating layer, that is thicker than the first gate insulating layer, located on a surface of the second conductivity
type drift region; and

a gate electrode located on the gate insulating layer,
wherein the drift region extends from the drain region towards a direction of the source region and towards a part of the
region of the first gate insulating layer,

wherein the second gate insulating layer comprises a first edge portion, a second edge portion and a planar bottom surface
extending from the first edge portion to the second edge portion, and

wherein a thickness of the second gate insulating layer decreases in a concave curve shape to each of the first edge portion
and the second edge portion and a top surface of the gate insulating layer extends continuously from the curve shape into
a top surface of the first gate insulating layer.

US Pat. No. 9,691,844

POWER SEMICONDUCTOR DEVICE

Magnachip Semiconductor, ...

1. A power semiconductor device comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a drift region located on the substrate having a first conductivity type;
an emitter electrode located on the first surface of the substrate;
a drain electrode located on the second surface of the substrate;
an emitter contact region in contact with the emitter electrode;
a trench gate structure that surrounds four sides of the emitter contact region;
a base region located under the emitter contact region having a second conductivity type;
a floating region located on an exterior region of the trench gate structure that surrounds the trench gate structure and
is deeper than the trench gate structure; and

a termination region located in the substrate and surrounding a cell region,
wherein the floating region is electrically floating and surrounds a bottom surface of the trench gate structure and is separate
from the base region, and

wherein an impurity concentration of the floating region is lower than an impurity concentration of the base region, and
wherein the cell region comprises the trench gate structure and the floating region, and wherein the termination region comprises
a termination ring region and a gate bus line.

US Pat. No. 9,842,780

METHOD FOR WAFER LEVEL RELIABILITY

Magnachip Semiconductor, ...

1. A method for ensuring wafer level reliability, comprising:
forming a trench on a semiconductor substrate;
forming a sidewall oxide layer and a liner nitride layer on the trench;
filling an insulating material on the liner nitride layer;
forming a PMOS element on the semiconductor substrate; and
assessing hot electron induced punch through (HEIP) for the PMOS element at a condition of gate and drain voltages satisfying
Vg=Vd, wherein Vg is the gate voltage and Vd is the drain voltage.

US Pat. No. 9,864,020

VERTICAL HALL SENSOR, HALL SENSOR MODULE AND METHOD FOR MANUFACTURING THE SAME

Magnachip Semiconductor, ...

1. A vertical Hall sensor comprising:
a first conductivity type substrate;
an input terminal comprising a first conductivity type input contact region situated inside the substrate, wherein the input
contact region is electrically connected to an input power source;

a first ground terminal and a second ground terminal, each comprising trenches spaced apart from each other by an interval
with the input terminal, an insulating layer disposed along sidewalls of the trenches, and a first conductivity type ground
contact region situated at bottoms of the trenches and electrically connected to a ground power source; and

a first sensing terminal and a second sensing terminal, each comprising a first conductivity type sensing contact region,
situated between the input terminal and the first ground terminal and between the input terminal and the second ground terminal
in the substrate, respectively, wherein the sensing contact regions are configured to detect a Hall voltage.

US Pat. No. 10,072,946

DISPLAY TERMINAL WITH FLIP COVER

Magnachip Semiconductor, ...

1. A device, comprising:a first body comprising a Hall sensor, the Hall sensor comprising a plurality of Hall elements disposed symmetrically and spaced apart from each other; and
a second body comprising a magnetic element, the second body being configured to overlap with the first body;
wherein the second body is configured to translate a maximum horizontal moving distance (LXmax) relative to the first body along a first axis of an overlapping region of the first body and a maximum vertical moving distance (LYmax) relative to the first body along a second axis of the overlapping region of the first body, L being a horizontal length of the Hall sensor and M being a vertical length of the Hall sensor,
wherein the magnetic element comprises a minimum size (LXmax*LYmax) corresponding to the maximum horizontal moving distance and the maximum vertical moving distance of the second body,
wherein LXmax and LYmax are respectively obtained based on a total value of a straight line moving distance and a rotational moving distance of the second body, or based on L or M, and
wherein LXmax is determined by the following:
LXmax=Max (A, Xc, Xd)+L+B; A and B being a left and a right horizontal sliding distance of the second body; Xc and Xd being a horizontal sliding distance by a clockwise and an anticlockwise rotation of the second body; and Max (A, Xc, Xd) being a maximum value among A, Xc and Xd.

US Pat. No. 9,888,534

TRIGGER CIRCUIT, LIGHT APPARATUS COMPRISING THE SAME AND TRIGGER METHOD

Magnachip Semiconductor, ...

1. A trigger circuit, comprising:
an off-time controller configured to receive a sensing voltage by sensing a driving current and to compare the sensing voltage
to first and second voltages that are close to a zero voltage value and symmetric to the zero voltage value to control a turn-off
time of a driving switch in order for the sensing voltage to correspond to the zero voltage value at a turn-on time point
of the driving switch; and

a switching controller configured to provide a switching control signal for turning on the driving switch at the turn-on time
point of the driving switch.

US Pat. No. 9,887,618

POWER SUPPLY DEVICE SENSING AC-OFF STATE

Magnachip Semiconductor, ...

1. A power supply device, comprising:
a rectifier configured to rectify AC power into DC power;
a transformer configured to supply output voltage by converting voltage of the DC power rectified by the rectifier; and
a Pulse Width Modulation (PWM) control module configured to determine an AC-off state, from a loss of AC power, based on a
sensed voltage rectified by the rectifier,

wherein the PWM control module comprises
a power device directly connected to the DC voltage rectified by the rectifier,
an AC-off detector configured to sense the AC-off state through the power device, and
an AC-off detector capacitor connected in series with the power device and configured to discharge a charged voltage based
on the sensed voltage rectified by the rectifier.

US Pat. No. 9,666,700

VERTICAL BIPOLAR JUNCTION TRANSISTOR AND MANUFACTURING METHOD THEREOF

MagnaChip Semiconductor, ...

1. A vertical bipolar junction transistor comprising:
a highly doped emitter region having a first conductivity type disposed on a semiconductor substrate;
a pair of highly doped collector regions, having the first conductivity type, symmetrically disposed on the semiconductor
substrate with respect to the emitter region;

a pair of highly doped base regions, having a second conductivity type opposite to the first conductivity type, symmetrically
disposed with respect to the emitter region, each base region being disposed between the emitter region and one of the collector
regions;

a drift region having a first doping concentration surrounding the emitter region and being deeper than either the base region
or the collector region, the drift region having the first conductivity type;

a base layer, having the second conductivity type, disposed below the drift region; and
a collector layer in contact with the base layer, the collector layer having a second doping concentration higher than the
first doping concentration, the collector layer having the first conductivity type;

wherein a field oxide layer defining an isolation layer is disposed between the emitter, collector, and base regions, and
wherein the isolation layer is deeper than either the base region or the collector region.

US Pat. No. 9,781,785

BALLAST TYPE DETECTING CIRCUIT AND LIGHT EMITTING DIODE LIGHTING APPARATUS HAVING THE SAME

Magnachip Semiconductor, ...

1. A ballast type detecting circuit comprising:
a ballast signal clamping circuit coupled to a ballast, wherein the ballast signal clamping circuit is configured to clamp
an output of the ballast; and

a ballast type detection circuit configured to compare first and second reference clocks and the clamped output of the ballast
to determine a type of the ballast, each of the first and second reference clocks having a frequency lower than an output
frequency of a first type ballast and higher than an output frequency of a second type ballast.

US Pat. No. 9,691,893

LOW-COST SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Magnachip Semiconductor, ...

1. A method of manufacturing a semiconductor device, the method comprising:
preparing a first region and a second region in a semiconductor substrate;
forming a first body region having a high concentration of dopant in the first region to form a high-threshold voltage device;
forming a second body region having a low concentration of dopant in the second region to form a low-threshold voltage device;
forming a gate electrode over the first body region and the second body region;
blanket implanting dopants of a second conductivity type into the first body and second body region to form low-doped drain
(LDD) regions;

forming a spacer next to the gate electrode; and
source-drain implanting a second conductivity type of dopant to form a low-resistance source/drain region and low-doped extension
that extends under the spacer,

wherein the source-drain implantation comprises tilted and rotated implantation, and
wherein the blanket implantation and the source-drain implantation are sufficient to compensate for enough of the first body
region of the high-threshold voltage device, to ensure a low-resistance link between the source/drain region and a channel
region.

US Pat. No. 9,716,171

SEMICONDUCTOR DEVICE

Magnachip Semiconductor, ...

1. A semiconductor device, comprising
a first gate insulator formed on a semiconductor substrate;
a second gate insulator formed on the semiconductor substrate, the second gate insulator being thicker than the first gate
insulator;

a first gate conductive layer formed on the first gate insulator;
a second gate conductive layer formed on the second gate insulator;
a first spacer, comprising a first bottom insulating layer, a first middle insulating layer overlying the first bottom insulating
layer, and a first upper insulating layer overlying the first middle insulating layer, the first spacer formed beside the
first gate conductive layer; and

a second spacer, comprising a second bottom insulating layer, a second middle insulating layer overlying the second bottom
insulating layer and a second upper insulating layer overlying the second middle insulating layer, the second spacer formed
beside the second gate conductive layer,

wherein a horizontal length of the first spacer in contact with a surface of the semiconductor substrate is different than
a horizontal length of the second spacer in contact with a surface of the semiconductor substrate,

wherein an end point of the second upper insulating layer is aligned with an end point of the second bottom insulating layer
and the second middle insulating layer, and

wherein a cross sectional area of the second upper insulating layer is larger than a cross sectional area of the first upper
insulating layer.

US Pat. No. 9,711,074

APPARATUS AND METHOD FOR PREVENTING IMAGE DISPLAY DEFECTS IN A DISPLAY DEVICE

MagnaChip Semiconductor, ...

1. An apparatus for preventing an abnormal screen display, comprising:
a separator configured to separate a clock signal and a data signal from a clock embedded signal;
a first latch that latches the data signal;
a lock detector that receives the clock signal and outputs a lock signal at a predetermined level after comparing an Nth clock
waveform and an N?1th clock waveform of the clock signal;

a control logic unit that selectively outputs a strobe signal based on the predetermined level of the lock signal;
a second latch that latches the data signal that is latched in the first latch based on the strobe signal; and,
an output section that outputs the data latched in the second latch as a panel driver signal.

US Pat. No. 9,692,404

POWER FACTOR CORRECTION CONTROLLING CIRCUIT AND DRIVING METHOD THEREOF

Magnachip Semiconductor, ...

1. A power factor correction controlling circuit comprising:
a control signal providing circuit configured to provide a control signal associated with a feedback signal;
a pulse width modulation signal controlling circuit configured to control a pulse width modulation signal based on one of
first and second bias signals; and

a power factor controlling circuit configured to provide a power factor control signal in response to an amplitude of the
pulse width modulation signal reaching an amplitude of the control signal,

wherein the control signal providing circuit is further configured to receive the feedback signal and compare the received
feedback signal with a predetermined reference voltage to generate the control signal.

US Pat. No. 9,992,845

LED DRIVER CIRCUIT AND LIGHT APPARATUS HAVING THE SAME IN

Magnachip Semiconductor, ...

1. A light apparatus using light-emitting diodes (LEDs), the light apparatus comprising:an LED array comprising LEDs operatively connected to one another in series;
an input unit configured to receive an alternating current (AC) power source signal;
a rectifier circuit configured to full-wave rectify the received AC power source signal and supply the full-wave rectified AC power source signal to the LED array;
a control circuit configured to selectively light the LEDs based on a voltage level of the full-wave rectified AC power source signal;
a converter configured to receive the full-wave rectified AC power source signal, output a direct current (DC) power source signal having a preset level, wherein the converter is further configured to convert the full-wave rectified AC power source signal into the direct current (DC) power source signal having the preset level, and at least one terminal of the converter is directly connected to a ground; and
a reference voltage generator configured to generate reference voltages having different voltage levels using the DC power source signal from the converter,
wherein the control circuit comprises
switching elements configured to selectively force nodes between the LEDs to be grounded,
comparators configured to turn-on one of the switching elements based on the voltage level of the full-wave rectified AC power source signal, and
resistors connected in series between the switching elements and the ground.

US Pat. No. 9,893,000

POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME

Magnachip Semiconductor, ...

1. A power semiconductor module, comprising:
a substrate comprising first, second, and third metal patterns separated from each other;
a semiconductor element located on the substrate;
a lead frame located on the substrate and comprising first, second, third, and fourth bodies;
a first terminal connected to the first body;
a second terminal connected to the second body; and
a third common terminal that connects the third body and the fourth body,
wherein a length of the third common terminal is longer than that of the first and second terminals, and
wherein the first terminal is electrically connected to a drain electrode of the semiconductor element, the second terminal
is electrically connected to a gate electrode of the semiconductor element, and the third common terminal is electrically
connected to a source electrode of the semiconductor element.

US Pat. No. 9,865,677

SUPER JUNCTION SEMICONDUCTOR DEVICE

Magnachip Semiconductor, ...

1. A super junction semiconductor device comprising:
a vertical pillar region located in an active region;
a first termination region and a second termination region located surrounding the active region;
first horizontal pillar regions located in the first termination region; and
second horizontal pillar regions located in the second termination region,
wherein the first horizontal pillar regions, the second horizontal pillar regions, and the vertical pillar region are connected,
and

wherein edges of the first horizontal pillar regions abut an epi layer.

US Pat. No. 9,825,537

PULSE-WIDTH MODULATION (PWM) CONTROLLING APPARATUS USING AUXILIARY WINDING VOLTAGE FOR FLYBACK CONVERTER

Magnachip Semiconductor, ...

1. A Pulse-Width Modulation (PWM) controlling apparatus, comprising:
a valley detector configured to detect a valley of an auxiliary winding voltage of a flyback converter;
an output voltage controller configured to output a first PWM control signal by performing averaging and sampling of the auxiliary
winding voltage;

an output current controller configured to output a second PWM control signal by performing an average current mode method
on a current signal (CS) voltage;

a latch configured to output a gate control signal in response to being supplied with a result of a logical OR operation of
the first PWM control signal output by the output voltage controller and the second PWM control signal output by the output
current controller, or being supplied with an output signal of the valley detector; and

a gate controller configured to perform a turning-on or turning-off operation of a first switch based on the gate control
signal.

US Pat. No. 9,825,137

SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING THE SAME

Magnachip Semiconductor, ...

1. A semiconductor element comprising:
a termination region outside an active region, the active region comprising trenches, wherein a center poly electrode is disposed
inside at least one of the trenches;

a transient region disposed between the active region and the termination region, the transient region comprising an inside
trench;

at least two gate poly electrodes are disposed adjacent to an upper portion of the center poly electrode;
a p-body region disposed between upper portions of the trenches;
a source region disposed at a side of the gate poly electrodes, wherein the source region is not disposed at the p-body region
shared with the gate poly electrode formed in the inside trench;

a channel stopper region disposed in the termination region, the channel stopper region including a via hole; and
an equipotential ring metal disposed over the channel stopper region, the equipotential ring metal electrically connecting
to the channel stopper region through the via hole included in the channel stopper region, wherein the via hole penetrates
the channel stopper region.

US Pat. No. 9,685,854

CHARGE PUMP APPARATUS AND CHARGE PUMPING METHOD

Magnachip Semiconductor, ...

1. A charge pumping method, comprising:
generating a first boosted voltage by boosting an input voltage by a first boosting mode with a charge pump circuit configured
to switch between a first configuration and a second configuration;

in response to receiving a signal to boost the input voltage by a second boosting mode, changing the level of a voltage charged
in at least one capacitor provided in the charge pump circuit in a configuration that differs from configurations of the charge
pump circuit in the first boosting mode and the second boosting mode, in preparation for a change to the second boosting mode;
and

generating a second boosted voltage by boosting the input voltage by the second boosting mode with the charge pump circuit
configured to switch between a third configuration and a fourth configuration.

US Pat. No. 9,653,034

COLUMN DATA DRIVING CIRCUIT INCLUDING A PRECHARGE UNIT, DISPLAY DEVICE WITH THE SAME, AND DRIVING METHOD THEREOF

Magnachip Semiconductor, ...

1. A column data driving circuit, comprising:
a precharge unit configured to
receive a plurality of preset signals and image data, the preset signals being adaptively established according to at least
a range of values of the image data, and

precharge a first set of column lines comprising a plurality of column lines based on one of the received plurality of preset
signals that corresponds to the received image data while never precharging a second set of column lines; and

a driving unit configured to
receive a data signal corresponding to the image data,
drive the second set of column lines during the precharging of the first set of column lines in response to the data signal,
and

sequentially drive the precharged first set of column lines in response to the data signal,
wherein the precharging of the first set of column lines and the driving of the second set of column lines occur substantially
simultaneously at each horizontal duration, wherein a column line, which is first driven through the driving unit is not precharged
by the precharge unit,

wherein the column data driving circuit is configured to simultaneously pulse (i) a first control signal from the driving
unit to drive the second set of column lines and (ii) a second control signal from the precharge unit to precharge the first
set of column lines.

US Pat. No. 10,267,649

METHOD AND APPARATUS FOR CALCULATING AZIMUTH

MagnaChip Semiconductor, ...

1. An apparatus comprising:a magnetic sensor configured to sense a magnetic field and convert the sensed magnetic field into a voltage;
an amplifier configured to amplify the voltage;
an analog-to-digital converter configured to convert the amplified voltage into voltage data; and
a processor configured to execute instructions stored in a memory, thereby configuring the processor to:
separate the voltage data into 3-axis magnetic field components in X, Y and Z axes to generate separated voltage data;
remove noise components of the separated voltage data by creating a median value of the separated voltage data and filtering the separated voltage data by selecting midmost voltage data;
apply a previously calculated offset to the filtered separated voltage data;
determine, based on the application of the previously calculated offset, whether the filtered separated voltage data correspond to a geomagnetic field;
selectively, based on a result of the determining of whether the filtered separated voltage data correspond to the geomagnetic field,
select offset data items from the filtered separated voltage data,
subtract a difference between the filtered separated voltage data and previously measured voltage data from a previous offset reference point,
set a resultant value as a new offset reference point, in response to the filtered separated voltage data being determined not to correspond to the geomagnetic field and the previously measured voltage data being determined to correspond to the geomagnetic field, and
calculate an offset by a geometrical method that uses the selected offset data items and the new offset reference point; and
determine a location or directional information of the apparatus based on the voltage data for the sensed magnetic field and selectively one of the calculated offset and the previously calculated offset, with increased location or directional determination speed and/or accuracy with respect to a presence of an abnormal magnetic field.

US Pat. No. 9,705,010

SCHOTTKY DIODE HAVING FLOATING GUARD RINGS

Magnachip Semiconductor, ...

1. A Schottky diode having a floating guard ring comprising:
a deep well of a first conductivity type formed in a substrate;
a first guard ring of a second conductivity type in a non-floating state formed to surround a center region of the deep well;
a second guard ring of a second conductivity type in a floating state formed in an outer region of the first guard ring to
surround the first guard ring;

a first well region of a first conductivity type formed in an outer region of the second guard ring to surround the second
guard ring;

element isolation layers formed on the region between the first guard ring and the second guard ring, and the region between
the second guard ring and the first well region;

an anode electrode formed on the substrate and electrically connected to the deep well and the first guard ring;
a cathode electrode formed on the substrate and electrically connected to the first well region; and
an additional element isolation layer formed between the second guard ring and the cathode electrode.

US Pat. No. 9,693,406

CIRCUIT FOR DRIVING AC DIRECT LIGHTING APPARATUS AND METHOD THEREFOR

Magnachip Semiconductor, ...

1. A circuit for driving an alternating current (AC) direct lighting apparatus, comprising:
a triac dimmer configured to control a brightness of a light emitting diode (LED) module;
a charger configured to be charged during a turn-off period of the triac dimmer;
a reference voltage generator configured to generate a reference voltage based on a voltage charged in the charger during
a first turn-off period of the triac dimmer and a voltage charged in the charger during a second turn-off period; and

a driving signal output circuit configured to output a driving signal of the LED module in response to a voltage charged in
a third turn-off period of the triac dimmer reaching the generated reference voltage.

US Pat. No. 9,984,755

ONE-TIME PROGRAMMABLE (OTP) MEMORY DEVICE

Magnachip Semiconductor, ...

1. An OTP memory device, comprising:an OTP cell array comprising OTP memory cells driven by an external supply voltage, the OTP memory cells comprising bit lines arrayed in rows and columns;
data input units respectively connected to the rows of the OTP memory cells and configured to select one of the rows of the OTP memory cells to which the supply voltage is to be applied;
a column decoder connected to each column of the OTP memory cells and configured to select one of the columns of the OTP memory cells to which the supply voltage is to be applied; and
a detection amplifier connected to the bit line and configured to perform a read operation of the OTP memory cells.

US Pat. No. 9,788,372

GATE OFF DELAY COMPENSATION CIRCUIT AND LIGHT APPARATUS HAVING THE SAME

Magnachip Semiconductor, ...

1. A gate off delay compensation circuit, comprising:
a sensing interval determiner configured to determine an interval in which a driving voltage corresponds to a first level
and second level of a reference voltage as a driving voltage sensing interval;

a driving voltage excess interval determiner configured to determine a driving voltage excess interval defined as an interval
in which the driving voltage is larger than the reference voltage; and

a driving voltage period determiner configured to determine a period of the driving voltage based on the driving voltage sensing
interval and the driving voltage excess interval.

US Pat. No. 9,780,650

CURRENT COMPENSATION CIRCUIT AND LIGHT APPARATUS COMPRISING THE SAME

Magnachip Semiconductor, ...

1. A current compensation circuit, comprising:
a current compensator configured to measure a compensation time in which a sensing voltage generated by a driving current
passing through a driving switching element drops below a first certain voltage in response to the driving switching element
being turned on and configured to delay a turn-off point of the driving switching element from a point at which the sensing
voltage reaches a second certain voltage during the measured compensation time; and

a switching controller configured to provide a switching control signal at a turn-off point of the delayed driving switching
element.

US Pat. No. 9,721,833

SEMICONDUCTOR DEVICE WITH VOIDS WITHIN SILICON-ON-INSULATOR (SOI) STRUCTURE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE

Magnachip Semiconductor, ...

1. A method of forming a semiconductor device with a void within a silicon-on-insulator (SOI) structure, the method comprising:
forming a silicon-on-insulator (SOI) substrate comprising
a semiconductor substrate,
an insulating layer on the semiconductor substrate, and
a semiconductor layer;
forming an opening of the semiconductor layer;
performing an isotropic etch process to form a void in the insulating layer; and
sealing the opening of the semiconductor layer.

US Pat. No. 9,721,941

SEMICONDUCTOR DEVICE IN A LEVEL SHIFTER WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT AND SEMICONDUCTOR CHIP

Magnachip Semiconductor, ...

1. A semiconductor chip comprising:
a first input pad and a first ground pad located in a low voltage region on a semiconductor substrate;
a second input pad, and a second ground pad located in a high voltage region on the semiconductor substrate;
a first electrostatic discharge (ESD) clamp formed between the first input pad and the first ground pad; and
a level shifter comprising a semiconductor device and an ESD stress blocking region,
wherein the semiconductor device comprises a gate insulation layer having a thin gate insulation layer portion and a thick
gate insulation layer portion, and a gate electrode formed over the gate insulation layer, and

wherein the ESD stress blocking region is electrically connected between the low voltage region and the gate electrode.

US Pat. No. 9,916,796

LIQUID CRYSTAL DISPLAY DEVICE WITH REPAIR FUNCTION AND REPAIR TYPE DATA FORMAT STRUCTURE

Magnachip Semiconductor, ...

1. A liquid crystal display device comprising:
a liquid crystal display and a display drive Integrated Circuit (IC);
a first input terminal and second input terminal located on the display drive IC;
a first repair amplifier connected to the first input terminal and a second repair amplifier connected to the second input
terminal and located on the display drive IC, wherein the first repair amplifier and second repair amplifier are formed on
a left side and a right side of the display drive IC, respectively; and

repair lines connected to respective output terminals of the first repair amplifier and the second repair amplifier, wherein
a liquid crystal line or pixel of the liquid crystal display is repaired using one of the repair lines.

US Pat. No. 9,905,185

SWITCHED COLUMN DRIVER OF DISPLAY DEVICE

Magnachip Semiconductor, ...

1. A column driver of a display device, comprising:
an upper output buffer configured to be driven between a first voltage rail and a second voltage rail, and output a first
output signal in response to a first input signal and a second input signal;

a bottom output buffer configured to be driven between the second voltage rail and a third voltage rail, and output a second
output signal in response to a third input signal and a fourth input signal;

a first switch group configured to selectively provide the first to the fourth input signals for a first or a second input
terminal of each of the upper output buffer and the bottom output buffer;

a second switch group configured to feed back the first and the second output signals to the first or the second input terminal
of each of the upper output buffer and the bottom output buffer; and

a third switch group configured to selectively provide the first output signal and the second output signal to a first panel
and a second panel,

wherein upon both the first switch group and the second switch group being driven by either the first voltage rail or the
second voltage rail, the third switch group is configured to be driven only by the first voltage rail.

US Pat. No. 9,871,063

DISPLAY DRIVER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Magnachip Semiconductor, ...

1. A method for manufacturing a display driver semiconductor device, comprising:
forming a plurality of trench isolating regions on a substrate defining a first region, a second region, and a third region;
forming a high voltage well region on the substrate;
forming a pair of low-concentration drift regions inside the high voltage well region on the second and third regions, respectively;
forming a low voltage well region inside the high voltage well region on the first region;
depositing a chemical vapor deposition (CVD) insulating layer through the first, second, and third regions of the substrate;
patterning the CVD insulating layer to remove the CVD insulating layer on the first region and the second region;
forming a first thermal oxide layer, a second thermal oxide layer, and a third thermal oxide layer on the first, second, and
the third regions, respectively;

removing the first thermal oxide layer by patterning and respectively forming a second gate insulating layer and a third gate
insulating layer on the second and the third regions;

forming a first gate insulating layer on the first region by forming the second thermal oxide layer on the first region; and
forming a first gate electrode, a second gate electrode, and a third gate electrode on the first, second, and the third regions,
respectively, by depositing and patterning a conductive material on the substrate.

US Pat. No. 9,742,456

METHOD OF SENSING FLIP COVER

Magnachip Semiconductor, ...

1. A method of sensing a flip cover coupled to an electronic device having a processor, comprising:
collecting, with the processor, a magnetic field intensity generated between a magnet of the flip cover and a Hall sensor
in the electronic device, the Hall sensor being configured to be covered by the flip cover; and

determining, with the processor, an opening angle of the flip cover, wherein the electronic device is responsive to the angle
of the flip cover,

wherein the determining the opening angle of the flip cover further comprises:
calculating an arithmetic mean value of the magnetic field intensity being collected;
calculating an angle weight based on the arithmetic mean value; and
determining the opening angle based on the calculated angle weight, and
wherein the opening angle is obtained by using a logarithmic function, and
wherein the opening angle is determined by the following:
Y=log a(Intensity N)

a=Exp [{Ln(Intensity 90)}/90],

wherein Y denotes an opening angle of the flip cover;
Intensity N denotes an angle weight at an N degree;
a denotes a base of the logarithmic function;
Exp denotes an exponential function; and
Ln denotes a natural logarithmic function.

US Pat. No. 9,767,749

SWITCHED COLUMN DRIVER OF DISPLAY DEVICE

Magnachip Semiconductor, ...

1. A column driver of a display device, comprising:
an upper output buffer configured to be driven between a first voltage rail and a second voltage rail, and output a first
output signal in response to a first input signal and a second input signal;

a bottom output buffer configured to be driven between the second voltage rail and a third voltage rail, and output a second
output signal in response to a third input signal and a fourth input signal;

a first switch group configured to selectively provide the first to the fourth input signals for a first or a second input
terminal of each of the upper output buffer and the bottom output buffer;

a second switch group configured to feed back the first and the second output signals to the first or the second input terminal
of each of the upper output buffer and the bottom output buffer; and

a third switch group configured to selectively provide the first output signal and the second output signal to a first panel
and a second panel,

wherein the third switch group is configured to be driven by the first voltage rail,
wherein in response to switches of the first switch group being provided with the high power voltage of the first voltage
rail,

switches of the second switch group are provided with the high power voltage of the first voltage rail, or
a first set of switches of the second switch group are provided with the high power voltage of the first voltage rail and
a second set of switches of the second switch group are provided with the half power voltage of the second voltage rail, or

switches of the second switch group are provided with the half power voltage of the second voltage rail.

US Pat. No. 9,753,002

HUMIDITY SENSOR WITH VOID WITHIN INTERCONNECT AND METHOD OF MANUFACTURING THE SAME

Magnachip Semiconductor, ...

18. A humidity sensor comprising:
a first insulating layer disposed on a substrate;
interconnect conductors disposed on the first interlayer insulating layer;
an etch stop layer contacts the first interlayer insulating layer and a portion of the interconnect conductors;
a second insulating layer disposed on the etch stop layer;
voids formed within the second insulating layer; and
a humidity sensing material deposited in the voids.

US Pat. No. 9,704,975

METHOD OF MANUFACTURING NON VOLATILE MEMORY DEVICE

Magnachip Semiconductor, ...

1. A non-volatile memory device, comprising:
a semiconductor substrate;
a well region of a first conductivity type situated on the semiconductor substrate;
dopant implanted into an ion implantation area, the ion implantation area situated in the well region;
a floating gate situated on the well region;
a control gate situated on both sides of the floating gate;
a tunnel oxide film situated between the floating gate and the ion implantation area;
a dielectric film situated between the floating gate and the control gate, wherein the dielectric film is formed to be in
contact with a sidewall of the floating gate and a sidewall of the tunnel oxide film; and

a gate insulator film disposed between the control gate and the ion implantation area, wherein a thickness of the gate insulator
film is smaller than a thickness of the dielectric film.

US Pat. No. 10,115,720

INTEGRATED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Magnachip Semiconductor, ...

10. A manufacturing method for a semiconductor device, the method comprising:providing a substrate comprising a first region and a second region;
forming a thick gate insulating layer on the first region;
forming a gate electrode on the thick gate insulating layer;
performing a wet etching process on the thick gate insulating layer disposed outside the gate electrode such that a thin buffer insulating layer is formed adjacent to the thick gate insulating layer, located outside of the gate electrode;
performing a sidewall oxidation of the gate electrode:
forming an LDD region in the substrate; and
forming a first spacer on the thin buffer insulating layer.

US Pat. No. 9,893,099

PHOTO SENSOR MODULE

Magnachip Semiconductor, ...

1. A photo sensor module, comprising:
a semiconductor substrate;
a field oxide layer, formed on the semiconductor substrate;
a passive device, placed on the field oxide layer;
at least one insulator film laminated on the field oxide layer; and
a photo diode formed on the at least one insulator film above the passive device.

US Pat. No. 9,887,621

POWER FACTOR CORRECTION CIRCUIT AND METHOD FOR CORRECTING POWER FACTOR, CONVERTER DEVICE THEREOF

Magnachip Semiconductor, ...

1. A power factor correction circuit comprising:
a sensor configured to sense a sensing voltage on the basis of a value of a current flowing into a power switch that is configured
to adjust an output voltage in accordance with an input voltage obtained by wave-rectifying an alternating current (AC) power;
and

a power factor correction controller configured to receive a reference signal and the sensing voltage and to output a gate-on
signal to turn on and to turn off the power switch, wherein the reference signal is generated by a reference signal generator
configured to receive the sensing voltage and to generate a reference signal.

US Pat. No. 9,825,634

LEVEL SHIFTING CIRCUIT AND METHOD FOR THE SAME

MagnaChip Semiconductor, ...

1. A level shifting circuit, comprising:
a transistor output unit that receives a first power supply signal, converts the first power supply signal to a second power
supply signal having a different level from the first power supply signal to an output terminal, and outputs the second power
supply signal; and

a current provision unit comprising a current mirror that generates a first current based on an input pulse signal to provide
the first current to the output terminal of the transistor output unit when the first power supply signal is inputted to the
transistor output unit, to shorten a prolonged portion of the second power supply signal.

US Pat. No. 10,062,447

POWER SWITCH CIRCUIT

MagnaChip Semiconductor, ...

1. A power switch circuit, comprising:a first level shifter that, in response to execution of a programming operation of a one-time programmable (OTP) memory cell array, turns on a first switching device that has received a supply voltage from an external supply voltage pad;
a second level shifter that, in response to execution of the programming operation, turns on a second switching device connected to the first switching device, to provide the supply voltage to the OTP memory cell array, wherein the second level shifter receives a deep sleep mode input signal in the deep sleep mode to output a constant rated voltage; and
a third level shifter that, in response to execution of a read operation of the OTP memory cell array, turns on a third switching device to provide a power voltage, which is internally generated within the power switch circuit, to the OTP memory cell array.

US Pat. No. 9,882,043

SEMICONDUCTOR DEVICE WITH TRENCH TERMINATION STRUCTURE

Magnachip Semiconductor, ...

1. A semiconductor device comprising:
a gate pad area in which a gate pad is formed on a substrate, wherein the gate pad is configured to receive a bias voltage;
an active area in which active trenches are formed in the substrate;
an isolation area comprising an isolation trench in the substrate between the gate pad area and the active area; and
a section of the active area adjacent to the gate pad where a P-body is not formed.

US Pat. No. 9,875,697

PARALLEL CONSTANT CURRENT LED DRIVING UNITS FOR DRIVING A LED STRING AND METHOD OF PERFORMING THE SAME

Magnachip Semiconductor, ...

1. A Light Emitting Diode (LED) driver apparatus, comprising:
a DC-DC converter supplying a driving voltage to an LED array;
two or more LED drivers comprising corresponding resistances driving the LED array responsive to a dimming signal, each LED
driver comprising a switching unit and a grounded corresponding resistance, each switching unit being directly connected to
another LED driver in parallel through a shared node, and each LED driver being configured to supply a corresponding constant
current to the LED array dependent on the dimming signal and the corresponding resistance; and

a controller providing respective enable signals, each generated by an AND logic circuit based on the dimming signal and a
corresponding control signal, to the two or more LED drivers to selectively operate each of the two or more LED drivers,

wherein the LED drivers provide a sum of the corresponding constant currents to the LED array through the shared node, and
wherein two or more of the corresponding resistances are different.

US Pat. No. 9,859,365

HIGH VOLTAGE DEVICE AND METHOD FOR FABRICATING THE SAME

Magnachip Semiconductor, ...

1. A method for fabricating a high voltage device, the method comprising:
forming a well region in a substrate;
forming a trench structure by etching a portion of the well region;
filling the trench structure with an insulation layer;
performing a planarization process on the insulation layer to form isolation regions in the well region;
forming substantially simultaneously drift regions in the well region through a first ion implantation process, two of the
drift regions disposed on opposing sides of one isolation region among the isolation regions and being isolated by the one
isolation region, and the drift regions having a different conduction type from the well region and having a depth less than
that of the isolation regions; and

forming a first gate electrode over the well region and a portion of one of the two drift regions but not a portion of the
other of the two drift regions,

wherein a second gate electrode is not formed over the other of the two drift regions.

US Pat. No. 9,780,653

DC-DC CONVERTER

Magnachip Semiconductor, ...

1. A DC-DC converter, comprising:
a comparator configured to compare a reference voltage to a feedback voltage;
a constant on-time (COT) generator configured to output an on-time signal of a power switch, in response to a result of the
comparison at the comparator;

a first switch and a second switch each configured to turn on for a predetermined time interval, according to the on-time
signal;

an inductor connected in series to a common terminal of the first and second switches;
a first feedback resistor and a second feedback resistor connected between the inductor and a load resistor; and
a coupling network comprising a coupling resistor, the coupling network configured to receive the on-time signal through the
coupling resistor and a feedback output voltage of the inductor, sum the received voltages, and output the result of summing
as a first feedback voltage,

wherein the first feedback voltage and a second feedback voltage outputted via the first feedback resistor and the second
feedback resistor are directly provided as the feedback voltage of the comparator.

US Pat. No. 10,109,731

POWER MOSFET AND METHOD FOR MANUFACTURING THE SAME

Magnachip Semiconductor, ...

15. A method for manufacturing a power MOSFET, the method comprising:forming a first conductivity type doping layer doped with first conductivity type impurities at a depth on a top of a second conductivity type body situated on a top of a first conductivity type epitaxial layer;
forming a gate electrode penetrating the first conductivity type doping layer and the second conductivity type body;
forming an insulating layer on a top of the first conductivity type doping layer;
etching the insulating layer so that the first conductivity type doping layer maintains the depth; and
forming a source electrode at a partial region of the etched insulating layer,
wherein the insulating layer is directly in contact with the first conductivity type epitaxial layer, the second conductivity type body, and the first conductivity type doping layer.

US Pat. No. 9,922,865

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Magnachip Semiconductor, ...

1. A method of manufacturing a semiconductor device, comprising:
forming a second conductivity type buried layer in a substrate,
forming a first well region of a second conductivity type and a second well region of a second conductivity type in the substrate;
forming a low dopant density well region of a second conductivity type disposed between the first well region of a second
conductivity type and the second well region of a second conductivity type,

wherein the low dopant density well region has a dopant density lower than that of the first well region and second well region;
forming a first conductivity type body region in the low dopant density well region of a second conductivity type;
forming a first gate electrode and a second gate electrode on the substrate;
forming a second conductivity type source region in contact with the first conductivity type body region;
forming a deep trench in the substrate;
forming a sidewall insulating film on a side surface of the deep trench and on the substrate;
etching back the sidewall insulating film formed on the substrate; and
depositing an interlayer insulating film on the substrate and on the sidewall insulating film to form an air gap within the
deep trench,

wherein both the first gate electrode and the second gate electrode overlap with the first conductivity type body region,
and

wherein the low dopant density well region of a second conductivity type is formed by diffusion of impurities in the first
well region of a second conductivity type and the second well region of a second conductivity type.

US Pat. No. 10,103,221

POWER SEMICONDUCTOR DEVICE

Magnachip Semiconductor, ...

1. A power semiconductor device comprising:a substrate having a first surface and a second surface opposite to the first surface;
a drift region having a first conductivity type;
an emitter electrode located on the first surface of the substrate;
a drain electrode located on the second surface of the substrate;
an emitter contact region in contact with the emitter electrode;
a base region of a second conductivity type between the emitter contact region and the drift region;
an electrically floating region of the substrate having an impurity concentration lower than an impurity concentration of the base region; and
a trench structure comprising a plurality of walls enclosing the electrically floating region of the substrate,
wherein the walls extend from the first surface of the substrate toward the drift region and separate the emitter contact region from the electrically floating region,
wherein the emitter contact region surrounds the trench structure, and
wherein the electrically floating region covers an end surface of each of the walls of the trench structure and prevents contact of the end surfaces with the drift region.

US Pat. No. 9,899,100

ONE TIME PROGRAMMABLE (OTP) CELL AND AN OTP MEMORY ARRAY USING THE SAME

Magnachip Semiconductor, ...

1. An anti-fuse device, comprising:
a gate insulating film formed on a semiconductor substrate;
a gate electrode formed on the gate insulating film; and
a salicide layer formed on a first portion of the gate electrode such that a second portion of the gate electrode omits the
salicide layer, wherein a hard breakdown of at least a portion of the gate insulating film occurs at a time of programming
the anti-fuse device.

US Pat. No. 10,243,558

COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) INVERTER CIRCUIT DEVICE

MagnaChip Semiconductor, ...

1. A CMOS inverter circuit device, comprising:a first P-type metal-oxide-semiconductor (PMOS) transistor and a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second PMOS transistor and a second NMOS transistor configured to:
each receive an identical input signal through a gate terminal, and
be connected in series respectively;
a third PMOS transistor connected to a first node connected with drains of the first PMOS transistor and the first NMOS transistor;
a third NMOS transistor connected to a second node connected with drains of the second PMOS transistor and the second NMOS transistor; and
a delay circuit unit comprising:
a fourth PMOS transistor and a fourth NMOS transistor configured to:
each receive the input signal through a respective gate, and
be connected in series in order for a fifth node connected with drains of the fourth PMOS transistor and the fourth NMOS transistor to be connected to a fourth node connected with a source of the first NMOS transistor and a source of the second PMOS transistor,
wherein respective channel lengths of the first and second NMOS transistors are identical to each other such that the first and second NMOS transistors are turned on or off simultaneously, and
wherein the fourth PMOS and fourth NMOS transistors of the delay circuit unit have channel lengths greater than channel lengths of the first, second, and third PMOS and NMOS transistors.

US Pat. No. 10,096,707

SEMICONDUCTOR STRUCTURE HAVING A JUNCTION FIELD EFFECT TRANSISTOR AND A HIGH VOLTAGE TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

Magnachip Semiconductor, ...

1. A method for forming a semiconductor device, the method comprising:providing a substrate;
forming a first deep well region of a first conductivity type in a first portion of the substrate;
forming a second deep well region of the first conductivity type in a second portion of the substrate, the first and second deep well regions being formed with an identical doping concentration and doping depth;
forming a deep diffusion region of the first conductivity type in the substrate between the first deep well region and the second deep well region;
forming a third well region of a second conductivity type in the deep diffusion region, the third well region being a gate region of a junction field effect transistor (JFET) and configured to control a pinch off voltage of the JFET;
forming an insulation layer on a top surface of the substrate;
forming a buried impurity layer of the second conductivity type in the first and second deep well regions, the buried impurity layer being in electrical contact with the third well region;
forming a drain region in the first portion of the substrate; and
forming a source region in the second portion of the substrate, the source region and the drain region being of the first conductivity type.

US Pat. No. 10,003,013

SEMICONDUCTOR DEVICE HAVING CIRCUITRY POSITIONED ABOVE A BURIED MAGNETIC SENSOR

Magnachip Semiconductor, ...

1. A semiconductor device comprising:a circuitry formed on a silicon substrate; and
a magnetic sensor having a sensing area formed under the circuitry,
wherein the sensing area comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area to the circuitry, and
wherein the P-doped area is discretely formed in the silicon substrate and has a higher doping concentration than that of the silicon substrate, and the P-doped area is different from the silicon substrate.

US Pat. No. 9,859,168

METHOD OF FABRICATING DMOS AND CMOS TRANSISTORS

Magnachip Semiconductor, ...

1. A method of fabricating a semiconductor device comprising a diffused metal-oxide-semiconductor (DMOS) transistor, an n-type
metal-oxide-semiconductor (NMOS) transistor, and a p-type metal-oxide-semiconductor (PMOS) transistor, the method comprising:
forming separation regions in a semiconductor substrate, the separation regions isolating a DMOS transistor area in which
to form the DMOS transistor, an NMOS transistor area in which to form the NMOS transistor, and a PMOS transistor area in which
to form the PMOS transistor from one another, and the DMOS transistor area comprising a source zone and a drain zone;

forming a gate insulating film between the source zone and the drain zone;
forming a DMOS gate electrode on the gate insulating film;
forming a first mask pattern on the semiconductor substrate to expose the drain zone and a second portion of the DMOS gate
electrode adjacent to the drain zone;

performing a first ion implantation process into the exposed second portion of the DMOS gate electrode and the semiconductor
substrate to form n-type well (NWELL) regions in the drain zone and the PMOS transistor area, respectively;

forming a second mask pattern on the semiconductor substrate to expose the source zone and a first portion of the DMOS gate
electrode adjacent to the source zone;

performing a second ion implantation process into the exposed first portion of the DMOS gate electrode and the semiconductor
substrate to form p-type well (PWELL) regions in the source zone and the NMOS transistor area, respectively;

forming a third mask pattern on the semiconductor substrate and performing a third ion implantation process into the semiconductor
substrate to form a high concentration drain region and a high concentration source region in the NWELL region in the drain
zone and the PWELL region in the source zone, respectively; and

forming a fourth mask pattern on the semiconductor substrate and performing a fourth ion implantation process into the semiconductor
substrate to form a well tab region in the PWELL region in the DMOS transistor area.

US Pat. No. 10,103,260

SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW RDSON AND MANUFACTURING METHOD THEREOF

Magnachip Semiconductor, ...

1. A semiconductor device comprising:a first P-type well region and a second P-type well region, asymmetric to the first P-type well region, each formed in a semiconductor substrate;
a gate insulating layer and a gate electrode formed on the substrate;
a first N-type source/drain region and a second N-type source/drain region formed on respective sides of the gate electrode; and
a N-type lightly diffused drain (LDD) region formed asymmetrically with respect to the gate electrode and extending from the second N-type source/drain region,
wherein the second P-type well region encompasses the second N-type source/drain region and the N-type LDD region, and
wherein the first N-type source/drain region contacts both the second P-type well region and a region of the substrate adjacent to the second P-type well region.

US Pat. No. 10,082,576

OPTICAL SENSOR SENSING ILLUMINANCE AND PROXIMITY

Magnachip Semiconductor, ...

1. An optical sensor comprising:a first photodiode, wherein only a visible light filter is arranged on the first photodiode;
a second photodiode, wherein only an infrared blocking filter is arranged on the second photodiode; and
a third photodiode, wherein the third photodiode has no filters arranged thereon,
wherein the optical sensor performs a first difference operation between second and third measured values measured through the second and third photodiodes, respectively, to measure a distance of an object and performs a second difference operation between a result of the first difference operation and a first measured value measured through the first photodiode to measure an illuminance of a specific wavelength.

US Pat. No. 10,256,396

MAGNETIC SENSOR AND METHOD OF FABRICATING THE SAME

MagnaChip Semiconductor, ...

1. A method of fabricating a magnetic sensor, the method comprising:forming hall elements;
forming a protection layer comprising a thin portion having a first thickness and comprising a thick portion having a second thickness that forms a protrusion that protrudes upward from an upper surface of the protection layer;
forming a seed layer disposed above the hall elements; and
forming an integrated magnetic concentrator (IMC) disposed above the hall elements and the seed layer, the IMC comprising an elevated portion protruding upward from an upper surface of the IMC, and the elevated portion overlapping with the protrusion of the protection layer.

US Pat. No. 10,290,501

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

MagnaChip Semiconductor, ...

1. A semiconductor device, comprising:a substrate comprising a WELL region;
a gate electrode comprising a gate length region disposed on a surface of the WELL region, wherein an entire lower surface of the gate length region spans opposing side ends of the gate electrode, and the entire lower surface of the gate length region is planar;
a source region and a drain region in the WELL region;
a first drift region in the WELL region overlapping the gate length region by an overlapping length;
a second drift region in the WELL region overlapping the gate length region; and
a third drift region spaced apart from the second drift region by an isolation layer,
wherein a depth of the third drift region is the same depth as a depth of the second drift region, and
wherein the first drift region partially encloses the source region and the second drift region partially encloses the drain region.

US Pat. No. 10,116,305

SEMICONDUCTOR DEVICE FOR DISPLAY DRIVER IC STRUCTURE

Magnachip Semiconductor, ...

1. A semiconductor device, comprising:a first transistor, a second transistor, and a third transistor formed on a semiconductor substrate, wherein
the first transistor comprises
a first gate insulator having a first thickness,
a first source region and a first drain region,
a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and
a first gate electrode,
the second transistor comprises
a second gate insulator having a second thickness that is thinner than the first thickness,
a second source region and a second drain region,
a pair of drift regions that encompass the second source region and the second drain region respectively, and
a second gate electrode, and
the third transistor comprises
a third gate insulator having the first thickness,
a third source region and a third drain region, and
a pair of drift regions that encompass the third source region and the third drain region respectively, and
a third gate electrode.

US Pat. No. 10,082,910

GESTURE CELL AND GESTURE SENSOR HAVING A PHOTODIODE COMPRISING A FIRST LAYER FORMED AS A SERPENTINE ELEMENT ON A SUBSTRATE

Magnachip Semiconductor, ...

1. A gesture cell comprising:a photodiode comprising a first layer, the first layer formed as a serpentine element on a substrate; and
an optical blind configured to guide a light that is incident from a first direction on the photodiode, the optical blind being placed on the photodiode obliquely toward the first direction,
wherein the serpentine element is continuously formed from multiple limbs positioned in the first directions and returning in a corresponding second direction, and each limb positioned in the first direction and the corresponding limb returning in the second direction are equally spaced apart.

US Pat. No. 10,008,508

ONE TIME PROGRAMMABLE (OTP) CELL HAVING IMPROVED PROGRAMMING RELIABILITY

Magnachip Semiconductor, ...

1. A non-volatile semiconductor storage device, comprising:a gate insulating film formed on a semiconductor substrate;
a gate electrode formed on the gate insulating film;
first and second spaced apart doped regions formed below the gate insulating film and the gate electrode in the semiconductor substrate,
wherein a grounded region of the first and second spaced apart doped regions is grounded via a contact; and
a well tap region formed adjacent to the first spaced apart doped region or the second spaced apart doped region in the semiconductor substrate, wherein the well tap region is grounded via a second contact.

US Pat. No. 9,991,192

SEMICONDUCTOR PACKAGE

Magnachip Semiconductor, ...

1. A semiconductor package, comprising:a first die comprising a low-side lateral double diffused metal oxide semiconductor (LDMOS);
a second die disposed above the first die;
a high-side LDMOS formed in the second die as a flip chip; and
a connection unit disposed between the first die and the second die,
wherein the second die comprises an electrode on a bottom thereof, with no electrode disposed on a top surface of the second die.

US Pat. No. 10,176,884

SENSE AMPLIFIER DRIVING DEVICE

MagnaChip Semiconductor, ...

1. A semiconductor memory device, comprising,a memory cell;
a bit line connected to the memory cell; and
a sense amplifier that is connected to the bit line, receives a first control signal, and detects and amplifies a bit line signal of the bit line, the sense amplifier comprising:
a precharge device that is turned on or turned off based on a read control signal; and
a transistor output unit that outputs an output voltage based on the bit line signal when the precharge device is turned off.

US Pat. No. 10,096,700

POWER SEMICONDUCTOR DEVICE COMPRISING TRENCH STRUCTURES

Magnachip Semiconductor, ...

1. A power semiconductor device, comprising:a semiconductor substrate;
trench structures comprising a first, a second, a third and a fourth trench structure formed in the substrate;
a second conductivity type body region formed between the trench structures;
a first conductivity type source region formed in the second conductivity type body region; and
an emitter electrode and a gate pad formed over the substrate,
wherein each trench structure comprises a top electrode and a bottom electrode, and each top electrode is insulated from a corresponding bottom electrode, and
wherein the first trench structure is symmetric to the fourth trench structure, and the second trench structure is symmetric to the third trench structure, and
wherein the first conductivity type source region is formed to be adjacent to the first trench structure and the fourth trench structure.

US Pat. No. 10,068,892

SEMICONDUCTOR DEVICE IN A LEVEL SHIFTER WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT AND SEMICONDUCTOR CHIP

Magnachip Semiconductor, ...

1. A semiconductor device in a level shifter, comprising:a gate insulating layer comprising a thin gate insulation layer and a thick gate insulation layer formed on a substrate;
a gate electrode formed on the thin gate insulation layer and on the thick gate insulation layer;
a non-silicide region, a silicide region, and a gate contact region formed on the gate electrode;
wherein the gate contact region does not overlap the thick gate insulation layer.

US Pat. No. 10,199,214

INSULATOR, CAPACITOR WITH THE SAME AND FABRICATION METHOD THEREOF, AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

MagnaChip Semiconductor, ...

1. A method for fabricating a capacitor, comprising:forming a first electrode;
forming an insulator having a laminate structure in which aluminum oxide (Al2O3) layers and hafnium oxide (HfO2) layers are laminated on the first electrode alternately in an iterative manner; and
forming a second electrode on the insulator,
wherein a portion of the laminate structure disposed on the first electrode outside the second electrode has a thickness that is less than or equal to a half of a total thickness of the laminate structure covered with the second electrode, and
wherein the insulator having the laminate structure is formed in the same chamber by an in-situ process in its entirety.

US Pat. No. 10,180,467

APPARATUS FOR TESTING MAGNETIC FIELD SENSOR ON WAFER AND METHOD THEREOF

Magnachip Semiconductor, ...

1. A method for testing a magnetic field sensor on a wafer, the method comprising:arranging the magnetic field sensor inside a magnetic field of a coil having a radial direction parallel to a surface of the wafer,
wherein the magnetic field sensor is arranged away from a center point of the coil by a distance,
wherein the coil has a cross-sectional area smaller than a cross-sectional area of the wafer, and
wherein the coil is configured to apply a three-axis magnetic field to the magnetic field sensor, and the distance corresponds to a distance between the coil and the wafer such that the magnetic field sensor contacts magnetic field lines generated from the three-axis magnetic field having an incident angle of approximately 45 degrees between a Z axis and an XY coordinate plane, at a point at which the magnetic field lines meet the surface of the wafer; and
detecting the three-axis magnetic field applied to the magnetic field sensor,
wherein the coil is a single coil used in applying the three-axis magnetic field to the magnetic field sensor, and
wherein in response to the three-axis magnetic field applied to the magnetic field sensor being separated into X, Y, and Z axis components, the X, Y, and Z axis components have similar values.

US Pat. No. 10,347,565

MULTI-CHIP PACKAGE OF POWER SEMICONDUCTOR

MagnaChip Semiconductor, ...

1. A multi-chip package of power semiconductor, comprising:a lead frame comprising:
a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other; and
a second segment group having a second gate segment, a second source segment, and a second drain segment that are separated from each other;
a first power semiconductor chip formed on the first segment group; and
a second power semiconductor chip formed on the second segment group, wherein the first source segment is physically connected to the second drain segment.

US Pat. No. 10,109,705

ULTRAHIGH VOLTAGE RESISTOR, SEMICONDUCTOR DEVICE, AND THE MANUFACTURING METHOD THEREOF

Magnachip Semiconductor, ...

1. A method for manufacturing a high voltage resistor comprising:forming a well region on a semiconductor substrate;
forming a first insulator layer on a surface of the well region;
forming a second insulator layer on a surface of the first insulator layer; and
forming a polysilicon layer on a surface of the second insulator layer,
wherein a first sloped side region extending a first sloped distance above the surface of the semiconductor substrate is included when forming the first insulator layer, and a second sloped side region extending a second sloped distance above the surface of the semiconductor substrate is included when forming the second insulator layer.

US Pat. No. 10,276,673

SEMICONDUCTOR DIE HAVING STACKING STRUCTURE OF SILICON-METALLIC CONDUCTIVE LAYER-SILICON

MagnaChip Semiconductor, ...

1. A semiconductor die, comprising:a stacking structure comprising:
a first semiconductor layer disposed over a second semiconductor layer; and
a metallic conductive layer between the first semiconductor layer and the second semiconductor layer;
first and second power semiconductor devices in the first semiconductor layer;
a first source bump and a first gate bump on the first semiconductor layer;
first trench gate electrodes under the first source bump;
a first channel between the first trench gate electrodes;
a second source bump and a second gate bump on the first semiconductor layer;
second trench gate electrodes under the second source bump; and
a second channel between the second trench gate electrodes.

US Pat. No. 10,269,677

SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURING THE SAME

MagnaChip Semiconductor, ...

1. A method to manufacture a semiconductor package, the method comprising:preparing a metal substrate;
attaching semiconductor dies to a first side of the metal substrate, the attached semiconductor dies being spaced apart from each other;
attaching a bonding film to the semiconductor dies;
applying a mold material in areas between the attached semiconductor dies and on a second side of the metal substrate, and curing the mold material to form a mold member;
grinding the mold member formed on the second side of the metal substrate and a part of the metal substrate;
removing the bonding film;
attaching a redistribution layer to the semiconductor dies; and
cutting between the semiconductor dies.

US Pat. No. 10,269,988

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

MagnaChip Semiconductor, ...

1. A semiconductor device, comprising:a substrate having a first doping concentration and comprising a Schottky barrier diode (“SBD”) region and a MOSFET region, the SBD region comprising a counter doping region in an upper portion of the substrate and a well region; and
a first trench disposed on a boundary line between the SBD region and the MOSFET region,
wherein the counter doping region has a second doping concentration, and
the counter doping region comprises a first doping region disposed in an upper portion of the SBD region and located outside the well region, and a second doping region disposed in an upper portion of the well region.

US Pat. No. 10,175,063

METHOD OF SENSING SLIDING BY HALL SENSOR AND SENSING SYSTEM USING THE SAME

MagnaChip Semiconductor, ...

1. A sensing device for sensing a horizontal sliding of a cover on a body, comprising:a magnetic field source on the cover; and
a Hall sensor in the body comprising a first Hall element and a second Hall element, wherein the first Hall element and the second Hall element are configured to detect a magnetic field strength generated by the magnetic field source on the cover and produce a first magnetic field strength and a second magnetic field strength, respectively, and
wherein the Hall sensor further comprises:
a similarity measurement unit configured to measure a ratio of the first magnetic field strength and the second magnetic field strength to produce a similarity value; and
a standard deviation measurement unit configured to measure a standard deviation of the first magnetic field strength and the second magnetic field strength to produce a standard deviation value,
a checking unit configured to check whether a threshold of one of the similarity value and the standard deviation value is satisfied, and
a determination unit configured to determine an occurrence of a horizontal sliding of the cover on a surface of the body comprising the Hall elements based on a result of the check.

US Pat. No. 10,566,422

POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

MagnaChip Semiconductor, ...

1. A power semiconductor device, comprising:a drain region and a source region disposed on a substrate;
a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region;
a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode;
a source contact plug connected to the source region;
a drain contact plug connected to the drain region; and
a field plate plug in contact with the protection layer,
wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug,
wherein a bottom surface of the field plug has a non-planar surface, and a top surface of the field plate plug is flat.

US Pat. No. 10,263,123

ELECTROSTATIC DISCHARGE DEVICE AND METHOD OF FABRICATING THE SAME

MagnaChip Semiconductor, ...

1. An electrostatic discharge (ESD) device comprising:a first conductivity-type semiconductor substrate;
a second conductivity-type epi-layer situated on the first conductivity-type semiconductor substrate;
a second conductivity-type semiconductor layer situated on a region among regions located between the first conductivity-type semiconductor substrate and the second conductivity-type epi-layer;
a second conductivity-type Zener region overlapping on the second conductivity-type semiconductor layer and the first conductivity-type semiconductor substrate, situated in a region and spaced apart from an upper side of the second conductivity-type epi-layer;
a first conductivity-type first doping region situated on the upper side of the second conductivity-type epi-layer and an upper region of the second conductivity-type semiconductor layer;
a first blocking structure surrounding the second conductivity-type semiconductor layer, the second conductivity-type Zener region, and the first conductivity-type first doping region;
a second conductivity-type second doping region situated on the upper side of the second conductivity-type epi-layer at an exterior region of the first blocking structure,
wherein the second conductivity-type Zener region extends across the first conductivity-type semiconductor substrate starting from a lower side of the second conductivity-type epi-layer to a greater depth than a lower side of the second conductivity-type semiconductor layer, and
wherein an upper side of the second conductivity-type Zener region is coplanar with the lower side of the second conductivity-type epi-layer.

US Pat. No. 10,217,836

METHOD OF MANUFACTURING POWER SEMICONDUCTOR DEVICE

MagnaChip Semiconductor, ...

1. A method of manufacturing a power semiconductor device, comprising:forming trenches in a substrate, wherein the substrate comprises a first surface and a second surface opposite to the first surface;
forming a gate insulating layer and a gate electrode in each of the trenches;
forming a P-type base region between the trenches in the substrate;
performing a first implantation process using P-type dopants implanted onto the P-type base region;
forming an N+ source region in the substrate;
forming an interlayer insulating layer on the N+ source region;
performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region;
forming an emitter electrode in contact with the N+ source region and the P+ doped region;
forming a P-type collector region on the second surface of the substrate; and
forming a drain electrode on the P-type collector region.

US Pat. No. 10,177,222

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

MagnaChip Semiconductor, ...

1. A semiconductor device, comprising:a semiconductor substrate in which a multi-depth trench is formed, the multi-depth trench comprising a shallow trench and a deep trench arranged below the shallow trench;
two dielectric materials, comprising a first dielectric material and a second dielectric material different from the first dielectric material, formed in the multi-depth trench,
wherein the first dielectric material is formed in a partial area of the multi-depth trench, the first dielectric material comprising a slope in the shallow trench that extends over a horizontal bottom surface of the shallow trench from a corner where a sidewall of the deep trench meets the horizontal bottom surface of the shallow trench, the slope being inclined with respect to the horizontal bottom surface of the shallow trench, and
wherein the second dielectric material is formed in areas of the multi-depth trench in which the first dielectric material is absent,
wherein the first dielectric material comprises a corner portion formed by the horizontal bottom surface of the shallow trench and a sidewall of the shallow trench and a bottom portion formed on a bottom plane of the deep trench, and wherein a cross-sectional area of the corner portion is larger than a cross-sectional area of the bottom portion.

US Pat. No. 10,772,207

FLEXIBLE SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME

MagnaChip Semiconductor, ...

1. A semiconductor package attached to a curved display panel, comprising:a semiconductor chip, having a top surface and a side surface, disposed on a curved flexible film, wherein the curved flexible film is disposed on the curved display panel;
a flexible cover layer attached to the top surface and the side surface of the semiconductor chip; and
an underfill material formed between the semiconductor chip and the curved flexible film, and overlapping a solder resist,
wherein the flexible cover layer is in direct contact with the underfill material, the solder resist, and the top and side surfaces of the semiconductor chip, and
wherein the top surface of the semiconductor chip on the curved flexible film remains flat.

US Pat. No. 10,504,932

DISPLAY DRIVER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

MagnaChip Semiconductor, ...

1. A method for manufacturing a semiconductor device, the method comprising:forming trench isolating regions on a substrate;
forming a well region on the substrate;
forming drift regions in the well region;
forming a gate insulating layer overlapped with the drift regions;
forming a gate electrode on the gate insulating layer;
forming spacers on side walls of the gate electrode;
forming a source region and a drain region in the drift regions;
forming a first insulating layer on the substrate and the gate electrode;
forming a second insulating layer on the first insulating layer; and
forming a contact plug in the first insulating layer and the second insulating layer.

US Pat. No. 10,269,653

METHOD OF FABRICATING DMOS AND CMOS TRANSISTORS

MagnaChip Semiconductor, ...

1. A semiconductor device, comprising:a semiconductor substrate;
a gate insulating film formed on the substrate;
a gate electrode formed on the gate insulating film;
a first well region and a second well region formed in the substrate, wherein the first well region and the second well region are in direct contact with each other, and an interface between the first well region and the second well region is disposed below the gate electrode; and
a high concentration drain region formed in the first well region; and
a high concentration source region formed in the second well region,
wherein the first well region is formed to be deeper than the high concentration drain region and is formed to be shallower below the gate electrode than below the high concentration drain region, and
wherein the second well region is formed to be deeper than the high concentration source region and is formed to be shallower below the gate electrode than below the high concentration source region.

US Pat. No. 10,261,590

APPARATUS AND METHOD FOR RECOGNIZING A MOVING DIRECTION OF GESTURE BASED ON DIFFERENCES BETWEEN SENSOR OUTPUT VALUES

MagnaChip Semiconductor, ...

1. An apparatus recognizing a moving direction of a gesture, comprising:first, second, third, and fourth sensors disposed at positions that are in first, second, third, and fourth directions, respectively, from a center, wherein each of the sensors outputs a value indicating detection of the gesture by the sensor; and
a controller configured to:
accumulate a first sum of measures based on differences between output values of the first sensor and the second sensor, and a second sum of measures based on differences between output values of the third sensor and the fourth sensor;
determine a first total number of intersecting points at which output values of the first sensor and the second sensor are equal, and a second total number of intersecting points at which output values of the third sensor and the fourth sensor are equal;
determine whether the first total number of intersecting points is equal to the second total number of intersecting points; and
estimate, in response to the determination of whether the first total number of intersecting points is equal to the second total number of intersecting points, an initial moving direction of the gesture,
wherein, the first direction is opposite to the second direction, the third direction is opposite to the fourth direction, and the first direction is transverse to the third direction.

US Pat. No. 10,236,297

SINGLE POLY NON-VOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME AND SINGLE POLY NON-VOLATILE MEMORY DEVICE ARRAY

MagnaChip Semiconductor, ...

1. A single poly non-volatile memory device, comprising:a first type lower well;
a first well and a second well formed spaced apart from each other in an upper portion of the first type lower well;
a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well;
first, second, and third doping regions disposed in an upper portion of the first well and formed adjacent to the selection transistor and the sensing transistor; and
a control gate formed in an upper portion of the second well, separated on an opposite side of the source electrode from the first well and connected to a gate of the sensing transistor.