US Pat. No. 9,070,420

MEMORY SHARING SYSTEM AND MEMORY SHARING METHOD

MStar Semiconductors, Inc...

1. A memory sharing system, comprising:
a memory device;
a master control device, coupled to the memory device via a data bus, for transmitting a clock signal to the memory device;
and

a slave control device, coupled to the memory device via the data bus and coupled to the master control device, comprising
a delay phase locked loop (DLL), the slave control device receiving the clock signal, with the DLL tracking a phase of the
clock signal, wherein the DLL receives the clock signal, and tracks a phase of the clock signal to generate an output signal
that is provided to the slave control device accessing the memory device via the data bus;

wherein the master control device and the slave control device access the memory device via the data bus,
wherein the memory device is a double data rate dynamic random access memory (DDR-DRAM),
wherein the slave control device transmits a request signal to the master control device to request an access right of the
memory device, and the master control device transmits a grant signal in response to the request signal to grant the access
right of the memory device to the slave control device, and

wherein the access right of the memory device is returned after the slave control device transmits an all-page-close command
to the memory device.

US Pat. No. 9,164,628

SIGNAL PROCESSING METHOD FOR TOUCH PANEL AND TOUCH PANEL SYSTEM

MStar Semiconductor, Inc....

1. A signal processing method adapted for a touch panel, the touch panel comprising a plurality of capacitor electrodes, the
method comprising:
providing a plurality of detection values respectively corresponding to a plurality of capacitance changes of the capacitor
electrodes;

low-pass filtering the detection values according to a filter structure to generate a plurality of filtered values, the filter
structure being associated with a characteristic of a touch event;

determining a touch position on the touch panel of the touch event according to one of the filtered values and the detection
values;

determining a displacement according to the touch position, the displacement being the characteristic of the touch event,
wherein:
when the displacement is greater than a first distance, the filter structure is set to a first filter structure;
when the displacement is between the first distance and a second distance, the filter structure is set to a second filter
structure;

when the displacement is smaller than the second distance, the filter structure is set to a third filter structure;
the first distance is greater than the second distance; and
filter strengths of the first filter structure, the second filter structure and the third filter structure are associated
with the first distance and the second distance, such that the filter strength of the third filter structure is heavier than
that of the second filter structure, and the filter strength of the second filter structure is heavier than that of the first
filter structure.

US Pat. No. 9,318,184

SIGNAL RECEIVER

MSTAR SEMICONDUCTOR, INC....

1. A DDR signal receiver, comprising:
a first stage amplifier, comprising:
a first current source, configured to provide a first current having a current value;
a first pair of active input devices, each of the first pair of active input devices having a control node, a first conduction
node and a second conduction node, one control node of the pair of active input devices receiving an input signal, the first
conduction nodes connected and receiving the first current, one of the second conduction nodes serving as an output nodes,
the first pair of active input devices outputting an output signal to a core circuit according to the current and the input
signal; and

a first pair of resistors, each resistor having a resistance value and connected between one of the second conduction nodes
and a power line; and

a second-stage amplifier, comprising:
a second current source, configured to provide a second current;
a second pair of active input devices, each of the second pair of active input devices having a control node, a first conduction
node and a second conduction node, the first conduction nodes of the second pair of active input devices connected to each
other, the control nodes of the second pair of active input devices connected to the first-stage output nodes, respectively;
and

a second pair of resistors, each of the second pair of resistors having second resistance value and connected between one
of the second conduction nodes of the second pair of active input devices and the power line;

wherein, a target voltage value is determined according to the resistance value and the current value, such that a voltage
swing of the output signal is limited within the target voltage value, and an operating voltage of the core circuit is substantially
equal to the target voltage value, one of the second conduction nodes of the second pair of active input devices outputs second
output signal, and a product of the second resistance value and the second current value is substantially equal to the operating
voltage, the signal receiver is formed in an integrated circuit, the integrated circuit comprises a plurality of core devices
and a plurality of high-voltage tolerant devices, the high-voltage tolerant devices have a higher voltage tolerance compared
to the core devices, the pair of active input devices are high-voltage tolerant devices, and the second pair of active input
devices are core devices.

US Pat. No. 9,060,334

WIRELESS COMMUNICATION DEVICE AND POWER SAVING METHOD THEREOF

MStar Semiconductor, Inc....

1. A method for reducing power consumption of a wireless communication device, employed in connection with a plurality of
base stations (BSs) and the wireless communication device, which selectively operates in an operating status and a sleep status,
the method comprising:
prompting the wireless communication device to enter the operating status; and
performing a base station measurement before the wireless communication device receives a paging message,
wherein the base station measurement is performed in a same frame in which the wireless communication device enters the operating
status and no paging message is received in the same frame, and

wherein an operation to prepare for receiving the paging message is performed only after the base station measurement is complete.

US Pat. No. 9,319,046

INTEGRATED CIRCUIT CAPABLE OF PREVENTING CURRENT BACKFLOW TO POWER LINE

MSTAR SEMICONDUCTOR, INC....

1. An integrated circuit, capable of preventing current backflow to a power line, comprising:
an input circuit, comprising:
a bonding pad, configured to electrically connect to an external signal line;
a pull-up switch, comprising a first control node and a first bulk node, configured to electrically connect the bonding pad
to the power line;

a bulk controlled switch, comprising a second control node and a second bulk node, configured to connect the first bulk node
and the second bulk node to the power line; and

a control circuit, electrically connected to the power line and the bonding pad, configured to control the first control node
and the second control node;

wherein, when the power line is at a predetermined voltage, the control circuit turns on the bulk control switch; when the
power line is at a ground voltage and the bonding pad is at the predetermined voltage, the control circuit turns off the bulk
controlled switch and the pull-up switch.

US Pat. No. 9,467,146

OUTPUT CIRCUIT ADAPTED FOR INTEGRATED CIRCUIT AND ASSOCIATED CONTROL METHOD

MStar Semiconductor, Inc....

1. An output circuit, adapted for an integrated circuit, comprising:
a driver, electrically connected to two output nodes outside the integrated circuit to output signals;
a pre-driver, configured to control the driver, comprising a load and an input transistor that are connected in series, wherein
between the load and the input transistor is a connection node for controlling the driver; and

a buffer circuit, configured to control the load and the input transistor according to an internal signal, and to pre charge
the connection node through the load before turning off the input transistor,

wherein the load and the input transistor are a first load and a first input transistor, respectively, the pre-driver further
comprises a second load and a second input transistor that are connected in series, the buffer circuit turns on the second
input transistor when turning off the first input transistor and increase impedance of the second load when pre charging the
connection node.

US Pat. No. 9,642,158

SCHEDULING METHOD AND DEVICE

MSTAR SEMICONDUCTOR, INC....

1. A scheduling method for a user equipment, comprising:
determining whether a valid time interval is smaller than a first time interval, the first time interval at least being a
sum of a first value and a length of a Global System of Mobile communication (GSM) timeslot, wherein said first value is a
difference between a length of one Time Division-Synchronous Code Division Multiple Access (TD-SCDMA) sub-frame and a length
of one Time Division Multiple Access (TDMA) frame; and

when the valid time interval is smaller than the first time interval, performing a search for a time length of N predetermined
search cycles, N consecutive TD-SCDMA sub-frames being regarded as one group in each of the predetermined search cycles, selecting
a fixed sub-frame in the group for the search and completing a GSM initialization synchronization of said user equipment;

wherein, said user equipment is operating in a TD-SCDMA mode;
wherein, in the N predetermined search cycles, the fixed sub-frames selected in respective predetermined search cycles are
different, and N is a natural number greater than or equal to 2.

US Pat. No. 9,214,955

BOOLEAN ENTROPY DECODER AND BOOLEAN ENTROPY DECODING METHOD FOR VIDEO DISPLAY SYSTEM

MSTAR SEMICONDUCTOR, INC....

1. A Boolean entropy decoder, for decoding a bitstream, comprising:
a decoding module, for generating an initial boolean value, a first boolean value and a second boolean value according to
the bitstream, requiring a first bit amount while generating a first value corresponding to the first boolean value, and requiring
a second bit amount while generating a second value corresponding to the second boolean value; wherein, the first boolean
value, the second value, the second boolean value and a temporary third value corresponding to a third boolean value are generated
during a same cycle; the decoding module, comprising:

a preliminary computing unit, for generating an adjusted split (S0—m1) according to a range (R0) and a probability (P0) corresponding to the initial boolean value, and said adjusted split is equal to:


 and
a determining unit, for determining the first bit amount according to the adjusted split;
a buffer, for temporarily storing a bit segment of the bitstream to be provided to the decoding module, the bit segment covering
the first bit amount and the second bit amount; and

an updating module, updating the buffer after fetching a new bit segment from the bitstream according to the first bit amount
and the second bit amount;

wherein, the decoding module selectively adjusts the temporary third value corresponding to the third boolean value after
the buffer is updated; and

wherein, the first bit amount is a number of bits in the buffer required when said bitstream is fetched for generating the
first value, and the second bit amount is a number of bits in the buffer required when the bitstream is fetched for generating
the second value.

US Pat. No. 9,210,471

DATA SAMPLING AND DATA ENCRYPTION/DECRYPTION METHOD AND ELECTRONIC DEVICE UTILIZING THE METHODS

MStar Semiconductor, Inc....

1. A signal sampling method, comprising:
(a) sampling an input signal with respect to a sampling clock signal;
(b) calculating a maximum transition timing and a minimum transition timing of the input signal according to a relation between
the sampling in step (a) and a reference clock signal;

(c) defining a voltage level transition interval according to the maximum transition timing and the minimum transition timing;
and

(d) determining phase of the sampling clock signal or phase of the input signal according to the voltage level transition
interval,

wherein the step (b) further comprises:
setting an earlier one of a first transition timing and a second transition timing as the minimum transition timing and setting
the other one of the first transition timing and the second transition timing as the maximum transition timing if the input
signal transits the voltage level at the first transition timing and the consecutive second transition timing and difference
between the first transition timing and the second transition timing is shorter than one half of the period of the reference
clock signal, and

wherein the step (b) further comprises:
setting a third transition timing as the maximum transition timing if the input signal transits the voltage level at the third
transition timing when the third transition timing occurs earlier than the time the maximum transition timing plus one half
of the period of the reference clock signal as well as earlier than the time the minimum transition timing minus one half
of the period of the reference signal clock, and, when the maximum transition time period occurs later than one half of the
period of the reference clock signal.

US Pat. No. 9,136,889

MIXER BIASING FOR INTERMODULATION DISTORTION COMPENSATION

MStar Semiconductor, Inc....

9. A receiver having downconverting mixers in a receiver signal processing chain, the receiver comprising:
the downconverting mixers configured to mix an RF signal with a biasing differential to generate a baseband signal;
a processor configured to determine intermodulation distortion compensation weights to minimize cross-correlation of quadrature
signal components of the RF signal produced by the receiver in the presence of a blocking signal; and

a circuit configured to generate a voltage to apply as the biasing differential across the downconverting mixers based on
the determined intermodulation distortion compensation weights.

US Pat. No. 9,147,375

DISPLAY TIMING CONTROL CIRCUIT WITH ADJUSTABLE CLOCK DIVISOR AND METHOD THEREOF

MStar Semiconductor, Inc....

1. A display timing control circuit, comprising:
an output pixel clock generator, for generating an output pixel clock signal according to a reference clock signal and a clock
divisor;

a display timing generator, coupled to the output pixel clock generator, for generating a display timing signal and an output
vertical reference signal according to the output pixel clock signal, with the output vertical reference signal having an
output frame rate; and

a clock adjusting unit, coupled to the output pixel clock generator and the display timing generator, for adjusting the clock
divisor according to the output pixel clock signal, the output vertical reference signal, and an input vertical reference
signal which has an input frame rate,

wherein the clock adjusting unit comprises:
a frequency shift detector, for detecting a frequency shift between the output vertical reference signal and the input vertical
reference signal;

a clock divisor generator, coupled to the frequency shift detector, for generating an updated value of the clock divisor according
to the frequency shift; and

a phase difference detector, coupled to the clock divisor generator, for detecting a phase difference between the output vertical
reference signal and the input vertical reference signal,

wherein the clock divisor generator determines a divisor adjustment amount of the clock divisor according to the phase difference.

US Pat. No. 9,112,472

VARIABLE GAIN LOW-NOISE AMPLIFIER

MStar Semiconductor, Inc....

1. An amplifier comprising:
an input port comprising a signal terminal and a common terminal between which a radio-frequency (RF) single-ended input signal
is accepted;

an output port comprising a positive terminal and a negative terminal between which an RF differential output signal is provided;
a plurality of amplifier stages commonly coupled to the signal terminal of the input port, the amplifier stages including
a plurality of subtrahend amplifier stages commonly coupled to the negative terminal of the output port and a plurality of
minuend amplifier stages commonly coupled to the positive terminal of the output port; and

a control circuit electrically connected to the amplifier stages to activate up to one of the subtrahend amplifier stages
and one of the minuend amplifier stages to form a differential set of amplifier stages that generates the differential output
signal from the single-ended input signal.

US Pat. No. 9,134,862

PARALLELOGRAM ELECTRODE TOUCH PANEL

MSTAR SEMICONDUCTOR, INC....

1. A touch panel, comprising:
a plurality of electrodes, forming a sensing area having a first border and a second border substantially perpendicular to
each other, disposed on a same plane, comprising:

a parallelogram electrode, having two first sides parallel to the first border and two second sides parallel to neither the
first border nor the second border; and

a right-angle triangle electrode, having a hypotenuse and two legs, wherein the hypotenuse is parallel to the two second sides
of the parallelogram electrode, and one of the legs is parallel to the second border; and

a connecting wire corresponding to the parallelogram electrode extending from an angle of the parallelogram electrode closest
to the second border,

wherein capacitance changes generated by the parallelogram electrode are used for calculating both a first direction coordinate
and a second direction coordinate of a touch position.

US Pat. No. 9,213,057

TESTING SYSTEM AND TESTING METHOD FOR TOUCH DEVICE

MStar Semiconductor, Inc....

1. A touch device testing system for testing a touch device, comprising:
a touch simulation module, comprising a plurality of conductive elements respectively corresponding to a plurality of touch
sensing regions of the touch device, each conductive element spanning all sensing regions of the touch device along a predetermined
axis;

a control module, coupled to the conductive elements, for generating and selectively providing a testing signal to one or
a plurality of conductive elements among the conductive elements; and

a determination module, coupled to the touch device, for determining whether the touch device correctly responds to a testing
that the control device applies to the touch sensing regions through the touch simulation module,

wherein the plurality of conductive elements cause capacitances changes in the plurality of touch sensing regions in response
to the testing signal.

US Pat. No. 9,098,231

APPARATUS AND METHOD FOR DISPLAYING IMAGE CHARACTERISTICS OF A SECOND DISPLAY ON A FIRST DISPLAY

MStar Semiconductor, Inc....

1. An image transform apparatus, for displaying image characteristics of a second display on a first display, the image transform
apparatus comprising:
a first transform unit comprising a first lookup table or a first calculator, for transforming a first image signal of the
first display to a first output signal according to a second gamma value associated with the second display;

a second transform unit, for transforming the first output signal to a second output signal according to a transform gain
associated with the first display and the second display; and

a third transform unit, for transforming the second output signal to a second image signal according to a first gamma value
associated with the first display,

wherein first lookup table and the first calculator define a relationship as follows:
(the first output signal)=(the first image signal)the second gamma value, and

wherein (the second image signal)=(the second output signal)1/the first gamma signal.

US Pat. No. 9,166,475

VOLTAGE REGULATOR WITH FAST AND SLOW SWITCHING CONTROL

MStar Semiconductor, Inc....

1. A switching regulator, configured to control a supply of power from a power source to a power load, comprising:
a control configuration select unit, for selecting between a high power mode and a low power mode in response to a control
signal which depends on a state of the power load, the control signal being received from a controller associated with the
power load;

a first control unit, enabled by the control configuration select unit when selecting the high power mode, the first control
unit comprising a fast clock that is configured to drive a pulse control unit to deliver pulses to switching circuitry; and

a second control unit, enabled by the control configuration select unit when selecting the low power mode, the second control
unit comprising a slow clock, wherein a frequency of the slow clock is lower than a frequency of the fast clock, the slow
clock configured to cause the switching circuitry to switch at a lower rate than the fast clock,

wherein when the first control unit is enabled the second control unit is disabled, and when the second control unit is enabled
the first control unit is disabled.

US Pat. No. 9,143,133

OUTPUT APPARATUS, OUTPUT DRIVER, AND LEVEL SHIFTING SYSTEM

MSTAR SEMICONDUCTOR, INC....

1. An output apparatus, comprising:
a high level shifting circuit, configured to shift an input signal to a high output signal, the input signal having two input
logic levels, the high output signal is at one of two different high output logic levels;

a high buffer circuit, configured to drive a high control node according to the high output signal;
a low level shifting circuit, configured to shift the input signal to a low output signal, the low output signal is at one
of two different low output logic levels;

a low buffer circuit, configured to drive a low control node according to the low output signal; and
an output driver, comprising the high control node and the low control node, configured to drive a pad;
wherein, the two low output logic levels are the same as the two input logic levels.

US Pat. No. 9,118,318

DRIVING CIRCUIT AND DRIVING METHOD

MStar Semiconductor, Inc....

1. A driving circuit, comprising:
a first driving module, configured to operate at a first operating voltage in a first mode and configured to be deactivated
in a second mode; and

a second driving module, wherein at least part of the second driving module operates at a protection voltage in the first
mode and operates at a second operating voltage in the second mode, wherein the second operating voltage and the protection
voltage are lower than the first operating voltage,

wherein the second driving module further comprises:
a pre-driving stage, configured to generate a pre-driving voltage according to an input voltage; and
a driving stage, configured to generate a driving current according to the pre-driving voltage,
wherein only the pre-driving stage operates at the protection voltage in the first mode and operates at the second operating
voltage in the second mode.

US Pat. No. 9,106,403

FREQUENCY OFFSET ESTIMATION METHOD AND ASSOCIATED APPARATUS APPLIED TO MULTI-CARRIER COMMUNICATION SYSTEM

MSTAR SEMICONDUCTOR, INC....

5. A frequency offset estimation apparatus for a multi-carrier communication system, comprising:
a fast Fourier transform (FFT) unit, configured to transform a representation of a reception signal from a time domain to
a frequency domain, and generate a plurality of symbols;

a buffer, configured to receive the symbols;
a conjugate multiplier, configured to receive a current symbol from the FFT unit and a previous symbol from the buffer to
perform conjugate multiplication to generate a plurality of correlating complex numbers;

a magnitude retrieval unit, configured to retrieve magnitudes of real parts of the correlating complex numbers;
a storage unit, configured to store the magnitudes of the real parts of the correlating complex numbers; and
a processor, configured to generate an M number of candidate subcarrier position sets according to a subcarrier position set
of a specific signal and an M number of candidate frequency offsets, to calculate an M number of calculated values according
to the correlating complex numbers corresponding to the M number of candidate subcarrier position sets, and to determine a
frequency offset according to a maximum calculated value among the M calculated

values, wherein M is an integer, and the processor is configured to calculate the M number of calculated values by
determining a first candidate subcarrier position set according to a first candidate frequency offset and the subcarrier position
set of the specific signal; and

summing up the magnitudes of the real parts of the plurality of correlating complex numbers corresponding to the first candidate
subcarrier position set to obtain a first calculated value.

US Pat. No. 9,060,424

BALL GRID ARRAY FORMED ON PRINTED CIRCUIT BOARD

MSTAR SEMICONDUCTOR, INC....

1. A ball grid array, formed on a printed circuit board, comprising:
a first ballout module, comprising a plurality of first solder balls arranged as an array, wherein two among the first solder
balls are grounded and remaining of the first solder balls are disposed within a shielding area defined by the two grounded
first solder balls, wherein a first row of the first ballout module faces a first direction, a first column of the first ball
module faces a second direction, the first direction is perpendicular to the second direction, and the two grounded first
solder balls are disposed at a third row of the first ballout module; and

a second ballout module, disposed adjacent to the first ballout module and comprising a plurality of second solder balls,
wherein two among the second solder balls are grounded and remaining of the second solder balls are disposed within a shielding
area defined by the two grounded second solder balls;

wherein the first ballout module and the second ballout module deploy substantially a same ballout arrangement associated
with relative positions of the two grounded solder balls and the remaining solder balls that are not grounded in each ballout
module;

wherein the ball grid array renders at most two grounded soldier balls in every five columns of solder balls.

US Pat. No. 9,280,201

ELECTRONIC DEVICE AND DIGITAL DISPLAY DEVICE

MSTAR SEMICONDUCTOR, INC....

1. An electronic device, comprising:
a sensing unit for sensing a frame image and generating a first sensing signal at a first time and a second sensing signal
sensed at a second time, wherein the first time is earlier than the second time;

an image reception interface for receiving the first sensing signal and the second sensing signal;
a movement detecting engine for comparing the first sensing signal with the second sensing signal to determine whether there
are differences between the first sensing signal and the second sensing signal;

an image processing engine outputting an encoding signal according to a comparison result outputted from the movement detecting
engine, indicating that there are differences between the first sensing signal and the second sensing signal;

a video encoding unit for generating an image signal according to the encoding signal;
a picture encoding unit for generating image information according to the encoding signal;
a scaling engine for generating an adjusted encoding signal according to the encoding signal; and
a bus transmission unit for combining the image signal, the image information and the adjusted encoding signal as an image
signal;

a host processing unit electrically connected to the sensing unit for performing a host function according to the image signal,
wherein the image processing engine outputs the encoding signal to the video encoding unit, the picture encoding unit and
the scaling engine.

US Pat. No. 9,125,129

MOBILE COMMUNICATION DEVICE AND ASSOCIATED CONTROL METHOD

MStar Semiconductor, Inc....

1. A mobile communication device, serviced by a wireless communication network, comprising:
an evaluation module, configured to evaluate a connection ability between the mobile communication device and a plurality
of base stations;

a determination module, configured to determine whether a report is to be issued according to the connection ability and a
customized rule different from a standard rule, wherein the standard rule corresponds to a threshold of the connection ability
defined by the wireless communication network;

a reporting module, that issues the report to the wireless communication network when the determination module determines
to issue the report; and

a recording module, recorded with an active set list;
wherein, when a quantity of base stations in the active set list has not reached an upper limit and a target base station
from the base stations is not included in the active set list, the determination module determines whether the report is to
be issued according to the connection ability of the target base station, in order to request the wireless communication network
to add the target base station into the active set list; and

while the standard rule comprises a standard period, the customized rule comprises a customized period shorter than the standard
period; the wireless communication network has a default that the mobile communication device issues the report when the connection
ability of the target base station remains greater than a first threshold for longer than the standard period, while the determination
module determines the report is to be issued when the connection ability of the target base station remains greater than the
first threshold for longer than the customized period.

US Pat. No. 9,166,847

SIGNAL RECEIVING APPARATUS AND TWO-STAGE ADAPTIVE EQUALIZATION METHOD THEREOF

MSTAR SEMICONDUCTOR, INC....

1. A signal receiving apparatus, comprising:
an equalization module, configured to receive an input signal and to perform an equalization process on the input signal according
to an equalization strength to generate an equalized signal;

a coarse tuning module, coupled to the equalization module, configured to adjust the equalization strength according to the
equalized signal until the equalized signal satisfies a preliminary convergence condition;

a fine tuning module, coupled to the equalization module, configured to adjust the equalization strength according to the
equalized signal when the equalized signal satisfies the preliminary convergence condition until the equalization strength
satisfies a final convergence condition;

a local oscillation source, configured to provide a local oscillation signal; and
a clock signal generation module, configured to receive an original signal and to perform a clock signal recovery process
on the original signal to generate a clock signal;

wherein the clock signal generation module is configured as a frequency synthesizer to generate a substitute clock signal
according to the local oscillation signal, if the clock signal remains in an unlocked status after a period of time.

US Pat. No. 9,274,809

ELECTRONIC APPARATUS HIBERNATION RECOVERY SETTING METHOD AND ELECTRONIC APPARATUS HAVING HIBERNATION STATE AND HIBERNATION RECOVERY MECHANISM

MSTAR SEMICONDUCTOR, INC....

1. An electronic apparatus hibernation recovery method, comprising:
assigning a plurality of priorities to a plurality of tasks in process on an electronic apparatus before the electronic apparatus
enters a hibernation state;

generating and storing a hibernation image file comprising the tasks and the priorities to a hard drive, wherein the tasks
with a same priority are stored in a same region of the hard drive; and

loading and restoring a part of the hibernation image file associated with the highest priority of the priorities when the
electronic apparatus recovers from the hibernation state.

US Pat. No. 9,184,955

METHOD AND DEVICE FOR SIGNAL PROCESSING

MSTAR SEMICONDUCTOR, INC....

1. A method for signal processing, comprising:
obtaining a predistortion signal for compensating a nonlinear distortion generated by a transmission path;
adding the predistortion signal to the transmission path to compensate the nonlinear distortion; and
outputting the nonlinear distortion compensated signal by the transmission path;
wherein, the transmission path is inputted with a baseband signal having a frequency fBB, and the predistortion signal has a frequency 3*fBB.

US Pat. No. 9,135,894

DATA ACCESS METHOD AND ELECTRONIC APPARATUS FOR ACCESSING DATA

MSTAR SEMICONDUCTOR, INC....

1. A data access method, applied to a storage apparatus for outputting an image frame to a panel, comprising:
performing a first write speed check operation at a predetermined point in time from a start of a write operation, comprising:
comparing a first predetermined accumulated written data amount corresponding to the first write check point to a first actual
accumulated written data amount; and

adjusting actual write speed to the storage apparatus when a difference between the first predetermined accumulated written
data amount and the first actual accumulated written data amount is greater than a predetermined value;

performing a second write speed check operation at a randomly defined point in time after the first write check operation,
comprising:

comparing a second predetermined accumulated written data amount corresponding to the second write check point to a second
actual accumulated written data amount; and

adjusting actual write speed to the storage apparatus when a difference between the second predetermined accumulated written
data amount and the second actual accumulated written data amount is greater than a predetermined value; and

performing a third write speed check operation when a predetermined row of said image frame is written into the storage apparatus,
comprising:

comparing a third predetermined accumulated written data amount corresponding to the third write check point to a third actual
accumulated written data amount; and

adjusting actual write speed to the storage apparatus when a difference between the third predetermined accumulated written
data amount and the third actual accumulated written data amount is greater than a predetermined value.

US Pat. No. 9,317,167

TOUCH CONTROL SYSTEM AND SIGNAL PROCESSING METHOD THEREOF

MSTAR SEMICONDUCTOR, INC....

1. A signal processing method for a touch panel, the touch panel comprising a first sensing region and a second sensing region,
the first sensing region being monitored by at least one sensor to generate a first monitoring result, the second sensing
region being monitored by at least one sensor to generate a second monitoring result, wherein the first monitoring result
comprising a plurality of first sub-results and the second monitoring result comprising a plurality of second sub-result,
the signal processing method comprising:
grouping the first sub-results to generate a first grouping result;
grouping the second sub-results to generate a second grouping result;
determining that the first sensing change group forms the touch point in the first sensing region when the first group result
indicates that a first sensing change group occurs in the first sensing region and the second grouping result indicates that
no sensing change group occurs in the second sensing region;

determining a distance between the first sensing change group and the second sensing change group when the first group indicates
that the first sensing change group occurs in the first sensing region and the second grouping result indicates that a second
sensing change group occurs in the second sensing region;

determining that the first sensing change group forms the touch point in the first sensing region and the second sensing change
group forms another touch point in the second sensing region when the distance is greater than a threshold;

collectively regarding the first sensing change group and the second sensing change group as an intermediate touch point,
and generating position information of the intermediate touch point according to the first monitoring result and the second
monitoring result when the distance is smaller than the threshold; and

performing step (a) and step (b) for the touch point:
a) determining whether a touch point formed in the first sensing region is close to the second region; and
b) generating position information of the touch point according to the first monitoring result and the second monitoring result
when a determination result of step (a) is affirmative.

US Pat. No. 9,197,876

FRAME RATE CONVERSION APPARATUS FOR 3D DISPLAY AND ASSOCIATED METHOD

MStar Semiconductor, Inc....

1. A frame rate conversion apparatus for three-dimensional (3D) stereo display, comprising:
a storage unit;
an input controller, for inputting an input frame sequence to the storage unit according to an input frame rate, the input
frame sequence comprising a plurality of frame pairs each having a left frame and a corresponding right frame; and

an output controller, for alternately outputting one of the left frames and one of the right frames from the storage unit
according to an output frame rate and left/right frame information associated with the frame pairs in the storage unit to
form an output frame sequence,

wherein the output controller successively outputs one of the left frames a predetermined number of times when outputting
the one of the left frames, and successively outputs one of the right frames the predetermined number of times when outputting
the one of the right frames,

wherein the output controller and the input controller do not simultaneously output from and input to a same frame buffer,
wherein the output controller selects a frame buffer to which one of the right frames has been most recently inputted by the
input controller to output after outputting one of the left frames,

wherein the output controller selects a frame buffer to which one of the left frames has been most recently inputted by the
input controller to output after outputting one of the right frames, and

wherein alternately outputting one of the left frames and one of the right frames from the storage unit comprises selectively
skipping at least one frame of the input frame sequence.

US Pat. No. 9,160,387

METHOD AND APPARATUS FOR NOISE CANCELING

MSTAR SEMICONDUCTOR, INC....

1. A circuit in a device, comprising:
a transceiver circuit, comprising:
a first receiver circuit, configured to receive a first signal from an antenna that captures a combination of a target signal
transmitted from outside the device and an output signal driven by a transmitter outside the transceiver circuit in the device;

a second receiver circuit configured to receive a second signal generated based on the output signal;
a processing circuit configured to cancel from the first signal noise due to the output signal based on the second signal;
and

a controller configured to turn on the second receiver circuit when a received signal strength indication (RSSI) of the first
receiver circuit is lower than a threshold.

US Pat. No. 9,118,523

SIGNAL RECEIVING APPARATUS AND SIGNAL RECEIVING METHOD

MSTAR SEMICONDUCTOR, INC....

1. A signal receiving apparatus, applicable in a wireless system, comprising:
an adjustment circuit, configured to receive a received signal having a first direct current (DC) signal and to adjust the
first DC signal according to an adjustment signal to generate an adjusted receiving signal having a second DC signal;

a first calculation circuit, configured to generate an error signal according to a comparison of the second DC signal with
a target DC signal, the first calculation circuit comprising:

an analog to digital converter (ADC), configured to convert the second DC signal from analog form to digital form; and
a first digital processing circuit, configured to calculate the error between the second DC signal and the target DC signal
to generate the error signal, the first digital processing circuit comprising:

a first logic circuit, configured to generate a differential calculus signal according to the second DC signal and a prior
DC signal;

a second logic circuit, configured to generate an integral calculus signal and the prior DC signal by operating integral calculus
on the differential calculus signal; and

a third logic circuit, configured to generate the error signal according to the integral calculus signal and the target DC
signal; and

a second calculation circuit, configured to generate a change rate according to the error signal and to update the adjustment
signal according to the change rate and the error signal.

US Pat. No. 9,319,971

FREQUENCY ADJUSTMENT METHOD

MStar Semiconductor, Inc....

1. A frequency adjustment method, applied to a reference oscillation signal, the method comprising:
dividing a frequency scan section into M scan frequencies, wherein M is a positive integer greater than 1;
down-converting a signal according to the M scan frequencies to obtain M down-converted signals;
performing a correlation calculation operation on the M down-converted signals, respectively, to obtain M correlation results;
grouping the M scan frequencies into N frequency groups, wherein N is a positive integer greater than 1, performing a group
calculation operation on the N frequency groups, respectively, to obtain N group calculation results; and

selecting a target frequency group from the N frequency groups according to the N group calculation results, and obtaining
an adjusted oscillation frequency from the target frequency group,

wherein each frequency group comprising P selected frequencies, wherein P is a positive integer greater than 1, corresponding
to P consecutive scan frequencies in the frequency scan section, wherein every two consecutive frequency groups in the N frequency
groups comprise same (P?1) selected frequencies,

wherein the step of performing the group calculation operation on the N frequency groups, respectively, to obtain the N group
calculation results comprises:

selecting the frequency group on which the group calculation operation is to be performed from the N frequency groups;
selecting P correlation results from the M correlation results according to the target frequency group;
sequentially corresponding P weightings to the selected P correlation results, and performing a weighted accumulation operation
on the selected P correlation results; and

repeating the above steps to obtain the N group calculation results corresponding to the N frequency groups.

US Pat. No. 9,257,992

COMMUNICATION DEVICE AND CONTROL METHOD THEREOF

MStar Semiconductor, Inc....

1. A control method, applied to a communication device comprising an oscillation signal source, a tunable capacitor array
and a frame counter, the control method comprising:
when the communication device operates in a normal mode, compensating a first frequency offset of the oscillation signal source
jointly or separately by the tunable capacitor array and the frame counter; and

when the communication device operates in a low power consumption mode, compensating a second frequency offset of the oscillation
signal source jointly or separately by the tunable capacitor array and the frame counter.

US Pat. No. 9,247,438

SEARCH METHOD FOR WIRELESS COMMUNICATION SYSTEM

MStar Semiconductor, Inc....

1. A search method for finding a target location in a variable space;
the variable space being constructed by a set of variables and having a plurality of sub-spaces, the target location rendering
an output result of a wireless communication to satisfy a target value; the search method comprising:

providing the set of variables;
identifying a target sub-space where the target location is located from the sub-spaces;
obtaining a plurality of gradients of the output result at a predetermined location from the target sub-space, each of the
gradients corresponding to a direction of change; and

selecting one from the directions of change according to the gradients, and changing values of the set of variables along
the selected direction of change to find the target location,

wherein the step of selecting one from the directions of change according to the gradients, and changing the values of the
set of variables along the selected direction of change to find the target location first changes the values of the set of
variables utilizing a first step-size to find the target location, and then changes the values of the set of variables utilizing
a second step-size to find the target location; the first step-size is greater than the second step-size.

US Pat. No. 9,196,015

IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD AND IMAGE DISPLAY SYSTEM

MStar Semiconductor, Inc....

1. An image processing apparatus, for generating an intermediate frame according to a previous frame and a next frame, the
intermediate frame comprising a plurality of intermediate image blocks each corresponding to a motion vector, the image processing
apparatus comprising:
a determining module, for determining whether each interpolated image, for each intermediate image block, generated according
to the motion vectors meets a correctness requirement to generate a correctness signal;

a selecting module, for selecting the interpolated image to represent the intermediate image block when the interpolated image
meets the correctness requirement, and selecting a substitutive image different from the interpolated image to represent the
intermediate image block when the interpolated image block fails to meet the correctness requirement,

each of the intermediate image blocks corresponding to a previous image block in the previous frame and a next image block
in the next frame, the image processing apparatus further comprising:

an interpolating module, for generating the interpolated image corresponding to the intermediate image block according to
the motion vector corresponding to the intermediate image block;

a mixing module, for mixing image data of the previous image block and the next image block according to a ratio to generate
a mixed image; and

a weighting module, for adding a product of multiplying image data of the mixed image with a first weighting and a product
of multiplying image data of the interpolated image by a second weighting to generate the substitutive image corresponding
to the intermediate image block.

US Pat. No. 9,183,115

TESTING METHOD AND TESTING APPARATUS FOR TESTING FUNCTION OF ELECTRONIC APPARATUS

MSTAR SEMICONDUCTOR, INC....

1. A testing method, for testing a function of a program in an electronic apparatus, the program associating the function
to an icon on an user interface, the method comprising:
a) searching for a location of the function in the program, detecting a hardware status corresponding to the function, stopping
testing the function when an error occurs in the hardware status, and not displaying a corresponding icon when the error occurs
in the hardware status, wherein the location comprises a position of the icon on the user interface;

b) sending a command according to the location to perform the function; and
c) determining whether an error occurs in the function according to a response of the function in response to the command;
wherein, the command comprises a sub-command representing a user behavior of moving to the icon on the user interface;
wherein, step (a) further comprises:
a1) determining whether the function corresponds to a dynamic command to generate a determination result;
a2) obtaining index information of all functions in the user interface from the electronic apparatus when the determination
result is affirmative, and obtaining the location of the function according to the index information; and

a3) obtaining the location of the function according to the program to be tested when the determination result is negative;
and

wherein, step (b) further comprises determining a function corresponding to the user interface, and stopping sending the command
when the function is not a function of the user interface.

US Pat. No. 9,258,149

REFINEMENT OF CHANNEL RESPONSE CALCULATION

MStar Semiconductor, Inc....

1. Apparatus for estimating, for a wireless signal acquired by a receiver, a channel response estimate having a set of potential
tap positions, the apparatus comprising
a measurement circuit to calculate signal significance values for said wireless signal for all tap positions in said set of
potential tap positions,

a decision circuit arranged to use the signal significance values produced by the measurement circuit to determine if any
of said tap positions in said set of potential tap positions should not be used to calculate the channel response estimate
and

an estimation circuit to calculate the channel response estimate using said set of potential tap positions less any tap positions
excluded by the decision unit,

wherein the decision unit is further arranged to, for one or more of the tap positions in said set of potential tap positions,
combine several of the signal significance values that correspond to the same tap position by filtering,

wherein the calculated signal significance values are measured by an average power of the wireless signal at all the tap positions
in said set of potential tap positions.

US Pat. No. 9,373,154

IMAGE PROCESSING APPARATUS HAVING REDUCED LINE BUFFER SIZE AND ASSOCIATED METHOD

MStar Semiconductor, Inc....

1. An image processing apparatus, comprising:
a first memory, for storing an original image having a first width;
a second memory;
a buffer, having a second width smaller than the first width;
a fetching module, for fetching a sub-image of the original image from the first memory and storing the sub-image into the
buffer; wherein a width of the sub-image is smaller than or equal to the second width, the fetching module configured to operate
with predefined rules for fetching the sub-image of the original image from the first memory; and

a processing module, for performing an image processing process on the sub-image image to generate a processed sub-image,
and storing the processed sub-image into the second memory,

wherein the original image comprises N number of sub-images, each of the sub-images having the width smaller than the second
width, and N is an integer greater than 1; and the fetching module sequentially fetches the N sub-images from the first memory
to the buffer for processing by the processing module,

wherein each sub-image comprises a main part and a border part, the border part of a first sub-image is also the main part
of a second sub-image, and the border part is selected to prevent image discontinuity of processed sub-images, wherein the
border part is used to perform the image processing process on the main part of the first sub-image to generate a processed
sub-image, while the border part of the first sub-image itself is not processed.

US Pat. No. 9,288,419

REMOTE CONTROLLER WITH DUAL POWER SUPPLY UNITS

MSTAR SEMICONDUCTOR, INC....

1. A remote controller, for controlling a television, the remote controller comprising:
a housing;
a first sub-system, disposed in the housing, comprising:
a first power supply, for powering the first sub-system;
a button module, coupled to the first power supply, comprising a plurality of operation buttons, for generating a first signal
for controlling the television to perform a first operation corresponding to one of the operation buttons being pressed; and

an infrared transmitter, for transmitting the first signal to the television,
wherein said first power supply generates power to the first sub-system only when a button of the button module is pressed;
and

a second sub-system, disposed in the housing, comprising a second power supply for supplying power continuously to the second
sub-system, the second power supply comprising a rechargeable power device, the second sub-system generating a second signal
for controlling the television to perform a second operation,

wherein the second power supply is coupled to the first sub-system, and powers the first sub-system when a button of the button
module is pressed and a power of the first power supply is lower than a predetermined value,

wherein when the remote controller is not in use, the second power supply is connected to a charging transformer.

US Pat. No. 9,244,571

TOUCH SENSING DEVICE

MStar Semiconductor, Inc....

1. A touch sensing device, comprising:
a plurality of electrodes, disposed on a plane and partially in a sensing area on the plane;
a plurality of wires, respectively coupled to the electrodes, extending to outside the sensing area; and
a conductive shielding plate, electrically insulated from the wires, covering a portion of the wires outside the sensing area,
wherein each of the plurality of wires respectively comprises:
a plurality of first wires, respectively coupled to the electrodes; and
a second wire, coupled to the first wires, and
wherein, the second wire and the shielding plate are disposed at a same conductive layer.

US Pat. No. 9,235,297

CAPACITIVE SENSING APPARATUS AND METHOD APPLIED TO TOUCH SCREEN USING THE CAPACITIVE SENSING APPARATUS

MStar Semiconductor, Inc....

1. A capacitive touch sensing apparatus, comprising:
a protecting layer;
a sensing layer comprising a single layer, disposed under the protecting layer, for sensing a touch to generate a position
signal;

a direct-current (DC) common voltage signal layer electrically connected with a DC voltage for shielding against signal interference;
a liquid crystal display (LCD) panel; and
a display controller coupled to the DC common voltage signal layer for generating an alternating current source driving signal
as part of a panel control signal while driving the LCD panel, wherein a source displacement of the source driving signal
is symmetrical to the DC voltage,

wherein the DC voltage of the panel control signal is applied by the display controller to the LCD panel during sensing of
the touch to prevent the panel control signal from coupling to the position signal,

wherein the DC voltage is a DC signal of 0 volts,
wherein the capacitive touch sensing apparatus does not include a shielding layer disposed between the DC common voltage signal
layer and the sensing layer and the DC common voltage signal layer is directly attached below the sensing layer, and

wherein the LCD panel displays image data by dot inversion while driving the LCD panel.

US Pat. No. 9,223,740

DETECTION METHOD AND APPARATUS FOR HOT-SWAPPING OF SD CARD

MSTAR SEMICONDUCTOR, INC....

1. A method for detecting a hot-swapping status of a Secure Digital (SD) card in a linux operating system, comprising:
activating a polling thread at an application end corresponding to a user-interacting application when the user-interacting
application is activated, wherein the user-interacting application is running in a user mode and requiring the hot-swapping
status, wherein the polling thread for detecting the hot-swapping status of the SD card is disposed in the user mode;

transmitting an inquiry command to the SD card at a predetermined frequency;
receiving a current command return message replied in response to the inquiry command, wherein the current command return
message comprises information indicating whether the SD card is present;

determining the hot-swapping status according to a comparison of a previous command return message and the current command
return message;

replying the hot-swapping status to the user-interacting application;
deactivating the polling thread when the user-interacting application is terminated.

US Pat. No. 9,134,845

METHOD FOR MULTI-TOUCH CONTROL AND ASSOCIATED APPARATUS

MStar Semiconductor, Inc....

1. A multi-touch control method, comprising:
sensing a plurality of sensing values associated with a touch panel;
providing a threshold;
identifying two peak sensing values from the plurality of sensing values;
comparing each of the sensing values located between the two peak sensing values with the threshold to generate a comparison
result; and

selectively reporting a multi-touch event according to the comparison result,
wherein no multi-touch event is reported when the sensing values between the two peak sensing values are not lower than the
threshold, and

wherein the multi-touch event corresponding to the two peak sensing values is reported when at least one of the sensing values
between the two peak sensing values is lower than the threshold.

US Pat. No. 9,354,739

SELF-CAPACITIVE TOUCH CONTROL APPARATUS AND CONTROL METHOD THEREOF

MStar Semiconductor, Inc....

1. A control method for a self-capacitive touch control apparatus, the self-capacitive touch control apparatus comprising
a plurality of electrodes, the control method comprising:
a) detecting capacitance changes in the electrodes to generate sensing results;
b) calculating a total sensing amount according to the sensing results, and determining a number of touch points according
to the total sensing amount;

c) grouping the sensing results according to the number of touch points to generate a grouping result; and
d) generating position information of one or more touch points corresponding to the number of touch points according to the
grouping result and the sensing results,

wherein the number of touch points is determined by comparing the total sensing amount to a predetermined upper threshold
and a predetermined lower threshold.

US Pat. No. 9,276,592

MULTIMEDIA INTERFACE RECEIVING CIRCUIT

MStar Semiconductor, Inc....

1. A multimedia interface receiving circuit having multiple circuitry configurations, comprising:
a phase-locked loop (PLL), comprising a phase frequency detector, configured to generate a fundamental clock signal; and
four signal processing channels, each comprising:
an analog front-end circuit, configured to receive a respective input signal and to accordingly generate a processed signal;
a phase detecting circuit, configured to sample the processed signal to generate a sampled signal;
a demultiplexer, configured to convert the sampled signal to a demultiplexed signal;
a digital clock data recovery (DCDR) circuit, configured to perform a DCDR process on the demultiplexed signal to generate
corresponding phase adjustment information;

a phase adjusting circuit, configured to receive the phase adjustment information and the fundamental clock signal, and to
adjust a phase of the fundamental clock signal according to the phase adjustment information to generate a sampling clock
signal;

a multiplexer, configured to selectively transmit one of the fundamental clock signal and the sampling clock signal to the
phase detecting circuit according to the configuration of the multimedia interface receiving circuit;

in a High-Definition Multimedia Interface (HDMI) configuration:
one of the signal processing channels is disabled, and each of the other three signal processing channels receives one of
the respective input signals, and the PLL provides the fundamental clock signal to the other three signal processing channels;
and

in a DisplayPort (DP) configuration:
the PLL is configured so that when the PLL satisfies a lock condition, the phase frequency detector in the PLL is disabled,
and the PLL changes to be connected to receive the sampled signal generated by the phase detecting circuit in one of the four
signal processing channels in order to form an analog clock data recovery (ACDR) circuit to generate the fundamental clock
signal for the DP configuration that is provided to the other three signal processing channels.

US Pat. No. 9,274,657

SELF-CAPACITIVE TOUCH PANEL

MSTAR SEMICONDUCTOR, INC....

1. A self-capacitive touch panel, comprising: a plurality of sensors; a border region, wherein each unit area of the border
region comprises an R number of electrodes corresponding to a P number of first sensors among the plurality of sensors; and
a central region, wherein each unit area of the central region comprises an M number of electrodes corresponding to a Q number
of second sensors among the plurality of sensors; wherein, a ratio of R to P is greater than a ratio of M to Q, wherein R
and M are integers greater than 1, each of the P number of first sensors corresponds a plurality of first electrodes among
the R number of electrodes, the plurality of first electrodes have a first center of gravity, each of the Q number of second
sensors corresponds to a plurality of second electrodes among the M number of electrodes, and the plurality of second electrodes
have a second center of gravity; a first average distance between the first center of gravity and all possible touch points
in the plurality first electrodes is smaller than a second average distance between the second center of gravity and all possible
touch points in the plurality of second electrodes.

US Pat. No. 9,262,631

EMBEDDED DEVICE AND CONTROL METHOD THEREOF

MSTAR SEMICONDUCTOR, INC....

1. A control method for an embedded device, comprising:
performing a boot procedure before executing a program code;
wherein, the boot procedure comprises:
duplicating data-to-be-authenticated to an external random access memory (RAM); and
generating a predetermined digital signature by using the data-to-be-authenticated as an input;
executing the program code in the external random access memory (RAM);
authenticating data-to-be-authenticated comprising the program code, comprising:
generating a current digital signature by using the data-to-be-authenticated as an input; and
comparing the current digital signature with the predetermined digital signature; and
halting execution of the program code in the RAM when the current digital signature does not match the predetermined digital
signature;

wherein, the program code remains unchanged during operation; and
wherein, the current digital signature is a hash value, and the predetermined digital signature and an initial value are separately
stored in an integrated circuit and cannot be modified unless a reboot is performed or the integrated circuit is reset.

US Pat. No. 9,373,301

IMAGE PROCESSING DEVICE, IMAGE PROCESSING CHIP AND IMAGE PROCESSING METHOD

MSTar Semiconductor, Inc....

1. An image processing device, configured to process an image signal, comprising:
a circuit board;
a slot, disposed on the circuit board, to be plugged in by either a first connector corresponding to a first image interface
format or a second connector corresponding to a second image interface format; and

an image processing module, disposed on the circuit board and coupled to the slot, configured to detect the image signal inputted
from either the first connector or the second connector to determine a target image interface format, and to process the image
signal by an image processing method corresponding to the target image interface format,

wherein the first image interface format is High-Definition Multimedia Interface (HDMI) format, and the second image interface
format is DisplayPort interface format, and

wherein when the image processing module detects that the image signal provides a stable voltage as a voltage source at a
predetermined pin of the slot, the image processing module determines the target image interface format as HDMI format.

US Pat. No. 9,131,198

SIGNAL PROCESSING APPARATUS AND ASSOCIATED METHOD

MStar Semiconductor, Inc....

1. A signal processing apparatus, comprising:
an initial detecting module, for determining an initial carrier frequency offset of an input signal according to a spectrum
of the input signal;

a mixer, for adjusting the input signal according to the initial carrier frequency offset to generate a frequency-compensated
signal;

a symbol rate detecting module, for determining a symbol rate of the input signal;
a judging module, for performing a phase recovery on the frequency-compensated signal, and judges whether the initial carrier
frequency offset is correct as a judgement result according to whether the phase recovery renders a phase locking; and

a correcting module, coupled to the mixer, for selectively determining a corrected carrier frequency offset according to the
symbol rate and the spectrum and providing the corrected carrier frequency offset to the mixer based on the judgment result,

wherein when the judgment result of the judging module is negative, the correcting module selects a frequency segment having
a width corresponding to the symbol rate from the spectrum, and renders the corrected carrier frequency offset with a difference
between a center frequency of the frequency segment and a reference frequency.

US Pat. No. 9,363,503

IMAGE ACCESS METHOD AND IMAGE ACCESS APPARATUS

MStar Semiconductor, Inc....

1. An image access method, applied to an image access apparatus, comprising:
a) obtaining K sets of access settings; wherein, K is a positive integer, each set of the K sets of settings corresponds to
a code arrangement combination composed of a plurality of codes respectively representing a plurality of image sources; and

b) accessing, from a storage device and via a loader of the image access apparatus, data of the image sources respectively
represented by the codes sequentially according to the K sets of access settings,

wherein step (b) comprises:
when accessing the data of the image sources respectively represented by the codes sequentially according to the code arrangement
combination corresponding to an Xth set of access settings of the K sets of access settings, calculating a number of the codes in the code arrangement combination
to generate a counting result, where X is a positive integer not greater than K; and

obtaining the code arrangement combination corresponding to the Xth set of access settings according to the counting result, and accessing the data of the image source represented by the codes
for a W number of times, where W is associated with a width of an output image.

US Pat. No. 9,258,081

HIGH DYNAMIC RANGE AMAM PREDISTORTION

MStar Semiconductor, Inc....

1. An apparatus to receive a plurality of input in-phase (I) and quadrature (Q) data words provided from respective I and
Q data channels, the apparatus comprising:
a digital power amplifier configured to generate a radio-frequency (RF) analog signal in accordance with a sequence of predistorted
digital I and Q data words generated from the respective input I and Q data words and configured to generate maximum current
when an input data word provided thereto is a full scale value; and

a predistortion processor, comprising:
a multiplicative stage to evaluate a predetermined predistortion function with each of the input I and Q data words as arguments
to generate computed I and Q data words;

an additive stage to respectively generate additive I and Q data words, wherein the additive stage comprises a lookup table
stored in a memory and containing the additive I and Q data words indexed by the respective input I and Q data words; and

an adder to add the additive I and Q data words to the respective computed I and Q data words to produce corresponding predistorted
I and Q data words that compose the sequence of predistorted digital I and Q words used to generate the RF analog signal.

US Pat. No. 9,185,340

DISPLAY METHOD AND ASSOCIATED APPARATUS

MSTAR SEMICONDUCTOR, INC....

1. A display method, applied to a display apparatus, the display apparatus configured to receive a display frame having an
output width-height ratio and display an image frame according to a screen width-height ratio different from the output width-height
ratio; the display method comprising:
obtaining an image region and a subtitle region from the display frame;
generating a subtitle according to the subtitle region;
generating the image frame according to the image region; and
displaying the image frame and subtitle;
wherein the image region and the subtitle region are pixel-based; and
wherein the step of obtaining an image region and a subtitle region from the display frame comprises:
acquiring a plurality of horizontal sections from the display frame according to a predetermined horizontal axis;
identifying in the horizontal sections having a concentrated distribution of grayscale values; and
obtaining the subtitle region from the display frame according to at least one of the horizontal sections displaying the concentrated
distribution.

US Pat. No. 9,304,708

DATA ACCESSING METHOD AND ELECTRONIC APPARATUS UTILIZING THE DATA ACCESSING METHOD

MStar Semiconductor, Inc....

1. A data access method applicable on an electronic apparatus comprising a first storage apparatus and a second storage apparatus,
the method comprising:
storing a first part of data and a second part of data of an image frame in the first storage apparatus and the second storage
apparatus, respectively, wherein the first storage apparatus comprises static random access memory and the second storage
apparatus comprises a stand alone memory device with different characteristics compared to the static random access memory;

selectively accessing the first storage apparatus and the second storage apparatus via different data access paths for the
first part of data and the second part of data;

classifying portions of the image frame to the first part of data and the second part of data in an alternative fashion before
the storing step; and

the accessing step comprising accessing the first storage apparatus and the second storage apparatus in an alternative fashion,
wherein access speed to the first storage apparatus is different from access speed to the second storage apparatus.

US Pat. No. 9,264,281

WIRELESS COMMUNICATION RECEIVER WITH I/Q IMBALANCE ESTIMATION AND CORRECTION TECHNIQUES

MStar Semiconductor, Inc....

1. A wireless communication receiver, comprising:
a radio frequency (RF) front end configured to be in communication with an antenna;
a digital baseband processing module in communication with the RF front end and, comprising:
a digital front end, comprising:
an I/Q imbalance estimation module that receives plurality of I/Q samples of a received baseband signal and calculates a number
of quantities characterizing properties of the plurality of I/Q samples of a received baseband signal; and

an I/Q imbalance correction module that applies a plurality of I/Q imbalance correction values to the plurality of the I/Q
samples of the received baseband signal;

a digital processing module, coupled to the digital front end, that generates a plurality of estimates characterizing gain
and phase imbalance according to at least part of the quantities characterizing at least part of the properties of the I/Q
samples of the received baseband signal, wherein the digital processing module uses the estimates characterizing the gain
and the phase imbalance to calculate a configuration of generation of the I/Q imbalance correction values and supplies the
same to the I/Q imbalance correction module,

wherein the I/Q imbalance correction module generates one set of the I/O imbalance correction weights on one block of the
I/Q samples according to one set of the estimates of the gain and the phase imbalance calculated from a set of quantities
of another one block of the I/Q samples.

US Pat. No. 9,195,582

DATA STORING METHOD AND APPARATUS APPLIED TO FLASH MEMORY STORAGE DEVICE

MStar Semiconductor, Inc....

1. A method for storing data into a flash memory storage device, the flash memory storage device comprising a plurality of
storage units, the method comprising:
identifying a first tag, the first tag pointing to a storage unit storing a first data and the first data being a newly updated
data;

locating the storage unit storing the first data according to the first tag;
storing a second data to another storage unit;
pointing the first tag to the another storage unit storing the second data; and
rendering a second tag pointing to all remaining storage units apart from the another storage storing the second data,
wherein the step of pointing the first tag to the another storage unit storing the second data comprises:
modifying a storage position of the first tag such that the modified first tag points to the another storage unit storing
the second data, and

wherein:
a number of the storage units of the flash memory storage device is a first number, each storage unit comprises a second number
of bytes, a first storage unit of the first number of storage units comprises the first number of bytes for respectively storing
the first tag and the second tag, and the second number is greater than the first number;

in the first storage unit, relative positions of the first number of bytes for respectively storing the first tag and the
second tag respectively correspond to relative positions of first number of storage units;

a byte of the storage unit storing the first data is for storing the first tag while all other remaining bytes are for storing
another second tag, and a content of the byte corresponding to the first tag differs from a content of the bytes corresponding
to the second tag; and

the step of identifying the first tag and locating the storage unit storing the first data according to the first tag comprises:
checking one after another from a first byte of the first storage unit, and confirming a relative position of the identified
tag among the first number of consecutive bytes of the first storage unit upon identifying the byte storing the first tag;
and

confirming the relative position of the identified byte corresponding to the storage unit of the first number of storage units
is the storage unit storing the first data.

US Pat. No. 9,263,998

BROADBAND SINGLE-ENDED INPUT TO DIFFERENTIAL OUTPUT LOW-NOISE AMPLIFIER

MStar Semiconductor, Inc....

1. An amplifier comprising:
a pair of transistors each having a pair of input terminals between which an input voltage signal is applied and each having
a pair of output terminals between which a current flows in proportion to the input voltage signal, the input terminals and
the output terminals sharing a common terminal such that each of the input terminals and the output terminals comprise the
common terminal and a corresponding non-common terminal;

a feedback circuit electrically connected at opposite ends thereof between the non-common output terminal and the non-common
input terminal of a closed-loop one of the transistors, the opposite ends of the feedback circuit being electrically disconnected
from any two terminals of an open-loop one of the transistors;

an input port comprising a signal-carrying input terminal and a ground terminal between which a single-ended input signal
is accepted, the input terminal of the input port being electrically connected to the non-common input terminal of both of
the transistors; and

an output port comprising a positive terminal and a negative terminal between which a differential output signal is provided,
the positive terminal of the output port being electrically connected to the non-common terminal of the open-loop transistor
and the negative terminal of the output port being electrically connected to the non-common output terminal of the closed-loop
transistor.

US Pat. No. 9,244,580

CAPACITIVE TOUCH CONTROL SYSTEM AND DRIVING APPARATUS THEREOF

MStar Semiconductor, Inc....

1. A driving apparatus, adopted to an electrode in a capacitive touch control system, the driving apparatus comprising:
a signal generating module, configured to generate a driving signal; and
an adjusting module, connected between the electrode and the signal generating module, that generates an adjusted signal according
to the driving signal to replace the driving signal, and that controls a rising edge or a falling edge of a waveform of the
adjusted signal such that a high-frequency component in the adjusted signal is less than that in the driving signal,

wherein the adjusting module comprises:
a reference voltage source, comprising a first voltage supply end and a second voltage supply end, a first voltage output
from the first voltage supply end being lower than a second voltage output from the second voltage supply end;

a first switch, connected between the first voltage supply end and the electrode, the first switch being turned on when the
driving signal is in a first state and being turned off when the driving signal is in a second state;

a charging current source, configured to supply a charging current;
a second switch, connected between the charging current and the electrode; and
an operational amplifier, comprising a positive input end, a negative input end and an output end, the positive input end
being connected to the electrode, the negative input end being connected to the second voltage supply end, the output end
configured to control the second switch;

wherein, the second switch is turned on when a voltage at the positive input end is lower than a voltage at the negative input
end, and is turned off when the voltage at the positive input end is higher than the voltage at the negative input end.

US Pat. No. 9,088,254

DIFFERENTIAL-TO-SINGLE-END CONVERTER

MSTAR SEMICONDUCTOR, INC....

1. A converter, for converting a differential input signal to a single-end output signal, comprising:
a first transistor and a second transistor, driven by the differential input signal, the first and second transistors having
two first conduction nodes coupled to each other and two second conduction nodes not coupled to each other;

a third transistor and a fourth transistor, driven by the differential input signal, respectively connected in series with
the first and second transistors;

a pair of current sources, respectively connected in series with the third and fourth transistors, having a common control
node coupled to the second conduction node of the first transistor;

wherein, the second conduction node of the second transistor generates the single-end output signal.

US Pat. No. 9,094,178

CORRECTING APPARATUS FOR TIMING RECOVERY OF RECEIVER AND METHOD THEREOF

MSTAR SEMICONDUCTOR, INC....

1. A correcting method for timing recovery of a receiver, the receiver comprising a timing recovery module that outputs a
first symbol and a second symbol, the correcting method comprising:
calculating channel impulse responses for the first symbol and the second symbol to obtain a first set of peak times and a
second set of peak times, respectively; and

calculating a correction signal according to a relationship between the first set of peak times and the second set of peak
times, and sending the correction signal to the timing recovery module.

US Pat. No. 9,277,273

VIDEO DATA CONVERSION METHOD, DEVICE AND SMART TV

MSTAR SEMICONDUCTOR, INC....

1. A video data conversion method, comprising:
capturing a video image currently played on a video source, and converting the video image into dynamic texture data having
a size and a format required by a three-dimensional (3D) engine;

transmitting the dynamic texture data to the 3D engine, so that the 3D engine generates a map from the dynamic texture data;
and

mapping the map to a 3D user interface (UI) to obtain a dynamic texture map.

US Pat. No. 9,277,167

COMPENSATION DE-INTERLACING IMAGE PROCESSING APPARATUS AND ASSOCIATED METHOD

MSTAR SEMICONDUCTOR, INC....

1. A motion compensation de-interlacing image processing apparatus, comprising:
a temporal motion compensation module, for generating a temporal interpolation pixel and a temporal motion vector quality
index according to a previous field and a next field associated with a target pixel to be interpolated;

a spatial motion compensation module, for generating a spatial interpolation pixel and a jaggy index according to a current
field associated with the target pixel; and

a motion compensation blending module, for generating the target pixel according to the temporal interpolation pixel, the
spatial interpolation pixel, the temporal motion vector quality index and the jaggy index.

US Pat. No. 9,246,526

CONVOLUTIONAL DEINTERLEAVING APPARATUS AND ASSOCIATED METHOD

MStar Semiconductor, Inc....

9. A convolutional deinterleaving method, comprising:
a) storing a plurality of sets of data into a memory according to a deinterleaving rule, the plurality of sets of data being
of a same group;

b) selecting a representative channel state indicator according to an N number of channel state indicators corresponding to
an N number of sets of data of the group, wherein the N number of sets of data of the same group correspond to a same carrier
frequency, where N is an integer greater than 1; and

c) storing the representative channel state indicator into the memory,
wherein the memory comprises a data buffer, a first indicator buffer and a second indicator buffer; step (a) comprises storing
a plurality of sets of first data corresponding to a first carrier frequency and a plurality of sets of second data corresponding
to a second carrier frequency into the data buffer; the first indicator buffer stores the representative channel state indicator
of the plurality of sets of first data, and the second indicator buffer stores another representative channel state indicator
of the plurality of sets of second data; and step (b) comprises determining update time points of the first indicator buffer
and the second indicator buffer according to a distribution mode of the plurality sets of first data and the plurality sets
of second data.

US Pat. No. 9,093,010

IMAGE PROCESSING METHOD AND IMAGE PROCESSING APPARATUS

MStar Semiconductor, Inc....

1. An image processing method, comprising:
receiving an image according to a first timing signal having at least one first active pixel time period, at least one first
horizontal blanking time period and a first vertical blanking time period; and

outputting the image according to a second timing signal having at least one second active pixel time period, at least one
second horizontal blanking time period and a second vertical blanking time period,

wherein a pixel number corresponding to the first active pixel time period equals to a pixel number corresponding to the second
active pixel time period, the second horizontal blanking time period is less than the first horizontal blanking time period,
and the second vertical blanking time period is larger than the first vertical blanking time period.

US Pat. No. 9,052,815

TOUCH SENSING DEVICE AND APPARATUS AND TOUCH SENSING METHOD

MSTAR SEMICONDUCTOR, INC,...

1. A touch sensing device, electrically connected to a touch panel, the touch panel comprising a plurality of first-direction
electrodes disposed on a first plane and a plurality of second-direction electrodes disposed on a second plane, and a dielectric
layer disposed between the first plane and the second plane, the touch sensing device comprising:
a multiplexer, electrically connected to the touch panel via the plurality of first-direction electrodes and the plurality
of second-direction electrodes, for selective voltage driving or voltage sensing the plurality of first-direction electrodes
and the plurality of second-direction electrodes according to an operating mode; and

a control unit, electrically connected to the multiplexer, for transmitting a control signal, transmitting a drive signal
to the multiplexer, and receiving a sense signal from the multiplexer in response to the operating mode;

wherein when the operating mode is an active mode, the multiplexer selects and voltage drives the plurality of first-direction
electrodes according to the control signal, and selects and voltage senses the plurality of second-direction electrodes; and
when the operating mode is an idle mode, the multiplexer selects and voltage senses at least one of the first-direction electrodes
according to the control signal, and selects and drives at least one of the second-direction electrodes.

US Pat. No. 9,300,507

LOCAL OSCILLATION GENERATOR AND ASSOCIATED COMMUNICATION SYSTEM AND METHOD FOR LOCAL OSCILLATION GENERATION

MSTAR SEMICONDUCTOR, INC....

1. A local oscillation generator, applied to a communication system, for providing a local oscillation signal, the local oscillation
generator comprising:
an oscillation circuit, configured to provide a fundamental oscillation signal with a fundamental frequency;
a frequency multiplication circuit, coupled to the oscillation circuit, configured to multiply the fundamental oscillation
signal to generate a first oscillation signal with a first frequency;

a mixer, coupled to the oscillation circuit and the frequency multiplication circuit, said mixer receiving the fundamental
oscillation signal and the first oscillation signal, and configured to provide a mixed oscillation signal with a mixer frequency
according to the fundamental oscillation signal and the first oscillation signal; and

a frequency divider, coupled to the mixer, configured for frequency-dividing the mixed oscillation signal to provide a frequency-divided
signal with a divider frequency.

US Pat. No. 9,287,912

MULTIMODE RECEIVER WITH COMPLEX FILTER

MStar Semiconductor, Inc....

1. A radio frequency (RF) receiver comprising:
a first set of mixers receiving an RF signal according to a first communication mode;
a second set of mixers receiving the RF signal according to a second communication mode;
wherein one of the first set and the second set of mixers comprises a first mixer and a second mixer,
wherein a resistance circuit is disposed, and is always in a signal path, between each of the first mixer and the second mixer
and a low noise amplifier (LNA),

the RF receiver further comprising:
a digital filter, including a complex filter coefficient, coupled to an output of one of the first and second set of mixers,
wherein the digital filter has asymmetrical frequency response,

wherein the complex filter coefficient is set dynamically,
wherein the one of the first and second set of mixers to which the digital filter is coupled is coupled to a polyphase reactive
circuit, and

the RF receiver further comprising an additional filter including the polyphase reactive circuit, wherein the frequency response
of the digital filter compensates for a frequency response of the additional filter.

US Pat. No. 9,191,195

CIRCUIT AND METHOD FOR CALCULATING ERROR OF SAMPLING CLOCK, AND SIGNAL RECEIVING CIRCUIT AND METHOD

MSTAR SEMICONDUCTOR, INC....

1. A circuit for calculating an error of a sampling clock according to a first sample data group and a second sample data
group, each of the first sample data group and the second sample data group including a header having a first predetermined
sequence, the circuit comprising:
a correlation circuit, configured to respectively perform a correlation operation on the first sample data group and the second
sample data group with the first predetermined sequence to obtain a first correlation result and a second correlation result;

a comparison circuit, coupled to the correlation circuit, configured to compare the first correlation result and the second
correlation result to generate a sample data group offset; and

a calculation circuit, coupled to the comparison circuit, configured to generate the error of the sampling clock according
to the sample data group offset and a time difference between the first sample data group and second sample data group;

wherein the first correlation result comprises a first maximum correlation value, the second correlation result comprises
a second maximum correlation value, and the comparison circuit generates the sample data group offset according to offsets
of the first maximum correlation value and the second maximum correlation value.

US Pat. No. 9,164,798

METHOD, APPARATUS AND COMPUTER FOR LOADING RESOURCE FILE FOR GAME ENGINE

MSTAR SEMICONDUCTOR, INC....

1. A method for loading a resource file for a game engine, comprising:
activating a thread to preload a predetermined resource file, wherein the predetermined resource file comprises a texture
resource file and one or both of a structure resource file and a model resource file; and

accessing a header of one or both of the structure resource file and the model resource file to obtain a predetermined address
of a plurality of structs in one or both of the structure resource file and the model resource file, wherein the structs are
obtained from dividing one or both of the structure resource file and the model resource file and have a consistent recording
method as the game engine records corresponding resources in a memory;

mapping one or both of the structure resource file and the model resource file comprising the structs to the predetermined
address;

accessing all of the structs in one or both of the structure resource file and the model resource file after having mapped
to the predetermined address; and

cancelling a mapping relationship between one or both of the structure resource file and the model resource file comprising
the structs and the predetermined address after having accessed all of the structs in one or both of the structure resource
file and the model resource file to complete loading one or both of the structure resource file and the model resource file.

US Pat. No. 9,268,680

ELECTRONIC APPARATUS WITH COMPRESSED DATA STORAGE AND CONTROL METHOD THEREOF

MStar Semiconductor, Inc....

1. An electronic device, comprising:
a read-only memory (ROM) that stores a plurality of sets of compressed data corresponding to a plurality sets of uncompressed
data, wherein the plurality sets of uncompressed data are divided from one same set of original data;

a random access memory (RAM);
a processing module, coupled to the ROM and the RAM;
a demand paging module that receives a request from the processing module and upon determining that the request is aiming
at one set of the compressed data that only corresponds to one set of the uncompressed data of the original data, selects
only the one set of the compressed data; and

a decompression module, coupled to the demand paging module, that decompresses and stores the one set of compressed data selected
by the demand paging module to the RAM for use by the processing module,

wherein the RAM comprises a memory section for storing a set of decompressed data generated from decompressing the selected
one set of compressed data by the decompression module;

the processing module dynamically adjusts a size of the memory section, and
wherein the processing module dynamically adjusts a size of the memory section based on priority of an application associated
with the set of compressed data.

US Pat. No. 9,135,676

IMAGE INTERPOLATION PROCESSING APPARATUS AND METHOD THEREOF

MStar Semiconductor, Inc....

1. An image interpolation processing apparatus, comprising:
a motion vector generator configured to generate a first reference motion vector and a second reference motion vector for
an interpolated block of an interpolated frame according to the interpolated block and a plurality of blocks adjacent to the
interpolated block, the interpolated frame being interpolated between a previous original image frame and a next original
image frame, wherein: to generate the first reference motion vector and the second reference motion vector, the motion vector
generator is configured to: calculate a value curve as a plurality of motion vector variances with respect to an original
motion vector of the interpolated block and a plurality of original motion vectors of the plurality of adjacent blocks; select
a maximum value of the plurality of motion vector variances of the value curve; and determine a first block and a second block
of the plurality of adjacent blocks corresponding to a minimum value on the left side of the maximum value of the value curve
and a minimum value on the right side of the maximum value of the value curve, respectively, wherein the first reference motion
vector and the second reference motion vector correspond to an original motion vector of the first block and an original motion
vector of the second block, respectively;

a blurred block processor configured to determine an area property for the interpolated block as being one of an image covered
area, an image uncovered area and a non-blurred area according to the first reference motion vector and the second reference
motion vector, wherein an image covered area is a background image area visible in the previous original image frame but covered
by a foreground object in the next original image frame, an image uncovered area is a background image area covered in the
previous original image frame by a foreground object but visible in the next original image frame, and a non-blurred area
is a background image area visible in both the previous and next original image frames, the blurred block processor being
further configured to determine a representative motion vector for the interpolated block as being one of the first reference
motion vector and the second reference motion vector, wherein the blurred block processor comprises:

a covered/uncovered block and motion vector processor configured to: respectively determine a first block and a second block
corresponding to the interpolated block from the previous original image frame and the next original image frame according
to the first reference motion vector; respectively determine a third block and a fourth block corresponding to the first block
and the second block from respective previous original image frames of the first block and the second block according to the
second reference motion vector; respectively determine a fifth block and a sixth block corresponding to the first block and
the second block from respective next original image frames of the first block and the second block according to the second
reference motion vector; and calculate differences of corresponding blocks to determine the area property of the interpolated
block as being one of the image covered area, the image uncovered area and non-blurred area, and to determine the representative
motion vector of the interpolated block as being one of the first reference motion vector and the second reference motion
vector; and

a frame interpolator configured to generate the interpolated block according to the representative motion vector and the area
property.

US Pat. No. 9,330,487

APPARATUS AND METHOD FOR PROCESSING 3D IMAGES THROUGH ADJUSTMENT OF DEPTH AND VIEWING ANGLE

MStar Semiconductor, Inc....

1. A three-dimensional (3D) image processing apparatus, comprising:
a motion estimation module that estimates a motion vector between a first object in a first-eye image and a second object
in a second-eye image, the first object being at least similar to the second object; and

a motion interpolation module that multiplies the motion vector by a first shift ratio, for moving the first object in the
first-eye image, to generate a first motion vector, and generating a modified first-eye image by interpolation according to
the first motion vector and the first-eye image and further multiplies the motion vector by a second shift ratio to generate
a second motion vector, and generates a modified second-eye image by interpolating according to the second motion vector and
the second-eye image, wherein a sum of the first shift ratio and the second shift ratio is 1,

wherein the first-eye image is one of a right-eye image and a corresponding left-eye image, and the second-eye image is the
other of the right-eye image and the corresponding left-eye image,

wherein, when viewed, the first-eye image and the second-eye image are combined into a 3D image, and
wherein the modified first-eye image is one of another right-eye image and another corresponding left-eye image which, when
viewed, are combined into another 3D image.

US Pat. No. 9,312,882

METHOD AND DEVICE FOR STORING AND DECODING HYBRID AUTOMATIC REPEAT REQUEST TRANSMISSION BLOCK

MSTAR SEMICONDUCTOR, INC....

1. A method for storing a hybrid automatic repeat request (HARQ) transmission block, comprising:
obtaining the HARQ transmission block during a downlink signal transmission, wherein the transmission block comprises at least
one code block;

storing the code block of the at least one code block that cannot be correctly decoded to a divided storage space of a buffer,
wherein the storage space of the buffer is dynamically divided in a unit of code blocks;

recording starting addresses of the code block stored during a first time and during a second time in the storage space of
the buffer, respectively;

obtaining a bit of the code block transmitted during a third time;
obtaining bits of the code block stored during the first time and during the second time according to the recorded starting
addresses of the code block stored during the first time and the second time in the storage space of the buffer, respectively;
and

combining the obtained bits of the code block stored during the first time and during the second time with the obtained bit
of the code block transmitted during the third time in a pack buffer to decode the code block;

wherein, when the storage space of the buffer is dynamically divided in a unit of code blocks before obtaining the at least
one code block, the storage space of the buffer is dynamically divided in a unit of a largest code block; and

wherein, when the storage space of the buffer is dynamically divided in a unit of code blocks after obtaining the at least
one code block, the storage space of the buffer is dynamically divided in a unit of a code block that cannot be correctly
decoded.

US Pat. No. 9,191,182

DATA TRANSMISSION METHOD AND ASSOCIATED SIGNAL TRANSMITTER

MStar Semiconductor, Inc....

1. A signal transmission method, suitable for a signal transmitter, comprising:
providing a plurality of clock signals with different phases;
selecting some of the clock signals as a plurality of intermediate signals;
transmitting the intermediate signals to a signal output circuit of the signal transmitter via a clock distribution network;
and

selecting one of the intermediate signals as a reference clock of the signal output circuit to output a set of data.

US Pat. No. 9,280,232

TOUCH DETECTION METHOD AND ASSOCIATED APPARATUS

MStar Semiconductor, Inc....

1. A touch detection method, for detecting a touch point on a display device, comprising:
providing a display signal, according to which the display device has two parts of a vertical blanking interval within each
frame period, wherein the two parts of the vertical blanking interval are discontinuous; and

performing a touch detection in the two parts of the vertical blanking interval, respectively,
wherein the display device comprises an N number of rows of pixels, a first part of vertical blanking interval of the two
parts of the vertical blanking interval is between the display device updates Mth-row pixels and the display device updates (M+1)th-row pixels, N and M are positive integers, and M is smaller than N.

US Pat. No. 9,191,662

DISPLAY APPARATUS AND ASSOCIATED GLASSES

MStar Semiconductor, Inc....

1. A display apparatus, comprising:
a display, operating in a three-dimension (3D) mode or a two-dimension (2D) mode, that displays a 3D image content when operating
in the 3D mode, and displays a 2D image content when operating in the 2D mode;

a controller that controls the display to operate in one of the 3D mode and the 2D mode and generates a remote control signal
to control a pair of glasses, the remote control signal including an identification instruction requesting for an identification
code of the pair of glasses, the remote control signal further including both of audio data to be audibly played by the pair
of glasses and vibration data configured to cause the pair of glasses to vibrate;

a transmitting circuit configured to transmit the remote control signal to the pair of glasses; and
a receiving circuit that receives a status signal from the pair of glasses, the status signal indicating the identification
code of the pair of glasses and an indication of a power supply status of the pair of glasses that allows the display to show
the power supply status to the user by on-screen display (OSD),

wherein the 3D image content carries at least one set of a left frame and a right frame, each set forms a 3D image, and
wherein the display apparatus further comprises:
an image processing module that retrieves the 2D image content from the 3D image content; and
a format converting module that extracts the at least one set of the left frame and the right frame from the 3D image content,
and selects one frame from each set of left and right frames to form the 2D image content,

wherein the display apparatus automatically displays the 2D image content when the status signal indicates power supply for
the pair of glasses is interrupted, and

wherein the display apparatus is configured to record a plurality of operating parameters for a plurality of pairs of glasses
including predetermined audio volumes for speakers in respective pairs of glasses.

US Pat. No. 9,128,603

HAND GESTURE RECOGNITION METHOD FOR TOUCH PANEL AND ASSOCIATED APPARATUS

MStar Semiconductor, Inc....

1. A hand gesture recognition method applied to a touch panel comprising a plurality of sensors, each of the sensors generating
a respective sensing value according to a touch operation, the method comprising:
providing a first reference value, a second reference value, and a threshold value;
generating a count value by counting a total quantity of the sensing values of the sensors on at least one axis of the touch
panel that are greater than the threshold value without determining a number of peaks corresponding to touched points;

determining the touch operation as a first hand gesture when the count value is greater than the first reference value but
smaller than the second reference value; and

determining the touch operation as a second hand gesture when the count value is greater than the second reference value.

US Pat. No. 9,355,744

DYNAMIC MEMORY SIGNAL PHASE TRACKING METHOD AND ASSOCIATED CONTROL CIRCUIT

MSTAR SEMICONDUCTOR, INC....

1. A dynamic memory signal phase tracking method, applied to a memory controller that accesses a memory module, the method
comprising:
issuing a first memory access command and a first access request to an arbiter to request for a first access right of the
memory module;

issuing a second memory access command and a second access request to an arbiter to request for a second access right of the
memory module;

when the first access right is obtained, forwarding the first memory access command to the memory module and asserting a flag
signal;

during a period of asserting the flag signal, sequentially using a plurality of candidate delay phases to adjust a memory
signal for latching test data from the memory module, determining a delay phase according to latching results corresponding
to the plurality of candidate delay phases, and recording the determined delay phase;

updating an optimal delay phase according to the recorded determined delay phase; and
accessing the memory module according to the updated optimal delay phase.

US Pat. No. 9,310,997

METHOD, TOUCH DEVICE AND COMPUTER PROGRAM PRODUCT FOR CONVERTING TOUCH POINTS INTO CHARACTERS

MSTAR SEMICONDUCTOR, INC....

1. A method for converting at least one touch point into a character, applied to an input interface of a touch device comprising
a processor and a non-transitory computer-readable storage medium, the method comprising:
sensing the at least one touch point triggered by a user on the input interface to obtain a first touch point number information
and a first touch point position information, wherein a touch point corresponds to a discrete single position;

determining whether the first touch point number information matches with a predetermined touch point number information representative
of an input character;

determining whether the first touch point position information matches with a predetermined touch point position information
representative of the input character, wherein the first touch point position information comprises an angle and a distance;
and

determining the sensed touch point to be the input character based on a determination that the first touch point number information
matches with the predetermined touch point number information representative of the input character and a determination that
the first touch point position information matches with the predetermined touch point number information and the predetermined
touch point position information representative of the input character;

wherein, said predetermined touch point number information and said predetermined touch point position information representative
of the input character are contained in a lookup table.

US Pat. No. 9,219,627

CIRCUIT AND METHOD FOR TRANSMITTING OR RECEIVING SIGNAL

MStar Semiconductor, Inc....

6. A signal transceiving circuit, comprising:
a receiving path, configured to convert a first analog radio frequency (RF) input signal to a digital intermediate frequency
(IF) input signal and output the digital IF input signal, wherein the first analog RF input signal comprises a first signal
component conforming to a first wireless transmission standard and a second signal component conforming to a second wireless
transmission standard, and the digital IF input signal is outputted to be processed according to the first wireless transmission
standard and the second wireless transmission standard, respectively;

a first digital down converter, configured to receive and process the digital IF input signal to generate a first digital
baseband signal corresponding to the first signal component;

a second digital down converter, configured to receive and process the digital IF input signal to generate a second digital
baseband signal corresponding to the second signal component;

a first baseband processing module, configured to process the first digital baseband signal according to the first wireless
transmission standard or output a third digital baseband signal conforming to the first wireless transmission standard;

a second baseband processing module, configured to process the second digital baseband signal according to the second wireless
transmission standard or output a fourth digital baseband signal conforming to the second wireless transmission standard;

a first digital up converter, configured to receive and process the third digital baseband signal to generate a third digital
IF signal;

a second digital up converter, configured to receive and process the fourth digital baseband signal to generate a fourth digital
IF signal; and

a transmitting path, configured to convert the third digital IF signal to a third analog output signal and output the third
analog output signal, or convert the fourth digital IF signal to a fourth analog output signal and output the fourth analog
output signal.

US Pat. No. 9,046,953

CONTROL SYSTEM FOR TOUCH SCREEN

MSTAR SEMICONDUCTOR, INC,...

1. A control system for a touch screen, the touch screen comprising a screen and a touch sensor, the control system comprising:
a screen controller, for generating a common voltage to the screen, the common voltage varying within a first signal range;
a voltage-level shifter, having an input terminal and an output terminal, the input terminal being coupled to the common voltage;
the voltage-level shifter providing a timing signal at the output terminal according to the common voltage, the timing signal
varying within a second signal range, the first signal range being different from the second signal range; and

a touch controller, coupled to the output terminal, for controlling the touch sensor according to the timing signal;
wherein said common voltage is directly coupled to an AC coupling circuit of said voltage-level shifter.

US Pat. No. 9,093,985

PORTABLE CONTROL APPARATUS AND METHOD THEREOF FOR CALIBRATING AN OSCILLATING CIRCUIT

MStar Semiconductor, Inc....

1. A control apparatus, applied to a portable multi-media apparatus, comprising:
a driver, comprising:
an oscillating circuit, that generates a feedback signal and receives a calibration signal, the oscillating circuit further
configured to determine an operating frequency based at least in part on a calibration value indicated in the calibration
signal by way of selecting a corresponding set of a fine-tuning circuit,

an image processing unit, coupled to the oscillating circuit, that generates a display control signal according to the operating
frequency and provides the display control signal to a display of the portable multi-media apparatus, the image processing
unit configured to generate the display control signal such that an offset between a frequency of the display control signal
and a predetermined frequency is smaller than a predetermined error to meet operating requirements of the portable multi-media
apparatus;

a baseband controller, coupled to the driver, that receives the feedback signal and outputs the calibration signal to the
driver according to the feedback signal, wherein a frequency of the feedback signal is correlated to the operating frequency;
and

a crystal oscillator, coupled to the baseband controller, that provides a reference output frequency to the baseband controller,
the reference output frequency being used for generating the calibration signal,

wherein the display apparatus provides a user interface that presents an option of performing a calibration process resulting
in generating the calibration signal, and

wherein the baseband controller comprises a look up table and the baseband controller is configured to search for a calibration
code corresponding to the calibration value, the calibration code controlling the fine-tuning circuit.

US Pat. No. 9,092,372

MEMORY ACCESS AUTHORITY CONTROL METHOD AND MEMORY MANAGEMENT SYSTEM THEREOF

MStar Semiconductor, Inc....

1. A memory access authority control method, applicable to a memory comprising a command address space and a service address
space, the command address space storing a plurality of caller programs corresponding to a plurality of non-overlapped program
counter value intervals, respectively, the service address space storing a plurality of non-overlapped permissible access
intervals corresponding to the plurality of caller programs, respectively, the memory access authority control method comprising:
accessing a first caller program among the plurality of caller programs in the command address space according to a current
program counter value stored in a program counter;

querying a look-up table for a first permissible access interval in the service address space according to the current program
counter value, wherein the look-up table stores a plurality of mapping relationships between the plurality of program counter
intervals and the plurality of permissible access intervals in the service address space;

determining whether an access target address of the first caller program falls in the first permissible access interval to
generate a result; and

determining whether to permit an access of the first caller program to the service address space according to the result.

US Pat. No. 9,319,581

IMAGE EDITING METHOD AND ASSOCIATED APPARATUS

MSTAR SEMICONDUCTOR, INC....

1. An image editing method, for editing an original image derived from an image capture apparatus comprising an aperture,
a lens, and an optical sensor, the original image at least having a distinct figure and an indistinct figure respectively
corresponding to an in-focus object and an out-of-focus object, the image editing method comprising:
obtaining an out-of-focus object distance from the out-of-focus object to the lens;
performing an inverse blurring process on the indistinct figure according to the out-of-focus object distance and an optical
parameter to obtain a processed figure, said performing the inverse blurring process comprising:

obtaining a blurring convolution function according to a focal length of the lens, the aperture, the out-of-focus object distance
and the position of the optical sensor;

deducing an inverse blurring function according to the blurring convolution function; and
processing the indistinct figure according to the inverse blurring function to obtain the processed figure; and
forming a processed image according to the processed figure and the distinct figure, comprising:
forming said processed image containing the processed figure and the distinct figure by replacing the indistinct figure in
the original image with the processed figure.

US Pat. No. 9,313,057

TARGET SIGNAL DETERMINATION METHOD AND ASSOCIATED APPARATUS

MSTAR SEMICONDUCTOR, INC....

1. A method using delay correlation for determining whether an input signal is a target signal implemented in a signal receiving
electronic device with a non-transitory computer-readable storage medium storing an executable program, comprising:
receiving the input signal by the signal receiving electronic device;
sampling the input signal to generate 2N sample values, wherein the period of the sample values is N, where N is a positive
integer;

obtaining a first value according to a first operation method by processing the 2N sample values by the signal receiving electronic
device instructed by the executable program stored in the non-transitory computer-readable storage medium;

obtaining a second value according to a second operation method by processing the 2N sample values by the signal receiving
electronic device instructed by the executable program stored in the non-transitory computer-readable storage medium;

obtaining a determination value according to a ratio of the first value and the second value, wherein the determination value
is a quotient of the first value divided by the second value, and the second value equals ?k=?NN-1|r(t?N?k)|2 where r(t) is a sample value at time t; and

determining whether the input signal is the target signal or not according to the determination value and a threshold; and
continuing to receive said input signal if said input signal is determined to be said target signal, otherwise, discontinuing
receipt of said input signal.

US Pat. No. 10,185,336

RECEIVER AND METHOD FOR CONTROLLER RECEIVER

MSTAR SEMICONDUCTOR, INC....

1. A receiver, comprising:a bias current source, powered by a first voltage source, generating a bias current according to a second voltage source, wherein the first voltage source is higher than the second voltage source;
a comparator, coupled to the bias current source, comparing two input signals to generate a comparison signal according to the bias current; and
an output circuit, coupled to the comparator, powered by the second voltage source to generate an output signal according to the comparison signal, wherein the output signal and the second voltage source belong to a same power domain,
wherein the two signals received by the comparator are respectively an input signal from an external circuit and a reference voltage, and
wherein the comparison signal has a common mode voltage, and the reference voltage is equal to the common mode voltage.

US Pat. No. 9,215,437

PASSIVE 3D IMAGE SYSTEM AND IMAGE PROCESSING METHOD THEREOF

MSTAR SEMICONDUCTOR, INC....

1. A passive 3D image system, for receiving an original image comprising N rows of original data, the original image being
a left-eye image or a right-eye image, N being a positive even integer, the passive 3D image system comprising:
a passive 3D image display module, comprising a polarizing film;
a scaling module, for generating a scaled image comprising N/2 rows of scaled data according to the N rows of original data,
wherein the scaled data is generated by the scaling module according to a first original data and a second original data,
and the luminance of the scaled data is adjusted according to an average luminance and a larger luminance of the first original
data and the second original data; and

a luminance adjusting module, for adjusting the N/2 rows of scaled data to increase a luminance of the scaled image according
to the N rows of original data;

wherein, the adjusted scaled image comprises N/2 rows of processed data, and is displayed by the passive 3D image display.

US Pat. No. 9,223,739

DETECTION METHOD AND APPARATUS FOR HOT-SWAPPING OF SD CARD

MSTAR SEMICONDUCTOR, INC....

1. A method for detecting hot-swapping of a Secure Digital (SD) card in a Linux® operating system, comprising:
detecting whether a card reader is plugged to the Linux® operating system;
activating a Linux® operating system kernel mode polling thread corresponding to the card reader on a one-on-one basis and
transmitting an inquiry command to the SD card in the card reader at a predetermined frequency when it is detected that the
card reader is plugged to the Linux® operating system;

receiving a current command return message replied in response to the inquiry command, wherein the current command return
message comprises information indicating whether the SD card is present;

determining whether the SD card has been newly removed or newly plugged in since the prior cycle of said predetermined frequency
according to a comparison of a previous command return message and the current command return message;

when the previous command return message indicates the presence of the SD card and the current command return message indicates
the absence of the SD card, determining that the SD card is newly removed and clearing information associated with the SD
card from the procfs process filesystem and sysfs system filesystem of the Linux® operating system and transmitting KOBJ_REMOVE
event through a uevent file; and

when the previous command return message indicates the absence of the SD card and the current command return message indicates
the presence of the SD card, determining that the SD card is newly plugged in and recording the information associated with
the SD card in the procfs process filesystem and sysfs system filesystem of the Linux® operating system and transmitting a
KOBJ_ADD event.

US Pat. No. 9,160,591

SIGNAL PROCESSING METHOD AND ASSOCIATED DEVICE, AND METHOD FOR DETERMINING WHETHER SPECTRUM OF MULTICARRIER SIGNAL IS REVERSED

MStar Semiconductor, Inc....

1. A signal processing device, comprising:
an analog-to-digital converter (ADC), configured to convert an analog signal to a digital signal;
a conversion circuit, configured to convert the digital signal from time domain to frequency domain, the digital signal converted
to frequency domain comprising a plurality of sets of data exhibiting a predetermined order, wherein the predetermined order
is associated with frequencies respectively corresponding to the plurality of sets of data;

a calculation circuit, coupled to the conversion circuit, configured to perform a correlation operation according to the data
and the predetermined order to generate a forward correlation result, to perform the correlation operation according to the
data and a reverse order of the predetermined order to generate a reverse correlation result, and to selectively generate
a control signal according to the forward correlation result and the reverse correlation result; and

a data processing circuit, coupled between the ADC and the conversion circuit, configured to process the digital signal in
time domain according to the control signal so that the data subsequently generated by the conversion circuit exhibits one
of the predetermined order and the reverse order.

US Pat. No. 9,093,037

METHOD AND ASSOCIATED APPARATUS FOR POWER-SAVING DISPLAY

MSTAR SEMICONDUCTOR, INC....

1. A method for power-saving display, applied to a display comprising a display characteristic, the display characteristic
associating a data luma value and a drive value to a target display luma value, the drive value relating to a light source
brightness, the method comprising:
providing a threshold drive value according to a light leakage characteristic of the display;
providing a reference curve according to the threshold drive value, for associating the target display luma value to a plurality
of sets of reference data luma values and reference drive values;

mapping a representative data luma value of a frame comprising a plurality of original data luma values and a corresponding
original drive value to the target display luma value according to the display characteristic;

obtaining a power-saving data luma value and a power-saving drive value from the plurality of sets of reference data luma
values and reference drive values associated with the reference curve; and

displaying the frame by applying a relationship between the power-saving data luma value and the representative data luma
value to each of the plurality of original data luma values.

US Pat. No. 9,086,961

REPAIR METHOD AND DEVICE FOR ABNORMAL-ERASE MEMORY BLOCK OF NON-VOLATILE FLASH MEMORY

MSTAR SEMICONDUCTOR, INC....

1. A method for repairing an abnormal-erase memory block of a non-volatile flash memory, comprising:
scanning bit data in a first to-be-read page of a block, wherein said block comprises said first to-be-read page and a second
to-be-read page;

determining whether the first page is in an abnormal-erase status; and
setting bits in the first page from logic “0” to logic “1”, and then erasing both the first to-be-read page and the second
to-be-read page when the first page is in the abnormal-erase status;

wherein, the second to-be-read page is un-scanned.

US Pat. No. 9,077,420

RF RECEIVER WITH SIDEBAND SYMMETRY CIRCUIT

MStar Semiconductor, Inc....

1. A radio frequency (RF) receiver comprising: a first mixer receiving an RF signal; a second mixer receiving the RF signal;
a resonant circuit coupled to an input of the second mixer; a direct current circuit coupled to an output of the first mixer
to inject a direct current thereto,
wherein a resonant frequency of the resonant circuit is set at a frequency such that a voltage on the output of the second
mixer is a predetermined voltage,

wherein the resonant circuit comprises a switch capacitor, and the frequency of the resonant circuit is set by changing a
switching state of the switch capacitor, and

wherein the switch capacitor is a first switch capacitor, and the resonant circuit further comprises a second switch capacitor;
wherein a capacitance of the first switch capacitor is twice or more of a capacitance of the second switch capacitor.

US Pat. No. 9,077,387

OPERATION MODE SWITCHING MODULE AND ASSOCIATED METHOD

MSTAR SEMICONDUCTOR, INC....

1. An operation mode switching module, for switching a near-field communication (NFC) device between a sleep mode and a communication
mode, the operation mode switching module comprising:
a resonant circuit driver, for driving a resonant circuit to generate an oscillation signal;
a detector, for detecting a level of effect of the environment upon the oscillation signal, comprising:
a signal level detector, for detecting an amplitude of the oscillation signal; and
a state machine, for determining whether to switch the NFC device from the sleep mode to the communication mode according
to the level of effect of the environment upon the oscillation signal, wherein the communication mode comprises a reader/writer
mode and a card-emulation mode

wherein when a difference between the amplitude and an initial amplitude reaches a first threshold, the state machine switches
the NFC device from the sleep mode to the communication mode, when the difference between the amplitude and the initial amplitude
reaches the first threshold but does not reach a second threshold, the state machine switches the NFC device from the sleep
mode to the reader/writer mode, and when the difference between the amplitude and the initial amplitude reaches the second
threshold, the state machine switches the NFC device from the sleep mode to the card-emulation mode.

US Pat. No. 9,420,525

CELL SEARCH METHOD AND DEVICE

MSTAR SEMICONDUCTOR, INC....

1. A cell search method, applied to a wireless communication system to perform cell search synchronization, frame signals
of the wireless communication system comprising a first sub-frame and a second sub-frame, both of the first sub-frame and
the second sub-frame comprising a first regular timeslot and a down pilot timeslot; the cell search method comprising:
determining whether a length of an actual synchronization search window is smaller than a length of a first synchronization
search window, wherein the length of the first synchronization search window is a sum of a length of the first sub-frame and
a length of the first regular timeslot and the down pilot timeslot of the second sub-frame; and

when the length of the actual synchronization search window is smaller than the length of the first synchronization search
window, duplicating a part of data carried in the first regular timeslot and the down pilot timeslot of the second sub-frame
to before the actual synchronization search window, or duplicating a part of data carried in the first regular timeslot and
the down pilot timeslot of the first sub-frame to after the actual synchronization search window, such that a sum of a length
of the duplicated data and the length of the actual synchronization search window is not smaller than the length of the first
synchronization search window.

US Pat. No. 9,391,562

LOCAL OSCILLATION GENERATOR, ASSOCIATED COMMUNICATION SYSTEM AND METHOD FOR LOCAL OSCILLATION GENERATION

MSTAR SEMICONDUCTOR, INC....

16. A communication system, comprising a local oscillation generator for providing a local oscillation signal, the local oscillation
generator comprising:
a multi-phase circuit, for providing a plurality of multi-phase oscillation signals having a same fundamental frequency and
different phases; and

a multiplexer, coupled to the multi-phase circuit, for continuously conducting one of the multi-phase oscillation signals
in a plurality of adjacent time slots, respectively, to form an output oscillation signal,

wherein the local oscillation generator provides the local oscillation signal according to the output oscillation signal,
a synthesized frequency of the output oscillation signal is different from the fundamental frequency, a phase difference exists
between two of the multi-phase oscillation signals conducted by the multiplexer in two adjacent time slots, and a ratio of
the fundamental frequency to the synthesized frequency is equal to a ratio of the phase difference to 360 degrees.

US Pat. No. 9,136,849

INTEGER FREQUENCY DIVIDER AND PROGRAMMABLE FREQUENCY DIVIDER CAPABLE OF ACHIEVING 50% DUTY CYCLE

MStar Semiconductor, Inc....

1. An integer frequency divider, comprising:
a clock input end, configured to provide a clock;
N latches, where N is a positive integer greater than or equal to 2, the latches connected in series according to a connection
order, the latches comprising a first latch and a plurality of candidate latches, each of the latches comprising:

a signal input stage, configured to receive an input signal;
a clock receiving stage, configured to receive an input clock; the clock receiving stage of the latch treating the clock as
the input clock when the latch corresponds to an odd number in the connection order; the clock receiving stage of the latch
treating an inverted clock of the clock as the input clock when the latch corresponds to an even number in the connection
order; and

a signal output stage, configured to output an output signal according to the input signal and the input clock;
a selection circuit, coupled to the signal output stages of each of the candidate latches, configured to select a second latch
from the candidate latches according to a selection signal;

wherein:
the signal input stage of the first latch comprises a positive signal input unit and an inverted signal input unit that respectively
receive the input signal and an inverted signal of the input signal; the signal output stage of the second latch comprises
a positive signal output end and an inverted signal output end that respectively output the output signal and an inverted
signal of the output signal; and

the selection circuit couples the positive signal input unit of the first latch to the inverted signal output end of the second
latch, and couples the inverted signal input unit of the first latch to the positive signal output end of the second latch.

US Pat. No. 9,058,551

RFID TAG AND OPERATING METHOD THEREOF

MStar Semiconductor, Inc....

1. A method for operating a radio frequency identification (RFID) tag, comprising:
receiving a read command;
determining whether a disguise state used to mislead an unauthorized RFID reader is activated based on the read command, and
wherein activation of the disguise state is comprises:

generating, by the RFID tag, a mode parameter, wherein the generating is performed randomly;
selecting a simulation situation from a situation group according to the mode parameter, the situation group comprising a
first situation, a second situation, and a third situation; and

selectively generating a response signal according to the simulation situation, wherein the first situation is that the RFID
tag generates a normal response signal serving as the response signal, and the normal response signal comprises virtual identity
information or virtual content information stored in the RFID tag,

wherein the second situation is that the RFID tag does not generate any response signal, and
wherein the third situation is that the RFID tag generates a collision signal serving as the response signal to simulate a
signal collision.

US Pat. No. 9,552,193

AUTOMATED COMPILER SPECIALIZATION FOR GLOBAL OPTIMIZATION

MStar Semiconductor, Inc....

1. A compiling method for compiling a source code file in a code base, the method comprising:
compiling the source code file in the code base using an optimizing compiler specialized to the code base and accordingly
generating an intermediate representation;

analyzing the intermediate representation to obtain and store characteristics of the code base, wherein the intermediate representation
is not itself further modified;

recompiling the code base with the optimizing compiler using the characteristics of the code base,
obtaining reusable resources from the characteristics of the code base; and
optimizing compiled code using the reusable resources for use in the recompiling step; and
rebuilding the optimized compiler according to (i) the reusable resources for use in the recompiling step, (ii) transformation
specifications, which specify a pattern that matches a common subsequence and a library call that is used to replace the common
subsequence, and (iii) guard code, which is used to skip a given optimization pass.

US Pat. No. 9,237,038

CHANNEL AND NOISE ESTIMATION METHOD AND ASSOCIATED APPARATUS

MSTAR SEMICONDUCTOR, INC....

1. A channel and noise estimation method, applied to a channel and noise estimation apparatus of a wireless communication
system, the channel and noise estimation method comprising:
performing channel estimation on a received signal to obtain a real channel estimation value;
filtering the real channel estimation value to obtain a filtered channel estimation value;
calculating a biased noise power value, a biased signal power value, a biased noise correlation and a biased signal correlation
according to the filtered channel estimation value; and

respectively calculating an unbiased noise power value, an unbiased signal power value, an unbiased noise correlation and
an unbiased signal correlation according to the biased noise power value, the biased signal power value, the biased noise
correlation and the biased signal correlation by using a first inverted matrix;

wherein the step of performing the channel estimation on the received signal to obtain the real channel estimation value comprises:
performing the channel estimation on at least one signal received by a first reception antenna and a second reception antenna,
respectively, to obtain corresponding real channel estimation values HLS1 and HLS2, where HLS1 represents the real channel estimation value corresponding to the first reception antenna, and HLS2 represents the real channel estimation value corresponding to the second reception antenna;

wherein the step of filtering the real channel estimation value to obtain the filtered channel estimation value comprises:
filtering the real channel estimation values HLS1 and HLS2 by utilizing a first filter and a second filter, respectively, to obtain corresponding filtered channel estimation values
Yw1(k), Yw2(k), Yu1(k) and Yu2(k), where Yw1(k) represents the filtered channel estimation value obtained from filtering HLS1 by the first filter, Yw2(k) represents the filtered channel estimation value obtained from filtering HLS2 by the first filter, Yu1(k) represents the filtered channel estimation value obtained from filtering HLS1 by the second filter, and Yu2(k) represents the filtered channel estimation value obtained from filtering HLS2 by the second filter;

wherein values of HLS1 and HLS2 are:

HLS1=Hideal1+v1  (1)

HLS2=Hideal2+v2  (2)

where Hideal1 represents an ideal channel estimation value of the first reception antenna, v1 represents a noise value of the first reception antenna, Hideal2 represents an ideal channel estimation value of the second reception antenna, and v2 represents a noise value of the second reception antenna; and

values of Yw1(k), Yw2(k), Yu1(k) and Yu2(k) are calculated through following equations:

Yw1(k)=wHLS1  (3)

Yw2(k)=wHLS2  (4)

Yu1(k)=uHLS1  (5)

Yu2(k)=uHLS2  (6)

where w represents a coefficient row vector of the first filter, k represents a kth subcarrier on a frequency domain, and u represents a coefficient row vector of the second filter; and

wherein the step of calculating the biased noise power value, the biased signal power value, the biased noise correlation
and the biased signal correlation according to the filtered channel estimation value comprises:

calculating biased noise power values Sw1 and Sw2, biased signal power values Su1 and Su2, a biased noise correlation Pw12 between Yw1(k) and Yw2(k), and a biased signal correlation Pu12 between Yu1(k) and Yu2(k) corresponding to the first reception antenna and the second reception antenna according to Yw1(k), Yw2(k), Yu1(k) and Yu1(k), respectively; and

values of Sw1, Sw2, Su1, Su2, Pw12 and Pu12 are calculated through following equations:

Sw1=Ek(Yw1(k)·Yw1(k)*)  (7)

Sw2=Ek(Yw2(k)·Yw2(k)*)  (8)

Su1=Ek(Yu1(k)·Yu1(k)*)  (9)

Su2=Ek(Yu2(k)·Yu2(k)*)  (10)

Pw12=Ek(Yw1(k)·Yw2(k)*)  (11)

Pu12=Ek(Yu1(k)·Yu2(k)*)  (12)

where Sw1 represents the biased noise power value corresponding to the first reception antenna, Sw2 represents the biased noise power value corresponding to the second reception antenna, Su1 represents the biased signal power value corresponding to the first reception antenna, Su2 represents the biased signal power value corresponding to the second reception antenna, Pw12 represents the biased noise correlation between Yw1(k) and Yw2(k), Pu12 represents the biased signal correlation between Yu1(k) and Yu2(k), Ek(?) represents a frequency-domain average, and (?)* represents a conjugation; and

wherein after the step of calculating the unbiased noise power value, the unbiased signal power value, the unbiased noise
correlation and the unbiased signal correlation according to the biased noise power value, the biased signal power value,
the biased noise correlation and the biased signal correlation, the method further comprising:

frequency-domain smoothing the unbiased noise power value, the unbiased signal power value, the unbiased noise correlation
and the unbiased signal correlation;

time-domain filtering the frequency-domain smoothed unbiased noise power value, unbiased signal power value, unbiased noise
correlation and unbiased signal correlation; and

demodulating the filtered unbiased noise power value, unbiased signal power value, unbiased noise correlation and unbiased
signal correlation to restore an original transmission signal.

US Pat. No. 9,077,568

RECEIVING APPARATUS AND METHOD FOR ACCELERATING EQUALIZATION CONVERGENCE

MSTAR SEMICONDUCTOR, INC....

1. A receiving apparatus, applied to a receiving end of a communication device comprising an equalizer, the receiving apparatus
comprising:
a filter, configured to filter a received signal to reduce a multipath effect of the received signal and to output a filtered
signal, wherein the filter is for enlarging an energy difference between a first-path signal and a second-path signal in the
received signal; and

a channel estimator, configured to perform channel estimation on the received signal to generate an estimation result, which
is for determining which of the received signal and the filtered signal is to be selected and sent to the equalizer.

US Pat. No. 9,654,307

COMMUNICATION APPARATUS

MStar Semiconductor, Inc....

1. A communication apparatus, correcting a situation of an spectrum inverted signal that the communication apparatus receives,
comprising:
a channel estimation module, determining a channel estimation parameter, receiving at least one frame signal to generate a
convolution restored frame signal corresponding to the frame signal, wherein the channel estimation parameter, the frame signal
and the convolution restored frame signal are time-domain signals; and

an equalization module, coupled to the channel estimation module, comprising:
a first computation circuit, receiving the channel estimation parameter and the convolution restored frame signal to generate
a transformed channel estimation parameter and a transformed convolution restored frame signal, wherein the transformed channel
estimation parameter and the transformed convolution restored frame signal are frequency-domain signals; and

a second computation circuit, coupled to the first computation circuit, receiving the transformed channel estimation parameter
and the transformed convolution restored frame signal to generate an original frame signal corresponding to the frame signal,
wherein the original frame signal is a time-domain signal;

wherein, the first computation circuit further feeds back a transient original frame signal to the channel estimation module
to update the channel estimation parameter, and the transient original frame signal is a time-domain signal.

US Pat. No. 9,386,254

BROADCAST METHOD AND BROADCAST APPARATUS

MStar Semiconductor, Inc....

1. A broadcast method, for a broadcast apparatus signally connected to an input apparatus, the input apparatus generating
a plurality of corresponding control signals according to a plurality of operations; the broadcast method comprising:
receiving one of the control signals;
determining verification information and a set of broadcast parameters when the one of the control signals matches a tag;
and

broadcasting according to the set of broadcast parameters;
wherein, the step of determining verification information and a set of broadcast parameters when the one of the control signals
matches a tag comprises:

retrieving the broadcast parameter from a parameter database according to the tag and the verification information;
wherein, the parameter database stores a plurality of relationships, each of the relationships corresponds to a tag, a verification
information, and a set of broadcast parameters;

wherein, when the tag is a function instruction, the set of broadcast parameters are settings of a broadcast state; and when
the tag is an adjustment instruction, the set of broadcast parameters are adjustment amounts of settings of a broadcast state.

US Pat. No. 9,369,400

WIRELESS RECEIVING SYSTEM AND SIGNAL PROCESSING METHOD THEREOF

MSTAR SEMICONDUCTOR, INC....

1. A wireless receiving system, comprising:
a decoding module, configured to receive and decode a packet to generate a decoding result;
an estimating module, configured to retrieve packet length information from the decoding result, and to estimate an estimated
transmission end time of the packet according to the packet length information; and

a searching module, configured to determine a search start time according to the estimated transmission end time, and to start
packet searching at the search start time;

wherein, the estimating module retrieves the packet length information from a part of the decoding result, and estimates the
estimated transmission end time of the packet before the packet is completely decoded.

US Pat. No. 9,363,779

REDUCING INTERFERENCE IN WIRELESS TIME DIVISION DUPLEX SYSTEMS BY MONITORING AND LIMITING TIMING ADVANCE

MStar Semiconductor, Inc....

1. A method for reducing interference in a wireless network, comprising:
at a user equipment device in a first wireless coverage area of the wireless network using a time division duplex transmission
scheme, limiting a timing advance value for uplink transmissions to a maximum value that is less than a guard period for the
first wireless coverage area based on potential interference caused by uplink transmissions made by the user equipment device
in the first wireless coverage area or at least one other user equipment device in the first wireless coverage area to downlink
transmissions intended for at least one user equipment device in a second wireless coverage area of the wireless network,

wherein the wireless network communicates via a time division long term evolution (LTE) communication scheme and the maximum
timing advance value is limited according to at least one of a cell radius of the first wireless coverage area and a cell
radius of the second wireless coverage area,

employing a current timing advance value which is less than or equal to the maximum value to transmit data, via LTE, from
the user equipment device to a base station of the first wireless coverage area; and

sending a message to a base station from the user equipment device in the first wireless coverage area comprising information
configured to indicate the current timing advance value employed at the user equipment device, the message being configured
to allow the base station to take an appropriate action to prevent the user equipment device in the first wireless coverage
area from causing interference.

US Pat. No. 9,237,334

METHOD AND DEVICE FOR CONTROLLING SUBTITLE APPLIED TO DISPLAY APPARATUS

MSTAR SEMICONDUCTOR, INC....

1. A subtitle control method, applicable to a display apparatus, for dynamically adjusting a subtitle of an original image,
the original image comprising a right-eye frame and a left-eye frame, the right-eye frame comprising right-eye subtitle information,
the left-eye frame comprising left-eye subtitle information, the method comprising:
selecting an adjusted subtitle display mode;
determining a shift distance of the right-eye subtitle information and the left-eye subtitle information;
selectively adjusting the shift distance according to the adjusted subtitle display mode and a selected 3D depth, such that
an adjusted subtitle presented by the right-eye frame and the left-eye frame shows an adjusted subtitle 3D depth; and

determining an original subtitle display mode, comprising:
comparing the shift distance of the right-eye subtitle information and the left-eye subtitle information;
determining the original subtitle display mode as a static display mode when the shift distance is substantially stable; and
determining the original subtitle display mode as a dynamic 3D display mode when the shift distance changes with time;
wherein, the adjusted subtitle display mode comprises a static display mode and a dynamic 3D display mode, and when the adjusted
subtitle display mode is different from the original subtitle display mode, the selected 3D depth is generated according to
the adjusted subtitle display mode to accordingly adjust the shift distance.

US Pat. No. 9,176,857

METHOD AND APPARATUS FOR MANAGING VIDEO MEMORY IN EMBEDDED DEVICE

MStar Semiconductor, Inc....

1. A method for managing an image memory in an embedded device, comprising:
obtaining a node from a linked list of the image memory;
judging whether valid data is present in a memory block corresponding to the node in the image memory;
judging whether valid data is present in a memory block corresponding to a previous node in the image memory when no valid
data is present in the memory block corresponding to the node;

judging whether the valid data is movable when valid data is present in the memory block corresponding to the previous node;
when the valid data stored in the memory block corresponding to the previous node is movable, exchanging memory block information
in the node with memory block information in the previous node, and moving the valid data stored in the memory block corresponding
to the previous node to the memory block corresponding to the node,

after the step of judging whether valid data is present in the memory block corresponding to the node, the method further
comprising, when valid data is present in the memory block corresponding to the node, obtaining a previous node of the node
and performing the step of judging whether valid data is present in the memory block corresponding to the previous node until
a first node in the linked list of the image memory is obtained; and

after the step of judging whether the valid data stored in the memory block corresponding to the previous node is movable,
the method further comprising, when it is judged the valid data stored in the memory block corresponding to the previous node
is immovable, obtaining a previous node of the previous node and performing the step of judging whether valid data is present
in the memo T block corresponding to the obtained node until the first node in the linked list of the image memory is obtained,

wherein the step of judging whether the valid data stored in the memory block corresponding to the previous node is movable
comprises judging whether the memory block corresponding to the previous node is a layer surface; wherein when the memory
block corresponding to the previous node is the layer surface, the valid data stored in the memory block corresponding to
the previous node is immovable; and

when the memory block corresponding to the previous node is not the layer surface, judging whether the memory block corresponding
to the previous node is locked; wherein, when the memory block corresponding to the previous node is locked, the valid data
stored in the memory block corresponding to the previous node is immovable.

US Pat. No. 9,177,380

3D VIDEO CAMERA USING PLURAL LENSES AND SENSORS HAVING DIFFERENT RESOLUTIONS AND/OR QUALITIES

MStar Semiconductor, Inc....

1. A three-dimensional (3D) video camera, comprising:
a first camera lens configured to provide a first sensing signal by a first sensing element;
a second camera lens configured to provide a second sensing signal by a second sensing element, wherein the first camera lens
and the second camera lens have different resolutions; and

an image processing unit configured to receive the first sensing signal and the second sensing signal to generate a first
eye image and a first comparison image, and to generate 3D depth information according to the first eye image and the first
comparison image,

wherein the image processing unit is configured to process the first comparison image with reference to the first eye image
to obtain a second comparison image, and generate the 3D depth information by comparing the first eye image and the second
comparison image to calculate horizontal distances between same objects in the first eye image and the second comparison image
resulting from visual differences between the same objects in the first eye image and the second comparison image, wherein
the calculated horizontal distances represent the 3D depth information;

wherein the first comparison image is processed with scaling or decolorizing before the horizontal distances representative
of 3D depth information are calculated according to the first eye image and the first comparison image; and

wherein the image processing unit comprises:
a first image processing circuit configured to receive the first sensing signal to generate the first eye image;
a second image processing circuit configured to receive the second sensing signal to generate the first comparison image;
a pre-processing circuit configured to receive the first eye image and the first comparison image to generate the second comparison
image; and

a 3D depth generator configured to receive and compare the second comparison image and the first eye image to generate a block
base 3D depth as the 3D depth information by dividing the second comparison image and the first eye image into a plurality
of blocks, with each of the blocks of the first eye image respectively corresponding to one of the blocks of the second comparison
image, and vice versa, and comparing the corresponding blocks in the first-eye image and the second comparison image based
on a distance calculation to respectively provide the block base 3D depth as the 3D depth information; and

a 3D video camera further comprises a 3D depth interpolation unit configured to receive the block base 3D depth and perform
an interpolation to obtain a sub-block base 3D depth as the 3D depth information.

US Pat. No. 9,088,320

TRANSMITTER WITH PRE-DISTORTION MODULE, A METHOD THEREOF

MSTAR SEMICONDUCTOR, INC....

1. A transmitter comprising:
a pre-distortion module configured to (i) receive a first digital value, and generate a first pre-distorted digital value
based on the first digital value and a corresponding distortion angle, the first digital value being a first combination of
an in-phase component and a quadrature component of a signal for transmission, and (ii) receive a second digital value, and
generate a second pre-distorted digital value based on the second digital value and the corresponding distortion angle, the
second digital value being a second combination of the in-phase component and the quadrature component of the signal for transmission;
and

a phase controller, coupled to the pre-distortion module and an amplifier, configured to (a) control the amplifier to drive
a current according to the first pre-distorted digital value and phase information in relation to the first digital value,
during a first phase range of a carrier signal determined at least partially based on the corresponding distortion angle,
and (b) control the amplifier to drive the current according to the second pre-distorted digital value and phase information
in relation to the second digital value, during a second phase range of the carrier signal determined at least partially based
on the corresponding distortion angle.

US Pat. No. 9,058,044

REFERENCE VOLTAGE GENERATION CIRCUIT

MSTAR SEMICONDUCTOR, INC....

1. A reference voltage generation circuit, comprising:
an auto-activation unit;
an operational amplifier unit; and
a tail current resistor;
wherein, an input end of the operational amplifier unit is grounded via the tail current resistor, and the auto-activation
unit is coupled to the operational amplifier unit so that the reference voltage generation circuit operates at an operating
point.

US Pat. No. 9,054,932

WIRELESS RECEPTION SYSTEM AND METHOD FOR ESTIMATING CHANNEL EFFECT THEREOF

MSTAR SEMICONDUCTOR, INC....

1. A wireless reception system, comprising: a reception module for receiving a reference signal and at least one input signal
transmitted via a multipath environment, wherein the reference signal is associated with a known signal unaffected by the
multipath environment; a preliminary estimation module for generating a plurality of candidate channel effects according to
the at least one input signal; an equalization module for performing an equalization process on the reference signal according
to each of the candidate channel effects to generate a plurality of equalization results; and a selection module for selecting
an optimal equalization result most similar to the known signal from the equalization results, and to select the candidate
channel effect corresponding to the optimal equalization result to represent the multipath environment, wherein the reference
signal is a transmission parameter signaling (TPS) having undergone differential binary phase shift keying (DBPSK), and the
selection module selects the equalization result having a smallest imaginary part from the equalization results as the optimal
equalization result most similar to the known signal.

US Pat. No. 9,444,665

SIGNAL PROCESSING SYSTEM AND SIGNAL PROCESSING METHOD COOPERATING WITH VARIABLE GAIN AMPLIFIER

MSTAR SEMICONDUCTOR, INC....

1. A signal processing system, comprising:
a variable gain amplifier, configured to apply a variable gain to an analog input signal to generate an amplified analog signal;
an analog-to-digital converter (ADC), configured to convert the amplified analog signal to an amplified digital signal;
a gain compensation circuit, configured to apply a compensation gain to the amplified digital signal to generate a compensated
signal, wherein the compensated signal has an instantaneous change lower than a predetermined threshold, and the gain compensation
circuit further comprises a conversion circuit, configured to receive an initial difference, in a unit of decibels, between
a first gain value and a second gain value, and to accordingly generate a converted difference in a unit of linear multiples
for the gain compensation module to determine the compensation gain; and

a signal processing circuit, configured to perform a signal processing procedure on the compensated signal.

US Pat. No. 9,378,800

MEMORY CONTROLLER AND ASSOCIATED SIGNAL GENERATING METHOD

MSTAR SEMICONDUCTOR, INC....

1. A signal generating method of a memory controller, for controlling a first memory module, comprising:
generating a first clock signal, a bank control signal and a first-part address signal that have a signal period of a unit
time;

generating a command signal having a signal period of the unit time, wherein the command signal comprises a plurality of command
groups each having a first command, a second command, a third command and a fourth command that are consecutive; and

generating a second-part address signal having a signal period twice of the unit time;
wherein, a first signal edge of the first clock signal occurs during latching intervals of the command signal, the bank control
signal and the first-part address signal; a second signal edge of the first clock signal occurs during latching intervals
of the command signal, the bank control signal, the first-part address signal and the second-part address signal; a third
signal edge of the first clock signal occurs during latching intervals of the command signal, the bank control signal and
the first-part address signal; and a fourth signal edge of the first clock signal occurs during the latching intervals of
the command signal, the bank control signal, the first-part address signal and the second-part address signal.

US Pat. No. 9,356,766

ENABLING HALF DUPLEX FREQUENCY DIVISION DUPLEX (HD-FDD) OPERATION OF USER EQUIPMENTS IN FULL DUPLEX FREQUENCY DIVISION DUPLEX (FD-FDD) NETWORK

MSTAR SEMICONDUCTOR, INC....

1. A method in a wireless communication network comprising a first base station and a user device, the method comprising:
signaling using a message by said first base station to said user device for indicating support of half duplex frequency division
duplex (HD-FDD) operation; and

configuring said first base station to support concurrently said HD-FDD operation and a second duplex operation comprising
a full duplex frequency division duplex (FD-FDD) operation or a time division duplex (TDD) operation;

wherein the message is carried by a predefined portion of an orthogonal variable spreading factor (OVSF) tree, and said signaling
using said message further comprises sending said message from said first base station to said user device by a second base
station with a base station group comprising said first base station;

wherein when said user device receiving said message is a HD-FDD device, said user device does not discard said first base
station during a search phase; and

wherein said base station group is characterized by a common frequency layer, a common size, a common area and a common network.

US Pat. No. 9,232,170

TELEVISION SIGNAL RECEIVING DEVICE AND METHOD FOR DETERMINING WHETHER CHANNEL INCLUDES TELEVISION PROGRAM SIGNAL

MSTAR SEMICONDUCTOR, INC....

1. A television signal receiving device, for determining whether a target channel includes a television program signal, comprising
a tuner to receive a radio-frequency (RF) signal, select the target channel from a plurality of channels included in the RF
signal, and down-convert the target channel, the television signal receiving device comprising:
an analog-to-digital converter (ADC), configured to convert an analog signal carried in the down-converted target channel
to a digital signal;

an operation circuit, configured to perform an operation on the digital signal to obtain a correlation comparing result; and
a control circuit, configured to determine whether the target channel includes the television program signal according to
the correlation comparing result.

US Pat. No. 10,075,285

LOOP BANDWIDTH ADJUSTING METHOD FOR PHASE LOCKED-LOOP UNIT AND ASSOCIATED LOOP BANDWIDTH ADJUSTING UNIT AND PHASE RECOVERY MODULE

MSTAR SEMICONDUCTOR, INC....

1. A loop bandwidth adjusting method, for a phase-locked loop (PLL) unit of a phase recovery module in a wireless communication system, comprising:adjusting an operating bandwidth of the PLL unit to a first bandwidth;
measuring a plurality of first phase errors between a compensated input signal and a reference clock signal, and obtaining a first statistical value of the plurality of first phase errors, wherein the compensated input signal is generated according to an input signal and a phase compensating signal generated by the PLL unit;
adjusting the operating bandwidth of the PLL unit to a second bandwidth;
measuring a plurality of second phase errors between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the plurality of second phase errors; and
adjusting the operating bandwidth according to the first statistical value and the second statistical value;
wherein, the first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.

US Pat. No. 9,509,419

COMMUNICATION CIRCUIT AND ASSOCIATED CALIBRATION METHOD

MStar Semiconductor, Inc....

1. A communication circuit, comprising:
a receiver path, comprising:
an input port; and
a reception mixer, coupled to the input port, configured to mix a signal of the input port with a reception oscillation frequency;
and

a signal source circuit; and
an auxiliary mixer, coupled between the input port and the signal source circuit, operable in an auxiliary mode;
wherein, when the auxiliary mixer operates in the auxiliary mode, the signal source circuit provides an auxiliary signal,
and the auxiliary mixer mixes the auxiliary signal with the reception oscillation frequency and sends a mixed result to the
input port,

wherein the auxiliary mixer is further operable in a reception mode; when the auxiliary mixer operates in the reception mode,
the auxiliary mixer is configured to co-operate with a frequency translating filter backend circuit to filter the signal of
the input port,

the communication circuit further comprising:
a switch circuit, coupled between the frequency translating filter backend circuit, the signal source circuit and the auxiliary
mixer;

wherein, when the auxiliary mixer operates in the auxiliary mode, the switch circuit conducts the signal source circuit to
the auxiliary mixer; when the auxiliary mixer operates in the reception mode, the switch circuit conducts the frequency translating
filter backend circuit to the auxiliary mixer.

US Pat. No. 9,448,967

STREAM DATA PROCESSOR

MStar Semiconductor, Inc....

1. A stream data processor, comprising:
one or more stream input interfaces;
one or more stream output interfaces;
one or more memories;
one or more stream processing units that implement data processing operations, each stream processing unit comprising a plurality
of processing elements that implement processing operations and each processing element comprising one or more read-blocks
and one or more write-blocks; and

one stream control unit that provides configuration data to the stream processing units to perform sequencing of the data
processing operations,

wherein the stream control unit provides a separate configuration, a separate synchronous enable and a common trigger to each
read-block and write-block, and

wherein the stream control unit provides a new configuration to each read-block and write-block once each of the one or more
read-blocks and one or more write-blocks has asserted a respective done flag indicating that a configured operation has completed.

US Pat. No. 9,350,403

RECEIVER IN PHYSICAL LAYER OF MOBILE INDUSTRY PROCESSOR INTERFACE (MIPI-PHY)

MStar Semiconductor, Inc....

1. A receiver, for receiving a pair of differential signals provided by a transmitter, comprising:
a control module, configured to generate an enable signal and provide a bias voltage when a predetermined change occurs in
the differential signals, the control circuit comprising a low-speed data receiving circuit that generates the enable signal;

a high-speed data receiving circuit, triggered by the enable signal to generate an output signal according to the differential
signals and the bias voltage; and

a masking circuit, triggered by the enable signal to start masking the output signal;
wherein, when the control module provides the bias voltage, the output signal is in a first state wherein one of the pair
of differential signals is maintained high by the bias voltage and the other one of the pair of differential signals is low;
upon detecting that the output signal enters a second state from the first state, wherein the other of the pair of differential
signals is high, caused by the transmitter, the control module stops providing the bias voltage and generates a disable signal
to the masking circuit to prompt the masking circuit to stop masking the output signal,

wherein the first state and the second state are in accordance with the Mobile Industry Processor Interface (MIPI).

US Pat. No. 9,215,605

METHOD FOR ESTIMATING FREQUENCY DIFFERENCE

MSTAR SEMICONDUCTOR, INC....

1. A method for estimating a frequency difference between a transmission terminal and a reception terminal according to a
reception signal, comprising:
in a first period, receiving and storing a first part of the reception signal;
in a second period, frequency shifting the first part of the reception signal according to an L number of sweep frequencies
to obtain a plurality of first part frequency-shifted signals corresponding to the L number of sweep frequencies, where L
is a positive integer;

performing a correlation calculation on the first part frequency-shifted signals to obtain a plurality of first part correlation
results;

in the second period, receiving and storing a second part of the reception signal;
in a third period, frequency shifting the second part of the reception signal according to the L number of sweep frequencies
to obtain a plurality of second part frequency-shifted signals corresponding to the L number of sweep frequencies;

performing the correlation calculation on the second part frequency-shifted signals to obtain a plurality of second part correlation
results; and

estimating the frequency difference according to the first part correlation results and the second part correlation results;
wherein said frequency difference is estimated according to a partial accumulation result;
wherein in the third period, the step of frequency shifting the second part of the reception signal according to the L number
of sweep frequencies to obtain the second part frequency-shifted signals corresponding to the L number of sweep frequencies
comprises:

sampling the second part of the reception signal to obtain a K number of sets of sampled data, where K is a positive integer;
and

frequency shifting the K number of sets of sampled data according to the L number of sweep frequencies to obtain the second
part frequency-shifted signals, respectively; and

wherein the step of estimating the frequency difference according to the first part correlation results and the second part
correlation results comprises:

for the L number of sweep frequencies, obtaining an L number of accumulation results corresponding to the sweep frequencies
by accumulating the first part correlation results and the second part correlation results;

obtaining a maximum accumulation result by comparing the accumulation results;
obtaining an accumulation result average according to the accumulation results; and
obtaining the frequency difference according to the maximum accumulation result and the accumulation result average.

US Pat. No. 9,201,550

MUTUAL CAPACITIVE TOUCH PANEL AND TOUCH CONTROL SYSTEM

MStar Semiconductor, Inc....

1. A single-layer mutual capacitive touch panel, operable under control of a controller, comprising:
a first driving electrode;
a second driving electrode;
N number of first receiving electrodes, surrounding the first driving electrode, each side of the first driving electrode
corresponding to one of the first receiving electrodes;

M number of second receiving electrodes, surrounding the second driving electrode, each side of the second driving electrode
corresponding to one of the second receiving electrodes;

a driving channel, through which the controller simultaneously sends a driving signal to the first driving electrode and the
second driving electrode; and

(N+M) number of receiving channels, respectively corresponding to one of the N number of first receiving electrodes and the
M number of second receiving electrodes;

wherein, the N number of first receiving electrodes and the M number of second receiving electrodes respectively correspond
to different receiving channels, the controller receives (N+M) number of sensing results via the (N+M) number of receiving
channels when sending the driving signal, and N and M are positive integers;

a third driving electrode, wherein the controller drives the first driving electrode and the third driving electrode in a
time-division manner; and

P number of third receiving electrodes, corresponding to the third driving electrode;
wherein, P is a positive integer, and one of the P number of third receiving electrodes and one of the N number of first receiving
electrodes connect to a same receiving channel,

wherein planar profiles of the first driving electrode, the second driving electrode, the third driving electrode, the N number
of first receiving electrodes, the M number of second receiving electrodes and the P number of third receiving electrodes
are rhombuses, and

wherein N, M and P are equal to 4, the first driving electrode, the third driving electrode and the second driving electrode
are adjacently arranged in a row by vertices thereof, the four first receiving electrodes encompass four edges of the first
driving electrodes, the four second receiving electrodes encompass four edges of the second driving electrode, and the four
third receiving electrodes encompass four edges of the third driving electrode; two of the four first receiving electrodes
act as two of the four third receiving electrodes, and two of the four second receiving electrodes act as the remaining two
of the four third receiving electrodes.

US Pat. No. 9,484,923

SIGNAL TRANSMISSION CIRCUIT SUITABLE FOR DDR

MStar Semiconductor, Inc....

1. A signal transmission circuit suitable for DDR, adapted to drive a connecting pad, said signal transmission circuit comprising:
a level shifting circuit, comprising:
an up level shifter;
a down level shifter; and
wherein, the up level shift and the down level shifter are disposed between a DDR operating voltage and a ground voltage,
receive an input signal, and correspondingly output a first shift signal and a second shift signal, respectively; the input
signal comprises a first operating voltage and a second operating voltage, the first operating voltage is equal to the ground
voltage, and the second operating voltage is smaller than the DDR operating voltage;

a buffer circuit, comprising:
an up buffer unit, disposed between the DDR operating voltage and a first reference voltage, coupled to an output of the up
level shifter to receive the first shift signal and to output a first logic signal according to the first shift signal; and

a down buffer unit, disposed between the ground voltage and a second reference voltage, coupled to an output of the down level
shifter to receive the second shift signal and to output a second logic signal according to the second shift signal;

an output circuit, comprising:
a pull-up circuit, coupled between the DDR operating voltage and the connecting pad, further coupled to the up buffer unit
to selectively output the DDR operating voltage to the connecting pad according to the first logic signal; and

a pull-down circuit, coupled between the ground voltage and the connecting pad, further coupled to the down buffer unit to
selectively output the ground voltage to the connecting pad according to the second logic signal;

wherein, the up level shifter and the down level shifter adopt input and output (IO) devices to respectively output the first
shift signal and the second shift signal; the up buffer unit, the down buffer unit, the pull-up circuit and the pull-down
circuit adopt core devices; the second reference voltage is equal to the second operating voltage, and the first reference
voltage is a difference between the DDR operating voltage and the second reference voltage,

wherein the up level shifter comprises:
a 1st inverter;

a 2nd inverter;

a 3rd inverter;

a 4th inverter; and

a 5th inverter;

wherein, the 1st to 5th inverters are disposed between the first operating voltage and the second operating voltage of the input signal, the 1st inverter has its input end coupled to the input signal, the 1st, 2nd and 3rd inverters are connected in series to output an inverted signal of the input signal, the 4th inverter has its input end coupled to an output end of the 2nd inverter to cause the 1st, 2nd, 4th and 5th inverters to be connected in series to output a non-inverted signal of the input signal;

an 11th switch element, comprising a control end, a first path end and a second path end, the 11th switch element having its control end coupled to an output end of the 3rd inverter to receive the inverted signal of the input signal, and its first path end coupled to the ground voltage;

a 12th switch element, comprising a control end, a first path end and a second path end, the 12th switch element having its control end coupled to an output end of the 5th inverter to receive the non-inverted signal of the input signal, and its first path end coupled to the ground voltage;

a 13th switch element, comprising a control end, a first path end and a second path end, the 13th switch element having its control end coupled the control end of the 12th switch element and the output end of the 5th inverter to receive the non-inverted signal of the input signal, and its first path end coupled to the second path end of
the 12th switch element;

a 14th switch element, comprising a control end, a first path end and a second path end, the 14th switch element having its control end coupled to the second reference voltage, its first path end coupled to a connecting
node between the second path end of the 12th switch element and the first path end of the 13th switch element, and its second path end coupled to the second path end of the 13th switch element;

a 15th switch element, comprising a control end, a first path end and a second path end, the 15th switch element having its first path end coupled to the DDR operating voltage, its second path end and control end coupled
together and further coupled to the second path end of the 11th switch element, wherein a connecting node between the second path end of the 15th switch element and the second path end of the 11th switch element is defined as a first node;

a 16th switch element, comprising a control end, a first path end and a second path end, the 16th switch element having its control end coupled to the first node, its first path end coupled to the DDR operating voltage;

a 17th switch element, comprising a control end, a first path end and a second path end, the 17th switch element having its control end coupled to the first node, and its path end coupled to the second path end of the 16th switch element;

an 18th switch element, comprising a control end, a first path end and a second path end, the 18th switch element having its control end coupled to the first reference voltage, its first path end coupled to a connecting node
between the first path end of the 17th switch element and the second path end of the 16th switch element, its second path end coupled to the second path end of the 17th switch element and further coupled to the second path end of the 13th switch element and the second path end of the 14th switch element, wherein a connecting node between the second path end of the 18th switch element, the second path end of the 17th switch element, the second path end of the 13th switch element and the second path end of the 14th switch element is defined as a second node;

a 19th switch element, comprising a control end, a first path end and a second path end, the 19th switch element having its control end coupled to the second node, and its first path end coupled to the DDR operating voltage;
and

a 20th switch element, comprising a control end, a first path end and a second path end, the 20th switch element having its control end coupled to the second node, its first path end coupled to the first reference voltage,
and its second path end coupled to the second path end of the 19th switch element, wherein a connecting node between the second path end of the 20th switch element and the second path end of the 19th switch element serves as the output end of the up level shifter to output the first shift signal;

wherein, the 11th, 12th, 13th, 14th and 20th switch elements are second-type switch elements, the 15th, 16th, 17th, 18th and 19th switch elements are first-type switch elements, and a type of the first-type switch elements is opposite a type of the second-type
switch elements.

US Pat. No. 9,473,868

MICROPHONE ADJUSTMENT BASED ON DISTANCE BETWEEN USER AND MICROPHONE

MStar Semiconductor, Inc....

1. A sound collecting system, comprising:
a plurality of microphones, configured to receive sounds;
a distance estimation module, configured to estimate a user distance between a user and the plurality of microphones; and
an adjustment module, configured to adjust a position of at least one of the plurality of microphones according to the user
distance,

wherein the position of the at least one of the plurality of microphones is associated with a distance between the plurality
of microphones, the adjustment module determines a target distance according to the user distance and compares whether the
distance satisfies the target distance, and the adjustment module adjusts the position of the at least one microphone of the
plurality of microphones when the distance does not satisfy the target distance so that the distance satisfies the target
distance.

US Pat. No. 9,450,583

INPUT/OUTPUT CIRCUIT WITH HIGH VOLTAGE TOLERANCE AND ASSOCIATED APPARATUS

MSTAR SEMICONDUCTOR, INC....

1. An input/output (IO) circuit with an internal operating voltage for interfacing with an external circuit providing an external
signal at an external operating voltage, comprising:
a voltage generator, generating a bias voltage higher than said internal operating voltage and less than or equal to a sum
of a maximum tolerable voltage and a pre-determined cross voltage; and

a switch circuit, with said pre-determined cross voltage, for conditioning said external signal to an internal signal at a
clamping voltage based on said bias voltage, comprising:

a first end, for receiving said external signal at said external operating voltage;
a second end, coupled to the voltage generator for receiving said bias voltage; and
a third end, coupled to an internal circuit with said maximum tolerable voltage, and to provide said internal signal at said
clamping voltage to said internal circuit;

wherein said clamping voltage is larger than said internal operating voltage and less than or equal to said maximum tolerable
voltage, and said internal circuit is on a same chip as the IO circuit.

US Pat. No. 9,197,168

AMPLITUDE MODULATION TO PHASE MODULATION (AMPM) DISTORTION COMPENSATION

MStar Semiconductor, Inc....

1. An apparatus to generate amplitude modulation to phase modulation (AMPM) predistortion data that compensates for phase
distortion in a power amplifier of a communication device, the apparatus comprising:
a test signal generator to generate a baseband test signal that is upconverted and provided to the power amplifier;
a reference oscillator to generate a reference oscillator signal;
a coupler to obtain the amplified test signal from the power amplifier;
a combiner coupled to the reference oscillator and the coupler to combine, by wave superposition, the amplified test signal
and the reference oscillator signal into a resultant signal that is an outcome of interference between the amplified test
signal with the reference oscillator signal;

a measurement circuit to generate a measurement signal that characterizes the resultant signal; and
a processor coupled to the measurement circuit and configured to:
determine a predistortion phase shift that when applied to the test signal maximizes the interference between the amplified
test signal and the reference oscillator signal as indicated to by the measurement signal; and to

generate the AMPM predistortion data that corresponds with the predistortion phase shift.

US Pat. No. 9,083,996

REMOTE MONITORING METHOD FOR SMART TV, AND SMART TV SYSTEM

MSTAR SEMICONDUCTOR, INC....

1. A remote monitoring method for a smart TV, wherein the smart TV is connected to a plurality of external devices, comprising:
retrieving real-time status information of the smart TV and an external device, wherein the external device is connected to
the smart TV at a particular connection level, wherein the real-time status information is recorded in advance to facilitate
quick retrieval;

transmitting the real-time status information to the remote device by the smart TV in response to detection request information
transmitted from the remote device, such that the remote device monitors a real-time status of the smart TV and the external
device;

receiving a control command transmitted from the remote device; and
performing an operation control according to the control command;
wherein the detection request information comprises a hop count corresponding to the particular connection level of the external
device to facilitate the retrieval of the real-time status information of the external device; and

wherein the hop count is decreased by one when the detection request information is received by the smart TV or one of plurality
of external devices, and the detection request information is further forwarded to an adjacent external device when a remaining
hop count is non-zero.

US Pat. No. 9,060,340

RE-CONFIGURABLE COMMUNICATION DEVICE AND MANAGING METHOD THEREOF

MSTAR SEMICONDUCTOR, INC....

1. A communication device, comprising:
a physical information recognizing module for recognizing a set of physical information relative to at least one communication
network, comprising:

an RF unit for receiving RF signals from the at least one communication network; and
a converting unit, coupled to the RF unit, for converting the RF signals into digital baseband signals;
an MAC information recognizing module for recognizing a set of MAC information relative to the at least one communication
network, comprising:

a protocol detector for detecting, based on the digital baseband signals, a multiple access protocol associated with the RF
signals;

a resource detector for detecting a radio resource allocation of the at least one communication network based on the digital
baseband signals;

a pattern detector for detecting an automatic repeat request (ARQ) pattern and/or a traffic pattern of the digital baseband
signals; and

a routing/mobility detector for deriving a routing/mobility characteristic associated with the at least one communication
network from the digital baseband signals;

a coordinating module, coupled to the physical information recognizing module and the MAC information recognizing module,
for generating a set of control signals selectively based on the set of physical information and the set of MAC information;
and

a re-configurable transmitting/receiving module, coupled to the coordinating module and configured according to the set of
control signals, for transmitting/receiving data via the at least one communication network.

US Pat. No. 9,811,709

CAPACITOR SENSOR STRUCTURE, CIRCUIT BOARD STRUCTURE WITH CAPACITOR SENSOR, AND PACKAGE STRUCTURE OF CAPACITIVE SENSOR

MSTAR SEMICONDUCTOR, INC....

1. A capacitive fingerprint sensor structure, comprising:
a substrate;
a semiconductor chip, comprising a fingerprint sensing controller circuit; and
a redistribution layer (RDL), disposed on said substrate and electrically connected to said semiconductor chip, comprising:
a first wire, longer than an orthographic projection of said semiconductor chip;
a second wire, longer than said orthographic projection; and
a dielectric material, disposed between said first wire and said second wire,
wherein said RDL is a passive capacitance sensing circuit used by said fingerprint sensing controller circuit.

US Pat. No. 9,813,277

METHOD AND APPARATUS FOR PROCESSING A MULTIPLE-CARRIER SIGNAL PROVIDED WITH SUBCARRIERS DISTRIBUTED IN A BAND

MStar Semiconductor, Inc....

1. A method for processing a multiple carrier signal provided with subcarriers distributed in a band, comprising:
calculating a subcarrier noise of an edge of the band;
calculating a subcarrier noise of a center of the band;
calculating a first ratio of the subcarrier noise of the edge of the band to the subcarrier noise of the center of the band;
determining whether the first ratio is greater than a threshold;
acknowledging that the edge of the band suffers from interference when the first ratio is greater than the threshold; and
dividing the first ratio by a ratio of a frequency width of the edge of the band to a frequency width of the center of the
band.

US Pat. No. 9,674,012

DECISION FEEDBACK EQUALIZER AND CONTROL METHOD THEREOF

MStar Semiconductor, Inc....

1. A decision feedback equalizer (DFE), comprising:
a channel estimator, generating a channel impulse response (CIR) estimation vector according to an input signal at a CIR estimation
frequency;

a feed-forward equalizer (FFE) coefficient calculating unit, coupled to the channel estimator, generating an FFE coefficient
according to the CIR estimation vector at a first frequency;

a feed-backward equalizer (FBE) coefficient calculating unit, coupled to the channel estimator and the FFE coefficient calculating
unit, generating an FBE coefficient according to the CIR estimation vector and the FFE coefficient at a second frequency;

an FFE, coupled to the FFE coefficient calculating unit, generating a feed-forward equalization filtered result according
to the input signal and the FFE coefficient;

an FBE, coupled to the FBE coefficient calculating unit, generating a feed-backward equalization filtered result according
to a decision signal and the FBE coefficient; and

a decider, coupled to the FFE and the FBE, generating an updated decision signal according to the feed-forward equalization
filtered result and the feed-backward equalization filtered result;

wherein, at least one of the first frequency and the second frequency is smaller than the CIR estimation frequency,
wherein the first frequency is smaller than the second frequency.

US Pat. No. 9,552,482

METHOD FOR DETERMINING DEBUG AUTHORIZATION FOR MOTHERBOARD CONTROL MODULE AND ASSOCIATED MOTHERBOARD CONTROL MODULE

MStar Semiconductor, Inc....

15. A motherboard control module, comprising:
a chip, storing a device identity of the motherboard control module; and
a flash memory, comprising a plurality of data regions; and
a controller, configured to access the device identity, obtain a corresponding chip unique password according to the device
identity and a data region identity of a first data region of the data regions, compare a characteristic of the chip unique
password with a first chip unique reference password stored in the first data region, encrypt the first data region by an
exclusive proprietary private key of a manufacturer of the motherboard control module when the characteristic of the chip
unique password matches the first chip unique reference password to generate a digital signature, enable the digital signature
to be sent to a system manufacturer, wait to receive a debug approval corresponding to the digital signature from the system
manufacturer, and upon receiving the debug approval, deactivate a digital signature authentication mechanism of the flash
memory to authorize an execution of a debug function of the flash memory.

US Pat. No. 9,432,058

ERROR CORRECTION APPARATUS AND ASSOCIATED METHOD

MStar Semiconductor, Inc....

1. An error correction apparatus, applied to a digital signal received at a signal reception terminal, comprising:
a first error correction module, configured to perform first error correction on an input signal to generate an intermediate
signal satisfying a termination condition, wherein the input signal corresponds to the digital signal; and

a second error correction module, coupled to the first error correction module, for receiving and selectively performing second
error correction on the intermediate signal to generate a corrected signal;

wherein, the termination condition is associated with a maximum error correction capability of the second error correction,
wherein the first error correction is a low-density parity check (LDPC),
wherein the termination condition is that an error level of the intermediate signal is smaller than a threshold, the error
level is a parity check sum generated by the first error correction module according to the input signal and a parity check
matrix, and the threshold is associated with the maximum error correction capability of the second error correction, and

wherein when the intermediate signal is determined to be error-free, not performing the second error correction on the intermediate
signal and outputting the intermediate signal as the corrected signal,

wherein the second error correction is Boss-Chaudhuri-Hocquenghem (BCH) error correction, and the maximum error correction
capability is associated with a maximum recovery bit count of the second error correction,

wherein the termination condition is that an error level of the intermediate signal is smaller than the threshold, which is
a product of the maximum error correction capability and a predetermined weighting, and

wherein as a result of the threshold being calculated with respect to the maximum error correction capability, the second
error correction completely corrects the intermediate signal.

US Pat. No. 9,218,087

SELF-CAPACITIVE TOUCH PANEL

MSTAR SEMICONDUCTOR, INC....

1. A self-capacitive touch panel, comprising:
a border electrode, having a first centroid representing a position at which a detected capacitance change of the border electrode
occurs; and

a central electrode, having a second centroid representing a position at which a detected capacitance change of the central
electrode occurs;

wherein, a first average distance from the first centroid to all possible touch points in the border electrode is smaller
than a second average distance from the second centroid to all possible touch points in the central electrode.

US Pat. No. 9,203,677

SIGNAL PROCESSING METHOD AND ASSOCIATED APPARATUS

MStar Semiconductor, Inc....

1. A signal processing apparatus, receiving a spectral line corresponding to an original signal, comprising:
a starting point determining module, for finding a maximum energy of the spectral line and determining at least one search
starting point according to the maximum energy;

a searching module, for searching for at least one minimum energy from the at least one search starting point along the spectral
line towards a region having a lower energy, the at least one minimum energy satisfying a predetermined condition; and

a symbol rate determining module, for determining a symbol rate of the original signal according to the at least one minimum
energy.

US Pat. No. 10,050,821

RECEIVING CIRCUIT FOR ESTIMATING FREQUENCY OFFSET AND ASSOCIATED METHOD

MSTAR SEMICONDUCTOR, INC....

1. A receiving circuit for estimating a frequency offset, comprising:a front circuit, that receives a remote signal transmitted from a transmitting circuit, and accordingly generates a received signal; and
a calculation circuit, coupled to the front circuit, the calculation circuit configured to:
calculate an exponent of a power of the received signal to generate a high-order signal;
perform frequency-domain transform on the high-order signal to generate a spectrum;
search for a peak of an amplitude of the spectrum to generate a peak coordinate value reflecting a frequency at which the peak occurs; and
add the peak coordinate value with a compensation value to generate a sum, divide the sum by a first divisor to generate a remainder, subtract the compensation value from the remainder to generate a first difference, and divide the difference by a second divisor to generate an offset estimation value,
wherein the offset estimation value reflects the frequency offset between a local frequency of the transmitting circuit and a local frequency of a receiving circuit.

US Pat. No. 9,813,282

SAMPLING PHASE DIFFERENCE COMPENSATION APPARATUS AND METHOD, AND COMMUNICATION DEVICE CAPABLE OF COMPENSATING SAMPLING PHASE DIFFERENCE

MStar Semiconductor, Inc....

1. A sampling phase difference compensation apparatus, comprising:
a signal generator, generating a first signal and a second signal, outputting the first signal to a first path in a first
time interval, and outputting the second signal to a second path in a second time interval, wherein the first and second time
intervals are different, and the first and second paths are different;

a signal analyzer, receiving a transmitted first signal from the first path and a transmitted second signal from the second
path, and performing a predetermined calculation on the transmitted first and second signals to determine a phase difference
relationship between the transmitted first and second signals, wherein the phase difference relationship is associated with
a frequency-dependent phase difference and a sampling phase difference, the transmitted first signal is associated with the
first signal and the transmitted second signal is associated with the second signal; and

a compensator, performing a sampling phase difference compensation according to the phase difference relationship.

US Pat. No. 9,805,685

DISPLAY CONTROLLER, VIDEO SIGNAL TRANSMITTING METHOD AND SYSTEM THEREOF FOR TRANSMITTING VIDEO SIGNALS WITH MULTIPLE DATA RATE AND REDUCED NUMBERS OF SIGNALS LINE

MSTAR SEMICONDUCTOR, INC....

1. A method implemented in a first display controller, the method comprising:
receiving, by a processing circuit of the first display controller, a video signal;
converting, by the processing circuit, a first partial pixel data of the video signal to output a first display control signal,
the first display control signal including data displayed in a first portion of a frame;

generating, by a clock generator of an interface circuit of the first display controller, an external clock signal; and
processing, by the interface circuit, a second partial pixel data of the video signal to output a partial video signal to
a second display controller, the partial video signal being outputted together with the external clock signal, the partial
video signal including data displayed in a second portion of the frame, the first and the second portions being different
portions of the frame,

wherein the partial video signal comprises a data enable (DE) signal, a horizontal synchronization signal, a vertical synchronization
signal, a red data, a blue data and a green data, and

wherein the partial video signal is transmitted with a multiple data rate per clock cycle of the external clock signal such
that a number of signal lines needed by the partial video signal is reduced.

US Pat. No. 9,563,345

ELECTRONIC DEVICE AND METHOD FOR CONTROLLING THE SAME

MSTAR SEMICONDUCTOR, INC....

18. An electronic device, comprising:
a screen;
a gravity sensor, configured to detect a first tilt angle on a first virtual plane between the electronic device and a reference
plane in a first direction, and a second tilt angle on a second virtual plane between the electronic device and the reference
plane in a second direction; and

a control unit, configured to control the electronic device to perform an operation according to a combination of the first
tilt angle and the second tilt angle when the electronic device is in an unlocked state, and configured not to perform the
operation when the electronic device is in a locked state;

wherein the electronic device operates in either the locked state or the unlocked state;
wherein, when the combination of the first tilt angle and the second tilt angle satisfy a predetermined combination in a predetermined
time period, the control unit controls the electronic device to operate in either the locked state or the unlocked state;

wherein, the operation is associated with a user interface or an audio/video playback;
wherein, the first virtual plane and the second virtual plane are different planes; and
wherein, the electronic device is switched from the unlocked state to the locked state by a lock operation, and the lock operation
is triggered by detecting a finger press on the screen for a second predetermined time period.

US Pat. No. 9,524,212

METHOD, DEVICE AND OPERATING SYSTEM FOR PROCESSING AND USING BURN DATA OF NAND FLASH

MSTAR SEMICONDUCTOR, INC....

1. A non-transitory computer-readable storage medium with an executable program stored thereon for implementing a method for
processing burn data of NAND flash, before burning data, the method comprising:
identifying all half-empty blocks containing the burn data to be burned in the NAND flash, wherein the half-empty blocks includes
both blank pages and non-blank pages;

writing a predetermined label character to all of the blank pages of all of the half-empty blocks to convert the half-empty
blocks to full blocks, wherein the full blocks includes only non-blank pages, and the predetermined label character is used
for distinguishing the blocks written with the predetermined label character from other full blocks.

US Pat. No. 9,483,415

METHOD AND APPARATUS FOR MANAGING MEMORY

MStar Semiconductor, Inc....

1. An apparatus for managing a memory, the memory comprising a working region and a compression region, the working region
storing uncompressed data, the apparatus comprising:
a management module, configured to determine whether a set of target data is to be moved from the working region to the compression
region according to a recent usage index and a compression ratio of the set of target data; and

a compression/decompression module, configured to compress the set of target data and to move the compressed target data to
the compression region when the management module determines that the set of target data is to be moved,

wherein when a usage ratio of the working region is lower than a first threshold, the management module determines whether
to move the target data to the compression region according to an exchange condition; the exchange condition is associated
with the recent usage index and the compression ratio of the target data, and is associated with a set of first data in the
compression region; when the exchange condition is established, the compression/decompression module compresses the target
data, moves the compressed target data to the compression region, decompresses the first data, and moves the decompressed
first data to the working region.

US Pat. No. 9,484,040

AUDIO DECODING METHOD AND ASSOCIATED APPARATUS

MStar Semiconductor, Inc....

1. An audio decoding method, the method comprising:
dividing, in an audio decoding apparatus of a windows media audio (WMA) file playback apparatus, an audio data into a header
part and a data part;

determining a first packet data from the data part according to the header part, wherein the first packet data is a part of
the data part and a data size of the first packet is smaller than a data size of the data part;

generating a first packet header corresponding to the first packet data according to the header part, a data size of the first
packet header is smaller than a data size of the header part, and the first packet header is different from the header part;

inserting a predefined synchronization word and the first packet header at a beginning of the first packet data to generate
a first intermediate data;

detecting the synchronization word in the first intermediate data to confirm a position of the first packet data, and decoding
the first packet data according to the first packet header;

detecting whether a fast-forward command is received during decoding process, and generating a fast-forward message when the
fast-forward command is received;

determining a third packet data from the data part according to the information in the header part and the fast-forward message;
generating a third packet header corresponding to the third packet data according to the information in the header part;
generating a third intermediate data according to the synchronization word, the third packet header and the third packet data;
and

detecting the synchronization word in the third intermediate data, and decoding the third packet data according to the third
packet header,

wherein steps subsequent to receiving, and executing, the fast-forward command are all performed without re-reading the header
part.

US Pat. No. 9,444,610

METHOD AND DEVICE FOR DETECTING PRIMARY SYNCHRONIZATION SIGNAL

MSTAR SEMICONDUCTOR, INC....

1. A device for detecting a primary synchronization signal, comprising:
a capturing and storage module, configured to capture a time-domain signal sequence for synchronization;
a correlation module, coupled to the capturing and storage module, configured to obtain a correlation result corresponding
to the time-domain signal sequence, wherein the correlation result is a value obtained from performing a sliding correlation
on the time-domain signal sequence;

a normalization module, coupled to the correlation module, configured to normalize the correlation result according to a received
signal strength indicator corresponding to the time-domain signals to obtain a ratio of the correlation result to the received
signal strength indicator; and

a sorting module, coupled to the normalization module, configured to sort the normalized correlation result to ascertain a
position of a peak value corresponding to the correlation result, wherein the position of the peak value is a position of
the primary synchronization signal;

wherein, the correlation result is obtained according to a correlation operation on three sets of local characteristic sequences
when a sampling point is read to obtain the correlation result, and the received signal strength indicator corresponding to
the time-domain signal sequence and the correlation result are obtained in parallel in a same clock cycle; and

wherein, the correlation module comprises:
a correlation unit, configured to conjugate multiply the time-domain signal sequence having a first predetermined length with
a local characteristic sequence to obtain a decorrelation value, to group and sum up the decorrelation result according to
the first predetermined length to obtain an accumulated decorrelation value corresponding to the grouped decorrelation value,
and to sum up the accumulated decorrelation value to obtain the correlation result;

a phase rotation unit, configured to obtain a phase rotation value corresponding to a frequency offset of the time-domain
signal sequence;

wherein, after the correlation unit obtains the accumulated decorrelation value corresponding to the grouped decorrelation
value and before the correlation unit sums up the accumulated decorrelation value, the correlation unit further multiplies
the phase rotation value with the accumulated decorrelation value to obtain the accumulated decorrelation value that is frequency
offset eliminated; and

wherein, said decorrelation value is a sequence having a length of the first predetermined length.

US Pat. No. 9,443,109

COMPUTING DEVICE AND METHOD OF PROCESSING SECURE SERVICES FOR COMPUTING DEVICE

MSTAR SEMICONDUCTOR, INC....

1. A method of processing secure services, applied to a processing unit of a computing device to control the processing unit
to process multiple secure services, the computing device comprises a storage unit, the method comprising:
controlling a core of the processing unit to perform following steps in a secure mode:
accessing the storage unit to obtain a first command that comprises first secure service information;
processing a first secure service associated with the first secure service information according to the first command; and
accessing the storage unit to obtain a second command that comprises second secure service information, comprising:
storing the second command into the storage unit;
issuing a notification to the core which is in the secure mode;
controlling the core to access the storage unit according to the notification to obtain the second command; and
processing a second secure service associated with the second secure service information according to the second command;
wherein, during a period from a time point that the core accesses the storage unit to obtain the first command to a time point
that the core accesses the storage unit to obtain the second command, controlling the core to stay in the secure mode.

US Pat. No. 9,344,663

SENSING METHOD ON SENSING DEVICE BY SMART TERMINAL AND SMART TERMINAL USING THE SAME

MSTAR SEMICONDUCTOR, INC....

1. A sensing method for a smart terminal to interact with a sensing device in a remote control device, comprising:
(A), obtaining a current sensing device usage information by the smart terminal, wherein the current sensing device usage
information comprises an identity of a current application and a type of a sensing device currently applied by the current
application, wherein the current application is defined as an application opened on the smart terminal and also currently
being used by a user;

(B), determining whether a change occurs in a sensing device usage situation according to the current sensing device usage
information and a previous sensing device usage information pre-stored at the smart terminal; and

(C), transmitting a notification to the remote control device when the change occurs in the sensing device usage situation,
so that the remote control device takes control of the sensing device currently applied by the current application.

US Pat. No. 9,251,558

FRAME DRAWING METHOD, FRAME UPDATING METHOD AND ASSOCIATED MOBILE ELECTRONIC DEVICE

MSTAR SEMICONDUCTOR, INC....

1. A frame updating method, applied for updating a frame of an electronic device, the electronic device comprising a user
interface, the frame corresponding to a first region of a user interface, the frame updating method comprising:
determining a second region from the user interface, and storing an image of the second region into a memory, wherein the
second region comprises the first region;

fetching an image of the first region from the memory according to the first region to generate the frame;
receiving a movement command;
performing a movement on the first region in the user interface according to the movement command;
determining whether the moved first region exceeds the second region; and
when the moved first region exceeds the second region, updating the image of the second region in the memory.

US Pat. No. 9,148,309

APPARATUS AND METHOD FOR ESTIMATING CHANNEL EFFECTS

MSTAR SEMICONDUCTOR, INC....

1. An apparatus for estimating channel effects, comprising:
a receiver, configured to receive first data and first reference data arriving in a first time period, second data and second
reference data arriving in a second time period, and third data and third reference data arriving in a third time period,
wherein the first data, the second data and the third data are transmitted via a first sub-carrier, and the first reference
data, the second reference data and the third reference data are transmitted via a second sub-carrier;

an estimation circuit, configured to estimate channel effects corresponding to the first data, the third data, the first reference
data, the second reference data and the third reference data, respectively;

a coefficient calculation circuit, for performing a Wiener filter coefficient calculation according to the channel effects
corresponding to the first reference data, the second reference data and the third reference data to generate a set of time-domain
interpolation coefficients; and

an interpolation circuit, configured to interpolate the channel effects respectively corresponding to the first data and the
third data according to the set of time-domain interpolation coefficients to generate a channel effect corresponding to the
second data,

wherein the set of time-domain interpolation coefficients comprise a first coefficient W1 and a second coefficient W2, and
the coefficient calculation circuit generates the first coefficient W1 and the second coefficient W2 according to an equation:


where T1 represents the channel effect corresponding to the first reference data, T2 represents the channel effect corresponding
to the second reference data, and T3 represents the channel effect corresponding to the third reference data.

US Pat. No. 9,063,723

FUNCTION-BASED SOFTWARE COMPARISON METHOD

MStar Semiconductor, Inc....

1. A method for comparing a first subroutine and a second subroutine in functionality, comprising:
defining a plurality of instruction sets, each of which being associated with a corresponding instruction set process;
performing a capturing process to obtain a first program section and a second program section respectively from the first
subroutine and the second subroutine, and respectively categorizing the first program section and the second program section
to one of the instruction sets;

performing a program section comparison process to select and perform one of the instruction set processes according to the
instruction set to which the first program section is categorized and the instruction set to which the second program section
is categorized, so as to compare whether the first program section and the second program section are identical in functionality;
and

setting a first branch pointer to a value within a predetermined range;
wherein, the capturing process comprises performing a machine code capturing process, the machine capturing process comprising:
when the value of the first branch pointer falls within the predetermined range, obtaining a machine code from the first subroutine
according to a first pointer, and updating the first pointer to point to a next machine code in the first subroutine; when
the first branch pointer is not within the predetermined range, obtaining a machine code from the first subroutine according
to the first branch pointer, and updating the first branch pointer to point to a next machine code in the first subroutine;

after the machine code is obtained from the first subroutine, adding the machine code to the first program section; and
when the first program section cannot be categorized to any of the instruction sets, iterating the machine code capturing
process.

US Pat. No. 9,053,662

METHOD FOR ADJUSTING UNIFORMITY OF A DISPLAY PANEL AND ASSOCIATED DISPLAY CONTROLLER

MSTAR SEMICONDUCTOR, INC....

1. A method for adjusting a uniformity of a panel, the panel comprising a plurality of blocks, each of the blocks associating
a first input value to a corresponding display value via a measurement, the first input value comprising a first input component,
the method comprising:
adjusting a brightness of the display value corresponding to each of the blocks to match a target brightness by accordingly
providing a modified first input component corresponding to the first input component for each of the blocks;

each of the blocks associating a second input value to a corresponding color temperature value via the measurement, the second
input value comprising the modified first input component; and

adjusting the corresponding color temperature value of each of the blocks to match a target color temperature value by accordingly
providing a corresponding modified second input component and a corresponding modified third input component for each of the
blocks, so as to generate a corresponding modified display value according to the modified first input component, the modified
second input component and the modified third input component.

US Pat. No. 9,905,201

DISPLAY CONTROL METHOD AND DEVICE FOR APPLICATION PROGRAM INTERFACE

MSTAR SEMICONDUCTOR, INC....

1. A display control method for an application program interface, for controlling and displaying the application program interface
on a display device, the display control method comprising:
determining an appropriate resolution corresponding to an application program interface to be executed from at least two predetermined
selectable resolutions by:

determining whether the application program is in a white list, wherein the white list is established in advance and records
a list of application programs having the appropriate resolution as a predetermined resolution, and the predetermined resolution
is selected from the at least two predetermined selectable resolutions; and

determining that the appropriate resolution is the predetermined resolution when it is determined that the application program
is in the white list;

determining corresponding configuration information according to the appropriate resolution;
establishing a display window having a size equal to a size corresponding to the appropriate resolution according to the configuration
information, and loading a resource file corresponding to the application program interface; and

rendering the application program interface in the display window on the display device according to the appropriate resolution
and the resource file.

US Pat. No. 9,615,133

CONTROL MODULE OF MULTIMEDIA DEVICE AND METHOD FOR CONTROLLING MULTIMEDIA DEVICE TO GENERATE IMAGE DATA REQUIRED BY DISPLAY MODULE

MStar Semiconductor, Inc....

1. A control module of a television, configured to generate image data required by a display module, comprising:
a signal receiving and analyzing unit, configured to receive a first signal to accordingly generate a pre-boot command at
a first time point, and to receive a second signal to accordingly generate a boot command at a second time point; and

a processor, configured to perform a pre-boot process including television signal processing according to the pre-boot command
to generate the image data, and to enter a waiting mode when the pre-boot process is complete, and to exit the waiting mode
according to the boot command;

wherein, in the waiting mode the display module is not activated such that the image data is not used to display an image
by the display module when the processor remains in the waiting mode, and

wherein the television comprises the display module, and during the pre-boot process, according to the pre-boot command, the
processor sets a register value according to the boot command generated by the signal receiving and analyzing unit, after
the pre-boot process is complete, the processor controls the display module to display the image according to the register
value and the image data.

US Pat. No. 9,510,122

ELECTRONIC DEVICE, AND CALIBRATION SYSTEM AND METHOD FOR SUPPRESSING NOISE

MStar Semiconductor, Inc....

1. A calibration system, applied to an electronic device with noise suppression, comprising:
a first audio receiving module comprising a first microphone, configured to receive a voice and to generate a first received
result gained by an adjustment value;

a second audio receiving module comprising a second microphone, configured to receive the voice and to generate a second received
result gained by the adjustment value; and

a correction module, configured to correct the adjustment value;
wherein the electronic device performs noise suppression according to the first and second received results,
wherein the first audio receiving module and the second audio receiving module have an error tolerance that is between a first
error tolerance and a second error tolerance, the correction module calculates an actual error value from the first and second
received results, and the adjustment value remains uncorrected when an absolute value of the actual error value is greater
than twice an absolute value of the first error tolerance.

US Pat. No. 9,479,184

FREQUENCY CALIBRATION APPARATUS OF PHASE LOCKED LOOP AND METHOD THEREOF

MSTAR SEMICONDUCTOR, INC....

1. A frequency calibration apparatus, applied to a phased locked loop (PLL) that comprises a reference frequency divider,
a main frequency divider and a voltage control oscillator (VCO), the frequency calibration apparatus comprising:
a frequency detecting module, coupled to the reference frequency divider and the main frequency divider, that compares a feedback
clock with a reference clock to generate three comparison results, the frequency detecting module comprising:

a first counter that generates a first count according to the reference clock received from the reference frequency divider
during a monitoring period;

a second counter that generates a second count according to the feedback clock received from the frequency divider during
the monitoring period;

a comparing unit, coupled to the first counter and the second counter, that compares the second count with the first count
to generate the three comparison results; and

a search module, coupled to the comparing unit and the VCO, that selects three candidate frequency curves from a plurality
of candidate frequency curves and selects a frequency curve from the three candidate frequency curves for the VCO respectively
corresponding to the three comparison results.

US Pat. No. 9,460,687

CALIBRATION SYSTEM AND CALIBRATION METHOD FOR DISPLAY DEVICE

MStar Semiconductor, Inc....

1. A calibration system for a display device, comprising:
an image signal source, coupled to the display device, configured to drive the display device to display a reference image
and an indication icon in the reference image;

a user-motion sensing module, configured to detect a user motion and to generate a corresponding sensing result;
a control module, coupled to the user-motion sensing module and the image signal source, configured to control the image signal
source to move the indication icon according to the sensing result; and

a calibration interface, which allows a user to adjust an image characteristic parameter of the display device corresponding
to a region after the user selects the region in the reference image by the indication icon,

wherein the indication icon comprises a cursor; the control module fills coordinate information of the cursor into a hardware
cursor address buffer of the display device, fetches image information associated with the image characteristic parameter
from a corresponding data buffer, and retrieves the image characteristic parameter according to the image information.

US Pat. No. 9,418,600

APPARATUS FOR CONTROLLING A DISPLAY AND METHOD THEREOF

MStar Semiconductor, Inc....

1. An apparatus for controlling a display having a backlight module provided with a first set of backlight units and a display
panel provided with a second set of pixel units, the apparatus comprising:
a reference value generator that generates:
a reference value representative of a portion of pixels contained in an input image associated with one of the second set
of pixel units of the display panel, and

a maximum pixel value generated by selecting a maximum value from pixel values of the portion of pixels contained in the input
image;

a control value generator that generates a backlight control value, in view of the reference value and the maximum pixel value,
to control one of the first set of backlight units, the one of the first set of backlight units being associated with the
one of the second set of pixel units; and

a compensation circuit that adjusts the portion of pixels contained in the input image in view of the backlight control value,
wherein the compensation circuit comprises:
a calculating unit that estimates a backlight luminance corresponding to a target unit of the one of the second set of pixel
units, in view of a plurality of backlight control values of individual ones of the first set of backlight units that are
adjacent to the one of the first set of backlight units, for considering a diffusion property of light, and the backlight
control value, and

an adjusting unit that adjusts a pixel value of the portion of pixels contained in the input image associated with the target
unit according to the backlight luminance to provide an adjusted pixel value,

wherein the maximum pixel value is used, by the control value generator, to limit a minimum luminance of the one of the first
set of backlight units, and

wherein the compensation circuit calculates the adjusted pixel value according to an equation which is expressed as follows:
Y?=Y×BL full/BL P,
wherein:
Y? is the adjusted pixel value,
Y is the pixel value before adjusting,
BL full is the luminance of the one of the first set of backlight units before reducing, and
BL P is the backlight luminance corresponding to the target unit of the one of the second set of pixel units.

US Pat. No. 9,418,631

DISPLAY CONTROL APPARATUS AND METHOD AND IMAGE PROCESSING METHOD

MSTAR SEMICONDUCTOR, INC....

1. A display method, for displaying a frame on a display panel, comprising:
providing the frame comprising a valid data region that is larger than a visual region of the display panel, wherein a partial
region of the valid data region corresponds to the entire visual region, and the partial region has a same number of scan
lines as the visual region;

generating an output timing signal according to a relative position of the visual region corresponding to the valid data region,
such that said output timing signal corresponds to quantity of scan lines that only link to the partial region of the valid
data region;

outputting the frame and the output timing signal to the display panel so as to display the partial region of the valid data
region in the visual region of the display panel according to the output timing signal; and

providing a glasses control signal, so that a pair of 3D glasses is turned on during a scan interval corresponding to a remaining
region of the valid data region excluding the partial region.

US Pat. No. 9,337,940

SECOND-ORDER INTERMODULATION DISTORTION CALIBRATION APPARATUS, SYSTEM AND METHOD

MSTAR SEMICONDUCTOR, INC....

1. A second-order intermodulation distortion calibration transceiver system, comprising:
a transmitter, comprising:
a logic circuit, configured to provide two modulation signals, wherein the two modulation signals have different frequencies
when the calibration transceiver system operates in a calibration mode; and

two transmission paths, configured to up-convert and combine the two modulation signals to a radio-frequency (RF) transmission
signal; and

a receiver, comprising:
a reception path, configured to down-convert an RF reception signal to a baseband reception signal, and said RF transmission
signal serves as the RF reception signal when the calibration transceiver system operates in the calibration mode; and

a baseband signal processor, configured to process the baseband reception signal; and
a calibrator, configured to adjust the reception path in the calibration mode to minimize a signal strength of a second-order
crossover component of the baseband reception signal;

a coupling switch, coupled to the transmitter, the receiver and the calibrator, for selectively providing a closed circuit
such that the RF transmission signal serves as the RF reception signal to be provided to the receiver;

wherein, the calibrator further controls the coupling switch to selectively provide the closed circuit; and
wherein, the two modulation signals comprise a first modulation signal and a second modulation signal, the two transmission
paths comprise a first transmission path and a second transmission path, the first modulation signal is transmitted to the
first transmission path, and the second modulation signal is transmitted to the second transmission path.

US Pat. No. 9,330,664

CONTROLLER FOR VOICE-CONTROLLED DEVICE AND ASSOCIATED METHOD

MStar Semiconductor, Inc....

1. A controller for a voice-controlled device, comprising:
an environment detector, configured to detect an environment to obtain an environmental parameter associated with a volume
value;

a setting module, configured to set a threshold according to the environmental parameter, wherein the setting module sets
the threshold to a higher threshold when the volume value is higher and sets the threshold to a lower threshold when the volume
value is lower; and

a recognition module, configured to receive a speech, to perform speech recognition on the speech to generate a confidence
score of speech recognition, and to compare the confidence score of speech recognition with the threshold to generate a control
signal.

US Pat. No. 9,232,213

STEREO IMAGE OUTPUT APPARATUS AND ASSOCIATED METHOD

MSTAR SEMICONDUCTOR, INC....

1. A stereo image output method, comprising:
providing a first request command at a first time point, wherein the first request command corresponds to a second set of
stereo images;

outputting image frame information from a storage unit in response to the first request command, wherein the image frame information
comprises memory addresses of a first set of stereo images stored in a memory;

triggering an image synchronization operation to update the image frame information in the storage unit according to the first
request command;

outputting the first set of stereo images from the memory according to the outputted image frame information;
providing a second request command at a second time point, wherein the second request command corresponds to a third set of
stereo images;

outputting the updated image frame information from the storage unit in response to the second request command, wherein the
updated image frame information comprises memory addresses of the second set of stereo images stored in a memory; and

outputting the second set of stereo images from the memory according to the outputted updated image frame information.

US Pat. No. 9,612,696

SENSING ELECTRODES AND SENSING METHOD THEREOF

MStar Semiconductor, Inc....

1. A sensing method for a touch control apparatus, for sensing from a sensing electrode, the sensing electrode comprising
a plurality of first sensing electrode units arranged in a first direction and a plurality of dummy lines arranged between
the first sensing electrode units, the sensing method comprising:
sensing with the first sensing electrode units;
calculating a value in a sensed coordinate position corresponding to the first direction according to a sensed result of the
first sensing electrode units;

calculating a capacitance compensation value of a second direction according to the value of the first direction and a capacitance
compensation function associated with a capacitance sensing value sensed by at least one of the dummy lines, wherein the second
direction is perpendicular to the first direction; and

calculating a value in the sensed coordinate position corresponding to the second direction according to the capacitance compensation
value and a sensed result of the first sensing electrode units to obtain the sensed coordinate position.

US Pat. No. 9,503,292

METHOD AND DEVICE FOR CALCULATING COEFFICIENTS OF FEED-FORWARD EQUALIZER AND FEED-BACKWARD EQUALIZER IN DECISION FEEDBACK EQUALIZER

MSTAR SEMICONDUCTOR, INC....

1. A method for calculating a feed-forward equalizer (FFE) coefficient of an FFE in a minimum mean square error decision feedback
equalizer (MMSE-DFE) based on a fast transversal recursive squares (FT-RLS) algorithm, the FFE having a length LF, LF being a positive integer, the method comprising:
a) generating a channel impulse response (CIR) estimation vector h according to an input signal of the FFE;
b) generating a priori forward prediction error ? according to the CIR estimation vector h and a forward prediction coefficient
vector w;

c) providing a minimum cost of forward prediction ?;
d) generating a normalized gain vector c according to the forward prediction coefficient vector w, the minimum cost of forward
prediction ? and the priori forward prediction error ?, wherein the normalized gain vector c includes elements c[0] to c[LF];

e) providing a posteriori forward prediction error ?
f) updating the forward prediction coefficient vector w according to the posteriori forward prediction error ? and the normalized
gain vector c;

g) providing a conversion factor ?;
h) generating the FFE coefficient according to the conversion factor ? and the normalized gain vector c; and
updating the FFE with said FFE coefficient;
wherein, step (a) to step (g) are collectively a 1st iteration operation and have an LF number of iterations; step (d) is a 2nd iteration operation having an n number of iterations, and wherein in the Nth iteration of the LF iterations of the 1st iteration operation, the number of iterations of the 2nd iteration operation n equals N?1; the 2nd iteration operation computes the elements c[1] to c[N?1], and directly sets the elements c[N] to c[LF] to 0 instead of computing the elements c[N] to c[LF].

US Pat. No. 9,424,902

MEMORY CONTROLLER AND ASSOCIATED METHOD FOR GENERATING MEMORY ADDRESS

MStar Semiconductor, Inc....

12. A method for generating a memory address, for addressing a DDR DRAM, comprising:
determining a memory address of the DDR DRAM, the memory address comprising a bank group address;
determining a burst length of the DDR DRAM to be L, where L=2x;

receiving a system address; and
setting an (x+1)th bit from an LSB of the system address to be comprised in the bank group address of the memory address; wherein, L and x are
positive integers.

US Pat. No. 9,424,657

IMAGE MOTION DETECTION METHOD, IMAGE PROCESSING METHOD AND APPARATUS USING THE METHODS

MSTAR SEMICONDUCTOR, INC....

1. An image processing method, for detecting an image motion information between a first image unit and a second image unit,
wherein the first image unit and second image unit respectively comprises a plurality of blocks and each of the blocks comprises
a plurality of pixels; the image motion detection method comprising:
analyzing pixels at a same position in the blocks of the first image unit to generate a first image statistical information,
comprising a first brightness distribution information or a first color distribution information;

analyzing pixels at a same position in the blocks of the second image unit to generate a second image statistical information,
comprising a second brightness distribution information or a second color distribution information; and

comparing the first image statistical information with the second image statistical information to calculate the image motion
information, wherein the image motion information indicates a motion of a first pixel from a first position in said first
image unit to a second position in said second image unit;

wherein, the first position and the second position have a same brightness distribution or a same color distribution.

US Pat. No. 9,198,037

IDENTIFICATION PROCESSING APPARATUS AND MOBILE DEVICE USING THE SAME

MStar Semiconductor, Inc....

1. An identification processing apparatus, for use in a mobile device, for performing an identification procedure according
to a smart card, comprising:
a near field communication integrated circuit, comprising:
non-volatile memory for storing a first password; and
an authentication unit, coupled to the non-volatile memory, for determining whether to perform the identification procedure
according to the first password and a second password,

an antenna; and
a wireless charging unit that supplies power to the input interface in the absence of power being supplied from a battery
of the mobile device,

wherein the second password is received at the antenna when powered by the wireless charging unit,
wherein the wireless charging unit supplies power directly to the near field communication integrated circuit when the battery
is dead or the mobile device is turned off, the authentication unit performs the identification procedure when the battery
is dead or the mobile device is turned-off, and the second password is received at the antenna when the battery is dead or
the mobile device is turned-off,

wherein the authentication unit of the near field communication integrated circuit has an encryption unit, for encrypting
the first password, and upon determining to perform the identification procedure, the encryption unit is used for decrypting
the first password again.

US Pat. No. 9,177,712

TRANSFORMER

MStar Semiconductor, Inc....

1. A transformer, comprising:
a first substantially octagonally-shaped planar coil having a plurality of successive vertices defined by respective angled
intersections of adjacent segments of the first planar coil, having two input ends disposed, respectively, at two of the successive
vertices of the first planar coil, with a distance between the two input ends, wherein each input end is in electrical communication
with a series of adjacent segments and successive vertices that complete two full turns; and

a second planar coil, having two output ends disposed at a side substantially opposite the two input ends;
wherein, the second planar coil has two points relative to the two input ends of the first planar coil, and an exclusively
planar coil path length between the two points on the second planar coil is substantially equal to the distance of the two
input ends, and

wherein the two points on the second planar coil relative to the two input ends of the first planar coil have substantially
equal impedances, such that two input signals at the two input ends inducts equal energy at the two points on the second planar
coil and the two output ends produce two output signals with substantially equal signal strengths.

US Pat. No. 9,049,088

CARRIER AND SAMPLING FREQUENCY OFFSETS ESTIMATION METHOD AND ASSOCIATED APPARATUS APPLIED TO MULTI-CARRIER COMMUNICATION SYSTEM

MStar Semiconductor, Inc,...

1. A frequency offset estimation apparatus for a multi-carrier communication system, comprising:
a fast Fourier transform (FFT) unit, configured to transform a reception signal from a time domain to a frequency domain,
and to generate a plurality of samples corresponding to a plurality of symbols;

a conjugate multiplier, configured to generate a plurality of correlating complex numbers by conjugate multiplying the samples
corresponding to two consecutive symbols, wherein said consecutive symbols are corresponding to a plurality of predetermined
subcarrier indices;

a powering unit, configured to receive an exponent, raise the correlating complex numbers to a power of said exponent, and
to generate a plurality of powered correlating complex numbers; and

a calculation unit, configured to receive the powered correlating complex numbers and to estimate a frequency offset accordingly,
wherein the frequency offset comprises at least one of a carrier frequency offset (CFO) and a sampling frequency offset (SFO).

US Pat. No. 10,142,678

VIDEO PROCESSING DEVICE AND METHOD

MSTAR SEMICONDUCTOR, INC....

1. A video processing device, capable of automatically determining an operation mode, comprising:a memory, storing a display parameter of a predetermined mode;
a control signal processing circuit, receiving a control signal from a transmitter, and performing following steps according to at least one data access address indicated by the control signal when the predetermined mode is a first mode:
determining whether the data access address satisfies a predetermined access address;
outputting the display parameter of the predetermined mode in the memory to the transmitter when the data access address satisfies the predetermined access address; and
outputting a display parameter of a second mode to the transmitter after the display parameter of the predetermined mode in the memory is replaced by the display parameter of the second mode when the data access address does not satisfy the predetermined access address, and
a controller, causing the video processing device to operate in a first mode when the control signal processing circuit determines that the data access address satisfies the predetermined access address within a predetermined time interval, and causing the video processing device to operate in a second mode when the control signal processing circuit does not determine that the data access address satisfies the predetermined access address within the predetermined time interval.

US Pat. No. 10,090,061

MEMORY TEST DATA GENERATING CIRCUIT AND METHOD

MSTAR SEMICONDUCTOR, INC....

1. A memory test data generating circuit, generating a plurality of sets of test data, the plurality of sets of test data provided to a memory via a plurality of channels by a memory controller to test the memory, the memory test data generating circuit comprising:a plurality of counters, generating a plurality of counter values; and
a data repetition and combination unit, generating the plurality of sets of test data according to the plurality of counter values, a bit width between the memory test data generating circuit and the memory controller, and a bit width between the memory controller and the memory;
wherein, the test data of the channels is periodical identical data series.

US Pat. No. 9,635,639

PAGING INDICATOR TRANSMISSION METHOD, SYSTEM AND RECEPTION DEVICE FOR MOBILE COMMUNICATION SYSTEM

MSTAR SEMICONDUCTOR, INC....

1. A paging indicator transmission method for a mobile communication system, comprising:
step 1: paging a set of terminals by grouping paging indicators, and carrying paging indicators of each terminal by a paging
indicator channel, wherein the paging indicator channel of each cell utilizes a same burst structure comprising a training
sequence, and two paging indicators corresponding to each terminal, and the two paging indicators are located at known locations
on opposite sides of the training sequence, respectively;

step 2: determining whether a cell signal quality is greater than a set value K; and
step 3: the terminal controlling an RF component thereof to receive only a part of data of the timeslot where the paging indicator
channel is located, wherein

when the cell signal quality is greater than the set value K, the part of the data received by the RF component of the terminal
comprises the training sequence in the timeslot where the paging indicator PICH is located, and only one of the two paging
indicators corresponding to the terminal; and

when the cell signal quality is smaller than or equal to the set value K, the part of the data received by the RF component
of the terminal comprises the two paging indicators corresponding to the terminal in the timeslot where the paging indicator
channel is located, and all data between the two paging indicators including the training sequence of the timeslot where the
paging indicator channel is located.

US Pat. No. 9,577,789

FREQUENCY DEINTERLEAVING AND TIME DEINTERLEAVING CIRCUIT, METHOD THEREOF AND RECEIVING CIRCUIT OF DIGITAL TELEVISION

MStar Semiconductor, Inc....

1. A frequency deinterleaving and time deinterleaving circuit, configured to perform a frequency deinterleaving operation
and a time deinterleaving operation on an interleaved signal by using a first memory and a second memory, the circuit adapted
for multiple digital video standards, the circuit comprising:
a frequency deinterleaving control module, configured to generate a first access index according to a setting value;
a time deinterleaving control module, configured to generate a second access index according to the setting value;
a first address generating unit, configured to generate a first access address according to the first access index; and
a second address generating unit, configured to generate a second access address according to the second access index;
wherein, the setting value corresponds to a digital video standard of the interleaved signal; the first memory is accessed
for temporary data of the frequency deinterleaving operation according to the first access address, and the second memory
is accessed for temporary data of the time deinterleaving operation according to the second access address,

wherein the time deinterleaving control module further comprises a convolution operation unit and a row-column operation unit,
and the time deinterleaving control module selects one of the convolution operation unit and the row-column operation unit
according to the setting value.

US Pat. No. 9,495,054

TOUCH CONTROL SYSTEM AND COORDINATE CORRECTION METHOD THEREOF

MStar Semiconductor, Inc....

1. A touch control system, comprising:
a first sensing region;
a second sensing region, wherein a part of the first sensing region and a part of the second sensing region are defined as
an intersection region;

at least one first sensor, configured to monitor the first sensing region to generate at least one first sensing amount;
at least one second sensor, configured to monitor the second sensing region to generate at least one second sensing amount;
an initial coordinate generating module, configured to generate an initial coordinate according to the at least one first
sensing amount and the at least one second sensing amount, and to determine whether a touch point corresponding to the initial
coordinate is in the intersection region;

a correction value generating module, configured to generate a correction value according to the at least one first sensing
amount and the at least one second sensing amount when a determination result of the initial coordinate generating module
is affirmative; and

a corrected coordinate generating module, configured to multiply the initial coordinate by a first weight to generate a first
weighted result, to multiply the correction value by a second weight to generate a second weighted result, and to add the
first weighted result and the second weighted result to generate a corrected coordinate of the touch point.

US Pat. No. 9,489,084

SENSING METHOD AND SENSING APPARATUS FOR SENSING ELECTRODE CLUSTER

MSTAR SEMICONDUCTOR, INC....

1. A sensing method for a sensing electrode cluster, the sensing electrode cluster comprising a plurality of groups, each
comprising a plurality of bars, the sensing method comprising:
scanning each of the groups according to a first scanning sequence to generate a first position;
scanning each of the groups according to a second scanning sequence to generate a second position; and
determining a sensing position according to the first position and the second position;
wherein the first scanning sequence is different from the second scanning sequence.

US Pat. No. 9,462,336

TELEVISION CONTROL CHIP HAVING DATA PROTECTION FUNCTION AND METHOD FOR CONTROLLING TELEVISION SET

MSTAR SEMICONDUCTOR, INC....

1. A control chip, for controlling a television with a multimedia playback function and a data processing function, the control
chip comprising:
a multimedia playback circuit, driving the multimedia playback function and configured to generate multimedia playback information
by tracking an amount of multimedia data corresponding to a television program that has already been played;

a data processing circuit, driving the data processing function comprising a data storage function, a network transmission
function or a recording function, said data processing circuit configured to generate data processing information associated
with an amount of data that has been processed; and

a data protection circuit, coupled to the multimedia playback circuit and the data processing circuit, configured to control
the data processing circuit through an application program interface to a corresponding driver program layer or middleware
layer of the data processing circuit such that the television stops the data processing function, according to the multimedia
playback information and the data processing information,

wherein the multimedia playback circuit continually transmits the multimedia playback information to the data protection circuit,
the data processing circuit continually transmits the data processing information to the data protection circuit, and when
the amount of data that has been processed exceeds a predetermined value associated with the amount of multimedia data that
has already been played, the data protection circuit controls the data processing circuit, such that the television stops
the data processing function.

US Pat. No. 9,437,262

MEMORY CONTROLLER AND ASSOCIATED SIGNAL GENERATING METHOD

MStar Semiconductor, Inc....

1. A signal generating method of a memory controller, for controlling a memory module, comprising:
generating a first clock signal having a signal period of a unit time;
generating a command signal having a signal period of the unit time, wherein the command signal comprises a plurality of command
groups each having a first command and a second command that are consecutive;

generating an address signal set having a signal period of twice of the unit time;
setting a first signal edge of the first clock signal to within a latching interval of the command signal;
setting a second signal edge of the first clock signal to within the latching interval of the command signal and a latching
interval of the address signal set; and

controlling the memory module according to the command signal and the address signal.

US Pat. No. 9,429,620

SIGNAL PROCESSING SYSTEM WITH BIST FUNCTION, TESTING METHOD THEREOF AND TESTING SIGNAL GENERATOR

MStar Semiconductor, Inc....

1. A signal processing system, comprising:
a module under test, having a signal input end;
an oscillation signal generator, configured to generate an oscillation signal;
a translational filter, comprising a baseband filtering circuit and a mixer that is controlled by the oscillation signal,
the mixer having a high-frequency side and a low-frequency side, the high-frequency side being coupled to the signal input
end of the module under test, a low pass filter of the baseband filtering circuit being coupled to the low-frequency side;
and

a testing module, configured to provide a testing signal to the low-frequency side, so as to generate a high-frequency testing
signal at the high-frequency side of the mixer,

wherein the translation filter provides a bandpass filtering function controlled at least in part by the oscillation signal
for the module under test in a normal operation mode and up-converts the test signal to generate a high-frequency testing
signal at the high-frequency side of the mixer in a test mode.

US Pat. No. 9,420,218

TELEVISION SYSTEM

MSTAR SEMICONDUCTOR, INC....

1. A television system, comprising:
a television, comprising:
an image processing module integrated into said television, configured to perform an image processing procedure on an input
signal to generate an output image to be displayed on the television;

a display of said television, configured to play the output image; and
an image capturing module, integrated in a single chip and integrated into said television with the image processing module,
coupled to an input end and an output end of the image processing module, for receiving an image capturing instruction to
capture the input signal of the input end or the output image, and for selectively capturing one of the input signal and the
output image in response to an image capturing instruction, wherein the image capturing module captures the input signal or
the output image as a captured image and the captured image is an image file;

wherein, when the captured image is according to the output image, the captured image is a same image as an image to be displayed
on the television.

US Pat. No. 9,419,786

MULTI-LANE SERIAL LINK SIGNAL RECEIVING SYSTEM

MStar Semiconductor, Inc....

1. A multi-lane serial link signal receiving system, comprising:
a clock generating circuit, configured to provide a fundamental clock signal; and
a plurality of data receiving channels, each receiving an input signal and the fundamental clock signal, each comprising:
a phase detecting circuit, configured to sample the input signal according to a sampling clock signal to generate a sampled
signal;

a multi-order digital clock data recovery (DCDR) circuit, configured to perform a DCDR process on the sampled signal to generate
phase adjusting information; and

a phase adjusting circuit, configured to receive the phase adjusting information and the fundamental signal, and to adjust
a phase of the fundamental signal according to the phase adjusting information to generate the sampling clock signal for the
phase detecting circuit,

wherein the clock generating circuit generates the fundamental clock signal according to the local oscillation signal when
the multi-lane serial link signal receiving system is operated in a first mode and the fundamental clock signal according
to the input signal when the multi-lane serial link signal receiving system is operated in a second mode.

US Pat. No. 9,329,911

DRIVER INITIALIZATION FOR A PROCESS IN USER MODE

MSTAR SEMICONDUCTOR, INC....

1. A hardware control method for multitasking drivers under a user mode, comprising:
performing driver initialization for a current process under the user mode, comprising:
establishing a process image file to store register values exclusive to said current process for a hardware device; and
establishing a shared image file to store hardware device register values shared among processes;
receiving a request for access to the hardware device from the current process under the user mode, wherein the request comprises
a current identifier corresponding to the current process;

determining whether the current process has obtained a mutual exclusion (mutex) of the hardware device;
when the current process has obtained the mutex, determining whether the current identifier and a prior identifier corresponding
to a prior process that previously accessed the hardware device are the same; and when the current identifier and the prior
identifier are different, performing a context switch to the current process from the prior process to allow the current process
to access the hardware device, comprising:

reading said register values exclusive to said current process from said process image file; and
writing said register values exclusive to said current process to said process image file;
when the current process has obtained the mutex, determining whether an identifier of a first thread corresponding to the
current process and an identifier of a second thread corresponding to the prior process having previously obtained the mutex
are the same;

when the identifier of the first thread and the identifier of the second thread are the same, incrementing a mutex counter
by 1, and accessing the hardware device by the first thread; and

when the identifier of the first thread and the identifier of the second thread are different, waiting until the mutex is
obtained by the first thread.

US Pat. No. 9,331,823

WIRELESS COMMUNICATION APPARATUS AND METHOD

MSTAR SEMICONDUCTOR, INC....

1. A wireless communication apparatus, comprising:
a plurality of transceivers, corresponding to a plurality of component carriers, wherein at least one of the transceivers
connects to at least one first base station via at least one of the component carriers;

a communication module, connected to the transceivers, configured to perform communication according to the component carriers
corresponding to the transceivers; and

a processing module, while communication is performed by simultaneously utilizing the transceivers, configured to select a
first transceiver from the transceivers to receive information of at least one second base station, to select a second transceiver
from the transceivers, and to render the second transceiver to connect to the first base station via the component carrier
corresponding to the first transceiver, wherein the component carrier corresponding to the second transceiver and the component
carrier corresponding to the first transceiver are continuous carriers in a same waveband, to select the transceiver corresponding
to a least quantity of component carriers from the transceivers, to select the transceiver from the transceivers in turn,
to select the transceiver with least influences according to statuses of the component carriers corresponding to the transceivers
wherein a total bandwidth of the component carrier corresponding to the transceiver with the least influences is smaller than
respective total bandwidths of the component carriers corresponding to the other transceivers, to select the transceiver corresponding
to the component carrier that carries communication contents; and to select the transceiver corresponding to the component
carrier that only receives signals.