US Pat. No. 9,572,211

METHOD AND SYSTEM FOR IMPROVING LED LIFETIME AND COLOR QUALITY IN DIMMING APPARATUS

MICROCHIP TECHNOLOGY INCO...

1. A circuit arrangement for controlling a light emitting diode (LED) device, comprising:
a modulator operable to receive a pulse width modulation signal and a high frequency signal, and to generate a modulated high
frequency signal; and

a feedback circuit comprising an error amplifier and a compensation network, wherein the feedback circuit is synchronously
switched from a first configuration to a second configuration during off times of the modulated high frequency signal, wherein:

the first configuration comprises the error amplifier and compensation network coupled together; and
the second configuration comprises inverting and non-inverting inputs of the error amplifier shorted together.

US Pat. No. 9,269,597

OPEN CAVITY PLASTIC PACKAGE

MICROCHIP TECHNOLOGY INCO...

1. A process of manufacturing a sensor device comprising the steps of:
placing an integrated circuit die on a support placed on a bottom part of a mold;
wire-bonding the integrated circuit die;
placing a top part of a mold on top of said bottom part to form a cavity into which a plastic material can be injected to
form a package, wherein the top part of the mold comprises a spring-loaded pin arrangement comprising a cylindrical cover
having a conical recess that covers a sensor area on the integrated circuit die; and

injecting plastic material into the mold formed by the top and bottom part, wherein the cylindrical cover provides for an
opening in the package formed by said injected plastic material, wherein a pin extends from the cylindrical cover and is guided
within a spring housing wherein the pin can be vertically moved against a spring force.

US Pat. No. 9,071,181

THREE PHASE BRUSHLESS DC MOTOR SENSOR-LESS CONTROL USING SINUSOIDAL DRIVE METHOD AND APPARATUS

MICROCHIP TECHNOLOGY INCO...

1. A method for determining back electromotive force (BEMF) of a brushless direct current (BLDC) motor, said method comprising
the steps of:
detecting a substantially zero current in at least one phase of the BLDC motor;
computing each phase voltage of the BLDC motor when the substantially zero current is detected in the at least one phase of
the BLDC motor;

averaging the computed phase voltages; and
subtracting the averaged computed phase voltages from the computed phase voltage of the at least one phase in which the substantially
zero current was detected, wherein the difference thereof is the BEMF of the at least one phase.

US Pat. No. 9,450,585

SELECTING FOUR SIGNALS FROM SIXTEEN INPUTS

MICROCHIP TECHNOLOGY INCO...

1. An apparatus for selecting signals from a plurality of y signals in a device, comprising
a switching matrix receiving y input signals,
a plurality of multiplexers coupled with the switching matrix, each multiplexer having n inputs, one or more control inputs,
and a single output, wherein each multiplexer receives a set of n of said y signals,

a mode register coupled with the switching matrix allowing to program one of a plurality of assignment modes, wherein
in a first assignment mode the switching matrix operates to assign each multiplexer to a different set of n of said y signals,
wherein each set of n signals is divided into a plurality of subsets of input signals, wherein one of the subsets of each
multiplexer comprises more than one and less than n input signals and is also a subset of input signals of another multiplexer,
and

in a second assignment mode, the switching matrix assigns an identical set of input signals from said y input signals to all
of the plurality of independently controlled multiplexers.

US Pat. No. 9,287,884

ENHANCED NUMERICAL CONTROLLED OSCILLATOR

MICROCHIP TECHNOLOGY INCO...

1. A numerical controlled oscillator generating an output signal with a digital clock signal having a variable frequency,
wherein the numerical oscillator is controlled by a programmable numerical value being subject to a transfer function and
comprises a comparator configured to compare an output value of the transfer function with an output value of a duty cycle
register and to generate the output signal, wherein the output signal has a first logic state when the output value of the
transfer function is equal to or greater than the output value of the duty cycle register and otherwise a second logic state.

US Pat. No. 9,252,769

MICROCONTROLLER WITH OPTIMIZED ADC CONTROLLER

MICROCHIP TECHNOLOGY INCO...

1. A microcontroller comprising:
a plurality of ports coupled with an analog bus through an analog multiplexer;
an analog-to-digital converter (ADC) coupled with the analog bus, wherein the ADC comprises a sample and hold capacitor; and
a sample and hold pull up/down circuit coupled with the sample and hold capacitor, wherein each one of the plurality of ports
is programmable to operate as an analog input port, a digital input port or a digital output port and comprises a respective
port pull up/down circuit.

US Pat. No. 9,450,419

COMBINED POWER SUPPLY AND INPUT/OUTPUT SYSTEM WITH BOOST CAPABILITY

MICROCHIP TECHNOLOGY INCO...

1. A combined power and input/output system, comprising:
a host system operable to drive a high voltage and a low voltage on a combined power and I/O line;
a target system operably coupled to the host system via the combined power and I/O line; and
a power boost circuit in the target system coupled with the combined power and I/O line and operable to convert the high voltage
supplied on the combined power and I/O line to a voltage higher than the high voltage, wherein the higher voltage is stored
on a power supply capacitor, wherein the power boost circuit comprises an inductor and a diode interposed between the host
system and the power supply capacitor on the combined power and I/O line; and

a switching system operable in cooperation with the power boost circuit to charge and discharge the inductor into the power
supply capacitor during communication when said combined power and I/O line is at the high voltage.

US Pat. No. 9,312,852

INDUCTIVE LOAD DRIVER SLEW RATE CONTROLLER

MICROCHIP TECHNOLOGY INCO...

1. An integrated circuit for driving a first load switch wherein the first load switch powers a current load, the integrated
circuit comprising:
a first digital slew-rate control unit for generating control signals, wherein the first digital slew-rate control unit receives
a first input signal and generates first control signals based on the first input signal and a feedback signal that indicates
the rate of voltage change on the load; and

a first load driver circuit operated by the first control signals and the first input signal, wherein the first load driver
circuit comprises a large low impedance driver receiving said first control signals and a small current limited driver receiving
said first input signal, wherein an output of the large low impedance driver is coupled with the output of the small current
limited driver to generate a slew-rate controlled first output voltage for operating the first load switch.

US Pat. No. 9,306,746

RANDOMIZING CURRENT INJECTION CIRCUIT TO OBSCURE GATE NOISE FOR ADDED SECURITY

MICROCHIP TECHNOLOGY INCO...

1. A circuit for obscuring gate switching noise, comprising:
a synchronous clock source;
an asynchronous clock source;
a plurality of current sources;
a random number generating circuit receiving clock inputs from the synchronous clock source and the asynchronous clock source,
the random number generating circuit generating randomly changing asynchronous digital control signals, and

a bitstream buffer receiving the asynchronous digital control signals and controlling an amplitude of current from the plurality
of current sources, wherein the bitstream buffer comprises an input and a plurality of outputs, wherein each output has a
predefined offset with respect to a stored bitstream and wherein each current source is coupled with a different one of said
plurality of outputs.

US Pat. No. 9,281,808

VARIABLE VOLTAGE LEVEL TRANSLATOR

MICROCHIP TECHNOLOGY INCO...

1. An integrated circuit (IC) device comprising:
a microcontroller with an input/output I/O circuitry comprising a plurality of input/output ports, and
a plurality of external pins coupled with the microcontroller;
wherein the microcontroller comprises an I/O voltage supply comprising switching circuitry which is programmable through said
microcontroller,

at least one of the input/output ports is selectively connected to at least two different I/O supply voltages via switchable
connections controlled by the switching circuitry, and

wherein the microcontroller is configured to control the switching circuitry to dynamically and selectively control the switchable
connections between the at least one input/output port and the at least two different I/O supply voltages, and

wherein at least one of the at least two different I/O supply voltages is provided through one of the external pins and another
one of the at least two different I/O supply voltages is an internal supply voltage of the microcontroller.

US Pat. No. 9,189,940

METHOD AND APPARATUS FOR DETECTING SMOKE IN AN ION CHAMBER

MICROCHIP TECHNOLOGY INCO...

1. A method for detecting smoke, comprising the steps of:
coupling an ionization chamber to a capacitive sensing module (CSM);
determining a change in a capacitance of the ionization chamber using the CSM by:
determining a first change in the capacitance of the ionization chamber when the ionization chamber is at a first polarity;
determining a second change in the capacitance of the ionization chamber when the ionization chamber is at a second polarity;
determining a difference between the first change and the second change; and
using the difference in determining the change in the capacitance of the ionization chamber; and
detecting the presence of smoke by detecting a predetermined change in the capacitance.

US Pat. No. 9,154,155

2-PHASE SWITCHED CAPACITOR FLASH ADC

MICROCHIP TECHNOLOGY INCO...

1. An input stage for a switched capacitor analog-to-digital converter, comprising
a differential voltage input receiving an input voltage;
a differential reference voltage input receiving a chopped reference voltage;
a common voltage connection;
a differential output;
a pair of input capacitors coupled between the differential voltage input and the differential output;
a pair of reference capacitors coupled between the differential reference voltage input;
a switching unit controlled by a first and second phase operable
during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the
first terminal of the reference capacitors with the inverted differential voltage reference; and

during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple
the first terminal of the reference capacitors with the non-inverted differential voltage reference,

wherein the first and second phase are defined by non-overlapping clock signals.

US Pat. No. 9,467,154

LOW POWER AND INTEGRABLE ON-CHIP ARCHITECTURE FOR LOW FREQUENCY PLL

MICROCHIP TECHNOLOGY INCO...

1. An integrated circuit, comprising:
a phase detector;
a first charge pump and a second charge pump coupled to the phase detector, and configured to receive inputs from the phase
detector, the first charge pump outputting a low current and the second charge pump outputting a high current, wherein the
first charge pump and the second charge pump have synchronized outputs with respect to the inputs received from the phase
detector; and

a dual input loop filter coupled to the first charge pump and the second charge pump and comprising a first input receiving
the low current and a second input receiving the high current and an output providing for an output voltage.

US Pat. No. 9,342,195

SYSTEM AND METHOD TO SHARE ELECTRODES BETWEEN CAPACITIVE TOUCH CONTROLLER AND GESTURE DETECTION DEVICE

MICROCHIP TECHNOLOGY INCO...

1. A system comprising:
a capacitive touch controller,
a gesture detection device,
a capacitive sensor having at least one first and at least one second electrode, wherein the at least one first electrode
is coupled with a controllable generator for supplying an AC signal to said first electrode; and

a configurable coupling between the at least one second electrode, an input of the touch controller and an input of the gesture
detection device, wherein the coupling can be configured to allow the system to perform a touch detection from signals received
from said second electrode by the touch controller in a first configuration mode in which said controllable generator is turned
off and to perform a gesture detection from signals received from said second electrode by the gesture detection device in
a second configuration mode in which said controllable generator is turned on.

US Pat. No. 9,298,570

PROCESSOR DEVICE WITH RESET CONDITION TRACE CAPABILITIES

MICROCHIP TECHNOLOGY INCO...

10. A method for debugging executed code within a processor device comprising a system clock module for providing internal
clock signals, wherein resetting the processing device requires the system clock module to be reset for a minimum reset duration,
the method comprising:
executing code by a central processing unit (CPU);
upon determining of a reset, forwarding reset signals to internal units of the microcontroller with the exception of the system
clock module to allow further operation of a trace module;

recording trace information after reception of said reset by the trace module, and
generating a signal having said minimum reset duration after recording said trace information that resets the system clock
module.

US Pat. No. 9,240,785

ANALOG SIGNAL COMPATIBLE CMOS SWITCH AS AN INTEGRATED PERIPHERAL TO A STANDARD MICROCONTROLLER

MICROCHIP TECHNOLOGY INCO...

1. An microcontroller, comprising:
a plurality of external input/output connection;
a digital processor;
a memory coupled to the digital processor; and
at least one analog signal compatible complementary metal oxide semiconductor (CMOS) switch coupled to and controlled by the
digital processor, and configured to switch signals through a first and a second external input/output connection of said
plurality of external input/output connections, wherein the at least one analog signal compatible CMOS switch comprises a
first switching node coupled with the first external input/output connection of said plurality of external input/output connections
and a second switching node coupled with the second external input/output connection of said plurality of external input/output
connections, and

wherein the at least one analog signal compatible CMOS switch provides
a low impedance between the first external input/output connection and the second external input/output connection when the
digital processor asserts a control signal at a first logic level thereto, and

a high impedance between the first external input/output connection and the second external input/output connection when the
digital processor asserts the control signal at a second logic level thereto.

US Pat. No. 9,210,769

CONSTANT BRIGHTNESS LED DRIVE COMMUNICATIONS PORT

MICROCHIP TECHNOLOGY INCO...

1. A method for driving a light emitting diode (LED) and optically transmitting digital information using a single node of
an integrated circuit device, said method comprising the steps of:
generating a plurality of pulses from a single node of an integrated circuit device, wherein the pukes are arranged within
consecutive constant periods, each period having an ON time defined by a pulse and an OFF time; and

coupling the plurality of pulses from the single node of the integrated circuit device to a light emitting diode (LED);
wherein the plurality of pulses from the single node of the integrated circuit device control light intensity from the LED
and optically transmit digital information, wherein the light intensity from the LED is substantially proportional to pulse
widths of the plurality of pulses and wherein a bit is encoded within each period by either a falling or rising edge.

US Pat. No. 9,337,253

METHOD AND APPARATUS FOR CONSTRUCTING AN ISOLATION CAPACITOR IN AN INTEGRATED CIRCUIT

MICROCHIP TECHNOLOGY INCO...

9. An integrated circuit device adapted to have voltage isolation between different voltage domains, comprising:
a primary integrated circuit;
a first insulating layer over at least a portion of a face of the primary integrated circuit;
a plurality of first high voltage rated isolation capacitors over the first insulating layer, wherein each of the plurality
of first high voltage rated isolation capacitors comprises

a first electrically conductive layer on the first insulating layer, wherein the first insulating layer entirely insulates
the first electrically conductive layer, wherein some of the first electrically conductive layers are configured to be coupled
to respective circuit connection pads or leadframe finger connections on the primary integrated circuit;

a first high voltage rated dielectric layer on a portion of a respective one of the plurality of first electrically conductive
layers; and

a second electrically conductive layer on the respective high voltage rated dielectric layer, wherein the second electrically
conductive layer comprises at least one contact pad area which is electrically insulated from the primary integrated circuit.

US Pat. No. 9,312,844

SLOPE COMPENSATION MODULE

MICROCHIP TECHNOLOGY INCO...

1. A slope compensation module for use with current mode control in a switched-mode power supply (SMPS) controller,
said SMPS controller comprising:
an error amplifier comprising an output; and
a voltage comparator comprising a first input;
said slope compensation module comprises:
a slope compensation capacitor coupled between the output of the error amplifier and the first input of the voltage comparator;
a slope compensation switch coupled in parallel with the slope compensation capacitor; and
a programmable constant current source coupled to the an output side of the slope compensation capacitor and to the slope
compensation switch;

wherein when the slope compensation switch is open the slope compensation capacitor charges through the programmable constant
current source to a circuit common and thereby generates a linearly decreasing (negative slope) ramp voltage.

US Pat. No. 9,257,980

MEASURING CAPACITANCE OF A CAPACITIVE SENSOR WITH A MICROCONTROLLER HAVING DIGITAL OUTPUTS FOR DRIVING A GUARD RING

MICROCHIP TECHNOLOGY INCO...

13. A capacitive sensor system, said system comprising:
a capacitive sensor;
a guard ring associated with the capacitive sensor;
a first resistor coupled to the guard ring;
a second resistor coupled to the guard ring; and
a microcontroller, comprising:
a digital processor with memory;
a plurality of digital output drivers controlled by the digital processor;
a sample and hold capacitor;
an analog-to-digital converter (ADC) having a digital output coupled to the digital processor;
at least two digital output nodes of the microcontroller coupled to respective ones of the plurality of digital output drivers,
wherein one of the at least two digital output nodes is coupled to the first resistor and the other one of the at least two
digital output nodes is coupled to the second resistor;

a first analog node is coupled to a first analog bus in the microcontroller and the capacitive sensor;
the first analog bus is switchably coupled to a power supply common, a power supply voltage, the sample and hold capacitor,
or a second analog bus;

the second analog bus is switchably coupled to the power supply common, the power supply voltage, the sample and hold capacitor,
or the first analog bus; and

the sample and hold capacitor is switchably coupled to either the first analog bus or an input of the ADC.

US Pat. No. 9,172,387

SAMPLING INPUT STAGE WITH MULTIPLE CHANNELS

MICROCHIP TECHNOLOGY INCO...

1. An analog input stage having m differential input channels, wherein m>1,wherein the analog input stage is configured to
select one of the m differential input channels and provide an output signal, the analog input stage comprising;
n identical selection units each having m differential channel inputs and one differential output, wherein n is at least 2m?1:

each selection unit is operable to be coupled to any of the differential input channels through respective differential multiplexer
units, wherein the multiplexor units are driven to select one of the differential input channels and couple the selected differential
channel input through a butterfly switch unit with the differential output of the selection unit:

wherein the differential output signals of the n selection units are combined whereby unwanted crosstalk from channels other
than a selected channel are removed by cancellation, wherein the multiplexers in each of the n selection units are designed
to forward a respective differential input signals of a channel in a non-inverting or an inverting fashion when selected.

US Pat. No. 9,159,442

SERIAL MEMORY WITH FAST READ WITH LOOK-AHEAD

MICROCHIP TECHNOLOGY INCO...

1. A serial memory comprising:
memory arranged in a plurality of memory blocks,
a serial interface for receiving a read instruction and associated memory address; and
a controller configured to only store a plurality of most significant bits from each memory blocks which are accessed in parallel
before an entire address has been received through said serial interface, wherein the controller is further configured to
stream out one of the plurality of most significant bits upon full reception of the memory address while retrieving the remaining
bits from memory using the entire address and stream out the remaining bits after the most significant bits have been streamed
out, wherein most significant data bits of each memory block are accessible separately via a plurality of separate data lines
and wherein remaining data bits of each memory block are coupled in parallel via common data lines.

US Pat. No. 9,425,186

ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT

MICROCHIP TECHNOLOGY INCO...

1. An electrostatic discharge protection circuit, formed by a diode and a metal-oxide-semiconductor (MOS) transistor set on
a semiconducting substrate, comprising:
a first well, having a first conducting mode;
a second well, locating adjacent to the first well and having a second conducting mode;
a first high doping concentration region, locating in the second well and having a second conducting mode, the first high
doping concentration region electrically connected to a connected pad;

a second high doping concentration region, locating in the second well and having a first predetermined distance from the
first high doping concentration region, having a first conducting mode;

a third high doping concentration region, locating in the second well and having a first conducting mode;
a fourth high doping concentration region, locating in the first well and having a second predetermined distance from the
third high doping concentration region, having a first conducting mode, the fourth high doping concentration region electrically
connected to a ground pad;

a fifth high doping concentration region, locating in the first well and locating adjacent to the fourth high doping concentration
region, having a second conducting mode, the fifth high doping concentration region electrically connected to the ground pad;
and an electrode, locating on a surface of the second well between the third high doping concentration region and the fourth
high doping concentration region, the electrode electrically connected to a trigger point;

wherein the second high doping concentration region is electrically connected to the third high doping concentration region.

US Pat. No. 9,336,122

DEVICE HAVING CONFIGURABLE BREAKPOINT BASED ON INTERRUPT STATUS

MICROCHIP TECHNOLOGY INCO...

1. A processor device having debug capabilities, comprising:
a central processing unit;
an interrupt controller;
a status unit operable to be set into a first mode indicating an interrupt has occurred or into a second mode indicating normal
execution of code;

a debug unit coupled with said status unit and comprising a configurable breakpoint unit, wherein a condition can be set for
a breakpoint that the breakpoint is only activated if the device is executing any instruction within an interrupt service
routine and if the status unit is in the first mode.

US Pat. No. 9,306,055

HIGH VOLTAGE DOUBLE-DIFFUSED MOS (DMOS) DEVICE AND METHOD OF MANUFACTURE

MICROCHIP TECHNOLOGY INCO...

1. A double diffused metal oxide semiconductor (DMOS) transistor, comprising:
a substrate;
a base implant region formed in the substrate;
a source region formed in the base implant region;
a drain region formed in the substrate;
a floating gate formed above the substrate;
a control gate extending over the base implant region;
a floating gate electrode electrically coupled to the floating gate;
an oxide layer above said floating gate and said control gate;
a highly doped source implant implanted through a first vertical opening in the oxide layer, wherein the first vertical opening
is filled with a conductive material to provide for a source electrode contacting said source region;

a highly doped drain implant implanted through a second vertical opening in the oxide layer, wherein the second vertical opening
is filled with a conductive material to provide for a drain electrode contacting said drain region; and

control electronics configured to control a voltage applied to the floating gate via the floating gate electrode, thereby
controlling a breakdown voltage and a source-drain resistance of the DMOS transistor.

US Pat. No. 9,257,517

VERTICAL DMOS-FIELD EFFECT TRANSISTOR

MICROCHIP TECHNOLOGY INCO...

1. A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET), with a cell structure comprising:
a substrate of a first conductivity type forming a drain region;
an epitaxial layer of the first conductivity type on said substrate;
first and second base regions of a second conductivity type within said epitaxial layer, spaced apart by a predefined distance;
first and second source regions of a first conductivity type arranged in said first and second base regions, respectively,
wherein said first and second base region are operable to form first and second lateral channels between said source region
and said epitaxial layer;

a gate structure insulated from said epitaxial layer by an insulating layer and arranged above the region between the first
and second base regions and wherein the gate structure comprises first and second gate regions each forming a first and second
gate, each gate region only covering the first and second lateral channel, respectively within said first and second base
region, wherein the insulating layer comprises a gate oxide layer on top of which a thick oxide layer is arranged and patterned
to form a pedestal between said first and second source regions and wherein the gate structure is U-shaped and surrounding
said pedestal,

wherein the first and second gate are formed only by first and second vertical side walls of said U-shaped gate structure
and wherein the first and second vertical side walls have a thickness defined by a trench and horizontal bottom end faces
having said thickness of said trench form the first and second gate, respectively and cover the first and second lateral channels,
respectively.

US Pat. No. 9,176,011

SINGLE WIRE ANALOG OUTPUT SENSOR ARCHITECTURE

MICROCHIP TECHNOLOGY INCO...

1. A analog integrated sensor device comprising:
an interface with only two connecting lines including a ground line and a signal line, wherein the signal line is configured
to receive power and to output an analog value;

a power capacitor coupled between the ground line and the signal line and configured to be charged when a supply voltage is
fed to the signal line during a charging time period;

analog sensor circuitry operable to be powered by the power capacitor and further operable to output an analog output signal
on the signal line during an output time period once the power capacitor has been charged sufficiently.

US Pat. No. 9,144,041

CAPACITIVE/INDUCTIVE PROXIMITY DETECTION FOR WI-FI PROTECTION

MICROCHIP TECHNOLOGY INCO...

1. A wireless device comprising:
a Wi-Fi unit having a controllable power output radio frequency amplifier;
at least one capacitive sensor and at least one inductive sensor located at each corner of said wireless device; and
a microcontroller and memory, said microcontroller further comprising:
an inductive sensor interface coupled to the inductive sensors,
a capacitive sensor interface coupled to the capacitive sensors, and
an analog-to-digital converter (ADC) having analog inputs coupled to the inductive and capacitive sensor interfaces and digital
outputs coupled to the microcontroller;

wherein the microcontroller determines when there is a change in a capacitance value of any one of the capacitive sensors,
thereafter determines whether there is a change in an inductance value of any one of the inductive sensors and whether there
is a change in mutual capacitance values between the capacitive sensors;

whereby if the capacitive value of any one of the capacitive sensors has changed and the inductive value of any one of the
inductive sensors has changed then the power output of the radio frequency amplifier is reduced; and

whereby if the capacitive value of any one of the capacitive sensors has changed and any one of the mutual capacitance values
has changed then the power output of the radio frequency amplifier is reduced.

US Pat. No. 9,071,264

MICROCONTROLLER WITH SEQUENCER DRIVEN ANALOG-TO-DIGITAL CONVERTER

MICROCHIP TECHNOLOGY INCO...

1. A microcontroller comprising:
a central processing unit (CPU);
at least one analog input port coupled with a first external pin of the microcontroller which is operable to be coupled with
an external sensor capacitor,

an analog to digital converter (ADC) for measuring a capacitance of the external sensor capacitor;
a pre-charge unit operable to independently pre-charge the external sensor capacitor and an internal sample & hold capacitor
of the ADC to either one of a first and second voltage;

a sequencer operable to be programmed by said CPU and operable to determine a timing sequence for pre-charging said external
and internal capacitors, parallel switch said internal and external capacitors to share a charge and control the ADC to measure
the shared charged.

US Pat. No. 9,388,621

DECRYPTION OF ACCESS CODES OF DIVERSE PROTOCOLS IN BARRIER OPERATOR SYSTEMS

Overhead Door Corporation...

1. A barrier operator system for controlling a motor to move a barrier between open and closed positions, comprising:
remote control transmitter devices capable of each transmitting encrypted commands of first and second encryption protocols;
and

a barrier operator, including a receiver, comprising a microcontroller configured to decrypt encrypted commands of said first
and second encryption protocols, thereby to actuate said motor in accordance with such differently encrypted commands;

wherein the microcontroller is also configured to, based on receipt of a first user input, enter a learn mode which permits
selection of one of multiple different operational parameters of the barrier operator for adjustment, the selection being
based upon a second user input subsequent in time to the first user input;

wherein a given one of the multiple different operational parameters comprises which encrypted commands of the second encryption
protocol are known by the microcontroller, and wherein permission of the selection of the given one of the multiple different
operational parameters is based upon the second user input being receipt of a known encrypted command of the first encryption
protocol;

wherein the microcontroller is also configured to, when in the learn mode and the given one of the multiple different operational
parameters is selected, learn a new encrypted command of the second encryption protocol.

US Pat. No. 9,258,027

PROXIMITY DETECTION USING AN ANTENNA AND DIRECTIONAL COUPLER SWITCH

MICROCHIP TECHNOLOGY INCO...

4. A mobile device with proximity detection functionality, comprising: a digital processor,
an antenna,
a device directional coupler controlled by the digital processor for coupling the antenna with a radio frequency (RF) system,
wherein the device directional coupler comprises:

a directional coupler switching unit configured to selectively couple either the RF system or a capacitance measurement device
with the antenna,

wherein the digital processor is operable to measure a capacitance value of the antenna through the capacitance measurement
device when said directional coupler switching unit is controlled to couple the antenna with the capacitance measurement device
and further to determine whether the measured capacitance value of the antenna has changed from a previous measurement of
a capacitance value of the antenna, and to detect proximity of an person to the antenna when the capacitive value of the antenna
has changed by at least a certain value.

US Pat. No. 9,286,241

CRYPTOGRAPHIC TRANSMISSION SYSTEM

MICROCHIP TECHNOLOGY INCO...

9. A method for handling encryption keys in processor microcontroller, comprising:
selecting a key encryption key (KEK) from a predetermined one of a plurality of key storage slots arranged in non-volatile
memory through a select register coupled with a CPU of the microcontroller, wherein the plurality of key storage slots are
each configured to store either a Key Encryption Key (KEK) or a key for encrypting/decrypting data and wherein the on-chip
key storage slots can only be accessed by a hardware encryption/decryption engine and cannot be accessed by the CPU of the
microcontroller thereby forming a firewall between non-volatile memory coupled with the hardware encryption/decryption engine
which are inside the firewall and the CPU which is outside the firewall;

transferring a content of the selected on-chip key storage slot to a key register which is accessible to the hardware encryption/decryption
engine;

checking a register flag in a configuration register coupled with the hardware encryption/decryption engine to determine if
the key encryption key is to be used for encrypting/decrypting data or encrypting/decrypting a session key; and

if the key encryption key is to be used for encrypting/decrypting a session key, preventing the key encrypt key from encrypting/decrypting
data.

US Pat. No. 9,197,271

PROXIMITY DETECTION USING AN ANTENNA AND DIRECTIONAL COUPLER SWITCH

MICROCHIP TECHNOLOGY INCO...

1. A method for determining proximity of a object to an antenna of a radio frequency device, said method comprising the steps
of:
measuring a reflected voltage standing wave value of the antenna through a return loss bridge coupled between the antenna
and a directional coupler switch operable to switch between a plurality of ports, wherein the directional coupler switch comprises
at least a first port coupled with an RF subsystem;

determining whether the reflected voltage standing wave value of the antenna has changed from a previous measurement of a
reflected voltage standing wave value of the antenna; and

detecting proximity of the object to the antenna when the reflected voltage standing wave value of the antenna has changed
by at least a certain value.

US Pat. No. 9,338,035

MICROCONTROLLER WITH CAN BUS MODULE AND AUTO SPEED DETECT

MICROCHIP TECHNOLOGY INCO...

1. A method for initializing a Controller Area Network (CAN) module in a microcontroller,
the method comprising:
measuring period times between a plurality of falling or rising edges of a CAN signal;
sorting said period times by their respective value;
determining difference values between adjacent period times of said sorted period times;
sorting said difference values by their respective value;
selecting a first difference value from said sorted difference values and determining a first frequency from said first difference
value;

initializing said CAN module using said selected frequency;
receiving a CAN signal frame;
determining whether an error occurred;
in response to said determining of an error, selecting a next difference value from said sorted difference values and determining
an associated frequency and repeating initializing the CAN module until a valid CAN frequency has been found.

US Pat. No. 9,310,828

COMPLEMENTARY OUTPUT GENERATOR MODULE

MICROCHIP TECHNOLOGY INCO...

1. A complementary output generator module for a microcontroller, wherein the complimentary output generator is configurable
through a processing core of the microcontroller and comprises:
a clock input coupled to a clock source;
a plurality of rising event inputs that are programmably selectable, wherein at least one of the selected rising event inputs
initiates a rising event signal synchronous with the clock source when at least one rising event occurs at a respective selected
one of the rising event inputs;

a plurality of falling event inputs that are programmably selectable, wherein at least one of the selected falling event inputs
initiates a falling event signal synchronous with the clock source when at least one falling event occurs at a respective
selected one of the falling event inputs; and

a plurality of outputs, wherein
a first one of the plurality of outputs asserts a first output drive signal upon detection of the rising event signal until
detection of the falling event signal, and

a second one of the plurality of outputs asserts a second output drive signal upon detection of the falling event signal until
detection of a next rising event signal.

US Pat. No. 9,310,952

CAPACITIVE TOUCH SYSTEM USING BOTH SELF AND MUTUAL CAPACITANCE

MICROCHIP TECHNOLOGY INCO...

1. A method for determining multiple touch events in a multi-touch sensor system having a touch sensor including a plurality
of nodes defined by a plurality of first electrodes arranged in a first layer and second electrodes arranged in a second layer,
the method comprising:
performing self capacitance measurements for at least two of the plurality of second electrodes using a capacitance detector;
detecting one or more touch events as a result of the performed self capacitance measurements;
performing a plurality of mutual capacitance measurements for only a subset of the nodes, wherein the subset is fewer than
all of the nodes and includes at least the nodes corresponding to the touch events and wherein a mutual capacitance measurement
is performed between first and second electrodes, wherein a pulse drive circuit is connected with one of said first electrodes
and the capacitance detector is connected with one of said second electrodes and wherein the pulse drive circuit is synchronized
with the capacitance detector, wherein a mutual capacitance measurement is based on charging and/or discharging of a measured
capacitance and the pulse drive circuit is synchronized to influence the charging and/or discharging of the measured capacitance;
and

detecting two or more touch events as a result of the plurality of mutual capacitance measurements.

US Pat. No. 9,301,086

DATA TRANSMISSION SYSTEM AND METHOD FOR BLUETOOTH INTERFACE

MICROCHIP TECHNOLOGY INCO...

1. A data transmission system of a Bluetooth interface, the data transmission system comprising:
a central electronic apparatus comprising a central Bluetooth module; and
a peripheral electronic apparatus comprising a peripheral Bluetooth module,
wherein a transmitting and receiving operation of a plurality of characteristic information is performed between the central
Bluetooth module and the peripheral Bluetooth module, wherein the characteristic information indicates a plurality of buffer
size information in the central Bluetooth module and the peripheral Bluetooth module, and a data transmission operation is
performed between the central Bluetooth module and the peripheral Bluetooth module based on the characteristic information
through a central enable flag and a peripheral Bluetooth module enable flag respectively.

US Pat. No. 9,261,931

PERIPHERAL SPECIAL FUNCTION REGISTER WITH SOFT-RESET DISABLE

MICROCHIP TECHNOLOGY INCO...

1. A microcontroller comprising a plurality of peripherals wherein one of the peripherals is a digital to analog converter
having an output coupled with an external pin of the microcontroller,
wherein the microcontroller is operable to be reset by a power supply reset and wherein the microcontroller is further operable
to generate an internally generated reset signal, and wherein the digital to analog converter is configurable through a configuration
register comprising at least one control bit,

wherein the control bit controls an operating mode of the digital to analog converter such that in a first operating mode,
both the power supply reset signal and the internally generated reset signal reset the digital to analog converter and in
a second operating mode only a power supply reset resets the digital to analog converter and wherein the digital to analog
converter maintains an output voltage programmed though an associated special function register at the external pin.

US Pat. No. 9,207,209

METHOD AND APPARATUS FOR DETECTING SMOKE IN AN ION CHAMBER

MICROCHIP TECHNOLOGY INCO...

1. A method for detecting smoke, comprising the steps of:
determining a voltage on a conductive screen with a delta-sigma analog-to-digital converter, wherein the conductive screen
is located between a first ion chamber and a second ion chamber, wherein the first ion chamber is open to smoke ingress and
the second ion chamber is closed to smoke ingress; and

detecting a presence of smoke by:
applying a first voltage potential to the first and second ion chambers at a first polarity;
determining a first voltage on the conductive screen caused by the first voltage potential at the first polarity;
applying a second voltage potential to the first and second ion chambers at a second polarity;
determining a second voltage on the conductive screen caused by the second voltage potential at the second polarity;
determining a voltage difference between the first and the second voltages; and
detecting the presence of smoke when the voltage difference changes by a certain amount.

US Pat. No. 9,504,122

FLUORESCENT REPLACEMENT LED LAMPS

MICROCHIP TECHNOLOGY INCO...

1. A light emitting diode (LED) apparatus for replacing a fluorescent lamp, comprising:
a LED lamp structure having first, second, third and fourth electrical contacts configured to match size and locations of
respective electrical contacts of a fluorescent lamp;

a first LED light string and first power supply located in the LED lamp structure, the first power supply having plus and
minus power inputs;

a second LED light string and second power supply located in the LED lamp structure, the second power supply having plus and
minus power inputs;

a first plurality of diodes arranged in a bridge rectifier configuration and having first, second, third and fourth nodes,
wherein the first node is coupled to the minus power input of the first power supply, the second node is coupled to the first
electrical contact, the third node is coupled to the plus power input of the first power supply, and the fourth node is coupled
to the second electrical contact;

a second plurality of diodes arranged in a bridge rectifier configuration and having first, second, third and fourth nodes,
wherein the first node is coupled to the minus power input of the second power supply, the second node is coupled to the third
electrical contact, the third node is coupled to the plus power input of the second power supply, and the fourth node is coupled
to the fourth electrical contact;

a third plurality of diodes arranged in a series coupled string, wherein an anode of the series coupled string of the third
plurality of diodes is coupled to the minus power input of the first power supply and the first node of the first plurality
of diodes, and a cathode of the series coupled string of the third plurality of diodes is coupled to the plus power input
of the second power supply and the third node of the second plurality of diodes; and

a fourth plurality of diodes arranged in a series coupled string, wherein an anode of the series coupled string of the fourth
plurality of diodes is coupled to the minus power input of the second power supply and the first node of the second plurality
of diodes, and a cathode of the series coupled string of the fourth plurality of diodes is coupled to the plus power input
of the first power supply and the third node of the first plurality of diodes.

US Pat. No. 9,412,942

RESISTIVE MEMORY CELL WITH BOTTOM ELECTRODE HAVING A SLOPED SIDE WALL

MICROCHIP TECHNOLOGY INCO...

1. A method of forming a resistive memory cell, comprising:
forming a plurality of bottom electrode connections;
depositing a bottom electrode layer over the bottom electrode connections;
performing a first etch to remove portions of the bottom electrode layer such that the remaining bottom electrode layer defines
at least one sloped surface;

forming an oxidation layer on each sloped surface of the remaining bottom electrode layer;
performing a second etch on the remaining bottom electrode layer and oxidation layer on each sloped surface to define at least
one upwardly-pointing bottom electrode region above each bottom electrode connection, each upwardly-pointing bottom electrode
region defining a bottom electrode tip;

removing the oxidation layer on each sloped surface; and
forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged
between the top electrode and the respective bottom electrode top.

US Pat. No. 9,245,988

ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND ELECTRONIC APPARATUS THEREOF

MICROCHIP TECHNOLOGY INCO...

1. An electrostatic discharge protection device, comprising:
a substrate;
a first P-well, formed in the substrate, wherein along a specific direction, the P-well has a first N-type high doping region,
a first P-type high doping region, a second N-type high doping region, a second P-type high doping region, and a third N-type
high doping regions sequentially located thereon, and the first, third N-type high doping regions and the first, second P-type
doping regions are connected to a first ground end; and

a first N-well, formed in the substrate, neighboring to the first P-well, wherein along the specific direction, the N-well
has a third P-type high doping region, a fourth N-type high doping region, a fourth P-type high doping region, a fifth N-type
high doping region, and a fifth P-type high doping regions sequentially located thereon, and the third, fifth P-type high
doping regions and the fourth, fifth N-type high doping regions are coupled to a first voltage supply end, and the second
N-type high doping region, the fourth P-type high doping region are coupled to the first input/output end.

US Pat. No. 9,207,820

METHOD AND SYSTEM FOR MULTI-TOUCH DECODING

Microchip Technology Inco...

1. A method for decoding multiple touches on a touch sensing surface, said method comprising the steps of:
scanning a plurality of channels aligned on an axis for determining self values of the channels;
determining left and right slope values for at least one self value, wherein local maximum self values are determined by detecting
a slope sign transition and potential maximum self values are each determined by a predetermined change of slope ratios between
respective left and right slope;

scanning a plurality of nodes of those channels that have the local maximum self value for determining mutual values of the
nodes; and

comparing the mutual values to determine which one of the nodes has the largest mutual value, wherein the node having the
largest mutual value on the local maximum self value channel is a potential touch location.

US Pat. No. 9,354,743

APPARATUS FOR IMPROVING SIGNAL-TO-NOISE PERFORMANCE OF PROJECTED CAPACITANCE TOUCH SCREENS AND PANELS

MICROCHIP TECHNOLOGY INCO...

1. An apparatus for generating a high voltage and selectively coupling the high voltage to a plurality of nodes, comprising:
a voltage boost circuit having a high voltage output;
a voltage reference coupled to the voltage boost circuit;
a plurality of voltage level shifters/drivers, each one having a high voltage input coupled to the high voltage output of
the voltage boost circuit and an independently controllable high voltage output;

logic circuits coupled to the plurality of voltage level shifters/drivers, wherein the logic circuits control the high voltage
outputs thereof; and

a serial-to-parallel interface coupled to the logic circuits and the voltage boost circuit.

US Pat. No. 9,356,613

PULSE DENSITY MODULATION DIGITAL-TO-ANALOG CONVERTER WITH TRIANGLE WAVE GENERATION

MICROCHIP TECHNOLOGY INCO...

1. A pulse density modulated digital-to-analog converter (PDM DAC) with triangle wave generation, comprising:
a pulse density modulation (PDM) generator having an input;
a low pass filter coupled to an output of the PDM generator; and
a triangle wave generator having an output providing digital values representing a triangle waveform to the input of the PDM
generator, wherein an output pulse sequence of the PDM generator is determined by the digital values generated by the triangle
wave generator and the low pass filter outputs the triangle waveform.

US Pat. No. 9,093,433

USING BUMP BONDING TO DISTRIBUTE CURRENT FLOW ON A SEMICONDUCTOR POWER DEVICE

MICROCHIP TECHNOLOGY INCO...

1. A semiconductor power chip, comprising:
a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device comprises at least one
first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of
said semiconductor die, wherein the first, second and third contact elements are arranged in parallel and each has the form
of an elongated strip;

a loaf bump disposed on each of the plurality of second contact elements and the plurality of third contact elements wherein
each loaf bump extends substantially over a respective surface area of the plurality of second contact elements and the plurality
of third contact elements; and

at least one ball bump or loaf on the at least one first contact element.

US Pat. No. 9,431,390

COMPACT ELECTROSTATIC DISCHARGE (ESD) PROTECTION STRUCTURE

MICROCHIP TECHNOLOGY INCO...

1. An electrostatic discharge (ESD) protection device, comprising:
a field effect transistor (FET) having a drain, at least two gates and a source, wherein the drain thereof is coupled to a
node of a circuit to be protected from an ESD event;

at least one diode coupled between the source of the FET and a power supply common;
a first resistor coupled between the at least two gates of the FET; and
a second resistor coupled to a one of the at least two gates and the power supply common.

US Pat. No. 9,257,899

CHARGE PUMP CIRCUIT AND PHASE LOCK LOOP CIRCUIT HAVING THE SAME

MICROCHIP TECHNOLOGY INCO...

1. A charge pump circuit, comprising:
an up-side current source, configured for providing a first current;
a down-side current source, configured for providing a second current;
a main switch set, an end of the main switch set connected with the up-side current source serially and another end of the
main switch set connected with the down-side current source serially, the main switch set having a control end, the main switch
set configured for controlling the first current to flow from the up-side current source to the control end according to a
rising signal, controlling the second current to flow from the control end to the down-side current source according to a
falling signal, and outputting a voltage of the control end;

an assist switch set, an end of the assistant switch set electrically connected with the end of the main switch set and another
end of the assistant switch set electrically connected with the another end of the main switch set, the assistant switch set
having an assistant end, the assistant switch set configured for controlling the first current to flow from the up-side current
source to the assistant end according to the inversely rising signal, and controlling the second current to flow from the
assistant end to the down-side current source according to the inversely falling signal;

a main voltage divider, coupled to the main switch set and configured for generating a voltage division to the control end
when the charge pump circuit is activated, and stopping generating the voltage division to the control end after a predetermined
time of activating the charge pump circuit; and

an assistant voltage divider, coupled to the assistant switch set and generating the voltage division to the assistant end.

US Pat. No. 9,257,942

AUDIO AMPLIFIER APPARATUS

MICROCHIP TECHNOLOGY INCO...

1. An audio amplifier apparatus, suitable for driving a loudspeaker, the audio amplifier apparatus comprising:
a soft charge unit, coupled to the loudspeaker through an output terminal, and supplying a driving current according to a
first control signal to soft charge the loudspeaker, so as to gradually increase a voltage level on the output terminal;

a first amplification module, coupled to the output terminal, receiving an audio signal according to the first control signal,
and amplifying the audio signal to output a first amplified signal for driving the loudspeaker, wherein the first amplification
module comprises:

a first amplifier, having an input terminal and an output terminal, wherein the input terminal of the first amplifier receives
the audio signal, and the output terminal of the first amplifier outputs the first amplified signal; and

a first capacitor, having a first end and a second end, wherein the first end of the first capacitor is coupled to the input
terminal of the first amplifier, and the second end of the first capacitor is coupled to the output terminal of the first
amplifier;

a second amplification module, coupled to the output terminal, receiving the audio signal according to a second control signal,
and amplifying the audio signal to output a second amplified signal for driving the loudspeaker,

wherein the soft charge unit generates the second control signal by comparing the voltage level on the output terminal with
a predetermined voltage level,

wherein when the voltage level on the output terminal is smaller than the predetermined voltage level, only the first amplification
module amplifies the audio signal in response to the first control signal to output the first amplified signal for driving
the loudspeaker,

wherein when the voltage level on the output terminal reaches the predetermined voltage level, only the second amplification
module amplifies the audio signal in response to the second control signal to output the second amplified signal for driving
the loudspeaker;

a first resistor, having a first end and a second end, wherein the first end of the first resistor is coupled to the output
terminal of the first amplifier;

a first switch, having a first terminal and a second terminal, and turned on or off according to the first control signal,
wherein the first terminal of the first switch receives the audio signal, and the second terminal of the first switch is coupled
to the input terminal of the first amplifier and the first end of the first capacitor; and

a second switch, having a first terminal and a second terminal, and turned on or off according to the first control signal,
wherein the first terminal of the second switch is coupled to the second end of the first resistor, and the second terminal
of the second switch is coupled to the output terminal of the first amplifier,

wherein when the voltage level on the output terminal is not equal to the predetermined voltage level, the first switch and
the second switch are turned on according to the first control signal, and when the voltage level on the output terminal is
equal to the predetermined voltage level, the first switch and the second switch are turned off according to the first control
signal.

US Pat. No. 9,106,136

PULSE WIDTH MODULATION LOAD SHARE BUS

MICROCHIP TECHNOLOGY INCO...

1. A power supply system, comprising:
a plurality of power supply modules having respective power outputs coupled in parallel;
each of the plurality of power supply modules having a controller for controlling the power output thereof;
each one of the controllers is coupled to a load share bus (LSB) and comprises a digital load share timer, wherein
each of the controllers monitors logic levels on the LSB,
a one of the controllers asserts a load share signal on the LSB,
when the asserted load share signal on the LSB is detected, remaining ones of the controllers start their respective digital
load share timers and assert their load share signals on the LSB, and

when the load share signal on the LSB is de-asserted the respective digital load share timers stop;
wherein each one of the controllers determines from their respective digital load share timers a maximum percent power value
being supplied by a one of the plurality of power supply modules;

then each one of the controllers compares the maximum percent power value to the percent power value being supplied by a respective
one of the plurality of power supply modules;

when the maximum percent power value is greater than the percent power values supplied by respective ones of the plurality
of power supply modules, then these respective ones of the plurality of power supply modules output powers are increased;
and

when the maximum percent power value is substantially the same as a percent power value supplied by a one of the plurality
of power supply modules, then this respective one of the plurality of power supply modules output power is reduced.

US Pat. No. 9,054,733

QUANTIZATION NOISE COUPLING DELTA SIGMA ADC WITH A DELAY IN THE MAIN DAC FEEDBACK

MICROCHIP TECHNOLOGY INCO...

1. A delta-sigma modulator comprising:
a first summing point subtracting a first feedback signal from an input signal and forwarding a result to a transfer function;
a second summing point adding an output signal from said transfer function to said input signal and subtracting a second feedback
signal;

a first integrator receiving an output signal from said second summing point;
a quantizer receiving an output signal from said integrator and generating an output bitstream;
a digital-to-analog converter receiving said bitstream, wherein the first and second feedback signal are the output signal
from said digital-to-analog converter delayed by a one sample delay,

wherein the delta-sigma modulator operates with a charge phase and a transfer phase and quantization is performed in the transfer
phase.

US Pat. No. 9,455,037

EEPROM MEMORY CELL WITH LOW VOLTAGE READ PATH AND HIGH VOLTAGE ERASE/WRITE PATH

MICROCHIP TECHNOLOGY INCO...

1. An electrically erasable programmable read only memory (EEPROM) cell, comprising:
a substrate including at least one active region;
a floating gate above the substrate;
a write/erase gate arranged above the floating gate and defining a write/erase path for performing write and erase operations
of the cell; and

a read gate arranged above the substrate and laterally adjacent to the floating gate and the write/erase gate, the read gate
defining a read path for performing read operations of the cell, wherein the read path is distinct from the write/erase path,

a floating gate oxide between the floating gate and the substrate; and
a read gate oxide between the read gate and the substrate;
wherein the read gate oxide is thinner than the floating gate oxide.

US Pat. No. 9,131,448

STANDALONE RADIO FREQUENCY WIRELESS DEVICE HAVING DATA ACQUISITION CAPABILITIES

MICROCHIP TECHNOLOGY INCO...

1. A wireless data acquisition device, comprising:
a radio frequency transceiver;
a sensor external connection;
a receive analog-to-digital converter (ADC);
an analog signal multiplexer having a first input coupled to the sensor external connection, a second input coupled to an
analog output of the radio frequency transceiver, and an output coupled to the receive ADC;

a transmit digital-to-analog converter (DAC) coupled to an analog input of the radio frequency transceiver;
baseband signal decoding and encoding logic coupled to an output of the receive ADC and an input of the transmit DAC, respectively;
media access control (MAC) logic coupled to the baseband signal decoding and encoding logic;
a communications interface coupled to the MAC logic and to one of a plurality of external connections;
a state machine coupled to the radio frequency transceiver, baseband signal decoding and encoding logic, the MAC logic, and
a control input of the analog signal multiplexer;

configuration storage coupled to the state machine and to another one of the plurality of external connections;
wherein the state machine uses configuration information stored in the configuration storage to configure operation of the
radio frequency transceiver, baseband signal decoding and encoding logic, analog signal multiplexer and the MAC logic, the
state machine being used in place of a microcontroller;

a timer coupled to the state machine.

US Pat. No. 9,048,863

PULSE DENSITY DIGITAL-TO-ANALOG CONVERTER WITH SLOPE COMPENSATION FUNCTION

MICROCHIP TECHNOLOGY INCO...

1. A pulse density modulated digital-to-analog converter (PDM DAC) with slope compensation function, comprising:
the PDM DAC comprising
a PDM DAC accumulator,
PDM DAC adder having an output coupled to an input of the PDM DAC accumulator and a second input coupled to an output of the
PDM DAC accumulator,

a PDM DAC multiplexer having an output coupled to a first input of the PDM DAC adder, and
a PDM DAC increment value register having an output coupled to a first input of the PDM DAC multiplexer;
a slope generator comprising
a slope generator accumulator having an output coupled to a second input of the PDM DAC multiplexer,
a slope generator multiplexer having an output coupled to an input of the slope generator accumulator and a first input coupled
to the output of the PDM DAC increment value register,

a slope value register,
a slope generator adder having an output coupled to a second input of the slope generator multiplexer, a first input coupled
to an output of the slope value register and a second input coupled to the output of the slope generator accumulator,

a non-positive detect circuit having an input coupled to the output of the slope generator accumulator, and
control logic having an input coupled to an output of the non-positive detect circuit, a first control output coupled to an
enable input of the slope generator accumulator and a second control output coupled to a control input of the slope generator
multiplexer; and

a D-latch having a D-input coupled to a carry-out output of the PDM DAC adder and a clock input coupled to a clock signal;
wherein when a zero or negative output from the slope generator accumulator is detected by the non-positive detect circuit
the control logic forces a zero output from the slope generator accumulator, and when a slope mode control signal is applied
to the PDM DAC multiplexer the first input of the PDM DAC adder is coupled to the output of the slope generator accumulator,
otherwise to the output of the PDM DAC increment value register.

US Pat. No. 9,246,667

METHOD AND APPARATUS FOR CLOCK RECOVERY

MICROCHIP TECHNOLOGY INCO...

1. An integrated circuit device comprising
an internal oscillator for generating a system clock,
a trimming logic comprising a trimming register for adjusting an oscillation frequency of the internal oscillator;
a CAN protocol controller comprising:
a serial data receiver using the system clock or a clock derived from the system clock to sample a received serial data stream,
wherein a received serial CAN data stream includes a synchronization signal, wherein the synchronization signal is operable
to indicate that the system clock is correct, too fast or too slow; and

a circuit for decoding the synchronization signal operable to re-adjust a value stored in the trimming register upon evaluation
of the synchronization signal.

US Pat. No. 9,071,172

SINE MODIFIED TRAPEZOIDAL DRIVE FOR BRUSHLESS DC MOTORS

MICROCHIP TECHNOLOGY INCO...

1. A method for modifying trapezoidal drive to a brushless direct current (BLDC) motor, said method comprising the steps of:
starting a commutation drive period;
dividing the commutation drive period into N time segments;
associating the N time segments into N degree segments, wherein a one of the N degree segments in the middle of the N time
segments is substantially zero (0) degrees;

determining cosine values for each of the N degree segments; and
modifying a duty cycle of a pulse width modulation (PWM) drive to the BLDC motor with the cosine values at appropriate times
during the commutation drive period.

US Pat. No. 9,506,813

DIGITAL TEMPERATURE SENSOR WITH INTEGRATED DIGITAL TEMPERATURE FILTER

MICROCHIP TECHNOLOGY INCO...

1. Integrated temperature sensor device comprising:
a temperature sensor configured to provide an analog signal corresponding to an ambient temperature;
an analog-to-digital converter receiving the analog signal and generating a plurality of subsequent digital temperature values;
a controllable digital filter coupled to the analog-to-digital converter and configured to receive said digital temperature
values, wherein the controllable digital filter is configured to adjust a temperature value rate of change of said plurality
of subsequent digital temperature values;

a first register coupled with the analog-to-digital converter for storing the output of the analog-to-digital converter;
a second register coupled with the digital filter for storing the filtered temperature value; and
a serial interface configured to access said first and second register.

US Pat. No. 9,377,507

PROCESSOR DEVICE WITH INSTRUCTION TRACE CAPABILITIES

MICROCHIP TECHNOLOGY INCO...

1. A processor device having debug capabilities, comprising:
a central processing unit;
debug circuitry including a trace module and an external interface;
wherein the trace module generates a trace stream including information about executed instructions, wherein the trace stream
is output through the external interface;

and wherein the trace module is further operable to detect an asynchronous trigger signal and upon detection to synchronize
the asynchronous trigger signal to a system clock and to generate a trace trigger packet while the asynchronous trigger signal
is synchronized and to insert a trace packet into the generated trace stream,

wherein the asynchronous trigger signal is a trigger signal applied through an external pin of the processor device.

US Pat. No. 9,129,695

SELF-BIASING CURRENT REFERENCE

MICROCHIP TECHNOLOGY INCO...

1. A method for determining a charge state of a memory cell having a floating gate, said method comprising the steps of:
sensing a first current in a hit-line when all memory cells coupled to the bit-line are de-asserted;
converting the first current to a voltage;
storing the voltage;
providing a reference current based upon the stored voltage;
comparing the reference current with a second current in the bit-lime when a single memory cell. connected to the bit-fine
is asserted during a read operation thereof; and

determining a bit value charge state stored in the single memory cell from the comparison of the reference current with the
second current.

US Pat. No. 9,429,980

FLEXIBLE CLOCKING FOR AUDIO SAMPLE RATE CONVERTER IN A USB SYSTEM

MICROCHIP TECHNOLOGY INCO...

1. A microcontroller comprising:
an on-chip sample rate converter, wherein the sample rate converter receives a source audio signal that is sampled at a first
sampling rate, and wherein the sample rate converter generates an output audio signal sampled at a second sampling rate, and
wherein the sample rate converter utilizes a master clock signal in converting the sample rate of the audio signal, and

a master clock circuit configured to generate the master clock signal wherein the master clock circuit selects from an on-chip
system clock signal or a bus interface clock signal and scales the frequency of the selected clock signal to generate the
master clock signal with the frequency of the second sampling rate.

US Pat. No. 9,385,313

RESISTIVE MEMORY CELL HAVING A REDUCED CONDUCTIVE PATH AREA

MICROCHIP TECHNOLOGY INCO...

1. A method of forming a resistive memory cell, comprising:
forming a bottom electrode layer on a substrate; oxidizing an exposed region of the bottom electrode layer to form an oxide
region, wherein a vertical cross section of the oxide region comprises a non-orthogonal shape;

removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode wherein the
non-orthogonal shape of the oxide region creates a pointed tip region at a peripheral edge of the bottom electrode;

forming:
(a) a first electrolyte region and first top electrode over a first portion of the pointed tip region of the bottom electrode,
such that the first electrolyte region is arranged between the first top electrode and the first portion of the pointed tip
region of the bottom electrode to define a first memory element; and

(b) a second electrolyte region and second top electrode over a second portion of the pointed tip region of the bottom electrode,
such that the second electrolyte region is arranged between the second top electrode and the second portion of the pointed
tip region of the bottom electrode to define a second memory element.

US Pat. No. 9,224,659

METHOD AND APPARATUS FOR SEMICONDUCTOR TESTING AT LOW TEMPERATURE

MICROCHIP TECHNOLOGY INCO...

1. An apparatus for testing semiconductor devices at low temperature, comprising:
a test chuck;
an adhesive tape arranged on the test chuck; and
an isolated test strip arranged on the adhesive tape, the isolated test strip comprising an array of semiconductor devices
on a frame and being partially cut to electrically isolate adjacent semiconductor devices in the array;

wherein the adhesive tape is configured to resist warping of the isolated test strip away from the test chuck at temperatures
extending below ?20° C.

US Pat. No. 9,602,895

INTEGRATED CIRCUIT DEVICE WITH TAMPER DETECTION INPUT AND HAVING REAL TIME CLOCK CALENDAR LOGGING THEREOF

MICROCHIP TECHNOLOGY INCO...

1. An integrated circuit device, comprising:
a real time clock and calendar (RTCC) circuit configured to be coupled with an external power source;
a time stamp capture register coupled with the RTCC; and
an external input coupled with the time stamp capture register for receiving an event signal that initiates capture of time
and date information provided by the RTCC into the time stamp capture register; wherein:

the time stamp capture register is a plurality of time stamp capture registers; and
the device further comprises a plurality of false trigger filters, wherein each of the plurality of false trigger filters
is coupled to a respective one of the plurality of time stamp capture registers.

US Pat. No. 9,520,042

SMOKE DETECTOR WITH ENHANCED AUDIO AND COMMUNICATIONS CAPABILITIES

MICROCHIP TECHNOLOGY INCO...

1. An apparatus for detecting smoke and having audio and communications capabilities, comprising:
a logic device;
a smoke sensor coupled to the logic device;
a local area network (LAN) communications interface coupled to the logic device, wherein the LAN communications interface
is coupled to an Ethernet local area wired communications bus and/or wherein the LAN communications interface comprises a
wireless interface coupled to a radio frequency antenna;

an audio amplifier coupled to the logic device;
a speaker coupled to the audio amplifier; and
a power supply coupled to and powering the logic device, communications interface and audio amplifier;
wherein the apparatus is configured to be installed in a dwelling;
wherein when the smoke sensor detects smoke the logic device generates at least one smoke alarm tone through the audio amplifier
and to the speaker, and a smoke alarm signal through the communications interface;

wherein audio content is provided through the LAN communications interface, the logic device, the audio amplifier and to the
speaker when there is not a current smoke alarm.

US Pat. No. 9,349,950

RESISTIVE MEMORY CELL WITH TRENCH-SHAPED BOTTOM ELECTRODE

MICROCHIP TECHNOLOGY INCO...

1. A resistive memory cell, comprising:
a top electrode;
a bottom electrode structure extending in a first direction and having a trench shape and defining a pair of spaced apart
bottom electrode sidewalls; and

an electrolyte switching region arranged between the top electrode and the bottom electrode sidewall comprising a trench-shaped
region extending perpendicular to the first direction and defining four discrete areas of contact between the electrolyte
switching region and the bottom electrode structure to provide a path for the formation of a conductive filament or vacancy
chain from the bottom electrode sidewall to the top electrode when a voltage bias is applied to the resistive memory cell.

US Pat. No. 9,569,025

LCD CONTROLLER WITH CAPACITIVE TOUCH INTERFACE

MICROCHIP TECHNOLOGY INCO...

1. An integrated circuit device comprising:
a touch controller comprising at least one input,
a liquid crystal display (LCD) controller comprising a plurality of outputs, wherein the LCD controller is configured to drive
a segmented LCD comprising a plurality of segment electrodes and common electrodes wherein each segment electrode and each
common electrode is individually accessible for connection, wherein the segment electrodes are arranged in groups spaced apart
from each other and wherein at least one group forms a seven-segment display,

a plurality of external connections wherein each segment electrode and each common electrode is coupled with one of said plurality
of external connections, and

a multiplexer operable in a first mode to connect said plurality of external connections with said plurality of outputs of
the LCD controller and in a second mode to connect at least one of said plurality of external connections connected to a common
electrode with said touch controller, wherein the common electrode is used as a touch sensor electrode.

US Pat. No. 9,362,496

RESISTIVE MEMORY CELL WITH TRENCH-SHAPED BOTTOM ELECTRODE

MICROCHIP TECHNOLOGY INCO...

1. A resistive memory cell, comprising:
a top electrode;
a bottom electrode structure having a trench shape and defining a bottom electrode connection and a bottom electrode sidewall
extending from the bottom electrode connection and defining an interior trench area;

wherein the bottom electrode sidewall extends from a top surface of the bottom electrode connection to a tip region defining
a tip surface facing generally away from the bottom electrode connection;

wherein the bottom electrode sidewall adjacent the bottom electrode connection has a first sidewall region thickness in a
first direction, and the tip surface facing away from the bottom electrode connection has a tip thickness in the first direction
that is less than the first sidewall region thickness; and

an electrolyte layer defining an electrolyte switching region arranged between the top electrode and the tip region of the
bottom electrode sidewall and at least a portion of the electrolyte layer extends into the interior trench area, wherein the
electrolyte layer provides a path for the formation of a conductive filament or vacancy chain from the tip surface of the
bottom electrode sidewall to the top electrode, via the electrolyte switching region, when a voltage bias is applied to the
resistive memory cell, wherein an insulating layer is arranged between the electrolyte layer and a surface of the bottom electrode
sidewall facing the interior trench area.

US Pat. No. 9,195,497

MICROCONTROLLER WITH CONTEXT SWITCH

MICROCHIP TECHNOLOGY INCO...

1. A microprocessor or microcontroller device comprising:
a central processing unit (CPU);
a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks, wherein a bank select
register determines which memory bank is currently coupled with the CPU; and

a first set of special function registers and a second set of special function registers, wherein upon occurrence of a context
switch either the first or the second set of special function register are selected as active context registers for the CPU
and the respective other set of special function registers are selected as inactive context registers, wherein at least some
of the registers of the active context registers are memory mapped to more than two memory banks of said data memory and wherein
all registers of the inactive context registers are memory mapped to at least one memory location within the data memory.

US Pat. No. 9,129,680

SELF-BIASING MULTI-REFERENCE

MICROCHIP TECHNOLOGY INCO...

1. A method for determining a charge state of a memory cell having a floating gate, said method comprising the steps of:
sensing a first current in a bit-line when all memory cells coupled to the bit-line are de-asserted;
converting the first current to a voltage;
storing the voltage;
providing a reference current based upon the stored voltage;
providing a voltage reference used as an input for a sense amplifier from the stored voltage;
comparing the reference current to a second current in the bit-line with the sense amplifier when a single memory cell connected
to the bit-line is asserted during a read operation thereof; and

determining from the sense amplifier output a bit value charge state stored in the single memory cell from the comparison
of the reference current with the second current.

US Pat. No. 9,385,043

SPACER ENABLED POLY GATE

MICROCHIP TECHNOLOGY INCO...

1. A method for forming insulated polysilicon gates on a semiconductor integrated circuit die, said method comprising the
steps of:
forming an array of ring-shaped insulated polysilicon gates by:
depositing a first dielectric on a face of a semiconductor substrate;
creating a plurality of trenches in the first dielectric down to a face of the semiconductor substrate;
depositing a spacer film on the first dielectric including walls and a bottom of the each of the trenches;
removing portions of the spacer film from a face of the first dielectric and the bottom of the each of the trenches exposing
the face of the semiconductor substrate, wherein only spacer films remain on the walls of the trenches;

depositing a second dielectric over the first dielectric and between the spacer films on the walls of the trenches sufficient
to fill a spaced defined therebetween;

removing a portion of the first and second dielectrics until substantially flat top portions of the spacer films are exposed
between the first and second dielectrics;

removing the spacer films between the first and second dielectrics to the exposed face of the semiconductor substrate, thereby
leaving an array of ring-shaped spacer-film-width channels therein, each spacer-film-width channel having a lateral width
equal to a thickness of the removed spacer film;

growing gate oxides on exposed faces of the semiconductor substrate at the bottoms of the array of ring-shaped spacer-film-width
channels;

depositing polysilicon on upper faces of the first and second dielectrics and into the array of ring-shaped spacer-film-width
channels such that each spacer-film-width channel is fully filled with polysilicon up to and above a full height of the channel;

removing portions of the polysilicon on the upper faces of the first and second dielectrics and top portions of the polysilicon
in the array of fully filled ring-shaped spacer-film-width channels, such that the removal of polysilicon reduces each spacer-film-width
channel from being fully filled to being only partially filled, with top faces of the remaining polysilicon in each spacer-film-width
channel being located below the upper faces of the first and second dielectrics; and

removing the first and second dielectrics from the face of the semiconductor substrate leaving thereon an array of ring-shaped
polysilicon gates, each insulated by a respective gate oxide; and

etching an area extending across the array of ring-shaped polysilicon gates to separate the array of ring-shaped polysilicon
gates into an array of independent line-shaped polysilicon gates for an array of insulated gate transistors.

US Pat. No. 9,590,649

ANALOG-TO-DIGITAL CONVERSION WITH MICRO-CODED SEQUENCER

MICROCHIP TECHNOLOGY INCO...

1. An apparatus for analog-to-digital conversion using a micro-coded sequencer, comprising:
means for analog-to-digital conversion;
a micro-coded sequencer coupled to and configured to control the analog-to-digital conversion means;
an address decoder coupled to the memory and operable to select a micro-coded word for the micro-coded sequencer; and
a memory coupled to the micro-coded sequencer, wherein the memory is configured to store micro-coded words for instructing
the micro-coded sequencer how to control the analog-to-digital conversion means.

US Pat. No. 9,509,321

MAIN CLOCK HIGH PRECISION OSCILLATOR

MICROCHIP TECHNOLOGY INCO...

1. A clock oscillator comprising:
a high speed oscillator generating a high speed clock signal and comprising a digital to analog converter providing a trimming
function;

a counter receiving said high speed clock signal at a clock input;
a time base having a very low drift and controlling said counter, wherein the counter generates a difference value between
a reference value and a counter value; and

a digital integrator having an m-bit input and receiving said difference value being an integer and comprising n-bits, wherein
n Bits (MSB) of the n-bit integer difference value are shifted at the m-bit input of the digital integrator in order to reduce
a tuning time while remaining bits of the n-bit integer difference value remain un-shifted.

US Pat. No. 9,437,093

DIFFERENTIAL CURRENT MEASUREMENTS TO DETERMINE ION CURRENT IN THE PRESENCE OF LEAKAGE CURRENT

MICROCHIP TECHNOLOGY INCO...

1. A method for determining ion current in an ion chamber, said method comprising the steps of:
coupling first and second electrodes of an ion chamber to a voltage at a first polarity;
determining a first current between the first and the second electrodes of the ion chamber caused by the voltage at the first
polarity;

coupling the first and the second electrodes of the ion chamber to the voltage at a second polarity;
determining a second current between the first and the second electrodes of the ion chamber caused by the voltage at the second
polarity; and

determining a difference between the first and second currents, wherein the difference is the ion current through the ion
chamber.

US Pat. No. 9,430,107

DETERMINING TOUCH LOCATIONS AND FORCES THERETO ON A TOUCH AND FORCE SENSING SURFACE

MICROCHIP TECHNOLOGY INCO...

1. A method for decoding multiple touches and forces thereof on a touch sensing surface, said method comprising the steps
of:
scanning a plurality of channels aligned on an axis for determining self-capacitance values of each of the plurality of channels;
comparing the self-capacitance values to determine which one of the channels has a local maximum self-capacitance value, wherein
left and right slope values are determined for the at least one self-value, wherein:

the left slope value is equal to the at least one self-value minus a self-value of a channel to the left of the at least one
channel, and

the right slope value is equal to the at least one self-value minus a self-value of a channel to the right of the at least
one channel:

wherein when the left slope value is greater than zero (0) and the right slope value is less than zero (0), then determine
a local maximum self-capacitance value and return to the step of scanning the plurality of nodes of the at least one channel,
and when no then continue to next step:

wherein when a ratio between a positive left slope value and a positive right slope value is greater than a predefined threshold,
then determine a local maximum self-capacitance value and return to the step of scanning the plurality of nodes of the at
least one channel, and when not then continue to the next step;

wherein when a ratio between a negative left slope value and a negative right slope value is less than a predefined threshold,
then determine a local maximum self-capacitance value and return to the step of scanning the plurality of nodes of the at
least one channel, and when not then continue to the next step;

wherein when there is another self-value, then return to the step of determining left and right slope values;
scanning a plurality of nodes of at least one channel having local maximum self-capacitance value for determining mutual values
of the nodes;

comparing the mutual values to determine which one of the nodes has the largest mutual capacitance value, wherein the node
having the largest mutual capacitance value on the local maximum self-capacitance value channel is a potential touch location;
and

determining a force at the potential touch location from a change in the mutual capacitance values of the node at the potential
touch location during no touch and during a touch thereto.

US Pat. No. 9,367,179

CAPACITIVE VOLTAGE DIVIDER TOUCH SENSOR

MICROCHIP TECHNOLOGY INCO...

1. A system for measuring capacitance, comprising:
a microcontroller comprising a measurement circuit and a plurality of external pins;
a reference capacitor coupled to a first pin and to a second pin of the microcontroller;
the first pin connected to a first switching unit of the microcontroller configured to apply or remove a reference voltage
or ground to said first pin;

the second pin connected to a second switching unit of the microcontroller configured to apply or remove a reference voltage
or ground to said second pin;

a pad connected to the first pin wherein the second pin is connected to the reference capacitor; and
an analog to digital converter in said microcontroller operable to measure a voltage between the first pin and second pin,
wherein the microcontroller is configured to control the first and second switching units to apply in a first state the reference
voltage simultaneously to said first and said second pin from which state the reference voltage is removed from the first
pin, and the second pin is switched from the reference voltage to ground and after a predetermined settling time, said analog
to digital converter is controlled to measure a first voltage between the first pin and the second pin, and thereafter to
control the first and second switching units to apply in a second state the reference voltage simultaneously to said first
and said second pin from which state said reference voltage is removed from said second pin and first pin is switched from
the reference voltage to ground and after a predetermined settling time, said analog to digital converter is controlled to
measure a second voltage between the first pin and the second pin.

US Pat. No. 9,379,621

DIGITAL SLOPE COMPENSATION FOR PEAK CURRENT CONTROLLED CONVERTERS

MICROCHIP TECHNOLOGY INCO...

1. A method for providing slope compensation in a switched-mode power supply (SMPS) controller, said method comprising the
steps of:
turning on a pulse width modulation (PWM) control signal at a beginning of a PWM cycle;
sampling an input voltage (vin) to a SMPS;

converting the sampled input voltage (vin) to a digital representation thereof (VIN_D);

sampling an output voltage (vo) from the SMPS;

converting the sampled output voltage (vo) to a digital representation thereof (VOUT_D);

sampling an inductor current (IL) of the SMPS when the PWM control signal turns on at the beginning of the PWM cycle, wherein the inductor current (IL) is at a minimum inductor current value (IV);

converting the sampled minimum inductor current value (IV) to a digital representation thereof (IV_D);

determining a digital slope compensated peak current reference (ICMP_D) with a digital processor according to the steps of:

determining A, where A is a function of the digital representations of the sampled output voltage (VOUT_D) and the sampled input voltage (VIN_D),

for a buck converter topology

for a boost converter topology

for a buck-boost converter topology

wherein ? is within a range of 0.5 determining B, where B is a function of the digital representations of the sampled output voltage (VOUT_D) and the sampled input voltage (VIN_D),

for the buck converter topology

for the boost converter topology

for the buck-boost converter topology

wherein ? is within the range of 0.5 multiplying A of any of the buck converter topology, the boost converter topology and the buck-boost converter topology with
the digital minimum inductor current (IV_D),

multiplying B of any of the buck converter topology, the boost converter topology and the buck-boost converter topology with
a digital control reference current (IC_D), and

adding results of the multiplying A and the multiplying B to determine the digital slope compensated peak current reference
(ICMP_D=A*IV_D+B*IC_D);

converting the digital slope compensated peak current reference (ICMP_D) to an analog slope compensated peak current reference (ICMP) with a digital-to-analog converter (DAC);

comparing the analog slope compensated peak current reference (ICMP) to the inductor current (IL) with an analog comparator;

turning off the PWM control signal with an output from the analog comparator when the inductor current (IL) is substantially equal to the analog slope compensated peak current reference (ICMP); and

returning to the step of turning on the PWM control signal at the beginning of a next PWM cycle.

US Pat. No. 9,671,920

COMPENSATION OF A TARGET OBJECT COUPLING TO FEEDING LINES IN CAPACITIVE SENSING SYSTEM

MICROCHIP TECHNOLOGY INCO...

1. An input device comprising one or more electrodes configured for capacitive sensing, an electronic circuit, one or more
conductive feed line connecting said electrodes with said electronic circuit, further comprising one or more additional feed
lines connected to the electronic circuit which are not connected with any electrodes, wherein at least one other signal is
generated by the one or more additional feed lines wherein the one or more additional feed lines each operate as an electrode
and wherein the at least one other signal is used to correct a sensor signal;
wherein an electrode is split into multiple segments and a feed line is routed between at least two electrode segments, wherein
the electrode segments are galvanically connected through a connection line.

US Pat. No. 9,159,218

INITIATION OF CARBON MONOXIDE AND/OR SMOKE DETECTOR ALARM TEST USING IMAGE RECOGNITION AND/OR FACIAL GESTURING

MICROCHIP TECHNOLOGY INCO...

1. An apparatus for detecting smoke and having pattern recognition capabilities, comprising:
a logic device;
a smoke sensor coupled to the logic device;
an image sensor coupled to the logic device and configured to detect a pattern on a substrate;
a communications interface coupled to the logic device;
an audible alarm generator coupled to the logic device; and
a power supply coupled to and powering the logic device, communications interface and the audible alarm generator;
wherein when the smoke sensor detects smoke the logic device generates at least one smoke alarm tone through the audible alarm
generator, and a smoke alarm signal through the communications interface; and

wherein the logic device is configured to initiate a smoke alarm testing in response to detection of the pattern by the image
sensor.

US Pat. No. 9,288,697

WIRELESS COMMUNICATION CIRCUIT WITH A WIDEBAND RECEIVED SIGNAL STRENGTH INDICATOR

MICROCHIP TECHNOLOGY INCO...

1. A wireless communication circuit with a wideband received signal strength indicator, comprising:
a front end signal processing unit, electrically connected to an antenna, configured to receive and process a wireless signal
from the antenna and to output a low frequency analog signal;

a filter unit, electrically connected to the front end signal processing unit, and configured to receive the low frequency
analog signal from the front end signal processing unit and to output a determined band signal;

a first analog-to-digital converter module, electrically connected to the filter unit, and configured to receive and transform
the determined band signal from the filter unit into a first digital signal;

a first demodulator, electrically connected to the first analog-to-digital converter module and the front end signal processing
unit, and configured to receive and demodulate the first digital signal from the first analog-to-digital converter module
and to output a first control signal;

a second analog-to-digital converter module, selectively electrically connected to the front end signal processing unit or
the filter unit, and configured to receive the low frequency analog signal from the front end signal processing unit or the
determined band signal from the filter unit, and to transform the low frequency analog signal from the front end signal processing
unit or the determined band signal from the filter unit into a second digital signal;

a second demodulator, electrically connected to the second analog-to-digital converter module, the first demodulator and the
front end signal processing unit, and configured to receive and demodulate the second digital signal from the second analog-to-digital
converter module and to output a second control signal;

a first switch, electrically connected between the front end signal processing unit and the second analog-to-digital converter
module;

a second switch, electrically connected between the filter unit and the second analog-to-digital converter module;
a third switch, electrically connected between the second demodulator and the front end signal processing unit;
a fourth switch, electrically connected between the first demodulator and the front end signal processing unit; and
a controller, electrically connected to the first switch, the second switch, the third switch and the fourth switch, and configured
to control a switching configuration of the first switch, the second switch, the third switch and the fourth switch to determine
a circuit operation of the wireless communication circuit.

US Pat. No. 9,907,129

MULTIPLE LED STRING DIMMING CONTROL

MICROCHIP TECHNOLOGY INCO...

1. An integrated circuit device configured to drive multiple LED strings, the device comprising:
a switch mode power supply (SMPS) control circuit configured to generate primary and secondary power transistor control signals
and receive at least one current sense signal and an output voltage sense signal;

an output compare circuit configured to generate a plurality of pulse width modulated signals; and
a logic circuit configured to generate signals for selecting a reference voltage and for activating an absorber mode;
wherein:
the signal for activating an absorber mode is configured to be shared with the secondary power transistor control signal;
and

the logic circuit is configured to be synchronized with the output compare circuit.

US Pat. No. 9,812,380

BUMPS BONDS FORMED AS METAL LINE INTERCONNECTS IN A SEMICONDUCTOR DEVICE

MICROCHIP TECHNOLOGY INCO...

1. An apparatus, comprising:
an array of conductive contact elements;
a passivation layer formed over the plurality of conductive contact elements, the passivation layer comprising passivation
openings over a plurality of the conductive contact elements;

an array of conductive bumps including one or more interconnection bumps, wherein each interconnection bump is formed over
the passivation layer and extends into at least two of the passivation openings and into contact with at least two underlying
conductive contact elements to thereby provide a conductive coupling between the at least two underlying conductive contact
elements;

a frontside drain connection;
a frontside source connection within a same cell of source metal as the frontside drain connection; and
only a single metal interconnect layer, which includes the array of conductive contact elements;
wherein the frontside source connection and the frontside drain connection are covered by a same conductive bump.

US Pat. No. 9,627,246

METHOD OF FORMING SHALLOW TRENCH ISOLATION (STI) STRUCTURES

MICROCHIP TECHNOLOGY INCO...

1. A method of forming a trench isolation structure for an integrated circuit, the method comprising:
forming a nitride layer over a semiconductor substrate;
performing a trench etch process through portions of the nitride layer and the semiconductor substrate to form a trench;
depositing a trench oxide layer over remaining portions of the nitride layer and extending into the trench to form a filled
trench;

depositing a sacrificial planarizing layer over the trench oxide layer, the sacrificial planarizing layer being etch-selective
with respect to the trench oxide layer;

performing a multi-step etch process that including:
a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface
of the trench oxide layer;

wherein the planarizing etch process includes at least one selective etch that is either selective to the sacrificial planarizing
layer with respect to the trench oxide layer or selective to the trench oxide layer with respect to the sacrificial planarizing
layer; and

removing the remaining portions of the nitride layer such that the remaining oxide of the filled trench defines a trench isolation
structure that projects above an exposed upper surface of the semiconductor substrate.

US Pat. No. 9,473,205

COAXIAL DATA COMMUNICATION WITH REDUCED EMI

MICROCHIP TECHNOLOGY INCO...

1. A transmission circuit using a coaxial cable having a center conductor and a shield, comprising:
an integrated circuit comprising a differential driver having first and second outputs;
a common mode choke coupled between the first output of the differential driver and the center conductor of the coaxial cable,
and between a first ground node and the shield of the coaxial cable;

a terminating impedance coupled between the second output of the differential driver and the first ground node; and
a dissipative resistor coupled between the shield of the coaxial cable and a second ground node wherein the dissipative resistor
is from 3 ohms to 100 ohms.

US Pat. No. 9,471,074

USB REGULATOR WITH CURRENT BUFFER TO REDUCE COMPENSATION CAPACITOR SIZE AND PROVIDE FOR WIDE RANGE OF ESR VALUES OF EXTERNAL CAPACITOR

MICROCHIP TECHNOLOGY INCO...

1. A voltage regulator, comprising:
an operational amplifier;
a gm enhanced current buffer driver;
a biasing circuit coupled to the current buffer driver to set a biasing ratio for gm-boost of the current buffer driver;
an enable/disable function to enable/disable the biasing circuit for reducing standby current:
an output power driver, wherein the current buffer driver is coupled between the operational amplifier and the output power
driver;

a current feedback circuit coupled between the output power driver and the current buffer driver; and
a feedback loop coupled between the output power driver and the operational amplifier.

US Pat. No. 9,318,702

RESISTIVE MEMORY CELL HAVING A REDUCED CONDUCTIVE PATH AREA

MICROCHIP TECHNOLOGY INCO...

1. A method of forming a resistive memory cell, comprising:
forming a bottom electrode layer on a substrate;
oxidizing an exposed region of the bottom electrode layer to form an oxide region extending laterally from a first lateral
side to a second lateral side;

removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed
tip region adjacent the first lateral side of the oxide region and having a shape defined in part by a shape of the first
lateral side of the oxide region;

forming an electrolyte region and a top electrode over at least a portion of the bottom electrode and the oxide region that
was formed prior to forming the pointed tip region of the bottom electrode, such that the electrolyte region is arranged between
the top electrode and the pointed tip region of the bottom electrode.

US Pat. No. 9,141,572

DIRECT MEMORY ACCESS CONTROLLER

MICROCHIP TECHNOLOGY INCO...

1. A microcontroller comprising a single chip with:
at least one bus;
a central processing unit (CPU) coupled with said bus, wherein said CPU has direct access to said bus;
a memory coupled with said bus;
a plurality of peripherals coupled with said bus;
a direct memory access (DMA) controller having DMA channels, said DMA controller operating independently from said CPU and
being coupled with said bus, wherein said DMA controller has direct access to said bus and wherein each DMA channel comprises
an associated channel control register and wherein the DMA controller further comprises a general control register; wherein
for access to said bus said DMA controller is programmable by setting or resetting a control bit in said general control register
to operate in a first mode to have priority over said CPU and said plurality of peripherals and in a second mode to immediately
suspend data transfer on all DMA channels and grant the CPU direct access to said bus.

US Pat. No. 9,144,051

PROXIMITY DETECTION USING AN ANTENNA AND DIRECTIONAL COUPLER SWITCH

MICROCHIP TECHNOLOGY INCO...

1. A directional coupler for coupling an antenna with a radio frequency (RF) system, comprising:
a first connection configured to couple an antenna coupled with the first connection with a directional coupler switch arranged
within the directional coupler;

a second connection configured to couple an RF system coupled with the second connection with the first connection through
the directional coupler switch; and

a third connection configured to couple the first connection with a capacitance measurement device coupled with the third
connection through the directional coupler switch, wherein the capacitance measurement device measures capacitance values
of the antenna, wherein the directional coupler switch is controlled to couple the first connection with either the second
connection or the third connection.

US Pat. No. 9,805,572

DIFFERENTIAL CURRENT MEASUREMENTS TO DETERMINE ION CURRENT IN THE PRESENCE OF LEAKAGE CURRENT

MICROCHIP TECHNOLOGY INCO...

1. An apparatus for detecting smoke, comprising:
an ionization chamber having a radiation source and comprising first and second electrodes, wherein the ionization chamber
is open to smoke ingress;

a pulse generator coupled to the first electrode of the ionization chamber, wherein the pulse generator output comprises voltage
transitions from substantially zero volts to substantially a voltage;

a capacitor coupled to the second electrode of the ionization chamber; a precharge voltage reference;
a precharge switch coupled between the precharge voltage reference and the capacitor, wherein the precharge switch initially
couples the precharge voltage reference to the capacitor for charging the capacitor to a first voltage;

a voltage determination circuit coupled to the capacitor; and
a pulse counter coupled to the pulse generator and counting a number of pulses therefrom, wherein the pulse counter counts
the number of pulses from the pulse generator required to charge the capacitor to a second voltage.

US Pat. No. 9,607,978

ESD-PROTECTION CIRCUIT FOR INTEGRATED CIRCUIT DEVICE

MICROCHIP TECHNOLOGY INCO...

1. An integrated circuit device comprising:
a supply voltage connection;
an open drain output connection; and
an open drain output driver cell having electro-static discharge protection, comprising:
an N? well;
a first P? body diffused in the N? well, wherein the first P? body comprises a first P+ diffusion and a first N+ diffusion;
a second P? body diffused in the N? well, wherein the second P? body comprises a second P+ diffusion and a second N+ diffusion;
a first gate and a first insulating oxide over a portion of the first P-body and a portion of the N? well, wherein the first
gate provides for control of the output driver cell;

a second gate and a second insulating oxide over a portion of the second P-body and a portion of the N-well;
a source and body contact coupled with the supply voltage connection and comprising the first P+ diffusion and the first N+
diffusion connected together; and

wherein the second P+ diffusion, the second N+ diffusion and the second gate are connected together and connected with the
open drain output connection;

wherein an electro-static discharge (ESD) and reverse voltage protection diode is formed between the first and second P? bodies.

US Pat. No. 9,542,051

ANALOG ELIMINATION OF UNGROUNDED CONDUCTIVE OBJECTS IN CAPACITIVE SENSING

MICROCHIP TECHNOLOGY INCO...

1. A method for performing a touch determination with a capacitive sensor, comprising:
performing a calibration method, wherein the calibration method is performed before performing the touch determination, the
calibration method comprising:

performing an individual self capacitance measurement and storing a first measurement value;
performing an individual mutual capacitance measurement and storing a second measurement value; and
calculating a scale factor from said first and second measurement values;
initiating a self capacitance measurement of a capacitive sensor, wherein at the same time a mutual capacitance measurement
including the capacitive sensor is performed; and

applying said scale factor to said self capacitance or said mutual capacitance measurement.

US Pat. No. 9,525,372

METHOD AND SYSTEM FOR DETERMINING THE POSITION OF A SYNCHRONOUS MOTOR'S ROTOR

MICROCHIP TECHNOLOGY INCO...

1. A method for determining a rotor position in a synchronous three phase motor, said method comprising the steps of:
coupling combinations of two of three stator windings to a first voltage; coupling third one of the three stator windings
to a second voltage;

measuring first times for currents through all combinations of the three stator windings to equal a reference current; and
determining a rotor position from the measured first times, wherein the rotor position is within an electrical sector associated
with a phase time measurement pair having the largest absolute value of a difference there between.

US Pat. No. 9,473,161

MIXED SIGNAL AUTOMATIC GAIN CONTROL FOR INCREASED RESOLUTION

MICROCHIP TECHNOLOGY INCO...

1. An apparatus for analog-to-digital conversion at high resolution, comprising:
a selectable gain amplifier having an input for an analog signal;
an analog-to-digital converter (ADC) coupled to the selectable gain amplifier and adapted to receive an analog output therefrom
and convert samples of the analog output into digital representations thereof;

a controller coupled to the ADC and the selectable gain amplifier, wherein
the controller selects gains of the amplifier based upon the digital representations, and
shifts bit positions of the digital representations based upon the selected gains, wherein:
the selectable gain amplifier has a plurality of selectable gains;
the plurality of selectable gains comprise gains of one (1), two (2), four (4) and eight (8); and
wherein the digital representation is shifted three bits toward the most significant bit when the gain selected is one (1),
shifted two bits toward the most significant bit when the gain selected is two (2), shifted one bit toward the most significant
bit when the gain selected is four (4), and not shifted when the gain selected is eight (8).

US Pat. No. 9,444,040

SIDEWALL TYPE MEMORY CELL

MICROCHIP TECHNOLOGY INCO...

1. A cell for a resistive memory, comprising:
a bottom electrode;
a top electrode layer defining a sidewall; and
an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between
the bottom electrode and the top electrode sidewall via the electrolyte layer; and

wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode
sidewall extends non-horizontally with respect to the horizontal substrate, wherein the top electrode sidewall defines a ring
shape extending around an outer perimeter of the bottom electrode.

US Pat. No. 9,201,446

TIMEBASE PERIPHERAL

MICROCHIP TECHNOLOGY INCO...

1. A microcontroller comprising a programmable timebase, wherein the timebase comprises a trigger input to start a timer or
counter of the timebase and wherein the timebase can be configured to operate in a first mode to generate a plurality of timer/counter
event signals until a reset bit in a control register is set and in a second mode to generate a single timer/counter event
signal and in a third mode to generate a predefined number of timer/counter event signals, wherein the predefined number is
defined by a plurality of bits of a register and wherein the first mode is set by setting a first mode bit and the second
mode or the third mode are set by setting a second mode plurality of bits, wherein the control register is a first control
register and the plurality of bits are bits of a second control register associated with the timebase.

US Pat. No. 9,153,568

CHIP, ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND FABRICATION THEREOF

MICROCHIP TECHNOLOGY INCO...

1. An electrostatic discharge protection device, comprising:
an N well;
a P type doping region, disposed in the N well;
a first N type doping region, disposed in the P type doping region;
a plurality of N type sub-doping regions, disposed in the P type doping region in parallel, wherein the N type sub-doping
regions do not contact to the first N type doping region, and the N type sub-doping regions are electrically connected to
a first source rail-line;

a first N+ type doping region, disposed in the first N type doping region;
a first P+ type doping region, disposed in the first N doping region, wherein the first N+ doping region and the first P+
doping region are electrically connected to a pad;

a second N+ doping region, disposed in the P type doping region, wherein second P+ type doping region and the second N+ doping
region are electrically connected to a second source rail-line;

wherein the N type sub-doping regions are disposed between the first N type doping region and the second N+ doping region;
wherein when the first source rail-line is electrically connected to a system voltage and the second source rail-line is electrically
connected to a ground voltage, there is a depletion region generated between the N type sub-doping region and the P type doping
region so as to block a channel current between the first N+ type doping region and the second N+ type doping region.

US Pat. No. 9,953,886

SINGLE-WAFER REAL-TIME ETCH RATE AND UNIFORMITY PREDICTOR FOR PLASMA ETCH PROCESSES

MICROCHIP TECHNOLOGY INCO...

1. A method for testing a semiconductor plasma etch chamber, the method comprising:depositing a film on a substrate of a wafer, the wafer including a center region and an edge region;
depositing photoresist on top of the film in a pattern that isolates the center region from the edge region of the wafer;
performing an etch process on the wafer that includes at least three process steps, the at least three process steps including:
etching the film in any areas without photoresist covering the areas until a first clear endpoint signal is achieved;
after the first clear endpoint signal is achieved, performing an in-situ ash to remove any photoresist; and
after performing an in-situ ash, etching the film in any areas exposed by the removal of the photoresist until a second clear endpoint is achieved;
determining whether both endpoints are achieved within respective previously set tolerances; and
if both endpoints are achieved within the previously set tolerance, qualifying the plasma etch chamber as verified.

US Pat. No. 9,866,200

MULTIPLE COIL SPRING MEMS RESONATOR

Microchip Technology Inco...

1. A MEMS (microelectromechanical systems) resonator comprising:
a center anchor connected to a substrate;
a resonator body comprising one or more pairs of coil springs and an outer closed ring suspended above the substrate, the
coil springs extending in a spiral pattern from the center anchor to the outer closed ring, the center anchor is at a nodal
point of the resonator body;

one or more transducers formed on the outer closed ring, each transducer being formed perpendicular to and extending outward
from the outer closed ring;

a set of drive electrodes and a set of sense electrodes formed attached to the substrate, each transducer being capacitively
coupled to one drive electrode and one sense electrode, a pair of the drive and sense electrodes being coupled to drive a
respective transducer using electrostatic parallel plate drive, the drive and sense electrodes and the respective transducer
being capacitivly coupled in a parallel plate configuration and each of the drive and sense electrodes being separated from
the respective transducer by a narrow gap in the parallel plate configuration.

US Pat. No. 9,858,083

DUAL BOOT PANEL SWAP MECHANISM

MICROCHIP TECHNOLOGY INCO...

1. A central processing unit with dual boot capabilities, comprising:
an instruction memory comprising a first and second memory area which are configured to be individually programmable, wherein
first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory,
respectively;

wherein the instruction set for the central processing unit comprises a opcode, the sole purpose of the opcode to cause a
swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the opcode in the
active memory immediately followed by a program flow change instruction in the active memory, whereupon the inactive memory
becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues
in the new active memory.

US Pat. No. 9,786,536

RETICLE RACK SYSTEM

MICROCHIP TECHNOLOGY INCO...

11. A system of reticle rack units for storing reticles in a semiconductor fab, the system including multiple reticle rack
units, each reticle rack unit comprising:
a frame with four uprights and multiple crossbars, the frame having a longest dimension defining a front side and a back side;
four turnstiles mounted to the frame to pivot around a respective rotational axis parallel to the four uprights;
wherein each turnstile defines a plurality of reticle nests sized to hold reticles.

US Pat. No. 9,625,997

HUMAN INTERFACE DEVICE AND METHOD

MICROCHIP TECHNOLOGY INCO...

1. A method for state tracking based gesture recognition engine for a sensor system comprising the steps of:
defining a plurality of sequential states of a finite-state machine, wherein the finite state machine is a first order Markov
Model,

determining a Sequence Progress Level (SPL) for each state,
mapping a state probability distribution to an SPL on run-time, and
utilizing the mapped SPL estimate as an output value of the sensor system, wherein a most likely state is computed using a
Forward (Baum-Welch) Algorithm.

US Pat. No. 9,587,964

CAPACITIVE PROXIMITY DETECTION USING DELTA-SIGMA CONVERSION

MICROCHIP TECHNOLOGY INCO...

1. A proximity detection system, said system comprising:
a comparator having first and second inputs and an output, wherein the second input is coupled with a reference voltage and
the first input is coupled with a holding capacitor;

a capacitive sensor;
a switch for coupling the capacitive sensor alternately to a voltage and the holding capacitor;
a clock having an output;
a flip-flop having an input coupled with the output of the comparator, a clock input coupled to the output of the clock and
an output;

a feedback resistor coupled between the output of the flip-flop and the first input of the comparator;
a duty cycle counter having a clock input coupled to the output of the clock, a reset input, an enable input coupled to the
output of the flip-flop, and an output for providing a number of clock outputs counted, wherein the duty cycle counter only
counts the clock outputs when the enable input thereof is at a first logic level; and

a circuit for controlling the switch whenever the output of the flip-flop goes from a second logic level to the first logic
level;

wherein the number of clock outputs counted are used in determining proximity of an object to the capacitive sensor.

US Pat. No. 9,385,053

METHOD AND APPARATUS FOR SEMICONDUCTOR TESTING AT LOW TEMPERATURE

MICROCHIP TECHNOLOGY INCO...

1. A method for testing a plurality of semiconductor devices arranged on a strip, comprising:
forming an array of semiconductor devices on a frame, wherein contact pads of adjacent semiconductor devices are shorted;
partially cutting the strip to electrically isolate individual semiconductor devices in the array;
placing the strip on an adhesive tape configured to resist warping of the isolated test strip away from the test chuck at
temperatures extending below ?20° C.;

arranging the strip and tape on a test chuck;
exposing the test chuck, strip, and tape to temperatures below an ambient temperature; and
testing the plurality of semiconductor devices while exposed to a low temperature.

US Pat. No. 9,263,397

WAFER MAPPING PROCESS CONTROL WITH INDICATOR LINE

MICROCHIP TECHNOLOGY INCO...

1. A method for providing alignment in a die picking process, comprising:
aligning a semiconductor wafer based on a reference die;
forming an indicator line prior to picking a die, the indicator line formed relative to the reference die by picking a number
of dice along a line extending across the wafer; and

using the indicator line to monitor a position of the picking machine relative to the wafer.

US Pat. No. 9,208,095

CONFIGURABLE CACHE FOR A MICROPROCESSOR

MICROCHIP TECHNOLOGY INCO...

1. A cache module for a central processing unit comprising:
a cache control unit controlling an operation of said cache module and comprising an interface for a memory and an interface
for a central processing unit, wherein upon request by the central processing unit, the cache module provides data and/or
instructions to said central processing unit,

a cache memory coupled with said control unit, wherein said cache memory comprises a plurality of cache lines, at least one
cache line of said plurality of cache lines comprises an address tag bit field and an associated storage area for storing
instructions or data, wherein said address tag bit field is readable and writeable by said central processing unit and wherein
said cache control unit is operable upon detecting that an address has been written to said address tag bit field by said
central processing unit to initiate a preload function in which instructions or data from said memory are loaded from said
address into said at least one cache line.

US Pat. No. 10,048,089

DIGITAL PERIOD DIVIDER

MICROCHIP TECHNOLOGY INCO...

1. A system comprising:a digital period divider generating an output signal that is proportional to an angle defined by a rotational input signal comprising a plurality of subsequent pulses, wherein the digital period divider comprises
a first counter comprising N bits, with R least significant bits (LSB) and P most significant bits (MSB), a count input, and a reset input, wherein the count input receives a reference clock signal and the reset input receives the rotational input signal, wherein R and P are integer numbers greater than 1 and R+P=N;
a latch having P bits and being coupled with the P most significant bits of the first counter;
a second counter having P bits comprising a count input and a reset input, wherein the count input receives the first clock signal; and
a first comparator operable to compare the P bits of the latch with the P bits of the second counter and generating an output signal, wherein the output signal is also fed to the reset input of the second counter;
an interval measurement unit determining an interval time of an interval defined by succeeding pulses of the output signal; and
a missing pulse detector operable to compare a current interval with a parameter to determine whether a pulse is missing in the rotational input signal.

US Pat. No. 9,857,394

MULTIPLE CHANNEL CAPACITIVE VOLTAGE DIVIDER SCANNING METHOD AND APPARATUS

MICROCHIP TECHNOLOGY INCO...

1. A method for determining change in capacitance of at least one capacitive sensor of a plurality of capacitive sensors,
said method comprising steps of:
coupling by first switches the plurality of capacitive sensors with a first voltage;
coupling by second switches a sample and hold capacitor with a second voltage;
coupling by the first and second switches the plurality of capacitive sensors with the sample and hold capacitor, wherein
electron charge from the plurality of capacitive sensors is transferred to the sample and hold capacitor;

measuring by a processor a resulting voltage on the sample and hold capacitor; and
comparing by the processor the resulting voltage to a previously measured resulting voltage, wherein if the resulting voltage
is different than the previously measured resulting voltage then the at least one capacitive sensor of the plurality of capacitive
sensors has changed capacitance value.

US Pat. No. 9,844,117

APPARATUS AND METHOD FOR LED RUNNING LIGHT CONTROL AND STATUS

MICROCHIP TECHNOLOGY INCO...

1. A light emitting diode (LED) running light, comprising:
a plurality of series coupled LED block cells;
each of the plurality of the LED block cells comprising
at least one LED; and
a bypass circuit comprising a switch independently connecting a cathode of the at least one LED with an input terminal of
a current sink, wherein the bypass circuit decouples the cathode of the LED from the current sink when a voltage at an anode
of the LED is greater than a certain voltage value,

wherein each bypass circuit comprises:
a first transistor forming said switch and being coupled between the cathode of the LED and the current sink;
a zener diode coupled between the anode of the LED and one end of a first resistor having another end thereof coupled to a
power supply common; and

a second transistor having an input coupled to a junction of the zener diode and the first resistor, and an output coupled
to an input of the first transistor, wherein a voltage across the first resistor turns on the second transistor which then
turns off the first transistor, thereby decoupling the cathode of the LED from the current sink.

US Pat. No. 9,512,659

CODE HOPPING BASED SYSTEM WITH INCREASED SECURITY

MICROCHIP TECHNOLOGY INCO...

1. A wireless access system comprising:
a transmitter and a receiver for exchange of secure data wherein the system uses an encryption and a decryption algorithm
to exchange a secure data packet, said secure data packet comprising:

an unencrypted data portion,
an encrypted data portion, wherein the encrypted data portion comprises:
a first data portion formed by a first data section of data encrypted by the encryption algorithm, wherein the first data
section forms part of a hopping code, and

a second data portion comprising data decrypted by the decryption algorithm, wherein the data decrypted by the decryption
algorithm comprises a combination of a secure signature derived from the hopping code and encrypted data formed by a second
data section of the data encrypted by the encryption algorithm, wherein the secure signature is formed by CRC data calculated
by a CRC algorithm applied to the data encrypted by the encryption algorithm, wherein the secure signature comprises a predefined
number of bits from the CRC data.

US Pat. No. 9,404,948

MAINS VOLTAGE ZERO-CROSSING DETECTOR

MICROCHIP TECHNOLOGY INCO...

1. A mains voltage zero-crossing detector, comprising:
a first output driver coupled between an first rail voltage and an external node;
a second output driver coupled between a second rail voltage and the external node;
an amplifier having first and second differential inputs, and first and second single ended outputs, wherein a first output
thereof is coupled to a control input of the first output driver and a second output thereof is coupled to a control input
of the second output driver;

a feedback network coupled between the external node and the second differential input of the amplifier;
a voltage reference coupled to the first differential input of the amplifier;
a class B control circuit coupled to the control inputs of the first and second output drivers, wherein the class B control
circuit forces one of the first or second output drivers off when the other output driver is conducting, and releases control
back to the amplifier as it stops conducting; and

a current mode detector circuit coupled to the control inputs of the first and second output drivers, wherein the current
mode detector circuit provides mains voltage zero-crossing detection based upon currents applied to the control inputs of
the first and second output drivers.

US Pat. No. 9,323,985

AUTOMATIC GESTURE RECOGNITION FOR A SENSOR SYSTEM

MICROCHIP TECHNOLOGY INCO...

1. A method for touchless gesture recognition comprising:
detecting one or more gesture-related signals using an associated plurality of detection sensors; and
evaluating the touchless gesture detected from the one or more gesture-related signals using an automatic recognition technique
to determine if the touchless gesture corresponds to one of a predetermined set of gestures, wherein in determining a start
of the gesture, a start is determined if the distance between the target object and at least one sensor decreases and the
distance between the target object and at least another sensor increases, and a short term variance or an equivalent measure
over a predetermined plurality of signal samples is less than a threshold.

US Pat. No. 9,269,606

SPACER ENABLED ACTIVE ISOLATION FOR AN INTEGRATED CIRCUIT DEVICE

MICROCHIP TECHNOLOGY INCO...

1. A method for forming an active isolation structure in a semiconductor integrated circuit die, the method comprising:
depositing a first hard mask layer on a surface of a semiconductor substrate;
removing portions of the first hard mask layer to form at least one trench, each trench defining side walls and an open bottom
exposing the semiconductor substrate surface;

depositing a spacer layer over the first hard mask and extending into each said trench to cover the exposed semiconductor
substrate surface in each said trench;

removing portions of the spacer layer, including portions of the spacer layer covering the exposed semiconductor substrate
surface in each said trench, such that remaining portions of the spacer layer define spacer layer side walls covering the
side walls of each said trench, the spacer layer side walls having upper, rounded portions;

depositing a second hard mask layer extending into each trench between opposing spacer layer side walls in each respective
trench;

after depositing the second hard mask layer, performing a material removal process that removes (a) upper portions of the
first hard mask layer, (b) upper portions of the second hard mask layer, and (c) the upper, rounded portions of the spacer
layer side walls to expose lower, non-rounded surfaces of the spacer layer side walls,

after performing the material removal process, removing the spacer layer side walls such that remaining portions of the first
and second hard mask layers define a mask pattern;

transferring the mask pattern to the semiconductor substrate by removing portions of the semiconductor substrate to form openings
in the semiconductor substrate; and

filling the openings in the semiconductor substrate with an isolation material.

US Pat. No. 9,236,852

INPUT CAPTURE PERIPHERAL WITH GATING LOGIC

MICROCHIP TECHNOLOGY INCO...

1. A microcontroller comprising an input capture peripheral, wherein the input capture peripheral receives an input signal
and is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral comprises
a gating input which controls whether an input capture function is activated, wherein the gating input is operable to be coupled
with the output of a first comparator comparing the input signal with a threshold value.

US Pat. No. 9,685,432

COMPACT ELECTROSTATIC DISCHARGE (ESD) PROTECTION STRUCTURE

MICROCHIP TECHNOLOGY INCO...

1. An electrostatic discharge (ESD) protection device, comprising:
a first field effect transistor (FET) having a drain, at least two gates and a source, wherein the drain thereof is coupled
to a node of a circuit to be protected from an ESD event;

at least one first diode having an anode coupled to the source of the first FET;
a first resistor coupled between the at least two gates of the first FET; and
a second resistor coupled to a one of the at least two gates and a cathode of the at least one first diode;
a second field effect transistor (FET) having a drain, at least two gates and a source, wherein the drain thereof is coupled
to a power supply common;

at least one second diode having an cathode coupled to the cathode of the at least one first diode;
a third resistor coupled between the at least two gates of the second FET; and
a fourth resistor coupled to a one of the at least two gates of second FET and a cathode of the at least one second diode.

US Pat. No. 9,634,135

POWER FIELD EFFECT TRANSISTOR

MICROCHIP TECHNOLOGY INCO...

1. A field-effect transistors (FET) cell structure comprising:
a substrate being highly doped and being of a first conductivity type and forming a drain of the FET;
an epitaxial layer of the first conductivity type on said substrate;
first and second base regions of a second conductivity type arranged within said epitaxial layer and spaced apart;
first and second source regions of a first conductivity type arranged within said first and second base region, respectively;
a gate structure insulated from said epitaxial layer by an insulation layer and arranged above the region between the first
and second base regions and covering at least partly said first and second base region,

a drain contact via structure reaching from a top of the device into the epitaxial layer and being located in an area where
the epitaxial layer extends from the substrate to the top of the device, wherein a bottom end of the drain contact via structure
which is located within the epitaxial layer is coupled with the substrate through an implant connecting only the epitaxial
layer and the bottom region of the drain contact via structure with the substrate, wherein the implant starts within a bottom
region of the epitaxial layer and extends vertically into said substrate in the area of the drain contact and only connects
with the bottom end of the drain contact via structure, the substrate and the epitaxial layer.

US Pat. No. 9,630,352

OPEN CAVITY PLASTIC PACKAGE

MICROCHIP TECHNOLOGY INCO...

1. A mold for forming a package for an integrated circuit sensor device, comprising
a bottom part for supporting an integrated circuit die;
a top part that is operable to be placed on top of said bottom part to form a cavity into which a plastic material can be
injected to form the package, wherein the top part of the mold comprises a spring-loaded pin arrangement comprising a pin
extending from a cylindrical cover and being guided within a spring housing wherein the pin can be vertically moved against
a spring force, wherein the cylindrical cover has a conical recess that is operable to cover a sensor area on the integrated
circuit die and wherein the top part provides for an opening through which the plastic material can be injected.

US Pat. No. 9,602,101

INTEGRATED DEVICE WITH AUTO CONFIGURATION

MICROCHIP TECHNOLOGY INCO...

1. Method for controlling a configuration in an integrated circuit device comprising at least one controllable input/output
port having a data output driver, a data input driver, a controllable pull-up resistor, a controllable pull-down resistor,
each connected with an external pin of the integrated circuit device, the method comprising;
enabling only the pull-up resistor and reading the associated input through the data input driver as a first bit;
enabling only the pull-down resistor and reading the associated input through the data input driver as a second bit;
tri-stating the first port and reading the associated input through the data input driver as another bit;
encoding a value from the read bits; and
determining a firmware operation form the encoded value.

US Pat. No. 9,351,158

METHOD FOR WIRELESS EASY CONNECT

MICROCHIP TECHNOLOGY INCO...

1. A method for connecting a wireless device to a wireless network, said method comprising the steps of:
listening for a trigger code when the wireless device is powered on;
sending the trigger code from a user device, wherein the trigger code is sent through a wireless router of the wireless network;
receiving the trigger code with the wireless device;
transmitting recognition information from the wireless device to the user device;
creating a pair-wise key from the recognition information;
handshaking on the pair-wise key between the wireless device and the user device;
sending wireless router access information from the user device;
receiving the wireless router access information with the wireless device; and
sending the wireless router access information from the wireless device to the wireless router to join the wireless network
as a client.

US Pat. No. 9,300,319

2-PHASE SWITCHED CAPACITOR FLASH ADC

MICROCHIP TECHNOLOGY INCO...

1. An input stage for a switched capacitor analog-to-digital converter, comprising:
a switching unit comprising a plurality of switching devices;
a differential voltage input receiving an input voltage;
a differential reference voltage input receiving a chopped reference voltage;
a common voltage connection;
a differential output;
a pair of input capacitors coupled between the differential voltage input and the differential output via a first switching
device of the plurality of switching devices;

a pair of reference capacitors coupled between the differential reference voltage input and the differential output via a
second switching device of the plurality of switching devices;

wherein the switching unit is controlled by a first and second phase and operable:
during the first phase to connect first terminals of the input capacitors via a third switching device of the plurality of
switching devices with the common voltage connection and couple first terminals of the reference capacitors via the second
switching device with an inverted chopped reference voltage; and

during a second phase to connect the first terminals of the input capacitors via the first switching device with the input
voltage and couple the first terminals of the reference capacitors with the non-inverted chopped reference voltage.

US Pat. No. 9,842,076

SWITCHLESS USB C-CONNECTOR HUB

MICROCHIP TECHNOLOGY INCO...

16. A method for operating a USB hub, the USB hub comprising:
a USB integrated circuit device including USB hub logic including a plurality of USB ports, wherein:
at least one port comprises a pair of bi-directional transmission channels;
two physical layers are directly connected to the at least one port, wherein each physical layer being associated with one
bidirectional transmission channel; and

the USB hub logic is further configured to select one and only one of said physical layers for each port depending on a logic
condition; and

an external USB Type-C connector having connection pins that are arranged symmetrical that first bi-directional lines of an
associated plug inserted into the external connector are either connected with first bi-directional lines of the connector
or second bi-directional lines of the connector depending on an insertion direction of the plug;
the method comprising:
plugging in USB3 Type-C plug into the USB3 Type-C connector in a first configuration;
decoding configuration lines coupled to respective configuration contacts of the USB3 Type-C connector by the USB hub; and
selecting a first one of the physical layers associated with the USB3 Type-C connector.

US Pat. No. 9,712,206

PREAMBLE DESIGN AND PROCESSING METHOD FOR ON-THE-FLY, FRAME-BY-FRAME AIR DATA RATE DETECTION IN WIRELESS RECEIVERS

MICROCHIP TECHNOLOGY INCO...

1. A system for wireless communication comprising a transmitter and a receiver, wherein the transmitter is operable to wirelessly
transmit digital information using a common modulation format to the receiver with a selected data transmission rate, wherein
the data transmission rate can be selected from a predetermined plurality of data transmission rates, wherein the digital
information is transmitted using a transmission frame including a header part and a payload part, wherein the header part
comprises a preamble, wherein the preamble is transmitted first within the transmission frame, wherein the modulation format
is the same for all data transmission rates, wherein the header and payload parts are transmitted at a same data rate for
any of the selected data transmission rates, and wherein the receiver is configured to receive the preamble and to sample
the preamble with different sample rates and select the sample rate that produces a valid preamble from the received preamble,
wherein the header part comprises the preamble, and a start frame delimiter, wherein the selected sample rate from the preamble
defines one of a plurality of data transmission rate groups and the start frame delimiter is configured to further define
different data transmission rates within a data transmission rate group, and wherein a transmission time for the preamble
and the start frame delimiter for each of the plurality of data transmission rate groups has a different length and is defined
by a repetition of a chip sequence which encodes a data signal, wherein the chip sequence comprises a predefined chip pattern
for each of the plurality of data transmission rate groups.

US Pat. No. 9,577,650

PHASE LOCK LOOP LOCK INDICATOR

MICROCHIP TECHNOLOGY INCO...

1. A Circuit to indicate when a divided down version of an output signal of a Phase Locked Loop (PLL) has a frequency close
enough to the frequency of an input reference clock signal, wherein the circuit evaluates the output signals of the PLL Phase
Frequency Detector (PFD) to establish a lock-on signal of the PLL with respect to the input reference clock signal, wherein
the PFD provides for an up pulse signal, a down pulse signal, a not-up pulse signal and a not-down pulse signal, wherein the
not-up pulse signal and the not-down pulse signal are complementary to the up pulse signal and the down pulse signal, respectively,
wherein the circuit comprises a first OR gate receiving the up pulse signal and the down pulse signal and generating ORed
up- and down-pulse signals, and a second OR gate receiving the not-up pulse signal and the not-down pulse signal and generating
ORed not-up- and not-down- pulse signals, wherein the circuit is further configured to compare the duration of the ORed up-
and down-pulse signals with the duration of the ORed not-up- and not-down- pulse signals, and

wherein the circuit generates the lock-on signal when the duration of the ORed up- and down- pulse signals are smaller than
a certain fraction of the duration of the ORed not-up- and not-down- pulse signals.

US Pat. No. 9,261,932

MINIMIZING SWITCHOVER TIME IN A HOT SWAPPABLE PROGRAM MEMORY

MICROCHIP TECHNOLOGY INCO...

1. A method for hot swapping program code in a microcontroller comprising a central processing core comprising a stack and
a heap, a program memory comprising a first and second region, a volatile data memory, a plurality of peripheral devices wherein
each peripheral device is individually resettable, the method comprising:
executing a current program from the first region of the program memory;
defining a predetermined range of new code in the second region of the program memory from which to execute;
wherein the second region comprises information or instructions whether the stack pointer needs to be set up, whether the
heap needs to be set up, whether parts of the volatile data memory need to be initialized, and which peripheral device from
the plurality of peripheral devices requires a reinitialization or reset;

wherein a switch-over to the new code performs the steps of:
if required setting up the stack pointer and heap,
if required reinitializing said parts of the volatile data memory; and
reinitializing or resetting one or more peripheral device of the plurality of peripheral device;
and executing the new code.

US Pat. No. 9,176,088

METHOD AND APPARATUS FOR DETECTING SMOKE IN AN ION CHAMBER

MICROCHIP TECHNOLOGY INCO...

1. A method for detecting smoke, comprising the steps of:
coupling an ionization chamber to a capacitive voltage divider (CVD) circuit;
determining a change in a capacitance of the ionization chamber using the CVD circuit by:
determining a first change in the capacitance of the ionization chamber when the ionization chamber is at a first polarity;
determining a second change in the capacitance of the ionization chamber when the ionization chamber is at a second polarity;
determining a difference between the first change and the second change; and
using the difference in determining the change in the capacitance of the ionization chamber;
and
detecting the presence of smoke by detecting a predetermined change in the capacitance.

US Pat. No. 9,054,851

DITHERING CIRCUIT FOR SERIAL DATA TRANSMISSION

MICROCHIP TECHNOLOGY INCO...

1. A method for determining a unit time of a serial transmission protocol, wherein the serial transmission protocol defines
a unit time (UT) by transmitting a calibration pulse having a predetermined length of N*UT, wherein the transmission protocol
sends the calibration pulse followed by a plurality of data nibbles, wherein each data nibble is encoded by an associated
pulse width length which is a multiple of the UT, and wherein a receiver is operated by a system clock, the method comprising:
dividing the system clock by M, wherein M evenly divides N,
measuring the calibration pulse length using the divided system clock
sampling a received data nibble length by using a sampling clock, wherein the sampling clock is a clock signal derived by
dithering the divided system clock.

US Pat. No. 10,002,103

LOW-PIN MICROCONTROLLER DEVICE WITH MULTIPLE INDEPENDENT MICROCONTROLLERS

MICROCHIP TECHNOLOGY INCO...

1. A microcontroller device comprising:a plurality of external pins;
a first microcontroller comprising a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus,
a second microcontroller comprising a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus,
wherein first and second microcontroller are separate from each other and do not share any of their peripheral devices and communicate only via a dedicated interface,
wherein the dedicated interface comprises a bidirectional mailbox interface, a unidirectional master-slave interface and a unidirectional slave-master interface, and
wherein each unidirectional interface comprises a FIFO memory.

US Pat. No. 9,921,982

DEVICE AND METHOD TO ASSIGN DEVICE PIN OWNERSHIP FOR MULTI-PROCESSOR CORE DEVICES

MICROCHIP TECHNOLOGY INCO...

1. An embedded device comprising:
a plurality of processor cores, each comprising a plurality of peripheral devices, wherein each peripheral device may comprise
an output;

a housing comprising a plurality of assignable external pins; and
a protected pin ownership logic for each assignable external pin and configured to be programmable to assign an output function
of an associated assignable external pin to only one of the plurality of processor cores.

US Pat. No. 9,904,646

VIRTUAL GENERAL PURPOSE INPUT/OUTPUT FOR A MICROCONTROLLER

MICROCHIP TECHNOLOGY INCO...

1. A microcontroller comprising:
a plurality of general purpose input/output (GPIO) ports each having a plurality of bits each bit having a predefined association
with one of a plurality of external pins;

a first set of registers being directly programmable and operable to provide a first GPIO port control and digital data input/output
functionality for all bits of one of the plurality of GPIO ports through associated external pins;

a second set of registers being directly programmable and operable to provide a second GPIO port control and digital data
input/output functionality for all bits of the one of the plurality of GPIO ports through the associated external pins;

a multiplexer and associated select register configured to control the multiplexer to control a GPIO function of any of the
associated external pins of the one of the plurality of GPIO ports depending on a setting of the select register through either
said first or second register set or at least one of a plurality of peripheral devices of the microcontroller.

US Pat. No. 9,866,270

COAXIAL DATA COMMUNICATION WITH REDUCED EMI

MICROCHIP TECHNOLOGY INCO...

1. A transmission circuit using two coaxial cables each having a center conductor and a shield, comprising:
an integrated circuit comprising a differential driver having first and second outputs, and a differential receiver having
first and second inputs;

a first common mode choke coupled between the first output of the differential driver and a center conductor of the coaxial
cable, and between the second output of the differential driver and the shield of one of the coaxial cables, wherein the shield
is directly connected with a first ground node;

a first terminating impedance coupled between the second output of the first differential driver and a second ground node;
a second common mode choke coupled between the first input of the differential receiver and the center conductor of the other
coaxial cable, and between the second input of the differential receiver and the shield of the other coaxial cable;

second terminating impedances coupled between the first and second inputs of the differential receiver and the second ground
node; and

a dissipative element coupled between the shield of the other coaxial cable and the first ground node.

US Pat. No. 9,825,617

INDUCTIVE LOAD DRIVER SLEW RATE CONTROLLER

MICROCHIP TECHNOLOGY INCO...

1. An integrated circuit for driving a first load switch wherein the first load switch powers a current load, the integrated
circuit comprising:
a first digital slew-rate control unit for generating first control signals comprising a first digital logic gate receiving
a feedback signal from the current load through a series connected first capacitor and first resistor wherein a node between
the first resistor and the first capacitor is coupled with an input of the first digital logic gate, wherein the first digital
slew-rate control unit generates the first control signals based on the feedback signal that indicates the rate of voltage
change on the current load; and

a first driver operated by the first control signals, wherein the first driver generates a slew-rate controlled output signal
that operates the first load switch,

wherein the first driver is modulated to generate the slew-rate controlled output signal during state transitions of the first
load switch, wherein the modulation performs discrete slew-rate adjustments.

US Pat. No. 9,780,748

SELECTABLE PROGRAMMABLE GAIN OR OPERATIONAL AMPLIFIER

MICROCHIP TECHNOLOGY INCO...

1. A configurable amplifier, comprising:
a differential input stage and a bias circuit coupled to the differential input stage;
a first output block;
a second output block;
a feedback network; and
a plurality of switches coupled to the differential input stage, the feedback network, the first output block and the second
output block;

wherein
the differential input stage, the feedback network, and the first output block are coupled together as a programmable gain
amplifier when certain ones of the plurality of switches are arranged in a first mode,

the differential input stage and the second output block are coupled together as an operational amplifier without any feedback
network when the certain ones of the plurality of switches are arranged in a second mode, and

wherein the bias circuit has a first set of bias parameters for the programmable gain amplifier configuration when in the
first mode, and a second set of bias parameters for the operational amplifier configuration when in the second mode.

US Pat. No. 9,778,289

MEASURING OUTPUT CURRENT IN A BUCK SMPS

MICROCHIP TECHNOLOGY INCO...

1. An apparatus for determining a power inductor current sample point in a buck switched-mode power supply (SMPS), comprising:
a constant current source having first and second nodes, wherein the first node thereof is coupled to a voltage source;
a constant current sink having first and second nodes, wherein the constant current sink is twice the current value of the
constant current source;

a current source switch coupled between the second node of the constant current source and the first node of the constant
current sink;

a current sink switch coupled between the second node of the constant current sink and a voltage source common;
a timing capacitor coupled between the first node of the constant current sink and the voltage source common;
a voltage comparator having a first input coupled to a predetermined reference voltage, a second input coupled to the timing
capacitor and an output, wherein the output thereof is at a first logic level when the voltage on the timing capacitor is
greater than the predetermined reference voltage, and at a second logic level when the voltage on the timing capacitor is
equal to or less than the predetermined reference voltage; wherein

when a high side switch signal from the SMPS goes to a first logic level the current source switch turns on and couples the
constant current source to the timing capacitor, whereby a voltage on the timing capacitor increases;

when the high side switch signal from the SMPS goes to a second logic level the current source switch turns off and decouples
the constant current source from the timing capacitor, whereby the voltage on the timing capacitor stays the same; and

when a 50% pulse width modulation (PWM) period signal from the SMPS is received the current sink switch turns on and couples
the constant current sink to the timing capacitor, whereby the voltage on the timing capacitor decreases twice as fast it
increased when the high side switch signal is at the second logic level, and when the high side switch signal is at the first
logic level the voltage on the timing capacitor decreases at the same rate as it increased.

US Pat. No. 9,735,820

MULTI-CURRENT HARMONIZED PATHS FOR LOW POWER LOCAL INTERCONNECT NETWORK (LIN) RECEIVER

MICROCHIP TECHNOLOGY INCO...

1. A local interconnect network receiver, comprising:
a battery voltage input;
an input from a local interconnect network (LIN) bus; and
a current mirror configured to mirror a current defined by a reference resistor coupled to the battery voltage input in a
sense resistance, such that a voltage at an output point of the sense resistance defines dominant and recessive states of
the LIN bus in active, silent and sleep modes.

US Pat. No. 9,753,830

DYNAMIC PAUSE PERIOD CALCULATION FOR SERIAL DATA TRANSMISSION

MICROCHIP TECHNOLOGY INCO...

1. A serial transmission peripheral device for transmitting serial transmission data comprising:
a transmitter configured to sequentially transmit a plurality of data nibbles, wherein each data nibble is encoded in a variable
length data pulse, and

a register programmable to set a desired transmission length for a plurality of transmission frames each of the plurality
of transmission frames including a plurality of sequential variable length data nibble pulses and a pause pulse, wherein the
desired transmission length of the transmission frame is a constant pulse width, the constant pulse width not based on a value
associated with any one of the plurality of sequential variable length data nibble pulses;

wherein for each transmission frame, the transmitter is configured to calculate a required length of the pause pulse and to
add the pause pulse at the end of a transmission of the plurality of sequential variable length data nibble pulses; and

wherein the pause pulse length is computed when a pause period starts.

US Pat. No. 9,712,950

BLUE-TOOTH COMMUNICATION SYSTEM AND BROADCASTING METHOD THEREOF

MICROCHIP TECHNOLOGY INCO...

1. A broadcasting method for a blue-tooth communication system, comprising:
detecting N blue-tooth receivers in a blue-tooth range of a blue-tooth transmitter, wherein N is a positive integer;
broadcasting a data package by the blue-tooth transmitter during at least one transmitting timing window; and
during N receiving timing windows, receiving N returned data packages which are respectively returned by the corresponding
blue-tooth receivers by the blue-tooth transmitter during N receiving timing windows, wherein at least one of the N returned
data packages includes an acknowledge message which is recorded in a header field of the corresponding returned data package;

wherein one of the received returned data packages is to indicate that the data package was a broadcast data package.

US Pat. No. 9,705,408

POWER CONVERTER WITH SLEEP/WAKE MODE

MICROCHIP TECHNOLOGY INCO...

1. A method for entering and exiting a low power sleep mode in a power converter, said method comprising the steps of:
providing a primary-side energy storage circuit comprising
a primary-side start-up controller,
a power switch coupled to a transformer, and
a primary-side energy storage capacitor;
providing a secondary-side energy storage circuit comprising
a secondary-side controller, and
a secondary-side energy storage capacitor;
coupling the primary-side and secondary-side energy storage circuits through the transformer;
controlling the power switch, during start-up, with the primary-side start-up controller until an operating voltage on the
secondary-side energy storage capacitor reaches a desired value; and

entering into a low power sleep mode, wherein the primary-side and secondary-side circuitry, in a low IQ mode, operates from
energy stored in their respective energy storage capacitors, wherein when a respective voltage on either one of the energy
storage capacitors is less than or equal to respective low voltage limits then either the primary-side start-up controller
can wake itself or the secondary-side controller can wake itself and can wake the primary-side start-up controller, whereby
the primary and secondary energy storage capacitors are charged until both respective voltages are greater than their respective
low voltage limits,

wherein the secondary-side controller raises a voltage on the secondary-side energy storage capacitor before going into the
low power sleep mode and when the voltage on the secondary-side energy storage capacitor rises, a voltage on the primary-side
energy storage capacitor also rises, wherein the primary-side start-up controller detects this rise in voltage on the primary-side
energy storage capacitor and thereby goes into the low power sleep mode.

US Pat. No. 9,667,212

GAIN CONTROL METHOD, MODULE, AND WIRELESS SIGNAL RECEIVER USING THE SAME

MICROCHIP TECHNOLOGY INCO...

1. A gain control method, executed in a wireless signal receiver, comprising:
continuously monitoring a wideband channel to check whether an interference signal exists in a wireless signal;
obtaining an interference received signal strength indicator (RSSI) when the interference signal exists in the wireless signal;
and

controlling a front end gain of the wireless signal receiver according to the interference RSSI;
wherein:
the wireless signal receiver is prohibited from using a maximum front end gain when the interference signal exists in the
wireless signal;

an interference score is updated according to the interference RSSI;
the front end gain of the wireless signal receiver is determined by the interference score; and
the interference score is increased by 1 when the interference signal exists in the wireless signal, and the interference
score is decreased by 1 when the interference signal does not exist in the wireless signal, wherein a lowest interference
score is equal to 0, and the wireless signal receiver is prohibited from using the maximum front end gain when the interference
score is not equal to 0.

US Pat. No. 9,589,828

METHOD FOR PHOTOLITHOGRAPHY-FREE SELF-ALIGNED REVERSE ACTIVE ETCH

MICROCHIP TECHNOLOGY INCO...

1. A method for photolithography-free self-aligned reverse active etch of a semiconductor wafer, said method comprising the
steps of:
depositing a pad oxide on a silicon substrate of the semiconductor wafer;
depositing an active silicon nitride on the pad oxide;
forming shallow trench isolation (STI) wells in the silicon substrate;
forming an oxidization liner in the STI wells, wherein the oxidization liner is only formed where the silicon substrate is
exposed;

depositing an oxide over the silicon nitride and the STI wells;
depositing a partially planarized organosilicate layer over the oxide;
performing a dry plasma etch to remove the partially planarized organosilicate layer from the oxide by first non-selective
etching thereby removing some of the partially planarized organosilicate layer and some of the oxide and then selectively
etching the oxide thereby only removing the oxide, wherein the oxide above the silicon nitride is removed to a predefined
thickness;

performing a chemical-mechanical polish (CMP) to remove all of the oxide covering the active silicon nitride; and
removing the active silicon nitride, wherein portions of the silicon substrate are exposed between the remaining oxide and
ready for the step of active transistor element doping in the silicon substrate.

US Pat. No. 9,583,435

FORMING FENCE CONDUCTORS USING SPACER ETCHED TRENCHES

MICROCHIP TECHNOLOGY INCO...

1. A method for forming fence conductors in a semiconductor integrated circuit die, said method comprising the steps of:
depositing a first dielectric on a face of a semiconductor substrate;
creating at least one trench in the first dielectric;
depositing a sacrificial film on the first dielectric including walls and a bottom of the at least one trench;
removing portions of the sacrificial film from a face of the first dielectric and the bottom of the at least one trench, wherein
only sacrificial films remain on the walls of the at least one trench;

depositing a second dielectric between the sacrificial films on the walls of the at least one trench;
removing the first and second dielectrics until top portions of the sacrificial film are exposed between the first and second
dielectrics;

removing the sacrificial films between the first and second dielectrics leaving at least two narrow channels therein;
depositing conductive material on faces of the first and second dielectrics and into the at least two narrow channels;
removing portions of the conductive material on the faces of the first and second dielectrics until only tops of the conductive
material are exposed in the at least two narrow channels: and

depositing a barrier layer in one of the at least two narrow channels before the step of depositing the conductive material
therein.

US Pat. No. 9,543,899

CLASS D POWER DRIVER PERIPHERAL

MICROCHIP TECHNOLOGY INCO...

1. A class D power driver peripheral, comprising:
a voltage comparator;
a differential amplifier having first and second inputs adapted for coupling to a load;
an operational amplifier having a first input coupled to an output of the differential amplifier and a second input coupled
to an analog voltage, wherein an output of the operational amplifier is coupled to a first input of the voltage comparator;
and

a closed loop compensation circuit coupled between the first input and the output of the operational amplifier;
a capacitive sensing module (CSM) having an output coupled to a second input of the voltage comparator and to an external
capacitor, wherein the CSM provides a triangle waveform output to the voltage comparator and the external capacitor determines
a frequency of the triangle waveform; and

a complementary output generator (COG) having an input coupled to an output of the voltage comparator and a plurality of outputs
controlled by the output of the voltage comparator and configured to drive a driver stage coupled with the load.

US Pat. No. 9,543,948

PHYSICAL FORCE CAPACITIVE TOUCH SENSORS

MICROCHIP TECHNOLOGY INCO...

1. A physical force capacitive touch sensor, comprising:
a substrate;
a capacitive sensor element on a face of the substrate comprising an array of electrodes;
a cover comprising a first section forming a substantially non-deformable spacer on the substrate that surrounds the capacitive
sensor element and a second section forming a flexible cover covering the capacitive sensor element;

an electrically conductive plane coupled with the flexible cover via an array of pedestals and being proximate to the capacitive
sensor element and being arranged to at least partially cover each electrode in said array of electrodes;

wherein a density of pedestals in the array of pedestals coupled between the flexible cover and the electrically conductive
plane is greater than a density of electrodes in the array of electrodes; and

wherein when a mechanical force is applied to the flexible cover, the flexible cover and electrically conductive plane are
biased toward the capacitive sensor element, whereby the capacitive sensor element changes capacitance value.

US Pat. No. 9,521,503

AUDIO PLAYER WITH BLUETOOTH FUNCTION AND AUDIO PLAYING METHOD THEREOF

MICROCHIP TECHNOLOGY INCO...

1. An audio player with a Bluetooth function, comprising:
a master Bluetooth speaker, configured for having a Bluetooth field, receiving a digital compression audio, and decoding the
digital compression audio to generate a master decoded audio and a master decoded time corresponding to the master decoded
audio;

a plurality of slave Bluetooth speakers, disposed in the Bluetooth field to receive the digital compression audio transmitted
from the master Bluetooth speaker and receiving the master decoded time after the master Bluetooth speaker generating the
master decoded time, wherein each slave Bluetooth speaker decodes the digital compression audio to generate a slave decoded
audio and a slave decoded time corresponding to the slave decoded audio, and each slave Bluetooth speaker comprises:

a processor, configured for receiving the master decoded time and the slave decoded time and determining a time difference
between the master decoded time and the slave decoded time to generate a compensated signal indicating the time difference;
and

a compensation element, electrically connected to the processor and configured for receiving the compensated signal and the
slave decoded audio, wherein the compensation element adjusts the slave decoded audio based on the compensated signal to synchronize
the slave decoded audio and the master decoded audio and accordingly generates a compensated audio;

wherein when the master Bluetooth speaker analogizes the master decoded audio to play the analog master decoded audio, the
slave Bluetooth speaker analogizes the compensated audio to synchronously play the analog compensated audio.

US Pat. No. 9,825,754

INDEPENDENT UART BRK DETECTION

MICROCHIP TECHNOLOGY INCO...

1. A universal asynchronous receiver/transmitter (UART) module comprising:
a receiver unit being clocked by a programmable receiver clock configured to sample an incoming data signal and comprising
a counter clocked by said receiver clock, wherein the counter is reset to start counting with every falling edge of the data
signal and to trigger a break (BRK) detection signal if the counter reaches a programmable threshold value;

wherein the counter stops counting for triggering the BRK detection signal upon a rising edge of the data signal.

US Pat. No. 9,733,290

SENSOR DEVICE AND METHOD FOR CAPACITIVE APPROXIMATION DETECTION

MICROCHIP TECHNOLOGY INCO...

1. Capacitive sensor device with an electrode system, comprising:
a first transmitting electrode and a first reception electrode, wherein the first transmitting electrode is capacitively coupled
with the first reception electrode, and

a second transmitting electrode and a second reception electrode, wherein the second transmitting electrode is capacitively
coupled with the second reception electrode, a signal generator for feeding the first transmitting electrode with a first
electric alternating signal and the second transmitting electrode with a second electric alternating signal wherein the first
and second reception electrode receive signals from the first and second transmitting electrodes, respectively and wherein
the first reception electrode provides a respective first electric value and the second reception electrode provides a respective
second electric value, and

a signal processing device, which is coupled with the first reception electrode and with the second reception electrode, and
wherein the signal processing device forms a first measurement variable from the difference between the first electric value
and the second electric value and wherein the signal processing device further forms a second measurement variable from the
sum of the first electric value and the second electric value,

wherein the first electric variable substantially reduces the influence of interfering electric fields and the second electric
variable is non-zero in response to an object to be detected approaching the first and second transmitting electrodes unevenly,
and

wherein the AC voltage component of the first electric alternating signal is inverse to the AC voltage component of the second
electric alternating signal.

US Pat. No. 9,664,571

DIGITAL TEMPERATURE SENSOR WITH INTEGRATED TIMER AND BURST MODE

MICROCHIP TECHNOLOGY INCO...

1. Integrated temperature sensor device comprising:
a temperature sensor coupled with a sensor conditioning circuit providing a single analog signal, wherein the temperature
sensor is biased by the sensor conditioning circuit such that an ambient temperature can be derived from the single analog
signal;

an analog-to-digital converter coupled to the sensor conditioning circuit and receiving the single analog signal; and
a timer and control circuit which is configured to perform a sequence of temperature measurement periods and shut-down time
periods, wherein multiple temperature measurements are taken during each measurement period and the integrated temperature
sensor device is switched into a low power mode during the shut-down time periods, wherein the timer and control circuit is
programmable to set a number of temperature measurements and a length of the shut-down period.

US Pat. No. 9,632,526

MICROCONTROLLER WITH DIGITAL CLOCK SOURCE

MICROCHIP TECHNOLOGY INCO...

1. A microcontroller comprising:
a numerical controlled oscillator receiving a first clock signal and being configured to generate a second clock signal;
a first multiplexer controlled to select the first clock signal or the second clock signal;
wherein the selected clock signal is distributed within the microcontroller as the system clock, wherein the system clock
drives the operation of the microcontroller.

US Pat. No. 9,619,231

PROGRAMMABLE CPU REGISTER HARDWARE CONTEXT SWAP MECHANISM

MICROCHIP TECHNOLOGY INCO...

1. A method for performing a context switch in a central processing unit (CPU) comprising a plurality context defining register
sets, wherein each set of registers having the same number of CPU registers; the method comprising:
upon occurrence of an exception automatically switching to a register set of said plurality of context defining register sets,
wherein selection of a register set of said plurality of context defining register can further be manually initiated by executing
a context switch instruction; and

indicating a currently used context in a first bitfield and a most recent context selected by said instruction in a second
bitfield of a context status register.

US Pat. No. 9,601,615

HIGH VOLTAGE DOUBLE-DIFFUSED MOS (DMOS) DEVICE AND METHOD OF MANUFACTURE

MICROCHIP TECHNOLOGY INCO...

1. A method of simultaneously forming a double diffused metal oxide semiconductor (DMOS) transistor and an electrically erasable
programmable read-only memory (EEPROM) cell, comprising:
forming a first mask over a substrate;
forming a drift implant region in the substrate using the first mask to align the drift implant region;
simultaneously forming a first floating gate over the drift implant region in the substrate, and a second floating gate over
the substrate at a location spaced apart from the drift implant region;

forming a second mask covering the second floating gate and covering a portion of the first floating gate;
forming a base implant region in the substrate using an edge of the first floating gate to self-align the base implant region;
and

simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating
gate;

wherein the first floating gate, first control gate, drift implant region, and base implant region form components of the
DMOS transistor, and wherein the second floating gate and second control gate form components of the EEPROM cell.

US Pat. No. 9,515,549

CAPLESS VOLTAGE REGULATOR USING CLOCK-FREQUENCY FEED FORWARD CONTROL

MICROCHIP TECHNOLOGY INCO...

1. A voltage regulator for controlling an output device, comprising:
an error amplifier;
a controlled conductance output device; and
a load predicting circuit;
wherein an output of the error amplifier and an output of the load predicting circuit are summed to control the controlled
conductance output device; and

wherein the load predicting circuit is a frequency to current converter.

US Pat. No. 9,467,141

MEASURING CAPACITANCE OF A CAPACITIVE SENSOR WITH A MICROCONTROLLER HAVING AN ANALOG OUTPUT FOR DRIVING A GUARD RING

MICROCHIP TECHNOLOGY INCO...

13. A capacitive sensor system, said system comprising:
a capacitive sensor;
a guard ring associated with the capacitive sensor;
a microcontroller, comprising:
a digital processor with memory;
a plurality of external input/output nodes that can be programmed to function as analog nodes,
a multiplexer controlled by the digital processor for selecting one of said analog nodes and coupling the analog node to an
analog bus;

an analog-to-digital converter (ADC) coupled with the analog bus for converting an analog voltage on the analog bus to a digital
representation thereof and having a digital output coupled to the digital processor for conveying the digital representation;

a further external node which can be connected by means of a programmable switch controlled by the digital processor to the
analog bus independent from said multiplexer;

a sample and hold capacitor coupled to a plurality of switches;
a first node coupled to the plurality of switches;
wherein a first one of the plurality of switches couples the sample and hold capacitor to either an input of the ADC or the
first node;

a second node coupled to the plurality of switches and the capacitive sensor;
a third node coupled to the guard ring associated with the capacitive sensor; and
an analog driver having an analog input coupled to the second node and an analog output coupled to the third node, whereby
a voltage on the third node is substantially the same as a voltage on the second node;

wherein
a first one of the plurality of switches couples the first and second nodes together when closed,
a second one of the plurality of switches couples the first node to a power supply common when closed,
a third one of the plurality of switches couples the second node to a power supply voltage when closed,
a fourth one of the plurality of switches couples the first node to the power supply voltage when closed, and
a fifth one of the plurality of switches couples the second node to the power supply common when closed.

US Pat. No. 9,337,811

ASYMMETRIC HYSTERETIC CONTROLLERS

MICROCHIP TECHNOLOGY INCO...

11. An apparatus for hysteretic control of a pulse width modulation (PWM) generator, comprising:
a digital-to-analog converter (DAC);
a digital multiplexer having a first input coupled to a low limit register, a second input coupled to a high limit register,
an output coupled to an input of the DAC, and a control input coupled to an output of the PWM generator;

a comparator having a first input coupled to an output of the DAC and a second input coupled to a sense parameter from an
apparatus controlled by the PWM generator;

a polarity reversing circuit coupled to an output of the comparator;
pulse stretcher and filter logic having an input coupled to the polarity reversing circuit and an output coupled to a control
input of the PWM generator;

a blanking gate coupled between an output of the polarity reversing circuit and an input of the pulse stretcher and filter
logic;

a blanking timer; and
an edge detector coupled to the output of the PWM generator and an input of the blanking timer, wherein the edge detector
generates a pulse when the output of the PWM generator changes from a low level to a high level, or from the high level to
the low level, whereby the blanking timer starts a blanking time;

wherein the comparator compares the sense parameter to the DAC output representative of a high limit value stored in the high
limit register and coupled to the DAC input when the output of the PWM generator is high, and the DAC output representative
of a low limit value stored in the low limit register and coupled to the DAC input when the output of the PWM generator is
low;

whereby when the sense parameter is greater than the high limit value a signal from the pulse stretcher and filter logic causes
the PWM generator output to change from high to low, and when the sense parameter is less than the low limit value the signal
from the pulse stretcher and filter logic causes the PWM generator output to change from low to high.

US Pat. No. 10,096,189

DECRYPTION OF ACCESS CODES OF DIVERSE PROTOCOLS IN BARRIER OPERATOR SYSTEMS

OVERHEAD DOOR CORPORATION...

1. A barrier operator system for controlling a motor that moves a barrier between open and closed positions, comprising:at least one remote control transmitter device capable of transmitting encrypted commands in accordance with at least one of a plurality of encryption protocols, the encrypted commands instructing a barrier operator to move the barrier between the open and closed positions;
wherein the barrier operator is configured to:
in a regular operation mode, receive a learned encrypted command, decrypt the learned encrypted command, and control the motor in accordance with the decrypted learned command;
in a learn mode entered into in response to user input,
receive a learned command encrypted in accordance with one of the plurality of encryption protocols,
determine which of the plurality of encryption protocols the learned command was encrypted with, and indicate which of the plurality of encryption protocols the learned command was encrypted with,
in response to receipt of the learned command, open a window of time for receiving an unlearned command encrypted with another of the plurality of encryption protocols,
receive the unlearned command within the window of time, determine which of the plurality of encryption protocols the unlearned command was encrypted with, and indicate which of the plurality of encryption protocols the unlearned command was encrypted with, and
learn the unlearned command.

US Pat. No. 10,090,850

MICROCONTROLLER WITH DIGITAL DELAY LINE ANALOG-TO-DIGITAL CONVERTER

MICROCHIP TECHNOLOGY INCO...

1. A microcontroller comprising:a processor core;
memory; and
a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC), wherein each differential digital delay line is configured to operate at a speed according to a respective differential current, the ADC comprising:
a plurality of differential digital delay lines;
a first circuit comprising a set of delay elements included in the differential digital delay lines;
a second circuit comprising another set of delay elements included in the differential digital delay lines;
wherein:
the first circuit is configured to generate data representing an analog to digital conversion of an input; and
the second circuit is configured to calibrate a source to the differential digital delay lines; and
a plurality of latches configured to store data representing or based on relative speeds of respective delay elements;
wherein a respective latch is configured to save data from a slower differential digital delay line upon a completion of faster differential digital delay line.

US Pat. No. 10,044,264

MICROCONTROLLER WITH AVERAGE CURRENT MEASUREMENT CIRCUIT USING VOLTAGE-TO-CURRENT CONVERTERS

MICROCHIP TECHNOLOGY INCO...

1. A microcontroller, comprising:an external connection configured to receive a voltage from a shunt resistor;
a voltage-to-current converter having an input coupled to the external connection and adapted to convert the voltage to a current, wherein an output of the voltage-to-current converter is coupled to a sample capacitor and the current therefrom charges the sample capacitor to a sample voltage during a measurement time period;
at least one sample time period adjustment capacitor configured to be selectively switched in parallel with the sample capacitor;
an analog-to-digital converter (ADC) configured to be coupled to the sample capacitor after the measurement time period is over, wherein the ADC samples and then converts the sample voltage on the sample capacitor to a digital representation thereof; and
a sample voltage reset switch coupled to the sample capacitor, wherein the sample voltage reset switch resets the sample capacitor to a substantially zero voltage after the ADC has sampled the sample voltage thereon.

US Pat. No. 10,003,329

SYSTEM, METHOD AND APPARATUS HAVING IMPROVED PULSE WIDTH MODULATION FREQUENCY RESOLUTION

MICROCHIP TECHNOLOGY INCO...

1. An apparatus having improved pulse width modulation frequency resolution, said apparatus comprising:a pulse width modulation circuit operable to generate a pulse width modulation signal comprising a first and a second period;
a delay circuit delaying said pulse width modulation signal;
a multiplexer receiving said pulse width modulation signal and said delayed pulse width modulation signal; and
control logic coupled with said multiplexer, the control logic for:
selecting either said pulse width modulation signal or said delayed pulse width modulation signal depending on the selected period of said pulse width modulation signal, wherein the pulse width modulated output signal of said multiplexer has a third period which lies between said first and second period; and
selecting in alternating sequence said pulse width modulation signal and said delayed pulse width modulation signal to generate the pulse width modulated output signal of said multiplexer with the third period which lies between said first and second period.

US Pat. No. 9,921,985

DIRECT MEMORY ACCESS CONTROLLER

MICROCHIP TECHNOLOGY INCO...

1. A microcontroller comprising:
a bus;
a central processing unit (CPU) coupled with said bus;
a memory coupled with said bus;
a plurality of peripherals coupled with the bus;
a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from said CPU and being
coupled with said bus, wherein for access to said bus said DMA controller is programmable in a first mode to have priority
over said CPU and the plurality of peripherals and in a second mode to immediately suspend data transfer on all DMA channels
and grant the CPU direct access to the bus.

US Pat. No. 9,865,813

METHOD FOR FORMING RESISTIVE MEMORY CELL HAVING A SPACER REGION UNDER AN ELECTROLYTE REGION AND A TOP ELECTRODE

MICROCHIP TECHNOLOGY INCO...

1. A method of forming a resistive memory cell, comprising:
forming a bottom electrode layer on a substrate;
oxidizing an exposed region of the bottom electrode layer to form an oxide region;
removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a sidewall
and a pointed tip region at a top of the sidewall adjacent the oxide region;

depositing a spacer layer over at least the pointed tip region of the bottom electrode and the adjacent oxide region;
removing a portion of the spacer layer such that a spacer region remains laterally adjacent the sidewall of the bottom electrode;
forming an electrolyte region and a top electrode over at least the spacer region, the pointed tip region of the bottom electrode,
and the adjacent oxide region, such that the electrolyte region is arranged between the top electrode and the pointed tip
region of the bottom electrode.

US Pat. No. 9,829,542

CIRCUIT FOR MEASURING POWER VIOLATIONS USING HIGH SIDE CURRENT SENSING

MICROCHIP TECHNOLOGY INCO...

1. A power monitoring circuit comprising:
monitoring circuitry configured to detect and count transient deviations in the output current of a power supply, wherein
detecting a transient deviation comprises:

comparing the output current with a first threshold current; and
determining that the output current exceeds the first threshold current; and
monitoring circuitry configured to detect and measure prolonged deviations in the output current of the power supply, wherein
detecting a transient deviation comprises:

comparing the output current with a second threshold current;
determining that the output current exceeds the second threshold current;
determining a duration during which the output current exceeds the second threshold current;
comparing the determined duration with a duration threshold; and
determining that the duration exceeds the duration threshold.

US Pat. No. 9,804,977

UNIVERSAL SERIAL BUS SMART HUB

MICROCHIP TECHNOLOGY INCO...

1. A USB hub comprising:
a hub upstream port;
a plurality of hub downstream ports;
a processor;
a memory communicatively coupled to the processor for storing USB host stack code and a plurality of configuration parameters;
a USB hub core having a core upstream port and a plurality of core downstream ports, the USB hub core operable to implement
a USB hub interface between the core upstream port and the plurality of core downstream ports; and

a plurality of multiplexors, each of the plurality of multiplexors connected to a respective one of the plurality of core
downstream ports, and each multiplexor having:

a first port communicatively coupled to one of the hub downstream ports,
a second port communicatively coupled to one of the plurality of core downstream ports,
a third port communicatively coupled to the processor, and
a select input communicatively coupled to the processor and operable to communicatively couple the first port with the second
port, the third port, or both the second port and the third port, the select input of each of the plurality of multiplexors
being independently controllable by the processor for independent control of the connections provided by each of the plurality
of multiplexors;

wherein the processor is configured:
to detect when a USB device is coupled to a first one of the plurality of hub downstream ports,
to control the select input of a first multiplexor connected to the first hub downstream port so that the first port is connected
to the third port,

to run the USB host stack code,
to enumerate the USB device,
charge the USB device using a custom electrical handshake;
charge the USB device using a custom message-based handshake;
obtain a product ID (PID) and a vendor ID (VID) from the USB device,
use the PID and the VID to determine a custom battery charging protocol for the USB device,
and cause the USB hub to charge the USB device a specific battery charging protocol corresponding to the USB device, the specific
battery charging protocol one of the custom electrical handshake and the custom message-based handshake.

US Pat. No. 9,786,779

HIGH VOLTAGE DOUBLE-DIFFUSED MOS (DMOS) DEVICE AND METHOD OF MANUFACTURE

MICROCHIP TECHNOLOGY INCO...

1. A method of controlling a double diffused metal oxide semiconductor (DMOS) transistor including a base implant region formed
in a substrate, a source region formed in the base implant region comprising a highly doped source implant, a drain region
formed in the substrate comprising a highly doped drain implant, a floating gate, a stepped control gate extending over the
base implant region and over the floating gate, a control gate electrode electrically coupled to the stepped control gate,
a floating gate electrode electrically coupled to the floating gate, an oxide layer above said floating gate and said stepped
control gate, a first vertical opening in the oxide layer filled with a conductive material to provide for a source electrode
contacting said source region, a second vertical opening in the oxide layer filled with a conductive material to provide for
a drain electrode contacting said drain region, and wherein the highly doped source implant and the highly doped drain implant
are implanted through the first vertical opening and the second vertical opening, respectively, the method comprising:
applying a voltage to the floating gate via the floating gate electrode, thereby influencing a breakdown voltage and a source-drain
resistance of the DMOS transistor.

US Pat. No. 9,785,263

TOUCH SCREEN STYLUS WITH FORCE AND/OR ANGLE SENSING FUNCTIONALITY

MICROCHIP TECHNOLOGY INCO...

1. A handheld stylus, comprising:
a handheld body;
an outer ring coupled to or integral with the body;
a tip arranged radially inside of the outer ring and spaced apart from the outer ring to be movable with respect to the outer
ring, the tip being movably coupled to the body such that the tip is movable relative to the outer ring and in an axial direction
in response to forces applied to the tip; and

a plurality of capacitive sensors defined between the outer ring and the tip, the plurality of capacitive sensors arranged
in two rows spaced apart from each other in the axial direction, each of the plurality of capacitive sensors configured to
detect a respective capacitance during an interaction between the handheld stylus and a display device; and

a processor configured to:
calculate, based on the respective capacitances detected by the plurality of capacitive sensors arranged spaced apart from
each other in the axial direction, relative movements between the tip and the outer ring along the axial direction resulting
from forces applied to the tip;

calculate, based on the respective capacitances detected by the plurality of capacitive sensors, stylus state data including
at least one of (a) an angle of the stylus relative to the display device or (b) a magnitude of force on the stylus tip; and

communicate the calculated stylus state data to the display device to control a visual parameter of markings generated on
the display device based on the calculated stylus state data.

US Pat. No. 9,739,669

TEMPERATURE SENSOR PERIPHERAL HAVING INDEPENDENT TEMPERATURE COEFFICIENT AND OFFSET ADJUSTMENT PROGRAMMABILITY

MICROCHIP TECHNOLOGY INCO...

1. A circuit arrangement for measuring a temperature and producing a voltage representative thereof, comprising:
first and second voltage-to-current converters each having a single voltage input, a current adjust input and a current output;
a first operational amplifier having first and second inputs and an output;
a first programmable resistor coupled to the current adjust input of the first voltage-to-current converter, wherein the first
resistor adjusts a value of a first current from the current output thereof;

a second programmable resistor coupled to the current adjust input of the second voltage-to-current converter, wherein the
second resistor adjusts a value of a second current from the current output thereof;

a third resistor coupled between the output and the second input of the first operational amplifier;
the outputs of the first and second voltage-to-current converters and the second input of the first operational amplifier
are coupled together;

a first reference voltage coupled to the voltage input of the first voltage-to-current converter;
a second reference voltage coupled to the voltage input of the second voltage-to-current converter;
a third reference voltage provided by a digital to analog converter (DAC), wherein the third reference voltage is coupled
to the first input of the operational amplifier;

wherein a third current through the third resistor is equal to the second current minus the first current.

US Pat. No. 9,753,070

EVALUATION METHOD AND EVALUATION DEVICE FOR A CAPACITIVE CONTACT SENSOR

MICROCHIP TECHNOLOGY INCO...

21. An evaluation method for a capacitive contact sensor, wherein the capacitive contact sensor is configured to evaluate
an alternating electric field generated by the capacitive contact sensor, wherein a sensor electrode generates a measurement
signal, and wherein from the measurement signal a reference signal is formed, and at least one detection signal is generated,
when the reference signal meets at least one detection criterion;
wherein the measurement signal is low-pass filtered and wherein following the low-pass filtering of the measurement signal
a difference signal between the measurement signal and the low-pass filtered measurement signal is formed, wherein the difference
signal constitutes the reference signal.

US Pat. No. 9,660,535

METHOD AND SYSTEM TO DYNAMICALLY POSITION A SWITCH MODE POWER SUPPLY OUTPUT VOLTAGE

MICROCHIP TECHNOLOGY INCO...

1. A power supply circuit, comprising:
a pulse width modulation controller coupled with a flyback circuit, wherein the flyback circuit comprises a primary circuit
comprising a primary winding of a flyback transformer connected in series with a first field effect transistor controlled
by the pulse width modulation controller and a secondary circuit comprising a second field effect transistor connected in
series with an output capacitor wherein the series connected second field effect transistor and output capacitor are connected
in parallel with a secondary winding of the flyback transformer, wherein the pulse width modulation controller controls the
first field effect transistor and the second field effect transistor synchronously to said first field effect transistor to
generate a desired output voltage through the flyback transformer, wherein the pulse width modulation controller further comprises
an input receiving a dimming control signal and wherein a load is coupled with the output capacitor and a load current is
regulated using an error amplifier, comparator and a latch, wherein another input of the latch is used to terminate a pulse
width modulated current pulse through said load asynchronously to generate a square wave pulse current, and

a shunt resistor coupled between ground and a node of the series connected second field effect transistor and the output capacitor,
wherein a voltage across the shunt resistor is measured by the pulse width modulation controller.

US Pat. No. 9,672,909

MEMORY CELL RETENTION ENHANCEMENT THROUGH ERASE STATE MODIFICATION

MICROCHIP TECHNOLOGY INCO...

10. A system for managing a resistive memory cell having binary values of 0 and 1, comprising:
a circuit configured to determine the status of the resistive memory cell;
electronics storing a resistance threshold value for the memory cell, wherein the memory cell is identified by the circuit
as erased having a 0 value if a detected resistance of the memory cell is above the resistance threshold value and identified
by the circuit as programmed having a 1 value if the detected resistance of the memory cell is below the resistance threshold
value; and

control electronics configured to:
form the resistive memory cell from a virgin state of the resistive memory cell having no filament formed therein and having
a maximum resistance value of the memory cell, wherein forming the resistive memory cell comprises forming a filament across
an electrolyte switching region of the resistive memory cell by applying an electrical charge, wherein the memory cell having
the formed filament has a first resistance below the resistance threshold value;

erase the memory cell by partially shrinking the filament to define an erased state having a 0 value and having a second resistance
greater than the first resistance and above the resistance threshold value, but substantially less than the maximum resistance
value of the memory cell;

program the memory cell to a quasi-erased state having a 0 value and having a third resistance between the first and second
resistances, and above the resistance threshold value such that the memory cell is identified by the circuit as erased;

maintain the memory cell in the quasi-erased state until a reprogramming of the memory cell; and
program the memory cell to a programmed state having a 1 value and having a fourth resistance between the first and third
resistances, and below the resistance threshold value such that the memory cell is identified by the circuit as programmed.

US Pat. No. 9,584,153

EFFICIENT DITHERING TECHNIQUE FOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS

MICROCHIP TECHNOLOGY INCO...

9. A system, comprising:
a multi-level digital-to-analog converter;
a variable resolution quantizer;
a random sequence generator coupled to the variable resolution quantizer to generate a random sequence for determining resolution
of the variable resolution quantizer;

wherein an average uniform quantization function is provided by switching between an N-level quantizer function and an N?1
level quantizer function.

US Pat. No. 9,568,526

NOISE DETECTION AND CORRECTION ROUTINES

MICROCHIP TECHNOLOGY INCO...

1. A method for reducing noise in a sensor measurement system, comprising:
performing capacitive to digital conversion measurements
from a sampling waveform, detecting that the sensor measurement system is experiencing noise,
in response to a detection that the sensor measurement system is experiencing noise, dynamically modifying the sampling waveform
by changing one or more delays before performing the sampling waveform again.

US Pat. No. 9,569,375

UNIFYING CLASS DEVICE INTERFACE WITH ONE HOST INTERFACE BY USING EMBEDDED CONTROLLER

MICROCHIP TECHNOLOGY INCO...

1. A system for communicating between a host and a plurality of peripheral devices, the system comprising:
a plurality of class drivers on the host, wherein each of the class drivers implements functionality associated with one or
more of the plurality of peripheral devices;

a plurality of miniport drivers on the host, wherein each miniport driver provides an interface by which one or more of the
class drivers communicate with one or more of the plurality peripheral devices using class protocols, wherein the miniport
drivers communicate through a single host interface supported by the host; and

an embedded controller that interfaces with the plurality of peripheral devices using the respective native bus protocols
of the peripheral devices and wherein the embedded controller interfaces with the plurality of miniport drivers using the
single host interface.

US Pat. No. 9,542,009

KNOB BASED GESTURE SYSTEM

MICROCHIP TECHNOLOGY INCO...

1. A gesturing apparatus, comprising:
a base;
a ball rotationally attached to the base;
a shaft having a first end coupled to the ball;
a first target attached at a location of the shaft toward the first end thereof;
a second target attached to and is disposed around the shaft toward a second end thereof;
a first plurality of capacitive sensor elements disposed around the shaft toward to the first end thereof, wherein the first
target varies a capacitance of at least one of the capacitive sensors of the first plurality of capacitive sensors depending
on a distance between the first target and the at least one of the capacitive sensors; and

a second plurality of capacitive sensor elements disposed around the shaft toward to the second end thereof, wherein the second
target varies capacitances of the second plurality of capacitive sensors depending on a distance between the second target
and respective capacitive sensors of the second plurality of capacitive sensors,

wherein when the shaft is rotated substantially perpendicular to the base, the first target is proximate to at least one of
the first plurality of capacitive sensor elements, wherein the at least one of the first plurality of capacitive sensor elements
changes capacitance value that is used in determining rotation position of the shaft, and

wherein when the shaft is tilted away from being substantially perpendicular to the base, the second target is closer to at
least one of the second plurality of capacitive sensor elements, wherein the at least one of the second plurality of capacitive
sensor elements changes capacitance value that is used in determining tilt position of the shaft;

a third plurality of capacitive sensor elements disposed around the shaft and located between the first and second plurality
of capacitive sensor elements; an elastic foam allows motion of the shaft toward or away from the base, wherein the first
target is proximate to the third plurality of capacitive sensor elements, wherein the third plurality of capacitive sensor
elements changes capacitance value that is used in determining rotation position of the shaft and position toward or away
from the base; a knob attached to the second end of the shaft; a control stick attached to the second end of the shaft; a
biasing element for biasing the shaft into a perpendicular position, wherein the biasing element is a spring, wherein the
knob can be pushed against a force applied by the spring, wherein the control stick can be pushed against a force applied
by the spring, wherein ratiometric changes of the capacitance of the first and third capacitive sensor elements determine
a vertical position of the first target; a digital processor coupled with the plurality of capacitive sensor elements, wherein
the digital processor embedded in a microcontroller comprising an analog front end coupled with the capacitive sensor elements,
and wherein the analog front end comprises a capacitance measurement circuit generating a voltage proportional to a measured
capacitance, wherein the capacitive measurement unit comprising a capacitive voltage divider.

US Pat. No. 9,496,887

ANALOG TO DIGITAL CONVERTER WITH INTERNAL TIMER

MICROCHIP TECHNOLOGY INCO...

15. An analog-to-digital converter, comprising:
circuitry for receiving an analog input and converting the input to a digital signal; and
non-transitory control circuitry configured for:
receiving a sampling time;
receiving a conversion time;
determining a power up time from at least one sleep mode; and
causing the analog-to-digital converter to enter into the at least one sleep mode if the sum of the power up time and conversion
time is less than the sampling time.

US Pat. No. 9,233,300

SYSTEM TO DELIVER PRIORITIZED GAME AUDIO WIRELESSLY WITH A MINIMAL LATENCY

MICROCHIP TECHNOLOGY INCO...

1. A system to deliver prioritized game audio wirelessly with a minimal latency, comprising:
a game console, having a game audio signal as a stereo audio signal;
a game controller, electrically connected to the game console, used to control the game audio signal;
a wireless audio transmitter, with a first antenna, electrically connected to the game console, used to take the game audio
signal from the game console and generate a corresponding radio signal from the game audio signal; and

a wireless gaming headphone, with a second antenna, wirelessly connected to the game console, used to receive wirelessly the
corresponding radio signal from the wireless audio transmitter;

wherein the game audio signal is separated as two components:
a background music track (BGM) and
a digital command for sound effects (SFX), the background music track is processed as a low-priority game audio to be played
with a delay around 40 ms and the digital command for sound effects is processed as a high-priority game audio to be played
with a delay from 10 ms to 20 ms.

US Pat. No. 9,865,814

RESISTIVE MEMORY CELL HAVING A SINGLE BOTTOM ELECTRODE AND TWO TOP ELECTRODES

MICROCHIP TECHNOLOGY INCO...

1. An array of resistive memory structures, each memory structure comprising:
a bottom electrode formed on a substrate;
an oxide region formed on top of the bottom electrode
and deforming a top surface of the bottom electrode such that the bottom electrode has a pointed tip region proximate the
oxide region;

a first electrolyte region and first top electrode formed over a first portion of the pointed tip region of the bottom electrode,
with the first electrolyte region arranged between the first top electrode and the first portion of the pointed tip region
of the bottom electrode to define a first memory element; and

a second electrolyte region and second top electrode over a second portion of the pointed tip region of the bottom electrode,
with the second electrolyte region is arranged between the second top electrode and the second portion of the pointed tip
region of the bottom electrode to define a second memory element.

US Pat. No. 9,733,693

COMBINED POWER SUPPLY AND INPUT/OUTPUT SYSTEM WITH BOOST CAPABILITY

MICROCHIP TECHNOLOGY INCO...

1. A combined power and input/output system, comprising:
a host system comprising a switch configured to switch current from a source to a host line;
a target system operably coupled to the host system via the host line, wherein the host line provides power and data;
a power boost circuit in the target system configured to generate a supply voltage from a signal received on the host line,
wherein the host system is configured to drive the host line to charge a power supply capacitor of the target system in a
first mode; and

wherein the host system is further configured to alternately connect and disconnect the power boost circuit with the source
via said switch to charge and discharge the power supply capacitor when driving the host line during a communication in a
second mode, wherein the power supply capacitor is charged to a voltage higher than a voltage provided by the host system.

US Pat. No. 9,754,133

PROGRAMMABLE DEVICE PERSONALIZATION

MICROCHIP TECHNOLOGY INCO...

1. A semiconductor device, wherein the semiconductor is configured to operate in a general purpose mode in which its operation
is identical to a generic commercially available semiconductor device and is further configurable to operate in a second mode
different from said general purpose mode and wherein the semiconductor device comprises:
a secure memory configured to store a programmable key, the secure memory inaccessible to read operations external to the
semiconductor device;

a programming interface for programming the programmable key in the secure memory;
a plurality of configurable features of the semiconductor device that are associated with the programmable key, each configurable
feature having a set of multiple selectable configurations;

wherein:
when said programmable key is programmed, the semiconductor device operates in the second mode wherein a value of the programmable
key defines a selection of one of the multiple configurations for each of the configurable features;

the programmable key comprises a plurality of sub-keys, wherein each sub-key includes information defining one of the plurality
of configurable features, the configurable features comprises at least a pinout, a peripheral set availability and other settings
of the semiconductor device;

a value of each sub-key defines a selection of one of the multiple configurations for the configurable feature associated
with said each sub-key;

in the general purpose mode, the semiconductor device has a predefined pinout configuration;
in the second mode, when an associated sub-key of the programmable key for defining a pinout configuration is programmed,
the semiconductor device has pinout configuration which is different from said predefined pinout configuration, the pinout
configurations defining assignment of external pins in the semiconductor device for communication of a microcontroller to
a peripheral device;

in the general purpose mode, communication operation of the semiconductor device having the predefined pinout configuration
with external devices is identical to another commercially available semiconductor device;

in the second mode, communication operation of the semiconductor device having a particular pinout configuration with the
external devices is different from the general purpose mode according to the value of the programmable key utilized as an
encryption key.

US Pat. No. 9,673,868

WIRELESS DOOR LOCK POWER TRANSFER SYSTEM HAVING COMMUNICATIONS CAPABILITIES

MICROCHIP TECHNOLOGY INCO...

1. An apparatus for transferring power wirelessly to a door lock, comprising:
a first electric inductor shaped as a coil, adapted to receive a first portion of a door locking bolt and installed in a door
frame;

a power transmitter having an alternating current (AC) output coupled to the first electric inductor and an input coupled
to a first power source;

a second electric inductor shaped as a coil that surrounds the door locking bolt and is installed in a door;
a power receiver having an input coupled to the second electric inductor and an output for providing a second power source;
and

a door frame transceiver and a door transceiver for communicating between the door frame and the door, wherein:
the door frame transceiver is coupled to the power transmitter and modulates the AC output thereof for reception by the door
transceiver through the second inductor; and

the door transceiver is coupled to the power receiver, wherein the power receiver modulates a load on the second inductor
that is detected by the door frame transceiver through the first inductor.

US Pat. No. 9,665,204

CONTINUOUS CIRCLE GESTURE DETECTION FOR A SENSOR SYSTEM

MICROCHIP TECHNOLOGY INCO...

1. A method for detecting a continuous circle gesture, comprising
receiving a sequence of vectors representative of an object movement by a object detection unit, wherein the received sequence
of vectors comprises measurement values mk(i) of electrodes i at times k;

determining from the received sequence of vectors a sequence of velocity vectors or an approximation thereof;
estimating an angle between subsequent velocity vectors; and
determining a rotation direction, wherein the rotation direction is determined by a sign of the angle.