US Pat. No. 9,306,552

HIGH VOLTAGE MAXIMUM VOLTAGE SELECTOR CIRCUIT WITH NO QUIESCENT CURRENT

Linear Technology Corpora...

1. A maximum voltage selection circuit comprising:
multiple inputs, each for receiving a different input voltage;
an output for delivering the highest of the input voltages; and
a voltage selection circuit that:
automatically selects the input having the largest voltage magnitude;
automatically delivers the voltage at the selected input to the output; and
does not draw quiescent operating current from any of the inputs,
wherein for each and every unique combination of two of the multiple inputs, the voltage selection circuit comprises:
an enhancement mode FET with a channel connected in series between a first input of the unique combination of the two inputs
and the output, the enhancement mode FET also having a gate;

a connection between the gate of the enhancement mode FET and the second input of the unique combination of the two inputs
through the channel of a depletion mode FET;

an additional enhancement mode FET with a channel connected in series between the second of the unique combination of the
two inputs and the output, the additional enhancement mode FET having a gate; and

a connection between the gate of the additional enhancement mode FET and the first of the unique combination of the two inputs
through the channel of an additional depletion mode FET.

US Pat. No. 9,331,709

ANALOG-TO-DIGITAL CONVERTER

LINEAR TECHNOLOGY CORPORA...

1. An analog-to-digital converter system comprising:
a capacitive digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither
value; and

a control circuit comprising a scrambler circuit for selectively permutating bit values of digital codes applied to the capacitive
digital-to-analog converter; the control circuit configured to sequentially apply a plurality of digital codes to the capacitive
digital-to-analog converter during an analog-to-digital conversion operation to derive an encoded numerical representation
of the combination of the analog signal value and the analog dither value.

US Pat. No. 9,337,731

POWER CONVERTER FOR GENERATING BOTH POSITIVE AND NEGATIVE OUTPUT SIGNALS

LINEAR TECHNOLOGY CORPORA...

1. A power converting system responsive to an input signal to produce an output signal regulated with respect to the input
signal, the system comprising:
an input node for receiving the input signal,
an output node for producing the output signal,
a first inductive element having a first node coupled to the input node,
a second inductive element having a first node coupled to the output node,
a first switching element coupled to a second node of the first inductive element,
a second switching element coupled directly between the first node of the first inductive element and a second node of the
second inductive element,

a first capacitive element coupled between the second node of the first inductive element and the second node of the second
inductive element, and

a control circuit for controlling the first switching element, the control circuit being configured to set a duty cycle of
the first switching element to a first value for providing the output signal of a first polarity in response to the input
signal of the first polarity, and to set the duty cycle of the first switching element to a second value for providing the
output signal of a second polarity in response to the input signal of the first polarity.

US Pat. No. 9,231,611

ANALOG-TO-DIGITAL CONVERTER

LINEAR TECHNOLOGY CORPORA...

1. An analog-to-digital converter system comprising:
a sampling digital-to-analog converter configured to sample an analog value and to provide a representation of a residue of
the sampled analog value with respect to a digital code;

a plurality of registers configured to store codes representing weighting factors of the sampling digital-to-analog converter
measured to account for variations in a manufacturing process;

a control circuit configured to derive and apply a first digital code to the sampling digital-to-analog converter during an
analog-to-digital conversion operation, the control circuit comprising a mismatch-shaping encoder configured to selectively
permutate bit values of a code to derive the first digital code; and

a digital circuit configured to combine bit values of the first digital code with codes stored in the plurality of registers
to derive a digital output code representing an analog signal value.

US Pat. No. 9,325,250

METHOD AND SYSTEM FOR POLARITY INDEPENDENT STEP-UP CONVERTER CAPABLE OF OPERATING UNDER ULTRA-LOW INPUT VOLTAGE CONDITION

Linear Technology Corpora...

1. A voltage step-up converter comprising:
an input source having a variable polarity;
a single step-up transformer including a primary winding and two secondary windings, wherein the primary winding is coupled
to the input source;

a first depletion mode transistor coupled at its first terminal to the input source and at its second terminal to a reference
point; and

a second depletion mode transistor coupled at its first terminal to the primary winding and at its second terminal to the
reference point;

a coupling capacitor between the first depletion mode transistor and a second winding of the secondary winding; and
a second coupling capacitor between the second depletion mode transistor and a first winding of the secondary winding,
wherein the step-up converter is polarity independent.

US Pat. No. 9,596,728

MAINTAINING OUTPUT CAPACITANCE VOLTAGE IN LED DRIVER SYSTEMS DURING PWM OFF TIMES

Linear Technology Corpora...

1. A light emitting diode (LED) driver system comprising:
a control signal input configured to receive a control signal;
a pulse-width modulation (PWM) input configured to receive a PWM signal;
a driver having a first input coupled to the PWM input, a second input coupled to the control signal input, a third input
configured to receive an LED current sense signal, a fourth input configured to receive a first feedback signal, and a differential
output, wherein the driver is configured to deliver a level of current indicated by the control signal, to a light emitting
diode (LED) load when the PWM signal is ON and stop delivering the level of current when the PWM signal is OFF;

an output capacitance element coupled across the differential output of the driver; and
a first feedback path coupled between the differential output of the driver and the fourth input of the driver, wherein the
first feedback path has a store circuit configured to:

store an information indicative of a first voltage level across the output capacitance element as a stored feedback reference
signal just after the PWM signal is turned OFF; and

cause the voltage across the output capacitance element to be at the first voltage level just before the PWM signal is turned
ON.

US Pat. No. 9,209,981

POWER OVER ETHERNET ON DATA PAIRS AND SPARE PAIRS

Linear Technology Corpora...

1. A Power over Ethernet (PoE) system comprising:
Power Sourcing Equipment (PSE) selectably connectable to a set of data wire pairs and to a set of spare wire pairs in an Ethernet
system for providing a PoE voltage over at least the data wire pairs;

a Powered Device (PD) connected to the PSE by at least the data wire pairs to receive the PoE voltage; and
a PSE controller as part of the PSE, the PSE controller comprising:
a first output port (OUT1);
a second output port (OUT2);
a first switch control port coupled to a first switch, the first switch selectively coupling the PoE voltage to the data wire
pairs;

a second switch control port coupled to a second switch, the second switch selectively coupling the OUT1 to the OUT2; and
processing circuitry configured for performing the method comprising:
keeping the first switch and the second switch off during a detection and classification routine, performed via the OUT1 and
the OUT2;

performing the detection and classification routine to determine if the PoE voltage should be applied to both the data wire
pairs and the spare wire pairs, or to only the data wire pairs, or to neither the data wires pairs or the spare pairs;

keeping the second switch off while turning on the first switch to supply the PoE voltage to only the data wire pairs if it
is determined that the PoE voltage should only be provided to the data wire pairs; and

turning on the second switch and the first switch to supply the PoE voltage to both the data wire pairs and the spare wire
pairs if it is determined that the PoE voltage should be provided to both the data wire pairs and the spare wire pairs.

US Pat. No. 9,374,105

CONVERTING TIME-ENCODED SIGNAL INTO ANALOG OUTPUT

LINEAR TECHNOLOGY CORPORA...

1. A converter comprising:
an input port for receiving a time-encoded signal having an encoding parameter that characterizes time intervals separating
transitions between states;

a time-encoded to digital converter coupled to the input port that determines a numerical value by evaluating a relationship
between the encoding parameter and a timebase; and

a digital to analog converter coupled to the time-encoded to digital converter that receives a digital representation of the
numerical value and generates an analog output representative of the time-encoded signal.

US Pat. No. 9,330,283

HIGH-FREQUENCY RMS-DC CONVERTER USING CHOPPER-STABILIZED SQUARE CELLS

Linear Technology Corpora...

1. An RMS-to-DC converter receiving an input signal and providing a converter output signal, comprising:
a chopper-stabilized square cell receiving the input signal and a feedback signal to provide the converter output signal;
a feedback circuit receiving the converter output signal and providing the feedback signal to the chopper-stabilized square
cell; and

a variable gain amplifier that amplifies the converter output signal of the chopper-stabilized square cell, wherein the feedback
circuit adjusts a gain of the variable gain amplifier.

US Pat. No. 9,054,727

ANALOG-TO-DIGITAL CONVERTER SYSTEM AND METHOD

LINEAR TECHNOLOGY CORPORA...

1. An analog-to-digital converter system comprising:
a sampling digital-to-analog converter configured to provide a sampled representation of a first analog value comprising a
portion of an analog signal value and a portion of an analog dither value;

a dither generator circuit configured to apply a digital dither code to the sampling digital-to-analog converter at a sampling
instance; and

a control circuit configured to derive a first digital code to represent the first analog value; the control circuit further
configured to combine the first digital code and the digital dither code to derive an encoded numerical representation of
the analog signal value;

wherein the dither generator circuit is configured to be responsive to a preceding digital code derived during a preceding
analog-to-digital conversion operation to represent an analog value.

US Pat. No. 9,337,792

TRIMMING GAIN AND CMMR IN DIFFERENCE AMPLIFIER

LINEAR TECHNOLOGY CORPORA...

1. A multistage amplifier comprising:
a multistage amplifier circuit that has multiple transconductance input stages, each of which has differential inputs and
an adjustable tail current input that controls the amount of the transconductance of the input stage;

a resistive voltage divider network that controls the closed loop gain of the multistage amplifier circuit and that comprises
multiple resistors that provide different voltage divider ratios at different points, each point being connected to one of
the transconductance input stages,

wherein adjustment of tail currents at the tail current inputs controls the degree to which each point affects the closed
loop gain of the multistage amplifier, and

at least one of the following lettered limitations:
A. an adjustable tail current generator circuit that generates the tail currents in an adjustable manner, wherein the sum
of the transconductances of the input stages remains substantially the same, notwithstanding adjustments to the adjustable
tail currents by the adjustable tail current generator circuit, and wherein the adjustable tail current generator circuit
includes at least one differential pair of transistors; or

B. wherein the multistage amplifier is a difference amplifier; wherein adjustment of the tail currents at the tail current
inputs also simultaneously controls the common mode rejection ratio of the difference amplifier; wherein adjustment of the
tail currents at the tail current inputs also controls the gain of the difference amplifier; wherein the differential inputs
of each of the transconductance input stages are connected to each of the sets of three resistors; and the first set of resistors
provides a feedback path in the difference amplifier; and one of the following parenthetically numbered limitations:

(1) the second of the set of resistors provides a feed forward path in the difference amplifier; the first set of resistors
has a first, second, and third resistor, the first resistor being connected at one end to a negative input of the difference
amplifier and at the other end to one end of the second resistor, the other end of the second resistor being connected to
one end of the third resistor, and the other end of the third resistor being connected to an output of the difference amplifier;
the second set of resistors has a fourth, fifth, and sixth resistor, the fourth resistor being connected at one end to a positive
input of the difference amplifier and at the other end to one end of the fifth resistor, the other end of the fifth resistor
being connected to one end of the sixth resistor, and the other end of the sixth resistor being connected to a reference voltage;
one of the differential inputs to a first of the transconductance input stages is connected to the junction between the first
and the second resistors; the other differential input to the first of the transconductance input stages is connected to the
junction between the fifth and the sixth resistors; one of the differential inputs to a second of the transconductance input
stages is connected to the junction between the second and the third resistors; and the other differential input to the second
of the transconductance input stages is connected to the junction between the fourth and the fifth resistors; or

(2) the first set of resistors has a first, second, third, and fourth resistor, the first resistor being connected at one
end to a negative input of the difference amplifier and at the other end to one end of the second resistor, the other end
of the second resistor being connected to one end of the third resistor, the other end of the third resistor being connected
to one end of the fourth resistor, the other end of the fourth resistor being connected to an output of the difference amplifier;
the second set of resistors has a fifth, sixth, seventh, and eighth resistor, the fifth resistor being connected at one end
to a positive input of the difference amplifier and at the other end to one end of the sixth resistor, the other end of the
sixth resistor being connected to one end of the seventh resistor, the other end of the seventh resistor being connected to
one end of the eighth resistor, the other end of the eighth resistor being connected to a reference voltage; one of the differential
inputs to a first of the transconductance input stages is connected to the junction between the first and the second resistors;
the other differential input to the first of the transconductance input stages is connected to the junction between the sixth
and the seventh resistors; one of the differential inputs to a second of the transconductance input stages is connected to
the junction between the third and the fourth resistors; the other differential input to the second of the transconductance
input stages is connected to the junction between the sixth and the seventh resistors; one of the differential inputs to a
third of the transconductance input stages is connected to the junction between the second and the third resistors; the other
differential input to the third of the transconductance input stages is connected to the junction between the seventh and
eighth resistors; one of the differential inputs to a fourth of the transconductance input stages is connected to the junction
between the second and the third resistors; and the other differential input to the fourth of the transconductance input stages
is connected to the junction between the fifth and the sixth resistors; or

C. the multistage amplifier is a single-ended input amplifier.

US Pat. No. 9,488,997

POWER OVER ETHERNET SYSTEM WHERE POWER SOURCING EQUIPMENT DETECTS ACTUAL VOLTAGE AT POWERED DEVICE

Linear Technology Corpora...

1. A system comprising:
Power Sourcing Equipment (PSE) providing combined data and voltage over wires, the PSE having a variable voltage source for
generating a voltage for transmission on the wires after powering up of the PSE, the wires having a resistance;

a Powered Device (PD) connected to the PSE by at least the wires to receive the data and voltage;
test circuitry in the PSE that generates information relating to an actual voltage drop between the PSE and the PD, due to
resistance in the wires, during a testing phase prior to the variable voltage source powering the PD; and

compensation circuitry in the PSE coupled to the variable voltage source, the compensation circuitry configured to control
the variable voltage source, after the testing phase while the PD is being powered by the variable voltage source, based on
a current through the wires to compensate for an actual voltage drop along the wires due to the resistance in the wires so
that a voltage provided at the PD is approximately a predetermined voltage.

US Pat. No. 9,077,244

EXPANDING DC/DC CONVERTER INTO MULTIPHASE DC/DC CONVERTER

LINEAR TECHNOLOGY CORPORA...

1. A DC/DC converter for converting an input DC signal at an input node of the converter into an output DC signal at an output
node of the converter, comprising:
a primary switcher configured as a single-phase converter, the primary switcher including a primary power stage coupled between
the input node and the output node, and having at least one primary power switch responsive to the input DC signal for producing
the output DC signal, and a controller for producing a switch drive signal for controlling the primary power switch to produce
the output DC signal at a desired level,

multiple secondary power stages coupled between the input node and the output node for producing the output DC signal, each
of the multiple secondary power stages having at least one secondary power switch responsive to the input DC signal for producing
the output DC signal, and

an expander system coupled to the primary switcher for enabling the controller of the single-phase converter to control the
secondary power stages for operation in a multiphase DC/DC conversion mode,

the expander system being responsive to the switch drive signal of the controller for producing a master drive signal to form
multiple slave drive signals for respectively controlling secondary power switches in the multiple secondary power stages,
the slave drive signals having phases shifted with respect to the master drive signal and with respect to each other,

the expander system responsive to a difference between sensed values of output current in the primary power stage and a secondary
power stage for adjusting a slave drive signal for a respective secondary power switch so as to modify duty cycles of the
secondary power switches based on the sensed values of output current.

US Pat. No. 9,484,799

SWITCHED CAPACITOR DC-DC CONVERTER WITH REDUCED IN-RUSH CURRENT AND FAULT PROTECTION

Linear Technology Corpora...

1. A circuit for controlling a switched capacitor DC/DC converter to generate an output voltage Vout comprising:
a controller circuit for generating control signals for controlling switches in the switched capacitor DC/DC converter to
generate Vout;

an input terminal for an input voltage Vin1;

an input current sensor for generating an input current signal corresponding to an input current;
a current limit circuit coupled to the input current sensor for detecting when the input current has reached a current limit
level and for controlling in-rush current into the converter so as not to exceed the current limit level, wherein the current
limit circuit controls the in-rush current so as not to exceed a predetermined maximum current level;

a series transistor coupled between the input terminal and the converter;
a series transistor controller for controlling the series transistor to limit the in-rush current into the converter to the
current limit level during start-up when Vin1 is applied to the input terminal;

a fault detection circuit comprising:
a first fault circuit for detecting whether there is an input current fault or a Vout fault during a start-up phase of the
circuit and for turning off the series transistor if a fault is detected during the start-up phase; and

a second fault circuit for detecting whether there is an input current fault or a Vout fault during a steady state phase of
the circuit and for turning off the series transistor if a fault is detected during the steady state phase.

US Pat. No. 9,077,374

RESOLUTION-BOOSTED SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER

Linear Technology Corpora...

1. An analog-to-digital converter (ADC) receiving an analog signal as input and providing an output digital value representative
of the analog signal, comprising:
a first multiplexer receiving two or more reference signals to provide a selected reference signal;
a sigma delta modulator receiving the selected reference signal and the analog signal to provide a set of pulses representative
of the analog signal received;

a control circuit causing the first multiplexer to select (i) in a first phase of a conversion, a first one of the reference
signals as the selected reference signal and (ii) in subsequent phases of the conversion, the other reference signals, one
at a time, as the selected reference signal, such that the sigma delta modulator provides, respectively, a first set of pulses
in the first phase and an additional set of pulses in each of the subsequent phases of the conversion; and

a digital circuit combining in each conversion the first set and the subsequent sets of pulses to provide the digital output
value.

US Pat. No. 9,306,531

EXPONENTIAL ROM TABLE TUNING USING TRIM FOR FREQUENCY AGILE ANALOG FILTERS

Linear Technology Corpora...

1. A tunable and trimmable analog filter comprising:
a tunable analog filter that:
sets the frequency of a characteristic of the tunable analog filter based on a digital tuning signal that is indicative of
a desired frequency of the characteristic;

and
contains components having values that deviate from specified values due to variations during manufacture of the tunable analog
filter, the value deviations causing the frequency of the characteristic not to precisely match the frequency indicated by
the digital tuning signal; and

a trimming circuit that:
includes a non-volatile memory that contains data;
receives tuning information indicative of a desired frequency for the characteristic of the tunable analog filter; and
generates the digital tuning signal by trimming the tuning information to compensate for the deviations in component value
and by using the data contained within the non-volatile digital memory,

wherein:
the non-volatile digital memory includes an input and an output and wherein the data causes the output to substantially be
an exponential function of its input, or

the tunable analog filter is an RC filter and the tuning information is based on the natural logarithm of a constant divided
by the desired frequency, or

the tunable analog filter is a gm/C filter and the tuning information is based on the natural logarithm of a constant divided
by the desired frequency, or

the tunable analog filter is a poly-phase tunable analog filter, the poly-phase tunable analog filter has a CppI input that
receives a CppI digital tuning signal that causes the frequency of a CppI characteristic of the tunable analog filter to be
set by the CppI digital tuning signal that is indicative of the frequency of the characteristic and a CppQ input that receives
a CppQ digital tuning signal that causes the frequency of a CppQ characteristic of the tunable analog filter to be set by
the CppQ digital tuning signal that is indicative of the frequency of the characteristic; and the trimming circuit generates
the Cppl and the CppQ digital tuning signals by trimming the tuning information to compensate for the deviations in component
value and by using the data contained within the non-volatile digital memory.

US Pat. No. 9,287,002

BOOTSTRAP SAMPLING CIRCUIT WITH ACCURATELY AVERAGING PRE-CHARGE CIRCUIT

LINEAR TECHNOLOGY CORPORA...

1. A sampling circuit comprising:
a sampling capacitor;
an electronic sampling switch that:
has a control input that controls whether the electronic sampling switch is in a sample state or a hold state;
connects the sampling capacitor to an input signal while in the sample state; and
disconnects the sampling capacitor from the input signal while in the hold state;
a switch controller that:
controls the control input to the electronic sampling switch so as to cause the electronic sampling switch to be in the sample
state during one period and the hold state during another period;

while in the sample state, causes the impedance of the electronic sampling switch that is seen by the input signal to be substantially
independent of the voltage of the input signal;

includes a pre-charge circuit that pre-charges the control input to the electronic sampling switch prior to each commencement
of the sample state to approximately the average of the voltage of the input signal and the voltage on the sampling capacitor
immediately prior to each commencement of the sample state, the amount of the pre-charging being substantially independent
of the voltage of the input signal,

wherein
the electronic sampling switch includes a sampling field effect transistor (FET),
the control input is the gate of the sampling FET,
the pre-charge circuit includes two pre-charge FETs,
only while the control input to the electronic sampling switch is being pre-charged:
one of the pre-charge FETs is turned on and closes a current path between the input signal and the gate; and
the other pre-charge FETs is turned on and closes a current path between the input signal and the sampling capacitor;
the current path between the input signal and the gate includes a resistor; and
the current path between the input signal and the sampling capacitor includes a resistor.

US Pat. No. 9,152,158

LINEAR REGULATOR IC WITH VERSATILE GROUND PIN

Linear Technology Corpora...

1. A voltage regulator comprising:
a current source having a first terminal coupled to a reference voltage terminal and a second terminal coupled to a voltage
input (Vin) terminal, the reference voltage terminal for being connected to a component for creating a reference voltage;

an amplifier having a first input terminal coupled to receive the reference voltage, the amplifier having a second input terminal
coupled to an output voltage (Vout) terminal for receiving an output voltage of the regulator;

the amplifier having a first power supply terminal coupled to the Vin terminal;
the amplifier having a second power supply terminal; and
an output circuit controlled by an output of the amplifier for causing an output voltage at the Vout terminal to substantially
equal the reference voltage,

the second power supply terminal being configured to allow a user to couple the second power supply terminal to either the
Vout terminal, system ground, or another voltage in order to provide a sufficient voltage across the first power supply terminal
and the second power supply terminal during operation to allow the amplifier to operate properly to achieve output voltage
regulation.

US Pat. No. 9,305,700

AUTO RESONANT DRIVER FOR WIRELESS POWER TRANSMITTER SENSING REQUIRED TRANSMIT POWER FOR OPTIMUM EFFICIENCY

Linear Technology Corpora...

1. A power transmission system for wirelessly supplying power to a load comprising:
a transmitter inductor;
a transmitter capacitor connected to the transmitter inductor to create a tank circuit having a resonant frequency;
a first switch coupled to a first node of the tank circuit and to a first voltage to cause the tank circuit to be intermittently
charged;

a second switch coupled to the first node of the tank circuit and to a second voltage to cause the tank circuit to be intermittently
discharged; and

a feedback circuit for switching the power switch, the feedback circuit comprising:
a first comparator coupled to the first voltage and to the first node and having a first comparator output terminal;
a second comparator coupled to the second voltage and to the first node and having a second comparator output terminal;
a latch having a first latch input terminal coupled to the first comparator output terminal;
the latch having a second latch input terminal coupled to the second comparator output terminal; and
a latch output terminal automatically generating switching signals for the first switch and the second switch at the resonant
frequency,

wherein the first comparator, second comparator, and latch are configured such that positive and negative currents flow through
the inductor as the first switch and the second switch are switched, wherein,

a. at a negative to positive inductor current transition while the second switch is on, the first node goes from above the
second voltage to below the second voltage, triggering the second comparator and the latch and turning on the first switch,
wherein,

b. at a positive to negative inductor current transition while the first switch is on, the first node goes from below the
first voltage to above the first voltage, triggering the first comparator and the latch and turning on the second switch,
and wherein,

c. steps a and b repeat.

US Pat. No. 9,256,570

I2C ISOLATED, BIDIRECTIONAL COMMUNICATION SYSTEM WITH ISOLATED DOMAIN CURRENT SOURCE PULL-UPS

LINEAR TECHNOLOGY CORPORA...

1. A communication system containing two or more communication interface devices for communicating between separate I2C busses, a communication interface device of the two or more communication interface devices comprising:
a current source internal to the communication interface device, the current source being connected to one of the I2C buses and arranged to pull the one I2C bus to a logic high level in the absence of an active pull down device on the one I2C bus;

a pull down component connected to the one I2C bus arranged to pull down the one I2C bus to a logic low level; and

a detector configured to detect when a remote communication interface device is pulling the signal level on the one I2C bus to a logic low level meeting the I2C specification at the same time as the communication interface device is pulling the signal level on the one I2C bus to a valid logic low meeting the I2C specification, wherein the detector includes a comparator arranged to compare the ratio of current in the pull down component
to the total current supplied by the current source.

US Pat. No. 9,236,840

LINEAR BROADBAND PNP AMPLIFIER

Linear Technology Corpora...

1. A differential amplifier, comprising:
a differential pair comprising a first transistor and a second transistor, and a first current source and a second current
source, the first current source and second current source providing a collector-emitter current of the first transistor and
a collector-emitter current of the second transistor, respectively;

a first trans-linear loop and a second trans-linear loop coupled to a base terminal and an emitter terminal of the first transistor
and a base terminal and an emitter terminal of the second transistor, respectively, wherein each trans-linear loop comprises:

a third transistor, a fourth transistor and a fifth transistor, connected such that a corresponding one of the first transistor
and the second transistor, the third transistor, the fourth transistor and the fifth transistor form a closed loop of base-emitter
junctions; and

a third current source, wherein a current in a corresponding one of the first current source and the second current source
and a current in the third current source are provided in substantially the same ratio as an area of the emitter terminal
of the corresponding one of the first transistor and the second transistor to an area of an emitter terminal of the fifth
transistor; and

a first feedback loop and a second feedback loop coupled to the base and the emitter terminals of the first transistor and
the base and the emitter terminals of the second transistor, respectively, wherein each feedback loop comprising a sixth transistor
having a base terminal connected to a collector terminal of the fifth transistor of the corresponding one of the first trans-linear
loop and the second trans-linear loop and a collector terminal connected to an emitter terminal of the fourth transistor of
the corresponding one of the first trans-linear loop and the second trans-linear loop.

US Pat. No. 9,078,317

FLOATING OUTPUT VOLTAGE BOOST REGULATOR DRIVING LEDS USING A BUCK CONTROLLER

Linear Technology Corpora...

1. A current regulator system for driving a string of light emitting diodes (LEDs) with a regulated current comprising:
a first switch having a first terminal coupled to receive a positive input voltage Vin, relative to ground, from a power supply,
the first switch having a second terminal coupled to a first end of an inductor;

a rectifier having a first terminal coupled to the second terminal of the first switch, the rectifier having a second terminal
outputting a negative voltage ?Vee relative to ground;

a second end of the inductor coupled to ground;
an LED load coupled between the positive input voltage Vin and the negative voltage ?Vee such that approximately a voltage
equal to Vin+Vee is applied across the LED load; and

a controller connected to detect a current through the LED load and control a switching duty cycle of the first switch, at
a switching frequency, to regulate the LED current to substantially match a target current.

US Pat. No. 9,188,477

RADAR SYSTEM AND METHOD FOR PROVIDING INFORMATION ON MOVEMENTS OF OBJECT'S SURFACE

Linear Technology Corpora...

1. A system for producing an output signal representing movement of an object's surface, comprising:
a continuous wave (CW) signal source for producing an CW signal directed at the object's surface, the CW signal being produced
at a first frequency,

a receiving element for receiving a signal reflected from the object's surface when the CW signal hits this surface, and
a down-converting frequency mixer for converting the received signal into a signal of a second frequency lower than the first
frequency, the frequency mixer being configured to produce an output signal representing an AM component of the received signal
and having a parameter representing movement of the object's surface,

wherein the frequency mixer comprises a local oscillator (LO) port for receiving a coherent LO injection from the CW signal
source to produce the output signal representing the AM component of the received signal, and

an amplitude of the output signal corresponding to an amplitude of the AM component of the received signal represents movement
of the object's surface.

US Pat. No. 9,166,473

DC/DC POWER CONVERTER WITH FEEDBACK CONTROL OPERABLE IN LINEAR AND NON-LINEAR MODES

LINEAR TECHNOLOGY CORPORA...

1. A current mode power conversion system that operates in cycles, each cycle including an on time and an off time, the system
including an inductor having a set point current and a control loop that regulates measured inductor current to equal the
set point current and connected to store energy during the on time of each cycle and use the energy during the off time of
each cycle, the system providing a stable output voltage and a maximum limited output current to a load during constant load
conditions, the system comprising:
a feedback control linearly operable so as to control the output voltage across the load during constant load conditions,
and non-linearly operable so as to control the output voltage across the load during certain detected changes in the inductor
current set point so as to speed up the transient response of the power conversion system, the feedback control including:

a circuit for producing a first signal as a function of a difference between a reference voltage and a signal proportional
to the output voltage, the first signal representing the inductor current set point,

a circuit for producing a derivative signal representing the derivative of the first signal, and a transient detector configured
for detecting a change in the set point current of the inductor, wherein the feedback control is responsive to the transient
detector for switching from linear operation to nonlinear operation when a threshold detector detects a change in the inductor
current set point that has a magnitude that exceeds the threshold.

US Pat. No. 9,069,368

LIGHT LOAD STABILITY CIRCUITRY FOR LDO REGULATOR

Linear Technology Corpora...

1. A linear regulator circuit for generating a regulated output voltage comprising:
an error amplifier having differential inputs, including a first input and a second input;
the first input being connected to a reference voltage, and the second input corresponding to an output voltage of the regulator,
the regulator being controlled to cause the voltage at the second input to substantially equal the voltage at the first input;

a bipolar pass transistor connected between an input voltage and a load;
a driver circuit coupled between an output of the error amplifier and a base of the pass transistor; and
an AC-coupled feedback circuit comprising:
a bipolar feedback transistor having a base coupled to the base of the pass transistor;
an emitter resistor coupled to the emitter of the feedback transistor;
a collector resistor coupled to the collector of the feedback transistor; and
a feedback capacitor coupled between a collector of the feedback transistor and the output of the error amplifier,
the feedback circuit being configured to increase a phase margin of the regulator at load currents below a certain threshold,
wherein the feedback circuit is substantially ineffectual at load currents substantially above the threshold.

US Pat. No. 9,072,147

PRE-CHARGING INDUCTOR IN SWITCHING CONVERTER TO ACHIEVE HIGH PWM DIMMING RATIO IN LED DRIVERS

Linear Technology Corpora...

1. A method for controlling a regulator for dimming of a light emitting diode (LED) load comprising:
providing a dimming signal having a duty cycle, the dimming signal controlling an LED ON-time and an LED OFF time, the dimming
signal being at a first frequency;

controlling a regulator to supply current to the LED load during the LED ON-time, and to supply no current to the LED load
during the OFF-time, the regulator having an inductor;

detecting an inductor current during a steady-state condition of the regulator during the ON-time to generate a first value
corresponding to the inductor current;

storing the first value during the OFF-time;
pre-charging the inductor to a current level related to the stored first value, prior to a next ON-time of the LED load;
maintaining a control signal in a feedback loop of the regulator substantially constant during the OFF-time; and
upon the dimming signal designating the ON-time, controlling the regulator to again supply current to the LED load, wherein
at a start of the ON-time, the inductor has been pre-charged with a current approximately equal to the inductor current during
the steady-state condition of the regulator so that the current supplied to the LED load at the beginning of an ON-time is
approximately equal to the current supplied to the LED load at the end of the previous ON-time.

US Pat. No. 9,300,307

ARBITRARY PHASE TRAJECTORY FREQUENCY SYNTHESIZER

LINEAR TECHNOLOGY CORPORA...

1. A frequency synthesizer comprising:
a voltage controlled oscillator (VCO) producing at an output thereof a synthesized frequency signal having a frequency controlled
based on a signal received at an input of the VCO;

a digitally adjustable frequency divider coupled to the output of the VCO and producing at an output thereof a reduced frequency
signal from the synthesized frequency signal;

a phase digital-to-analog converter (DAC) receiving a timing signal and a digital control signal, and producing at an output
thereof a delayed version of the timing signal that is delayed according to the digital control signal;

a phase detector (PD) coupled to the output of the digitally adjustable frequency divider, the output of the phase DAC, and
a reference clock, and producing a phase control signal at an output of the PD coupled to the input of the VCO; and

a digital signal converter operative to control the digitally adjustable frequency divider and the phase DAC so as to cause
a phase or frequency of the synthesized frequency signal output by the VCO to track a desired phase or frequency trajectory
encoded in a digital signal received by the digital signal converter.

US Pat. No. 9,197,235

SUPPRESSING DIELECTRIC ABSORPTION EFFECTS IN SAMPLE-AND-HOLD SYSTEMS

LINEAR TECHNOLOGY CORPORA...

1. Sample-and-hold (S/H) circuitry operating in track and hold phases, and comprising:
a first S/H circuit having a first hold capacitor at which a first voltage value is maintained in the hold phase, and
a dielectric absorption (DA)-suppressing circuit connectable to the first hold capacitor for operating the S/H circuitry in
an additional phase after completing the hold phase and before entering the track phase,

the DA-suppressing circuit being configured to supply the first hold capacitor, during an operation in the additional phase,
with a second voltage value which is negatively correlated with the first voltage value.

US Pat. No. 9,134,744

LOW CURRENT DC-DC CONVERTER WITH INTEGRATED LOW CURRENT COULOMB COUNTER

LINEAR TECHNOLOGY CORPORA...

1. A power supply system having an input node and an output node, comprising:
a regulator circuit responsive to an input signal at the input node for producing an output signal at the output node at a
desired level, and having a controller, an inductive element and a first switch coupled to the inductor element and controlled
by the controller to produce the output signal, and

a Coulomb counter for producing a Coulomb count signal proportional to the number of Coulombs passing from the input node
to the output node, the Coulomb counter being enabled by an enabling signal representing a predetermined time period, for
determining the number of Coulombs passing from the input node to the output node during the predetermined time period.

US Pat. No. 9,182,428

SWITCHED CAPACITANCE VOLTAGE DIFFERENTIAL SENSING CIRCUIT WITH NEAR INFINITE INPUT IMPEDANCE

LINEAR TECHNOLOGY CORPORA...

1. A voltage sensing circuit for sensing a differential voltage across two nodes that each have a non-zero common mode voltage,
the voltage sensing circuit comprising:
a voltage differential sensing circuit configured to sense the differential voltage across the two nodes that each have the
non-zero common mode voltage, the voltage differential sensing circuit having a positive input impedance that is imposed across
the nodes when the voltage sensing circuit is connected to the nodes; and

an impedance compensation circuit configured to generate a compensation current that is delivered to the two nodes that substantially
cancels the loading effect of the positive input impedance on the two nodes.

US Pat. No. 9,176,163

ANEMOMETER DETECTING THERMAL TIME CONSTANT OF SENSOR

Linear Technology Corpora...

1. A method for analyzing fluid flow comprising:
a. applying power to cause a temperature of a diode junction to change from a first temperature to a second temperature, wherein
the diode junction is a base-emitter junction of a bipolar transistor, the transistor having an emitter, base, and collector,
wherein applying the power comprises:

controlling a first switch to couple a power supply to the collector of the transistor to supply a first current between the
collector and the emitter to heat the diode junction to the second temperature; and

controlling a second switch to couple the base to a first driving signal for driving the transistor to conduct the first current
between the collector and the emitter;

b. reducing the power by controlling first switch and the second switch to cease driving the transistor to conduct the first
current after heating the diode junction to the second temperature, reducing the power causing the temperature of the diode
junction to change from the second temperature toward the first temperature at an exponential rate, the rate corresponding
to a time constant, where the time constant is related to a fluid flow interacting with the diode junction;

c. coupling a current source to the base of the transistor by at least one measurement control switch, while the temperature
of the diode junction changes from the second temperature toward the first temperature, to drive the diode junction at a current
while coupling a voltage drop across the diode junction to an analog-to-digital converter (ADC), an output of the ADC being
coupled to a digital processor;

d. measuring a changing voltage drop across the diode junction at various times by the digital processor as the temperature
changes from the second temperature toward the first temperature; and

e. correlating the time constant to fluid flow by the digital processor.

US Pat. No. 9,250,638

VOLTAGE REGULATOR SLEEP CONTROL IN DROPOUT MODE

LINEAR TECHNOLOGY CORPORA...

1. A switching regulator for converting an input voltage at an input node to a regulated output voltage at an output node,
comprising:
an inductive element,
a switch coupled to the inductive element and controlled to produce the regulated output voltage, and
an input-output comparator configured for comparing a difference between the input voltage and the output voltage, and producing
a first sleep signal for placing the regulator into a sleep mode when the regulator is operating in a dropout mode and the
difference between the input voltage and the output voltage becomes less than a first predetermined value, the sleep mode
being a mode during which the switch is open and not regulating the output voltage and during which power used by circuitry
internal to the switching regulator, other than the switch and inductor, is cut or reduced, thereby causing this other internal
circuitry to operate with no more than only a very low quiescent current.

US Pat. No. 9,246,383

SYSTEM AND METHOD FOR INPUT VOLTAGE REGULATION OF SWITCH MODE SUPPLIES IMPLEMENTING BURST MODE OPERATION

Linear Technology Corpora...

1. A switching regulator that supplies output current at a regulated voltage level to a load, the switching regulator being
operable in a burst mode, the switching regulator comprising:
an input node;
an output node coupled to the load;
a switch mode power supply coupled to the load; and
a control circuit coupled between the input node and the switch mode power supply, wherein the control circuit is configured
to determine when to enter burst mode, in which switching elements of the switch mode power supply provide output current
to the load on an intermittent aperiodic basis, based on a voltage at the input node that is below a predetermined threshold
level and at least one of (i) a current at the input node or (ii) the output current being below a predetermined current threshold.

US Pat. No. 9,106,202

POLY-PHASE FILTER WITH PHASE TUNING

Linear Technology Corpora...

1. A poly-phase filter, comprising:
terminals for receiving inphase input signals I and ?, and quadrature input signals Q and Q;
terminals for providing inphase output signals Iout and Iout, and quadrature output signals Qout and Qout,

variable resistors connecting across the terminals for receiving inphase input signal I, quadrature input signal Q, inphase
input signal ?, and quadrature input signal Q, and the terminals for providing inphase output signal Iout, quadrature output signal Qout, inphase output signal Iout, and quadrature output signal Qout, respectively; and

variable capacitors connecting across the terminals for receiving inphase input signal I, quadrature input signal Q, inphase
input signal ?, and quadrature input signal Q, and the terminals for providing quadrature output signal Qout, inphase output signal Iout, quadrature output signal Qout, and inphase output signal Iout, respectively, wherein each adjustment that increases or decreases the capacitance of each variable capacitor connected to
the terminals providing inphase output signals Iout, and Iout correspondingly decreases or increases by an equal amount the capacitance of each variable capacitor connected to the terminals
providing quadrature output signals Qout and Qout.

US Pat. No. 9,448,960

ADDRESS TRANSLATION IN I2C DATA COMMUNICATIONS SYSTEM

LINEAR TECHNOLOGY CORPORA...

1. A readdressing circuit for providing data communications over a data line and a clock line between at least one master
device and multiple slave devices, comprising:
a data input node for receiving a data signal transferred over the data line and including an address word produced by the
master device,

a data output node coupled to the multiple slave devices,
an address generator for storing a multi-bit fixed offset value, the address generator being responsive to the address word
at the data input node for generating multiple unique addresses for the multiple slave devices and providing the translated
address immediately to the data output node without requiring extra clock cycles, and

an address transmit detection circuit for allowing the multiple unique addresses to be provided at the data output node when
the address word is detected at the data input node, and for preventing an output signal of the address generator from being
supplied to the data output node when the address word is not detected at the data input node.

US Pat. No. 9,374,050

LEVEL-SHIFTING AMPLIFIER

LINEAR TECHNOLOGY CORPORA...

1. A differential amplifier that, when connected to a positive or negative supply voltage and to a ground voltage, provides
a differential pair of outputs signals at a differential output that are an amplification of a differential pair of input
signals at a differential input, comprising:
a differential input stage that receives the differential pair of input signals from the differential input and that includes
a first transistor associated with one of the input signals and a second transistor associated with the other input signal;
and

a differential output stage that generates the differential pair of output signals at the differential output and that includes
a third transistor associated with one of the output signals and a fourth transistor associated with the other output signal,

wherein the first, second, third, and fourth transistors are all P type or all N type, and
wherein the differential pair of output signals has a common mode that is:
near the ground voltage when the first, second, third, and fourth transistors are all N type and the supply voltage is positive
with respect to the ground voltage;

near the supply voltage when the first, second, third, and fourth transistors are all P type and the supply voltage is positive
with respect to the ground voltage;

near the ground voltage when the first, second, third, and fourth transistors are all P type and the supply voltage is negative
with respect to the ground voltage; or

near the supply voltage when the first, second, third, and fourth transistors are all N type and the supply voltage is negative
with respect to the ground voltage.

US Pat. No. 9,172,364

ISOLATED BOOTSTRAPPED SWITCH

Linear Technology Corpora...

13. An input sampling network receiving a differential signal across a first analog input terminal and a second analog input
terminal, comprising:
an analog to digital converter having a first input terminal and a second input terminal;
a first and second bootstrapped switch circuits each selectably coupling the first analog input terminal of the input sampling
network to the first input terminal of the analog-to-digital converter; and

third and fourth bootstrapped switch circuits each selectably coupling the second analog input terminal of the input sampling
network to the second input terminal of the analog-to-digital converter, wherein one or more of the first, second, third and
fourth bootstrapped switch circuits (i) are coupled to a timing circuit that provides one or more clock signals, (ii) each
have an input terminal and an output terminal, and (iii) each comprise:

a switch having a first terminal coupled to the input terminal of the input terminal of the corresponding bootstrapped switch
circuit, a second terminal coupled to the output terminal of the corresponding bootstrapped switch circuit, and a control
terminal;

a charge pump coupled to the clock signals and isolated from the timing circuit via a first capacitor and a second capacitor,
the charge pump generating an output voltage; and

a logic circuit coupled to the clock signals and isolated from the timing control circuit via a third capacitor and a fourth
capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from
the output voltage of the charge pump.

US Pat. No. 9,397,668

SYSTEM AND METHOD FOR PROVIDING PROGRAMMABLE SYNCHRONOUS OUTPUT DELAY IN A CLOCK GENERATION OR DISTRIBUTION DEVICE

Linear Technology Corpora...

1. A clock frequency division circuit, which receives a delay value, a synchronization signal, and an external clock signal
of a given frequency, comprising:
a decode circuit receiving the delay value and providing a set of initial count values;
one or more counters each (a) being associated with a corresponding programmable divisor, (b) receiving an input clock signal
derived from the external clock signal and a corresponding one of the initial count values, and (c) providing a frequency
divided output signal that has a frequency that is the given frequency divided by the corresponding programmable divisor,
wherein, subsequent to detecting a transition in the synchronization signal, each counter provides a transition in the respective
frequency divided output signal after a time period represented by the corresponding initial count value; and

a synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal
that enables the frequency divided output signal to be output after expiration of the initial count value.

US Pat. No. 9,391,577

LOW-VOLTAGE ANALOG VARIABLE GAIN AMPLIFIER WITH ENHANCED LINEARITY

Linear Technology Corpora...

1. A variable gain amplifier comprising:
a first transistor having a control terminal, a first current handling terminal, and a second current handling terminal, the
first transistor receiving at its control terminal a first input voltage for modulating a current through the first transistor,
the second current terminal providing an output current of the first transistor;

a first resistance having a first terminal coupled to the first current handling terminal of the first transistor; and
a first MOSFET having a control terminal, a first current handling terminal and a second current handling terminal, wherein
the second current handling terminal of the first MOSFET is coupled to a second terminal of the first resistance, and wherein
the first current handling terminal of the first MOSFET is coupled to ground,

the first MOSFET receiving at its control terminal a combined bias voltage and a signal proportional to the first input voltage.

US Pat. No. 9,377,794

RAPID POWER UP OF POWER OVER ETHERNET EQUIPMENT SYSTEM

Linear Technology Corpora...

1. A system comprising:
Power Sourcing Equipment (PSE) providing combined data and voltage over wires, the PSE having a voltage source for generating
a voltage for transmission on the wires after powering up of the PSE; and

a Powered Device (PD) connected to the PSE by at least the wires to receive the data and voltage,
wherein the PSE contains a memory that stores information identifying that the PD is able to receive the voltage over the
wires for powering the PD,

wherein the PSE contains a controller,
wherein, when the PSE is powered up, the controller is configured to access the information stored in the memory and, based
on the information, control the PSE to supply the voltage to the wires to power the PD,

wherein the system is a Power Over Ethernet system, and wherein the controller is configured to perform an abbreviated PoE
detection and classification routine, detecting a power requirement of the PD, each time the PSE is powered up.

US Pat. No. 9,240,718

ACCURATE CURRENT SENSING IN H-BRIDGE APPLICATIONS WITHOUT AMPLIFIER HAVING HIGH COMMON MODE REJECTION RATIO

LINEAR TECHNOLOGY CORPORA...

1. A current sensing circuit comprising:
a shunt resistance through which current to be sensed travels;
a first differential amplifier that provides an amplified output of the voltage across the shunt resistance;
a second differential amplifier that provides an amplified output of the voltage across the shunt resistance and that is not
the first differential amplifier; and

a switching system that delivers a current sensing signal output based on:
the amplified output of the first differential amplifier and not the amplified output of the second differential amplifier
when the common mode voltage of the shunt resistance is low; and

the amplified output of the second differential amplifier and not the amplified output of the first differential amplifier
when the common mode voltage of the shunt resistance is high.

US Pat. No. 9,312,815

BROADBAND INTEGRATED RF/MICROWAVE/MILLIMETER MIXER WITH INTEGRATED BALUN(S)

LINEAR TECHNOLOGY CORPORA...

1. A broadband radio frequency, microwave, or millimeter mixer system comprising:
a balun that has:
an unbalanced port;
a balanced port;
a first and a second inductor tightly and inversely magnetically coupled to one another; and
a third inductor which is not magnetically coupled to the first or the second inductors; and
a mixer connected to the balanced port of the balun,
wherein the balun, including its three inductors, and the mixer are all integrated onto a single substrate that forms an integrated
circuit.

US Pat. No. 9,178,427

FLOATING OUTPUT VOLTAGE BOOST-BUCK REGULATOR USING A BUCK CONTROLLER WITH LOW INPUT AND LOW OUTPUT RIPPLE

Linear Technology Corpora...

1. A circuit having a converter coupled to drive a floating load comprising:
an input terminal for receiving an input voltage Vin;
a first inductor having a first end for being coupled to ground;
a first switch coupled to a second end of the first inductor for coupling the second end to the input voltage when the first
switch is in an on-state to charge the first inductor;

a rectifier coupled to the second end of the first inductor for electrically coupling the second end of the first inductor
to a first terminal of the load when the first switch is in an off-state, wherein the converter generates a voltage VEE at
the first terminal during steady state operation;

a first capacitor coupled between the input voltage and the first terminal of the load, wherein a voltage across the first
capacitor equals Vin-VEE, where VEE is a negative voltage with respect to ground at the first terminal of the load;

a second inductor having a first end coupled to the second end of the first inductor at least during a time when the first
switch is in its on-state, wherein the load is coupled between a second end of the second inductor and the first capacitor;
and

a controller coupled to receive a first feedback signal corresponding to an instantaneous current through the first inductor
when the first switch is on, and the controller coupled to receive a second feedback signal corresponding to a load current
or load voltage,

wherein the controller controls at least the first switch to regulate a peak current through the first inductor to regulate
the load current or load voltage.

US Pat. No. 9,104,418

LOW POWER TIMING, CONFIGURING, AND SCHEDULING

LINEAR TECHNOLOGY CORPORA...

1. A device for executing a sequence of configuration steps for an integrated radio transmitter or receiver, the device comprising:
an initiating circuit generating timing trigger signal;
a memory storing a sequence of configuration steps;
a microsequencer configured to retrieve configuration steps of the sequence from the memory and to execute the retrieved configuration
steps; and

a microprocessor configured to perform one or more operations selected from the group consisting of: configure the microsequencer,
load the memory with the sequence of configuration steps, trigger the microsequencer to begin executing the sequence, and
execute instructions based upon an output signal of the microsequencer,

wherein the microsequencer consumes less power when executing the sequence of configuration steps than the microprocessor
consumes when executing the sequence of configuration steps.

US Pat. No. 9,116,048

CIRCUITS FOR AND METHODS OF ACCURATELY MEASURING TEMPERATURE OF SEMICONDUCTOR JUNCTIONS

LINEAR TECHNOLOGY CORPORA...

1. An analog system for providing at a system output an analog output signal proportional to the absolute temperature of a
semiconductor junction, the system comprising:
an analog preprocessing stage comprising a variable offset buffer and resistance extraction circuit; wherein the variable
offset buffer is configured and arranged so as to process an analog signal from the semiconductor junction so as to produce
an analog preprocessed signal including a resistance error term stored in the resistance extraction circuit; and

an analog temperature to voltage converter stage for converting the analog preprocessed signal to an analog voltage proportional
to absolute temperature representing the absolute temperature of the semiconductor junction;

wherein the system is configured and arranged so as to extract the resistance error term as a function of three analog excitation
currents of different values I1, I2 and I3 applied in a measurement cycle sequentially through the semiconductor junction, and produce at least one instantly resistance
error free analog signal representative of the semiconductor junction temperature as a function of two of the excitation currents
I1 and I2 and independent of excitation current I3.

US Pat. No. 9,419,807

PD IN POE SYSTEM HAVING REDUNDANT PSE CHANNEL INPUTS

Linear Technology Corpora...

1. A Power Over Ethernet (PoE) system, the PoE system being configured to deliver operating power to a load in a Powered Device
(PD) via data lines, the PoE system comprising:
a Powered Device (PD) having a first channel and a second channel, the first channel comprising a first wire pair, the second
channel comprising a second wire pair, the PD further comprising:

a first PD controller having input terminals coupled to the first wire pair, the first PD controller being configured to perform
hand-shaking with a first Power Sourcing Equipment (PSE) coupled to the first channel to identify to the first PSE that a
first PoE voltage is to be provided on the first channel, the first PD controller having a first Power Good (PWRGD) terminal
for issuing a first PWRGD signal upon the first PoE voltage being detected on the first channel;

a second PD controller having input terminals coupled to the second wire pair, the second PD controller being configured to
perform hand-shaking with a second PSE coupled to the second channel to identify to the second PSE that a second PoE voltage
is to be provided on the second channel, the second PD controller having a second PWRGD terminal for issuing a second PWRGD
signal upon the second PoE voltage being detected on the second channel;

a first PWRGD switch controlled by the first PD controller, the first PWRGD switch being connected in series with a first
wire in the first wire pair, the first PWRGD switch being controlled to be closed upon the first PD controller issuing the
first PWRGD signal;

a second PWRGD switch controlled by the second PD controller, the second PWRGD switch being connected in series with a second
wire in the second wire pair, the second PWRGD switch being controlled to be closed upon the second PD controller issuing
the second PWRGD signal;

a rectifying bridge coupled between the first PD controller and a regulating power supply, and coupled between the second
PD controller and the regulating power supply;

a first current load in the first channel drawing at least a minimum current needed to cause the first PSE to continue to
supply the first PoE voltage to the first channel when the first PWRGD switch is closed and when the load is not drawing a
current from the first channel;

a first auxiliary switch connected in series with the first PWRGD switch between the first PD controller and the rectifying
bridge; and

a second auxiliary switch connected in series with the second PWRGD switch between the second PD controller and the rectifying
bridge,

the first auxiliary switch and the second auxiliary switch being controlled by the first PWRGD signal and the second PWRGD
signal to be in opposite states when one or both of the first PWRGD signal and the second PWRGD signal are issued,

the first auxiliary switch and the second auxiliary switch being controlled by the first PWRGD signal and the second PWRGD
signal to be both open when neither the first PWRGD signal nor the second PWRGD signal is issued,

wherein only one of the first channel or the second channel is coupled to the rectifying bridge when the first PSE is supplying
the first PoE voltage and the second PSE is supplying the second PoE voltage.

US Pat. No. 9,472,304

CONFIGURING SIGNAL-PROCESSING SYSTEMS

Linear Technology Corpora...

1. A configurable signal-processing circuit that provides a plurality of selectable signal-processing operations, the configurable
signal-processing circuit comprising a configuration circuit to detect an externally applied timing pattern for inputting
an input signal and outputting an output signal to and from the configurable signal processing-processing circuit, the configuration
circuit providing a configuration code responsive to the timing pattern that selects a first signal-processing operation from
among the plurality of selectable signal-processing operations.

US Pat. No. 9,431,319

EXPOSED, SOLDERABLE HEAT SPREADER FOR INTEGRATED CIRCUIT PACKAGES

LINEAR TECHNOLOGY CORPORA...

1. An integrated circuit package comprising:
a semiconductor die that contains an electronic circuit and exposed electrical connections to the electronic circuit;
a thermally-conductive heat spreader having a first outer surface and a second outer surface substantially parallel to the
first outer surface, the first outer surface being affixed to all portions of a silicon side of the semiconductor die in a
thermally-conductive manner; and

non-electrically conductive, encapsulation material completely encapsulating the semiconductor die and the heat spreader,
except for the second outer surface of the heat spreader which is solderable and forms part of an exterior surface of the
integrated circuit package,

wherein:
the integrated circuit package is an embedded die package;
the semiconductor die is an embedded die;
the semiconductor die includes a circuit side that is substantially parallel to the silicon side;
the integrated circuit package further includes at least one electroplated electrical connection to the circuit side of the
semiconductor die; and

the at least one electroplated electrical connection is electrically connected entirely through an electroplated or sputtered
conductive routing layer to a terminal in the exterior surface of the integrated circuit package that includes the second
outer surface of the heat spreader, the terminal including a leadframe terminal exposed from the encapsulation material at
a portion of the exterior surface of the integrated circuit package and a portion of sidewalls of the integrated circuit package.

US Pat. No. 9,348,347

VOLTAGE GENERATOR WITH CURRENT SOURCE COMPENSATED FOR AN ERROR CURRENT OPERABLE OVER A WIDE VOLTAGE RANGE

Linear Technology Corpora...

1. A circuit comprising:
a first current source generating a first current and having an output terminal, a first voltage being generated at the output
terminal;

a set resistance coupled to the output terminal of the first current source, wherein a voltage drop across the set resistance
generates a reference voltage for setting a target output level of a regulator;

the output terminal also being connected to a control terminal of a transistor that introduces a first error current, wherein
the first error current offsets the first voltage from a target first voltage; and

a correction circuit connected to a second terminal of the first current source, the correction circuit generating a second
current approximately equal to the first error current, which modifies the first current to compensate for the first error
current so as to cause the first voltage to be approximately the target first voltage,

wherein operation of the correction circuit is not dependent on a magnitude of the first voltage.

US Pat. No. 9,270,190

PREDICTIVE AND REACTIVE CONTROL OF SECONDARY SIDE SYNCHRONOUS RECTIFIERS IN FORWARD CONVERTERS

Linear Technology Corpora...

6. A forward converter comprising:
a primary side containing a pulse width modulation (PWM) controller for controlling switching of a power switch at a duty
cycle to achieve a regulated output voltage of the converter;

a transformer having a primary winding, connected to the power switch, and a secondary winding;
a secondary side coupled to the primary side via the transformer, the secondary side including a forward transistor and a
catch transistor;

the secondary side including a secondary side switch controller that controls switching of the forward transistor and the
catch transistor without communication from the primary side, the secondary side switch controller comprising:

a first circuit coupled to a first end of the secondary winding and detecting rising and falling edges of a first voltage
at the first end of the secondary winding, the rising and falling edges corresponding to the turning on and turning off of
the power switch, the first circuit generating a first digital signal upon a rising edge of the first voltage and generating
a second digital signal upon a falling edge of the first voltage;

a second circuit receiving the first digital signal and the second digital signal, the second circuit turning on the catch
transistor upon detecting the second digital signal, the second circuit turning off the catch transistor a predetermined period
of time prior to detecting the first digital signal for each cycle such that the catch transistor is turned off prior to the
power switch being turned on,

wherein the second circuit functions to turn on and off the catch transistor during a continuous conduction mode of the converter;
a third circuit for controlling the catch transistor during a discontinuous conduction mode, the third circuit comprising:
a comparator for detecting a voltage across the catch transistor to identify a low load current condition, wherein the comparator
triggers within a first period subsequent to a rising edge of the second digital signal during the low load condition;

a counter configured to count a certain number of rising edges of the first digital signal during an evaluation period; and
logic circuitry coupled to the comparator and the counter, the logic circuit being configured for keeping the catch transistor
off for one or more cycles if it is determined that the comparator is triggered within the first period, evidencing the low
load current condition, and wherein the logic circuit is further configured to allow the catch transistor to be turned on
if the comparator does not trigger within the first period over a predetermined number of rising edges of the first digital
signal during the evaluation period.

US Pat. No. 9,454,168

LDO REGULATOR POWERED BY ITS REGULATED OUTPUT VOLTAGE FOR HIGH PSRR

Linear Technology Corpora...

1. A regulator comprising:
a linear regulator having an input voltage terminal, for receiving an input voltage, and having an output voltage terminal,
for providing a regulated output voltage Vout, the linear regulator comprising:

a first feedback loop comprising a first error amplifier and a reference current source, wherein the error amplifier and reference
current source are powered by an upper rail voltage and a lower rail voltage, wherein the upper rail voltage tracks Vout;

a power transistor coupled between the input voltage terminal and the output voltage terminal, a conductivity of the power
transistor being controlled by an output of the first error amplifier to generate Vout; and

a second feedback loop for generating the upper rail voltage comprising:
a second error amplifier having a first input coupled to receive Vout, an output of the second error amplifier controlling
a first circuit in the second feedback loop for generating the upper rail voltage that tracks Vout.

US Pat. No. 9,246,436

LOW POWER RADIO RECEIVER

LINEAR TECHNOLOGY CORPORA...

1. A wireless receiver comprising:
a first passive mixer having a first input node, a second input node, and at least one output node;
an oscillator coupled to the first input node of the first passive mixer;
a buffer having an output node coupled to the second input node of the first passive mixer, wherein the buffer is configured
to provide isolation from the first passive mixer; and

an antenna operatively connected to an input node of the buffer,
wherein the operative coupling between the antenna and the buffer is passive.

US Pat. No. 9,479,142

PHASE ERROR COMPENSATION CIRCUIT

Linear Technology Corpora...

1. A phase error compensation circuit comprising:
a first transconductance circuit having a differential input and a differential output;
a second transconductance circuit having a differential input and a differential output;
a first multiplier circuit comprising:
a differential control input (VCI);

a second differential input coupled to the differential output of the first transconductance circuit; and
a differential output;
a second multiplier circuit comprising:
a differential control input (VCQ);

a second differential input coupled to the differential output of the second transconductance circuit; and
a differential output;
a first differential load comprising a first load and a second load, together having a differential input coupled to the differential
output of the second multiplier circuit and sharing a common node; and

a second differential load comprising a first load and a second load together having a differential input coupled to the differential
output of the first multiplier circuit and sharing the common node, wherein the first multiplier circuit is configured to
multiply the differential current signal provided by the first transconductance circuit times a first scaling constant provided
at the differential control input of the first multiplier circuit.

US Pat. No. 9,270,133

MONITORING CELLS IN ENERGY STORAGE SYSTEM

LINEAR TECHNOLOGY CORPORA...

1. A system for monitoring an energy storage system composed of multiple cells connected in series, comprising:
a chain of monitors including first and second monitors, the first monitor being configured for monitoring cells in a first
group of the cells in the energy storage system to produce first monitored data, and the second monitor being configured for
monitoring cells in a second group of the cells in the energy storage system to produce second monitored data for delivery
to a controller, the second monitor being further configured for receiving the first monitored data from the first monitor
for delivery to the controller,

a first group of switches, each coupled to a different one of the cells in the first group of cells and controlled by a control
signal produced by the first monitor to control charging of the cell to which the switch is coupled, and

a second group of switches, each coupled to a different one of the cells in the second group of cells and controlled by a
control signal produced by the second monitor to control charging of the cell to which the switch is coupled,

the controller being responsive to monitored data for producing control data identifying at least one of the multiple cells
and instructing the chain of monitors to control charging of the identified cell, the control data being transferred over
the chain of monitors,

the first monitor being further configured to receive the control data from the second monitor and determine whether the identified
cell is one of the cells in the first group of cells,

the second monitor being further configured to receive the control data and determine whether the identified cell is one of
the cells in the second group of cells,

the first monitor producing the control signal to control the switch in the first group of cells that is the identified cell,
if the identified cell is in the first group of cells, and

the second monitor producing the control signal to control the switch in the second group of cells that is the identified
cell, if the identified cell is in the second group of cells.

US Pat. No. 9,496,840

RADIO RECEIVER

LINEAR TECHNOLOGY CORPORA...

1. A radio receiver comprising:
an antenna configured to receive a signal;
a first mixer coupled to the antenna and configured to output a first mixer output signal based on the signal received by
the antenna;

a buffer having a buffer input coupled to an output of the first mixer and configured to output at a buffer output a buffer
signal based on the first mixer output signal; and

a first charge pump coupled to the buffer output and configured to produce a first charge pump output signal based on the
buffer signal.

US Pat. No. 9,351,352

BOOST THEN FLOATING BUCK MODE CONVERTER FOR LED DRIVER USING COMMON SWITCH CONTROL SIGNAL

Linear Technology Corpora...

1. A converter coupled to drive a light emitting diode (LED) load comprising:
an input terminal for receiving an input voltage;
a boost portion of the converter, the boost portion being controlled to supply a boosted voltage higher than the input voltage,
the boost portion comprising:

a first inductor having a first end coupled to the input terminal;
a first switch coupled to a second end of the first inductor for pulling the second end to a low voltage when the first switch
is in an on-state to charge the first inductor;

a first rectifier, coupled between the first switch and a first capacitor, to conduct a current through the first inductor
when the first inductor is discharging while the first switch is in an off-state, the first capacitor being coupled to smooth
a current and for being charged to the boosted voltage;

a buck mode portion of the converter, the buck portion being controlled to supply an output voltage to an LED load that is
less than the boosted voltage, the buck mode portion comprising:

a second inductor, wherein the LED load is coupled between a first end of the second inductor and the first capacitor;
a second switch coupled to a second end of the second inductor to charge the second inductor when the first switch and the
second switch are in an on-state;

a second rectifier, coupled between the second end of the second inductor and the first capacitor, to conduct a current through
the second inductor when the second inductor is discharging while the first switch and the second switch are in an off-state;

a controller receiving a first feedback signal corresponding to a current through the first switch or the second switch in
their on-states, and the controller receiving a second feedback signal corresponding to an LED load current or LED load voltage,

wherein the controller controls the first switch and the second switch to have the same duty cycle and regulates a peak current
through the first switch or the second switch to regulate the LED load current or load voltage,

wherein the controller comprises:
an error amplifier receiving a signal corresponding to a load current or a load voltage, the error amplifier generating a
control voltage corresponding to a switching duty cycle needed to achieve a target load current or load voltage;

a pulse width modulation (PWM) comparator comparing the control voltage to a signal corresponding to an instantaneous current
through the first switch or the second switch;

a switch control circuit coupled to receive an output of the PWM comparator for switching the states of the first switch and
the second switch when a ramping current through the first switch or the second switch crosses the control voltage; and

an oscillator for resetting the first switch and the second switch at a beginning of a switching cycle.

US Pat. No. 9,478,982

POWER SUPPLY SYSTEM AND METHOD

Linear Technology Corpora...

1. A power control system comprising:
an event data bus configured to carry event information;
a plurality of power supply managers, each coupled to the event data bus;
one or more point of load (POL) regulators assigned to each power supply manager, respectively;
wherein each power supply manager is configured to communicate event information with other power supply managers over the
event data bus, and

wherein in a given period, more time slots are allocated on the event data bus the more critical a fault condition is.

US Pat. No. 9,525,351

INDUCTOR CURRENT SENSING IN A BUCK CONVERTER USING MULTIPLE FILTERS

Linear Technology Corpora...

1. A circuit comprising:
at least one switch in a voltage regulator switching at a duty cycle to supply current through an inductor to generate a target
output voltage;

a current sense circuit that generates a current sense signal that is substantially proportional to the current through the
inductor, the current sense circuit comprising:

a first portion detecting the actual current through the inductor, the first portion outputting a signal having a first AC
component and a first DC component;

a first low pass filter passing the first DC component and attenuating the first AC component;
a second portion detecting a substantially rectangular waveform corresponding to the duty cycle of the regulator;
a first high pass filter passing a second AC component of the substantially rectangular waveform and blocking a second DC
component of the substantially rectangular waveform, wherein the second AC component is substantially proportional to a ramping
current through the inductor, and wherein an amplitude of the second AC component is greater than an amplitude of the first
AC component; and

a summing node summing the second AC component, the first DC component, and the first AC component for filtering by the first
low pass filter,

wherein an output of the first low pass filter comprises the first DC component summed with an attenuated second AC component
to provide a signal substantially proportional to the actual current through the inductor with reduced switching noise.

US Pat. No. 9,467,303

CONTROLLER AREA NETWORK BUS TRANSMITTER WITH COMPLEMENTARY SOURCE FOLLOWER DRIVER

Linear Technology Corpora...

1. A driver for a bus, wherein the bus comprises two conductors, the driver comprising:
a main driver comprising:
a first drive MOSFET having a drain coupled to a first conductor of the bus and a source coupled to a first voltage; and
a second drive MOSFET having a drain coupled to a second conductor of the bus and a source coupled to a second voltage lower
than the first voltage,

wherein a first input data state applied to the main driver causes the first drive MOSFET to pull the first conductor towards
the first voltage and causes the second drive MOSFET to pull the second conductor towards the second voltage, and wherein
a second data state applied to the main driver causes the first drive MOSFET and the second drive MOSFET to be off so as to
be high impedances; and

a source follower circuit comprising:
a first source follower MOSFET having a source coupled to the first conductor and a drain coupled to the first voltage; and
a second source follower MOSFET having a source coupled to the second conductor and a drain coupled to the second voltage,
wherein the first input data state applied to the source follower circuit causes the first source follower MOSFET to pull
the first conductor towards the first voltage and causes the second source follower MOSFET to pull the second conductor towards
the second voltage, and wherein the second data state causes the first source follower MOSFET and the second source follower
MOSFET to be off so as to be high impedances,

wherein the first source follower MOSFET and the second source follower MOSFET are controlled to turn on simultaneously with
or prior to the first drive MOSFET and the second drive MOSFET turning on, and

wherein the first source follower MOSFET and the second source follower MOSFET are controlled to turn off simultaneously with
the first drive MOSFET and the second drive MOSFET turning off or after the first drive MOSFET and the second drive MOSFET
have turned off.

US Pat. No. 9,524,824

DRIVER FOR WIRELESS POWER TRANSMITTER SENSING REQUIRED TRANSMIT POWER FOR OPTIMUM EFFICIENCY

Linear Technology Corpora...

1. A power transmission system for wirelessly supplying power to a load comprising:
a transmitter inductor;
a first switch coupled between a voltage source and the transmitter inductor and controlled to generate a varying current
through the transmitter inductor;

a receiver inductor magnetically coupled to the transmitter inductor;
a voltage regulator receiving power from the receiver inductor to generate a regulator output voltage;
a load coupled to an output of the voltage regulator, wherein power in the transmitter inductor is wirelessly coupled to the
receiver inductor for being converted to a regulated voltage by the regulator for driving the load;

a peak voltage detector coupled to detect a peak voltage on the transmitter inductor, wherein a peak voltage on the transmitter
inductor is affected by an ability of the voltage regulator to achieve regulation for driving the load; and

a controller for controlling a peak current through the transmitter inductor, the controller being controlled to modulate
the peak current through the transmitter inductor so as to modulate a peak current through the receiver inductor, wherein
the peak voltage on the transmitter inductor increases during a time when the voltage regulator is able to achieve regulation,

wherein the controller is configured to variably increase and decrease the peak current through the transmitter inductor,
by modulating the peak current through the transmitter inductor, to detect a level of the peak current through the transmitter
inductor that corresponds with the increase of the peak voltage as a result of the voltage regulator achieving regulation,
and

wherein the controller is controlled to temporarily cease modulating the peak current through the transmitter inductor, as
a result of detecting the increase of the peak voltage, to limit the peak current through the transmitter inductor to a level
adequate to supply sufficient voltage to the voltage regulator necessary to achieve regulation.

US Pat. No. 9,627,976

CONTROL ARCHITECTURE WITH IMPROVED TRANSIENT RESPONSE

LINEAR TECHNOLOGY CORPORA...

1. A power interface device comprising:
a main switching converter configured to receive a first voltage at an input terminal and to output a second and different
voltage at an output terminal, the main switching converter including a first main switch, a second main switch, and a main
inductor, wherein the first main switch at one end is coupled to the input terminal and at another end is coupled to a main
node, the second main switch at one end is coupled to the main node and at another end is coupled to a ground terminal, and
the main inductor at one end is coupled to the main node and at another end is coupled to the output terminal;

an auxiliary switching converter coupled in parallel with the main switching converter and configured to receive the first
voltage at the input terminal and to output the second voltage at the output terminal, the auxiliary switching converter including
a first auxiliary switch, a second auxiliary switch, and an auxiliary inductor, wherein the first auxiliary switch at one
end is coupled to the input terminal and at another end is coupled to an auxiliary node, the second auxiliary switch at one
end is coupled to the auxiliary node and at another end is coupled to a ground terminal, and the auxiliary inductor at one
end is coupled to the auxiliary node and at another end is coupled to the output terminal; and

an auxiliary control loop circuit at one end coupled to the output terminal and at another end coupled to the auxiliary switching
converter, the auxiliary control loop circuit configured to detect a transient at the output terminal and responsive to the
transient issue an auxiliary control signal for driving the auxiliary switching converter to output fast transient high frequency
current to the output terminal, wherein:

the auxiliary control loop circuit is configured to prevent a lower frequency component of a transient signal associated with
the transient from entering the auxiliary switching converter by using a resistor and an adder circuit,

the resistor is coupled at one end to the auxiliary inductor and at another end to the adder circuit coupled to the output
terminal, and

the auxiliary switching converter is configured to operate at an auxiliary switching frequency different from a main switching
frequency of the main switching converter.

US Pat. No. 9,571,052

TRANSCONDUCTANCE (GM) BOOSTING TRANSISTOR ARRANGEMENT

LINEAR TECHNOLOGY CORPORA...

1. A circuit for increasing input transconductance comprising:
an input that receives an input voltage;
an input stage that receives the input voltage from the input, the input stage including a field effect transistor (FET) that
is directly connected to the input voltage and that has a gate, source, drain, and body terminal; and

an amplifier that has an input connected to the input voltage and that generates an amplified version of the input voltage
received at the input that is applied to the body terminal of the FET,

wherein application of the amplified version to the body terminal of the FET increases the transconductance of the FET compared
to what it would be in the same circuit without the amplified version being applied to the body terminal of the FET.

US Pat. No. 9,564,820

METHODS AND SYSTEMS FOR CONTROL OF DC-DC CONVERTERS

Linear Technology Corpora...

1. A switching regulator having a primary side and a galvanically isolated secondary side, and configured to provide a regulated
voltage level to a load, the switching regulator comprising:
a transformer having a primary winding on the primary side and a secondary winding on the secondary side;
an input node on the primary side;
an output node on the secondary side and coupled to the load;
a first switch on the primary side configured to control current flow through the primary winding of the transformer;
a first feedback control loop including the input node and configured to regulate a first duty cycle of the first switch to
provide a constant average value at the output node; and

a duty switch in the first feedback control loop having a first terminal coupled to the input node,
wherein the first feedback control loop is responsive only to primary side signal values,
wherein the first feedback loop is configured to use a second duty cycle of the duty switch and a voltage at the input node
to create a replica of the regulated voltage level of the output node, and

wherein the second duty cycle of the duty switch matches the first duty cycle of the first switch.

US Pat. No. 9,535,437

POWER OVER ETHERNET POWER SOURCING EQUIPMENT PROVIDES LOW VOLTAGE OUTPUT FOR INCREASED EFFICIENCY IN LOW POWER MODE

Linear Technology Corpora...

1. A Power Over Ethernet (PoE) system comprising:
Power Sourcing Equipment (PSE) providing data and voltage over Ethernet wires, the PSE having at least one voltage source
for generating at least a first voltage during a first mode of operation and a lower second voltage during a second mode of
operation; and

a Powered Device (PD) having at least one load, the PD being connected to the PSE by at least the Ethernet wires to receive
the data and voltage, the PD having at least one voltage converter for converting at least one of the first voltage and second
voltage to a target voltage for the at least one load,

wherein the at least one voltage converter in the PD comprises a switching voltage regulator and a linear regulator,
wherein, upon a first triggering event occurring, the PSE is configured to provide the first voltage over the Ethernet wires
to power the at least one load in the PD and, upon a second triggering event occurring, the PSE is configured to provide the
second voltage over the Ethernet wires to power the at least one load in the PD.

US Pat. No. 9,859,951

POWER OVER DATA LINES DETECTION AND CLASSIFICATION SCHEME

Linear Technology Corpora...

1. A Power Over Data Lines (PoDL) system comprising:
Power Source Equipment (PSE) coupled to a Powered Device (PD) via a wire pair, wherein differential data signals and DC power
are transmitted over the same wire pair, the PSE comprising a first power source for supplying a first voltage to the PD;

the PD comprising a PD load and comprising a digital communications portion, separate from the PD load, for communicating
over the wire pair;

an alternate power source coupled to the PD load via other than the wire pair, the alternate power source comprising a second
power source generating power independent from the first power source, wherein the second power source is sufficient to fully
power the PD load; and

wherein the alternate power source separately powers the PD load while the PSE separately powers the digital communications
portion in the PD over the wire pair for allowing data communications via the wire pair.

US Pat. No. 9,639,719

CHOPPER-STABILIZED SQUARE CELLS

LINEAR TECHNOLOGY CORPORA...

1. A chopper stabilized square cell receiving a first signal, a second signal and a clock signal, and having a first output
signal and a second output signal, comprising:
a first square cell;
a second square cell, wherein the first and second square cells each receive an input signal and provide an output signal;
an input switch circuit operated by the clock signal to provide the first signal and the second signal in an alternating manner
to the first square cell and the second square cell, such that when the first signal is provided as the input signal to the
first square cell, the second signal is provided as the input signal to the second square cell and when the first signal is
provided as the input signal to the second square cell, the second signal is provided as input signal to the first square
cell; and

an output switch circuit operated by the clock signal to provide the output signal of the first square cell and the output
signal of the second square cell in an alternating manner as the first output signal and the second output signal, such that
when the output signal of the first square cell is provided as the first output signal, the output signal of the second square
cell is provided as the second output signal and when the output signal of the first square cell is provided as the second
output signal, the output signal of the second square cell is provided as the first output signal.

US Pat. No. 9,660,456

SWITCHING OF CONDUCTOR PAIR IN POWER OVER ETHERNET SYSTEM

LINEAR TECHNOLOGY CORPORA...

1. A system for providing power to a powered device (PD) over a cable having four twisted pairs, comprising:
Power Sourcing Equipment (PSE) circuitry,
a first switch for coupling the PSE circuitry to two of the twisted pairs when turned on and for decoupling the PSE circuitry
from the two twisted pairs when turned off, and

a switch control circuit for turning the first switch off to enable the PSE circuitry to perform a prescribed operation in
connection with the PD over only the other two twisted pairs, and for turning the first switch on to enable the PSE circuitry
to perform the prescribed operation in connection with the PD over all four twisted pairs,

wherein the switch control circuitry has a configuration that cause the following sequence:
turns the first switch off;
measures the resistance of the PD while the first switch is off;
stores the resistance measurement;
turns the first switch on;
measures the resistance of the PD while the first switch is on; and
compares the measured resistance of the PD while the first switch is on with the stored measured resistance of the PD while
the first switch was off to determine the number of PD signature circuits the PD has.

US Pat. No. 9,685,933

NOTCH FILTER FOR RIPPLE REDUCTION

Linear Technology Corpora...

1. A circuit comprising:
an input chopper receiving an input signal;
an amplifier receiving a first signal corresponding to an output of the input chopper;
an output chopper, synchronized with the input chopper, receiving a second signal corresponding to an output of the amplifier,
the output chopper comprising a first set of switches controlled by at least clocked phase 1 and phase 2 control signals at a chopping frequency, the output chopper outputting a third signal containing chopping ripple at the chopping
frequency; and

a notch filter coupled to receive the output of the output chopper, the notch filter comprising a sampling capacitor, a hold
capacitor, and a second set of switches between the sampling capacitor and the hold capacitor,

wherein the sampling capacitor is directly coupled to an output of the output chopper with no switches therebetween,
wherein the second set of switches is temporarily closed during each output chopper switch cycle to connect the sampling capacitor
to the hold capacitor, pursuant to a phase 3 control signal at the chopper frequency, to transfer charge from the sampling capacitor to the hold capacitor at least once
per switching cycle of the output chopper, wherein the hold capacitor is isolated from the output chopper during times when
the second set of switches is open, such that the chopping ripple from the output chopper is not transferred to the hold capacitor.

US Pat. No. 9,811,113

SYSTEM AND METHOD FOR SYNCHRONIZATION AMONG MULTIPLE PLL-BASED CLOCK SIGNALS

Linear Technology Corpora...

1. A clock generation system receiving a reference frequency signal and a synchronization signal having a first logic state
and a second logic state, comprising a plurality of clock generators connected in parallel to receive the reference frequency
signal, wherein each clock generator comprises:
a reference frequency divider which receives the reference frequency signal and provides a frequency-divided reference signal;
a phase-locked loop which receives the frequency-divided reference signal and provides a phase-locked signal that is phase-locked
to the frequency-divided reference signal; and

an output frequency divider that receives the phase-locked signal and provides an output signal of a predetermined frequency
that is a function of the frequency of the reference frequency signal, wherein the reference frequency divider is phase-reset
by a transition to the first logic state in the synchronization signal, and wherein the output frequency divider is phase-reset
by a transition to the second logic state following the transition to the first logic state in the synchronization signal.

US Pat. No. 9,658,118

PRECISION TEMPERATURE MEASUREMENT DEVICES, SENSORS, AND METHODS

LINEAR TECHNOLOGY CORPORA...

1. A method for calibrating a first temperature sensor disposed on a substrate, the method comprising:
providing a second temperature sensor on the substrate having the first temperature sensor disposed thereon, wherein the second
temperature sensor is operative to perform temperature measurements based on thermal diffusivity (TD);

obtaining a first temperature measurement using the first temperature sensor, wherein the first temperature sensor is operative
to perform temperature measurements based on characteristics of a semiconductor junction, a bipolar transistor, or a MOSFET
transistor;

substantially concurrently with the obtaining of the first temperature measurement, applying a reference frequency signal
to the second temperature sensor and obtaining a second temperature measurement using the second temperature sensor;

computing, based on the first and second temperature measurements, a calibration adjustment value for the first temperature
sensor operating based on the characteristics of a semiconductor junction, a bipolar transistor, or a MOSFET transistor; and

adjusting, based on the computed calibration adjustment value, a third temperature measurement from the first temperature
sensor operating based on the characteristics of a semiconductor junction, a bipolar transistor, or a MOSFET transistor.

US Pat. No. 9,685,938

HIGH VOLTAGE SELECTOR CIRCUIT WITH NO QUIESCENT CURRENT

LINEAR TECHNOLOGY CORPORA...

1. A maximum-voltage selection circuit comprising:
multiple inputs, each for receiving a different input voltage;
an output for delivering the highest of the input voltages; and
a voltage selection circuit that:
automatically selects the input having the largest voltage magnitude;
automatically delivers the voltage at the selected input to the output; and
does not draw quiescent operating current from any of the inputs,
wherein for each and every unique combination of two of the multiple inputs, the voltage selection circuit comprises:
an enhancement mode FET with a channel connected in series between a first input of the unique combination of the two inputs
and the output, the enhancement mode FET also having a gate;

a connection between the gate of the enhancement mode FET and the second input of the unique combination of the two inputs
through the channel of a depletion mode FET, the gate of the depletion mode FET being connected to the output;

an additional enhancement mode FET with a channel connected in series between the second of the unique combination of the
two inputs and the output, the additional enhancement mode FET having a gate; and

a connection between the gate of the additional enhancement mode FET and the first of the unique combination of the two inputs.

US Pat. No. 9,595,991

LOW POWER RADIO RECEIVER

LINEAR TECHNOLOGY CORPORA...

1. A frequency converting element comprising:
a mixer having first and second input nodes and an output node; and
a charge pump,
wherein an input node of the charge pump is coupled to the output node of the mixer, and
wherein the charge pump receives a mixer output signal at the input node of the charge pump, and outputs an amplified version
of the mixer output signal, and

wherein the input node of the charge pump is directly coupled to the output node of the mixer.

US Pat. No. 9,859,909

ANALOG TO DIGITAL CONVERSION YIELDING EXPONENTIAL RESULTS

Linear Technology Corpora...

1. An analog to digital converter (ADC) providing an exponential result, comprising:
a ramp ADC comprising:
a first input configured to receive an analog input signal;
a second input configured to receive a first clock signal; and
a logic gate having an output operative to provide an internal gated clock signal based on the received first clock signal;
and

an exponential function circuit comprising:
an M-bit digital register comprising:
a first input configured to receive the internal gated clock signal of the ramp ADC;
a second input; and
an output operative to provide an M-bit exponential digital result of the analog input signal; and
an M-bit multiplier circuit comprising:
a first input coupled to the output of the M-bit digital register;
a second input operative to receive a reference signal; and
an output coupled to the second input of the M-bit digital register.

US Pat. No. 9,691,681

LASER DRILLING ENCAPSULATED SEMICONDUCTOR DIE TO EXPOSE ELECTRICAL CONNECTION THEREIN

LINEAR TECHNOLOGY CORPORA...

1. A method of making an integrated circuit package that contains therein a semiconductor die having a silicon side and one
or more electrical connections to an electronic circuit within the semiconductor die, the method comprising:
encapsulating the semiconductor die and its electrical connections in non-electrically conductive, encapsulation material;
laser drilling the encapsulation material to expose one of the electrical connections within the integrated circuit package,
thereby creating a via opening in an external surface of the encapsulation material to the electrical connection;

electroplating or sputtering over the via opening in the encapsulation material to create a conductive routing layer from
the external surface of the encapsulation material to the electrical connection;

attaching a first surface of a thermally-conductive heat spreader in a thermally-conductive manner to the silicon side of
the semiconductor die before the encapsulating;

during the encapsulating, also encapsulating the attached heat spreader in the non-electrically conductive, encapsulation
material, except for a second surface of the heat spreader, and

electroplating the first surface of the heat spreader to the silicon side of the semiconductor die.

US Pat. No. 9,634,481

MOSFET PROTECTION USING RESISTOR-CAPACITOR THERMAL NETWORK

LINEAR TECHNOLOGY CORPORA...

1. A system for supplying power from an input node to an output node, the system comprising surge stopper circuitry including
a semiconductor element that includes a MOSFET in a case, the surge stopper circuitry comprising:
a circuit for protecting the semiconductor element, comprising:
an analog multiplier responsive to a voltage across the semiconductor element and a current flowing through the semiconductor
element to produce an output voltage representing a product of values representing the voltage across the semiconductor element
and the current in the semiconductor element,

a transconductance amplifier coupled to an output of the analog multiplier for receiving the output voltage of the analog
multiplier to produce an output current,

an analog RC circuit coupled to the output of the transconductance amplifier and configurable to include a selected number
of resistive elements having selected resistance values and a selected number of capacitive elements having selected capacitance
values, the RC circuit being configurable to provide an RC thermal model that reproduces a desired thermal behavior of the
semiconductor element, the RC circuit being responsive to the output current of the transconductance amplifier to produce
an output voltage, and

a comparator for comparing the output voltage of the RC circuit with a reference voltage to produce a control signal supplied
to the semiconductor element, and

a sensor that senses the temperature of the MOSFET case, wherein the circuit has a configuration that
supplies a voltage that is proportional to case temperature to a node of the RC circuit to produce a thermal model with the
desired thermal behavior of the semiconductor element.

US Pat. No. 9,614,436

CIRCUIT AND METHOD FOR DYNAMIC SWITCHING FREQUENCY ADJUSTMENT IN A POWER CONVERTER

LINEAR TECHNOLOGY CORPORA...

1. A method for dynamically adjusting a frequency of a clock signal that determines a switching frequency of one or more switches
in a power converter, comprising:
detecting a change from a predetermined steady state value in an output voltage of the power converter and indicating the
change by an enable signal of a predetermined duration; and

upon receiving the enable signal, doubling the frequency of the clock signal by combining in time the clock signal with its
complement for the predetermined duration, so as to increase the switching frequency of the switches, thereby restoring the
output voltage to the predetermined steady state value.

US Pat. No. 9,660,856

DISTORTION COMPENSATION CIRCUIT

Linear Technology Corpora...

1. An analog distortion compensation circuit configured to compensate for a distortion in a baseband in-phase (I) signal and
a distortion in a corresponding baseband quadrature (Q) signal, the analog distortion compensation circuit comprising:
an in-phase I attenuator configured to attenuate the baseband in-phase I signal;
a quadrature Q attenuator configured to attenuate the baseband Q signal; and
a plurality of the following calculation circuits configured to receive the attenuated in-phase I signal and the attenuated
baseband Q signal and perform calculations based on the received attenuated I and Q signals:

a second order intermodulation circuit configured to calculate a second order intermodulation correction signal IM2 based
on IM2=I2+Q2;

(ii) a second order harmonic distortion circuit configured to calculate a second order harmonic correction signal HD2@0° based
on HD2@0°=I2?Q2;

(iii) a second order harmonic distortion circuit configured to calculate a second order harmonic correction signal HD2@90°
based on HD2@90°=2IQ;

(iv) a third order intermodulation circuit configured to calculate a third order intermodulation correction signal IM3@0°
based on IM3@0°=I3+Q2I;

(v) a third order intermodulation circuit configured to calculate a third order intermodulation correction signal IM3@90°
based on IM3 @90°=I2Q+Q3;

(vi) a third order harmonic distortion circuit configured to calculate a third order harmonic correction signal HD3@0° based
on HD3@0°=I3?3Q2I; and

(vii) a third order harmonic distortion circuit configured to calculate a third order harmonic correction signal HD3@90° based
on HD3@90°=32Q?Q3,

wherein the analog distortion compensation circuit is configured to use a result of the plurality of the calculation circuits
to generate an I distortion compensation signal at a first output and a Q distortion compensation signal at a second output.

US Pat. No. 9,671,465

DETECTING FAULTS IN HOT-SWAP APPLICATIONS

LINEAR TECHNOLOGY CORPORA...

1. A system for supplying power from an input node to an output node comprising:
at least one switch coupled between the input node and the output node and controlled by a switch control signal for performing
switching operations to provide power from the input node to the output node, the switch being supplied with an ON signal
to command the switch to turn on,

fault detecting circuitry for indicating a fault condition of the switch when the switch is commanded to turn on and at least
one of the following conditions is detected:

a voltage across the switch exceeds a predetermined value or
a value of the switch control signal is insufficient to turn the switch on, or
the fault condition being indicated only if the detected condition is present for a predetermined period of time; and
wherein at least one of the following:
multiple switches are coupled in parallel between the input node and the output node; and at least one of the following:
the fault detecting circuitry is configured for indicating the fault condition when the switches are commanded to turn on
and switch control signals for all of the switches are insufficient to turn the switches on; or

the fault detecting circuitry is configured for indicating the fault condition when the switches are commanded to turn on
and the switch control signal for any one of the switches is insufficient to turn the switch on; or

the fault detecting circuitry is configured for indicating the fault condition when the switch is commanded to turn on, the
switch control signal for the switch is insufficient to turn the switch on, and an output signal of the switch is not being
regulated; or

the switch includes a MOSFET and the fault detecting circuit is configured for indicating the fault condition when the MOSFET
is commanded to turn on and a voltage between drain and source of the MOSFET is greater than a first threshold value for a
first predetermined period of time; or

the switch includes a MOSFET and the fault detecting circuit is configured for indicating the fault condition when the MOSFET
is commanded to turn on and a gate to source voltage of the MOSFET is below a second threshold value for a second predetermined
period of time; or

multiple MOSFET switches are coupled between the input and output nodes; and
wherein the fault detecting circuit is configured for indicating the fault condition when the MOSFET switches are commanded
to turn on and gate to source voltages of all of the MOSFET switches are below a threshold value for a predetermined period
of time.

US Pat. No. 9,866,245

ACTIVE DIFFERENTIAL RESISTORS WITH REDUCED NOISE

LINEAR TECHNOLOGY CORPORA...

1. An active differential resistor, comprising:
an input node and an output node operative to provide a differential resistance;
a diode having a first node and a second node;
a capacitor coupled in series between the first node of the diode and the input node; and
a current source coupled across the first node and the second node of the diode and configured to forward bias the diode such
that a Johnson-Nyquist noise of the active differential resistor is replaced by a shot noise.

US Pat. No. 9,851,372

METHOD OF MANUFACTURING AN ANEMOMETER USED FOR DETERMINING A FLUID FLOW

Linear Technology Corpora...

1. A method of manufacturing an anemometer used for determining a fluid flow comprising:
providing a temperature sensor having electrical characteristics that vary with temperature, the temperature sensor being
thermally coupled to a metal base; and

providing a metal rod having one end configured for attachment to the base, the entire rod having a mass, wherein providing
the rod comprises:

calculating the mass of the rod needed to achieve a desired reaction of the temperature sensor to transients in the fluid
flow, wherein different masses of the rod vary the reaction of the temperature sensor to transients in the fluid flow;

manufacturing the rod to have the calculated mass; and
attaching the rod to the metal base so that the entire rod is within the fluid flow to be measured and the rod is heated when
the temperature sensor is heated.

US Pat. No. 9,785,219

LOW POWER TIMING, CONFIGURING, AND SCHEDULING

Linear Technology Corpora...

1. A device for triggering performance of a task on a time schedule comprising:
a component for performing the task and having an active state and an inactive state of operation;
a counter receiving a clock signal at an input, and producing a count signal at an output;
a first register for storing a first comparison value;
a second register for storing a second comparison value larger than the first comparison value; and
a comparison block for triggering the performance of the task by the component on the time schedule based on the count signal
and the first and second comparison values,

wherein based on a comparison of the count signal and the first comparison value, the comparison block triggers the component
to perform the task when the component operates in the active state, and

wherein based on a comparison of the count signal and the second comparison value, the comparison block changes the state
of operation of the component to the active state to trigger the component to perform the task.

US Pat. No. 9,705,325

CONTROLLING SWITCHING CIRCUITS TO BALANCE POWER OR CURRENT DRAWN FROM MULTIPLE POWER SUPPLY INPUTS

LINEAR TECHNOLOGY CORPORA...

1. A flyback converter power supply circuit having an output comprising:
multiple power supply inputs for respectively receiving multiple voltages from multiple voltage sources;
multiple switching circuits that each include a switching regulator having a flyback configuration coupled to the respective
power supply inputs to respectively receive the multiple voltages including at least two voltages having different values;

at least one primary inductive winding coupled to each of the switching circuits;
at least one secondary winding coupled to each of the primary windings and to the output;
a clock circuit that creates a switching cycle; and
control circuitry that controls the switching circuits by:
receiving a signal present in the current path of the at least one primary inductive winding that is representative of the
instantaneous current in the at least one primary inductive winding;

comparing the signal with a single threshold value common to all of the switching circuits, the single threshold value being
based on the voltage at the output of the power supply circuit; and

shortening a pulse width of a switching cycle when the signal exceeds the threshold so as to limit the instantaneous peak
current in said at least one primary inductive winding in each switching cycle to a peak current value common to all of the
switching circuits to balance power drawn from the multiple power supply inputs.

US Pat. No. 9,642,200

MAINTAINING LED DRIVER OPERATING POINT DURING PWM OFF TIMES

Linear Technology Corpora...

1. A light emitting diode (LED) driver circuit comprising:
a control signal input configured to receive a control signal;
a pulse-width modulation (PWM) input configured to receive a PWM signal;
a power stage having a first input coupled to the PWM input, a second input configured to receive an operating point signal,
and an output, wherein the power stage is configured to deliver a level of current indicated by the control signal, to a light
emitting diode (LED) load when the PWM signal is ON and stop delivering the level of current when the PWM signal is OFF;

a feedback circuit coupled between the output and the second input of the power stage, wherein the feedback circuit is configured
to generate the operating point signal to cause the power stage to deliver a level of current indicated by the control signal,
when the PWM signal is ON;

a store and hold circuit having a first node coupled to the PWM input and a second node coupled to the second input of the
power stage, wherein the store and hold circuit is configured to store an information indicative of a level of the operating
point signal just after the PWM signal is turned OFF and cause the operating point signal to be at that level just before
the PWM signal is turned ON.

US Pat. No. 9,632,519

CLASS AB INVERTING DRIVER FOR PNP BIPOLAR TRANSISTOR LDO REGULATOR

Linear Technology Corpora...

1. A low dropout (LDO) regulator comprising:
a first PNP transistor connected in series between an input voltage Vin terminal and an output voltage Vout terminal for coupling
to a load;

an NPN driver transistor having a collector coupled to a base of the first PNP transistor, for controlling a conductivity
of the PNP transistor, and having an emitter coupled to ground;

an error amplifier receiving a voltage corresponding to the output voltage and receiving a set voltage, the error amplifier
being connected in a feedback loop for matching the voltage corresponding to the output voltage to the set voltage; and

an inverting circuit comprising:
a push-pull circuit connected to a base of the NPN driver transistor, the push-pull circuit comprising a second PNP transistor,
acting as a pull-up transistor, and a first NPN transistor, acting as a pull-down transistor;

a first control circuit connected to a base of the second PNP transistor;
a second control circuit connected to a base of the first NPN transistor; and
a current diverting transistor, coupled to a first current source, controlling an amount of current to the first control circuit
and to the second control circuit, wherein a base of the current diverting transistor is coupled to an output of the error
amplifier,

wherein the inverting circuit is connected between the input voltage and ground, and wherein the inverting circuit has a minimum
voltage drop between the input voltage and ground less than two diode drops to allow the inverting circuit to operate with
an input voltage within two diode drops above ground.

US Pat. No. 9,634,844

DETECTION SCHEME FOR FOUR WIRE PAIR POWER OVER ETHERNET SYSTEM

Linear Technology Corpora...

1. A Power Over Ethernet (PoE) system for supplying power via four wire pairs in an Ethernet cable comprising:
Power Sourcing Equipment (PSE) providing data and voltage over Ethernet wires, the PSE having a voltage source for generating
a PoE voltage for transmission on the Ethernet wires, the Ethernet wires comprising four pairs of wires;

a Powered Device (PD) connected to the PSE by at least the Ethernet wires to receive the data and voltage, the PD presenting
PoE characteristics to the PSE upon the PD receiving a first signal during a handshaking phase prior to a full voltage level
being applied to the PD;

the PSE further comprising:
a controller for controlling the first signal to be applied to a first set of Ethernet wires including a first pair of wires
and a second pair of wires;

a first current detection component coupled between a third pair of wires in the Ethernet wires and a switch;
a second current detection component coupled between a fourth pair of wires in the Ethernet wires and the switch;
the controller for detecting that the currents through the first current detection component and the second current detection
component are approximately equal, consistent with the first pair of wires and the second pair of wires being connected together
at the PD, and of a magnitude characteristic of the PD being PoE-enabled while the PSE supplies the first signal to the PD,
and, in response, controlling the PSE to apply the full PoE voltage to the first pair of wires and the second pair of wires
while the switch is closed to cause the third pair of wires and the fourth pair of wires to be coupled to a low voltage via
the switch.

US Pat. No. 10,090,666

CIRCUIT ARCHITECTURES FOR PROTECTING AGAINST PODL WIRE FAULTS

Linear Technology Corpora...

1. A Power over Data Lines (PoDL) system comprising:Power Sourcing Equipment (PSE) configured for coupling to a Powered Device (PD) via a wire pair, comprising a first wire and a second wire, wherein differential data signals and DC power are conducted over the same wire pair;
a controller configured to detect a voltage on the first wire, after the DC power is initially coupled to the wire pair, and compare the voltage on the first wire to a first upper threshold limit and a first lower threshold limit for the first wire to determine whether a wiring fault condition exists with respect to the first wire;
the controller also configured to detect a voltage on the second wire, after the DC power is initially coupled to the wire pair, and compare the voltage on the second wire to a second upper threshold limit and a second lower threshold limit for the second wire to determine whether a wiring fault condition exists with respect to the second wire;
a first switch in series with the first wire, controlled by the controller,
wherein the controller opens at least the first switch when the fault condition is detected with respect to the first wire; and
a second switch in series with the second wire, controlled by the controller,
wherein the controller opens at least the second switch when the fault condition is detected with respect to the second wire.

US Pat. No. 9,860,072

SYSTEM WITH SLEEP AND WAKE UP CONTROL OVER DC PATH

Linear Technology Corpora...

1. A method performed by a system including a master and a slave linked via a wire pair, the master including a first data
path and the slave including a second data path coupled to the first data path via the wire pair, the first data path comprising
a first transceiver, the second data path comprising a second transceiver, the method comprising:
operating the system in a first mode of operation, wherein the master and slave are powered and data is transmitted between
the master and slave via the first data path and the second data path;

disabling at least the second transceiver in the slave to disable data transmission via the wire pair in a low power second
mode of operation;

while in the second mode, transmitting a DC voltage by the master on the wire pair signaling to the slave to enable the second
transceiver to reenter the first mode of operation; and

detecting the DC voltage on the wire pair by the slave, transmitted by the master, and, in response, enabling the second transceiver
to activate the second data path,

wherein reentering the first mode is controlled independently of the first data path and the second data path.

US Pat. No. 9,748,843

DCR INDUCTOR CURRENT-SENSING IN FOUR-SWITCH BUCK-BOOST CONVERTERS

Linear Technology Corpora...

1. An inductor current-sensing circuit for measuring a current in a primary inductor of a four-switch buck boost converter
with an inductance and an equivalent DC resistance, the four-switch buck boost converter receiving an input voltage and providing
an output voltage, the inductor current-sensing circuit comprising:
a first RC network coupled between a first terminal of the primary inductor and a virtual ground reference;
a second RC network coupled between a second terminal of the primary inductor and the virtual ground reference, wherein the
first RC network and the second RC network each have a time constant substantially equal to the ratio between the inductance
and the DC resistance; and

a decoupling capacitor connecting the virtual ground reference to a system ground reference.

US Pat. No. 10,135,336

CONTROL ARCHITECTURE WITH IMPROVED TRANSIENT RESPONSE

Linear Technology Corpora...

1. A power interface device comprising:a output sense terminal configured to sense a shared converter output voltage of a main switching converter and an auxiliary switching converter at an output terminal;
an auxiliary current sense terminal configured to sense an auxiliary current of an auxiliary switching converter; and
an auxiliary control loop circuit configured to detect a transient signal at the output terminal and, responsive to the transient signal, issue an auxiliary control signal for controlling the auxiliary switching converter based on the shared converter output voltage and the sensed auxiliary current,
wherein the auxiliary switching converter is configured to operate at an auxiliary switching frequency different from a main switching frequency of the main switching converter.

US Pat. No. 9,973,079

SYNCHRONIZED CHARGE PUMP-DRIVEN INPUT BUFFER AND METHOD

Linear Technology Corpora...

1. An electronic circuit, comprising:an analog-to-digital converter operated according to a first clock signal, the first clock signal having a first frequency, the analog-to-digital converter having a frequency rejection band and producing a digital output signal based on an analog input signal; and
a charge pump circuit providing a negative power supply voltage to the analog-to-digital converter, the charge pump circuit being operated according to a second clock signal having a second frequency that is different from the first frequency of the first clock signal, wherein the second frequency, for operating the charge pump circuit, is selected to be within the frequency rejection band of the analog-to-digital converter, such that a noise effect on the digital output signal of noise introduced by the charge pump is attenuated by the frequency rejection of the analog-to-digital converter.

US Pat. No. 9,960,752

SWITCHABLE TERMINATION WITH MULTIPLE IMPEDANCE SELECTIONS

Linear Technology Corpora...

1. A termination matching circuit comprising:first and second nodes;
a first series interconnection of a first switch device and a first impedance element coupled between the first and second nodes;
a second series interconnection of a second switch device and a second impedance element coupled between the first and second nodes;
a third impedance element coupled to and between the first switch device at the first series interconnection and to the second switch device at the second series interconnection; and
first and second control circuits respectively coupled to a control terminal of the first switch device and a control terminal of the second switch device,
wherein a selectable impedance is provided between the first and second nodes of the termination matching circuit through selective activation of the first and second switch devices by the first and second control circuits.

US Pat. No. 9,851,772

1-WIRE BUS PD DETECTION AND CLASSIFICATION SCHEME FOR ETHERNET PODL

Linear Technology Corpora...

1. A Power over Data Lines (PoDL) system for supplying power and data over a wire pair, the wire pair being a first wire and
a second wire coupled to a Powered Device, the system comprising:
a Power Sourcing Equipment (PSE) side of the wire pair, the PSE side comprising:
a DC voltage source supplying a DC voltage;
a first low pass filter coupled to the first wire;
a first switch coupled between the DC voltage source and the first low pass filter for selectively coupling the DC voltage
to the first wire;

a first pull-up current source coupled to the first low pass filter at a first node;
a first pull-down device coupled to the first node;
a first control circuit controlling the first switch and the first pull-down device; and
a first differential data transceiver coupled to the wire pair via a first high pass filter;
a Powered Device (PD) side of the wire pair, the PD side comprising:
a second low pass filter coupled to the first wire;
a first capacitor coupled to the second low pass filter;
a second pull-down device coupled to the second low pass filter;
a second differential data transceiver coupled to the wire pair via a second high pass filter; and
a second control circuit controlling the second pull-down device, wherein the first capacitor is coupled to a voltage input
terminal of the second control circuit,

wherein, prior to the first switch being closed for coupling the DC voltage source to the first wire, the first pull-up current
source charges the first capacitor to an operating voltage of the second control circuit to power the second control circuit,
and

wherein the first control circuit and the second control circuit are configured to transmit and receive first serial data
via the first wire by controlling the first pull-down device and the second pull-down device prior to the DC voltage source
being applied to the first wire, such that the first pull-up current source provides power to operate the second control circuit
while also being used to pull-up the first wire for transmitting serial data via the first wire.

US Pat. No. 9,825,553

VOLTAGE REGULATION IN RESONANT POWER WIRELESS RECEIVER

Linear Technology Corpora...

1. A control system for controlling a power receiving circuit configured for receiving power wirelessly, producing an output
voltage and having a resonant LC circuit including an inductive element and a capacitive element coupled in parallel, the
control system comprising:
a controllable shunt circuit coupled in parallel to the resonant LC circuit that, when activated, shunts substantially all
current generated by the resonant LC circuit, and

a feedback loop circuit configured for regulating the output voltage by activating the controllable shunt circuit during only
a portion of each cycle of a voltage developed across the resonant LC circuit so as to cause the output voltage to be at a
pre-determined level, the feedback loop circuit comprising a pulse width modulation (PWM) control circuit that produces a
PWM control signal responsive to a difference between the output voltage and a reference voltage, to control the controllable
shunt circuit.

US Pat. No. 9,774,206

VOLTAGE COMPENSATED ACTIVE CELL BALANCING

LINEAR TECHNOLOGY CORPORA...

1. A monitoring device that determines an open cell voltage during battery stack balancing, the monitoring device comprising:
an input terminal that receives an input signal from a battery system management (BSM);
an output terminal that outputs cell parameters used to determine an open cell voltage associated with one of a plurality
of cells within the battery stack connected to the monitoring device based on the input signal received from the BSM;

the monitoring device having a configuration that:
measures a cell voltage associated with the one of the plurality of cells within the battery stack;
determines a voltage drop associated with a measured balancing current by taking into consideration balancing current associated
with the one of the plurality of cells, a cell above the one of the plurality of cells, and a cell below the one of the plurality
of cells, and current simultaneously flowing through the plurality of cells;

calculates the open cell voltage during balancing, stack loading, and stack charging by adjusting the measured cell voltage
based on the voltage drop; and

actively balances multiple cells in the battery stack based on the calculated open cell voltage, wherein:
the active balancing and the calculating the open cell voltage are performed concurrently, and
the actively balances includes removal of charge from a cell and returning that removed charge to one or more other cells
in the stack.

US Pat. No. 9,774,297

DOUBLE-BALANCED FIELD-EFFECT TRANSISTOR MIXER WITH DIRECT SINGLE-ENDED INTERMEDIATE FREQUENCY OUTPUTS

LINEAR TECHNOLOGY CORPORA...

1. A double-balanced FET mixer comprising:
a single-ended RF port that receives or delivers a single-ended RF signal;
an RF balun that converts the received single-ended RF signal into a differential RF signal or that generates the delivered
single-ended RF signal from a received differential RF signal;

a local oscillator input port that receives a local oscillator signal;
an IF port that receives or delivers a single-ended IF signal; and
a passive mixer core comprising at least two field-effect transistors that process the local oscillator signal and that generate
or process the differential RF signal and the single-ended IF signal.

US Pat. No. 10,003,190

INRUSH CONTROL WITH MULTIPLE SWITCHES

Linear Technology Corpora...

1. A system for supplying power from an input node to a load coupled to an output node, comprising:a first limiting circuit configured to control a first switch so as to limit an output current of the first switch,
a second limiting circuit configured to control a second switch, independent of the first limiting circuit, so as to limit an output current of the second switch in an amount that is different than the limit imposed by the first limiting circuit on an output of the first switch, and
a logic circuit configured to produce an output signal responsive to the output current of the first switch being limited by the first limiting circuit and the output current of the second switch being limited by the second limiting circuit.

US Pat. No. 9,967,104

DETECTING GROUND ISOLATION FAULT IN ETHERNET PODL SYSTEM

Linear Technology Corpora...

1. A Power over Data Lines (PoDL) system, the system including Power Sourcing Equipment (PSE) configured for being coupled to a Powered Device (PD) via a wire pair, the PSE also being configured for coupling a DC voltage to the wire pair via one or more power switches so that differential data signals and DC power can be conducted over the same wire pair, the PSE comprising:a sense circuit coupled to sense a leakage current in a current loop, wherein the current loop includes at least one wire in the wire pair between the PSE and PD, wherein the leakage current is indicative of a ground isolation fault between the PD and a ground of the PSE, wherein the sense circuit is configured to identify if the sensed leakage current indicative of the ground isolation fault is above a threshold value;
wherein the sense circuit comprises:
a first current sensing circuit configured to sense a sourcing current level to a PD load when the one or more power switches are closed, the first current sensing circuit comprising a first differential amplifier outputting a first signal indicative of the sourcing current level;
a second current sensing circuit configured to sense a return current level from the PD load when the one or more power switches are closed, the second current sensing circuit comprising a second differential amplifier outputting a second signal indicative of the return current level;
a detector circuit configured to detect signals corresponding to the sourcing current level and the return current level and determining if the return current is sufficiently changed by a leakage current to signal the ground isolation fault, the detector circuit comprising:
a combiner coupled to receive the first signal and the second signal; and
a comparator that determines whether an output of the combiner indicates the ground isolation fault.

US Pat. No. 9,698,800

SYSTEM AND METHOD FOR CLOCK GENERATION WITH AN OUTPUT FRACTIONAL FREQUENCY DIVIDER

Linear Technology Corpora...

1. A clock signal generation circuit, comprising:
a phase-locked loop including a voltage-controlled oscillator, the phase-locked loop receiving an input clock signal and providing
an output signal that is phase-locked to the input clock signal; and

a frequency divider circuit receiving the output signal of the phase-locked loop, wherein the frequency divider circuit (i)
generates a plurality of signals of various frequencies by dividing the frequency of the output signal of the phase-locked
loop by selected numerical constants, and (ii) generates an output signal of the clock signal generation circuit from one
of the signals of various frequencies, wherein the various frequencies include both an integer submultiple and a fractional
submultiple of the frequency of the output signal of the phase-locked loop, and wherein the fractional submultiple is not
an integer submultiple.

US Pat. No. 9,634,480

MOSFET PROTECTION USING RESISTOR-CAPACITOR THERMAL NETWORK

LINEAR TECHNOLOGY CORPORA...

1. A circuit for protecting a semiconductor element in a system for supplying power from an input node to an output node,
the semiconductor element including a MOSFET in a case, the circuit comprising:
an analog multiplier responsive to a voltage across the semiconductor element and a current flowing through the semiconductor
element to produce an output voltage representing a product of values representing the voltage across the semiconductor element
and the current in the semiconductor element,

a transconductance amplifier coupled to an output of the analog multiplier for receiving the output voltage of the analog
multiplier to produce an output current,

an analog RC circuit coupled to the output of the transconductance amplifier and configurable to include a selected number
of resistive elements having selected resistance values and a selected number of capacitive elements having selected capacitance
values, the RC circuit being configurable to provide an RC thermal model that reproduces a desired thermal behavior of the
semiconductor element, the RC circuit being responsive to the output current of the transconductance amplifier to produce
an output voltage,

a comparator for comparing the output voltage of the RC circuit with a reference voltage to produce a control signal supplied
to the semiconductor element, and

a sensor that senses the temperature of the MOSFET case, wherein the circuit has a configuration that
turns the MOSFET off when the MOSFET case temperature exceeds a predefined temperature threshold.

US Pat. No. 9,998,000

BALANCING CHARGE PUMP CIRCUITS

LINEAR TECHNOLOGY CORPORA...

1. A circuit for controlling a switched capacitor converter, comprising:a first comparator circuit coupled to a first current source and a second current source; and
a voltage divider configured to sample an input voltage at an input node and provide a reference voltage to the first comparator circuit, wherein the first comparator circuit is configured to:
control the first and second current sources such that the first current source draws a first current from a first terminal of a flying capacitor of the switched capacitor converter, and the second current source provides a second current to a second terminal of the flying capacitor upon determining that a voltage across the flying capacitor is above a first threshold from the reference voltage;
control the first and second current sources such that the first current source provides the first current to the first terminal of the flying capacitor, and the second current source draws the second current from the second terminal of the flying capacitor upon determining that the voltage across the flying capacitor is below a second threshold from the reference voltage; and
turn OFF the first and second current sources upon determining that the voltage across the flying capacitor is above the second threshold and below the first threshold from the reference voltage.

US Pat. No. 9,897,981

DETECTION AND CLASSIFICATION SCHEME FOR POWER OVER ETHERNET SYSTEM

Linear Technology Corpora...

1. A Power Over Ethernet (PoE) system comprising:
Power Sourcing Equipment (PSE) providing data and voltage over Ethernet wires, the PSE having a voltage source for generating
a PoE voltage for transmission on the Ethernet wires; and

a Powered Device (PD) connected to the PSE by at least the Ethernet wires to receive the data and voltage, the PoE voltage
having a first magnitude for powering the PD,

the PD comprising a voltage limiting circuit electrically coupled to input terminals of the PD, wherein the voltage limiting
circuit responds in a predetermined manner to a first signal generated by the PSE to create a voltage-limited signal, and
wherein the voltage limiting circuit is selected to convey particular PoE requirements of the PD, the voltage limited signal
being less than the PoE voltage having the first magnitude;

the PSE further comprising:
a first signal generator providing the first signal on the Ethernet wires to the input terminals of the PD at a particular
time, wherein the first signal is applied to the voltage limiting circuit in the PD;

a first detector detecting the voltage-limited signal, generated by voltage limiting circuit in the PD, in response to the
first signal; and

a processing circuit configured for detecting the voltage-limited signal and, in response to a detected magnitude of the voltage-limited
signal, associating the voltage-limited signal with the particular PoE requirements of the PD, and controlling the PSE to
supply power to the PD via the Ethernet wires consistent with the PoE requirements of the PD conveyed by the voltage-limited
signal;

a switch in the PD connected to disconnect the voltage limiting circuit from across the Ethernet wires after the PSE has determined
the PoE requirements of the PD, such that the voltage limiting circuit does not limit the PoE voltage having the first magnitude.

US Pat. No. 9,853,838

PODL SYSTEM WITH ACTIVE DV/DT AND DI/DT CONTROL

Linear Technology Corpora...

1. A Power over Data Lines (PoDL) system, which enables power and differential data transmission over a single wire pair,
comprising:
a passive coupling network in Power Sourcing Equipment (PSE) coupled to the wire pair for coupling a DC power signal and differential
data to the wire pair;

a passive decoupling network in a Powered Device (PD) coupled to the wire pair for decoupling the DC power signal and differential
data from the wire pair;

a PD load powered by the DC power signal; and
dV/dt limiting circuitry, separate from the passive coupling network and the passive decoupling network, comprising one or
more active components, wherein the dV/dt limiting circuitry limits dV/dt in the power signal, the dV/dt limiting circuitry
being configured to limit the dV/dt of the DC power signal at all currents drawn by the load.

US Pat. No. 9,793,734

MONITORING CELLS IN ENERGY STORAGE SYSTEM

Linear Technology Corpora...

1. A system for monitoring an energy storage system composed of cells connected in series, comprising:
a plurality of monitors arranged in a chain for monitoring and controlling conditions of the cells, and
a controller coupled to the chain of monitors for receiving monitored data produced by the monitors and transferred over the
chain in a first direction, the controller being responsive to the monitored data by producing control data transferred over
the chain of the monitors in a second direction opposite to the first direction, the control data including address information
identifying a cell to be controlled,

a monitor of the plurality of monitors being configured for monitoring conditions of multiple serially connected cells and
being associated with multiple switches respectively coupled to the multiple monitored cells to control conditions of the
monitored cells,

the monitor being responsive to the control data by controlling a switch corresponding to the cell identified in the address
information to perform an operation in connection with the identified cell.

US Pat. No. 9,793,800

MULTIPHASE SWITCHING POWER SUPPLY WITH ROBUST CURRENT SENSING AND SHARED AMPLIFIER

Linear Technology Corpora...

1. A multiphase switching power supply comprising:
a first power supply portion switching at a first phase,
wherein the first power supply portion comprises a first inductor and a first current detection circuit for generating a first
voltage signal corresponding to a first AC component of current through the first inductor and for generating a second voltage
signal corresponding to a first DC component of current through the first inductor,

wherein the first power supply portion further comprises a first summing circuit for summing the first voltage signal and
the second voltage signal to create a composite first current sense signal corresponding to a current through the first inductor;

a second power supply portion, substantially identical to the first power supply portion, switching at a second phase, different
from the first phase,

wherein the second power supply portion comprises a second inductor and a second current detection circuit for generating
a third voltage signal corresponding to a second AC component of current through the second inductor and generating a fourth
voltage signal corresponding to a second DC component of current through the second inductor,

wherein the second power supply portion further comprises a second summing circuit for summing the third voltage signal and
the fourth voltage signal to create a composite second current sense signal corresponding to a current through the second
inductor;

a differential amplifier,
wherein the first current detection circuit and the second current detection circuit share the differential amplifier, wherein
the differential amplifier has a gain for amplifying a fifth voltage signal in the first current detection circuit, to generate
the second voltage signal corresponding to the first DC component of current through the first inductor, and for similarly
amplifying a sixth voltage signal in the second current detection circuit, to generate the fourth voltage signal corresponding
to the second DC component of current through the second inductor;

a first multiplexer having inputs coupled to the first power supply portion and the second power supply portion to receive
the fifth voltage signal and the sixth voltage signal and having an output coupled to inputs of the differential amplifier,
the first multiplexer coupling the fifth voltage signal to the inputs of the differential amplifier during a switching cycle
of the first power supply portion, and the first multiplexer coupling the sixth voltage signal to the inputs of the differential
amplifier during a switching cycle of the second power supply portion;

a first sample and hold circuit sampling and holding the second voltage signal output from the differential amplifier, corresponding
to the first DC component of current through the first inductor, during the switching cycle of the first power supply portion,
an output of the first sample and hold circuit being connected to an input of the first summing circuit;

a second sample and hold circuit sampling and holding the fourth voltage signal output from the differential amplifier corresponding
to the second DC component of current through the second inductor, during the switching cycle of the second power supply portion,
an output of the second sample and hold circuit being connected to an input of the second summing circuit; and

a second multiplexer having an input coupled to the output of the differential amplifier, the second multiplexer connecting
the output of the differential amplifier to the first sample and hold circuit during the switching cycle of the first power
supply portion and connecting the output of the differential amplifier to the second sample and hold circuit during the switching
cycle of second power supply portion.

US Pat. No. 9,780,974

BROADBAND POWER COUPLING/DECOUPLING NETWORK FOR PODL

Linear Technology Corpora...

1. A Power over Data Lines (PoDL) system for supplying power and data over a wire pair, the wire pair being a first wire and
a second wire coupled to a powered device, the system comprising:
a DC voltage source having a first voltage source terminal and a second voltage source terminal, where a DC voltage is across
the first voltage source terminal and the second voltage source terminal;

a first series combination of two or more inductors having a first terminal coupled to the first voltage source terminal,
the series combination of inductors also having a second terminal outputting a first filtered DC voltage for coupling to the
first wire, wherein the first series combination comprises a first inductor, having the first terminal, and a second inductor,
having the second terminal, wherein the first inductor has a first inductance greater than a second inductance of the second
inductor;

a second series combination of two or more inductors having a third terminal coupled to the second voltage source terminal,
the second series combination of inductors also having a fourth terminal outputting a second filtered DC voltage for coupling
to the second wire, wherein the second series combination comprises a third inductor, having the third terminal, and a fourth
inductor, having the fourth terminal, wherein the third inductor has an inductance approximately equal to the first inductance,
and wherein the fourth inductor has an inductance approximately equal to the second inductance;

a differential data transceiver having a first data terminal and a second data terminal;
a first capacitor having a fifth terminal coupled to the first data terminal, the first capacitor having a sixth terminal
for coupling to the first wire to combine data with the first filtered DC voltage; and

a second capacitor having a seventh terminal coupled to the second data terminal, the second capacitor having an eighth terminal
for coupling to the second wire to combine the data with the second filtered DC voltage.

US Pat. No. 9,769,090

ADJUSTING CURRENT LIMIT THRESHOLDS BASED ON POWER REQUIREMENT OF POWERED DEVICE IN SYSTEM FOR PROVIDING POWER OVER COMMUNICATION LINK

LINEAR TECHNOLOGY CORPORA...

1. A system for supplying power to a powered device (PD) over a communication link, comprising a current limit adjusting mechanism
including:
a current limit circuit for monitoring current in the system, the current limit circuit being responsive to a first overcurrent
event so as to restrict the current based on a first current limit threshold defined to respond to the first overcurrent event,

a current limit threshold storage for storing values of the first current limit threshold for various PD power requirements,
a power requirement determining circuit for determining a power requirement of the PD, and
a threshold control circuit for accessing the current limit threshold storage to determine a stored value of the first current
limit threshold for a particular power value required by the PD,

the threshold control circuit being configured to provide the current limit circuit with a first threshold value produced
in accordance with the determined stored value of the first current limit threshold,

the current limit circuit being configured to compare a value representing the monitored current with the provided first threshold
value so as to restrict the current based on the provided first threshold value.

US Pat. No. 9,667,429

PSE CONTROLLER IN POE SYSTEM DETECTS DIFFERENT PDS ON DATA PAIRS AND SPARE PAIRS

Linear Technology Corpora...

1. A method performed by a Power over Ethernet (PoE) system comprising data wire pairs and spare wire pairs, the system comprising
a Power Sourcing Equipment (PSE) controller having an OUT1 terminal connected to a data wire pair, an OUT2 terminal connected to a spare wire pair, and a SENSE terminal connected to the OUT1 terminal via a first resistor and connected to the OUT2 terminal via a second resistor, the system further comprising a switch controlled by the PSE controller coupled between a
PoE voltage source and the SENSE terminal, the method comprising:
supplying a first current to the OUT1 terminal and measuring a V11 voltage at the OUT1 terminal by the PSE controller;

supplying a second current to the OUT1 terminal and measuring a V12 voltage at the OUT1 terminal by the PSE controller;

by using V11 and V12, detecting whether there is a signature resistance of a PoE-compatible Powered Device (PD) connected to the data wire pair;

supplying the first current to the OUT2 terminal and measuring a V21 voltage at the OUT2 terminal by the PSE controller;

supplying the second current to the OUT2 terminal and measuring a V22 voltage at the OUT2 terminal by the PSE controller;

by using V21 and V22, detecting whether there is a signature resistance of a PoE-compatible PD connected to the spare wire pair;

supplying the first current to the SENSE terminal and measuring a VSENSE1 voltage at the SENSE terminal by the PSE controller;

supplying the second current to the SENSE terminal and measuring a VSENSE2 voltage at the SENSE terminal by the PSE controller;

by using VSENSE1 and VSENSE2, detecting whether there is zero, one, or two PoE-compatible PDs connected to the data wire pair and the spare wire pair;
and

based on the detection of voltages at the OUT1, OUT2, and SENSE terminals, determining, by the PSE controller, whether to control the switch to couple the PoE voltage source
to the data wire pair and spare wire pair.

US Pat. No. 9,667,264

TRANSITION TIMING CONTROL FOR SWITCHING DC/DC CONVERTER

LINEAR TECHNOLOGY CORPORA...

1. A DC/DC converter for providing power to a load device, the load device having a first operational phase that is sensitive
to external injected noise and a second operational phase that is immune to the external injected noise, the DC/DC converter
comprising:
a coil;
a switch for controlling current in the coil;
a first input terminal that receives a start signal of the first operational phase for the load device; and
control circuitry, responsive to the start signal, for controlling the switch to avoid switching by the switch during the
first operational phase;

wherein the switch controls the frequency of the current to the coil;
further comprising a counter to increment or decrement a counter value during a half period of the switching frequency of
the switch, the switching frequency being 1/(2×half period); and

wherein the control circuitry is, responsive to the start signal, to compare the counter value with reference values to control
the switching frequency of the switch.

US Pat. No. 9,977,446

INVERTING AMPLIFIER RECEIVING NEGATIVE FEEDBACK VOLTAGE IN VOLTAGE REGULATOR

Linear Technology Corpora...

1. A circuit comprising:an inverting amplifier for receiving a negative input voltage of a first magnitude and generating a positive output voltage of the same first magnitude, the inverting amplifier comprising:
a high impedance input terminal of a first transistor receiving the negative input voltage;
a first differential amplifier coupled to the first transistor; and
a first resistor coupled to a reference voltage,
an output of the first differential amplifier controlling current through the first resistor, wherein a voltage drop across the first resistor is the positive output voltage of the same first magnitude as the negative input voltage.

US Pat. No. 9,831,781

FAST TRANSIENT POWER SUPPLY WITH A SEPARATED HIGH FREQUENCY AND LOW FREQUENCY PATH SIGNALS

Linear Technology Corpora...

17. A power interface device comprising:
a main switching converter coupled to an input terminal and an output terminal and configured to operate at a first switching
frequency to source a low frequency current from the input terminal to the output terminal;

an auxiliary switching converter coupled to the input terminal and the output terminal in parallel with the main switching
converter and configured to operate at a second and higher switching frequency than the first switching frequency to source
a fast transient high frequency current from the input terminal to the output terminal;

a feedback sense circuit configured to sense an output voltage at the output terminal;
an error amplifier configured to receive the sensed output voltage and a reference voltage and output a transient signal based
on the sensed output voltage and the reference voltage;

a low pass filter configured to receive the transient signal and output a lower frequency component of the transient signal;
a high pass filter configured to receive the transient signal and output a higher frequency component of the transient signal;
a main driver circuit configured to drive the auxiliary switching converter based on the lower frequency component of the
transient signal; and

an auxiliary driver circuit configured to drive the auxiliary switching converter based on the higher frequency component
of the transient signal.

US Pat. No. 10,013,003

FEED FORWARD CURRENT MODE SWITCHING REGULATOR WITH IMPROVED TRANSIENT RESPONSE

LINEAR TECHNOLOGY CORPORA...

1. A current mode switching regulator circuit comprising:a power switch controller for generating control signals for controlling a duty cycle of a power switch for generating a regulated voltage to a load, the power switch controller comprising:
a voltage feedback loop, sensing at least an output voltage of the regulator circuit, for providing feedback signals to the power switch controller for maintaining a regulated output voltage of the regulator circuit;
a current sense circuit configured to generate a current sense signal corresponding to a current through the power switch; and
a current feedback loop that compares the current sense signal to a threshold value to turn off the power switch at a peak current for controlling the duty cycle of the power switch;
a first circuit that generates a first signal prior to and in anticipation of a first load current step;
the power switch controller further comprising an offset circuit connected in the current feedback loop that, in response to the first signal, generates an offset signal that offsets the current sense signal by an amount corresponding to the anticipated first load current step to adjust the duty cycle of the power switch for the first load current step without sensing the output voltage of the regulator,
wherein, after the first load current step has occurred and the offset signal has adjusted the current sense signal, the regulator circuit regulates the output voltage based on a feedback voltage in the voltage feedback loop corresponding to the output voltage of the regulator circuit.

US Pat. No. 9,966,832

PREDICTIVE RIPPLE-CANCELLING SIGNAL INTO ERROR AMPLIFIER OF SWITCH MODE POWER SUPPLY

Linear Technology Corpora...

1. A switching converter comprising:a transistor switch;
a voltage feedback circuit configured to generate a feedback voltage, the feedback voltage having a ripple component at a switching frequency of the transistor switch;
an error amplifier configured to generate a control signal for use in determining when to turn off the transistor switch during a switching cycle, the error amplifier having inputs comprising an inverting input and a non-inverting input;
a filter configured to pass the ripple component of the feedback voltage;
a processing circuit configured to process the ripple component of the feedback voltage over a number of switching cycles to derive a predicted ripple component of the feedback voltage;
a reference voltage generator configured to generate a reference voltage; and
a combiner circuit configured to combine the predicted ripple component of the feedback voltage with one of the reference voltage or the feedback voltage before being applied to the respective inputs of the error amplifier to at least partially offset effects of the ripple component of the feedback voltage.

US Pat. No. 9,899,921

ADAPTIVE SLOPE COMPENSATION FOR CURRENT MODE SWITCHING POWER SUPPLY

LINEAR TECHNOLOGY CORPORA...

1. A current mode switching converter comprising:
a transistor switch;
an inductor configured to conduct a ramping inductor current as the transistor switch is turned on and off at a particular
duty cycle;

a current sensor configured to convert the ramping inductor current to a corresponding current sense signal, the current sense
signal having an up-slope portion with a first slope and having a down-slope portion with a second slope, wherein, at duty
cycles greater than 50%, the first slope is less than an absolute value of the second slope;

a ramp generator configured to generate a ramp voltage while the current sense signal has the first slope;
an adaptive slope compensation circuit configured to generate a compensation voltage for the ramp voltage to create a compensated
ramp voltage;

a combining circuit configured to sum the compensated ramp voltage with the current sense signal to create a compensated current
sense signal;

a threshold voltage generator configured to generate a threshold voltage for determining a peak current through the inductor;
and

a comparator configured to receive the compensated current sense signal and the threshold voltage for determining when to
turn off the transistor switch,

wherein the adaptive slope compensation circuit forces the compensated current sense signal to have an up-slope greater than
an absolute value of its down-slope at least for duty cycles greater than 50%.

US Pat. No. 9,955,443

TIMING SYNCHRONIZATION FOR WIRELESS NETWORKS

Linear Technology Corpora...

1. A system for maintaining synchronization of nodes in a wireless network comprising:a first node comprising a transmitter, a receiver, and a first time keeper and configured for wireless communication with a second node comprising a transmitter, a receiver, and a second time keeper,
wherein:
the first node transmits a keep-alive packet to the second node upon expiration of a keep-alive interval following transmission of a previous packet from the first node to the second node, so as to maintain synchronization between the first time keeper of the first node and the second time keeper of the second node,
the first node adjusts the keep-alive interval between transmissions of keep-alive packets based on a determination that no acknowledgment of receipt of a previous keep-alive packet is received from the second node, and
the first node adjusts the keep-alive interval by reducing the interval between transmissions of keep-alive packets upon determining that no acknowledgment of receipt of the previous keep-alive packet is received from the second node.

US Pat. No. 10,368,410

PWM CONTROL FOR LEDS WITH REDUCED FLICKER WHEN USING SPREAD SPECTRUM SWITCHING FREQUENCIES

Linear Technology Corpora...

1. A light emitting diode (LED) driver comprising:a PWM dimming circuit for receiving a dimming control signal, wherein the dimming circuit outputs a string of PWM pulses having pulse widths corresponding to the perceived brightness of at least one LED, where the PWM pulses control a first switch in series with the at least one LED using pulse width modulation;
a switching converter for supplying a regulated current or regulated voltage, the converter controlling at least a second switch at a switching frequency to supply the regulated current or regulated voltage to the at least one LED, the converter comprising a first oscillator for generating a first signal that controls the switching frequency;
a spread spectrum control (SSC) circuit configured to generate a varying second signal level, the varying second signal level being coupled to the first oscillator to control the first oscillator to vary the switching frequency during operation of the converter; and
a synchronizing circuit coupled to the SSC circuit for controlling the SSC circuit to generate substantially the same second signal level at a start of each PWM pulse in the string of PWM pulses while the pulse widths are constant, such that the switching frequency of the converter is forced to be substantially the same at the start of each PWM pulse while the pulse widths are constant.

US Pat. No. 10,122,413

POWER OVER DATA LINES SYSTEM USING VOLTAGE CLAMP IN PD FOR DETECTION OR CLASSIFICATION

Linear Technology Corpora...

1. A Power Over Data Lines (PoDL) system comprising:Power Source Equipment (PSE) coupled to a Powered Device (PD) via a wire pair, wherein differential data signals and DC power for operating the PD are transmitted over the same wire pair;
a PSE controller and a PD controller configured to carry out a low power handshaking phase over the wire pair, the handshaking phase providing a first signature signal from the PD to the PSE to identify whether the PD is compatible for receiving an operating voltage over the wire pair or to identify a particular voltage requirement of the PD or to identify a maximum power level of the PD;
a voltage limiting circuit across the wire pair that limits a voltage across the wire pair to a predetermined magnitude, wherein the voltage of the predetermined magnitude provides the first signature signal;
a current source in the PSE coupled to the wire pair for conducting a current through the voltage limiting circuit to cause the voltage limiting circuit to generate the first signature signal of the PD; and
a first detector in the PSE coupled to the wire pair and configured to detect the first signature signal on the wire pair to identify a particular voltage requirement of the PD or to identify a maximum power level of the PD.

US Pat. No. 10,218,394

ACTIVE DIFFERENTIAL RESISTORS WITH REDUCED NOISE

LINEAR TECHNOLOGY CORPORA...

1. An active differential resistor, comprising:an input node and an output node;
a field effect transistor (FET) having a drain coupled to the input node and a source coupled to the output node;
a first voltage source circuit coupled between the drain and the source of the FET; and
a second voltage source circuit coupled between a gate and the source of the FET, wherein the first and second voltage source circuits are configured to bias the FET into a saturation region, such that a Johnson-Nyquist noise of the active differential resistor is replaced by a shot noise.

US Pat. No. 10,256,867

POWER OVER DATA LINES SYSTEM PROVIDING A VARIABLE VOLTAGE TO POWERED DEVICE

Linear Technology Corpora...

1. A Power Over Data Lines (PoDL) system comprising:Power Source Equipment (PSE) coupled to a Powered Device (PD) via a wire pair, wherein differential data signals and DC power are transmitted over the same wire pair;
a variable voltage converter in the PSE coupled to receive an input voltage and output a regulated voltage;
a PSE controller and a PD controller configured to carry out a low power handshaking phase over the wire pair to at least identify whether the PD is compatible for receiving an operating voltage over the wire pair and to identify a particular voltage requirement of the PD, wherein voltages within a first voltage range are carried by the wire pair during the handshaking phase;
wherein the PSE controller is configured to control the variable voltage converter to output a voltage on the wire pair corresponding to the particular voltage requirement of the PD identified during the handshaking phase, wherein the particular voltage requirement of the PD is allowed to be below or within the first voltage range; and
an Undervoltage Lockout (UVLO) circuit in the PD configured to detect a DC voltage on the wire pair and determine whether the voltage is above a threshold voltage,
wherein the UVLO circuit is configured to couple the wire pair conducting a voltage above the threshold level to a PD load after the handshaking phase, and
wherein the UVLO circuit is configured to prevent coupling the wire pair conducting a voltage above the threshold level to the PD load if the voltage above the threshold level occurs during the handshaking phase.

US Pat. No. 10,177,580

ENERGY STORAGE DEVICE STACK BALANCING USING SWITCHED INDUCTOR BACKGROUND

Linear Technology Corpora...

1. An energy storage stack balancing circuit for balancing a set of serially connected energy storage devices, the balancing circuit comprising:an electronic switching system that controls a delivery of energy into and out of an inductor; and
a controller configured to control the electronic switching system so as to cause energy to be transferred from a selected one or more of the serially connected energy storage devices into the inductor, and then out of the inductor concurrently into a plurality of other energy storage devices in the serially connected energy storage devices.

US Pat. No. 10,313,139

POWER OVER DATA LINES SYSTEM WITH REDUNDANT POWER CONNECTIONS

Linear Technology Corpora...

1. A powered data communications system comprising:a master device having a first port and a second port, the master device being configured to apply a DC voltage from a voltage source to the first port;
a plurality of slave devices, each slave device having a third port and a fourth port;
conductors serially connecting the slave devices, via their third port and fourth port, to the master device in a ring between the first port and the second port of the master device, wherein a first end slave device is coupled to the first port of the master device, and a second end slave device is coupled to the second port of the master device, the conductors being configured to simultaneously carry the DC voltage and data;
the plurality of slave devices being configured to be sequentially powered up, starting with the first end slave device and ending with the second end slave device, by sequentially applying the DC voltage to an adjacent downstream slave device in a first direction around the ring by closing switches in the slave devices;
the slave devices and the master device being configured to perform a detection routine on the adjacent downstream slave device prior to applying the DC voltage to the adjacent downstream slave device; and
wherein the master device is configured to detect whether the DC voltage has been sequentially applied to all the slave devices by detecting a presence of the DC voltage at the second port of the master device and, if the master does not detect the presence of the DC voltage at the second port, the master device is configured to apply the DC voltage to both the first port and the second port to sequentially power up the slave devices in both the first direction and a second direction around the ring of the slave devices.

US Pat. No. 10,284,099

HYBRID POWER CONVERTERS COMBINING SWITCHED-CAPACITOR AND TRANSFORMER-BASED STAGES

Linear Technology Corpora...

1. A power converter comprising:a switched-capacitor power converter stage including first and second switches connected in series between an input node of the power converter and a ground node, wherein the second switch is directly connected between the first switch and the ground node; and
a pulse-width modulation (PWM) or resonant output circuit having a first input node connected to a switching node common to the first and second switches of the switched-capacitor power converter stage and having a second input node directly connected to the ground node,
wherein the PWM or resonant output circuit comprises:
a power transformer having an output winding inductively coupled to only a single input winding, and
two inductors, each respective inductor of the two inductors being coupled between a respective side of the output winding and an output power node of the PWM or resonant output circuit.

US Pat. No. 10,263,414

ADAPTIVE IN-RUSH CURRENT CONTROL FOR MINIMIZING MOSFET PEAK TEMPERATURE UPON VOLTAGE STEP

Linear Technology Corpora...

1. A method for controlling a pass MOSFET between an input voltage and a load when there is an input voltage step between a source and drain of the MOSFET, wherein a bypass capacitor is connected in parallel with the load and charges during the voltage step, the method comprising:setting an in-rush current through the MOSFET so that the charging current of the bypass capacitor due to the voltage step has a fixed ratio to the load current;
determining when the bypass capacitor is sufficiently charged; and
setting a current limit, different from the in-rush current, after it has been determined that the bypass capacitor has been sufficiently charged.

US Pat. No. 10,261,477

DETECTION AND CLASSIFICATION SCHEME FOR POWER OVER ETHERNET SYSTEM

Linear Technology Corpora...

1. Power Sourcing Equipment (PSE) for use with a Powered Device (PD) connected to the PSE by at least Ethernet wires to receive data and voltage, the PD comprising a first circuit electrically coupled to input terminals of the PD, wherein the first circuit has characteristics, wherein the first circuit responds in a predetermined manner to a first signal generated by the PSE to create a second signal, and wherein the first circuit is selected to convey particular Power over Ethernet (PoE) requirements of the PD, the PSE comprising:a DC power source for generating a PoE voltage for transmission on the Ethernet wires to power the PD;
a first signal generator for providing the first signal on the Ethernet wires to the input terminals of the PD at a particular time, wherein the first signal is applied to the first circuit in the PD;
a first detector for detecting a ramping analog amplitude of the resulting second signal, generated by the first circuit in the PD, in response to the first signal and during application of the first signal to the first circuit in the PD; and
a processing circuit configured for detecting a magnitude of the ramping amplitude of the second signal, while the second signal is ramping, after an elapsed time and, in response to the detected magnitude after the elapsed time, associating the second signal with the particular PoE requirements of the PD, and controlling the PSE to supply power to the PD via the Ethernet wires consistent with the PoE requirements of the PD conveyed by the second signal.

US Pat. No. 10,263,794

MAINTAIN POWER SIGNATURE CONTROLLER AT POWER INTERFACE OF POE OR PODL SYSTEM

Linear Technology Corpora...

1. A Powered Device (PD) for use in a system for supplying power and differential data over at least one wire pair, wherein DC power is supplied by a Power Sourcing Equipment (PSE) to the PD via the at least one wire pair, and wherein the PSE is configured to cease providing the DC voltage on the at least one wire pair if a current drawn by the PD is below a first threshold current, the PD comprising:a first DC de-coupling circuit in the PD coupled to the at least one wire pair for de-coupling a DC voltage from the at least one wire pair;
a first full bridge rectifier in the PD coupled to receive the DC voltage from the first DC de-coupling circuit and output a predetermined polarity of the DC voltage; and
a first current source in the PD having at least a first terminal coupled to the at least one wire pair between the first DC de-coupling circuit and the first full bridge rectifier, and
wherein the first current source is configured to draw current from the at least one wire pair above the first threshold current even if a PD load downstream from the first full bridge rectifier draws a current less than the first threshold current.

US Pat. No. 10,152,111

LOW POWER TIMING, CONFIGURING, AND SCHEDULING

Linear Technology Corpora...

1. A network device, comprising:a network interface circuit;
a microprocessor;
a timing circuit configured to, based on a primary timing signal, generate an output time signal and switch the network device from an inactive state to an active state when a predetermined length of time for a packet transmission slot is reached; and
a microsequencer circuit configured to, in response to the network device being switched to the active state, activate and configure the network interface circuit for the packet transmission, independent of the microprocessor and delays encountered by the microprocessor.

US Pat. No. 10,382,005

COMMUNICATIONS SYSTEM USING HYBRID COMMON MODE CHOKE AND KELVIN SENSING OF VOLTAGE

Linear Technology Corpora...

5. A system for filtering AC common mode signals from a pair of wires carrying differential data comprising:a first port having two first terminals coupled to a transceiver that receives the differential data;
a second port having two second terminals coupled to the pair of wires;
a third port having two third terminals connected to AC termination circuitry;
a DC voltage source coupled to the pair of wires via a DC-coupling circuit, wherein the DC voltage source also acts as the AC termination circuitry;
a common mode choke (CMC) coupled between the second port and the first port, the CMC comprising a first transformer with two windings having the same polarity; and
a differential mode choke (DMC) coupled between the first port and the third port, the DMC comprising a second transformer with two windings having opposite polarities,
wherein the CMC attenuates the AC common mode signals on the pair of wires and substantially passes the differential data, and
wherein the DMC substantially passes the AC common mode signals that pass through the CMC from the pair of wires and applies the AC common mode signals to the termination circuitry to further attenuate the AC common mode signals prior to being received by the transceiver.

US Pat. No. 9,525,351

INDUCTOR CURRENT SENSING IN A BUCK CONVERTER USING MULTIPLE FILTERS

Linear Technology Corpora...

1. A circuit comprising:
at least one switch in a voltage regulator switching at a duty cycle to supply current through an inductor to generate a target
output voltage;

a current sense circuit that generates a current sense signal that is substantially proportional to the current through the
inductor, the current sense circuit comprising:

a first portion detecting the actual current through the inductor, the first portion outputting a signal having a first AC
component and a first DC component;

a first low pass filter passing the first DC component and attenuating the first AC component;
a second portion detecting a substantially rectangular waveform corresponding to the duty cycle of the regulator;
a first high pass filter passing a second AC component of the substantially rectangular waveform and blocking a second DC
component of the substantially rectangular waveform, wherein the second AC component is substantially proportional to a ramping
current through the inductor, and wherein an amplitude of the second AC component is greater than an amplitude of the first
AC component; and

a summing node summing the second AC component, the first DC component, and the first AC component for filtering by the first
low pass filter,

wherein an output of the first low pass filter comprises the first DC component summed with an attenuated second AC component
to provide a signal substantially proportional to the actual current through the inductor with reduced switching noise.

US Pat. No. 9,472,304

CONFIGURING SIGNAL-PROCESSING SYSTEMS

Linear Technology Corpora...

1. A configurable signal-processing circuit that provides a plurality of selectable signal-processing operations, the configurable
signal-processing circuit comprising a configuration circuit to detect an externally applied timing pattern for inputting
an input signal and outputting an output signal to and from the configurable signal processing-processing circuit, the configuration
circuit providing a configuration code responsive to the timing pattern that selects a first signal-processing operation from
among the plurality of selectable signal-processing operations.