US Pat. No. 10,128,250

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

LONGITUDE LICENSING LIMIT...

1. A semiconductor device comprising:a semiconductor substrate;
a plurality of first insulating films for element isolation, each of which is embedded in a main surface of the semiconductor substrate and extends in a first direction;
a plurality of second insulating films for element isolation, each of which is embedded in the main surface of the semiconductor substrate and extends in a second direction intersecting the first direction, and which, in conjunction with the plurality of first insulating films for element isolation, demarcate a plurality of first active regions disposed in a matrix formation, wherein the plurality of second insulating films extend to a first vertical height relative to the semiconductor substrate;
first and second word trenches which are provided extending in the second direction in the main surface of the semiconductor substrate, and which are disposed between two of the plurality of second insulating films for element isolation that are adjacent to one another in the first direction;
first and second word lines, embedded respectively in lower portions of the first and second word trenches, with the interposition of gate insulating films;
first and second embedded insulating films disposed respectively over first and second word lines, wherein the first and second embedded insulating films extend to a second vertical height relative to the semiconductor substrate, and the second vertical height is greater than the first vertical height;
first impurity-diffused layers provided between the first word lines and the second word lines;
second impurity-diffused layers provided between the first word lines and one of said two second insulating films for element isolation; and
third impurity-diffused layers provided between the second word lines and the other of said two second insulating films for element isolation;
wherein the first and second word trenches are formed in self-alignment relative to the plurality of second insulating films for element isolation so that a first width between one second insulating film of the plurality of second insulating films and the first word line trench is substantially equal to a second width between another second insulating film of the plurality of second insulating films and the second word trench.

US Pat. No. 10,128,149

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

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1. A method of manufacturing a semiconductor device, comprising:forming an interlayer insulating film above a semiconductor substrate;
forming in the interlayer insulating film an electrically conductive plug, the upper surface of which forms the same plane as the upper surface of the interlayer insulating film such that the interlayer insulating film is planarized;
forming a first titanium film directly on the interlayer insulating film and directly on the electrically conductive plug;
forming an aluminum diffusion-preventing film on the first titanium film;
forming a second titanium film on the aluminum diffusion-preventing film;
forming an aluminum film on the second titanium film; and
forming a wiring line by employing etching to shape the aluminum film, the second titanium film, the aluminum diffusion-preventing film, and the first titanium film so that in a cross-section including a bottom surface of the first titanium film, the bottom surface of the first titanium film that contacts the electrically conductive plug only contacts the electrically conductive plug.

US Pat. No. 10,115,693

SOLDER LAYER OF A SEMICONDUCTOR CHIP ARRANGED WITHIN RECESSES

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1. A semiconductor chip comprising:a semiconductor substrate;
a plurality of bump electrodes provided on one face side of said substrate;
a plurality of recesses provided on the other face side of said substrate;
a solder layer arranged within said recesses, wherein said recesses are formed so as to have a smaller aperture area from said other face side of said substrate towards said one face side thereof, and wherein the solder layer completely fills said recesses; and
a circuit forming layer disposed between the solder layer and the plurality of bump electrodes.

US Pat. No. 10,181,347

SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM

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1. A data processing system comprising:a semiconductor device; and
a controller connected to the semiconductor device, the controller being configured to issue a command, wherein the semiconductor device comprises:
a plurality of core chips; and
an interface chip configured to issue a read command to the plurality of core chips after receiving the command from the controller,
wherein each core chip of the plurality of core chips comprises:
an output terminal; and
a data output circuit configured to output read data to the output terminal in response to the read command, the read data being output in accordance with an output timing signal, wherein the output timing signal is indicative of an adjusted output period from reception of the read command to outputting of the read data by any one of the plurality of core chips; and
wherein the interface chip comprises:
an input terminal electrically connected to one of the output terminals; and
a data input circuit configured to receive, via the input terminal and in accordance with an input timing signal, the read data supplied from the at least one of the plurality of output terminals of the core chips, wherein the input timing signal is indicative of an adjusted input period from issuance of the read command to capture, from the input terminal, the read data received from any one the plurality of core chips.

US Pat. No. 10,126,765

SEMICONDUCTOR DEVICE HAVING INTERNAL VOLTAGE GENERATING CIRCUIT

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1. A method for controlling a charge pump comprising:alternatively charging a first capacitor to a first voltage difference and discharging the first capacitor by applying a second voltage to a first electrode of the first capacitor to generate a third voltage greater in absolute value than the first voltage difference and greater in absolute value than the second voltage on a second electrode of the first capacitor in an active state of the charge pump; and
applying a fourth voltage difference less than the first voltage difference to the first capacitor in a standby state of the charge pump, wherein applying the fourth voltage difference comprises applying a fourth voltage to a first end of the first capacitor and a fifth voltage to a second end of the first capacitor, and the fourth voltage and fifth voltage are greater than zero.

US Pat. No. 10,314,165

SEMICONDUCTOR DEVICE

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1. A semiconductor device comprising:a wiring substrate;
a first semiconductor chip installed on one surface of the wiring substrate, the first semiconductor chip having a first edge and a second edge opposite to the first edge;
a second semiconductor chip stacked on the first semiconductor chip so that the second semiconductor chip crosses over the first edge and the second edge of the first semiconductor chip and a portion of a surface of the first semiconductor chip is exposed, wherein the second semiconductor chip is the top most semiconductor chip in the package:
a warp regulating member disposed directly on the exposed portion of the surface, wherein the warp regulating member comprises a first edge that aligns with the first edge of the first semiconductor chip and a second edge that aligns with the second edge of the first semiconductor chip and the warp regulating member covers a majority of the exposed portion of the surface: and
a sealing body formed on the wiring substrate to cover the first semiconductor chip, the second semiconductor chip, and the warp regulating member;
wherein the warp regulating member is a highly-resilient body having a modulus of elasticity higher than that of the sealing body.

US Pat. No. 10,147,478

SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM

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1. A controller, comprising:a first external terminal configured to output a data strobe signal to a semiconductor device, the data strobe signal changing to a first logic level during a preamble period of time to indicate an initiation of a data transfer;
a second external terminal configured to output a data signal to the semiconductor device; and
a plurality of third external terminals configured to output a mode register command to the semiconductor memory device, the mode register command indicating a first period of time, the first period of time being a period of time during the preamble period for which the data strobe signal remains at the first logic level.

US Pat. No. 10,147,477

SYSTEM, METHOD, AND CONTROLLER FOR SUPPLYING ADDRESS AND COMMAND SIGNALS AFTER A CHIP SELECT SIGNAL

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1. A controller for controlling operation of a memory device, the controller comprising:an output circuit configured to:
supply a chip select signal, an address signal, a command signal, and a clock signal to the memory device; and
a data processing circuit configured to process read data and write data through a data terminal based on the chip select signal, the address signal, the command signal, and the clock signal supplied by the output circuit;
wherein the controller is configured to supply the address signal and the command signal to the memory device a predetermined duration after the output circuit supplies the chip select signal.

US Pat. No. 10,342,118

SEMICONDUCTOR DEVICE

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1. A semiconductor device comprising:a wiring substrate;
a first semiconductor chip installed on one surface of the wiring substrate, the first semiconductor chip having a first edge and a second edge opposite to the first edge;
a second semiconductor chip stacked on the first semiconductor chip so that the second semiconductor chip crosses over the first edge and the second edge of the first semiconductor chip and a portion of a surface of the first semiconductor chip is exposed, wherein the second semiconductor chip is the top most semiconductor chip in the package:
a warp regulating member disposed directly on the exposed portion of the surface, wherein the warp regulating member comprises a first edge that aligns with the first edge of the first semiconductor chip and a second edge that aligns with the second edge of the first semiconductor chip and the warp regulating member covers a majority of the exposed portion of the surface: and
a sealing body formed on the wiring substrate to cover the first semiconductor chip, the second semiconductor chip, and the warp regulating member;
wherein the warp regulating member is a highly-resilient body having a modulus of elasticity higher than that of the sealing body.

US Pat. No. 10,200,044

SEMICONDUCTOR DEVICE HAVING IMPEDANCE CALIBRATION FUNCTION TO DATA OUTPUT BUFFER AND SEMICONDUCTOR MODULE HAVING THE SAME

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1. A semiconductor device comprising:a data terminal;
a calibration terminal;
a first power supply line configured to be supplied with a first power supply potential;
a second power supply line configured to be supplied with a second power supply potential;
a first transistor unit coupled between the first power supply line and the data terminal;
a plurality of second transistor units coupled between the second power supply line and the calibration terminal, wherein each second transistor unit of the plurality of second transistor units comprises a plurality of transistors coupled to a resistor, the plurality of transistors and the resistor are not shared with other second transistor units, and the plurality of second transistor units are connected in parallel to each other so that an impedance of each of the second transistor units is adjustable using an impedance code; and
an impedance control circuit configured to adjust the impedance of each of the second transistor units so that a potential of the calibration terminal matches a reference potential, the impedance control circuit reflecting the impedance of one of the second transistor units to the first transistor unit; and
wherein the reference potential is different in potential level from an intermediate potential between the first power supply potential and the second power supply potential.

US Pat. No. 10,311,939

SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM

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1. A method for transferring data from a first semiconductor device to a second semiconductor device, the method comprising:transferring preamble length information from the second semiconductor device to the first semiconductor device;
storing the preamble length information in a register in the first semiconductor device;
transferring a clock signal from the second semiconductor device to the first semiconductor device;
switching between a Delay Lock Loop (DLL) selection mode in which a DLL circuit is activated and a DLL non-selection mode in which the DLL circuit is not activated;
transferring, from the first semiconductor device to the second semiconductor device, a preamble having a duration specified by the preamble length information followed by a toggle signal having a burst length; and
transferring, from the first semiconductor device to the second semiconductor device, data in synchronization with the toggle signal;
wherein in the DLL selection mode, transferring the toggle signal further comprises:
phase adjusting the toggle signal to the clock signal using the DLL circuit; and
in the DLL non-selection mode, transferring the toggle signal comprises:
transferring the toggle signal with the clock signal as a reference.