US Pat. No. 9,172,265

BATTERY CHARGER, VOLTAGE MONITORING DEVICE AND SELF-DIAGNOSIS METHOD OF REFERENCE VOLTAGE CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. A battery charger comprising:
a first reference voltage generating circuit that outputs a first reference voltage and a first divided voltage generated
by dividing the first reference voltage;

a second reference voltage generating circuit that outputs a second reference voltage and a second divided voltage generated
by dividing the second reference voltage;

an A/D converter that includes a reference voltage input section and an A/D conversion voltage input section; and
a switching section that supplies the first reference voltage or the second reference voltage to the reference voltage input
section and that supplies one of the first divided voltage, the second divided voltage and a voltage from a battery cell to
the A/D conversion voltage input section.

US Pat. No. 9,525,382

OSCILLATION CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. An oscillation circuit, comprising:
an electrical current generating portion configured to generate an electrical current having an oscillation frequency decreasing
as an amplitude thereof is decreased, said electrical current generating portion including an inverter having a first input
terminal and a first output terminal, said inverter configured to invert a level of a voltage input into the first input terminal
so that the inverter outputs the voltage from the first output terminal;

a control voltage generating portion configured to generate a control voltage having a magnitude decreasing as a magnitude
of a power source voltage is decreased;

an RC circuit connected to the first output terminal of the inverter, said RC circuit including a capacitor charging or discharging
the electrical current;

a Schmitt trigger circuit configured to receive a terminal voltage from the capacitor as an input voltage, and to supply an
output voltage to the first input terminal of the inverter; and

an electrical current control portion,
wherein said electrical current control portion includes a second input terminal connected to the electrical current generating
portion for receiving the electrical current; a control terminal connected to the control voltage generating portion for receiving
the control voltage; and a second output terminal, and

said electrical current control portion is configured to reduce the amplitude of the electrical current flowing between the
second input terminal and the second output terminal as the magnitude of the control voltage is decreased.

US Pat. No. 9,129,966

SEMICONDUCTOR DEVICE

LAPIS Semiconductor Co., ...

16. A semiconductor device comprising:
a semiconductor chip which includes a semiconductor substrate and a semiconductor circuit formed on said semiconductor substrate;
an electrode pad that is formed on said semiconductor chip and electrically connected to said semiconductor circuit;
a plurality of insulating layers and a plurality of wiring layers layered on said semiconductor chip and said electrode pad;
a first lower-side wiring path;
a first upper-side wiring path formed above said first lower-side wiring path, said first upper-side wiring path having a
wiring width narrower than a wiring width of said first lower-side wiring path;

a second lower-side wiring path formed in a same layer in which said first lower-side wiring path is formed;
a second upper-side wiring path formed above said second lower side wiring path, said second upper-side wiring path having
a wiring width wider than a wiring width of said second lower-side wiring path; and

at least one of said plurality of insulating layers which is formed between said first lower-side wiring path and said first
upper-side wiring path and between said second lower-side wiring path and said second upper-side wiring path,

wherein the insulating layers include three or more insulating layers and further include at least one more wiring layer,
said first lower-side wiring path and said second lower-side wiring path are formed on one or more of said plurality of insulating
layers;

at least one of said first lower-side wiring path and said second lower-side wiring path is electrically connected to said
electrode pad; and

said first upper-side wiring path and said second upper-side wiring path are formed on said plurality of insulating layers.


US Pat. No. 9,184,738

PWM (PULSE WIDTH MODULATION) SIGNAL OUTPUTTING CIRCUIT AND METHOD OF CONTROLLING OUTPUT OF PMW SIGNAL

Lapis Semiconductor Co., ...

1. A PWM (Pulse Width Modulation) signal outputting circuit, comprising:
a counting unit for counting a number of clocks to output a counter value, and for resetting the counter value to resume counting
when a reset signal is input to the counting unit;

a dead time value storage unit for storing a dead time value; and
a plurality of PWM signal outputting units for setting a start setting value and a termination setting value, each of the
PWM signal outputting units being configured to generate a termination signal and a start signal, each of said PWM signal
outputting units being configured to output a PWM signal, which is raised according to the start signal generated by itself
and is decreased according to the termination signal generated by itself, each of said PWM signal outputting units being configured
to generate the termination signal when the counter value matches to the termination setting value generated by itself,

wherein said PWM signal outputting units includes a front stage PWM signal outputting unit for generating the PWM signal that
is raised first, and a later stage PWM signal outputting unit for generating the PWM signal that is raised next after the
PWM signal that is raised first,

said later stage PWM signal outputting unit is configured to generate the start signal when a sum of the termination setting
value generated by the front stage PWM signal outputting unit and the dead time value matches to the counter value, and when
a difference between the start setting value generated by itself and the termination setting value generated by the front
stage PWM signal outputting unit is smaller than the dead time value,

said later stage PWM signal outputting unit is configured to generate the start signal when the start setting value generated
by itself matches to the counter value, and when the difference is greater than the dead time value,

said front stage PWM signal outputting unit is configured to generate the start signal when the dead time value matches to
the counter value, and when the start setting value generated by itself is smaller than the dead time value, and

said front stage PWM signal outputting unit is configured to generate the start signal when the start setting value generated
by itself matches to the counter value, and when the start setting value generated by itself is greater than the dead time
value.

US Pat. No. 9,143,247

WIRELESS COMMUNICATION METHOD AND APPARATUS

LAPIS SEMICONDUCTOR CO., ...

1. A wireless communication method for performing wireless communication by using a wireless signal, the wireless communication
method comprising:
an intensity indication data generation step of successively generating intensity indication data each indicating an instantaneous
radio wave intensity value of a received wireless signal;

a first data capturing and retaining step of causing a plurality of registers to intermittently capture and retain the instantaneous
radio wave intensity values indicated by each of the intensity indication data;

a first average calculation step of calculating an average of the instantaneous radio wave intensity values retained by the
plurality of registers;

a comparison step of comparing said average with a threshold;
a control step of enabling a wireless transmission operation when the average is less than or equal to the threshold;
a second data capturing and retaining step of, after said first average calculation step and upon detecting by said comparison
step that the average exceeds the threshold, causing one of the plurality of registers to capture and retain another instantaneous
radio wave intensity value of the received wireless signal; and

a second average calculation step of, upon detecting by said comparison step that the average exceeds the threshold, re-calculating
the average using the values retained by the plurality of registers after said second data capturing and retaining step, wherein

the first average calculation step includes calculating the average with a frequency corresponding to a frequency of capturing
the intensity indication data by the first data capturing and retaining step, and

the comparison step includes comparing the average with the threshold at a frequency corresponding to a frequency of calculation
of the average.

US Pat. No. 9,103,890

SEMICONDUCTOR CIRCUIT, BATTERY MONITORING SYSTEM, AND DIAGNOSIS METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor circuit comprising:
a plurality of input terminals respectively connected to a connection part of each of a plurality of serially connected batteries;
a plurality of switches each including a first end and a second end, the first ends of the plurality of switches respectively
connected to each of the plurality of input terminals;

a plurality of power supply lines each including a first end and a second end, the first ends of the plurality of power lines
respectively connected to each of second ends of the plurality of switches;

a selection unit to which the second ends of the plurality of power lines are connected and that selects two power supply
lines from the plurality of power supply lines;

a measurement unit that comprises an analogue signal to digital signal conversion unit and that, when input with respective
electrical signals flowing in the two power supply lines selected by the selection unit, converts a difference between the
electrical signals flowing in the two power supply lines into a digital signal and outputs the digital signal;

a computation unit that performs a predetermined computation on the digital signal output from the measurement unit and outputs
an electrical signal corresponding to a result of the computation; and

a control unit that performs
first control processing that controls the selection unit such that a set of input terminals and the selection unit are electrically
disconnected using the corresponding switches and selection is made from the plurality of power supply lines of a power supply
line in which an electrical signal corresponding to a first reference voltage flows and a power supply line in which an electrical
signal corresponding to a second reference voltage different from the first reference voltage flows, and

second control processing that controls the measurement unit such that an electrical signal corresponding to the second reference
voltage is converted into a digital signal and output.

US Pat. No. 9,099,026

SOURCE DRIVER IC CHIP

LAPIS Semiconductor Co., ...

1. A source driver IC chip configured to apply a driving pulse having a first gradation voltage based on a first gamma characteristic
and a driving pulse having a second gradation voltage based on a second gamma characteristic to respective source lines formed
on a display panel in response to a video signal, said source driver IC chip comprising:
a first external terminal for receiving a first power supply voltage;
a second external terminal for receiving a second power supply voltage;
a reference gradation voltage generating part configured to generate a reference gradation voltage based on said first gamma
characteristic or a reference gradation voltage based on said second gamma characteristic based on said first power supply
voltage inputted through said first external terminal and said second power supply voltage inputted through said second external
terminal;

a third external terminal for externally outputting said reference gradation voltage generated in said reference gradation
voltage generating part;

a fourth external terminal for receiving said first reference gradation voltage based on said first gamma characteristic;
a fifth external terminal for receiving said second reference gradation voltage based on said second gamma characteristic;
a first gradation voltage generating part configured to generate said first gradation voltage based on said first reference
gradation voltage inputted through said fourth external terminal; and

a second gradation voltage generating part configured to generate said second gradation voltage based on said second reference
gradation voltage inputted through said fifth external terminal.

US Pat. No. 9,099,027

DISPLAY PANEL DRIVING DEVICE HAVING PLURAL DRIVER CHIPS RESPONSIVE TO CLOCK SIGNAL WITH STABLE DUTY RATIO

LAPIS SEMICONDUCTOR CO., ...

1. A display panel driving device for use with a display panel having a plurality of signal lines and a plurality of scan
lines, with a plurality of pixel units being formed at crossing portions of the signal lines and scan lines, said display
panel driving device comprising:
a signal line driver that applies, on the basis of an input image signal, a pixel driving voltage to each of said signal lines,
wherein said signal lines are grouped into a plurality of signal line groups, said signal line driver includes a plurality
of driver chips, which are associated with the plurality of signal line groups respectively, and the driver chips are connected
in cascade through a clock line;

each said driver chip includes a pixel driving voltage generation unit and a clock transmission unit, the pixel driving voltage
generation unit applies the pixel driving voltage to each of those signal lines which belong to the associated signal line
group at a timing corresponding to a clock signal supplied via said clock line, and the clock transmission unit transmits
the clock signal supplied via said clock line to a subsequent one of said driver chips via said clock line; and

said clock transmission unit includes a ½ frequency division circuit, a delay circuit and an Exclusive NOR gate such that
the ½ frequency division circuit generates a frequency-divided clock signal by half-dividing a cycle of said clock signal
supplied, the delay circuit generates a delayed frequency-divided clock signal by delaying the frequency-divided clock signal
by a predetermined delay time, and the Exclusive NOR gate generates a shaped clock signal having a first level and a second
level, the shaped clock signal has the first level in a period when a logic level of said delayed frequency-divided clock
signal is equal to a logic level of said frequency-divided clock signal, the shaped clock signal has the second level in a
period when the logic levels are different, and the Exclusive NOR gate transmits the shaped clock signal having the first
and second levels to said subsequent driver chip via said clock line, said shaped clock signal being shaped to the same waveform
as said clock signal introduced to the ½ frequency division circuit,

wherein the delay circuit includes a plurality of inverters that are connected in series and each of the inverters includes
a pair of first FETs have a first conductivity type channel, with a drain of one of the first FETs being connected to a source
of the other first FET at a first connection point, gates of the first FETs being connected together at an input point, a
first potential being applied to a source of said one of the first FETs, and a drain of said other first FET being connected
to an output point,

a pair of second FETs having a second conductivity type channel, with a drain of one of the second FETs being connected to
a source of the other second FET at a second connection point, gates of the second FETs being connected together at said input
point, a second potential being applied to a source of said one of the second FETs, and a drain of said other second FET being
connected to said output point,

a first additional FET that applies said second potential to said first connection point when said output point is at said
second potential,

a second additional FET that applies said first potential to said second connection point when said output point is at said
first potential,

a third additional FET that is always in an on condition and applies said second potential to said first additional FET,
a fourth additional FET that is always in an on condition and applies said first potential to said second additional FET,
a fifth additional FET whose drain is connected to a gate of said third additional FET, with said first potential being applied
to a source of the fifth additional FET,

a sixth additional FET whose gate and drain are both connected to a gate of said fifth additional FET, with said second potential
being applied to a source of the sixth additional FET,

a seventh additional FET whose drain is connected to a gate of said fourth additional FET, with said second potential being
applied to a source of the seventh additional FET, and

an eighth additional FET whose gate and drain are both connected to a gate of said seventh additional FET, with said first
potential being applied to a source of the eighth additional FET.

US Pat. No. 9,128,914

SEMICONDUCTOR INTEGRATED CIRCUIT

LAPIS Semiconductor Co., ...

1. A semiconductor integrated interface circuit, comprising:
a plurality of processing parts which respectively process data appearing on a plurality of bus lines;
a receiving part for receiving packets;
a distributing part for distributing the received packets in accordance with destinations contained in the received packets;
a plurality of accumulating parts for accumulating the packets provided from the distributing part;
a plurality of relaying parts for converting the packets accumulated in the accumulating parts into data, and relaying the
converted data to said processing parts in response to a relay permission command assigned thereto; and

an output controlling part for supplying the relay permission command to a corresponding one of said relaying parts when the
distributed packet is determined as a relay permission packet based on packet identification information contained in the
distributed packet from said distributing part;

wherein said processing parts respectively generate communication data used for debugging, in accordance with the relayed
data from the corresponding relaying parts, and output said communication data to a succeeding stage with a debugging function;
wherein
the plurality of bus lines includes a first inner bus line and a second inner bus line;
said distributing part distributes the relay permission packet to the first inner bus line;
said output controlling part supplies the relay permission command to accumulating parts connected to the second inner bus
line; and

a processing part of the plurality of processing parts receives readout data from a bus line of the plurality of bus lines,
and transmits the received readout data to the outside as communication data according to a communication protocol.

US Pat. No. 9,148,185

FILTER CIRCUIT AND RECEIVING APPARATUS

LAPIS SEMICONDUCTOR CO., ...

1. A filter circuit for receiving an input frequency signal including signal components corresponding to a plurality of channels
having respective different frequency bands and for extracting a signal component corresponding to a desired channel from
said input frequency signal, the filter circuit comprising:
a first filter which performs filtering on the input frequency signal with such a band-pass characteristic that the frequency
band of the desired channel is included in a passband, thereby obtaining a pass frequency signal; and

a second filter which performs filtering on the pass frequency signal with such a filter characteristic that a signal level
of a frequency band of a channel adjoining the desired channel is attenuated,

wherein an attenuation band of said second filter is included in a frequency band of an attenuation band of said first filter.

US Pat. No. 9,128,831

ELECTRICAL DEVICE AND METHOD OF SETTING ADDRESS

LAPIS SEMICONDUCTOR CO., ...

1. An electrical device configured to add reliability check data to communication data so that the electrical device performs
data communication, comprising:
a plurality of apparatus connected with a daisy chain connection through a communication line so that the apparatus communicate
with each other through the communication line; and

a control unit connected to the apparatus so that the control unit is configured to communicate with the apparatus,
wherein one of said apparatus includes an address storage unit for storing an address of the one of the apparatus,
said one of the apparatus includes an address setting unit for adding a specific number to the address of the one of the apparatus
stored in the address storage unit to generate a new address of the one of the apparatus when the one of the apparatus receives
an address addition instruction,

said one of the said apparatus further includes an address setting data transmission control unit for transmitting the address
addition instruction to a later stage apparatus when the address setting unit adds a specific value to the address of the
one of the apparatus,

said one of the apparatus further includes a first transmission reception unit for receiving first data and a second transmission
reception unit for transmitting second data, and

said second transmission reception unit includes a first terminal for receiving third data output from the first transmission
reception unit and a second terminal for receiving fourth data output from the address setting data transmission control unit
so that the fourth data are preferentially processed relative to the third data.

US Pat. No. 9,099,536

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A method of producing a semiconductor device comprising the steps of:
preparing a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface,
said semiconductor substrate including a first conductive layer formed on the second main surface;

forming a through hole in the semiconductor substrate so that the through hole penetrates through the semiconductor substrate
from the first main surface to the second main surface, said first conductive layer being exposed at a bottom portion of the
through hole;

forming a seed layer in the through hole and on the first main surface so that the seed layer is disposed on a side surface
of the through hole from the bottom portion of the through hole to the first main surface;

forming a second conductive layer in the through hole so that the second conductive layer is disposed on the seed layer formed
in the through hole and on the first main surface through a first plating process;

forming a resist on the second conductive layer;
performing a developing process to form an opening portion in the resist so that the second conductive layer in the through
hole and on the first main surface is continuously exposed in the opening portion; and

forming a third conductive layer on the second conductive layer formed in the through hole and on the first main surface according
to the resist with the opening portion formed therein.

US Pat. No. 9,256,556

RAM MEMORY DEVICE CAPABLE OF SIMULTANEOUSLY ACCEPTING MULTIPLE ACCESSES

LAPIS SEMICONDUCTOR CO., ...

1. A RAM memory device comprising:
a RAM that writes or reads data in synchronization with a clock signal in response to either a first access or a second access;
a flash side interface adapted to relay the first access including a first control signal and being supplied from a flash
interface;

a processor side interface adapted to relay the second access including a second control signal and being supplied from a
processor;

a RAM control signal storage that stores the second access having been relayed by the processor side interface in response
to the first control signal; and

a multiplexer adapted to supply the first access having been relayed by the flash side interface to the RAM within one cycle
of the clock signal in response to the first control signal, and to supply the second access which is stored in the RAM control
signal storage to the RAM in or after a next cycle succeeding to said one cycle.

US Pat. No. 9,287,261

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a semiconductor substrate of one conductivity type;
an element isolation region in one principal face of the semiconductor substrate, and an element region surrounded by the
element isolation region;

a gate dielectric film on the one principal face of the semiconductor substrate;
a gate electrode that is formed on the gate dielectric film so as to extend from the element region to the element isolation
region at both sides of the element region in a gate width direction, each end portion in the gate width direction of the
gate electrode being located on the element isolation region via the gate dielectric film and including a portion located
at a first distance from a boundary between the element isolation region in proximity to the end portion and the element region,
and a plurality of protruding portions located at a second distance from the boundary that is longer than the first distance,
and the plurality of protruding portions sandwiching the portion located at the first distance;

first and second impurity regions of the one conductivity type respectively provided in the one principal face in two end
regions of the element region in the gate width direction, the two end regions contacting the element isolation region, the
first and second impurity regions of the one conductivity type being respectively separated from both ends of the gate electrode
in the gate length direction; and

first and second impurity regions of an opposite conductivity type respectively formed in the element region at both sides
of the gate electrode in the gate length direction.

US Pat. No. 9,185,817

DISPLAY PANEL

LAPIS SEMICONDUCTOR CO., ...

1. A display panel comprising:
a panel body of a rectangular shape including a display section;
a rectangular driver IC, provided within a region between the display section and a panel end portion of the panel body and
disposed with the display section in a longitudinal direction, which drives the display section;

a first input terminal group in which input terminals are disposed at intervals along a first long side of the rectangular
driver IC that faces the panel end portion, and to which input signals are input from outside of the display panel;

a second input terminal group in which input terminals are disposed at intervals along a second long side of the rectangular
driver IC that faces the display section, and to which input signals are input from outside of the display panel;

a first wiring group that is connected at one end to the first input terminal group, that is formed on the panel body between
the rectangular driver IC and the panel body, that includes a portion of first wiring passing under a first short side of
the rectangular driver IC and that extends out from between the rectangular driver IC and the panel body to connect at another
end to a CPU; and

a second wiring group that is connected at one end to the second input terminal group, that is formed on the panel body between
the rectangular driver IC and the panel body, that passes under the second long side of the rectangular driver IC and that
extends out from between the rectangular driver IC and the panel body to connect at another end to the CPU.

US Pat. No. 9,368,571

TRENCH ISOLATION STRUCTURE HAVING ISOLATING TRENCH ELEMENTS

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a semiconductor substrate;
an element isolating trench structure that includes an element isolating trench formed in one main surface of the semiconductor
substrate;

element formation regions; and
semiconductor elements that are formed in the element formation regions,
wherein a boundary between a first element formation region from among the element formation regions and the element isolating
trench is separated by

(A) a first side extending in a first direction from a first point,
(B) a second side extending in a second direction from the first point to a second point, the second direction being inclined
at an angle ? (0°
(C) a third side extending in the first direction from the second point,
wherein the first element formation region is disposed between the first side and the third side, and wherein
a boundary between a second element formation region from among the element formation regions and the element isolating trench
is separated by

(D) a fourth side facing the second side across the element isolating trench and extending in the second direction, and
(E) a fifth side being disposed on a line passing through an end point of the fourth side and extending in the first direction.

US Pat. No. 9,293,402

DEVICE WITH PILLAR-SHAPED COMPONENTS

LAPIS SEMICONDUCTOR CO., ...

1. A device with pillar-shaped post electrodes, comprising:
a substrate;
a wiring layer disposed on the substrate; and
the pillar-shaped post electrodes disposed on the wiring layer, each of the pillar-shaped post electrodes having a bottom
surface connected to the wiring layer, a top surface opposed to the bottom surface, and a lateral face part extending from
the bottom surface to the top surface to connect the bottom surface and the top surface,

wherein each of the pillar-shaped post electrodes is an integrated pillar-shaped electrode which is a single-body structure
electrode comprising directly-joined first and second pillar-shaped parts, and

wherein
the first pillar-shaped part is formed by plating,
the second pillar-shaped part is formed on the first pillar-shaped part by plating,
a lateral face of the first pillar-shaped part and a lateral face of the second pillar-shaped part form the lateral face part,
the lateral face of the second pillar-shaped part including a ring-like projection part, the ring-like projection part extending
in a circumferential direction of the lateral face of the second pillar-shaped part and projecting outward from the lateral
part of the second pillar-shaped part, and

a first area corresponding to the ring-like projection part on a surface of the substrate is within a second area corresponding
to the wiring layer on the substrate, the first area being defined on the surface of the substrate when the ring-like projection
part is viewed toward the substrate in a direction perpendicular to the surface of the substrate, the second area being defined
on the surface of the substrate when the wiring layer is viewed toward the substrate in the direction perpendicular to the
surface of the substrate.

US Pat. No. 9,223,335

SEMICONDUCTOR DEVICE

Lapis Semiconductor Co., ...

1. A semiconductor device, comprising:
a reference voltage generation circuit to which a power source voltage is applied;
a determining circuit connected to the reference voltage generation circuit; and
a control unit connected to the determining circuit for generating a constant electrical current,
wherein said control unit includes a current mirror circuit,
said determining circuit is connected to a ground potential through the control unit, and
said determining circuit includes a switching circuit for generating an output voltage according to a determination target
voltage.

US Pat. No. 9,257,377

SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE HAVING AN OSCILLATOR

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
an oscillator including a plurality of first terminals that are disposed on a first face of the oscillator;
an integrated circuit including a first region formed with a plurality of first electrode pads along one side on a first face
of the integrated circuit, and a second region formed with a plurality of second electrode pads on the first face of the integrated
circuit;

a lead frame that includes a plurality of second terminals, and on which the oscillator and the integrated circuit are mounted
such that the first terminals are sandwiched between the first electrode pads and the second terminals;

a first bonding wire that connects one of the plurality of first terminals to one of the plurality of first electrode pads;
and

a second bonding wire that connects one of the plurality of second terminals of the lead frame to one of the plurality of
second electrode pads,

wherein the plurality of first terminals of the oscillator are separated from each other by a specific distance along a first
direction on the first face of the oscillator,

wherein a width of the first region in the first direction is narrower than the specific distance between the plurality of
first terminals.

US Pat. No. 9,070,340

DRIVING DEVICE OF DISPLAY DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A driving device of a display device, comprising:
a first switching portion that is provided between a potential switching portion, that switches a potential of a drive signal
line to a target potential that corresponds to display data, and a display device, to which the potential of the drive signal
line is supplied as voltage, the first switching portion connecting the drive signal line to a power source during a time
until the potential of the drive signal line reaches a first reference potential that is higher than a potential of the drive
signal line during a previous cycle;

a second switching portion that is provided between the potential switching portion and the display device, and that connects
the drive signal line to a ground line during a time until the potential of the drive signal line reaches a second reference
potential that is lower than a potential of the drive signal line during the previous cycle; and

a control section that, when the potential of the drive signal line during the previous cycle is lower than the target potential,
operates the first switching portion by using, as the first reference potential, a potential that is less than or equal to
the target potential and that is closest to the target potential, among predetermined n types (n?1) of potentials, and, when
the potential of the drive signal line during the previous cycle is higher than the target potential, operates the second
switching portion by using, as the second reference potential, a potential that is greater than or equal to the target potential
and that is closest to the target potential, among the n types of potentials.

US Pat. No. 9,128,112

DETERMINATION DEVICE, ELECTRICAL DEVICE, AND METHOD OF DETERMINING MOVING STATE

LAPIS SEMICONDUCTOR CO., ...

1. A determination device, comprising:
a geomagnetism value obtaining unit for obtaining a geomagnetism value detected with a geomagnetism sensor; and
a geomagnetism value determining unit for determining whether a user having the geomagnetism sensor is in a moving state in
an automobile or on a train according to a magnitude of a change in the geomagnetism value obtained with the geomagnetism
value obtaining unit.

US Pat. No. 9,219,383

SEMICONDUCTOR CHIP AND SOLAR SYSTEM

LAPIS SEMICONDUCTOR CO., ...

1. A method of discharging a charging control system comprising a solar cell, a secondary cell, and a semiconductor chip having
four side surfaces, the method comprising:
electrically connecting a first electrode of the semiconductor chip that is located closest to one side surface of the semiconductor
chip in relation to other of the four side surfaces of the semiconductor chip to the solar cell;

electrically connecting a second electrode of the semiconductor chip that is located closest to the one side surface of the
semiconductor chip in relation to the other of the four side surfaces of the semiconductor chip to the secondary cell;

electrically connecting an interconnection line to the first electrode and the second electrode, wherein the interconnection
line is provided within the semiconductor chip and a discharge section is connected at a middle point of the interconnection
line; and thereafter

in a case where a voltage of the secondary cell is equal to or greater than a predetermined value, discharging an electric
current applied from the solar cell to the semiconductor chip by the discharge section to decrease an electric current flowing
from the solar cell to the secondary cell.

US Pat. No. 9,245,635

NONVOLATILE SEMICONDUCTOR MEMORY

LAPIS SEMICONDUCTOR CO., ...

1. A nonvolatile semiconductor memory comprising:
a plurality of memory cells;
word lines connected to the plurality of memory cells;
bit lines crossing the word lines and connected to the plurality of memory cells, respectively, such that at least two of
the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which
are connected to the selected bit lines to write data to said those memory cells;

charge amount measurement sections for measuring amounts of charge stored in the plurality of memory cells, respectively;
and

current path switching circuits connected to the bit lines, respectively, wherein each of those current path switching circuits
which are connected to the selected bit lines supplies a current from the power supply line to the memory cell concerned when
a measured value of the amount of charge measured by the charge amount measurement section associated with the memory cell
concerned does not reach a desired value for data writing, and supplies the current to a predetermined terminal, other than
a ground potential, through a bypass route when the measured value of the amount of charge reaches the desired value.

US Pat. No. 9,093,431

SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME

LAPIS SEMICONDUCTOR CO., ...

1. A stacked semiconductor device comprising a first semiconductor device and a second semiconductor device secured on the
first semiconductor device,
the first semiconductor device comprising:
a first semiconductor substrate;
a first circuit element formed at one main surface of the first semiconductor substrate;
a wiring portion connected with the first circuit element and formed at the one main surface of the first semiconductor substrate;
a post electrode that is connected with the wiring portion, and that is formed so as to protrude from the first semiconductor
substrate; and

a first through-type electrode formed in a first through hole penetrating through the first semiconductor substrate in a thickness
direction, and

the second semiconductor device comprising:
a second semiconductor substrate;
a second circuit element formed at one main surface of the second semiconductor substrate; and
a second through-type electrode formed in a second through hole penetrating through the second semiconductor substrate in
a thickness direction, connected with the second circuit element at the one main surface of the second semiconductor substrate,
and connected with the post electrode at an other main surface of the second semiconductor substrate, wherein

an area corresponding to an opening of the second through hole formed at the other main surface of the second semiconductor
substrate is smaller than an area corresponding to a top surface of the post electrode, and the post electrode and the second
through-type electrode are connected to each other via a solder terminal.

US Pat. No. 9,356,771

METHOD OF GENERATING CLOCK AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A method of generating a clock, comprising the steps of:
calculating a first frequency division number through dividing a frequency of an input clock by a target frequency and a specific
integer k (k?2);

calculating a second frequency division number according to the first frequency division number;
dividing a period of time of one cycle of the target frequency by the specific integer k to obtain sections in a number of
the specific integer k;

dividing the frequency of the input clock with the second frequency division number within one of the sections;
dividing the frequency of the input clock with the first frequency division number within each remaining one of the sections
in a number of (k?1); and

generating the clock having a frequency with one cycle equal to a period of time corresponding to each of the sections in
the number of the specific integer k obtained through dividing the frequency of the input clock.

US Pat. No. 9,298,248

SEMICONDUCTOR DEVICE AND ELECTRICAL TERMINAL

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device, comprising:
a moving state determining unit for obtaining first sensor data from a first acceleration sensor so that the moving state
determining unit monitors a transitional state of the first sensor data, and determines whether a user who possesses an electrical
terminal is walking or moving by a vehicle when the transitional state of the first sensor data exceeds a specific threshold
value;

a reliability information determining unit for determining reliability information indicating reliability of a determination
result of the moving state determining unit; and

a transmission processing unit for transmitting the determination result and the reliability information to a main control
unit that controls the electrical terminal,

wherein said reliability information determining unit is configured to determine that the reliability information is set to
a first value when the moving state determining unit performs the determination process for a period of time longer than a
specific level, and

said reliability information determining unit is configured to determine that the reliability information is set to a second
value indicating that the reliability is higher than that of the first value when the moving state determining unit performs
the determination process for a period of time shorter than the specific level.

US Pat. No. 9,412,567

PLASMA MONITORING METHOD AND PLASMA MONITORING SYSTEM

LAPIS SEMICONDUCTOR CO., ...

7. A plasma monitoring system comprising:
sensors each having
a substrate;
a first electrode;
an insulating film that is formed on the first electrode and has a contact hole formed therein, the contact hole exposing
a part of a surface of the first electrode; and

a second electrode that is formed on the insulating film and is electrically separated from the first electrode, and facing
a plasma during a plasma process;

voltmeters monitoring the plasma during first and second plasma processing of the plasma process, by measuring, for each respective
sensor of the sensors, potentials of the respective first electrode and the respective second electrode, or a potential difference
between the respective first electrode and the respective second electrode to determine charge-up;

a first wafer, wherein in the first plasma processing, a plurality of the sensors is arranged and bonded on the first wafer;
and

a second wafer, wherein in the second plasma processing, a group of the sensors is arranged and bonded at a plurality of different
positions on the second wafer, a total number of the group of the sensors arranged and bonded on the second wafer is different
from a total number of the plurality of the sensors arranged and bonded on the first wafer.

US Pat. No. 9,279,860

BATTERY MONITORING SYSTEM AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A battery monitoring system comprising:
a plurality of battery cell sets of a specific number plurality of serially connected battery cells;
a plurality of semiconductor devices that are each respectively provided to each of the plurality of battery cell sets and
that each measure battery voltage of the corresponding battery cell set, wherein:

each of the semiconductor devices comprises
a measuring section that measures the battery voltage of the corresponding battery cell set,
a high side communication section that is supplied with a drive voltage in a first voltage range, and, when a semiconductor
device is present at a higher position that operates at a higher operating voltage than the operating voltage of the semiconductor
device itself when measuring a battery cell set on the high side of the battery cell set measured by the semiconductor device
itself, is capable of performing communication with the high side semiconductor device,

a low side communication section that is supplied with a drive voltage in a second voltage range, and, when a semiconductor
device is present at a lower position that operates at a lower operating voltage than the operating voltage of the semiconductor
device itself when measuring a battery cell set on the low side of the battery cell set measured by the semiconductor device
itself, is capable of performing communication with the low side semiconductor device, and

a communication level converter that converts in both directions between the first voltage range of the high side communication
section and the second voltage range of the low side communication section, that is capable of converting a high side communication
signal input from the high side communication section to a low side communication signal and outputting the converted signal
to the low side communication section, and that is capable of converting a low side communication section input from the low
side communication section to a high side communication section and outputting the converted signal to the high side communication
section;

the semiconductor device at the highest stage in communication between the semiconductor devices further comprises a signal
level determination section that detects the first voltage range of the high side communication section, and that determines
the level of the low side communication signal that the communication level converter outputs to the low side communication
section when the first voltage range is narrower than a specific voltage range; and

the first voltage range of the highest stage is set to a specific voltage range narrower than the first voltage range of another
of the semiconductor devices.

US Pat. No. 9,246,331

POWER SUPPLY CONTROL SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. A power supply control system comprising:
a first switching section including one end connected to a battery and another end connected to a load; and
a second switching section including one end connected to a solar battery and another end connected to the load,
wherein the first switching section is configured to compare a first voltage that is a battery output voltage dropped by a
first voltage level, and a second voltage that is a voltage at a connection point to the load dropped by a second voltage
level, disconnect the battery and the load when the second voltage is equal to or greater than the first voltage, and connect
the battery and the load when the second voltage is smaller than the first voltage, and

wherein the second switching section is configured to compare a third voltage that is a solar battery output voltage dropped
by a third voltage level, which is lower than the first voltage level, and the second voltage, disconnect the solar battery
and the load when the second voltage is equal to or greater the third voltage, and connect the solar battery and the load
when the second voltage is smaller than the third voltage.

US Pat. No. 9,172,575

CORRELATOR AND DEMODULATION DEVICE INCLUDING CORRELATOR

LAPIS Semiconductor Co., ...

1. A correlator comprising:
a plurality of filter sections having different non-overlapping pass-band characteristics from each other, each of the plurality
of filter sections being input in parallel with an Orthogonal Frequency Division Multiplexing (OFDM) signal, which is a single
received signal and has been converted to a digital signal, where one symbol period comprises an effective symbol period and
a guard interval in which part of the signal of the effective symbol period has been copied, wherein the plurality of filter
sections is set such that each of the different non-overlapping pass-band characteristics of filter sections are adjacent
to each other;

a plurality of autocorrelation generating sections, provided so as to correspond to each of the plurality of filter sections,
that generate autocorrelation signals based on the signals passed through the corresponding filter sections; and

an autocorrelation output section that is input with each of the autocorrelation signals and, based on each of the autocorrelation
signals, either selects one of the autocorrelations or generates an autocorrelation appropriate for obtaining timing synchronization,
and outputs the selected or generated autocorrelation, wherein

the autocorrelation output section:
extracts an autocorrelation signal having the largest maximum value from the autocorrelation signals;
sets a threshold value by multiplying the extracted maximum value by a specific coefficient of less than 1;
extracts from the remaining autocorrelation signals any autocorrelations having a maximum value greater than the threshold
value;

addition-combines the autocorrelation signal having the largest maximum value and the extracted autocorrelation signals having
maximum values greater than the threshold value; and

outputs the addition-combined autocorrelation signal.

US Pat. No. 9,166,642

SIGNAL RECEIVING DEVICE AND SIGNAL RECEIVING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A frequency signal receiving device comprising:
a mixer generating an intermediate frequency which has a predetermined center frequency by mixing a received frequency signal
with a local oscillation frequency signal generated by a local oscillator, and outputting the intermediate frequency signal;

an IF filter comprising a high-pass filter and a low-pass filter connected in series to each other each of which includes
a resistance and condenser block that is connected to the resistance and a capacity thereof is changeable comprising a plurality
of condensers connected in parallel to each other via at least one corresponding switch respectively, and receiving said intermediate
frequency signal, and causing a frequency signal to pass therethrough, the passed frequency signal existing within a range
of a frequency band determined by a center frequency and a size of a frequency bandwidth set in the IF filter;

a controlling part providing the high-pass filter and the low-pass filter with a filter adjusting input signal, which part
changes the size of the frequency bandwidth set in the IF filter by changing a capacity value of the condenser block by turning
said switch on or off according to frequency components contained in the passed frequency signal, and providing the local
oscillator with an oscillating frequency setting input signal, which changes the local oscillation frequency signal so as
to match a center frequency of said intermediate frequency signal with the center frequency set in the IF filter that fluctuates
with the change of the size of the frequency bandwidth set in the IF filter,

wherein the local oscillator is a Phase Locked LOOP oscillator;
the center frequency and the size of the frequency bandwidth of the IF filter are set by a resistance element having a changeable
resistance value or a capacity element having a changeable capacitance value:

the controlling part comprises:
a first storing part in which a plurality of frequency bandwidth setting data pieces each consisting of digital data for setting
the size of the frequency bandwidth of the IF filter by changing one of the resistance values of the resistance element and
the capacitance value of the capacity element are stored for a plurality of mutually different sizes of the frequency bandwidth,
respectively;

a first selecting circuit for selecting one of the frequency bandwidth setting data pieces and outputting the selected data
piece to the IF filter;

a second storing part in which a plurality of local oscillation frequency signal setting data pieces each indicating a division
ratio for setting the frequency of the local oscillation frequency signal to the local oscillator are stored correspondingly
to a plurality of mutually different frequencies of the local oscillation frequency signal; and

a second selecting circuit for selecting one of the local oscillation frequency signal setting data pieces and outputting
the selected data piece to the oscillator, and

the controlling part outputs, in accordance with a setting signal inputted from an outside of the frequency signal receiving
device, the filter adjusting input signal to the IF filter by issuing a first selection command for selecting one of the frequency
bandwidth setting data pieces to the first selecting circuit, and the oscillation frequency setting input signal to the local
oscillator by issuing a second selection command for selecting one of the local oscillation frequency signal setting data
pieces to the second selecting circuit,

the plurality of local oscillation signal setting data pieces stored in the second storing part are associated to each other
with the frequency bandwidth setting data pieces stored in the first storing part so that the center frequency of the intermediate
frequency signal matches the center frequency set in the IF filter that fluctuates by setting one of a plurality of mutually
different sizes of the frequency bandwidth provided by the frequency bandwidth setting data pieces to the IF filter.

US Pat. No. 9,368,227

SEMICONDUCTOR DEVICE AND TEST METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a fuse circuit including a complementary fuse;
a test voltage application circuit; and
a comparison circuit, wherein
the complementary fuse includes
a first fuse, to one end of which a first voltage is applied and the other end of which serves as an output terminal, and
a second fuse, to one end of which a second voltage is applied and the other end of which is connected to the output terminal,the first and second fuses being connected in series, the complementary fuse storing one bit of data when one of the first
and second fuses is disconnected,
the test voltage application circuit is configured to apply a test voltage having the first voltage or the second voltage
to the output terminal of the complementary fuse and then stop applying the test voltage, and

the comparison circuit is configured to determine, after the test voltage application circuit stops applying the test voltage,
whether or not output data from the output terminal of the complementary fuse coincides with an expected value, and output
a result of the determination as a test result.

US Pat. No. 9,306,554

SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR APPARATUS

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor circuit that controls driving of a first load, the semiconductor circuit comprising:
an operational amplifier that includes a first input terminal, a second input terminal, and an output terminal, and that outputs
a first voltage from the output terminal;

a voltage drop circuit which drops the first voltage and generates a second voltage; and
an input switching part configured to input a third voltage to the second input terminal during a first interval in which
an active element is turned on by the first voltage, and to input the second voltage to the second input terminal during a
second interval in which the active element is turned off.

US Pat. No. 9,086,971

SEMICONDUCTOR DEVICE, CONFIDENTIAL DATA CONTROL SYSTEM, CONFIDENTIAL DATA CONTROL METHOD

LAPIS Semiconductor Co., ...

1. A semiconductor device comprising:
a correction unit that corrects an error in a plurality of confidential data segments based on a plurality of segment correction
data, wherein a single item of confidential data is divided into a plurality of confidential data segments and wherein a plurality
of segment correction data for correcting errors in the plurality of confidential data segments and the plurality of confidential
data segments are alternately stored on a storage unit; and

a synthesis unit that synthesizes the plurality of confidential data segments output from the correction unit.

US Pat. No. 9,070,618

RESISTANCE STRUCTURE, INTEGRATED CIRCUIT, AND METHOD OF FABRICATING RESISTANCE STRUCTURE

LAPIS Semiconductor Co., ...

1. A resistance structure comprising:
a well formed in a semiconductor substrate;
a first resistance element having long sides and short sides that is provided over the well with an insulating film interposed;
a second resistance element having long sides and short sides that is provided over the well with the insulating film interposed
and that is disposed side by side in the short side direction such that one long side thereof opposes one long side of the
first resistance element;

first wiring that is connected to one end of the first resistance element;
second wiring that is connected to one end of the second resistance element;
third wiring that connects the other end of the first resistance element with the other end of the second resistance element;
and

a connection portion that connects any of the first wiring, the second wiring and the third wiring with the well;
wherein the first resistance element and the second resistance element are disposed so as to be contained within the region
of formation of the well from a plan view perspective.

US Pat. No. 9,071,582

COMMUNICATION APPARATUS, RECEPTION CONTROL METHOD, AND TRANSMISSION CONTROL METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A communication apparatus comprising:
a transmission and reception part receiving a packet from a network and producing receive data which includes a header section
and a data body on the basis of the received packet in a reception operation, and making a packet on the basis of a transmit
data which includes a header section and a data and transmitting the packet to the network in a transmission operation;

a security part decrypting the data body including at least encrypted data in the receive data;
a control part connected to the transmission and reception part and the security part through a system bus;
an encryption data processing part connected to the system bus; and
a second bus connecting the encryption data processing part to the security part and being different and separated from said
system bus,

wherein the encryption data processing part supplies the receive data to the security part through said second bus when the
data body of the receive data produced in the transmission and reception part includes encrypted data, and supplies the receive
data to the control part through the system bus in the reception operation,

the control part supplies a decryption command to the security part through the system bus together with the receive data
while reducing in volume said data body of the receive data when determining that the receive data supplied from the encryption
data processing part include the encrypted data, and

the security part decrypts the encrypted data of the data body included in the receive data, which are supplied from the encryption
data processing part through said second bus, according to the decryption command to make plain-text data, and supplies the
plain-text data to the control part through the system bus in response to an encryption command.

US Pat. No. 9,054,662

AUTOMATIC AUDIO SIGNAL LEVEL ADJUSTMENT CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. An automatic audio signal level adjustment circuit capable of automatically adjusting a level of an input audio signal
within a specific range, comprising:
an amplitude adjustment determining circuit unit configured to generate an amplitude reduction instruction when the level
of the input audio signal is greater than a first reference value corresponding to a maximum value of the specific range,
said amplitude adjustment determining circuit unit being configured to generate an amplitude augmentation instruction when
the level of the input audio signal is smaller than a second reference value that is smaller than the first reference value
by a specific value; and

an amplitude adjusting circuit unit configured to output an output audio signal having a level reduced from the level of the
input audio signal when the amplitude adjustment determining circuit unit generates the amplitude reduction instruction, said
amplitude adjusting circuit unit being configured to output an output audio signal having a level augmented from the level
of the input audio signal when the amplitude adjustment determining circuit unit generates the amplitude augmentation instruction,
said amplitude adjusting circuit unit being configured to output an output audio signal equal to the input audio signal when
the amplitude adjustment determining circuit unit does not generate the amplitude reduction instruction and the amplitude
augmentation instruction,

wherein said amplitude adjustment determining circuit unit includes a reference value alternate transmission circuit unit
configured to alternately transmit the first reference value and the second reference value, and an amplitude adjustment instruction
generating circuit unit configured to compare the level of the input audio signal with a comparison reference value to generate
one of the amplitude reduction instruction and the amplitude augmentation instruction, and

said amplitude adjustment instruction generating circuit unit includes:
a comparing circuit unit configured to generate a first comparison result signal having a first logic value when the level
of the input audio signal is greater than the first reference value, and to generate a second comparison result signal having
a second logic value equal to an inverted value of the first logic value when the level of the input audio signal is smaller
than the second reference value;

a first flip-flop circuit unit configured to capture the first comparison result signal at a timing when the first reference
value is transmitted, and to output the first comparison result signal as an amplitude reduction instruction signal; and

a second flip-flop circuit unit configured to capture the second comparison result signal at a timing when the second reference
value is transmitted, and to output the second comparison result signal as an amplitude augmentation instruction signal.

US Pat. No. 9,269,991

BATTERY MONITORING SYSTEM AND BATTERY MONITORING DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A battery monitoring system, comprising:
a plurality of battery monitoring devices that are serially connected to each other, that are each provided for one of a plurality
of serially connected battery cell groups, and that monitor a voltage of a plurality of battery cells included in each of
the plurality of battery cell groups; and

a control circuit that is connected to one battery monitoring device of the plurality of battery monitoring devices and that
transmits a first activation signal to the one battery monitoring device,

wherein each particular one of the plurality of battery monitoring devices comprises:
a constant voltage generation circuit that generates and outputs a constant voltage;
a first activation circuit that outputs a second activation signal if the first activation circuit receives the first activation
signal from the control circuit; and

a second activation circuit that outputs a third activation signal in response to recognizing the constant voltage generated
by the constant voltage generation of another of the battery monitoring devices that is connected to the particular battery
monitoring device, and

wherein the constant voltage generation circuit generates the constant voltage if the constant voltage generation circuit
receives the second activation signal or the third activation signal.

US Pat. No. 9,318,391

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING A MOS-TYPE TRANSISTOR

LAPIS SEMICONDUCTOR CO., ...

1. A method for manufacturing a semiconductor device comprising:
laminating an oxide film layer and a semiconductor layer of a first-conductive-type on a semiconductor layer of a second-conductive-type
in order;

forming an active region of the first-conductive-type in the semiconductor layer of the first-conductive-type;
forming an insulating film on the semiconductor layer of the first-conductive-type;
forming a first region of the first-conductive-type by diffusing, based on a position of the active region of the first-conductive-type,
an impurity of the first-conductive-type within a first region of the semiconductor layer of the second-conductive-type that
includes a lower portion of the active region of the first-conductive-type;

forming a MOS-type transistor in the active region of the first-conductive-type;
removing the oxide film layer from a predetermined region, the predetermined region being a region of the semiconductor layer
of the first-conductive-type in which a first electrode, a second electrode and a third electrode are to be formed;

forming, in the first region of the first-conductive-type, a second region of the first-conductive-type by diffusing the impurity
of the first-conductive-type within the predetermined region from which the oxide film layer has been removed and on which
the first electrode is to be formed and, forming a third region of the first-conductive-type by diffusing the impurity of
the first-conductive-type within the predetermined region on which the third electrode is to be formed;

forming a region of the second-conductive-type by diffusing an impurity of the second-conductive-type within the predetermined
region from which the oxide film layer has been removed and in which the second electrode is to be formed; and

forming the first electrode, the second electrode and the third electrode.

US Pat. No. 9,300,506

CLOCK SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A clock buffer comprising:
an inverter core portion configured to generate an internal clock signal according to an input clock signal; and
an electric current suppressing portion configured to reduce an amplitude of the internal clock signal to be smaller than
that of the input clock signal,

wherein said electric current suppressing portion includes a first transistor connected to a first power source line having
a first potential, and a second transistor having a second potential, and

said clock buffer further comprises a third transistor having a first terminal connected to the first power source line, a
second terminal connected to a connection point between the first transistor and the inverter core portion, and a third terminal
for receiving a control signal.

US Pat. No. 9,202,425

DEVICE CIRCUIT AND DISPLAY APPARATUS HAVING OPERATIONAL AMPLIFIERS WITH PARASITIC DIODES

LAPIS SEMICONDUCTOR CO., ...

1. A driving circuit for driving a display panel having a plurality of scan lines, a plurality of data lines spaced apart
from the plurality of scan lines but arrayed to cross the plurality of scan lines, and a plurality of capacitive loads formed
in respective areas neighboring crossings of the scan lines and the data lines, the driving circuit comprising:
a first operational amplifier powered by a first power supply voltage and a second power supply voltage lower than the first
power supply voltage, having an output terminal for output of an analog voltage with a direct current voltage component of
positive polarity;

a second operational amplifier powered by a third power supply voltage and a fourth power supply voltage lower than the third
power supply voltage, having an output terminal for output of an analog voltage with a direct current voltage component of
negative polarity;

a first switching circuit for connecting the output terminal of the first operational amplifier to a first data line among
the plurality of data lines and connecting the output terminal of the second operational amplifier to a second data line among
the plurality of data lines, then interchanging connections so that the output terminal of the first operational amplifier
is connected to the second data line and the output terminal of the second operational amplifier is connected to the first
data line;

at least one protective diode having a terminal and another terminal, the terminal being connected to the output terminal
of the first operational amplifier or the output terminal of the second operational amplifier; and

a second switching circuit for switching a connection of the another terminal of the at least one protective diode before
the first switching circuit interchanges the connections.

US Pat. No. 9,136,386

SOI SUBSTRATE, METHOD OF MANUFACTURING THE SOI SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
an SOI substrate; and
a semiconductor element structure formed on the SOI substrate,
the SOI substrate including:
a semiconductor base;
a semiconductor layer formed over the semiconductor base; and
a buried insulating film which is disposed between the semiconductor base and the semiconductor layer, so as to electrically
isolate the semiconductor layer from the semiconductor base, the buried insulating film containing a lower insulating film
formed on the semiconductor base, a nitride film formed on the lower insulating film, and an upper insulating film formed
on the nitride film,

the semiconductor element structure including:
a gate structure having a gate insulating film formed on the semiconductor layer and a gate electrode formed on the gate insulating
film;

an insulating interlayer which is formed on the semiconductor layer of the SOI substrate and on the gate structure and has
a contact hole formed therein; and

a contact plug with which the contact hole is filled, the contact plug being electrically connected to the semiconductor layer,
and

the semiconductor layer including:
first and second impurity-diffused regions which have a same conductivity type and are formed on both sides of the gate structure,
respectively; and

a body region which is formed between the first and second impurity-diffused regions and directly under the gate structure;
and

wherein,
either one of the first and second impurity-diffused regions is electrically connected to the contact plug, and
a bias voltage is applied to the semiconductor base when the semiconductor base is used as a back-gate.

US Pat. No. 9,160,177

SEMICONDUCTOR CIRCUIT, BATTERY MONITORING SYSTEM, AND CONTROL METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor circuit comprising:
a drive component that includes first switching elements connected to discharge switching elements and resistive elements,
the discharge switching elements being formed for each of plural batteries connected in series and in such a way that first
ends of the discharge switching elements are connected to high potential sides of the batteries, second ends of the discharge
switching elements are connected to low potential sides of the batteries, and control ends of the discharge switching elements
are connected to control signal lines,

the resistive elements being connected between the control signal lines and the low potential sides of the batteries, and
the first switching elements interconnecting, in accordance with a drive time of the discharge switching elements, the control
signal lines and drive current sources that supply charge to the control signal lines; and

a drawing component that draws charge with draw current sources in accordance with a draw time in which the drawing component
draws the charge supplied from the drive component.

US Pat. No. 9,117,048

SEMICONDUCTOR INTEGRATING CIRCUIT LAYOUT PATTERN GENERATING APPARATUS AND METHOD

LAPIS Semiconductor Co., ...

1. A layout pattern generating apparatus for generating a layout pattern of each of elements included in a semiconductor integrated
circuit, the layout pattern generating apparatus comprising:
a storage;
a basic figure generator;
an additional figure generator;
a display unit;
an operation input unit; and
an element arrangement figure generator;
wherein
the storage stores
terminal figure relative position information including data describing a relative position of a terminal figure of a layout
pattern generation target element relative to an effective area figure of the layout pattern generation target element,

figure adjustment value information including data describing an adjustment value for a basic figure including the effective
area figure and the terminal figure, and

additional figure relative position information including data describing a relative position of an additional figure relative
to the basic figure, the additional figure being a figure other than the basic figure;

wherein the basic figure generator generates the effective area figure and the terminal figure of the layout pattern generation
target element on the basis of the terminal figure relative position information and the figure adjustment value information;

wherein the additional figure generator generates the additional figure of the layout pattern generation target element on
the basis of the generated effective area figure, the generated terminal figure and the additional figure relative position
information;

wherein the display unit displays the generated effective area figure, the generated terminal figure and the generated additional
figure;

wherein the figure adjustment value information is changed depending on an input from the operation input unit;
wherein the terminal figure relative position information includes data describing a relative position of an effective area
figure of each layout pattern generation target element;

wherein the element arrangement figure generator divides the generated effective area figure and the generated terminal figure;
and

wherein the additional figure generator performs the generating of the additional figure of the layout pattern generation
target element, on the basis of the divided effective area figure, the divided terminal figure and the additional figure relative
position information.

US Pat. No. 9,058,789

SYNCHRONOUS PROCESSING SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. A synchronous processing system having a plurality of semiconductor integrated circuits which each have a counter therein,
for allowing said counter in each of said plurality of semiconductor integrated circuits synchronously to repeat counting
common clock pulses from an initial value to a predetermined value in response to a processing operation start instruction
from external means and for allowing said counter to stop said counting in response to a processing operation stop instruction
from said external means,
wherein one of said plurality of semiconductor integrated circuits is set as a master chip, and the semiconductor integrated
circuits except said master chip are set as slave chips,

wherein said master chip comprises:
a first synchronization controller which generates a synchronization control signal having a fixed time width synchronously
with each of said common clock pulses in response to said processing operation start instruction, which generates said synchronization
control signal synchronously with each of said common clock pulses at which said counter in said master chip reaches said
predetermined value, and which stops generating said synchronization control signal in response to said processing operation
stop instruction; and

a first counter controller which allows the counter in said master chip to perform said counting synchronously with each of
said common clock pulses in response to said synchronization control signal from said first synchronization controller,

wherein said slave chip comprises:
a second synchronization controller which receives said synchronization control signal from said master chip; and
a second counter controller which allows said counter in said slave chip to perform said counting synchronously with each
of said common clock pulses in response to said synchronization control signal received by said second synchronization controller,
and

wherein said first counter controller allows said counter in said master chip to repeat said counting if said synchronization
control signal is supplied at the time point that a count value of said counter has reached said predetermined value and allows
said counter in said master chip to stop said counting if said synchronization control signal is not supplied at the time
point that the count value of said counter in said master chip has reached said predetermined value, and

said second counter controller allows said counter in said slave chip to repeat said counting from the initial value only
by supplying said synchronization control signal from said second synchronization controller to said counter of said slave
chip while the processing operation start instruction is supplied to said master chip, regardless of whether the count value
of said counter in said slave chip has reached said predetermined value if the synchronization control signal received is
supplied from said second synchronization controller and allows said counter in said slave chip to stop said counting if said
synchronization control signal is not supplied from said second synchronization controller at the time point that the count
value of said counter in said slave chip has reached said predetermined value.

US Pat. No. 9,390,685

SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND SIGNAL LOADING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A drive IC that outputs to a display panel a signal generated based on image data, the drive IC comprising:
a clock signal supply section configured to supply a plurality of clock signals;
an input terminal that has as an input a first differential signal or a second differential signal as input data;
a first output section configured to output the input data that has been input through the input terminal, according to a
clock signal supplied from the clock signal supply section;

an input data controller that includes the first output section and that is configured to control loading of the input data;
a first output terminal that is connected to the first output section and that outputs a signal corresponding to the first
differential signal;

a second output terminal that is connected to the first output section and that outputs a signal corresponding to the second
differential signal; and

a selector that is configured, based on a switching signal from a clock switching signal supply section, to select a clock
signal corresponding to the first differential signal or the second differential signal from among the plurality of clock
signals supplied from the clock signal supply section, and supply the selected clock signal to the first output section as
the clock signal.

US Pat. No. 9,134,752

TIME MEASUREMENT DEVICE, MICRO-CONTROLLER AND METHOD OF MEASURING TIME

LAPIS SEMICONDUCTOR CO., ...

1. A time measurement device comprising:
a first measurement unit configured to measure a clock period of a first reference clock signal within a specific cycle of
a second reference clock signal, said second reference clock signal having an oscillation frequency lower than that of the
first reference clock signal and oscillation accuracy higher than that of the first reference clock signal;

a calculation unit configured to calculate a physical amount indicating a variance amount of a clock period measured with
the first measurement unit relative to a reference clock period measured in advance as the clock period of the first reference
clock signal within the specific cycle of the second reference clock signal;

a compensation unit configured to compensate an expected measurement value indicating the clock period of the first reference
clock signal corresponding to a time as a measurement target according to the physical amount calculated with the calculation
unit; and

an output unit configured to output time information indicating that the clock period of the first reference clock signal
reaches an expected measurement value thus compensated after a clock period of the first reference clock signal measured with
the first measurement unit reaches the expected measurement value thus compensated; and

a first interruption unit configured to output a first interruption signal per cycle of the second reference clock signal;
a second interruption unit configured to output a second interruption signal after the clock period of the first reference
clock signal measured with the first measurement unit reaches the expected measurement value thus compensated;

a second measurement unit configured to measure an overflow number count of an overflow that occurred when the first measurement
unit measures the clock period of the first reference clock signal within the specific cycle of the second reference clock
signal; and

a third interruption unit configured to output a third interruption signal when the overflow occurs,
wherein said calculation unit is configured to determine whether the first interruption signal is output for the first time
after the first interruption unit outputs the first interruption signal,

said calculation unit is configured to initialize a measurement value of the first measurement unit so that the calculation
unit sets flag information indicating that a first interruption occurs after the first interruption signal is output for the
first time, and

said calculation unit is configured to retrieve a clock period of the first reference clock signal measured before as the
clock period of the first reference clock signal within the specific cycle of the second reference clock signal so that the
calculation unit initializes the flag information after the first interruption signal is not output for the first time,

said calculation unit is configured to control the first measurement unit to start measuring the clock period of the first
reference clock signal after the first interruption unit outputs the first interruption signal, and to wait for a next first
interruption signal,

said calculation unit is configured to retrieve the clock period of the first reference clock signal measured before as the
clock period of the first reference clock signal within the specific cycle of the second reference clock signal after the
first interruption unit outputs the next first interruption signal so that the calculation unit calculates a ratio between
the clock period of the first reference clock signal measured before and the reference clock period as the physical amount,

said compensation unit is configured to compensate the expected measurement value according to the ratio,
said output unit is configured to control the first measurement unit to start measuring the clock period of the first reference
clock signal measured with the first measurement unit after the compensation unit compensates the expected measurement value,
and to wait until the second interruption unit outputs the second interruption signal,

said output unit is configured to output the time information after the second interruption unit outputs the second interruption
signal,

said calculation unit is configured to calculate a product of the overflow number count of the overflow measured with the
second measurement unit and a clock period that causes the overflow,

said calculation unit is configured to calculate a sum of the product of the overflow number count of the overflow and a clock
period of the first reference clock signal measured with the first measurement unit without the overflow,

said calculation unit is configured to retrieve the sum as the clock period of the first reference clock signal within the
specific cycle of the second reference clock signal,

said second measurement unit is configured to measure the overflow number count of the overflow when the third interruption
unit outputs the third interruption signal,

said calculation unit is configured to initialize the measurement value of the first measurement unit and a measurement value
of the second measurement unit so that the calculation unit sets the flag information indicating that the first interruption
occurs when the calculation unit determines that the first interruption signal is output for the first time,

said calculation unit is configured to retrieve the clock period of the first reference clock signal measured before and the
overflow number count measured with the second measurement unit when the first interruption signal is not output for the first
time, and

said calculation unit is configured to calculate the product and the sum so that the calculation unit initializes the flag
information.

US Pat. No. 9,171,802

SEMICONDUCTOR WIRING PATTERNS

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device having a rectangular semiconductor element mounted on a substrate formed with an external input
terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal
and the external output terminal, wherein,
the semiconductor element comprises:
a plurality of first electrodes formed along a first edge of a surface thereof;
a plurality of second electrodes formed along an edge opposite to the first edge of the surface;
a plurality of third electrodes formed in a neighborhood of a functional block; and
an internal wiring for connecting the first electrodes and the third electrodes, and
the substrate comprises:
a first wiring pattern for connecting the external input terminal and the first electrodes;
a second wiring pattern for connecting the external output terminal and the second electrodes; and
a third wiring pattern for connecting the first electrodes and the third electrodes,
wherein the plurality of first electrodes and the plurality of second electrodes are formed along an outer edge of the semiconductor
element, and wherein the internal wiring and the third wiring pattern are connected in parallel to each other between the
first electrodes and the third electrodes.

US Pat. No. 9,136,827

POWER-ON RESET CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. A power-on reset circuit comprising:
a first sensor circuit;
a second sensor circuit; and
a reset signal generating circuit for generating a reset signal;
wherein the first sensor circuit has:
a first first-conductive-type MOS transistor which has a first source connected to a first power supply, a first drain, and
a first gate connected to a second power supply;

a first second-conductive-type MOS transistor which has a second source connected to the second power supply, a second drain
connected to the first drain, and a second gate to which a bias potential is applied; and

a first node which outputs a first signal corresponding to a potential of the first drain, in a process that a voltage between
the first power supply and the second power supply increases;

wherein the second sensor circuit has:
a second first-conductive-type MOS transistor which has a third source connected to the first power supply, a third drain,
and a third gate connected to the second power supply;

a second second-conductive-type MOS transistor which has a fourth source connected to the second power supply, a fourth drain
connected to the third drain, and a fourth gate to which the bias potential is applied; and

a second node which outputs a second signal corresponding to a potential of the third drain at timing occurring after timing
of outputting the first signal from the first node, in the process that the voltage between the first power supply and the
second power supply increases;

wherein the reset signal generating circuit generates the reset signal from the first signal and the second signal;
wherein the first first-conductive-type MOS transistor and the second first-conductive-type MOS transistor are P-type MOS
transistors, and the first second-conductive-type MOS transistor and the second second-conductive-type MOS transistor are
N-type MOS transistors; and

wherein the reset signal generating circuit has:
a NOR gate to which potentials of the first node and the second node are inputted;
an AND gate to which the potentials of the first node and the second node are inputted; and
a set-reset flip-flop circuit which has a set terminal to which an output of the NOR gate is inputted and a reset terminal
to which an output of the AND gate is inputted.

US Pat. No. 9,077,197

BATTERY RESIDUAL AMOUNT MEASUREMENT SYSTEM, COMPUTER-READABLE MEDIUM STORING BATTERY RESIDUAL AMOUNT MEASUREMENT PROGRAM, AND BATTERY RESIDUAL AMOUNT MEASUREMENT METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A battery residual amount measurement device comprising:
a first storage section that stores reference undischargeable amounts that correspond to ambient temperatures of a battery
and current values of current discharged from the battery;

a second storage section that stores a battery residual amount;
a current detection section that detects a current value of current discharged from a measurement object battery and that
outputs the current value of the current discharged from the measurement object battery; and

a calculating section, to which the current value of the current discharged from the measurement object battery output from
the current detection section is input, and that acquires, from the first storage section, the reference undischargeable amount
that corresponds to an ambient temperature of the measurement object battery and the current value of the current discharged
from the measurement object battery input from the current detection section, and outputs a present battery residual amount
to the second storage section that corresponds to the acquired reference undischargeable amount and a nominal battery capacity
of the measurement object battery.

US Pat. No. 9,473,016

SEMICONDUCTOR DEVICE AND POWER SOURCE CONTROL METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a power source section configured to step down a power source voltage to generate a step-down voltage, and to stop generation
of the step-down voltage responsive to input of a stop signal;

a control section configured to be driven by the step-down voltage generated by the power source section, and to output the
stop signal to the power source section to stop generation of the step-down voltage; and

a power source controller configured to prohibit input of the stop signal to the power source section until the step-down
voltage becomes a predetermined value or greater,

wherein the power source controller comprises
a first N-channel MOS transistor having a gate electrode, a source electrode, and a bulk electrode connected to ground voltage,
a first P-channel MOS transistor having a source electrode and a bulk electrode connected to the power source voltage, and
a gate electrode and a drain electrode connected to a drain electrode of the first N-channel MOS transistor,

a second P-channel MOS transistor having a source electrode and a bulk electrode connected to the power source voltage, and
a gate electrode connected to the gate electrode of the first P-channel MOS transistor,

a second N-channel MOS transistor having a source electrode connected to the ground voltage, a gate electrode connected to
the step-down voltage, and a drain electrode connected to a drain electrode of the second P-channel MOS transistor, and that
is configured to switch ON when the step-down voltage becomes the predetermined value or greater to place a drain electrode
potential of the second P-channel MOS transistor at a low level,

a logic inverting circuit that is driven by the power source voltage, that has an input terminal connected to the drain electrode
of the second N-channel MOS transistor and the drain electrode of the second P-channel MOS transistor, and that is configured
to invert a signal input at the input terminal to provide an output signal, and

an AND circuit configured to perform an AND computation of the output signal from the logic inverting circuit and the stop
signal.

US Pat. No. 9,306,695

FRAME TRANSMITTING APPARATUS, FRAME RECEIVING APPARATUS, AND FRAME TRANSMISSION/RECEPTION SYSTEM AND METHOD

LAPIS Semiconductor Co., ...

1. A frame receiving apparatus, comprising:
a processor that performs processes of:
receiving a low-level frame belonging to a physical layer from a communication network;
generating a timestamp representing a time at which the low-level frame is received and adding the timestamp to the low-level
frame, thereby generating a timestamped frame;

removing the timestamp from the timestamped frame, thereby holding the removed timestamp;
converting a frame obtained by removing the timestamp from the timestamped frame, to a high-level frame belonging to an upper
layer; and

restoring the removed timestamp to the high-level frame; and
a storing unit for selectively storing the time represented by the timestamp, depending on content of the high-level frame.

US Pat. No. 9,230,890

SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a resin;
a lead frame;
an oscillator that comprises a plurality of terminals separated from each other by a predetermined distance, and that is mounted
to an oscillator mounting region formed on a first face of the lead frame, the oscillator mounting region having a narrower
width than the distance between the plurality of terminals, the oscillator being completely sealed inside the resin;

an integrated circuit that is mounted to a second face of the lead frame, which is on an opposite side to the first face;
and

first bonding wires that connect the plurality of terminals of the oscillator to terminals of the integrated circuit.

US Pat. No. 9,219,510

SIGNAL RECEIVING SYSTEM, SEMICONDUCTOR DEVICE, AND SIGNAL RECEIVING METHOD

LAPIS Semiconductor Co., ...

1. A receiving system for obtaining information data based on a plurality of received signals obtained by receiving a broadcast
wave, which carries coded information data, with a plurality of antennas, the receiving device comprising:
a first receiving semiconductor chip that includes a demodulation decoding circuit and a first transmission processor, the
demodulation decoding circuit being configured to demodulate and synthesize the plurality of received signals such that the
signals received from respective antennas are added or subtracted with weighting and to decode a synthesized signal to obtain
received information data, and the first transmission processor being configured to perform a predetermined modulation process
on the received information data to obtain a received information modulation signal and send the received information modulation
signal to a transmission cable; and

a second receiving semiconductor chip that includes a first receiving processor and a data decoder, the first receiving processor
being configured to receive the received information modulation signal via the transmission cable, and to obtain the received
information data by demodulating the received information modulation signal with a demodulation process that corresponds to
the predetermined modulation process, and the data decoder being configured to decode the received information data to obtain
the information data,

wherein the second receiving semiconductor chip further includes a power supply voltage generating circuit, the power supply
voltage generating circuit being configured to generate a DC power supply voltage for operating the first receiving semiconductor
chip and applying the DC power supply voltage to the transmission cable, and

wherein the first receiving semiconductor chip further includes a power supply voltage derivation circuit configured to derive
the power supply voltage from the transmission cable.

US Pat. No. 9,337,687

CHARGING CONTROL SYSTEM AND DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a first terminal electrically connected to an electrode of a secondary battery;
a second terminal electrically connected to an electrode of a solar battery; and
a first interrupter connected to the first terminal and the second terminal, the first interrupter interrupting a connection
between the first terminal and the second terminal on the basis of a result of a comparison between a divided voltage of the
secondary battery and a divided voltage of the solar battery, wherein:

the divided voltage of the secondary battery is given when a first transistor turns on according to a bias voltage given on
the basis of a voltage of the solar battery, the first transistor being connected to the first terminal and a third terminal
which is electrically connected to the other electrode of the secondary battery, and

the first interrupter interrupts a connection between the first terminal and the third terminal when the first transistor
turns off.

US Pat. No. 9,088,053

COMPARATOR CIRCUIT, SEMICONDUCTOR DEVICE, BATTERY MONITORING SYSTEM, CHARGING PROHIBITION METHOD, AND COMPUTER-READABLE MEDIUM THAT DETECTS BATTERY VOLTAGES LOWER THAN A LOWEST OPERATIONAL POWER SUPPLY VOLTAGE

LAPIS SEMICONDUCTOR CO., ...

1. A comparator circuit comprising:
a switching element having a first terminal connected to a positive electrode of a battery cell, a second terminal connected
to a first fixed potential supply source, and a control terminal that controls conduction between the first terminal and the
second terminal in response to an applied voltage;

a voltage regulating unit that has one end connected to a negative electrode of the battery cell, and another end connected
to the control terminal and to a second fixed potential supply source, and that regulates the applied voltage from the battery
cell to the switching element; and

an output signal line connected to a connecting portion of the second terminal and the first fixed potential supply source.

US Pat. No. 9,407,305

INSTRUCTION BEAM DETECTION APPARATUS AND METHOD OF DETECTING INSTRUCTION BEAM

LAPIS SEMICONDUCTOR CO., ...

1. An instruction beam detection apparatus, comprising:
an image capturing unit having a global shutter for capturing an image of an instruction beam intermittently irradiated from
a light source of a remote control device within a detection range thereof at a timing instructed externally with the global
shutter;

a filter unit for attenuating light irradiated on the image capturing unit in at least one of a short wave length range and
a long wave length range relative to a wave length range of the instruction beam;

a control unit for detecting an illumination cycle of the instruction beam according to the image captured with the image
capturing unit so that the image capturing unit is controlled to capture the image at a timing synchronized with an irradiation
timing of the instruction beam irradiated from the light source; and

a detection unit for detecting a position of the instruction beam on a third image according to the third image captured with
the image capturing unit in a state that the control unit controls the image capturing unit to capture the third image at
a controlled image capturing timing,

wherein said control unit is configured to detect the illumination cycle adjusted such that a cumulative intensity of light
in a wave length range different from that of the instruction beam becomes smaller than a specific value within one cycle
during which the image capturing unit captures the third image.

US Pat. No. 9,231,506

SEMICONDUCTOR DEVICE, ELECTRICAL DEVICE AND CONTROL SIGNAL, GENERATION METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a control data storage section that stores control signal data including a duty ratio for generating a pulse width modulation
(PWM) signal for controlling operation of a drive section, and control data including an update cycle, an update value, and
an update-times number of the duty ratio of the PWM signal;

a control signal generation section that generates the PWM signal based on the control signal data;
a storage control section that controls storage of control data in the control data storage section; and
a notification section that notifies an updating timing of the control signal data to the control signal generation section
based on the update cycle,

wherein the control signal generation section updates the control signal data based on the update value included in the control
data in response to the notification, and generates the PWM signal based on the updated control signal data, and

wherein the control signal generation section repeats the update in response to the notification based on the update-times
number.

US Pat. No. 9,356,637

POWER-SUPPLY DEVICE, METHOD FOR CONTROLLING THE SAME, AND COMMUNICATION DEVICE INCLUDING THE SAME

LAPIS SEMICONDUCTOR CO., ...

1. A power-supply device for sending out a first power-supply voltage having a first voltage value to a first power supply
line and a second power supply line in a first mode and sending out a second power-supply voltage having a second voltage
value lower than the first voltage value to the second power supply line in a second mode, the power-supply device comprising:
a first power-supply circuit that generates the first power-supply voltage having the voltage value of one of the first and
second voltage values and sends out the first power-supply voltage to the first power supply line;

a second power-supply circuit that generates the second power-supply voltage;
a first switch that connects between the first and second power supply lines in an ON state and cuts off the connection between
the first and second power supply lines in an OFF state;

a second switch that connects between the second power-supply circuit and the second power supply line in the ON state and
cuts off the connection between the second power-supply circuit and the second power supply line in the OFF state; and

a power-supply switching control circuit that when switching from the first mode to the second mode, the second mode state
is obtained by: changing the voltage value of the first power-supply voltage to be generated in the first power-supply circuit
to the second voltage value;
then setting the second switch in the ON state;subsequently setting the first switch in the OFF state; andthen stopping the operation of the first power-supply circuit, and when switching from the second mode to the first mode,
the first mode state is obtained by: generating the first power-supply voltage having the second voltage value in the first
power-supply circuit; then setting the first switch in the ON state; subsequently setting the second switch in the OFF state;
and then changing the voltage value of the first power-supply voltage to be generated in the first power-supply circuit to
the first voltage value.

US Pat. No. 9,899,448

SEMICONDUCTOR DEVICE HAVING SOI SUBSTRATE

LAPIS Semiconductor Co., ...

1. A photodiode-on-SOIS (silicon on insulator substrate) device, comprising:
a silicon on insulator (SOI) substrate that includes a first surface and a second surface opposite to the first surface;
a semiconductor layer that includes a third surface opposite to the first surface and a fourth surface opposite to the third
surface, the fourth surface having a semiconductor element disposed thereon;

an oxide film layer that is formed in contact with the first surface and the third surface;
a first diffusion layer that is included in the semiconductor layer in a planar view, that is formed on a surface opposite
to the third surface and that is connected to a reference potential, the oxide film layer being interposed between the surface
opposite to the third surface and the third surface;

a photodiode, including:
a second diffusion layer that is connected to the reference potential and that is formed in a part of a region of the first
surface corresponding to a region that is adjacent to the first diffusion layer in the planar view, and

a third diffusion layer that is formed in the part of the region of the first surface corresponding to the region that is
adjacent to the first diffusion layer in the planar view, and that is formed separately from the second diffusion layer; and

a voltage application unit that applies a voltage to the second surface and the third diffusion layer in order to form a depletion
layer for the photodiode in the SOI substrate.

US Pat. No. 9,313,071

OFDM MODULATION SIGNAL DEMODULATOR, RECEIVING APPARATUS, AND RECEIVING AND DISPLAYING APPARATUS

LAPIS Semiconductor Co., ...

9. An orthogonal frequency division multiplexing (OFDM) modulation signal receiving apparatus comprising:
a demodulating part that receives an OFDM modulation signal and demodulates the received OFDM modulation signal;
an autocorrelation calculating part that calculates an autocorrelation value of the OFDM modulation signal for each of a plurality
of predetermined periods;

an intra-interval total sum value calculating part that successively generates comparison result values, each representing
a deviation of the autocorrelation value from a threshold value, and sums up the generated comparison result values at predetermined
intervals to obtain an intra-interval total sum value for each of the predetermined intervals; and

an output part that selects a piece of autocorrelation level data from a plurality of pieces of autocorrelation level data
representing the obtained intra-interval total sum values and outputs the selected piece of autocorrelation level data.

US Pat. No. 9,197,217

SEMICONDUCTOR DEVICE, MEASUREMENT DEVICE, AND CORRECTION METHOD

LAPIS SEMICONDUCTOR CO., ...

14. A semiconductor device, comprising:
an oscillator configured to oscillate at an oscillation frequency that corresponds to a predetermined frequency but contains
an error caused by an operating temperature of the oscillator;

a semiconductor integrated circuit that integrates
a temperature sensor configured to detect a peripheral temperature of the oscillator, and
a controller that is electrically connected to the oscillator and that corrects the error in the oscillation frequency of
the oscillator based on the peripheral temperature detected by the temperature sensor;

a sealing member that integrally seals the oscillator and the semiconductor integrated circuit;
a first measurement section that measures an oscillation of the oscillator; and
a second measurement section that measures an oscillation of a reference frequency generation section that oscillates at a
higher frequency than the predetermined frequency,

wherein the controller
causes the second measurement section to measure until a measurement result of the first measurement section reaches a specific
value, and

derives the error in the oscillation frequency of the oscillator based on the measurement result of the first measurement
section.

US Pat. No. 9,437,734

SEMICONDUCTOR DEVICE WITH PROTECTIVE FILMS AND MANUFACTURING METHOD THEREOF

LAPIS SEMICONDUCTOR CO., ...

6. A semiconductor device comprising:
a semiconductor substrate including a drain part and a source part, the drain part and the source part being formed by doping
an impurity into the semiconductor substrate;

a first dielectric layer formed in an area between the source part and the drain part, the first dielectric layer including
a first portion and a second portion whose thickness is smaller than a thickness of the first portion;

a gate electrode formed on the area and disposed on the semiconductor substrate and the first and second portions of the first
dielectric layer;

a second dielectric layer formed to cover the gate electrode and a surface of the semiconductor substrate;
a metal layer formed on the second dielectric layer;
a first pad being electrically connected to the source part;
a second pad being electrically connected to the drain part;
a first protective film including silicon nitride as a principal component and being formed on the second dielectric layer
and formed to directly cover the metal layer; and

a second protective film containing carbon and being formed to directly cover the first protective film,
wherein the second protective film is any of a phospho-silicate glass (PSG) film containing carbon, a boron phospho-silicate
Glass (BPSG) film containing carbon, and an undoped silicon glass (USG) film containing carbon.

US Pat. No. 9,356,610

CLOCK DATA RECOVERY CIRCUIT AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A clock data recovery circuit configured to receive an input data signal formed of a series of input data pieces synchronized
with a reference clock signal, and to generate a regenerated clock signal, comprising:
a regenerated clock generating circuit configured to generate a plurality of regenerated clock signals having phases different
from each other by a half of a cycle of the reference clock signal;

a latch circuit configured to sequentially latch the input data signal at an edge timing of the regenerated clock signals
so that the latch circuit generates a plurality of latch data signals;

a comparison circuit configured to generate an up signal having a pulse width greater than the cycle of the reference clock
signal when n-th one (n is a natural number) of the latch data signals is different from (n+1)th one of the latch data signals
among the latch data signals, said comparison circuit is configured to generate a down signal having a pulse width greater
than the cycle of the reference clock signal when the (n+1)th one of the latch data signals is different from (n+2)th one
of the latch data signals, said comparison circuit is configured to generate a plurality of up signals and a plurality of
down signals;

a logical sum signal generating circuit configured to generate a first logical sum signal formed of a logical sum of the up
signals and a second logical sum signal formed of a logical sum of the down signals; and

a charge pump configured to generate a phase control voltage through charging electron charges according to the first logical
sum signal, and discharging the electron charges according to the second logical sum signal,

wherein said regenerated clock generating circuit is configured to correct phases of the regenerated clock signals according
to the phase control voltage.

US Pat. No. 9,620,629

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a P-type base region provided on a surface layer portion of an N-type semiconductor layer;
an N-type emitter region provided inside the P-type base region;
a P-type collector region that is provided on the surface layer portion of the N-type semiconductor layer separately from
the P-type base region;

a gate insulating film that is provided on the surface of the N-type semiconductor layer, and that contacts the P-type base
region and the N-type emitter region;

a gate electrode provided on the gate insulating film;
a pillar shaped structure provided inside the N-type semiconductor layer between the P-type base region and the P-type collector
region, one end of the pillar shaped structure being connected to an N-type semiconductor that extends to the surface layer
portion of the N-type semiconductor layer, and the pillar shaped structure comprising an insulator extending in a depth direction
of the N-type semiconductor layer; and

an insulator region provided between the P-type base region and the P-type collector region of the surface layer portion of
the N-type semiconductor layer, wherein the pillar shaped structure is separated from the insulator region with the N-type
semiconductor interposed between the pillar shaped structure and the insulator region.

US Pat. No. 9,559,041

SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a semiconductor substrate having a first main surface, and a second main surface opposing the first main surface, the first
main surface comprising a recess portion filled with an oxide film;

a wiring portion over the first main surface of the semiconductor substrate;
a through-type electrode having one end connected to the wiring portion, the through-type electrode penetrating through the
oxide film and penetrating through the semiconductor substrate from a bottom surface of the recess portion to the second main
surface, the through-type electrode connecting the first main surface and the second main surface of the semiconductor substrate;
and

a protruding electrode on the second main surface and connected to another end of the through-type electrode.

US Pat. No. 9,350,292

OSCILLATION CIRCUIT, CURRENT GENERATION CIRCUIT, AND OSCILLATION METHOD

LAPIS SEMICONDUCTOR CO., ...

1. An oscillation circuit comprising:
a first current source having a dependency of current value on temperature exhibiting a first characteristic;
a second current source having a dependency of current value on temperature exhibiting a second characteristic;
a first conversion section that is input with a current from the first current source and configured to output a first current
including a specific characteristic which is converted from the first characteristic;

a second conversion section that is input with a current from the second current source and configured to output a second
current including the specific characteristic which is converted from the second characteristic;

a subtraction section that is input with the first current and the second current and a difference current that is a difference
between the first current and the second current; and

a clock generation section configured to generate a clock signal by alternately charging and discharging a first capacitor
and a second capacitor based on the difference current,

wherein the first characteristic and the second characteristic are represented by respective linear functions, both of the
linear functions having a gradient in a same direction.

US Pat. No. 9,293,216

SEMICONDUCTOR DEVICE AND METHOD OF SEARCHING FOR ERASURE COUNT IN SEMICONDUCTOR MEMORY

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a semiconductor memory in which data erasure is performed in units of blocks;
a block management memory that stores, corresponding to each of the blocks, an erasure count data piece representing a data
erasure count performed in the block;

a read address generation circuit that generates a read address signal in response to a search start instruction and provides
the read address signal to the block management memory to successively read the erasure count data pieces from the block management
memory; and

a minimum erasure count search circuit that searches for a block corresponding to an erasure count data piece representing
a minimum erasure count from among the erasure count data pieces read from the block management memory,

the minimum erasure count search circuit including:
a first latch that outputs, when the erasure count data piece read from the block management memory represents an erasure
count smaller than a minimum erasure count data piece, the erasure count data piece as the minimum erasure count data piece;
and

a second latch that outputs, when the erasure count data piece read from the block management memory represents an erasure
count smaller than the minimum erasure count data piece, an address indicated by the read address signal as a minimum erasure
count address.

US Pat. No. 9,660,795

START-STOP SYNCHRONOUS TYPE SERIAL DATA ACQUISITION DEVICE AND START-STOP SYNCHRONOUS TYPE SERIAL DATA ACQUISITION METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A start-stop synchronous type serial data acquisition device for acquiring serial data in start-stop synchronous type serial
communication, the start-stop synchronous type serial data acquisition device comprising:
a counter to which a clock signal that defines an acquisition timing of the serial data including a start bit is input, and
that is configured to count a number of cycles of the clock signal;

a changing circuit that, according to a transition of the clock signal when the start bit has been input, is configured to
change a maximum count value that is counted by the counter, the maximum count value corresponding to the start bit; and

a received data acquisition circuit configured to acquire the serial data per frame, each frame including start bits, data
bits and stop bits, wherein the received data acquisition circuit is configured to start to acquire the serial data in a case
in which the maximum count value is provided from the counter.

US Pat. No. 9,432,029

FREQUENCY MODULATION CIRCUIT AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A frequency modulation circuit comprising:
a modulation part for performing a frequency modulation with an input data signal while calibrating a modulation index based
on a calibration value;

a transmission frequency band setting part for selecting and setting a transmission frequency band in accordance with a given
channel selection signal within an entire transmission frequency range; and

a calibration-operating part for calculating, on the basis of said input signal, primary calibration values of the modulation
index at the central frequencies of respective ones of n (where the n denotes an integer of 2 or more) pieces of transmission
frequency bands which constitute said entire transmission frequency range, further comprising;

an interpolation-calculation part for performing an interpolation-calculation with respect to said n pieces of said primary
calibration values and calculating calibration values at intermediate frequencies of the central frequencies of neighboring
ones of the transmission frequency bands while calculating calibration values at frequencies at both ends of said entire transmission
frequency range to obtain (n+1) pieces of interpolated calibration values as secondary calibration values; and

a calibration value supply part for selecting one calibration value corresponding to the transmission frequency bands set
in said transmission frequency band setting part from among said n pieces of the primary calibration values or (n+1) pieces
of the secondary calibration values, and supplying the selected calibration value to said modulation part.

US Pat. No. 9,423,466

SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor circuit connected to a lower stage semiconductor chip and a higher stage semiconductor chip, comprising:
a first terminal directly connected to a power source line connected in series to a plurality of power source supply portions;
a first communication circuit for performing signal communication with the lower stage semiconductor chip according to a first
reference voltage supplied from the first terminal and a first power source voltage;

a second communication circuit for performing signal communication with the higher stage semiconductor chip according to a
second reference voltage greater than the first reference voltage and a second power source voltage greater than the first
power source voltage and the second reference voltage;

a level shift circuit for level shifting a first signal to a level corresponding to the second reference voltage of the second
communication circuit and the second power source voltage when the first signal is input to the first communication circuit
from the lower stage semiconductor chip, said level shift circuit being arranged to level shift a second signal to a level
corresponding to the first reference voltage of the first communication circuit and the first power source voltage when the
second signal is input to the second communication circuit from the higher stage semiconductor chip;

a voltage adjustment circuit for supplying the first power source voltage to the first communication circuit and outputting
the first power source voltage externally;

a second terminal connected to the power source line through a first filter for supplying a third power source voltage to
the voltage adjustment circuit;

a third terminal directly connected to the power source line without disposing any grounded circuitry element in parallel
to the third terminal and the power source line for supplying the second reference voltage to the second communication circuit;
and

a fourth terminal connected to the higher stage semiconductor chip for supplying the first power source voltage of the higher
stage semiconductor chip output from the higher stage semiconductor chip as the second power source voltage to the second
communication circuit.

US Pat. No. 9,202,589

NON-VOLATILE MEMORY AND SEMICONDUCTOR DEVICE

LAPIS Semiconductor Co., ...

1. A non-volatile memory comprising:
a plurality of zener zap devices, each of the zener zap devices formed in a well and including a cathode region on each side
of an anode region and a dual-presence region in which both a cathode region and an anode region are present between each
cathode region and the respective side of the anode region, wherein the plurality of zener zap devices are arranged in a linear
direction such that a zener zap device of the plurality of zener zap devices shares two cathode regions with adjacent zener
zap devices of the plurality of zener zap devices; and

a metal wiring line overlapping each dual-presence region of the plurality of zener zap devices, commonly connected to each
of the cathode regions, and supplying a write voltage to each of the zener zap devices.

US Pat. No. 9,407,146

POWER SOURCE CIRCUIT AND METHOD OF CONTROLLING POWER SOURCE CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. A power source circuit, comprising:
a power source terminal for inputting a power source voltage;
a switching regulator including a switching circuit connected to the power source terminal and a smoothing circuit connected
to the switching circuit;

a series regulator connected to the switching regulator in series;
a switching portion; and
a control portion,
wherein said smoothing circuit includes a capacitor and an inductor so that the smoothing circuit smoothes an output from
the switching circuit to output a first voltage,

said series regulator is connected to the switching circuit and the smoothing circuit in series, and is configured to receive
the first voltage or the power source voltage so that the series regulator outputs a second voltage,

said switching portion has a first terminal connected to the power source and a second terminal connected between the switching
regulator and the series regulator so that the switching portion supplies the power source voltage to the series regulator,

said control portion is configured to output a control signal for controlling an operation state in which the series regulator
outputs the second voltage and an idle state in which the switching regulator and the series regulator stop operating, and

said control portion is configured to measure the power source voltage during the operation state, and to output a switching
signal for controlling the switching portion to turn on or off in the idle state according to a measurement result of the
power source voltage.

US Pat. No. 9,252,779

SEMICONDUCTOR DEVICE AND METERING APPARATUS

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
an oscillator;
a semiconductor chip that includes an oscillation circuit connected to the oscillator, a timer circuit that generates a timing
signal of a frequency according to an oscillation frequency of the oscillation circuit, a measurement counter that receives
an output signal of the oscillation circuit and counts the output signal, a reference counter that receives a reference signal
and counts the reference signal, and a frequency correction section that connects the measurement counter and the reference
counter and that corrects a frequency of the timing signal based on temperature data and a comparison result that is obtained
by comparing a count value of the measurement counter within a predetermined period and a count value of the reference counter
within the predetermined period; and

a discrete device that includes at least one of a temperature sensing device that detects a peripheral temperature, that supplies
the detected temperature as temperature data to the frequency correction section, and that is provided as a separate body
to the semiconductor chip, or a capacitor that is electrically connected to both the oscillator and the oscillation circuit
and that is provided as a separate body to the semiconductor chip;

wherein the oscillator, the semiconductor chip and the discrete device are contained within a single package.

US Pat. No. 9,203,667

CIRCUIT AND METHOD FOR REMOVING FREQUENCY OFFSET, AND COMMUNICATION APPARATUS

LAPIS Semiconductor Co., ...

1. A circuit for removing a frequency offset of a baseband signal, the circuit comprising:
a sampling circuit which samples a frequency level of the baseband signal at every first interval to obtain a sequence of
sample levels;

a first difference absolute value calculating part which calculates first absolute values of differences between the frequency
levels adjacent to each other at every second interval having two times length of the first interval based on an arbitrary
first frequency level of the sample levels as a plurality of first difference absolute values;

a second difference absolute value calculating part which calculates second absolute values of differences between the frequency
levels adjacent to each other at every interval of the second interval based on a second frequency level of the sample levels
after the first interval from the first frequency level as a plurality of second difference absolute values;

first comparing parts which compare the plurality of first difference absolute values with a predetermined first determination
value to generate first comparison result values;

second comparing parts which compare the plurality of second difference absolute values with a predetermined second determination
value to generate second comparison result values;

an average calculating part which calculates an average value based on the sequence of the sample levels; and
a frequency offset holding part which includes a non-selecting part in which a non-selection signal indicative of non-selection
of at least one comparison result value of the first and second comparison result values is input, and which sets the average
value calculated by the average calculating part into the frequency offset when the first comparison result values other than
the at least one comparison result value corresponding to the non-selecting signal indicate that the first difference absolute
values are greater than the first determination value or the second comparison result values other than the at least one comparison
result value corresponding to the non-selecting signal indicate that the second difference absolute values are less than the
second determination value.

US Pat. No. 9,570,011

SOURCE DRIVER IC CHIP

LAPIS Semiconductor Co., ...

1. A source driver IC chip formed on a rectangular-shaped substrate, and being configured to apply a driving pulse having
a first gradation voltage based on a first gamma characteristic and a driving pulse having a second gradation voltage based
on a second gamma characteristic to each of a plurality of source lines formed on a display panel in response to a video signal,
said source driver IC chip comprising:
a reference gradation voltage generating part configured to generate a reference gradation voltage based on said first gamma
characteristic or a reference gradation voltage based on said second gamma characteristic based on a first power supply voltage
inputted through a first external terminal and a second power supply voltage inputted through a second external terminal,
and output the generated reference gradation voltage through a third external terminal;

a first gradation voltage generating part configured to generate said first gradation voltage based on said reference gradation
voltage based on said first gamma characteristic inputted through a fourth external terminal;

a second gradation voltage generating part configured to generate said second gradation voltage based on said reference gradation
voltage based on said second gamma characteristic inputted through a fifth external terminal;

a first drive part configured to generate said driving pulse having said first gradation voltage and said driving pulse having
said second gradation voltage in response to said video signal to apply the generated driving pulses to a first source line
group of said source lines; and

a second drive part configured to generate said driving pulse having said first gradation voltage and said driving pulse having
said second gradation voltage in response to said video signal to apply the generated driving pulses to a second source line
group of said source lines,

wherein said first and second drive parts are disposed along one of peripheral parts of said substrate, and said reference
gradation voltage generating part is disposed in an intermediate area located between an area where said first drive part
is disposed and an area where said second drive part is disposed.

US Pat. No. 9,484,472

SEMICONDUCTOR DEVICE, ELECTRICAL DEVICE SYSTEM, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device, comprising:
a first semiconductor layer having a first conductive type;
a circuit layer including a second semiconductor layer, said circuit layer being formed on one main surface of the first semiconductor
layer, said second semiconductor layer including a circuit element and having a second conductive type opposite to the first
conductive type;

a multilayer wiring layer including a first layered member at an uppermost position and a second layered member at a lowermost
position;

a penetrating conductive member;
a conductive portion; and
a first conductive type region formed on the one main surface of the first semiconductor layer and connected to the conductive
portion,

wherein each of said first layered member and said second layered member includes an interlayer insulation film and a wiring
layer formed on the interlayer insulation film,

said wiring layer of the first layered member includes a connecting point connected to a positive electrode of a voltage applying
unit or a ground;

said interlayer insulation film of the second layered member is situated on the circuit layer,
said wiring layer of the second layered member is connected to the circuit element,
said penetrating conductive member is disposed to penetrate from the one main surface of the first semiconductor layer to
the interlayer insulation film of the first layered member through the circuit layer and the multi layer wiring layer,

said conductive portion includes an electrode formed in the wiring layer of the first layered member and connected to the
penetrating conductive member,

said conductive portion is configured to be electrically isolated from both the circuit element and the wiring layer of the
first layered member, and

said first conductive type region has an impurity concentration greater than that of the first semiconductor layer.

US Pat. No. 9,417,683

DRIVING DEVICE FOR DRIVING A DISPLAY UNIT

LAPIS SEMICONDUCTOR CO., ...

1. A driving device for a display unit which displays an image based on a video data signal during each frame display period
including a data scanning period and a blanking period, comprising:
a data driver that applies pixel drive voltages respectively corresponding to luminance levels of each pixel based on said
video data signal to multiple data lines of said display unit in each horizontal scanning cycle during said data scanning
period as long as power supply thereto is kept; and

a drive controller that performs power supply to said data driver and superimposes a reference timing signal on said video
data signal and supplies the video data signal to said data driver,

wherein said data driver comprises:
a clock data recovery circuit that generates a clock signal synchronized in phase with said reference timing signal extracted
from said video data signal;

a data taking-in unit that sequentially takes in respective pixel data denoting luminance levels of each pixel based on said
video data signal in response to said clock signal and, each time that one horizontal scan line worth of pixel data has been
taken in, outputs the one horizontal scan line worth of pixel data; and

a pixel-driving voltage outputting unit that generates said pixel drive voltages corresponding to the pixels based on their
respective pixel data in said one horizontal scan line worth of pixel data outputted from said data taking-in unit to supply
to said multiple data lines, and

wherein said drive controller stops the power supply to said clock data recovery circuit and said data taking-in unit for
a first power stop period within said blanking period, and stops the power supply to said pixel-driving voltage outputting
unit for a second power stop period within said blanking period.

US Pat. No. 9,255,850

TEMPERATURE DETECTION CIRCUIT AND METHOD OF ADJUSTING THE SAME

LAPIS SEMICONDUCTOR CO., ...

1. A temperature detection circuit for generating a temperature detection signal indicating a temperature of a semiconductor,
comprising:
first and second diodes having respective p-n junctions independent from each other;
a first current path including a first variable voltage dividing resistor that is connected in series to the first diode and
whose dividing resistance ratio is variable according to a first offset adjustment signal, the first variable voltage dividing
resistor producing a first divided voltage;

a second current path including a second variable voltage dividing resistor that is connected in series to the second diode
and whose dividing resistance ratio is variable according to a second offset adjustment signal, the second variable voltage
dividing resistor producing a second divided voltage, the second current path having a node between the second diode and the
second variable voltage dividing resistor;

a reference voltage generation part that includes first and second input terminals and that generates a differential voltage
from the first divided voltage applied to the first input terminal and a potential at the node in the second current path
that is applied to the second input terminal, the reference voltage generation part applying the differential voltage to an
end of the first current path and also to an end of the second current path and additionally outputting the differential voltage
as a reference voltage, the differential voltage indicating a difference between the first divided voltage produced by the
first variable voltage dividing resistor and the potential at the node in the second current path; and

a temperature detection signal generation part that generates the temperature detection signal, the temperature detection
signal generation part receiving the second divided voltage produced by the second variable voltage dividing resistor, the
temperature detection signal generation part including an amplification part that amplifies the second divided voltage to
obtain an amplified voltage and a third variable voltage dividing resistor that adjusts a gain of the amplification part according
to a third offset adjustment signal; and

a fourth variable voltage dividing resistor that adjusts a level of the amplified voltage output from the second amplifier
according to a temperature gradient adjustment signal.

US Pat. No. 9,208,716

DISPLAY DRIVE CIRCUIT INCLUDING AN OUTPUT TERMINAL

LAPIS SEMICONDUCTOR CO., ...

1. A display system, comprising:
a display panel for displaying an image, the display panel including a glass substrate;
a plurality of lead lines formed on the glass substrate; and
a display drive circuit for controlling the displaying of the image by the display panel, the display drive circuit being
formed as a chip and connected to the lead lines, the display drive circuit comprising:

a rectangularly-shaped substrate having a main surface and having a longer side that is longer than another side of the rectangularly-shaped
substrate;

a power supply line formed on the main surface of the rectangularly-shaped substrate, the power supply line being disposed
along the longer side of the rectangularly-shaped substrate;

a plurality of switches disposed along the power supply line, each of which is connected to the power supply line;
a plurality of output terminals formed on the main surface of the rectangularly-shaped substrate and connected to the power
supply line between an end portion of the power supply line and a center portion of the power supply line;

first ground terminals formed at the end portion of the power supply line; and
second ground terminals formed at the center portion of the power supply line
wherein an amount of a current flowing in the power supply line to the first ground terminals is smaller than an amount of
a current flowing in the power supply line to the second ground terminals.

US Pat. No. 9,094,911

DATA COMMUNICATION SYSTEM, METHOD OF OPTIMIZING PREAMBLE LENGTH, AND COMMUNICATION APPARATUS

LAPIS SEMICONDUCTOR CO., ...

1. A data communication system comprising:
a transmission apparatus for transmitting a frame in response to a transmission command supplied thereto, and a receiving
apparatus for receiving said frame, said frame including a preamble, a start frame delimiter (SFD), and data in that order;

wherein said receiving apparatus includes:
a synchronization detection part which detects bit synchronization based on the preamble of the frame received by the receiving
apparatus from the transmitting apparatus;

a synchronization position information generating part which generates synchronization position information of a position
of the bit synchronization, included in the frame received in the receiving apparatus, detected by the synchronization detection
part, said synchronization position information generating part comprising a counter part to generate a bit number corresponding
to a time period between a first time point at which the bit synchronization is detected by the synchronization detection
part and a second time point at which the SFD of the frame is detected;

a transmitting and receiving part which transmits a frame including said synchronization position information to said transmission
apparatus;

wherein said transmission apparatus includes:
a preamble length calculating part which calculates a number of reduced bytes by subtracting a number of bits of the SFD from
said bit number and dividing by the bit number of one byte, and calculates an optimal value of a length of the preamble by
subtracting the number of reduced bytes from an initial preamble length; and

a transmit command issuing part which supplies said transmit command of transmission of a frame including a preamble having
a length based on the optimal value from the transmission apparatus to the receiving apparatus; and

a transmitting and receiving part which adjusts the preamble length of a frame toward said optimal value and transmits the
frame as a wireless signal.

US Pat. No. 10,043,743

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
a first conductive layer disposed on the second main surface;
a through hole passing through the semiconductor substrate from the first main surface to the second main surface to expose the first conductive layer at a bottom portion thereof;
an insulation film extending from the bottom portion of the through hole on a side of the second main surface to the first main surface through a side surface of the through hole;
an organic insulation film formed on the insulation film formed on the bottom portion of the through hole, the side surface of the through hole, and the first main surface; and
a second conductive layer formed to cover the organic insulation film formed on the bottom portion of the through hole, the side surface of the through hole, and the first main surface,
wherein said second conductive layer has a layer thickness on the first main surface greater than that thereof in the through hole.

US Pat. No. 9,602,090

SKEW ADJUSTMENT APPARATUS

LAPIS SEMICONDUCTOR CO., ...

1. A skew adjustment apparatus for adjusting a skew of a clock signal based on an original data signal on which the clock
signal is superimposed, the skew adjustment apparatus comprising:
a skew adjustment delay unit that generates first to N-th (N is an integer of 2 or more) delayed data signals being respectively
delayed from said original data signal by N number of different amounts of delay;

a decoder that generates first to N-th selection signals corresponding to the first to N-th delayed data signals and each
instantaneously having a first logic level when it represents selection and a second logic level when it represents deselection,
based on selection designation data applied thereto for designating selection of one of the first to N-th delayed data signals;

first to N-th transition delay units that generate first to N-th delayed selection signals by individually latching and delaying
the first to N-th selection signals; and

a data selection unit that selects a delayed data signal corresponding to a delayed selection signal having the first logic
level among the first to N-th delayed selection signals from among the first to N-th delayed data signals, and outputs the
delayed data signal selected,

wherein the first to N-th transition delay units delaying the first to N-th selection signals by a greater amount of delay
when the respective selection signals transition from the first logic level to the second logic level according to the selection
designation data than when the respective selection signals transition from the second logic level to the first logic level.

US Pat. No. 9,461,056

NON-VOLATILE MEMORY AND SEMICONDUCTOR DEVICE

LAPIS Semiconductor Co., ...

1. A non-volatile memory comprising:
a plurality of zener zap devices, each of the zener zap devices including a cathode region on each side of an anode region
and a dual-presence region in which both a cathode region and an anode region are present between each cathode region and
the respective side of the anode region, wherein the plurality of zener zap devices are arranged in a linear direction such
that a zener zap device of the plurality of zener zap devices shares two cathode regions with adjacent zener zap devices of
the plurality of zener zap devices; and

a metal wiring line overlapping each dual-presence region of the plurality of zener zap devices, commonly connected to each
of the cathode regions.

US Pat. No. 9,450,418

POWER SUPPLY DEVICE, METHOD FOR CONTROLLING THE POWER SUPPLY DEVICE, AND ELECTRONIC APPARATUS

LAPIS SEMICONDUCTOR CO., ...

1. A power supply device, comprising:
a first power supplying part which produces a first voltage;
a second power supplying part which produces a second voltage, the second power supplying part having an output current capacity
smaller than the first power supplying part;

a comparator for comparing a magnitude of the first voltage and a magnitude of the second voltage with each other; and
voltage control signal generation means for generating a voltage control signal on the basis of the comparison, wherein
the second power supplying part controls a voltage value of the second voltage so as to bring the voltage value of the second
voltage closer to a voltage value of the first voltage in response to the voltage control signal.

US Pat. No. 9,443,811

SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
at least one pad group including a plurality of pads provided on a semiconductor substrate and arranged in a row to form a
pad row as a whole, wherein

said pad group includes
at least one first pad provided with a first via-connection part electrically connected therewith and extended in a first
direction perpendicular to a row direction of the pad row, and

at least one second pad provided with a second via-connection part electrically connected therewith and extended in a second
direction opposite to the first direction,

said second pad is formed at a position moved in the first direction from the row direction of the pad row passing through
a center of said first pad, and

said first and second via-connection parts are connected to a circuit block provided in said semiconductor substrate.

US Pat. No. 9,430,340

INFORMATION PROCESSING DEVICE AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. An information processing device which includes a plurality of memories, comprising:
a verification control part that controls the plurality of memories to write a same write information data piece into each
of the plurality of memories according to a write instruction and then to read out information data pieces from the plurality
of memories; and

a coincidence determining part that performs a first verification to determine whether the respective read-out information
data pieces read out from the plurality of memories by the verification control part coincide with each other and outputs
a verification result signal representing a determination result,

wherein the verification control part is configured to output one of the read-out information data pieces as an information
data piece for memory checking,

wherein said write information data piece is a program data representing a program, said information processing device further
comprising:

a central processing unit (CPU) that, in response to power-on, reads out the program data from one memory of the plurality
of memories and performs a control function according to the program data read out from the one memory; and

a receive part that receives program data for a version upgrade and a version upgrade instruction signal,
wherein said CPU, in response to the reception of the version upgrade instruction signal, has the program data for version
upgrade written into the one memory of the plurality of memories.

US Pat. No. 10,121,871

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor layer including a first conductivity type semiconductor region and a second conductivity type semiconductor region joined to the first conductivity type semiconductor region;
a surface electrode connected to the second conductivity type region on one surface of the semiconductor layer, including a first Al-based electrode being in direct contact with the second conductivity type semiconductor region, a second Al-based electrode, a barrier metal interposed between the first Al-based electrode and the second Al-based electrode, and a plated layer on the second Al-based electrode; and
an insulating layer being in direct contact with the second conductivity type semiconductor region,
wherein the first Al-based electrode has an extending portion extending along an upper surface of the insulating layer and being in direct contact with the upper surface, and
the extending portion of the first Al-based electrode has an end portion on the upper surface of the insulating layer.

US Pat. No. 9,857,432

BATTERY MONITORING SYSTEM, SEMICONDUCTOR CIRCUIT, LINE-BREAKAGE DETECTION PROGRAM, AND LINE-BREAKAGE DETECTION METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A battery monitoring system comprising:
a plurality of batteries connected together in series;
a discharging unit including a resistor element provided straddling between a first signal line connected to a high potential
side in the plurality of respective batteries and a second signal line connected to a low potential side in the plurality
of respective batteries, and a discharge switching element connected in series with the resistor element;

a potential adjusting unit that is connected to the first signal line and supplies a lower potential than the potential of
the second signal line in cases in which the discharge switching element is provided between the resistor element and the
second signal line, and that is connected to the second signal line and supplies a higher potential than the potential of
the first signal line in cases in which the discharge switching element is provided between the resistor element and the first
signal line; and

a comparison unit that compares a first potential between the resistor element and the discharge switching element, against
a threshold voltage set from the potential of the first signal line and the potential of the second signal line.

US Pat. No. 9,813,675

SEMICONDUCTOR DEVICE, VIDEO DISPLAY SYSTEM, AND METHOD OF PROCESSING SIGNAL

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device, comprising:
a first input unit configured to receive a first signal;
a first processing unit configured to perform a frequency dispersion processing on the first signal;
a first output unit configured to output the first signal or the first signal on which the first processing unit performs
the frequency dispersion processing;

a second input unit configured to receive a second signal generated through performing a predetermined image processing with
an image processing unit on the first signal output from the first output unit;

a second processing unit configured to perform the frequency dispersion processing on the second signal; and
a second output unit configured to output one of the first signal and the second signal on which the frequency dispersion
process is performed as an output signal.

US Pat. No. 9,453,881

OSCILLATION CIRCUIT, INTEGRATED CIRCUIT, AND ABNORMALITY DETECTION METHOD

LAPIS SEMICONDUCTOR CO., ...

1. An oscillation circuit for use with an internal circuit of an IC (Integrated Circuit), comprising:
a main oscillation circuit that outputs a predetermined main clock signal to the internal circuit;
a sub oscillation circuit that outputs a sub clock signal having a frequency that is different from a frequency of the main
oscillation circuit;

a first abnormality detection section that detects a first abnormality according to a number of main clock signal cycles output
from the main oscillation circuit within a predetermined period corresponding to the sub clock signal output from the sub
oscillation circuit; and

a second abnormality detection section that detects a second abnormality according to a frequency divided clock signal of
the main clock signal output from the main oscillation circuit that has been frequency-divided and the sub clock signal output
from the sub oscillation circuit, based on whether or not the frequency divided clock signal is unchanged in a predetermined
period; and

an OR circuit that receives input signals generated by the first and second abnormality detection sections and that outputs
an abnormality detection signal when either the first abnormality detection section detects the first abnormality or the second
abnormality detection section detects the second abnormality, the OR circuit outputting a normal detection signal when neither
the first abnormality detection section detects the first abnormality nor the second abnormality detection sections detects
the second abnormality,

wherein the first abnormality detection section comprises a pair of comparators, and wherein the OR circuit receives input
signals generated by both of the comparators.

US Pat. No. 9,417,682

DISPLAY UNIT DRIVING DEVICE WITH REDUCED POWER CONSUMPTION

LAPIS SEMICONDUCTOR CO., ...

1. A driving device for driving a display unit, to thereby cause the display unit to display a sequence of images corresponding
to a video data signal, the displaying unit having m horizontal scan lines and n data lines, m and n each being an integer
larger than 1, the driving device comprising:
a drive controller configured to generate a pixel data sequence signal that corresponds to luminance levels of pixels of the
sequence of images, and that includes a series of frame data pieces, each frame data piece including m pieces of line data
respectively corresponding to the m horizontal scan lines; and

a data driver configured to import the pixel data sequence signal, and to apply, to the n data lines, pixel drive voltages
corresponding to the luminance levels denoted by the pixel data sequence signal,

wherein the drive controller is configured
to determine whether the video data signal is provided by a still-image provider or by a moving-image provider,
upon determining that the video data signal is provided by a still-image provider, to cause the data driver to operate in
a first power saving mode in which power supply to the data driver is stopped, and

upon determining that the video data signal is provided by a moving-image provider, to cause the data driver to operate in
a second power saving mode, in which the data driver stops importing the pixel data sequence signal in response to coincidence
of two neighboring pieces of the line data that correspond to two neighboring ones of the m horizontal scan lines.

US Pat. No. 9,377,307

SEMICONDUCTOR DEVICE, ELECTRICAL DEVICE, AND METHOD OF CONTROLLING POWER SOURCE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device, comprising: an atmospheric pressure value obtaining unit configured to obtain an atmospheric pressure
value from an atmospheric pressure sensor;
a moving state determining unit configured to determine a moving state of the semiconductor device as one of a moving state
in an automobile, a moving state on a train, a walking state, and a running state; and

a control unit configured to detect a variance state of the atmospheric pressure value obtained with the atmospheric pressure
value obtaining unit,

wherein said control unit is configured to control an on state and an off state of a power source of a GPS (Global Positioning
System) device according to a determination whether the variance state satisfies a specific condition,

said control unit is configured to control the on state and the off state of the power source of the GPS according to the
specific condition corresponding to the moving state determined with the moving state determining unit,

said moving state determining unit includes a geomagnetic sensor configured to determine the moving state of the semiconductor
device as the moving state in the automobile or the moving state on the train, and

wherein said control unit is configured to determine whether the semiconductor device is located in a tunnel according to
the variance state and the specific condition, and

said control unit is configured to control the power source of the GPS to turn off when the control unit determines that the
semiconductor device is located in the tunnel,

wherein said control unit is configured to control the power source of the GPS to turn on when the control unit determines
that the semiconductor device is not located in the tunnel,

said GPS device is configured to detect a position thereof based on a GPS signal received therewith and output positional
information.

US Pat. No. 9,350,531

COMMUNICATION DEVICE, CONTROL SIGNAL GENERATION METHOD, SHUTTER GLASSES, AND COMMUNICATION SYSTEM

LAPIS SEMICONDUCTOR CO., ...

12. A communication device, comprising:
a demodulating part which demodulates a received signal into a digital signal;
a data processing part which acquires said digital signal from said demodulating part and extracts data in said digital signal;
a timing signal identifying part which acquires said digital signal from said demodulating part and identifies whether or
not a predetermined reference timing signal pattern is present in said data;

a detection signal generating part which generates a timing detection signal upon completion of reception of a packet including
said data when said timing signal identifying part identifies that the predetermined reference timing signal pattern is present;
and

a control signal generating part which generates a control signal for a controlled device at a timing based on the completion
of reception of the signal, under a condition such that said predetermined reference timing signal pattern is identified as
being present,

wherein said data processing part and said timing signal identifying part operate respectively in response to said demodulating
part.

US Pat. No. 9,070,482

MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor memory device comprising:
a plurality of memory chips;
a memory controller chip that designates an address of one of said memory chips according to an access request received from
outside and controls access to the designated address;

a common bus configured to transmit signals between the memory controller chip and the memory chips; and
dedicated buses separated from said common bus and provided for each of the memory chips and configured to transmit signals
between said memory controller chip and said memory chips,

wherein each of the memory chips includes first and second storage regions, and an information holder that holds address information
representing an association between a specific address corresponding to a defective cell in the first storage region and an
address in the second storage region, and

the memory controller chip includes an address translating part that performs, upon receiving a request to access the specific
address in the first storage region indicated by the address information, address designation by translating the specific
address in the first storage region to an address in the second storage region corresponding to the specific address based
on the association represented by the address information,

wherein said address information represents an association between an address of a defective cell in the first storage region
and an address of a memory cell in the second storage region,

the memory controller chip includes a table holder that holds a table including said address information,
the address translating part performs address translation based on said address information included in the table, wherein
said memory controller chip includes a plurality of table holders which are provided respectively in association with said
plurality of memory chips, and the address information in each of the plurality of table holders represents an association
between an address of a defective cell in the first storage region and an address of a memory cell in the second storage region
in each of the plurality of memory chips, and

wherein said memory control chip designates a translated address in the second storage region via the dedicated bus in accordance
with a request to access the address of the defective cell in the first storage region, and designates a requested address
in the first storage region via the common bus in accordance with a request to access the address of the non-defective cell
in the first storage region.

US Pat. No. 9,865,312

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
an output driver having a variable current driving ability, for outputting an amplified data signal to outside through a transmission
line;

a nonvolatile memory having a specific area for storing output adjustment data to adjust the current driving ability of the
output driver;

an output adjustment data readout unit for reading out the output adjustment data from the specific area of the memory in
response to powering on; and

a current driving ability adjustment unit for adjusting the current driving ability of the output driver on a basis of the
output adjustment data read out from the memory.

US Pat. No. 9,812,417

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a substrate including, in a central portion of a main face of the substrate, n first element formation regions having a rectangular
flat plane shape and are arrayed along a first direction, and n+m second element formation regions having the same shape as
the first element formation regions and are arrayed along the first direction and adjacent to the first element formation
regions in a second direction intersecting the first direction;

a plurality of projecting electrodes formed at each of the first element formation regions and at each of the second element
formation regions; and

a plurality of dummy projecting electrodes formed, at a peripheral portion of the main face, overlapping a triangle defined
by a first edge of the first element formation region that forms a boundary between the first element formation region and
the peripheral portion, and a second edge of the second element formation region, the second edge being adjacent to a corner
of the first edge and that forms a boundary between the second element formation region and the peripheral portion.

US Pat. No. 9,601,065

DISPLAY PANEL DRIVER SETTING METHOD, DISPLAY PANEL DRIVER, AND DISPLAY APPARATUS INCLUDING THE SAME

LAPIS SEMICONDUCTOR CO., ...

1. A display panel driver setting method for setting a plurality of display panel drivers in accordance with specifications
based on a drive condition setting data stored in and read out from a memory, said plurality of display panel drivers being
configured to drive a single display panel that displays an image corresponding to a video signal, said method comprising:
causing one of said plurality of display panel drivers to supply a first signal indicating that said drive condition setting
data becomes a readout condition to said memory and to remaining ones of the display panel drivers:

causing said one display panel driver to fetch said drive condition setting data, which is read from said memory through a
common data line, to perform setting based on said drive condition setting data; and

causing said remaining ones of said plurality of display panel drivers to fetch said drive condition setting data all at once
from said common data line in response to said first signal supplied from said one display panel driver to perform said setting
based on said drive condition setting data.

US Pat. No. 9,502,352

SEMICONDUCTOR WIRING PATTERNS

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device having a rectangular semiconductor element mounted on a substrate formed with an external input
terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal
and the external output terminal, wherein,
the semiconductor element comprises:
a plurality of first electrodes formed along a first edge of the semiconductor element;
a plurality of second electrodes formed along a second edge opposite to the first edge of the semiconductor element;
a plurality of third electrodes formed in a neighborhood of a functional block; and
an internal wiring for connecting each of the first electrodes with the third electrodes, and
the substrate comprises
a first wiring pattern for connecting the external input terminal and the first electrodes;
a second wiring pattern for connecting the external output terminal and the second electrodes; and
a third wiring pattern for connecting the first electrodes with the third electrodes,
wherein for each first electrode, there is at least one corresponding third electrode such that a first wiring path and a
second wiring path connect between said first electrode and said at least one corresponding third electrode, the first wiring
path being part of the internal wiring of the semiconductor element and the second wiring path being part of the third wiring
pattern of the substrate.

US Pat. No. 9,503,136

RECEIVER AND RECEIVING METHOD OF RECEIVER

LAPIS SEMICONDUCTOR CO., ...

1. A receiver comprising:
an amplifying circuit for amplifying a received high frequency signal to obtain a reception signal;
a local oscillation circuit for generating a local oscillation signal;
a mixing circuit for mixing the reception signal with the local oscillation signal to generate a first intermediate frequency
signal;

a low-pass filter circuit for obtaining a component of a low frequency band of the first intermediate frequency signal, as
a second intermediate frequency signal;

a band-pass filter circuit for obtaining a component of a desired channel band of the second intermediate frequency signal,
as a selected intermediate frequency signal;

an interfering wave determining unit for determining that a far-off interfering wave exists out of the low frequency band
when a level of the second intermediate frequency signal is lower than a first threshold value and a level of the selected
intermediate frequency signal is lower than a second threshold value, determining that an out-of-channel-band interfering
wave exists out of the desired channel band when the level of the second intermediate frequency signal is equal to or higher
than the first threshold value and the level of the selected intermediate frequency signal is lower than the second threshold
value, and determining that an in-channel-band interfering wave exists in the desired channel band when the level of the second
intermediate frequency signal is equal to or higher than the first threshold value and the level of the selected intermediate
frequency signal is equal to or higher than the second threshold value; and

a controller that, when the interfering wave determining unit has determined that the far-off interfering wave exists, makes
an operation current of at least one circuit among the amplifying circuit, the mixing circuit, the low-pass filter circuit,
and the band-pass filter circuit lower than that in a case where it is determined that the out-of-channel-band interfering
wave or the in-channel-band interfering wave exists.

US Pat. No. 9,484,106

NONVOLATILE SEMICONDUCTOR MEMORY

LAPIS Semiconductor Co., ...

1. A nonvolatile semiconductor memory comprising:
a plurality of memory cells arranged in a matrix form;
word lines connected to said plurality of memory cells;
bit lines crossing said word lines and connected to said plurality of memory cells, respectively, such that a current is simultaneously
supplied from a power supply line via said bit lines to said memory cells to write data to said memory cells;

charge amount measurement sections for measuring amounts of charge stored in the corresponding ones of said memory cells,
respectively;

first current routes each being connected between said power supply line and a predetermined terminal being in a predetermined
potential;

second current routes each connecting said power supply line to the corresponding ones of said bit lines; and
a control circuit, connected to said charge amount measurement sections, for adjusting an amount of current supplied from
said power supply line to each of said first current routes and said second current routes depending on a measured value of
the amount of charge measured by said charge amount measurement section associated with the memory cell concerned;

wherein each of said first current routes includes a switch element connected to said power supply line, and a current amount
adjustment element connected between the switch element and said predetermined terminal.

US Pat. No. 9,454,165

SEMICONDUCTOR DEVICE AND CURRENT CONTROL METHOD THAT CONTROLS AMOUNT OF CURRENT USED FOR VOLTAGE GENERATION BASED ON CONNECTION STATE OF EXTERNAL CAPACITOR

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a current generation circuit that generates a current;
a voltage generation circuit that, using the current generated by the current generation circuit, generates and outputs a
predetermined voltage from a reference voltage, with an internal capacitor element that is connected to an output of the voltage
generation circuit, the internal capacitor element being provided within an integrated circuit on which the semiconductor
device itself is mounted;

a storage section that stores a flag indicating a connection state between the output of the voltage generation circuit and
an external capacitor element provided externally to the integrated circuit; and

a controller that, based on the flag, controls a current amount of the current used by the voltage generation circuit to generate
the predetermined voltage,

wherein the current generation circuit comprises
a first PMOS transistor, with a source connected to a power source voltage section,
a second PMOS transistor, with a source connected to the power source voltage section, and with a gate connected to a gate
of the first PMOS transistor;

a first NMOS transistor, with a drain connected to a drain and the gate of the first PMOS transistor, and with a gate connected
to a drain of the second PMOS transistor,

a second NMOS transistor, with a drain connected to the drain of the second PMOS transistor, with a source connected to a
location at a predetermined potential, and with a gate connected to the gate of the first NMOS transistor,

a first resistor element with one terminal connected to a source of the first NMOS transistor,
a second resistor element with one terminal connected to another terminal of the first resistor element, and with another
terminal connected to a location at the predetermined potential, and

a third NMOS transistor with a drain connected to the other terminal of the first resistor element, a source connected to
a location at the predetermined potential, and a gate connected to the controller,

wherein the controller places the third NMOS transistor in an OFF state in a case in which the flag indicates a connection
state of the output of the voltage generation circuit and the external capacitor element connected together, and places the
third NMOS transistor in an ON state in a case in which the flag indicates a connection state of the output of the voltage
generation circuit and the external capacitor element not connected together.

US Pat. No. 9,455,627

BOOST-TYPE SWITCHING REGULATOR AND SEMICONDUCTOR DEVICE FOR BOOST-TYPE SWITCHING REGULATOR

LAPIS SEMICONDUCTOR CO., ...

1. A boost-type switching regulator, comprising:
an inductor;
a rectifying element;
a capacitor;
a first switching element;
an output terminal configured to output an output voltage;
a detection voltage generating unit configured to generate a detection voltage according to a level of the output voltage
output from the output terminal;

an output voltage controlling unit configured to turn on and turn off the first switching element to increase the output voltage
when a level of the detection voltage is smaller than a specific value, said output voltage controlling unit being configured
to turn off the first switching element to decrease the output voltage when the level of the detection voltage is greater
than the specific value; and

a detection voltage level shifting unit configured to shift the level of the detection voltage so that the level of the detection
voltage during a voltage increasing period of the output voltage becomes greater than the level of the detection voltage during
a voltage decreasing period of the output voltage,

wherein said detection voltage generating unit includes a plurality of resistor elements connected to the output terminal
in series,

said detection voltage level shifting unit includes a plurality of flip flop circuits, a gate element, and a second switching
element connected to one of the resistor elements in parallel, and

said flip flop circuits are connected to the second switching element through the gate element in series so that only one
of the flip flop circuits is connected to the second switching element and others of the flip flop circuits are not connected
to any switching element.

US Pat. No. 9,406,279

SOURCE DRIVER IC CHIP

LAPIS Semiconductor Co., ...

1. A video display panel driving device comprising a first source driver IC chip and a second source driver IC chip, said
first source driver IC chip being configured to apply to a first source line group of a plurality of source lines of a display
panel a driving pulse having a gradation voltage corresponding to a brightness level of respective pixels represented by a
video signal, and said second source driver IC chip being configured to apply said driving pulse to a second source line group
of said source lines,
wherein each of said first and second source driver IC chips includes:
a first external terminal for receiving a reference gradation voltage;
a first gradation voltage generating part configured to generate a plurality of first gradation voltages having a first gamma
characteristic;

a second gradation voltage generating part configured to generate a plurality of second gradation voltages having a second
gamma characteristic; and

a reference gradation voltage generating part configured to generate a reference gradation voltage serving as a basis for
said first or second gamma characteristic to output the generated said reference gradation voltage through a second external
terminal,

wherein, said reference gradation voltage generating part of said first source driver IC chip generates a reference gradation
voltage serving as a basis for said first gamma characteristic, outputs said generated reference gradation voltage through
said second external terminal, and supplies said reference gradation voltage to said first external terminal of said second
source driver IC chip through a first reference gradation voltage supply line,

wherein said reference gradation voltage generating part of said second source driver IC chip generates a reference gradation
voltage serving as a basis for said second gamma characteristic, outputs said generated reference gradation voltage through
said second external terminal, and supplies said reference gradation voltage to said first external terminal of said first
source driver IC chip through a second reference gradation voltage supply line, and

wherein said first and second source driver IC chips generate said first and second gradation voltages based on said reference
gradation voltage outputted from said second external terminal and said reference gradation voltage received from said first
external terminal.

US Pat. No. 9,337,294

SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a substrate;
a first semiconductor region formed at a front surface of the substrate, the first semiconductor region including an active
element that regulates current flowing in a thickness direction of the substrate;

an implantation region in which phosphorus is implanted such that a peak portion of density per unit volume is disposed at
a predetermined distance from a rear surface of the substrate; and

a second semiconductor region between the implantation region and the rear surface of the substrate, in which impurities of
a predetermined conduction type are implanted, that is formed with a predetermined thickness, and through which the current
flows,

wherein a density per unit volume of phosphorus in the second semiconductor region is at most 1/10 of a density per unit volume
of the impurities of the predetermined conduction type in the second semiconductor region.

US Pat. No. 9,092,373

MICROCOMPUTER WITH BOOTABLE FLASH MEMORY

LAPIS Semiconductor Co., ...

1. A microcomputer comprising:
a central processing unit to perform processing and control in accordance with programs;
a memory to store data containing the programs therein; and
a read controller to read the data from the memory in accordance with the control from the central processing unit,
wherein the memory is partitioned by sectors each having a memory area in which a continuous address space is constant,
said memory providing a memory content of an address as read data when the address is designated, and providing security information
indicative of whether or not a memory content of a sector with the address is being protected, and

the read controller to control the output of the read data, wherein
when the memory is undesignated as storing a startup program and the read data outputted from the memory is protected by the
security information, a predetermined data, that is different from said read data stored in the memory undesignated as storing
a startup program, is outputted in place of said read data;

wherein the security information is a first value, if the read data outputted from the memory is protected, and a second value,
if the read data outputted from the memory is not protected, and

wherein the read controller includes:
a switch that outputs the first value when the memory us undesignated as storing a startup program and the second value when
the memory is designated as storing a startup program;

an AND gate having two input terminals that outputs a logical AND of inputted signals, the output signal from the switch being
inputted to one of the input terminals and the security information outputted from the memory is being inputted to the other
of the input terminals; and

a selector, to which the read data is outputted from the memory and an output signal from the AND gate are inputted, that
selects a predetermined data as an output data when the output signal from the AND gate is the second value, and the read
data outputted from the memory as the output data when the output signal from the AND gate is the first value.

US Pat. No. 9,071,216

SIGNAL PROCESSING DEVICE AND SIGNAL PROCESSING METHOD

LAPIS Semiconductor Co., ...

1. A signal processing device comprising:
a first amplifier that amplifies a level of an analog audio signal input from an external source with a first gain whose value
is variable;

a converter that converts the analog audio signal amplified by the first amplifier into a digital audio signal;
a signal processor that performs signal processing for controlling tone of the digital audio signal, the signal processor
including means for attenuating a low-frequency region of the digital audio signal;

a controller that detects a level of the digital audio signal before the signal processing and controls the value of the first
gain in accordance with the detected level of the digital audio signal before the signal processing; and

a second amplifier that detects a level of the digital audio signal after the signal processing, determines a second gain
in accordance with the detected level of the digital audio signal after the signal processing and the first gain, and amplifies
the digital audio signal after the signal processing with the second gain,

wherein the first gain applied to the first amplifier is set to be small if the level of the digital audio signal in the low-frequency
region is large and the second gain determined by the second amplifier is set to be large,

wherein the controller performs a first decay operation for increasing the first gain in accordance with a decrease in the
detected level of the digital audio signal before the signal processing after the first gain is reduced, and

wherein the second amplifier performs a second decay operation for increasing the second gain in accordance with a decrease
in the detected level of the digital audio signal after the signal processing after the second gain is reduced and stops performing
the second decay operation while the controller performs the first decay operation.

US Pat. No. 10,055,281

SEMICONDUCTOR COMMUNICATION DEVICE, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor communication device configured to execute an executable command and not to execute a non-executable command, said semiconductor communication device being configured to receive a data signal, in which a CRC (Cyclic Redundancy Check) data piece is arranged after a series of a plurality of data pieces, said data pieces representing a command, said CRC data piece representing a value calculated with a cyclic redundancy check calculation based on the data pieces, said semiconductor communication device being configured to perform transmission according to the executable command, said semiconductor communication device comprising:a CRC calculation portion configured to retrieve each of the data pieces and the CRC data piece as a retrieved data piece from the data signal, said CRC calculation portion being configured to perform the cyclic redundancy check calculation to obtain a CRC calculation value according to the retrieved data piece each time when the CRC calculation portion retrieves the retrieved data piece;
a comparing portion configured to generate an end detection signal indicating that the comparing portion detects a data end portion of the data signal when the CRC calculation value matches a value indicated with a subsequently retrieved data piece subsequently retrieved after the retrieved data piece is retrieved before the CRC calculation portion retrieves the data end portion; and
a communication responding portion configured to determine whether the command represented with the retrieved data piece is the non-executable command, said communication responding portion being configured to transmit a command error signal when the communication responding portion determines that the command is the non-executable command.

US Pat. No. 9,653,304

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A method of manufacturing a semiconductor device comprising:
forming a first gate member on a semiconductor substrate through a gate insulating film;
forming a spacer on the first gate member;
flattening a surface of the spacer;
forming a first gate by partially etching the first gate member using the spacer as a mask;
forming a second gate member so as to cover the first gate and the spacer having the flattened surface;
forming a first insulating film on a surface of the second gate member, after the second gate member is formed; and
forming a second gate by causing the second gate member to retreat while removing the first insulating film by etching.

US Pat. No. 9,602,003

VOLTAGE REGULATOR, SEMICONDUCTOR DEVICE, AND VOLTAGE GENERATION METHOD FOR VOLTAGE REGULATOR

LAPIS SEMICONDUCTOR CO., ...

1. A voltage regulator configured to generate an internal source voltage on the basis of a source voltage in an operational
mode is selected from either an active mode or a standby mode, said voltage regulator comprising:
a drive voltage generating part configured to generate a drive voltage and then apply said drive voltage to a drive line;
an output transistor configured to output a voltage corresponding to a voltage value of said drive line as said internal source
voltage; and

a compulsory drive circuit including a capacitor element configured to receive said source voltage at one end, a first switching
element configured to receive a ground voltage and apply said ground voltage to the other end of said capacitor element by
being set in an ON state over a period in which the selected operational mode is said standby mode, and a second switching
element that connects said other end of said capacitor element to said drive line only for a predetermined period in an ON
state when said operational mode transitions from said standby mode to said active mode.

US Pat. No. 9,595,965

LIQUID CRYSTAL DRIVE CIRCUIT AND LIQUID CRYSTAL DRIVE CIRCUIT CONTROL METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a first power source section that includes a first power source output terminal and a second power source output terminal
that output voltages at mutually different voltage levels, the first power source section changing the respective voltage
levels output from the first power source output terminal and the second power source output terminal according to switching
of a signal level of a first signal;

a first output section that includes a first output stage switch that is provided between the first power source output terminal
and a first voltage output terminal, and a second output stage switch that is provided between the second power source output
terminal and the first voltage output terminal; and

a controller that performs ON/OFF control of the first output stage switch and the second output stage switch such that both
the first output stage switch and the second output stage switch are in an OFF state over a predetermined period encompassing
a point in time when a signal level of the first signal switches.

US Pat. No. 9,589,501

DISPLAY DRIVE CIRCUIT INCLUDING AN OUTPUT TERMINAL

LAPIS SEMICONDUCTOR CO., ...

1. A display system, comprising:
a display panel for displaying an image, the display panel including a glass substrate;
a plurality of lead lines formed on the glass substrate; and
a display drive circuit for controlling the displaying of the image by the display panel, the display drive circuit being
formed as a chip and connected to the lead lines, the display drive circuit comprising:

a rectangularly-shaped substrate having a main surface and having a longer side that is longer than another side of the rectangularly-shaped
substrate;

a power supply line formed on the main surface of the rectangularly-shaped substrate, the power supply line being disposed
along the longer side of the rectangularly-shaped substrate;

a plurality of output terminals formed on the main surface of the rectangularly-shaped substrate and connected to the power
supply line between an end portion of the power supply line and a center portion of the power supply line;

first ground terminals formed at the end portion of the power supply line; and
second ground terminals formed at the center portion of the power supply line.

US Pat. No. 9,417,705

MOTION DETECTION DEVICE, ELECTRONIC DEVICE, MOTION DETECTION METHOD, AND PROGRAM STORAGE MEDIUM

LAPIS Semiconductor Co., ...

1. A controller comprising:
an input unit that receives sets of acceleration component data for each axis of a three-dimensional rectangular coordinate
system, the sets of acceleration component data expressing an acting acceleration;

a separating unit that separates the sets of acceleration component data into stationary components obtained by subjecting
the sets of acceleration component data to low-pass filter processing and motion components obtained by subtracting the stationary
components from the sets of acceleration component data;

a gravity axis determination unit that determines an axis whose separated stationary component is the largest to be a gravity
axis; and

a motion detection unit which, in a case in which an axis corresponding to a largest motion component showing a largest value
of the separated motion components is an axis other than the determined gravity axis, detects a motion axis of the acting
acceleration on the basis of the largest motion component.

US Pat. No. 10,056,424

SEMICONDUCTOR DEVICE, ELECTRICAL DEVICE SYSTEM, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device, comprising:an SOI (Silicon On Insulation) substrate formed of a first semiconductor layer having a first conductive type, an embedded oxide film, and a circuit layer; and
an interlayer insulation film formed on the SOI substrate,
wherein said SOI substrate has a circuit element region and an outer circumferential region surrounding the circuit element region in a plane view,
said circuit layer includes a plurality of single pixel circuits arranged in an array pattern,
each of said single pixel circuits includes a circuit element, a diode, and a conductive portion,
said circuit element is formed on the circuit layer,
said diode includes a first region formed on the first semiconductor layer and a first conductive member formed on the interlayer insulation film and electrically connected to the first region,
said first region has a second conductive type different from the first conductive type,
said conductive portion is electrically isolated from other elements,
said conductive portion includes a second region formed on the first semiconductor layer and an electrode formed on the interlayer insulation film and electrically connected to the second region,
said second region is arranged at a center of each of the single pixel in the plane view, and
said second region has the first conductive type.

US Pat. No. 9,542,902

DISPLAY DEVICE DRIVER

LAPIS SEMICONDUCTOR CO., ...

1. A display device driver for driving a display device in response to a video signal, said display device including a screen
containing a plurality of scanning lines and a plurality of data lines that respectively intersect the scanning lines so as
to form pixels at the intersection point therebetween, said display device driver comprising:
a scanning driver that applies scanning pulses in sequence to respective ones of said plurality of scanning lines; and
a data driver that applies pixel drive voltages to the respective ones of said data lines, said pixel drive voltages each
varying in correspondence to luminance levels represented by said video signal at the respective pixels, wherein

said data driver applies said pixel drive voltages at timings each corresponding to a scan pulse path length of the scanning
line that intersects said one of data lines, said scan pulse path length being equal to a length of a distance between an
apply point of a scanning pulse and an intersection point where a scanning line intersects said data line.

US Pat. No. 9,537,505

DATA PROCESSING APPARATUS AND METHOD OF PROCESSING DATA

LAPIS SEMICONDUCTOR CO., ...

1. A data processing apparatus, comprising:
an inputting circuit that receives a serial data formed of a sequence of serial data blocks of N bits (N is a natural number
greater than 2) and including a clock bit;

a first retrieving circuit that retrieves and obtains a data of K bits (K is a natural number greater than N, K>N) from each
of the serial data blocks as a first retrieved data;

a second retrieving circuit that retrieves and obtains a data of L bits (L is a difference between N and K, L=K?N) from each
of the serial data blocks as a second retrieved data;

a clock determining circuit that determines whether the clock bit is included in one of the first retrieved data and the second
retrieved data;

a first serial parallel converting circuit that performs parallel conversion to one of the first retrieved data and the second
retrieved data that includes the clock bit according to a determination result of the clock determining portion so that the
first serial parallel converting circuit obtains a first parallel data;

a second serial parallel converting circuit that performs parallel conversion to the other one of the first retrieved data
and the second retrieved data that does not include the clock bit according to the determination result of the clock determining
portion so that the second serial parallel converting circuit obtains a second parallel data; and

a combining circuit that combines the first parallel data and the second parallel data to output a parallel data of N bits.

US Pat. No. 9,973,192

LIQUID CRYSTAL DRIVE CIRCUIT AND LIQUID CRYSTAL DRIVE CIRCUIT CONTROL METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:an input terminal configured to receive as an input an inversion signal that transitions between a low level and a high level;
a timing regulation circuit configured to output a first output signal and a second output signal that transition between the low level and the high level, the timing regulation circuit configured to
shift the second output signal from the high level to the low level after shifting the first output signal from the high level to the low level, in a case in which the inversion signal transitions from the low level to the high level, and
shift the first output signal from the low level to the high level after having shifted the second output signal from the low level to the high level, in a case in which the inversion signal transitions from the high level to the low level; and
a voltage output section configured to receive the first output signal and the second output signal, and to output a first voltage and a second voltage that is lower than the first voltage.

US Pat. No. 9,870,807

REFERENCE CURRENT GENERATING CIRCUIT AND MEMORY DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A reference current generating circuit, comprising:
a positive temperature coefficient current source configured to generate a plurality of first currents, a value of each of
which increases with an increase of an ambient temperature thereof;

a negative temperature coefficient current source configured to generate a plurality of second currents, a value of each of
which decreases with the increase of the ambient temperature thereof;

a first current adjustment circuit configured to generate a positive temperature characteristic current by combining the first
currents based on a first adjustment setting signal;

a second current adjustment circuit configured to generate a negative temperature characteristic current by combining the
second currents based on a second adjustment setting signal; and

a current amplifier configured to amplify a combined current of the positive temperature characteristic current and the negative
temperature characteristic current, to thereby generate a reference current.

US Pat. No. 9,660,018

SEMICONDUCTOR DEVICE FABRICATING METHOD AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A method of fabricating a semiconductor device, the method comprising:
forming a lower electrode layer on a substrate;
forming a first insulating film on the lower electrode layer and forming an upper electrode on the first insulating film;
removing a part of the first insulating film at a region other than the upper electrode;
forming a second insulating film on the lower electrode, the first insulating film and the upper electrode, after said removing
the part of the first insulating film;

forming an opening in the second insulating film and patterning the lower electrode layer to form a lower electrode;
forming a third insulating film on the second insulating film and in the opening in the second insulating film;
removing a first part of the third insulating film by patterning to form a first open portion that exposes the upper electrode,
removing a second part of the third insulating film and a part of the second insulating film by patterning to form a second
open portion that exposes the lower electrode, and

forming in the first open portion a first conductive portion that is electrically connected to the upper electrode and forming
in the second open portion a second conductive portion that is electrically connected to the lower electrode.

US Pat. No. 9,627,477

TRENCH ISOLATION STRUCTURE HAVING ISOLATING TRENCH ELEMENTS

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising a semiconductor substrate, the semiconductor substrate comprising in one main surface
of the semiconductor substrate:
an element isolating trench; and
a semiconductor element that is formed in an element formation region,
wherein the element isolating trench has
(i) a first side that connects a first point and a second point,
(ii) a second side that connects the first point and a third point, and that forms an angle “90°??” (0° side,

(iii) a third side that faces the first side across the element isolating trench, and that runs parallel to the first side,
(iv) a fourth side that faces the third side across the element formation region, and that runs parallel to the third side,
and

(v) a fifth side that is disposed on a first line that extends at a right angle with respect to the first side, and that connects
a fourth point that is an end point of the third side and a fifth point that is an end point of the fourth side.

US Pat. No. 9,606,007

SEMICONDUCTOR DEVICE AND MEASUREMENT METHOD

LAPIS Semiconductor Co., ...

1. A semiconductor device comprising:
a first counter that performs a count operation based on a signal of a first frequency;
a second counter that performs a count operation based on a signal of a second frequency; and
a control section that determines a higher frequency out of the first frequency or the second frequency based on a count value
of the first counter and a count value of the second counter, measures the other frequency and computes a frequency ratio
by using the higher frequency as a reference, and acquires a measurement value by referring to a specific table expressing
correspondence relationships between the frequency ratio and the measurement values,

wherein the specific table includes a first region stored with ratios of the second frequency with respect to the first frequency,
and a second region stored with ratios of the first frequency with respect to the second frequency, and

frequency ratios are stored in the first region for cases in which the first frequency is lower than a value of a sum of the
second frequency plus a specific permissible value, and frequency ratios are stored in the second region for cases in which
the first frequency is greater than a value of the second frequency from which a specific permissible value has been subtracted.

US Pat. No. 9,602,124

A/D CONVERSION DEVICE HAVING LEVEL SHIFTER CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. An A/D conversion device comprising:
a level shifter circuit configured to level-shift an analog voltage of an input voltage signal to generate a conversion signal;
an A/D converter configured to A/D-convert a voltage of said conversion signal supplied from said level shifter circuit into
a digital value, wherein said level shifter circuit subtracts an instantaneous voltage value of said input voltage signal
from a reference voltage so as to output a signal value as said conversion signal; and

a reference voltage setting part configured so as to divide a voltage range in which a voltage value of the input voltage
range varies into plural voltage regions each having a width which is equal to or less than an input range of said A/D converter,
and to select, from said plural voltage regions, an instantaneous voltage region including said instantaneous voltage value
of said input voltage signal, and to set, as said reference voltage, a maximal voltage value in said instantaneous voltage
region selected.

US Pat. No. 9,530,481

FERROELECTRIC RANDOM ACCESS MEMORY WITH PLATE LINE DRIVE CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. A ferroelectric random access memory comprising:
a memory cell matrix constituted by a plurality of 1T1C type memory cells of j rows and k columns (j is an integer of 2 or
more and k is an integer of 1 or more), and having j bit lines, k word lines, and k plate lines, said k word lines and said
k plate lines being paired with each other, and each of said plurality of 1T1C type memory cells being connected to one of
said j bit lines and one pair of said k word lines and said k plate lines;

a word line drive circuit which selects either one word line of said k word lines in accordance with a selection signal;
a plate line drive circuit which selects one plate line of said k plate lines paired with the selected one word line, and
selectively applies one of a first potential and a second potential having a higher potential level than the first potential
to said one plate line during a data writing time period; and

an equalizing circuit which performs an equalizing process in which the first potential is applied to each of said j bit lines,
wherein

said plate line drive circuit applies, after said data writing time period, a third potential having a potential level between
the first and second potentials to said one plate line, during a predetermined time period including a starting time of said
equalizing process.

US Pat. No. 10,121,721

HEAT DISSIPATION BUMP ELECTRODE FOR CHIP ON FILM

LAPIS Semiconductor Co., ...

1. A semiconductor package, comprising:a semiconductor chip carrying a bump electrode formed thereon and including a semiconductor substrate and at least one electrode layer;
a wiring substrate carrying a lead line connected to said bump electrode, the lead line being formed on a facing surface of the wiring substrate facing the semiconductor chip;
at least one heat dissipation bump electrode for dissipating heat disposed on the semiconductor chip, a surface of said semiconductor substrate and said electrode layer being connected to each other through a metallic material at a location directly below said heat dissipation bump electrode within the surface of said semiconductor substrate; and
at least one heat dissipation pattern formed on said facing surface of the wiring substrate and being electrically connected to said heat dissipation bump electrode, to dissipate heat from the semiconductor chip, wherein
the heat dissipation bump electrode is formed over or around a high temperature area on the semiconductor chip, the high temperature area having a temperature higher than a predetermined threshold value during operation of the semiconductor chip.

US Pat. No. 10,033,969

SEMICONDUCTOR DEVICE, VIDEO DISPLAY SYSTEM, AND METHOD OF PROCESSING SIGNAL

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device, comprising:a first input unit configured to receive a first signal;
a first processing unit configured to perform a frequency dispersion processing on the first signal;
a first output unit configured to output the first signal or the first signal on which the first processing unit performs the frequency dispersion processing;
a second input unit configured to receive a second signal generated through performing a predetermined image processing with an image processing unit on the first signal output from the first output unit;
a second processing unit configured to perform the frequency dispersion processing on the second signal;
an enable signal input unit configured to receive an enable signal; and
a second output unit configured to output one of the first signal and the second signal on which the frequency dispersion process is performed as an output signal according to the enable signal.

US Pat. No. 9,659,887

SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
at least one pad group including a plurality of pads provided on a semiconductor substrate and arranged in a row to form a
pad row as a whole, wherein

said pad group includes: a plurality of first pads provided with a first via-connection part electrically connected therewith;
and a plurality of second pads provided with a second via-connection part electrically connected therewith;

said plurality of first pads are positioned so that each center point of said plurality of first pads is arranged along a
first center line,

said plurality of second pads are positioned so that each center point of said plurality of second pads is arranged along
a second center line,

said first via-connection part extends in a first direction perpendicular to the first center line,
said second via-connection part extends in a second direction opposite to the first direction,
the first and second center lines are positioned in parallel with each other and apart from each other, and
said first and second via-connection parts are connected to a circuit block provided in said semiconductor substrate.

US Pat. No. 9,601,993

BOOSTING CIRCUIT OF CHARGE PUMP TYPE AND BOOSTING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device for boosting a voltage, comprising:
a semiconductor chip which is supplied with an input voltage;
a first capacitor which is connected to the semiconductor chip and is supplied with a potential difference corresponding to
the input voltage;

a second capacitor which is connected to the semiconductor chip, is supplied with a first voltage corresponding to the potential
difference in a double boosting operation, and is supplied with a second voltage corresponding to twice the potential difference
in a triple boosting operation; and

an output capacitor which is connected to the semiconductor chip, is supplied with the second voltage from the first capacitor
and the second capacitor in the double boosting operation, and is supplied with a third voltage corresponding to three times
the potential difference from the first capacitor and the second capacitor in the triple boosting operation;

wherein the output capacitor is configured to be supplied with the first voltage and the second voltage in advance of being
supplied with the second voltage and the third voltage, in the double boosting operation and the triple boosting operation,
respectively.

US Pat. No. 9,582,019

SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a resistance section that includes a first terminal and a second terminal disposed in contact with an outer periphery, and
a serial resistance section in which a plurality of resistance elements are connected in series, wherein one end of the serial
resistance section is connected to the first terminal, and another end of the serial resistance section is connected to the
second terminal; and

a current adjustment section that includes a current source that supplies current to the serial resistance section, and disposed
adjacent to the resistance section such that a distance between the first terminal and the current adjustment section along
the outer periphery of the resistance section and a distance between the second terminal and the current adjustment section
along the outer periphery of the resistance section are equal.

US Pat. No. 9,553,603

R-2R LADDER RESISTOR CIRCUIT, LADDER RESISTOR TYPE D/A CONVERSION CIRCUIT, AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. An R-2R ladder resistor circuit, comprising:
a plurality of first resistance elements, one end of each being connected to an input terminal;
a plurality of second resistance elements, one end of each being connected to a reference potential;
a plurality of third resistance elements, one end of each being connected to an output terminal;
a plurality of switching connection sections that are each in correspondence relationships with the plurality of first resistance
elements, the plurality of second resistance elements, and the plurality of third resistance elements, and that connect the
input terminal and the output terminal according to a bit signal, wherein, according to the bit signal, each switching connection
section switchably connects another end of a third resistance element to another end of a first resistance element or to another
end of a second resistance element, among the first resistance element, the second resistance element, and the third resistance
element corresponding thereto,

wherein the switching connection sections each comprise a pair of CMOS switches that switch, according to the bit signal,
between a first connection state in which the another end of the first resistance element and the another end of the third
resistance element are connected without connecting the another end of the second resistance element and the another end of
the third resistance element, and a second connection state in which the another end of the second resistance element and
the another end of the third resistance element are connected without connecting the another end of the first resistance element
and the another end of the third resistance element, and

wherein one CMOS switch of the pair of CMOS switches is inserted between the first resistance element and the third resistance
element, another CMOS switch of the pair of CMOS switches is inserted between the second resistance element and the third
resistance element, and the one CMOS switch and the another CMOS switch perform opposite switching operations according to
the bit signal; and

a first CMOS switch, inserted between the one CMOS switch and the first resistance element, that includes a source and a drain
that are short-circuited such that the one CMOS switch and the first resistance element are connected, and that performs a
switching operation opposite to the one CMOS switch in the first connection state.

US Pat. No. 9,520,775

BOOSTING SYSTEM, DIAGNOSING METHOD, AND COMPUTER READABLE MEDIUM STORING DIAGNOSING PROGRAM FOR DIAGNOSING THE BOOSTING FUNCTIONS OF A BOOSTING SECTION

LAPIS Semiconductor Co., ...

1. A boosting system comprising:
a boosting section that generates a boosted voltage obtained by boosting a first voltage in accordance with a second voltage
outputted from a constant voltage circuit; and

a comparison circuit, to which the boosted voltage, the first voltage, the second voltage and a ground potential are input,
that compares a first difference value with a second difference value and that outputs results of comparison, wherein the
first difference value is obtained from a difference between the boosted voltage and the first voltage, the second difference
value is obtained from a difference between the second voltage and the ground potential,

wherein the comparison circuit comprises:
a single inverting amplifier;
a first capacitor and a second capacitor that are connected in parallel, wherein an input of the single inverting amplifier
is connected to the first capacitor and the second capacitor;

a first switching element that connects the first capacitor and the boosting section such that the first voltage is inputted;
a second switching element that connects the first capacitor and the boosting section such that the boosted voltage is inputted;
a third switching element that connects the second capacitor and the boosting section such that the second voltage is inputted;
a fourth switching element that connects the second capacitor to ground such that the ground potential is inputted; and
a fifth switching element that short-circuits the input and an output of the single inverting amplifier.

US Pat. No. 9,293,219

NON-VOLATILE MEMORY, SEMICONDUCTOR DEVICE AND READING METHOD

LAPIS Semiconductor Co., ...

1. A non-volatile memory circuit comprising:
a plurality of storage element sections each including a zener zap device and a switch section that connects an anode of the
zener zap device to an output terminal only during data reading; and

wherein cathodes of respective zener zap devices of the plurality of storage element sections are commonly connected so as
to be connected to a power supply employed in the writing or to a power supply employed in the reading,

wherein the output terminals of the plurality of storage element sections are commonly connected to an input terminal of a
detector, an anode of each of the storage element sections being connected to a ground voltage only during data writing,

wherein the switch section is switched ON only during data reading so as to connect the anode of the storage element section
through the output terminal to the input terminal of the detector; and

wherein the detector comprises a negative feedback circuit that restricts a voltage on the input terminal so as to lie within
a predetermined amplitude.

US Pat. No. 10,141,924

SEMICONDUCTOR CIRCUIT, VOLTAGE DETECTION CIRCUIT, AND VOLTAGE DETERMINATION CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor circuit comprising:a PMOS transistor that includes a first source connected to a power supply, a first drain, and a first gate to which a fixed potential is supplied;
an output circuit that outputs a first output signal, which is a reset signal or a power-on signal, and that outputs a second output signal according to a potential of the first drain;
a first constant current source connected to the first drain; and
a control circuit including an NMOS transistor that includes a second source to which a fixed potential is supplied, a second drain connected to the first drain, and a second gate to which the second output signal from the output circuit is applied,
wherein, according to the second output signal which is output from the output circuit, the control circuit is configured to control the NMOS transistor to increase a reference current flowing in the PMOS transistor such that a threshold voltage of the PMOS transistor increases in a case in which the power supply is in a rising state, and to control the NMOS transistor to decrease the reference current flowing in the PMOS transistor such that the threshold voltage of the PMOS transistor decreases in a case in which the power supply is in a falling state.

US Pat. No. 10,053,058

SEMICONDUCTOR DEVICE, WIPER SYSTEM, AND MOVING BODY CONTROL METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A moving body control device configured to control a moving body that moves along a specific path on a surface of a specific object, the moving body control device comprising:a storage section; and
a microcomputer connected to the storage section, the microcomputer being configured to
detect an abnormality occurring in the moving body moving along the specific path;
detect a position of the moving body as an abnormality occurrence position, in a case in which an abnormality has been detected;
store, in the storage section, abnormality occurrence position information expressing the abnormality occurrence position; and
control an adjusting section to adjust a pressing force at which the moving body presses against the surface of the specific object, based on the abnormality occurrence position information,
wherein the adjusting section adjusts the pressing force of the moving body at the abnormality occurrence position by increasing or decreasing the pressing force,
wherein the microcomputer is further configured to
in a case in which the pressing force has been increased,
determine whether the abnormality occurring in the moving body has increased or decreased compared to the abnormality before the pressing force was increased; and
control the adjusting section to decrease the pressing force in a case in which the microcomputer determines that the abnormality has increased, and to increase the pressing force in a case in which the microcomputer determines that the abnormality has decreased, or
in a case in which the pressing force has been decreased,
determine whether the abnormality occurring in the moving body has increased or decreased compared to the abnormality before the pressing force was decreased; and
control the adjusting section to increase the pressing force in a case in which the microcomputer determines that the abnormality has increased, and to decrease the pressing force in a case in which the microcomputer determines that the abnormality has decreased, and
wherein the specific object is a vehicle window, the moving body is a wiper, and the abnormality is chattering.

US Pat. No. 9,853,081

SEMICONDUCTOR DEVICE, ELECTRICAL DEVICE SYSTEM, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device, comprising:
a first semiconductor layer;
an insulation member layer formed on the first semiconductor layer;
a transistor disposed in an upper portion of the insulation member layer;
a first interlayer insulation film covering the transistor;
a layered member including a wiring layer formed on the first interlayer insulation film and a second interlayer insulation
film; and

a first penetrating electrode penetrating through the insulation member layer, the first interlayer insulation film, and the
layered member,

wherein said first penetrating electrode is electrically connected only to the first semiconductor layer,
said first penetrating electrode includes a first wiring formed in the wiring layer and a second wiring formed on the second
interlayer insulation film, and

said first wiring has a width smaller than that of the second wiring.

US Pat. No. 9,804,630

ADJUSTABLE REFERENCE CURRENT GENERATOR, SEMICONDUCTOR DEVICE AND ADJUSTABLE REFERENCE CURRENT GENERATING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. An adjustable reference current supplier for supplying a reference current with an instantaneous value varying in accordance
with an adjustment signal representing a target current comprising:
a reference current generation part for generating a reference current having a current value corresponding to said adjustment
signal supplied thereto,

a detection current generation part for generating a detection current having a current value which is m (where the m denotes
1 or more) times as large as a current value of said reference current,

a detection voltage generation part with a first resistor for generating a detection voltage having a voltage value corresponding
to a voltage drop across said first resistor in response to said detection current,

a monitor voltage generation part including a second resistor having a resistance value which is 1/n (where the n denotes
greater than 1) times as large as a resistance value of said first resistor and a terminal to which an external monitor current
is suppliable, and for generating a monitor voltage having a voltage value which value corresponds to a voltage drop across
said second resistor in response to said monitor current supplied thereto.

US Pat. No. 9,805,669

DISPLAY PANEL DRIVE DEVICE AND DISPLAY PANEL DRIVE METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A display panel drive device for receiving input video data signals each including a series of video data pieces respectively
representing brightness levels of pixels aligned with each other along a single horizontal scan line and for applying gradation
voltages respectively corresponding to the video data pieces to a display panel, each of the video data pieces belonging to
either one of first and second video data groups which are different from each other, said display panel drive device comprising:
a D/A converter configured to convert each of the video data pieces belonging to said first video data group into a first
analog gradation voltage; and

a gradation voltage interpolation circuit configured to obtain a second analog gradation voltage each corresponding to the
video data pieces belonging to said second video data group by interpolation based on the first analog gradation voltages
respectively corresponding to at least two of the pixels.

US Pat. No. 9,787,250

SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device, comprising:
an electronic component that comprises an oscillator and comprises a plurality of terminals on one face;
a semiconductor chip that is electrically connected to the electronic component and comprises a plurality of terminals on
one face;

a mounting base to which the electronic component and the semiconductor chip are each directly mounted on one face of the
mounting base, such that the plurality of terminals of the electronic component and the plurality of terminals of the semiconductor
chip face in a same direction;

first bonding wires that connect at least two of the plurality of terminals of the semiconductor chip to mounting base terminals
of the mounting base;

second bonding wires that directly connect at least two of the plurality of terminals of the electronic component to the plurality
of terminals of the semiconductor chip, and that have an apex height that is smaller than that of the first bonding wires;
and

a sealing member that completely seals at least the electronic component inside the sealing member,
wherein the first bonding wires stride over the second bonding wire.

US Pat. No. 9,767,760

DRIVING DEVICE FOR DISPLAY DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A driving device for driving a display device, comprising:
a source driver that applies pixel drive voltages respectively denoting luminance levels of pixels to a plurality of source
lines of the display device via external lines respectively, wherein said source driver includes:

a plurality of amplifiers provided correspondingly to the plurality of source lines respectively and configured to generate
said pixel drive voltages, each of the plurality of amplifiers having a control terminal and an output terminal with one of
said external lines connected thereto, said each amplifier being configured to output one of the generated pixel drive voltages
to the one external line via the output terminal and to operate with a transition speed based on a voltage supplied thereto
via the control terminal;

a bias voltage supply line having its opposed ends that are respectively a first end and a second end; and
a bias voltage generating part that generates a bias voltage and supplies said bias voltage across said opposed ends so that
said first end has a voltage higher than a voltage than at said second end,

wherein for each of said amplifiers, said bias voltage supply line is connected to the control terminal of said each amplifier
so that the longer a length of the external line connected to the output terminal of said each amplifier is, the shorter a
length of said bias voltage supply line between the control terminal of said each amplifier and said first end of the bias
voltage supply line is, and

wherein an external line at one side of the display is the shortest, and each of said external lines are longer in length
as they approach the other side of the display.

US Pat. No. 9,767,761

DRIVER CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. A driver circuit driving a display device comprising:
a gradation voltage generating circuit for generating m gradation voltages (m is an integer larger than or equal to 2) indicative
of m stages of gradation levels;

n decoder circuits (n is an integer larger than or equal to 2) each for selecting and outputting, out of the m gradation voltages,
n drive voltages corresponding to n data pieces on the basis of n input gradation signals;

m gradation voltage wirings each for transferring the m gradation voltages to said n decoder circuits, respectively; and
a charge supplementing circuit for supplementing, if a voltage drop occurs in any one or more of the m gradation voltage wirings,
said any one or more of the m gradation voltage wirings with an amount of electric charge.

US Pat. No. 9,759,781

BATTERY MONITORING SYSTEM AND BATTERY MONITORING CHIP

LAPIS SEMICONDUCTOR CO., ...

1. A battery monitoring system for a battery containing a plurality of battery cells connected together in series, wherein
mutually different portions from the plurality of battery cells form a plurality of battery cell groups, the battery monitoring
system comprising:
a plurality of battery monitoring chips that each comprises
a battery monitoring function section that is provided so as to correspond to one of the battery cell groups and that monitors
a state of each of battery cell included in the corresponding battery cell group, and

a voltage generation section that generates and supplies a drive voltage to a configuration circuit of the battery monitoring
function section based on power supplied from the battery,

wherein the plurality of battery monitoring chips are connected together in series with a communication path for performing
communication between each other, with an input end of the voltage generation section electrically connected to an output
end of a voltage generation section of another battery monitoring chip from among the plurality of battery monitoring chips;
and

a driven section that is connected to one battery monitoring chip from among the plurality of battery monitoring chips, and
that is driven by a drive voltage generated by the voltage generation section of the one battery monitoring chip accompanying
power consumption by each of the plurality of battery cells,

wherein the voltage generation section of the one battery monitoring chip is driven by a drive voltage generated by the voltage
generation section of a battery monitoring chip in a higher position corresponding to a battery cell group in a higher position
than the battery cell group corresponding to the one battery monitoring chip.

US Pat. No. 9,754,876

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a fuse element; and
a fuse window that is formed above a region including the fuse element, that includes a pair of first sidewalls extending
in a first direction running along a direction that current flows in the fuse element and a pair of second sidewalls extending
in a second direction intersecting the first direction, and that is formed with a projection projecting out from a sidewall
side toward the inside at an inner wall of at least one out of the first sidewalls or the second sidewalls, the projection
having a sidewall side width that is narrower than a projecting side width.

US Pat. No. 9,722,554

DIFFERENTIAL AMPLIFIER AND DISPLAY DRIVER INCLUDING THE SAME

LAPIS SEMICONDUCTOR CO., ...

1. A differential amplifier for sending out an output voltage obtained by amplifying an input voltage via an output line,
comprising:
first and second differential units for respectively generating a voltage corresponding to a difference value between a voltage
supplied to a first input terminal and a voltage supplied to a second input terminal on each of a first line;

a drive line connected with both of the first line of the first differential unit and the first line of the second differential
unit;

an output transistor for generating the output voltage on the basis of a voltage on the drive line;
a first connection switch for taking either one of a normal connection state in which the input voltage is supplied to the
first input terminal of the first differential unit and the output voltage is supplied to the second input terminal of the
first differential unit and an offset detection connection state in which the input voltage is supplied to the first and second
input terminals of the first differential unit;

a second connection switch for taking any one of a normal connection state in which the input voltage is supplied to the first
input terminal of the second differential unit and the output voltage is supplied to the second input terminal of the second
differential unit, an offset detection connection state in which the input voltage is supplied to the first and second input
terminals of the second differential unit, and a chopping connection state in which the input voltage is supplied to the second
input terminal of the second differential unit and the output voltage is supplied to the first input terminal of the second
differential unit; and

a control unit for performing first processing to determine the output voltage obtained when the first connection switch is
set to the offset detection connection state as a first offset value, second processing to determine the output voltage obtained
when the second connection switch is set to the offset detection connection state as a second offset value, and third processing
to set the first and second connection switches to the normal connection state when the first and second offset values have
polarities different from each other, and set the first connection switch to the normal connection state and set the second
connection switch to the chopping connection state when the first and second offset values have the same polarity.

US Pat. No. 9,704,912

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a first semiconductor layer including a first region and a second region adjacent to the first region;
a first insulator layer provided above the first semiconductor layer;
an intermediate semiconductor layer, having an n-type conduction, provided above the first region of the first semiconductor
layer and above the first insulator layer;

a second insulator layer provided above the intermediate semiconductor layer;
a second semiconductor layer provided above the first region of the first semiconductor layer and above the second insulator
layer;

a sensor formed in the second region of the first semiconductor layer;
a contact electrode connected to the intermediate semiconductor layer; and
a circuit element formed in the second semiconductor layer.

US Pat. No. 9,684,013

MOTION DETECTING DEVICE, PORTABLE TERMINAL DEVICE AND MOTION DETECTING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A motion detecting device comprising:
an input section to which acceleration signals, that express accelerations of respective axes of three axes of a three-dimensional
orthogonal coordinate system, are respectively inputted; and

a motion detecting section configured to set each of plural axes, that include two different axes that are selected from among
the three axes, as a plurality of designated axes in a predetermined order, and output a motion detection signal upon judgment
that directions of motion, that are detected on a basis of the acceleration signals of the respective axes that were inputted
to the input section, are directions of respective designated axes that have been set,

wherein upon detection that an acceleration signal of an axis has reached both a first threshold value that is set for a positive
side and a second threshold value that is set for a negative side, the motion detecting section is configured to detect that
motion in a direction of the axis has been carried out,

upon judgment that a direction of motion, that is detected on a basis of the acceleration signals of the respective axes that
were inputted to the input section, is a direction of the designated axis that has been set, the motion detecting section
is configured to generate designated axis detection information and store the designated axis detection information, and

upon judgment that a direction of motion, that is detected on a basis of the acceleration signals of the respective axes that
were inputted to the input section, is a direction that differs from the direction of the plurality of designated axes that
has been set, the motion detecting section is configured to delete the designated axis detection information, and return setting
of the designated axis to an initial state.

US Pat. No. 9,620,237

SEMICONDUCTOR DEVICE AND SEARCH CIRCUIT FOR AND METHOD OF SEARCHING FOR ERASURE COUNT IN SEMICONDUCTOR MEMORY

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a semiconductor memory in which data erasure is performed in units of blocks;
a block management memory that stores, corresponding to each of the blocks, a piece of erasure count data representing a count
of data erasures performed in the block; and

an erasure count search circuit that successively reads the pieces of erasure count data from said block management memory
so as to search for a block corresponding to a piece of erasure count data representing an intended erasure count from among
the pieces of erasure count data read from said block management memory,

wherein said erasure count search circuit includes:
a register that holds said intended erasure count;
a data searching portion that searches one erasure count data piece representing said intended erasure count of the read erasure
count data pieces by comparing an erasure count represented by each of said read erasure count data pieces with said intended
erasure count; and

an address output portion that outputs an address of a block corresponding to said one erasure count data piece as a searched
block address when said one erasure count data piece is searched by said data searching portion.

US Pat. No. 9,564,401

METHOD FOR THINNING, METALIZING, AND DICING A SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE MADE USING THE METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a semiconductor substrate having a first principal surface, a second principal surface opposing the first principal surface,
and a side surface, the first principle surface having a rectangular shape with four sides and having a semiconductor element,
and the second principal surface also having a rectangular shape with four sides, the side surface of the substrate being
formed by dicing to connect the sides of the first principal surface with corresponding sides of the second principal surface;
and

a conductive film on the second principal surface formed in direct contact with a diffusion layer formed on the second principal
surface, the conductive film being disposed so as to cover an entire surface of the second principal surface except an outer
edge portion of the second principal surface, wherein the outer edge portion includes the four sides of the second principal
surface,

wherein the semiconductor element is formed in a semiconductor element formation region, the semiconductor formation region
being a region of the first principal surface corresponding to a region where the conductive film is disposed on the second
principal surface in plan view of the first principal surface, wherein the semiconductor element comprises an electrode connected
to the first principal surface.

US Pat. No. 9,553,144

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a semiconductor substrate;
a first semiconductor region, having a first conduction type, on a main surface of the semiconductor substrate, and that includes
an extension portion extending in a specific direction and having a specific width as viewed along a direction orthogonal
to the main surface;

a second semiconductor region, having the first conduction type, on the main surface separated from the first semiconductor
region, and shaped to include a portion running along the extension portion of the first semiconductor region as viewed along
the direction orthogonal to the main surface;

a field relaxation layer on a second semiconductor region side of the main surface, and that is a semiconductor layer having
a second conduction type that is different than the first conduction type,

wherein an end portion of the field relaxation layer facing the first semiconductor region coincides with an end portion of
the second semiconductor region facing the first semiconductor region; and

a conductor connected to the second semiconductor region, and that has an end portion on a first semiconductor region side
positioned within a range of the field relaxation layer.

US Pat. No. 10,075,014

CHARGING CONTROL SYSTEM AND DEVICE

LAPIS Semiconductor Co., ...

1. A semiconductor device comprising:a first terminal electrically connected to an electrode of a first power source;
a second terminal electrically connected to an electrode of a second power source which is different from the first power source; and
a first interrupter connected to the first terminal and the second terminal, the first interrupter interrupting a connection between the first terminal and the second terminal on the basis of a result of a comparison between a divided voltage of the first power source and a divided voltage of the second power source, wherein:
the divided voltage of the first power source is given when a first transistor turns on according to a bias voltage given on the basis of a voltage of the second power source, the first transistor being connected to the first terminal and a third terminal which is electrically connected to the other electrode of the first power source, and
the first interrupter interrupts a connection between the first terminal and the third terminal when the first transistor turns off.

US Pat. No. 9,853,122

SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A method of fabricating a semiconductor device in which current flows in a thickness direction of a substrate, the method
comprising:
forming a first semiconductor region at a front surface of the substrate, the first semiconductor region including an active
element;

forming a damaged layer on a rear surface of the substrate;
etching the rear surface of the substrate self-consistently by a chemical solution to remove the damaged layer;
removing impurities adhered to the semiconductor substrate in association with the removing of the damaged layer;
forming a buffer layer by ion-implantation from the rear surface of the substrate; and
forming a second semiconductor region by implanting impurities of P-type conductivity from the rear surface of the substrate,
wherein a density per unit volume of phosphorous in the second semiconductor region is at most ? of a density of the impurities
of the P-type conductivity in the buffer layer.

US Pat. No. 9,838,022

SEMICONDUCTOR DEVICE WITH OSCILLATION FREQUENCY ERROR CORRECTION

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
an oscillator that is configured to oscillate at an oscillation frequency that corresponds to a predetermined frequency; and
a semiconductor integrated circuit that integrates
a register that stores a value for correcting an error in the oscillation frequency of the oscillator,
a clock generation circuit that creates a predetermined clock based on the value stored in the register,
a controller that is configured to derive the value for correcting the error in the oscillation frequency of the oscillator
based on a peripheral temperature, and

a timer circuit that determines a time based on the clock and transmits the time to the controller.

US Pat. No. 9,827,951

SEMICONDUCTOR DEVICE, WIPER SYSTEM, AND MOVING BODY CONTROL METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
an abnormality detection section that detects an abnormality occurring in a moving body that moves along a specific path on
a surface of a specific object;

a position detection section that detects a position of the moving body as an abnormality occurrence position, in a case in
which the abnormality detection section has detected the abnormality, and that stores abnormality occurrence position information
expressing the abnormality occurrence position in a storage section; and

a moving body controller that controls an adjusting section to adjust a pressing force with which the moving body presses
against the specific object, based on the abnormality occurrence position information,

wherein the storage section further stores the adjusted pressing force corresponding to the abnormality occurrence position,
the moving body controller determines whether the abnormality occurring in the moving body has increased or decreased in a
case in which the adjusting section is controlled to increase the pressing force of the moving body at the abnormality occurrence
position, and

the moving body controller controls the adjusting section so as to maintain the increase of the pressing force at the abnormality
occurrence position in a case in which the abnormality occurring in the moving body has decreased, and controls the adjusting
section so as to decrease the pressing force at the abnormality occurrence position in a case in which the abnormality occurring
in the moving body has increased.

US Pat. No. 9,754,991

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device, comprising:
a first semiconductor layer of a first conductivity type having a primary surface on one side thereof and a secondary surface
on an opposite side thereof, and having a sensor therein;

a second semiconductor layer of a second conductivity type having a circuit element formed therein, the second semiconductor
layer being formed at said one side of the primary surface of the first semiconductor layer;

an insulating layer formed between the first semiconductor layer and the second semiconductor layer, the insulating layer
being disposed on the primary surface of the first semiconductor layer and surrounding the circuit element, the insulating
layer including a charge-attracting semiconductor pattern of the first conductivity type that is disposed in relation to the
circuit element so as to attract electrical charges generated in the insulating layer.

US Pat. No. 9,722,553

HIGH-FREQUENCY AMPLIFIER CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. A high-frequency amplifier circuit for amplifying an input high-frequency signal and outputting the amplified high-frequency
signal, comprising:
a first amplification unit which receives a high-frequency signal via its input terminal and amplifies said high-frequency
signal so as to generate an high-frequency amplified signal;

a second amplification unit which further amplifies said high-frequency amplified signal to generate an output signal and
outputs said output signal via its output terminal;

a first bias unit which supplies a bias voltage to said first amplification unit in response to a first operating current
applied thereto;

a second bias unit which supplies a bias voltage to said second amplification unit in response to a second operating current
applied thereto;

an intermediate potential line which supplies an intermediate potential between a first potential and a second potential to
said first amplification unit and said second amplification unit;

a current generating unit which generates said first operating current; and
a current control unit which is connected to said intermediate potential line and which controls said second operating current
on the basis of said intermediate potential, wherein said first amplification unit includes:

a first field effect transistor (FET) of a first conductivity type, having a source terminal supplied with said first potential;
and

a first inductor connected to said intermediate potential line, and said second amplification unit includes:
a second FET of a second conductivity type opposite to said first conductivity type, having a source terminal supplied with
said second potential; and

a second inductor connected to said intermediate potential line.

US Pat. No. 9,703,304

VOLTAGE BOOSTER CIRCUIT, SEMICONDUCTOR DEVICE, AND VOLTAGE BOOSTER CIRCUIT CONTROL METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A voltage booster circuit comprising:
a reference voltage generation circuit that generates a first potential and supplies the first potential to a first potential
line;

a booster section that supplies a second potential to a second potential line, the second potential being boosted from the
first potential;

a booster control section, connected to the second potential line, that controls the booster section in accordance with the
second potential;

a switch connected to the first potential line and the second potential line; and
a control circuit that controls the switch in accordance with a potential difference between the first potential and the second
potential.

US Pat. No. 9,666,143

AMPLIFYING CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. An amplifying circuit for amplifying an input signal applied thereto through its input line, and for outputting the amplified
signal through its output line, the amplifying circuit comprising:
a first differential amplifier;
a second differential amplifier having an input capacitance larger than the first differential amplifier; and
an amplifier switch unit for outputting, through the output line, a signal caused by amplification of the input signal in
the first differential amplifier in response to an amplification mode setting signal indicative of a high speed mode, and
for outputting, through the output line, a signal caused by amplification of the input signal in the second differential amplifier,
in response to the amplification mode setting signal indicative of a small offset mode.

US Pat. No. 9,634,663

SEMICONDUCTOR CIRCUIT, SEMICONDUCTOR DEVICE AND POTENTIAL SUPPLY CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor circuit comprising:
a level shifter circuit that, in accordance with supply of a power supply voltage, converts a potential of an input signal
from a first potential to a second potential that is higher than the first potential and outputs the second potential through
an output node;

a potential supply circuit, to which a reset signal at a level in accordance with the power supply voltage is supplied, that
supplies a predetermined potential in accordance with the level of the reset signal; and

a control circuit that controls the potential of the output node of the level shifter circuit in accordance with a level of
the predetermined potential supplied from the potential supply circuit.

US Pat. No. 9,620,982

COMPARATOR CIRCUIT, SEMICONDUCTOR DEVICE, BATTERY MONITORING SYSTEM, CHARGING PROHIBITION METHOD, AND COMPUTER-READABLE MEDIUM

LAPIS SEMICONDUCTOR CO., ...

1. A monitoring method for determining necessity of charging prohibition, comprising:
acquiring a potential that is output from an output signal line of a comparator circuit,
the comparator circuit comprising
a first outer terminal connected to a positive electrode of a battery cell,
a second outer terminal connected to a negative electrode of the battery cell,
a switching element having (i) a first terminal to which a voltage applied to the first outer terminal is directly applied,
(ii) a second terminal connected to a first fixed potential supply source, and (iii) a control terminal that controls conduction
between the first terminal and the second terminal in response to an applied voltage,

a voltage regulating unit that has one end connected to the second outer terminal and another end connected to the control
terminal and to a second fixed potential supply source, and that regulates the voltage applied from the second outer terminal
to the switching element, and

the output signal line connected to a connecting portion of the second terminal and the first fixed potential supply source;
judging whether or not the acquired potential is a potential of the first or second fixed potential supply source; and
determining that a voltage of the battery cell is equal to or less than a charging prohibition voltage in a case in which
it is judged that the acquired potential is the potential of the first or second fixed potential supply source.

US Pat. No. 9,584,134

CORRECTING TEMPERATURE BASED OSCILLATION FREQUENCY ERRORS IN SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
an oscillator that has a first electrode and that is configured to oscillate at an oscillation frequency that corresponds
to a predetermined frequency;

a semiconductor integrated circuit that has a second electrode and that integrates
a register that stores a value for correcting an error in the oscillation frequency of the oscillator,
a clock generation circuit that creates a predetermined clock based on the value stored in the register,
a controller that is configured to derive the value for correcting the error in the oscillation frequency of the oscillator
based on a peripheral temperature, and

a timer circuit that determines a time based on the clock and transmits the time to the controller; and
a bonding wire that connects the first electrode of the oscillator and the second electrode of the semiconductor integrated
circuit.

US Pat. No. 9,575,129

BATTERY MONITORING SYSTEM AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A battery monitoring system comprising:
a plurality of battery cells connected in series and including a first battery cell at a highest potential and a second battery
cell at a lowest potential;

a first line having a first terminal connected to a high potential side of the first battery cell through a first filter,
said first filter being connected to a low potential side of the second battery cell;

a second line having a second terminal connected to the high potential side of the first battery cell through a second filter,
said second filter being connected to the low potential side of the second battery cell;

a third line having a third terminal connected to the low potential side of the second battery cell;
a discharge circuit disposed between the first line and the third line;
a circuit disposed between the second line and the third line, said circuit being configured to measure a voltage of the battery
cells when an electrical current flows through the circuit; and

a plurality of electro-static protection circuits each including one end portion connected to at least one of a high potential
side and a low potential side of each of the battery cells, and another end portion connected to the first line so that the
discharge circuit can discharge the electro-static protection circuits.

US Pat. No. 9,536,487

SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND SIGNAL LOADING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A drive IC that outputs to a display panel a signal generated based on image data, the drive IC comprising:
an input section that is input with one of a first differential signal or a second differential signal different than the
first differential signal, and configured to load the input first differential signal or the input second differential signal
according to a first clock signal and output the loaded differential signal;

a holding section configured to receive and load only the first differential signal output from the input section according
to a second clock signal, and hold and then output the held loaded signal;

an output section configured to load the first differential signal or the second differential signal according to a third
clock signal and output the loaded signal;

a selection section configured to
select and output the first differential signal as provided from the holding section to the output section, in which the first
differential signal has been input to the input section, and

select and output the second differential signal as provided from the input section to the output section, in a case in which
the second differential signal has been input to the input section; and

a clock signal supply section configured to supply to the output section the third clock signal corresponding to the first
differential signal or the second differential signal that has been input to the input section.

US Pat. No. 10,141,279

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

LAPIS Semiconductor Co., ...

1. A semiconductor device, comprising:a semiconductor substrate;
a conductor provided on a main surface of the semiconductor substrate;
an insulating layer disposed to cover a surface of the conductor and having a recess from a surface thereof towards the conductor, the recess having an opening provided at a bottom portion of the recess and exposing a portion of the conductor; and
an external connection terminal connected to the portion of the conductor exposed from the opening, wherein
in a plan view of the semiconductor device, the external connection terminal covers the entire opening, and the entire external connection terminal is within the recess.

US Pat. No. 10,134,347

DISPLAY DRIVER AND DISPLAY APPARATUS

LAPIS Semiconductor Co., ...

1. A display driver for supplying a pixel driving voltage corresponding to a video signal to a display device, said display driver comprising:a driving voltage generation part configured to generate a voltage as said pixel driving voltage by inverting a polarity of a voltage representing a luminance level of each pixel based on said video signal according to a polarity inversion signal received via a transmission line, said polarity inversion signal alternately indicating either one of positive and negative polarities; and
a polarity inversion abnormality detection part configured to generate an abnormality detection signal indicating an abnormality of said transmission line when said polarity inversion signal indicates only one constant polarity for a period of N frames (N is an integer greater than or equal to 2) of said video signal.

US Pat. No. 10,043,773

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:a substrate including, in a central portion of a main face of the substrate, n first element formation regions having a rectangular flat plane shape and arrayed along a first direction, and n+m second element formation regions having the same shape as the first element formation regions and arrayed along the first direction and adjacent to the first element formation regions in a second direction intersecting the first direction;
a plurality of projecting electrodes formed at each of the first element formation regions and at each of the second element formation regions;
a first row of dummy projecting electrodes arrayed, at a peripheral portion of the main face, in the second direction along a first edge of the first element formation regions that forms a boundary between the first element formation regions and the peripheral portion; and
a second row of dummy projecting electrodes arrayed, at a peripheral portion of the main face, in the first direction along a second edge of the second element formation regions that forms a boundary between the second element formation regions and the peripheral portion,
wherein the first row of dummy projecting electrodes opposes a row of the plurality of projecting electrodes that are arrayed along the second direction in the first element formation regions with the first edge therebetween, and
wherein the second row of dummy projecting electrodes opposes a row of the plurality of projecting electrodes that are arrayed along the first direction in the second element formation regions with the second edge therebetween.

US Pat. No. 9,755,644

INTERFACE CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

15. An interface circuit configured to receive a first voltage and a second voltage and generate an interface output signal
based on an input signal, the interface circuit comprising:
a latch circuit to which the input signal and said first voltage are supplied, the input signal having a signal level changeable
between the first voltage and a ground potential, to output the output signal,

wherein said latch circuit outputs said output signal as a signal having a signal level varying with an opposite phase to
said input signal in a first state in which the voltage level of said first voltage is higher than the logic threshold value,
and

when the voltage level of said first voltage transit from said first state to a second state in which the voltage level of
said first voltage is less than said logic threshold value, said latch circuit outputs holding the signal level in said first
state just before transition to said second state.

US Pat. No. 9,754,524

DISPLAY DRIVER

LAPIS SEMICONDUCTOR CO., ...

1. A display driver which drives a display device, by applying K (K is an integer greater than or equal to 2) pixel driving
voltages corresponding to pixel-by-pixel luminance levels indicated by an image data signal to K data lines of said display
device, respectively, said driver comprising:
a delayed clock generation part configured to generate first to t-th (t is an integer less than or equal to K and greater
than or equal to 2) delayed clock signals having phases different from each other and being synchronized with a reference
clock signal;

an output enable signal generation part configured to generate first to K-th output enable signals on the basis of said first
to t-th delayed clock signals, wherein said output enable signal generation part includes a shift register including first
to K-th flip-flops connected in series, wherein said first to K-th flip-flops are each supplied with any one of said first
to t-th delayed clock signals, and wherein outputs of said first to K-th flip-flops serve as said first to K-th output enable
signals respectively; and

an output part configured to apply the K pixel driving voltages to the K data lines at respective different timings on the
basis of said first to K-th output enable signals,

wherein:
said delayed clock generation part includes a phase comparator and a variable delay circuit group constituted by first to
(t+1)-th variable delay circuits each having a basic delay time which is one (t+1)-th of a period of said reference clock
signal are connected in series with each other;

said reference clock signal is supplied to the first variable delay circuit;
outputs of the first to t-th variable delay circuits in said variable delay circuit group serve as said first to t-th delayed
clock signals respectively; and

said phase comparator adjusts a delay time of each of the first to t-th variable delay circuits in the variable delay circuit
group on the basis of a phase difference between a signal output from the (t+1)-th variable delay circuit and said reference
clock signal.

US Pat. No. 9,722,457

SEMICONDUCTOR CHIP AND SOLAR SYSTEM

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a semiconductor chip having four sides;
a first terminal which is located along one side of the four sides of the semiconductor chip and which is electrically connected
to a solar cell;

a second terminal which is located along the one side of the semiconductor chip and which is electrically connected to a secondary
cell;

an interconnection line that electrically interconnects the first terminal and the second terminal;
a third terminal, which is located along the one side of the semiconductor chip and which is electrically connected to ground;
and

a discharge section which is formed on the semiconductor chip and is electrically connected to the interconnection line and
the first terminal.

US Pat. No. 9,576,898

RESISTANCE STRUCTURE, INTEGRATED CIRCUIT, AND METHOD OF FABRICATING RESISTANCE STRUCTURE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
a substrate having a well region in which a well is formed and an outer region of the substrate around the well region;
a pair of resistance bodies that comprise a first resistance body and a second resistance body, each having long sides and
short sides, that are provided over the well with an insulating layer interposed between the pair of the resistance bodies
and the well;

a first wiring that extends over the well region and the outer region, and that is connected to one end of one of the pair
of the resistance bodies;

a second wiring that connects another end of the one of the pair of the resistance bodies with one end of another one of the
pair of the resistance bodies; and

a connection portion that connects either of the first wiring or the second wiring with the well.

US Pat. No. 9,543,964

SEMICONDUCTOR DEVICE AND METERING APPARATUS

LAPIS Semiconductor Co., ...

1. A semiconductor device comprising:
an oscillator;
a semiconductor chip that includes:
an oscillation circuit that is connected to the oscillator,
a timer circuit that generates a timing signal of a frequency according to an oscillation frequency of the oscillation circuit,
and

a frequency correction section that corrects a frequency of the timing signal based on temperature data;
a lead frame that the oscillator and the semiconductor chip are mounted on, the lead frame having a through hole between the
oscillator and the semiconductor chip, wherein the oscillator and the semiconductor chip are contained within a single package;
and

a bonding wire, the oscillator being electrically connected to the semiconductor chip through the bonding wire via the through
hole, wherein

the oscillator is mounted on a first main face of the lead frame,
the semiconductor chip is mounted on a second main face, that is on the opposite side of the lead frame to the first main
face,

the through hole is included between the oscillator and the semiconductor chip in a direction that intersects with the first
main face and the second main face,

the through hole of the lead frame exposes a terminal portion of the oscillator to the second main face side, and
the bonding wire is connected to the terminal portion of the oscillator that is exposed to the second main face side through
the through hole.

US Pat. No. 9,495,925

DISPLAY DEVICE AND SOURCE DRIVER

LAPIS SEMICONDUCTOR CO., ...

1. A display device, comprising:
a display panel;
first to m-th source drivers (m is a natural integer greater than three) each including a first input terminal and a first
output terminal connected to the display panel;

first to n-th gate drivers (n is a natural integer greater than three);
a timing controller including a first terminal and a second terminal, said first terminal being provided for outputting or
inputting a first signal indicating a start point of a frame of image data to be displayed on the display panel;

a first signal line connected to the first terminal of the timing controller and each of the first input terminals of the
first to m-th source drivers in parallel so that the first signal is transmitted to each of the first to m-th source drivers
in parallel;

a second signal line connected to the second terminal of the timing controller and each of the first input terminals of the
first to m-th source drivers in parallel so that the first signal is transmitted to each of the first to m-th source drivers
in parallel; and

a third signal line connected to the first to m-th source drivers and the timing controller for transmitting a second signal
indicating a display direction of the image data,

wherein said first to m-th source drivers are configured to operate according to the first signal transmitted from one of
the first terminal of the timing controller and the second terminal of the timing controller selected according to the second
signal, and

each of said first to m-th source drivers further includes a selection unit configured to select the first signal transmitted
from the first terminal of the timing controller or the second terminal of the timing controller according to the second signal.

US Pat. No. 9,985,073

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:a first semiconductor layer including a first region and a second region;
an insulator layer provided above the first semiconductor layer;
a second semiconductor layer provided above the first region of the first semiconductor layer and above the insulator layer;
an n-type conduction region provided under the second semiconductor layer;
a sensor formed in the second region of the first semiconductor layer;
a first contact electrode connected to the n-type conduction region;
a second contact electrode connected to the second semiconductor layer, the second contact electrode being shorter than the first contact electrode;
a third contact electrode connected to the first contact electrode and the second region, the third contact electrode being longer than the second contact electrode; and
a circuit element formed in the second semiconductor layer.

US Pat. No. 9,881,855

SEMICONDUCTOR DEVICE AND METERING APPARATUS

LAPIS Semiconductor Co., ...

1. A semiconductor device comprising:
a first mounted component;
a discrete device that is connected to the first mounted component; and
a semiconductor chip that is connected to the discrete device,
wherein:
the first mounted component, the discrete device and the semiconductor chip are mounted on a lead frame, and
each of the first mounted component and the discrete device is electrically connected to the semiconductor chip through a
bonding wire;

wherein
the lead frame has a through hole, and
a cross-sectional area of the through hole is larger than a cross-sectional area of an external terminal of the first mounted
component.

US Pat. No. 9,740,219

SEMICONDUCTOR DEVICE AND POWER SOURCE SUPPLY METHOD DESCRIPTION

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:
an input terminal to which a power source, for which a time until a voltage equal or greater than a predetermined voltage
value is output fluctuates according to an external environment, is connected;

a power source section to which the input terminal supplies power from the power source;
a power source supply terminal that supplies power to a driven semiconductor device;
a switch that controls a connection between the power source section and the power source supply terminal;
a voltage regulator to which the input terminal supplies power from the power source, and that supplies a voltage to the power
source supply terminal; and

an output terminal that is connected to the driven semiconductor device, and that outputs a standby signal instructing the
driven semiconductor device to prepare for driving; and

a controller that generates the standby signal, and that controls a timing at which the generated standby signal is output
from the output terminal,

wherein the controller includes a reset circuit that outputs the standby signal, and a control circuit that transitions internal
operation to a control preparation state, due to the standby signal from the reset circuit.

US Pat. No. 9,741,534

MONITORING DEVICE, ION IMPLANTATION DEVICE, AND MONITORING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A monitoring device comprising:
a filtering section that extracts and outputs at least one of a high frequency component or a low frequency component of a
beam current received from a detection output section of an ion implantation device; and

a computation section that determines at least one of a value corresponding to a content ratio of the high frequency component
in the beam current, or a value corresponding to a content ratio of the low frequency component in the beam current.

US Pat. No. 9,892,968

SEMICONDUCTOR DEVICE HAVING A DUMMY PORTION, METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE HAVING THE SEMICONDUCTOR DEVICE

LAPIS Semiconductor Co., ...

1. A semiconductor device comprising:
a semiconductor substrate having an obverse surface and a reverse surface opposite to the obverse surface;
a plurality of active elements formed on the obverse surface;
an element-absence area provided adjacent to the active elements on the obverse surface, the element-absence area being free
of any of the active elements;

a first insulating film formed over the active elements and the element-absence area;
at least one electrode pad which is provided inside the first insulating film and is electrically connected to one or more
of the active elements,

the element-absence area further including:
a second insulating film for forming a shallow trench isolation, the second insulating film being disposed on the obverse
surface and under the first insulating film, the second insulating film including a dielectric; and

a plurality of island-shaped dummy portions made of the same material as the semiconductor substrate, each of the dummy portions
being disposed on the obverse surface and in the second insulating film, wherein each of the dummy portions has a peripheral
side in contact with and surrounded by the second insulating film in plan view, an interface between each of the dummy portions
and the first insulating film being coplanar with an interface between the second insulating film and the first insulating
film while a whole area of the interface of each of the dummy portions is in direct contact with the first insulating film;

at least one Through Silicon VIA electrode which is formed in Through Silicon VIA hole penetrating from the reverse surface
of the semiconductor substrate to the obverse surface, an outer edge of the at least one Through Silicon VIA electrode not
intersecting with boundaries where the dummy portions come in contact with the second insulating film for preventing a notch
from being formed, the at least one Through Silicon VIA electrode penetrating the semiconductor substrate from the reverse
surface through the second insulating film onto the at least one electrode pad, at a position to be interposed among the dummy
portions, to be electrically connected to the at least one electrode pad,

wherein the Through Silicon VIA hole has a first aperture part on the at least one electrode pad and a second aperture part
on the reverse surface of the semiconductor substrate, the second aperture part being larger than the first aperture part,

wherein a distance between each of two adjacent dummy portions surrounded by the second insulating film in plan view is smaller
than a diameter of the at least one Through Silicon VIA electrode, except a distance between another two adjacent dummy portions
that interpose the at least one Through Silicon VIA electrode; and

a ring-shaped dummy portion made of the same material as the semiconductor substrate, the ring-shaped dummy portion being
disposed on the obverse surface and in the second insulating film and having a peripheral side in contact with and surrounded
by the second insulating film in plan view,

wherein the at least one Through Silicon VIA electrode is disposed inside the ring-shaped dummy portion in plan view without
contacting the ring-shaped dummy portion.

US Pat. No. 9,887,012

WRITE VOLTAGE GENERATION CIRCUIT AND MEMORY APPARATUS

LAPIS SEMICONDUCTOR CO., ...

1. A write voltage generation and application circuit for generating a write voltage and applying the write voltage to a memory
cell thereby causing said memory cell to memorize data, the write voltage generation and application circuit comprising:
a power supply terminal configured to receive an external power supply voltage;
a boosting circuit configured to boost said external power supply voltage to generate a boosted supply voltage; and
a selective relay circuit configured
to selectively relay said external power supply voltage as said write voltage to said memory cell so that a first charge is
stored in said memory cell during a first part of a write period for writing data to said memory cell, and

to selectively relay said boosted supply voltage as said write voltage to said memory cell so that a second charge is stored
in said memory cell during a latter part of said write period,
the stored first charge being greater in amount than the stored second charge.