US Pat. No. 9,437,810

MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY

KABUSHIKI KAISHA TOSHIBA,...

1. A magnetoresistive element comprising:
a first magnetic layer;
an MgFeO layer; and
a second magnetic layer stacked in a first direction, the MgFeO layer disposed between the first and second magnetic layers;
wherein

Fe of the MgFeO layer is included at least in a central portion of the MgFeO layer in the first direction, and
the MgFeO layer contains at least one element selected from a group consisting of Ti, V, Mn, and Cu.

US Pat. No. 9,258,284

SERVER, METHOD OF GROUP KEY NOTIFICATION AND PROGRAM

Kabushiki Kaisha Toshiba,...

1. A server comprising:
a message communicator configured to communicate a message to a client;
a key information storage configured to store information about a key, the information including at least a key value, a first
validity term, and assignment information;

a key controller configured to generate a notification message about the key, the notification message including a value of
a client key and an update time when the message communicator receives a key request message from an authenticated client,
the key value corresponding with the assignment information, the update time deciding from the first validity term and a second
validity term of authentication succeeded state of the client;

wherein the message communicator transmits the notification message to the client;
a client information storage configured to store client information having a need to authenticate the client; and
an authenticator configured to authenticate the client from an authentication request message and the client information when
the message communicator receives the authentication request message,

wherein the key controller generates the notification message including the key value and the key update time when the message
communicator receives the key request message from the authenticated client, the key value corresponding with the assignment
information, the update time deciding from the first validity time and the second validity time, wherein the client information
includes address information of the client, and

wherein the key controller judges whether to include the update time in the notification message from the address information.

US Pat. No. 9,294,768

MOVING-PICTURE ENCODING APPARATUS AND MOVING-PICTURE DECODING APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. A moving-picture decoding apparatus, comprising:
an entropy decoder configured to obtain transformation coefficients from coded data obtained by coding processes according
to prediction directions;

an order controller configured to rearrange the transformation coefficients according to a scanning order corresponding to
a prediction direction of a target block from among scanning orders predetermined for the prediction directions;

a classifier configured to classify a mode applied to the target block into a predetermined first mode or a predetermined
second mode;

an inverse orthogonal transformer configured to obtain a predictive residual signal by subjecting the rearranged transformation
coefficients to an inverse orthogonal transformation by use of a first transformation basis common to the prediction directions
if the applied mode is classified into the first mode, and obtain a predictive residual signal by subjecting the rearranged
transformation coefficients to the inverse orthogonal transformation by use of a second transformation basis different from
the first transformation basis if the applied mode is classified into the second mode; and

a generator configured to generate a decoded image signal by use of the predictive residual signal,
wherein the inverse orthogonal transformer applies at least one of the first transformation basis and the second transformation
basis to both a first target block coded by inter-prediction and a second target block coded by intra-prediction.

US Pat. No. 9,281,474

VARIABLE RESISTANCE MEMORY AND METHOD OF MANUFACTURING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A variable resistance memory comprising:
a first wiring;
a second wiring provided above the first wiring and intersecting with the first wiring;
a third wiring provided above the second wiring and intersecting with the second wiring;
a first variable resistance element provided in an intersection region between the first wiring and the second wiring, the
first variable resistance element including a first variable resistance layer formed on the first wiring, and an ion source
electrode provided on the first variable resistance layer and penetrating through the second wiring, the ion source electrode
being directly connected to the second wiring; and

a second variable resistance element provided in an intersection region between the second wiring and the third wiring, the
second variable resistance element including a second variable resistance layer formed on the ion source electrode, the ion
source electrode being a common ion source electrode for the first and second variable resistance elements.

US Pat. No. 9,289,991

INKJET HEAD

Kabushiki Kaisha Toshiba,...

1. An inkjet head comprising:
a base plate including an attachment surface and first and second side surfaces each of which cross the attachment surface;
a driving element attached to the attachment surface and including a plurality of pressure chambers, a bottom surface of each
pressure chamber being positioned away from the attachment surface;

a nozzle plate attached to the driving element and including a plurality of nozzles respectively opened to the plurality of
pressure chambers;

a plurality of electrodes respectively provided in the plurality of pressure chambers;
a plurality of wires provided on each of the first and second side surfaces and respectively connected to the plurality of
electrodes;

a supplying unit including a first manifold, the first manifold being independent of the base plate, arranged in an outside
of the first side surface of the base plate, attached to the first side surface via the plurality of wires and connected to
the plurality of pressure chambers to supply the plurality of pressure chambers with ink; and

a discharging unit including a second manifold, the second manifold being independent of the base plate, arranged in an outside
of the second side surface of the base plate, attached to the second side surface via the plurality of wires and connected
to the plurality of pressure chambers to discharge the ink from the pressure chambers.

US Pat. No. 9,288,894

COUPLER APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. A coupler apparatus which transmits or receives an electromagnetic wave to or from another coupler apparatus, comprising:
a coupling element formed of a conductive material and comprising two portions and a coupling portion connecting the two portions
with each other, the coupling portion comprising a feeding point, and the two portions being symmetrical with respect to the
feeding point; and

a ground plane formed of a conductive material and comprising two cutouts, each of the cutouts larger than each of the two
portions so that each of the two portions face a part of each of the cutouts,

wherein:
the two portions comprises a first rectangular portion and a second rectangular portion,
the first rectangular portion comprises first and second open ends,
the second rectangular portion comprises third and fourth open ends,
a first current path is between the feeding point and the first open end through a first half of the coupling element and
a first half of the first rectangular portion,

a second current path is between the feeding point and the second open end through the first half of the coupling element
and a second half of the first rectangular portion,

a third current path is between the feeding point and the third open end through a second half of the coupling element and
a first half of the second rectangular portion,

a fourth current path is between the feeding point and the fourth open end through the second half of the coupling element
and a second half of the second rectangular portion, and

a length of each of the first, second, third, and fourth current paths corresponds to an integral multiple of ¼ of a wavelength
of a central frequency of the electromagnetic wave.

US Pat. No. 9,071,525

DATA RECEIVING APPARATUS, DATA RECEIVING METHOD, AND PROGRAM STORAGE MEDIUM

Kabushiki Kaisha Toshiba,...

1. A data receiving apparatus, comprising:
a receiving unit configured to receive via a network a frame including a header and a data sequence which is a series of data,
a sequence number being associated with each data in the data sequence;

a data storage configured to store data;
a first specifying unit configured to specify a temporary buffer area in the data storage for temporarily storing data of
the data sequence included in the received frame;

a second specifying unit configured to specify a destination buffer area in the data storage for storing data of the data
sequence included in the received frame;

a first identifying unit configured to, when the destination buffer area is specified by the second specifying unit, identify
a destination number range depending on a size of the specified destination buffer area so that the destination number range
follows a destination number range that was last identified, each sequence number included in an identified destination number
range being assigned to a position in the specified destination buffer area that corresponds to a relative position of the
sequence number within the identified destination number range;

a data writing unit configured to, when the frame including the header and the data sequence has been received by the receiving
unit, write a part of the data sequence included in the received frame that falls within one of destination number ranges
which has been identified by the first identifying unit in an assigned position in the destination buffer area that corresponds
to the sequence number of that data, and write remaining data of the data sequence included in the received frame that does
not fall within any of the destination number ranges in the temporary buffer area; and

a data copying unit configured to, when a destination buffer area is newly specified by the second specifying unit, read out
data, from the temporary buffer area, that has a sequence number which falls within a destination number range newly identified
by the first identifying unit for the newly specified destination buffer area so as to follow said destination number ranges
which have been identified by the first identifying unit and write the read-out data at an assigned position in the newly
specified destination buffer area that corresponds to the sequence number of the read-out data.

US Pat. No. 9,288,040

ENCRYPTION DEVICE

Kabushiki Kaisha Toshiba,...

2. An encryption device comprising:
a register;
an input circuitry configured to receive plain data;
a first partial encryption circuitry configured to calculate first intermediate data from the plain data;
a second partial encryption circuitry configured to calculate (i+1)-th intermediate data based on i-th intermediate data and
an encryption key, wherein i is an integer equal to or greater than one and smaller than N, and N is a predetermined integer
equal to or greater than two;

a first transform circuitry configured to:
transform j-th intermediate data into j-th transformed data, wherein j is an integer equal to or greater than one and equal
to or smaller than N; and

store the j-th transformed data in the register;
a second transform circuitry configured to transform the j-th transformed data stored in the register into the j-th intermediate
data;

a third partial encryption circuitry configured to calculate encrypted data from the N-th intermediate data;
an output circuitry configured to output the encrypted data; and
a random number generation circuitry configured to generate a random number, wherein
the second partial encryption circuitry is further configured to repeat processing to calculate (j+1)-th intermediate data
while j is equal to from 1 to N?1, the processing being repeated based on the j-th intermediate data and the encryption key,
the j-th intermediate data being transformed from the j-th transformed data by the second transform engine,

the first transform circuitry is further configured to:
transform the random number into a transformed random number using a predetermined first transform processing;
store the transformed random number in the register; and
transform the j-th intermediate data into the j-th transformed data,
the j-th transformed data being masked with the random number, and
the second transform circuitry is further configured to:
transform the transformed random number stored in the register into the random number using a second transform processing,
the second transform processing transforming the transformed data after the transform by the first transform processing into
the data before the transform by the first transform processing; and

transform the j-th transformed data stored in the register into the j-th intermediate data,
the j-th intermediate data being released from the mask using the random number, and
the random number not being stored in the register.

US Pat. No. 9,281,328

IMAGE SENSOR THAT INCLUDES A BOUNDARY REGION FORMED BETWEEN A LOGIC CIRCUIT REGION AND AN IMAGE-SENSING ELEMENT REGION AND MANUFACTURING METHOD THEREOF

KABUSHIKI KAISHA TOSHIBA,...

1. An image sensor comprising:
a semiconductor substrate;
a logic circuit region, formed on the substrate, including a plurality of gate patterns;
an image-sensing element region formed in a region different from the logic circuit region on the substrate, the image-sensing
element region including a plurality of image-sensing elements and element isolation portions for isolating the image-sensing
elements; and

a boundary region formed between the logic circuit region and the image-sensing element region, dummy element isolation portions
being arranged at a preset pitch in the boundary region, wherein

the boundary region has a boundary width not smaller than a thermal diffusion length of annealing for the substrate.

US Pat. No. 9,307,679

SERVER ROOM MANAGING AIR CONDITIONING SYSTEM

Kabushiki Kaisha Toshiba,...

1. A server room management air conditioning system in which the air conditioning system performs an air conditioning of the
server room in an all circulation mode in which outside air is not introduced but supplied air is manufactured from returned
air and supplied to the server room, the server room management air conditioning system comprising:
a coil setting control device configured to obtain an estimated amount of absolute humidity in the server room in the all
circulation mode,

first coils in which the number of the coils which are to be used for humidity control out of a group of coils is determined,
by the coil setting control device, in response to the estimated amount of absolute humidity in the server room in the all
circulation mode, wherein the first coils are configured to adjust the returned air of the server room to a predetermined
temperature value lower than a predetermined supplied air temperature target value to perform dehumidification;

second coils in which the number of the coils out of the group of coils which are to be used is determined, by the cooling
coil control device, for temperature control in response to the estimated amount of absolute humidity in the server room in
the all circulation mode, which are installed in a same area as an area of the first coils, and which adjusts the returned
air of the server room to a predetermined temperature value higher than the supplied air temperature target value so that
the returned air takes the supplied air temperature target value and a predetermined supplied air humidity target value when
the returned air is mixed with air adjusted by the first coils; and

an air supply fan that mixes the returned air adjusted by the first coils and the returned air adjusted by the second coils
to supply as supplied air to the server room.

US Pat. No. 9,176,240

APPARATUS AND METHOD FOR CHANNEL COUNT REDUCTION IN SOLID-STATE-BASED POSITRON EMISSION TOMOGRAPHY

Kabushiki Kaisha Toshiba,...

1. A data acquisition device for a gamma ray detector, comprising:
a summing circuit configured to sum a plurality of electrical signals from a corresponding plurality of sensors coupled to
an array of scintillation crystals to generate a first signal, the plurality of sensors converting received light into the
plurality of electrical signals, wherein the light is generated by a crystal of interaction in response to incident gamma
rays generated by an annihilation event;

a delay summing circuit configured to selectively delay and sum the plurality of electrical signals to generate a second signal;
a first circuit configured to receive the first signal and to determine an energy and an event time of the first signal; and
a second circuit configured to receive the first signal and the second signal and to determine, based on when the first and
second signals respectively exceed a predetermined threshold, which sensor of the plurality of sensors corresponds to a location
of the crystal of interaction.

US Pat. No. 9,280,518

PUBLIC KEY CRYPTOGRAPHY COMPUTING DEVICE

Kabushiki Kaisha Toshiba,...

1. A public key cryptography device for reducing computation time when converting between representations of a file, comprising:
at least one processor; and
a memory storing instructions, which, when executed by the at least one processor configure the processor to:
receive, via a hardware interface, a plurality of pieces of input data for public key cryptography indicative of elements
of a subgroup of a multiplicative group in a finite field and a plurality of pieces of first additional data for identifying
conjugates of the respective pieces of input data, the elements being represented by traces;

calculate a coefficient of an equation based on the pieces of input data, the equation having a solution that is a possible
value as a result of a predetermined computation performed on the pieces of input data;

obtain a plurality of solutions of the equation having the coefficient by performing a bit inversion in memory;
select one of the solutions as the result of the predetermined computation, based on the pieces of first additional data;
determine second additional data for identifying a conjugate of the result of the predetermined computation, based on the
pieces of first additional data; and

output the selected result of the predetermined computation and the second additional data to facilitate converting between
representations of a file for public key encryption.

US Pat. No. 9,272,559

COLOR ERASING APPARATUS

Kabushiki Kaisha Toshiba,...

1. A color erasing apparatus capable of erasing the color of an image formed with a color erasable material on a sheet, comprising:
a color erasing section configured to erase the color of an image formed on the sheet;
a control panel configured to set an area to scan the sheet;
a reading section configured to scan and read the image of the area set on the sheet; and
a control section configured to determine a state of the image erased by the color erasing section.

US Pat. No. 9,276,269

CATALYST LAYER, MEMBRANE ELECTRODE ASSEMBLY, AND ELECTROCHEMICAL CELL

KABUSHIKI KAISHA TOSHIBA,...

1. A catalyst layer comprising a catalyst material, wherein the catalyst layer has a single layer structure and has a porosity
of 20 to 90% by vol and the catalyst layer satisfies a relation:
R1?R0×1.2,
wherein:
R1 is an alignment ratio of the catalyst layer; and
R0 is an alignment ratio of the catalyst material in powder form having a random crystalline plane distribution,
wherein each of the alignment ratios is calculated from a X-ray diffraction spectrum having a diffraction angle 2? range from
10 to 90 degree measured using Cu-K?-rays, and is defined as a ratio of a diffraction peak area contributed by the most closely
packed crystalline planes of a material to a total area of all diffraction peaks of the same material at the 2? range from
10 to 90 degree,

wherein the catalyst layer is formed on a substrate having a flatness of 60% or more and wherein the substrate is a carbon
sheet.

US Pat. No. 9,263,140

NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A non-volatile semiconductor storage device comprising:
a memory cell array having an electrically rewritable non-volatile memory cell arranged therein; and
a control unit configured to perform controlling of repeating an erase operation to apply an erase pulse voltage to the memory
cell for data erase and an erase verify operation to verify whether data erase is completed, the erase pulse voltage including
a first erase pulse voltage generated in a first one of the erase operations as an initial one and a second erase pulse voltage
generated thereafter in a second one of the erase operations,

the control unit being configured to, when control of repeating the erase operation and the erase verify operation is performed,
cause the erase pulse voltage to increase by a certain step-up voltage in the erase operation if it is verified that data
erase is not completed in the erase verify operation, and

the control unit being configured to control the erase pulse voltage such that:
at least a voltage wave shape of the first erase pulse voltage when a vertical axis thereof denotes a voltage and a lateral
axis denotes time has a blunted wave-shape portion that is continuous to a saturation value thereof, the blunted wave-shape
portion being defined by a period in which a gradient at a first point of time is not larger than a gradient at a second point
of time before the first point of time in the voltage wave shape through the period; and

the first erase pulse voltage is longer than the second erase pulse voltage with respect to a width of the blunted wave-shape
portion.

US Pat. No. 9,152,554

NON-VOLATILE MEMORY SYSTEM WITH COMPRESSION AND ENCRYPTION OF DATA

Kabushiki Kaisha Toshiba,...

1. A memory system comprising:
a non-volatile memory;
a cache memory partitioned into at least a first area, a second area, and a third area;
a compressor configured to compress data;
an encryptor configured to encrypt data;
a decryptor configured to decrypt data;
a data flow controller configured to perform a first process that causes the encryptor to encrypt user data received from
a host in a non-compressed state and stored in the first area, and causes the encrypted user data to be written into the non-volatile
memory via the second area, and a second process that causes the encrypted user data to be subsequently read out from the
non-volatile memory into the third area, causes the decryptor to decrypt the encrypted user data and store the decrypted user
data in the first area, causes the compressor to compress the decrypted user data, causes the encryptor to encrypt the compressed
user data, and causes the encrypted and compressed user data to be written into the non-volatile memory via the second area;
and

a pattern tracking unit configured to track frequencies of data patterns during the first process for use during the second
process, wherein

the data flow controller is further configured to maintain a table of user data addresses, and
the frequencies of data patterns are stored in the table and associated with the user data addresses in the table.

US Pat. No. 9,295,141

IDENTIFICATION DEVICE, METHOD AND COMPUTER PROGRAM PRODUCT

Kabushiki Kaisha Toshiba,...

1. An identification device comprising:
a hardware processor configured to execute following elements:
a controller configured to control turning on/off of a plurality of light emitting apparatuses installed in a space via a
network individually by using pieces of identification information of their respective light emitting apparatuses; and

an identifying unit configured to determine an installation position of each of the light emitting apparatuses by using the
on/off control on the light emitting apparatuses, images capturing the space in time series by an imaging unit, and position/posture
information indicative of a position and a posture of the imaging unit, and identify each of the light emitting apparatuses
determined by the installation position corresponding to each of the light emitting apparatuses identified by the pieces of
identification information with each other.

US Pat. No. 9,386,683

PARTICLE ACCELERATOR AND MEDICAL EQUIPMENT

Kabushiki Kaisha Toshiba,...

1. A particle accelerator comprising:
a particle source from which a particle beam is extracted with a beam pulse width of not greater than 2 ?sec;
a linear accelerator that accelerates the particle beam extracted from the particle source;
a synchrotron that receives the particle beam transported thereto from the linear accelerator and causes the particle beam
to circulate in order to accelerate the particle beam until the particle beam gets to a predetermined energy level;

a bump electromagnet that shifts the circulating path of the particle beam each time the particle beam makes a full turn;
and

a controller that controls, by gradually reducing the amperage of electric current that is supplied to the bump electromagnet
each time the particle beam makes the full turn, extent of magnetic excitation of the bump electromagnet and controls timing
of magnetic excitation of the bump electromagnet according to the pulse timing of the particle source.

US Pat. No. 9,268,325

MANUFACTURING PROCESS MONITORING SYSTEM AND MANUFACTURING PROCESS MONITORING METHOD

Kabushiki Kaisha Toshiba,...

1. A manufacturing process monitoring system for monitoring anomalies in a manufacturing process for products, the system
comprising:
an information storage section configured to store data collected from plural lots of a manufactured product as previously
collected data;

a selection information section configured to create a value of a weighting factor, wherein the value of the weighting factor
pertains to a product yield for each lot of the manufactured product and establishes a priority associated with the weighting
factors when classifying the previously collected data, wherein a higher yield is classified with a higher priority;

a detection apparatus configured to acquire data in the manufacturing process that is subjected to anomaly monitoring;
a reference space formation section configured to classify the previously collected data provided from the information storage
section to produce classified data by using a product of a distance and the value of the weighting factor, the reference space
formation section configured to form a reference space based on the classified data, the distance being between the data subjected
to anomaly monitoring and each of the previously collected data provided from the information storage section; and

a monitoring section configured to monitor anomalies of the data subjected to anomaly monitoring based on the reference space.

US Pat. No. 9,222,994

PERPENDICULAR SPIN TORQUE OSCILLATOR FMR FREQUENCY MEASUREMENT METHOD

TDK Corporation, Tokyo (...

1. A method to characterize the frequency of a spin torque oscillator (STO), comprising:
(a) providing a STO including at least a magnetic reference layer (MRL) having a film plane, a magnetic oscillation layer
(MOL) having an in-plane magnetization component, and a non-magnetic spacer (junction) layer formed between the MRL and MOL,
said MRL has perpendicular magnetic anisotropy with a magnetization that is perpendicular to said film plane;

(b) applying a DC current that flows in a direction from the MRL through the MOL and induces an oscillation state with a certain
oscillation frequency within the MOL in-plane magnetization component;

(c) applying a magnetic field having at least an in-plane component to said STO to produce an in-plane magnetization component
within the MRL and a variable resistance across the STO; and

(d) measuring a resulting AC voltage change from essentially zero before the applied magnetic field to a value substantially
greater than zero that occurs from the variable resistance across the STO, said AC voltage change is directly related to the
MOL oscillation frequency.

US Pat. No. 9,288,769

WIRELESS POWER CONTROL APPARATUS AND METHOD HAVING MULTIPLE TRANSMIT POWER LEVELS

KABUSHIKI KAISHA TOSHIBA,...

3. A wireless communication apparatus comprising:
a reception unit configured to receive a first request frame and a second request frame, the first request frame indicating
a connection request from another communication apparatus and requiring an acknowledgement, the second request frame indicating
the connection request from the other communication apparatus and not requiring the acknowledgement;

a management unit configured to notify an upper layer of a first notification indicating that the first request frame is received,
and obtain, from the upper layer, a second notification indicating whether or not to connect to the other communication apparatus;

a measurement unit configured to measure a first value indicating a reception power value when the first request frame is
received, and a second value indicating a reception power value when the second request frame is received;

a determination unit configured to determine, before the second notification is obtained, which of a first difference value
and a second difference value is smaller, the first difference value being a difference value between the first value and
a target value which indicates a target reception power value, the second difference value being a difference value between
the second value and the target value;

a control unit configured to set, as a request transmission power, a transmission power value corresponding to the first value
when the first difference value is smaller than the second difference value, and configured to set, as the request transmission
power, a transmission power value corresponding to the second value when the second difference value is smaller than the first
difference value;

a generation unit configured to generate an accept frame including information indicating the request transmission power;
a transmission unit configured to transmit the accept frame to the other communication apparatus; and
a counter configured to count a number of times of reception of the first request frame,
wherein if the number of times of reception of the first request frame is not more than a predetermined threshold, the generation
unit generates an acknowledgement frame including information for requesting the first request frame as frame type information
for specifying a type of frame, and

wherein the determination unit determines, as the first difference value, a difference value between the target value and
an average of the first values.

US Pat. No. 9,529,714

ELECTRONIC DEVICE

SK Hynix Inc., Gyeonggi-...

1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes:
a first magnetic layer having a variable magnetization direction;
a second magnetic layer having a pinned magnetization direction; and
a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer,
wherein the second magnetic layer includes FeCoB and molybdenum (Mo) as an additive,
wherein a content of the molybdenum in the second magnetic layer is more than zero and less than 10%, and
wherein the second magnetic layer has a thickness of 10 Å to 30 Å.

US Pat. No. 9,288,443

BROADCAST CONTENT DISTRIBUTION SYSTEM, AND DISTRIBUTION APPARATUS AND BROADCAST RECEPTION TERMINAL DEVICE FOR USE IN THE SYSTEM

KABUSHIKI KAISHA TOSHIBA,...

1. A broadcast content distribution system, comprising:
a distribution apparatus which:
receives broadcast data over a broadcast network;
demodulates the received broadcast data to generate broadcast transport stream packets;
eliminates unnecessary packets from the broadcast transport stream packets to generate video-related data for a mobile terminal;
acquires time information to be provided by analyzing the broadcast transport stream packets;
generates program management information based on the provided time information;
accumulates the video-related data and the program management information;
accepts an individualized request to deliver video-related data of a designated program which has been sent through a network
and impossible time information which indicates that data reception becomes impossible;

determines whether or not data viewing becomes non-viewable by checking the impossible time information with the program management
information;

selects, when it is determined that data viewing becomes non-viewable, the whole video-related data of the requested program
from accumulated video-related data; and

distributes IP packets into which the selected whole video-related data is converted to a request origin;
a mobile broadcast reception terminal device which:
receives broadcast data over a broadcast network from a broadcast transmitting station and IP packets over a IP network;
reproduces a program included in the broadcast data;
monitors presence or absence of the data reception to generate the impossible time information;
accumulates the generated impossible time information;
accepts a request to play interrupted data;
accesses the distribution apparatus over the IP network;
transmits a request for distribution of the interrupted data and the accumulated impossible time information;
receives the IP packets for the requested data;
generates broadcast transport stream packets based on the received IP packets; and
decodes the broadcast transport stream packets to reproduce the interrupted content from at least an interrupted point.

US Pat. No. 9,280,134

IMAGE FORMING APPARATUS

Kabushiki Kaisha Toshiba,...

1. An image forming apparatus, comprising:
a paper feed section configured to store a sheet;
a toner cartridge which is detachably mounted from a first direction to store a toner;
a front wall having a first opening in the first direction of the image forming apparatus;
a processing unit which is detachably mounted from a second direction perpendicular to the first direction and is provided
with a photoconductor, a developing section for supplying the toner fed from the toner cartridge to the surface of the photoconductor
to convert an electrostatic latent image to a toner image and a cleaning section for collecting the toner adhered on the surface
of the photoconductor;

a power supply section located nearby a wall in the first direction of the image forming apparatus to respectively supply
power to the toner cartridge, the photoconductor, the developing section and the cleaning section;

a drive section located nearby a wall of the image forming apparatus opposite to the power supply section to respectively
drive the toner cartridge, the photoconductor, the developing section and the cleaning section;

a conveyance section configured to convey the sheet from the paper feed section to the processing unit;
a conveyance path cover section configured to rotate between an opening position for exposing the conveyance section and a
closing position covering the conveyance section to take out a sheet jammed in the conveyance section from the conveyance
section; and

a side wall having a second opening in the second direction of the image forming apparatus; wherein
the drive section is located opposed to the power supply section along the first direction;
the toner cartridge and the processing unit are mounted so that the longitudinal direction of the toner cartridge and the
processing unit is to be the first direction;

the processing unit can be detached when the conveyance path cover section is set at the opening position, and the processing
unit is mounted or removed to the drive section and the power supply section by mounting or removing from the second direction;
and

the toner cartridge is still mounted on the image forming apparatus when the processing unit is detached from the image forming
apparatus, the toner cartridge is exchanged via the first opening and the processing unit is exchanged via the second opening.

US Pat. No. 9,240,805

PARITY CHECK MATRIX CREATION METHOD, ENCODING APPARATUS, AND RECORDING/REPRODUCTION APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. A parity check matrix creation method comprising:
creating a mask matrix whose column weight is K (K is an integer not less than 2) by assigning one of “1” and “0” to each
element of M rows×N columns (M is an integer not less than 4, and N is an integer larger than M); and

creating a parity check matrix by, for each element in the mask matrix, arranging a cyclic permutation matrix having P rows×P
columns (P is an integer not less than 2) at a corresponding position when the element is “1” and arranging a zero matrix
having P rows×P columns at a corresponding position when the element is “0”,

wherein all N column vectors in the mask matrix are different,
any submatrix having M rows×L columns (L is an integer not more than (M?K+1)) obtained by arbitrarily extracting L continuous
columns from the mask matrix includes:

B1 (B1 is an integer not less than 1) first correction rows; and

Bi, (Bi, is an integer not less than 1, i includes all integers not less than 2 and not more than I, and I is an integer not less
than 2) ith correction rows,

each of the B1 first correction rows has a row weight of 1,

the B1 first correction rows have at least one “1” in total in each of A1 (A1 is an integer not less than 1 and not more than B1) first correction columns,

each of the Bi ith correction rows has a row weight of not less than 2,

each of the Bi ith correction rows has at least one “1” in total in Ai?1 (Ai?1 is an integer not less than 1 and not more than Bi?1) (i?1)th correction columns,

each of the Bi ith correction rows has “1” in one of Ai (Ai is an integer not less than 1 and not more than Bi) ith correction columns included in a column set excluding the first correction columns to (i?1)th correction columns,

the Bi ith correction rows include at least one “1” in total in each of the Ai ith correction columns,

a sum from A1 to AI equals L, and

Bi is not more than Ai?1×(K?1).

US Pat. No. 9,176,450

IMAGE FORMING APPARATUS THAT ERASES IMAGES DURING INTERRUPTION OF IMAGE FORMING

Kabushiki Kaisha Toshiba,...

1. An image forming apparatus comprising:
an image forming unit configured to form images that are to be transferred to first sheets;
a fixing and erasing unit configured to fix the images onto the first sheets and erase images formed with a decolorizable
material on second sheets; and

a controller configured to:
interrupt the image forming unit to stop formation of images that are to be transferred to the first sheets, and
control the fixing and erasing unit to carry out an erasing operation on the second sheets while the image forming unit is
interrupted.

US Pat. No. 9,280,173

ELECTRONIC DEVICE

Kabushiki Kaisha Toshiba,...

1. An electronic device comprising:
a first circuit board comprising a first face and a second face opposite the first face and to which an opening and a cutout
portion is provided, the opening penetrating through the first circuit board between the first face and the second face, the
cutout portion extending to a side separating from a center of the opening at an edge of the opening;

a second circuit board comprising a third face and a fourth face opposite the third face, the second circuit board overlapping
the first circuit board and being electrically connected to the first circuit board in a state in which the fourth face and
the first face face each other, the second circuit board covering the opening;

a first electronic component provided to the third face, and electrically connected to the second circuit board; and
a second electronic component provided to the fourth face and electrically connected to the second circuit board in a state
in which at least a portion of the second electronic component is held in the opening.

US Pat. No. 9,219,178

METHOD TO FABRICATE COLLIMATOR STRUCTURES ON A DIRECT CONVERSION SEMICONDUCTOR X-RAY DETECTOR

KABUSHIKI KAISHA TOSHIBA,...

1. A method of fabrication of a collimator structure on a detector of a Computed Tomography (CT) apparatus, the method comprising:
applying a first layer of resist to a semiconductor sensor;
applying a second layer of resist over the first layer of resist and the semiconductor sensor to cover both the first layer
of resist and the semiconductor sensor;

exposing the second layer of resist to ultraviolet (UV) light with a photomask to transfer a pattern from the photomask to
the second layer of resist;

removing portions of the second layer of resist corresponding to the pattern from the photomask to produce openings in the
second layer of resist, which expose upper portions of the semiconductor sensor;

depositing a layer of metal in the openings and on the second layer of resist to cover the openings, the first layer of resist,
the second layer of resist, and the semiconductor sensor;

polishing an upper portion of the layer of metal such that the layer of metal in the openings is flush with the second layer
of resist; and

dicing the first layer of resist and the second layer of resist.

US Pat. No. 9,170,339

RADIATION MEASUREMENT APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. A radiation measurement apparatus comprising:
a visible image acquisition unit that picks up a visible image;
a radiation intensity acquisition unit that measures intensity distribution of radiation coming from a direction being substantially
equal to an image picking up direction of the visible image acquisition unit;

an intensity display unit that displays an image obtained by overlaying the intensity distribution of radiation, which is
represented by using a plurality of colors being allocated to the intensity distribution of radiation on the visible image;

a movement distance calculation unit that calculates a movement distance between the visible images successively picked up
by the visible image acquisition unit; and

a resolution improvement unit that obtains a high resolution intensity distribution of the radiation intensity distribution
by overlaying a plurality of the radiation intensity distribution with a situation where the movement distance calculated
by the movement distance calculation unit is shifted.

US Pat. No. 9,307,533

APPARATUS AND METHOD FOR WIRELESS COMMUNICATION

Kabushiki Kaisha Toshiba,...

1. A wireless communication apparatus capable of controlling communication on at least a first frequency channel and a second
frequency channel, comprising:
a baseband processor to generate a beacon frame, the beacon frame, via the first frequency channel, notifying of an identifier
of the second frequency channel, frequency band information on the second frequency channel, and a group identifier which
is used on the second frequency channel, a group of the group identifier being a system component configured by the wireless
communication apparatus and that controls to transmit and receive frames on the first frequency channel and the second frequency
channel,

wherein each of the frames includes a source address and a destination address, and the baseband processor controls to:
receive, via the first frequency channel, a connection request frame in which a first address is specified as the source address;
receive, via the first frequency channel, a change request frame to change to the second frequency channel in which the first
address is specified as the source address, after permitting a connection request by the connection request frame, and

conduct, via the second frequency channel, sending of a frame in which the first address is specified as the destination address
and receiving of a frame in which the first address is specified as the source address, after permitting a change request
by the change request frame.

US Pat. No. 9,279,889

LIGHT DETECTION UNIT AND ALPHA RAY OBSERVATION DEVICE

Kabushiki Kaisha Toshiba,...

1. A light detecting unit to observe alpha rays by measuring a generated light generated by alpha rays occurring in a region
of a to-be-measured object, comprising:
a travel direction changing unit configured to change a travelling direction of the generated light;
a light detector configured to detect direction-changed light of the generated light changed in traveling direction; and
a shielding member including a portion provided on a straight line extending from the to-be-measured object to the light detector
to shield the light detector against radiation.

US Pat. No. 9,156,640

SHEET PROCESSING APPARATUS AND COLOR ERASING APPARATUS

Kabushiki Kaisha Toshiba,...

5. A color erasing apparatus, comprising:
a color erasing module configured to eliminate the color generation of a color material constituting an image to erase the
color;

a main body side guiding module configured to guide a sheet to the color erasing module;
a first movable module configured to provide a conveyance path for conveying the sheet between the main body side guiding
module and the first movable module at a first position opposite to the main body side guiding module, and move to a second
position to open the conveyance path through motion from the first position towards a first direction;

a second movable module configured to hold a detachable processing module for carrying out adding a mark on the sheet to indicate
the reuse times of the sheet, and move integrally with the first movable module from the first position to the second position;
and

a connection module comprising a rotation fulcrum, wherein the rotation fulcrum couples the second movable module with the
first movable module in such a manner that the second movable module can move to a third position to expose the processing
module through rotational motion from the second position in a second direction opposite to the first direction.

US Pat. No. 9,087,980

MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY

KABUSHIKI KAISHA TOSHIBA,...

11. A magnetoresistive element comprising:
a base layer; and
a stacked structure provided on the base layer, the stacked structure including: a first magnetic layer including a first
magnetic film having an axis of easy magnetization in a direction perpendicular to a film plane, the first magnetic film including
MnxGa100-x (45?x<64 atomic %); a second magnetic layer including a second magnetic film having an axis of easy magnetization in a direction
perpendicular to a film plane; a first nonmagnetic layer provided between the first magnetic layer and the second magnetic
layer, and containing at least one element selected from the group consisting of Mg, Ca, Ba, Al, Ag, Cu, Be, Sr, Zn, and Ti;
and a first interfacial layer provided between the first magnetic layer and the first nonmagnetic layer, the first interfacial
layer including a Heusler alloy,

a magnetization direction of the first magnetic layer being changeable,
wherein the second magnetic layer has a fixed magnetization direction,
wherein the magnetoresistive element further comprises: a third magnetic layer provided on the opposite side of the second
magnetic layer from the first nonmagnetic layer, having an axis of easy magnetization in a direction perpendicular to a film
plane, and having a magnetization direction antiparallel to the magnetization direction of the second magnetic layer; and
a second nonmagnetic layer provided between the second ferromagnetic layer and the third ferromagnetic layer,

wherein MS2 represents a saturation magnetization of the second magnetic layer, t2 represents a film thickness of the second magnetic layer, MS3 represents a saturation magnetization of the third magnetic layer, and t3 represents a film thickness of the third magnetic layer, and the following relationship is satisfied

MS2×t2

US Pat. No. 9,313,794

INTER-CELL INTERFERENCE MITIGATION

Kabushiki Kaisha Toshiba,...

1. A controller controlling communication in a cellular wireless communications network comprising a plurality of base stations,
each base station of the network defining a cell wherein a base station is capable of effecting wireless communication with
terminal stations located within the cell associated with that base station, each base station being capable of effecting
wireless communication with an associated terminal station on a communication channel of a plurality of communication channels
defined in a wireless communication medium, the control unit comprising:
a memory storing, for each base station, terminal station information for one or more terminal stations associated with that
base station, the terminal station information comprising classification information identifying a classification of the terminal
station, the classification being one of a first classification associated with an edge region of its associated cell, or
a second classification associated with a central region of its associated cell, utility information for the terminal station,
the utility information describing performance capability of that terminal station, and, if the classification information
is indicative of the first classification, the memory further storing interference risk information identifying any of the
other base stations that present an interference risk to the performance of the terminal station;

an allocation processor operable to allocate one or more of said terminal stations to a communications channel, the allocation
processor being configured to determine a list of terminal stations available for allocation, initially each terminal station
identified in the list being that terminal station, for each base station, with the highest performance capability in its
associated base station of the terminal stations identified in the stored information, the allocation processor being further
configured to identify a terminal station from the list on the basis of a selection criterion, to allocate that identified
terminal station to a communications channel, and thereafter to modify the list to remove therefrom the allocated terminal
station and, if the allocated terminal station is in the first classification, to modify the list to take account of any terminal
station identified in the list which, on the basis of the stored interference risk information, presents an interference risk
to the allocated terminal station.

US Pat. No. 9,281,365

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:
a first electrode;
a first insulating section arranged with the first electrode in a first direction;
a first semiconductor region including silicon carbide, the first semiconductor region being of a first conductivity type
and including a first semiconductor part and a second semiconductor part, the first semiconductor part overlapping the first
electrode in a second direction crossing the first direction, the second semiconductor part overlapping the first insulating
section in the second direction;

a second semiconductor region including silicon carbide, the second semiconductor region being of a second conductivity type,
a part of the second semiconductor region being provided between the first insulating section and the second semiconductor
part in the second direction, another part of the second semiconductor region being provided between the first electrode and
the second semiconductor part in the second direction;

a third semiconductor region including silicon carbide, the third semiconductor region being of the first conductivity type
and provided between the first insulating section and the part of the second semiconductor region in the second direction,
at least a part of the another part of the second semiconductor region being provided between the third semiconductor region
and the first semiconductor part in the first direction; and

a second insulating section including
a first insulating part provided between the first electrode and the first semiconductor part in the second direction,
a second insulating part provided between the first electrode and the first insulating section in the first direction,
a material of the second insulating section being different from a material of the first insulating section.

US Pat. No. 9,263,114

ELECTRONIC DEVICE

SK Hynix Inc., Gyeonggi-...

1. An electronic device comprising a semiconductor memory unit, the semiconductor memory unit comprising:
first to Nth variable resistance elements each having different resistance values according to values stored therein, wherein N is a natural
number equal to or greater than 2;

a reference resistance element having a first reference resistance value; and
first to Nth comparison units which correspond to the first to Nth in variable resistance elements, respectively, and each of which determines whether a resistance value of the corresponding
variable resistance element is greater or less than a second reference resistance value,

wherein the first to Nth comparison units are commonly coupled to the reference resistance element.

US Pat. No. 9,258,828

WIRELESS COMMUNICATION APPARATUS AND METHOD

KABUSHIKI KAISHA TOSHIBA,...

1. A wireless communication apparatus, comprising:
a storage which stores a first set and a second set, the first set including first inter frame spaces of one or more types
and the second set including second inter frame spaces of the one or more types, the first inter frame spaces and the second
inter frame spaces each indicating a time required before a frame can be transmitted after detecting carrier sense on a wireless
medium changed from busy to idle;

a selection unit which selects either the first set or the second set in order to use for communication; and
a transmission and reception processing unit which communicates with a first apparatus using a first communication scheme,
by using either the first inter frame spaces or the second inter frame spaces according to a selection result of the selection
unit;

wherein when each of the second inter frame spaces are compared with each of the first inter frame spaces of a same type,
a value of said each of the second inter frame spaces is equal to or larger than a value of said each of the first inter frame
spaces of the same type, a value of one of the second inter frame spaces of a first type is larger than a value of one of
the first inter frame spaces of the first type, and the value of one of the second inter frame spaces of the first type is
determined based on a value of an inter frame space used in a second communication scheme,

wherein the first communication scheme is a scheme for transmitting and receiving data between a plurality of devices, and
wherein the second communication scheme is a scheme for transmitting and receiving data between a plurality of devices.

US Pat. No. 9,294,269

COMMUNICATION APPARATUS AND COMMUNICATION METHOD

Kabushiki Kaisha Toshiba,...

1. A client apparatus comprising:
a computer; and
a program that includes an obtaining unit, a generation unit, and a communication unit, the program, when executed by the
computer, causes:

the obtaining unit to obtain a master key from a server apparatus, the master key being notified after authentication between
the server apparatus and the client apparatus succeeds;

the generation unit to generate an individual key by the client apparatus by using the master key from the sever apparatus,
the individual key being shared between the client apparatus and a second client apparatus that mutually authenticate each
other using the master key; and

the communication unit that communicates with the client apparatus and the second client apparatus using the individual key.

US Pat. No. 9,292,239

MAINTENANCE METHOD AND MAINTENANCE APPARATUS OF INFORMATION PROCESSING APPARATUS

Kabushiki Kaisha Toshiba,...

1. A maintenance method of an information processing apparatus, comprising:
acquiring a machine information including an identification information identifying a machine of the information processing
apparatus, a group name classifying the machine as an isolated group and a setting value information as value set in each
multiple setting items of the machine through an external storage apparatus;

acquiring a statistical data including an average value or a mode value of each setting value of the multiple setting items
generated for each group based on the setting value information of multiple information processing apparatuses;

comparing the machine information with the statistical data according to each setting item whose group name matches, and generating
an outlier information as an evaluation information denoting the propriety of the setting value of the machine when the setting
value information of the machine is excluded in a given threshold value for the average value or the mode value of the statistical
data; and

displaying the outlier information with the average value or the mode value from a display processing unit on a display unit.

US Pat. No. 9,219,227

MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY

KABUSHIKI KAISHA TOSHIBA,...

1. A magnetoresistive element comprising:
a first magnetic layer including MnxGa100-x (45?x<64 atomic %);

a second magnetic layer including MnyGa100-y (45?y<64 atomic %);

a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer; and
an interfacial layer provided between the first magnetic layer and the first nonmagnetic layer, and/or between the second
magnetic layer and the first nonmagnetic layer, the interfacial layer comprising a Heusler alloy including Mn,

the first and second magnetic layers comprising different Mn composition rates from each other, the first magnetic layer having
a smaller Mn concentration than the second magnetic layer, a magnetization direction of the first magnetic layer being changeable
and a magnetization direction of the second magnetic layer being unchangeable.

US Pat. No. 9,129,677

MEMORY DEVICE AND METHOD OF CONTROLLING MEMORY DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A memory device comprising:
a plurality of global column lines arranged in parallel and extending in a first direction;
a plurality of row lines extending in a second direction which is perpendicular to the first direction;
a plurality of column lines in a two-dimensional arrangement, which extend in a third direction which is perpendicular to
the first direction and the second direction;

a memory cell array including a plurality of memory cells each including a resistance change material, the memory cells being
arranged at intersections between the row lines and the column lines;

a plurality of sheet selectors disposed between the global column lines and the column lines; and
a controller configured to control the global column lines, the row lines, the column lines, the memory cells and the sheet
selectors,

the plurality of sheet selectors comprising:
a first transistor including a channel region, a first insulation layer formed on a first side surface of the channel region,
and a first select gate line extending in the second direction and formed on the first insulation layer in the first direction;
and

a second transistor including a channel region, a second insulation layer formed on a second side surface of the channel region,
which is opposed to the first side surface in the first direction, and a second select gate line extending in the second direction
and formed on the second insulation layer in the first direction, and

the controller being configured, at a time of storing or easing data in the memory cell array, to execute:
select a global column line, a row line and a select gate line in order to select the memory cells;
apply a select row line voltage to a selected row line of the plurality of row lines;
apply a non-select row line voltage to a non-selected row line of the plurality of row lines;
apply a select global column line voltage to a selected global column line of the plurality of global column lines;
apply a first non-select global column line voltage to a non-selected global column line of the plurality of global column
lines;

apply a non-select selector voltage to the first and second select gate lines;
apply a first select selector voltage to the first select gate line of the first transistor of a selected sheet selector of
the plurality of sheet selectors; and

apply, after passage of a first time after the applying of the first select selector voltage, a second select selector voltage
to the second select gate line of the selected sheet selector.

US Pat. No. 9,391,086

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Kabushiki Kaisha Toshiba,...

1. A method of manufacturing a nonvolatile semiconductor memory device, the method comprising:
forming a stacked body by alternately stacking a spacer film and a sacrificial film each in a plurality of layers;
forming a memory hole penetrating the stacked body in a stacked direction by etching;
forming an inter-electrode insulating film, a charge accumulation film, a tunnel insulating film, and a channel semiconductor
film in this order on a side surface of the memory hole;

forming a slit extending in a first direction in the stacked body, the slit dividing the stacked body in a second direction
intersecting with the first direction;

supplying a first etchant through the slit to remove each sacrificial film; and
embedding an electrode film into each gap space formed by removing each sacrificial film,
wherein the sacrificial film is made of a material that has a selective ratio relative to the spacer film and has reactivity
to a second etchant used etching the stacked body.

US Pat. No. 9,244,396

IMAGE FORMING APPARATUS AND CONVEYANCE SPEED CONTROL METHOD OF RECORDING MEDIUM IN IMAGE FORMING APPARATUS

Kabushiki Kaisha Toshiba,...

1. An image forming apparatus, comprising:
a transfer device configured to transfer an image onto a conveyed recording medium;
a fixer configured to heat, press and convey the recording medium to fix the transferred image on the recording medium;
a sensor configured to detect the bending amount of the recording medium between the transfer device and the fixer, the sensor
is non-contacted with the recording medium, and arranged towards a side of the recording medium on which the transferred image
is fixed; and

a control section configured to control at least one of the transfer device and the fixer so that the recording medium between
the transfer device and the fixer is conveyed in a bent state and the bending amount of the recording medium is reduced if
the bending amount of the recording medium exceeds a preset one according to the detection result of the sensor.

US Pat. No. 9,250,221

STANDARD SAMPLE AND METHOD OF PREPARING SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A method of preparing a standard sample, the method comprising:
forming a second layer containing an analysis target element on an entirety of an upper surface of a first layer which is
formed on a substrate;

dissolving the first and second layers to form a plurality of droplets containing the analysis target element on the substrate;
and

drying the droplets to form a plurality of particles containing the analysis target element on the substrate.

US Pat. No. 9,177,582

MAGNETIC DISK APPARATUS AND OFF-TRACKING DETECTION METHOD

Kabushiki Kaisha Toshiba,...

1. A disk apparatus comprising:
a first medium having a first disk surface on which first servo patterns are recorded, wherein the first servo patterns are
to be read at a first timing and data is to be wrote on the first disk surface by using a first head;

a second medium having a second disk surface on which second servo patterns are recorded, wherein the second servo patterns
are to be read at a second timing different from the first timing by using a second head; and

a controller to control the first head based on a first demodulated position and a control target position, the first demodulated
position being obtained by demodulating the first servo pattern, wherein

the controller
calculates a first estimated demodulated position from the first demodulated position and a first demodulated velocity based
on the first servo patterns,

calculates a second estimated demodulated position from the first demodulated position and a second demodulated velocity based
on the second servo patterns, each of the second servo patterns being read after reading each of the first servo pattern,
and

stops data writing operation of the first head in accordance with one of the first and second estimated demodulated positions
exceeding a particular threshold.

US Pat. No. 9,451,930

ULTRASONIC DIAGNOSIS APPARATUS, ULTRASONIC IMAGE PROCESSING APPARATUS, AND RECORDING MEDIUM ON WHICH ULTRASONIC IMAGE PROCESSING PROGRAM IS RECORDED

KABUSHIKI KAISHA TOSHIBA,...

1. An ultrasonic diagnosis apparatus, comprising:
a computer implemented by processing circuitry configured to acquire ultrasonic image data corresponding to a plurality of
time phases in a first period, including at least one contraction and one expansion, by ultrasonic scanning throughout the
first period for an observation region of an object to be examined, the observation region repeating contracting motion and
expanding motion upon application of a dynamic load including repetition of compression and release, generate velocity information
concerning a tissue in the observation region in the plurality of time phases in the first period, generate reference information
including a graphic chart of velocity of the observation region with time over a plurality of cycles, each of which includes
the contracting motion and the expanding motion, determine a second period corresponding to at least one of the contraction
motion and the expansion motion, in a period including at least part of the compression and the release, based on the reference
information, execute time integration with respect to the velocity information in the second period to generate strain information
concerning the tissue corresponding to a second plurality of time phases in the second period, and generate, based on the
strain information, a strain image indicating a strain distribution of the observation region; and

a display configured to display the strain image in a predetermined form.

US Pat. No. 9,246,014

NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR OPERATING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT

KABUSHIKI KAISHA TOSHIBA,...

1. A nonvolatile semiconductor memory element comprising:
a semiconductor film;
a lower insulating film that is disposed on the semiconductor film;
a conductive charge storage film that is disposed on the lower insulating film;
an upper insulating film that is disposed on the conductive charge storage film and that has a four-or-more-layer structure;
and

a control gate that is disposed on the upper insulating film;
wherein the upper insulating film includes:
a first insulating film that is disposed on the conductive charge storage film;
a second insulating film that is disposed on the first insulating film; and
a third insulating film that is disposed on the second insulating film;
wherein a thickness of the first insulating film is less than a thickness of the third insulating film, and
wherein the second insulating film is formed to have a trap level density larger than that of the third insulating film.

US Pat. No. 9,293,552

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A nonvolatile semiconductor memory device, comprising:
a memory cell array configured as an arrangement of memory cells, each memory cell holding data in a nonvolatile manner; and
a transfer transistor configured to transfer a certain voltage to a gate of the memory cell,
the transfer transistor comprising:
a pair of first diffusion regions formed in a surface of a semiconductor substrate;
a gate electrode layer formed, via a gate insulating layer, on the semiconductor substrate sandwiched by the pair of first
diffusion regions; and

a pair of first conductive layers each formed, via a first insulating layer, on the pair of first diffusion regions.

US Pat. No. 9,285,264

VIBRATION MEASURING APPARATUS FOR NUCLEAR REACTOR INTERNAL STRUCTURE AND VIBRATION MEASUREMENT METHOD THEREFOR

KABUSHIKI KAISHA TOSHIBA,...

1. A vibration measuring apparatus comprising: a holder comprising an interior space and an opening, the holder being formed
with a slot to at least a portion of a circumferential edge of the opening and retaining a bonding agent for bonding the holder
on the surface of the pressure vessel, the opening being configured to closely contact with a surface of a pressure vessel
of a nuclear reactor without a gap therebetween; a vibrator configured to be provided in the interior space of the holder,
the vibrator comprising an end side and a transmitting/receiving side opposite to the end side, wherein the transmitting/receiving
side of the vibrator is configured to transmit or receive an ultrasonic wave; a bias component configured to be provided in
the interior space between the holder and the end side of the vibrator, the bias component being configured to apply a biasing
force to the vibrator in a direction of to the transmittinq/receiving side from the end side; and a metal couplant configured
to be filled in the interior space of the holder between the transmitting/receiving of the vibrator and the opening of holder,
wherein the metal couplant at a first temperature is configured to be filled in the interior space in a solid state and at
a second temperature greater than the first temperature is configured to be in a liquid state when heated to the second temperature
by heat transferred to the metal couplant via the opening.

US Pat. No. 9,263,534

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:
a semiconductor substrate having a recess extending from a back surface of the semiconductor substrate in a depth direction
to a recessed surface at a recessed depth, the recess being adjacent to an unrecessed portion of the semiconductor substrate;
and

a metal film provided on the back surface of the semiconductor substrate on the unrecessed portion and on the recessed surface,
wherein,

a width of the recess at a first depth between the back surface and the recessed surface is greater than a width of the recess
at the back surface.

US Pat. No. 9,349,375

APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT FOR SEPARATING TIME SERIES SIGNALS

Inter-University Research...

1. A signal processing apparatus comprising:
an estimation unit configured to estimate an auxiliary variable of a processing target section including a first section of
an input signal where a time length is not zero and a second section different from the first section by using an approximating
auxiliary function for approximating an auxiliary function which has an auxiliary variable as an argument, the auxiliary function
being determined according to an objective function that outputs a function value that is smaller as a statistical independence
of a plurality of separated signals into which a plurality of input signals in time-series are separated by a demixing matrix
is higher, the auxiliary function being capable of calculating the demixing matrix that reduces a function value of the objective
function by alternately performing minimization of a function value regarding the auxiliary variable and minimization of a
function value regarding the demixing matrix, the estimation unit estimating a value of the auxiliary variable of the processing
target section based on the auxiliary variable previously estimated using the input signal in the first section and the input
signal in the second section, the processing target section being a section to which the minimization of the function value
regarding the auxiliary variable or the minimization of the function value regarding the demixing matrix is performed;

an updating unit configured to update the demixing matrix such that a function value of the approximating auxiliary function
is minimized based on the value of the estimated auxiliary variable and the demixing matrix; and

a generation unit configured to generate the separated signals by separating the input signals using the updated demixing
matrix, wherein

the input signals are signals that are sequentially input,
the first section is a section including the input signal which is input in advance, and
the second section is a section including the input signal which is currently input.

US Pat. No. 9,095,258

X-RAY IMAGING APPARATUS AND PROGRAM

KABUSHIKI KAISHA TOSHIBA,...

1. An X-ray imaging apparatus for performing X-ray imaging of an object and acquiring an X-ray fluoroscopic image, comprising:
an X-ray generation unit configured to irradiate the object with X-rays;
an X-ray collimator configured to limit an X-ray irradiation range of the X-ray generation unit;
a dose detection unit configured to detect the X-rays that have passed through the X-ray collimator;
a dose reduction rate calculation unit configured to calculate a reduction rate of an exposure dose of the object based on
a value detected by the dose detection unit in X-ray imaging before the X-ray irradiation range is limited by the X-ray collimator
and a value detected by the dose detection unit in X-ray imaging after the X-ray irradiation range is limited by the X-ray
collimator;

a display unit configured to display a graph based on the reduction rate,
wherein the display unit displays at least one of a full field imaging expected cumulative value graph and a limited field
imaging expected cumulative value graph as the graph, the full field imaging expected cumulative value graph representing
time-rate change in a cumulative value of the exposure dose when assuming that X-ray imaging is performed without limitation
of the X-ray irradiation range by the X-ray collimator from a current point, and the limited field imaging expected cumulative
value graph representing time-rate change in a cumulative value of the exposure dose when assuming that X-ray imaging is performed
with limitation of the X-ray irradiation range by the X-ray collimator from the current point.

US Pat. No. 9,104,379

ELECTRONIC APPARATUS

Kabushiki Kaisha Toshiba,...

1. An electronic apparatus comprising:
a first wall;
a second wall facing the first wall;
a moving portion between the first wall and the second wall, configured to move along the first wall and the second wall;
a flexible cable comprising an arcuate curving portion between the first wall and the second wall, a first portion which is
continuous from one of end portions of the arcuate curving portion, fixed on the moving portion, and brought into contact
with the first wall, and a second portion which is continuous from the other end portion of the arcuate curving portion, fixed
on the second wall, and brought into contact with the second wall, the flexible cable being moved such that the first portion
becomes longer and the second portion becomes shorter, or such that the first portion becomes shorter and the second portion
becomes longer, due to the movement of the moving portion; and

a first contact portion on the first wall and in contact with the first portion of the flexible cable, on which the flexible
cable slides more smoothly than on the second wall.

US Pat. No. 9,258,557

RATE OPTIMIZATION FOR SCALABLE VIDEO TRANSMISSION

Kabushiki Kaisha Toshiba,...

1. A method of processing a source data item to produce a transmission data item for transmission on a communications channel,
the transmission data item bearing information defining a playback content item, the method comprising:
encoding information defining a source data item into a plurality of layer data items, including a base layer item and an
enhancement layer item, the base layer item defining a playback content item corresponding to said source data item at a first
quality level and the enhancement layer item providing information to define, with said base layer, a playback content item
corresponding to said source item at a quality level higher than the first quality level, the encoding comprising determining
a plurality of rate values defining transmission rates corresponding, respectively, to transmission of said base layer item
alone or said base layer item and said enhancement layer item, on the basis of a prevailing channel condition of the communications
channel, and producing an encoded base layer item and an encoded enhancement layer item on the basis of said determined rate
values by maximizing a weighted sum of probabilities of transmitting at specific rates;

extracting, from said encoded layer items, a set of encoded layer items for transmission, the extracting being on the basis
of current channel information for the communications channel; and

assembling said extracted encoded layer items into a data sequence for transmission.

US Pat. No. 9,291,961

FIXING APPARATUS AND IMAGE FORMING APPARATUS HAVING THE SAME

Kabushiki Kaisha Toshiba,...

1. A fixing apparatus comprising: a rotating member;
a fixing member including a lamination of a resin layer and a conductive layer, a sheet having an unfixed image being conveyed
between the rotating member and the fixing member;

a heating unit configured to cause heating of the fixing member;
a support for one of the rotating member and the fixing member that is movable to change a positional state of the rotating
member with respect to the fixing member, the positional state including a contact state in which the rotating member is in
contact with the fixing member and a separate state in which the rotating member is apart from the fixing member;

a sensor configured to detect a temperature of the fixing member; and
a controller configured to cause the fixing apparatus to transition from a non-fixing state to a fixing state by,
if the detected temperature is lower than a first predetermined temperature, turning on the heating unit while the positional
state is in the contact state, and if the detected temperature is higher than the first predetermined temperature, turning
on the heating unit while the positional state is in the separate state and then controlling the support to change the positional
state from the separate state to the contact state when the detected temperature reaches a second predetermined temperature
that is higher than the first predetermined temperature.

US Pat. No. 9,291,725

RANDOM COINCIDENCE REDUCTION IN POSITRON EMISSION TOMOGRAPHY USING TANGENTIAL TIME-OF-FLIGHT MASK

Kabushiki Kaisha Toshiba,...

1. A method of reducing random events in positron emission tomography (PET) list mode data, the method comprising:
obtaining, for a PET scanner having a given reconstruction field of view (FOV), time-of-flight (TOF) prompt list-mode count
data that includes TOF information, the TOF prompt list-mode count data including a plurality of entries;

filtering the obtained prompt list-mode count data by removing those entries in the obtained prompt list-mode count data that
represent emission points lying outside a tangential TOF mask to obtain filtered list-mode count data; and

performing reconstruction on the filtered list-mode count data to generate a PET image.

US Pat. No. 9,294,052

PERSONAL COMPUTER TO OUTPUT AUDIO IN A NON-OPERATIVE STATE

Kabushiki Kaisha Toshiba,...

1. An electronic apparatus comprising:
a terminal configured to receive an audio signal from an external device;
an amplifier configured to amplify the audio signal;
a speaker configured to output sound corresponding to the audio signal which is amplified by the amplifier;
a power supply circuit configured to supply power to the amplifier;
a processor configured to select either enabling or disabling of a first mode, and to store data indicative of whether the
first mode is enabled or disabled, the first mode being a mode in which audio output is permitted when the electronic apparatus
is in a non-operative state, wherein the selection is performed in accordance with a user operation, and wherein the user
operation is performed when the electronic apparatus is in an operative state;

a switching circuit configured to switch between a first path which connects the terminal and the amplifier and a second path
which connects the terminal and the amplifier via a second controller configured to operate when the electronic apparatus
is in the operative state; and

a first controller configured to determine whether the data indicative of the enabling of the first mode is stored, when the
electronic apparatus is instructed to power off the apparatus,

wherein the first controller is configured to control the power supply circuit to continue supplying power to the amplifier
during the non-operative state of the electronic apparatus, and to switch the switching circuit to the first path, if the
data indicative of the enabling of the first mode is stored.

US Pat. No. 9,213,075

APPARATUS AND METHOD FOR MAGNETIC RESONANCE IMAGING

KABUSHIKI KAISHA TOSHIBA,...

1. A magnetic resonance imaging apparatus comprising:
a sequence controlling unit configured to, by controlling an execution of a pulse sequence, acquire magnetic resonance signals
corresponding to a plurality of channels in the pulse sequence executed as a series, the magnetic resonance signals being
configured to be arranged into a first region of a k-space so as to be positioned at first intervals and into a second region
larger than the first region so as to be positioned at second intervals larger than the first intervals;

an arranging unit configured to arrange the magnetic resonance signals corresponding to the plurality of channels into the
k-space as k-space data; and

an image generating unit configured to generate k-space data at the first intervals corresponding to the plurality of channels
based on the k-space data at the second intervals acquired by the execution of the pulse sequence and generate a magnetic
resonance image based on the generated k-space data at the first intervals, the k-space data at the first intervals acquired
by the execution of the pulse sequence, and sensitivity distributions corresponding to the plurality of channels.

US Pat. No. 9,397,167

NITRIDE SEMICONDUCTOR WAFER, NITRIDE SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR WAFER

Kabushiki Kaisha Toshiba,...

1. A nitride semiconductor device comprising:
a silicon substrate having a major surface;
a stacked multilayer unit formed on the major surface of the silicon substrate, the stacked multilayer unit including N number
of buffer layers stacked in a stacking direction perpendicular to the major surface, the buffer layers including a nitride
semiconductor, N being not less than two and not more than nine, the buffer layers including an i-th buffer layer (i being
an integer of 1 or more and less than N), and an (i+1)-th buffer layer provided on the i-th buffer layer, the (i+1)-th buffer
layer being in contact with the i-th buffer layer, the i-th buffer layer having an i-th lattice length Wi in a first direction
parallel to the major surface, the (i+1)-th buffer layer having an (i+1)-th lattice length W(i+1) in the first direction,
and a relation that 0.003?(W(i+1)?Wi)/Wi?0.008 being satisfied for all the buffer layers;

a silicon-containing unit provided on the stacked multilayer unit and containing silicon, the silicon-containing unit being
in contact with the stacked multilayer unit;

an upper layer unit provided on the silicon-containing unit and including a nitride semiconductor
wherein
the upper layer unit includes
an upper buffer layer provided on the silicon-containing unit and including a nitride semiconductor, and
a functional layer provided on the upper buffer layer and including a nitride semiconductor,
the functional layer includes an impurity-containing layer containing an impurity, and
an impurity concentration in the impurity-containing layer is higher than an impurity concentration in the upper buffer layer,
the upper layer unit further includes an intermediate layer provided between the upper buffer layer and the functional layer,
the intermediate layer includes
a first layer including a nitride semiconductor containing Al, and
a second layer provided on the first layer and including a nitride semiconductor,
an Al composition ratio of the second layer is lower than an Al composition of the first layer,
the intermediate layer further includes a third layer including a nitride semiconductor including Al and provided between
the first layer and the second layer, and

an Al composition ratio of the third layer is lower than the Al composition ratio of the first layer and higher than the Al
composition ratio of the second layer.

US Pat. No. 9,134,924

SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES TO ALLOCATE BLOCKS TO A MEMORY AND RELEASE ALLOCATED BLOCKS

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor storage device comprising:
an interface configured to receive data from an external host apparatus;
a first memory configured to store the data by a first unit or less, the first unit being an access unit from the external
host apparatus;

a nonvolatile memory configured to store the data transmitted from the interface via the first memory; and
a controller configured to:
allocate a plurality of blocks to a first memory area in the nonvolatile memory, each plurality of blocks being a unit of
data erasing, the plurality of blocks allocated to the first memory area including SLC (Single Level Cell) blocks;

allocate at least one of the SLC blocks to a second memory area in the nonvolatile memory from the first memory area, a plurality
of blocks allocated to the second memory area including SLC blocks and MLC (Multi Level Cell) blocks;

store a plurality of data in the first memory by the first unit;
store data outputted from the first memory in the SLC block in the first memory area by a first management unit, the first
management unit being twice or larger natural number times as large as the first unit and being less than the unit of data
erasing;

copy valid data stored in the SLC blocks to one of the MLC blocks when a first condition is satisfied; and
release at least one of the SLC blocks in which no valid data is stored from the second memory area, after copying the valid
data stored in the SLC blocks.

US Pat. No. 9,144,879

PLANARIZATION METHOD AND PLANARIZATION APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. A planarization method comprising:
planarizing a work surface of a work piece by bringing the work surface of the work piece containing a silicon oxide film
and a surface of a solid plate onto which hydrogen ions are adsorbed, the solid plate containing a solid acidic catalyst,
into contact or extremely close proximity with one another in a state in which a process liquid containing fluorine ions is
supplied to the surface of the solid plate,

wherein the catalyst is an acidic cation exchanger having a functioning group with an acid dissociation constant of 1.0×10?3 or less.

US Pat. No. 9,530,480

SEMICONDUCTOR MEMORY DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A method of controlling a magnetoresistive random access memory, comprising:
receiving an active command through command/address pins at a rising edge and a falling edge of a clock signal, the active
command specifying a first set of row addresses;

receiving a read command, after receiving the active command, through the command/address pins at a rising edge and a falling
edge of the clock signal, the read command specifying column addresses and a second set of row addresses;

reading data from at least one of memory cells, in response to receiving the read command, according to the first set of row
addresses and the second set of row addresses associated with the read command;

receiving a write command through the command/address pins at a rising edge and a falling edge of the clock signal, while
reading the data from the at least one of memory cells, the write command specifying column addresses and a second set of
row addresses;

outputting the data read from the at least one of memory cells to data input/output pins, according to the column addresses
associated with the read command, after a lapse of a predetermined read latency from receiving the read command;

receiving data through the data input/output pins, according to the column addresses associated with the write command, after
a lapse of a predetermined write latency from receiving the write command; and

writing the data inputted from the data input/output pins to at least one of memory cells according to the first set of row
addresses and the second set of row addresses associated with the write command.

US Pat. No. 9,357,644

JOINED STRUCTURAL BODY OF MEMBERS, JOINING METHOD OF MEMBERS, AND PACKAGE FOR CONTAINING AN ELECTRONIC COMPONENT

KABUSHIKI KAISHA TOSHIBA,...

1. A package containing an electronic component, comprising:
a substrate on which an electronic component is mounted;
a frame body which surrounds a portion on which the electronic component is mounted, the frame body being joined mechanically
with the substrate via a joining portion containing (1) at least one metal of a tin, an indium, or a zinc, and (2) a copper:
and

feed through terminals for inputting a signal into the electronic component and for outputting a signal from the electronic
component respectively,

wherein content of the at least one metal in the joining portion decreases toward a side of at least one of the substrate
or the frame body, and content of the copper in the joining portion increases in a same direction as the decreasing direction
of the content of the at least one metal, and

wherein the joining portion includes a first joining portion and a second joining portion, and the substrate and the feed
through terminals are joined together via the first joining portion, and the frame body and the feed through terminals are
joined together via the second joining portion.

US Pat. No. 9,284,156

PAPER SHEET HANDLING APPARATUS

Kabushiki Kaisha Toshiba,...

1. A paper sheet handling apparatus comprising:
a supply unit comprising a support surface which tilts from a vertical direction, and a mounting surface substantially perpendicular
to the support surface, and configured to receive a plurality of paper sheets which tilt along the support surface and are
stacked on the mounting surface;

a pick up mechanism configured to pick up the paper sheets from a mounting surface side of the supply unit;
a conveyance path configured to convey the picked up paper sheet;
an inspection device configured to inspect the conveyed paper sheet and arranged above the pick up mechanism in the vertical
direction; and

an accumulation unit configured to accumulate the inspected paper sheets,
wherein the conveyance path tilts from the pick up mechanism to the inspection device obliquely from the vertical direction
and extends upward from the pick up mechanism along the support surface in an area under the support surface, and the inspection
device obliquely tilts along the conveyance path.

US Pat. No. 9,287,288

SEMICONDUCTOR MEMORY DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor memory device comprising:
a substrate;
a stacked body provided above the substrate, the stacked body being including a plurality of electrode layers and a plurality
of insulating layers each provided between adjacent ones of the electrode layers; and

a columnar portion penetrating through the stacked body and extending in a stacking direction of the stacked body,
the columnar portion including:
a channel body extending in the stacking direction;
a charge storage film provided between the channel body and the electrode layer; and
a gap provided between the charge storage film and the electrode layer and
a first insulating film provided between the charge storage film and the electrode layer; the insulating film overlapping
a part of the electrode layer and a part of the gap when viewed along a first direction parallel to a surface of the substrate.

US Pat. No. 9,345,134

PRINTED WIRING BOARD

Kabushiki Kaisha Toshiba,...

1. A printed wiring board, comprising:
a circuit board having a first surface;
a ground pattern provided on the first surface of the circuit board;
a wiring pattern provided on the first surface of the circuit board, through which a signal or power is to be supplied, the
wiring pattern including a first pattern disposed between the ground pattern and a first edge of the circuit board, and a
second pattern disposed separately from the first pattern and between the ground pattern and a second edge of the circuit
board that is different from the first edge;

a conductive reinforcing plate covering the ground pattern and the wiring pattern, and electrically connected with the ground
pattern; and

an insulating adhesive member provided between the conductive reinforcing plate and the wiring pattern, and adhesively bonding
the circuit board and the conductive reinforcing plate.

US Pat. No. 9,322,881

PARTIAL DISCHARGE MEASUREMENT SYSTEM AND PARTIAL DISCHARGE MEASUREMENT METHOD BY REPEATED IMPULSE VOLTAGE

TOSHIBA MITSUBISHI-ELECTR...

1. A partial discharge measurement system based on repeated impulse voltage, the system comprising:
a DC power supply that outputs high voltage as a voltage obtained by multiplying an instruction voltage by a set factor;
a signal generator that generates a pulse signal representing a predetermined pulse width and a predetermined pulse repetition
frequency, and superimposes a period setting signal whose one period includes a pulse supply period and a pulse pause period
following the pulse supply period and the pulse signal on each other to generate a rectangular waveform signal in which a
predetermined number of the pulse signals are generated only in the pulse supply period;

a semiconductor switch that charges a capacitive element with the high voltage from the DC power supply when a voltage value
of the rectangular waveform signal is lower than a preset voltage threshold, while applies an impulse voltage having a peak
value equal to a value of the high voltage from the capacitive element to an object to be measured when the voltage value
of the rectangular waveform signal is equal to or higher than the voltage threshold;

a signal instruction section that outputs, to the signal generator, a square wave instruction signal in which the predetermined
pulse width, the predetermined pulse repetition frequency, and the predetermined number are set;

a voltage instruction section that outputs, to the DC power supply, a voltage instruction signal in which an initial voltage
is set as the instruction voltage in a first period of the rectangular waveform signal and sets in the voltage instruction
signal, in second and subsequent periods, a voltage obtained by adding a predetermined increment voltage lower than the initial
voltage to the instruction voltage in the immediately previous period as the instruction voltage;

a detection signal observation circuit that observes a detection signal based on a partial discharge generated in the object
to be measured to which the impulse voltages are applied;

a partial discharge frequency calculation section that counts the number of inputs of the detection signal on a per period
basis as a partial discharge frequency;

an application voltage signal observation circuit that observes an application voltage signal representing the impulse voltage
to be applied to the object to be measured; and

a voltage value acquiring section that sets, in a period in which the partial discharge frequency first becomes equal to or
more than a specified frequency, a peak value of a voltage represented by the application voltage signal from the application
voltage observation circuit as a partial discharge starting voltage.

US Pat. No. 9,157,870

PATTERN TEST APPARATUS

NuFlare Technology, Inc.,...

1. A pattern test apparatus which tests pattern defects by using a pattern image obtained by applying light to a test sample,
comprising:
a light source configured to apply test light of a predetermined wavelength to the test sample;
a polarizing beam splitter which reflects the light from the light source, and guides the light onto the test sample;
an imaging device which receives light which has been reflected by the test sample and reflected by the polarizing beam splitter;
an optical system which forms a Fourier transform plane of the test sample between the test sample and the polarizing beam
splitter; and

a polarizing controller disposed in the Fourier transform plane, the polarizing controller including a first region which
lets the test light through, and a second region which has an area greater than that of the first region and lets the light
reflected by the test sample through, the first region and the second region having different retardation quantities.

US Pat. No. 9,750,133

PRINTED CIRCUIT BOARD

Kabushiki Kaisha Toshiba,...

1. A printed circuit board comprising
a substrate having a trench between a first region and a second region, the first region being a region where a first package
is to be mounted, the second region being a region where a second package is to be mounted,

wherein the substrate has a first main surface and a second main surface, the first main surface being a surface on which
the first package is placed, the second main surface being positioned on a reverse side of the first main surface of the substrate,

the trench has an opening portion in the second main surface,
a depth of the trench from the second main surface is greater than half of a thickness of the substrate,
the trench does not reach the first main surface,
the substrate includes a conductor layer positioned near the first main surface and via which terminals of the first package
and terminals of the second package are electrically connected, and

the trench does not penetrate the conductor layer.

US Pat. No. 9,197,201

IMPULSE VOLTAGE GENERATION DEVICE

TOSHIBA MITSUBISHI-ELECTR...

1. An impulse voltage generation device comprising:
a high voltage generator for generating a high voltage;
a capacitive element;
a signal generator for generating a combined signal that is generated only in a period where supply of a pulse signal is effected
by superimposing a period setting signal whereof one cycle includes a pulse supply period and a pulse idling period subsequent
to the pulse supply period on a pulse signal whose frequency is an impulse repetition frequency higher than the frequency
of the period setting signal and whose amplitude represents a voltage value that is lower than the high voltage value; and

a semiconductor switch for accumulating electric charge on the capacitive element by means of the high voltage from the high
voltage generator when the voltage value of the combined signal is lower than the set gate voltage value, generating an impulse
voltage whose peak value is the value of the high voltage by means of the electric charge that is discharged from the capacitive
element when the voltage value of the combined signal exceeds the set gate voltage value and supplying the impulse voltage
between the first output terminal and the second output terminal where a load is provided.

US Pat. No. 9,357,643

CERAMIC/COPPER CIRCUIT BOARD AND SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A ceramic/copper circuit board comprising:
a ceramic substrate having a first surface and a second surface;
a first copper plate bonded to the first surface of the ceramic substrate via a first bonding layer containing at least one
active metal element selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), and
niobium (Nb) and at least one element selected from the group consisting of silver (Ag), copper (Cu), tin (Sn), indium (In),
and carbon (C); and

a second copper plate bonded to the second surface of the ceramic substrate via a second bonding layer containing at least
one active metal element selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al),
and niobium (Nb) and at least one element selected from the group consisting of silver (Ag), copper (Cu), tin (Sn), indium
(In), and carbon (C),

wherein each of end portions of the first and second copper plates has a shape in which a ratio (C/D) of an area C in relation
to an area D is from 0.2 to 0.6, wherein in cross sections of the end portions of the first and second copper plates, a point
A is a bonding edge of the copper plate and the ceramic substrate, a point B is a point where a straight line drawn from the
point A toward an inner side of an upper surface of the copper plate in a direction of 45° in relation to an interface of
the copper plate and the ceramic substrate intersects with the upper surface of the copper plate, a line AB is a straight
line connecting the point A and the point B, the area C is a cross section area of a portion protruded from the line AB toward
an outer side direction of the copper plate, and the area D is a cross section area of a portion corresponding to a right-angled
triangle whose hypotenuse is the line AB,

wherein R-shape sections are provided at edges of the upper surfaces of the first and second copper plates corresponding to
a corner portion of the area C, and each of lengths F of the R-shape sections viewed from the above of the first and second
copper plates is 10 ?m or more and 100 ?m or less, and

wherein end portions of the first and second bonding layers are protruded from the end portions of the first and second copper
plates, respectively, and each of lengths E of the end portions of the first and second bonding layers protruded from the
end portions of the first and second copper plates is from 10 ?m to 150 ?m.

US Pat. No. 9,455,053

SIC MATRIX FUEL CLADDING TUBE WITH SPARK PLASMA SINTERED END PLUGS

Westinghouse Electric Com...

1. A method of hermetically sealing at least one end cap to a nuclear reactor fuel rod cladding tube, the tube being formed
from a ceramic composite comprising:
(1) providing a tube formed from a ceramic composite, the tube having tube walls, at least one open end, and a circumferential
axis, and providing at least one end cap, the end cap having an exterior side and an interior side;

(2) applying the at least one end cap to the at least one open end of the tube to define an interface between a portion of
the end cap and the tube, wherein the at least one end cap is made from a material selected from the group consisting of multiple
layers of a SiC—SiC ceramic composite, a ternary carbide, and a ternary nitride;

(3) applying at least one primary electrode to the exterior side of the at least one end cap;
(4) applying current to the at least one electrode using a spark plasma sintering means to supply a rapid temperature rise
in the interface applied for 0.01 to 6.0 minutes at a rate of 200° C./min up to 1,500° C./min. where the temperatures at the
interface are from ambient to 2,500° C.

US Pat. No. 9,275,727

MULTI-LEVEL MEMORY ARRAY HAVING RESISTIVE ELEMENTS FOR MULTI-BIT DATA STORAGE

Intermolecular, Inc., Sa...

1. A device comprising:
a resistive switching memory element operable to switch between at least two resistive states,
a resistor array comprising multiple resistive elements; and
a multiplexer connected in series with the resistive switching memory element and the resistor array,
the multiplexer configured to selectively interconnect the multiple resistive elements in series to form different series
combinations having different resistances and to connect each of the multiple resistive elements or each of the different
series combinations to the resistive switching memory element.

US Pat. No. 9,730,368

LEAKAGE PREVENTING DEVICE OF ELECTROMAGNETIC WAVE AND WIRELESS POWER TRANSMISSION SYSTEM

Kabushiki Kaisha Toshiba,...

1. A leak preventing device of electromagnetic wave comprising:
a metal pipe arranged to surround a periphery of a first electric power transmission device, the first electric power transmission
device wirelessly transmitting electric power to a second electric power transmission device via an electromagnetic wave,
the second electric power transmission device being opposed to the first electric power transmission device;

an opening formed on the metal pipe along a circumferential direction of the metal pipe; and
a magnetic material part arranged within the metal pipe along the circumferential direction the metal pipe.

US Pat. No. 9,423,356

ILLUMINATION APPARATUS AND INSPECTION APPARATUS

NuFlare Technology, Inc.,...

1. An illumination apparatus comprising:
a light source that emits a laser beam; and
two lens arrays to which the laser beam is illuminated,
a plurality of element lenses, each element lens having a diameter greater than or equal to that of the laser beam, arranged
in the lens arrays, the lens arrays being rotatable through an optical axis of the laser beam,

wherein the two lens arrays are arrayed in an optical axis direction of the laser beam, and
the element lenses in each lens array are arranged such that a boundary between the element lenses adjacent to each other
radiates from a rotation center of the lens array and such that a direction in which the element lens of one of the lens arrays
traverses the optical axis of the laser beam is orthogonal to a direction in which the element lens of the other lens array
traverses the optical axis of the laser beam.

US Pat. No. 9,178,148

RESISTIVE RANDOM ACCESS MEMORY CELL HAVING THREE OR MORE RESISTIVE STATES

Intermolecular, Inc., Sa...

1. A semiconductor device comprising:
a first layer operable as a first electrode;
a second layer operable as a second electrode; and
a third layer disposed between the first layer and the second layer,
wherein the third layer is operable to switch between a first resistive state corresponding to a first resistance and a second
resistive state corresponding to a second resistance different from the first resistance,

wherein the third layer comprises a first sub-layer, a second sub-layer, and a third sub-layer,
wherein the second sub-layer is disposed between the first sub-layer and the third sub-layer,
wherein the first sub-layer comprises titanium oxide and has a thickness of about 8 Angstroms,
wherein the second sub-layer comprises hafnium oxide and has a thickness of about 50 Angstroms, and
wherein the third sub-layer comprises silicon oxide and has a thickness of about 20 Angstroms.

US Pat. No. 9,335,680

IMAGE FORMING APPARATUS HAVING FIXING DEVICE THAT RESPONDS TO REQUEST WHEN USING DECOLORABLE INK

Kabushiki Kaisha Toshiba,...

1. An image forming apparatus comprising:
a first electrographic image forming unit configured to form a first image on a first recording medium with a first material
that is thermally non-decolorable;

a second electrographic image forming unit configured to form a second image on a second recording medium with a second material
that is thermally decolorable; and

a fixing unit which is on a common carrying path shared by the first recording medium and the second recording medium, which
is configured to fix the first image to the first recording medium and to fix the second image to the second recording medium;

wherein a temperature of the fixing unit for fixing the first image and a temperature of the fixing unit for fixing the second
image are lower than a decolorizing temperature of the second material.

US Pat. No. 9,299,928

NONVOLATILE MEMORY DEVICE HAVING A CURRENT LIMITING ELEMENT

Intermolecular, Inc., Sa...

1. A semiconductor device comprising:
a first layer operable as a first electrode;
a second layer operable as a second electrode;
a third layer disposed between the first layer and the second layer,
wherein the third layer is operable as a variable resistance layer; and
a fourth layer disposed between the first layer and the third layer,
wherein the fourth layer is a resistive layer,
wherein the fourth layer maintains a constant resistance during operation of the semiconductor device, and
wherein the fourth layer is directly interfacing the third layer;
a current steering device disposed between the first layer and the second layer, wherein the fourth layer is disposed between
the third layer and the current steering device;

wherein the current steering device has a first impedance, wherein the fourth layer has a second impedance being between about
75% and about 125% of the first impedance.

US Pat. No. 9,224,951

CURRENT-LIMITING ELECTRODES

Intermolecular, Inc., Sa...

1. A device comprising:
a first layer formed over a substrate,
wherein the first layer is operable as a first electrode;
a second layer formed over the first layer,
wherein the second layer is operable to reversibly change resistance between at least two stable states responsive to a write
signal;

a third layer formed over the second layer,
wherein the third layer is operable as a second electrode;
wherein the first layer or the third layer is a constant-resistance layer operable as a current-limiting electrode;
wherein the constant-resistance layer comprises a first portion and a second portion,
wherein the first portion comprises a compound nitride of a transition metal and an additional element;
wherein the second portion comprises a binary nitride;
wherein the second portion directly interfaces the second layer; and
wherein the additional element comprises at least one of aluminum, boron, or silicon.

US Pat. No. 9,699,891

SUBSTRATE AND METHOD FOR MOUNTING SEMICONDUCTOR PACKAGE

Kabushiki Kaisha Toshiba,...

1. A substrate comprising:
a join-structure including a semiconductor package, first electrode pad, bump, second electrode pad, and circuit substrate
joined in the order named; and

a first wire and a second wire formed in a region below a corner of the semiconductor package, each of the first wire and
the second wire having a low-strength structure,

wherein:
one of the first wire and the second wire is connected to the first electrode pad or the second electrode pad, and the one
of the first wire and the second wire is connected to a bump and a first measurement circuit for measuring a connection,

the other of the first wire and the second wire is not connected to any of the first electrode pad and the second electrode
pad and the other of the first wire and the second wire is connected to a circuit substrate and a second measurement circuit
that measures another connection across the other of the first wire and the second wire, and

a break strength of each of the first wire and the second wire is lower than a break strength of the join-structure between
the circuit substrate and the semiconductor package.

US Pat. No. 9,756,196

IMAGE PROCESSING APPARATUS AND SYSTEM AND METHOD FOR TRANSMITTING AN IMAGE

Kabushiki Kaisha Toshiba,...

1. An image processing apparatus comprising:
an image reading sensor configured to read an image from a sheet to generate image data;
a display device;
a communication interface; and
a processor configured to:
generate a code that can be scanned to determine an email address of the image processing apparatus,
control the display device to display the code so that a user can scan the code on the display device with a user terminal,
control the communication interface to receive an email transmitted from the user terminal that scanned the code to the email
address of the image processing apparatus,

based on the received email, identify the image data and the email address of the user terminal, and
control the communication interface to transmit an email, with the image data attached, to the identified email address of
the user terminal.

US Pat. No. 9,648,788

SERVER ROOM MANAGING AIR CONDITIONING SYSTEM

Kabushiki Kaisha Toshiba,...

1. A server room management air conditioning system in which the air conditioning system performs an air conditioning of the
server room in an all circulation mode in which outside air is not introduced but supplied air is manufactured by an action
of returned air and supplied to the server room, the server room management air conditioning system comprising:
a plurality of cooling coils which adjust the returned air of the server room;
an air supply fan which mixes the supplied air adjusted by the plurality of cooling coils to supply as the supplied air to
the server room;

a first control device which obtains an outside air temperature measurement value, an outside air humidity measurement value,
a supplied air temperature measurement value, a supplied air humidity measurement value, a supplied air volume, and a value
that indicates load states of servers in the server room, and based on the obtained values,

determines a number of the cooling coils among the plurality of cooling coils as first coils to be used for adjusting the
returned air of the server room to a predetermined temperature value lower than a predetermined supplied air temperature target
value to perform dehumidification,

determines a number of the cooling coils among the plurality of cooling coils as second coils to be used for adjusting the
returned air of the server to a predetermined temperature value higher than the supplied air temperature target value so as
to adjust the returned air of the server room to the supplied air temperature target value and a predetermined supplied air
humidity target value when the returned air is mixed with air adjusted by the first coils, and

determines cooling coils to be used as the first coils and cooling coils to be used as the second coils so that the first
coils are biased to specific cooling coils.

US Pat. No. 9,425,394

DOPED OXIDE DIELECTRICS FOR RESISTIVE RANDOM ACCESS MEMORY CELLS

Intermolecular, Inc., Sa...

1. A method of fabricating a memory cell, the method comprising:
forming a first layer using atomic layer deposition (ALD) or chemical vapor deposition (CVD),
wherein the first layer comprises a first dielectric material and a second dielectric material arranged into a nanolaminate
of sub-layers comprising the first dielectric material and sub-layers comprising the second dielectric material,

wherein a dielectric constant of the first dielectric material is less than a dielectric constant of the second dielectric
material,

wherein a concentration of the first dielectric material in the first layer is greater than a concentration of the second
dielectric material in the first layer;

annealing the first layer in a first environment comprising an oxygen source;
after annealing the first layer in the first environment, forming a second layer over the first layer,
wherein the second layer is operable as an electrode; and
annealing the first layer and the second layer in a second environment comprising a nitrogen source,
wherein, after annealing, distribution of the first dielectric material and distribution of the second dielectric material
within the first layer are both uniform,

wherein the memory cell is operable to switching between two resistive states when a switching signal is applied to the memory
cell.

US Pat. No. 9,795,049

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:
a base plate having a support surface;
a semiconductor chip provided on the support surface, the semiconductor chip including a switching element, the switching
element including a first electrode, a second electrode, and a control electrode;

a first terminal plate including a first main body unit, the first terminal plate being electrically connected to the first
electrode;

a second terminal plate including a second main body unit, the second main body unit opposing the first main body unit at
a first spacing from the first main body unit, the second terminal plate being electrically connected to the second electrode;

a third terminal plate including a third main body unit, the third main body unit opposing the first main body unit and the
second main body unit at prescribed spacings from the first main body unit and the second main body unit, the third terminal
plate being electrically connected to the first electrode and the first terminal plate; and

a fourth terminal plate including a fourth main body unit, the fourth main body unit opposing the third main body unit at
a second spacing from the third main body unit, the fourth terminal plate being electrically connected to the second electrode
and the second terminal plate,

the second spacing being narrower than the first spacing.
US Pat. No. 9,291,928

TONER CONTAINING AROMATIC MATERIALS AND METHOD OF FORMING AN IMAGE USING THE SAME

Kabushiki Kaisha Toshiba,...

1. A toner comprising:
toner particles, each containing binder resin and a plurality of microcapsules dispersed therein, each of the microcapsules
containing a liquid material.

US Pat. No. 9,664,071

STEAM TURBINE PLANT

KABUSHIKI KAISHA TOSHIBA,...

1. A steam turbine plant comprising:
a heater configured to change water into steam, the heater producing high pressure steam and low pressure steam having a lower
pressure than the high pressure steam by using heat from a single heat source;

a high pressure turbine having a first inlet to supply the high pressure steam, a second inlet to supply the low pressure
steam and located downstream of the first inlet, and an exhaust port located downstream of the second inlet, the high pressure
turbine being configured such that the high pressure steam supplied from the first inlet drives the high pressure turbine,
expands in the high pressure turbine, decreases in pressure, and is then merged with the low pressure steam supplied from
the second inlet in the high pressure turbine, and the merged high pressure steam and low pressure steam further drive the
high pressure turbine, expand in the high pressure turbine, decrease in pressure, and are then exhausted from the exhaust
port;

a reheater located downstream of the high pressure turbine and configured to heat the steam exhausted from the exhaust port;
and

a reheat turbine located downstream of the reheater and configured to be driven by the steam from the reheater.

US Pat. No. 9,349,590

METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER

Kabushiki Kaisha Toshiba,...

1. A method for manufacturing a nitride semiconductor layer, comprising:
forming a first lower layer of a nitride semiconductor on a major surface of a substrate and forming a first upper layer of
a nitride semiconductor on the first lower layer to form a first stacked body including the first lower layer and the first
upper layer, the first lower layer having a first lattice spacing along a first axis parallel to the major surface, the first
upper layer having a second lattice spacing along the first axis larger than the first lattice spacing, at least a part of
the first upper layer having a first compressive strain along the major surface,

an absolute value of a ratio of a difference between the second lattice spacing and the first lattice spacing to the first
lattice spacing being not less than 0.005 and not more than 0.019, and

the forming the first upper layer including
making a growth rate of the first upper layer in a direction parallel to the major surface larger than a growth rate of the
first upper layer in a direction perpendicular to the major surface, and

forming the first upper layer while applying the first compressive strain on the first upper layer, the first compressive
strain being based on the difference between the second lattice spacing and the first lattice spacing, wherein

the second lattice spacing of the first upper layer after formation of the first stacked body has a value between an unstrained
lattice constant of the first upper layer and an unstrained lattice constant of a first base layer located between the first
lower layer and the substrate.

US Pat. No. 9,285,731

FIXING DEVICE THAT FIXES IMAGES OF DECOLORABLE AND NON-DECOLORABLE MATERIALS

Kabushiki Kaisha Toshiba,...

1. A fixing device, comprising:
a roller;
a pressing member pressed against the roller, such that when a sheet having an unfixed image is passed through a nip formed
between the roller and the pressing member, the unfixed image is fixed on the sheet;

a first heater configured to heat the roller;
a second heater configured to heat the pressing member; and
a controller configured to control the second heater, such that a time-averaged heat generation by the second heater when
an image of a decolorable material is fixed is greater than a time-averaged heat generation by the second heater when an image
of a non-decolorable material is fixed.

US Pat. No. 9,392,717

DISPLAY DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A display device comprising:
a housing comprising an opening;
a display unit housed in the housing and comprising a first face and a second face, the first face including a display screen,
the second face being on an opposite side of the first face;

a circuit substrate housed in the housing and comprising a first side and a second side;
a plurality of connector terminals disposed at each of the first side and the second side of the circuit substrate, and exposed
through the opening; and

a cover member covering the opening across the first side and the second side of the circuit substrate, wherein
the cover member comprises a first portion arranged along the first side, a second portion arranged along the second side,
a linking portion positioned in between the first portion and the second portion, and a fixing piece,

the first portion includes a first facing portion and a first top wall, the first facing portion being arranged so as to oppose
to the first side and rising from the second face, the first top wall being connected to the first facing portion and being
arranged so as to substantially parallel the second face,

the second portion includes a second facing portion and a second top wall, the second facing portion being arranged so as
to oppose to the second side and rising from the second face, the second top wall being connected to the second facing portion
and being arranged so as to substantially parallel the second face,

the fixing piece is disposed on at least one of the first facing portion, the first top wall, the second facing portion, and
the second top wall, and

the fixing piece and the circuit substrate are fixed by a fixing member.

US Pat. No. 9,311,028

PRINT JOB MANAGEMENT APPARATUS

Kabushiki Kaisha Toshiba,...

1. A print job management apparatus comprising:
a communication unit configured to receive a plurality of print jobs and, for each print job, a data storage time which indicates
a period of time for storing the respective print job;

a storage unit configured to store the plurality of print jobs; and
a processor functioning as:
a holding condition managing unit that
controls the storage unit to store each received data storage time in correspondence with the respective print job,
determines whether the period of time for each print job has passed, and
removes from the storage unit each print job for which the corresponding period of time has passed, and
a print controlling unit that
receives a signal from an image forming apparatus designating one of the plurality of print jobs, and
transmits the designated print job to the image forming apparatus if the signal is received before the period of time corresponding
to the designated print job passes.

US Pat. No. 9,276,203

RESISTIVE SWITCHING LAYERS INCLUDING HF-AL-O

Intermolecular, Inc., Sa...

1. A resistive random access memory cell comprising:
a first layer operable as a first electrode;
a second layer operable as a second electrode; and
a third layer operable as a resistive switching layer and disposed between the first layer and the second layer,
wherein the third layer is operable to repeatedly switch between a first resistive state and a second resistive state when
switching voltages are applied between the first layer and the second layer,

the third layer comprising a single material including hafnium, aluminum, oxygen, and nitrogen,
wherein a thickness of the third layer is between 20 and 100 Angstroms.

US Pat. No. 9,292,428

MEMORY SYSTEM

KABUSHIKI KAISHA TOSHIBA,...

1. A memory system comprising:
a nonvolatile semiconductor storage device including a nonvolatile semiconductor memory;
a volatile memory in which a plurality of management data to manage writing in or reading from the nonvolatile semiconductor
storage device is stored;

a controller that issues a first command to designate first management data stored in the volatile memory, and that issues
a second command to designate writing in or reading from the nonvolatile semiconductor storage device; and

a circuit,
wherein the nonvolatile semiconductor storage device includes:
a first module that generates first random number data by shuffling first seed data based on the first management data designated
by the first command,

a second module that randomizes write data into first data based on the first random number data, the write data corresponding
to the second command to designate writing in the nonvolatile semiconductor storage device, and

a third module that recovers second data into read data using the first random number data, the second data being stored in
the nonvolatile semiconductor memory, and the read data corresponding to the second command to designate read from the nonvolatile
semiconductor device,

the circuit inverts the data randomized by the second module for each page, based on the first command,
the nonvolatile semiconductor memory is formed of a plurality of pages, to store a plurality of bits of data in one memory
cell,

the nonvolatile semiconductor memory includes at least a lower page and an upper page,
the circuit inverts data of one of the lower page and the upper page, based on the second data, and
the second data is number of erases, and the circuit inverts data of the lower page when the number of erases is an odd number,
and inverts data of the upper page when the number of erases is an even number.

US Pat. No. 9,395,669

IMAGE FORMING APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. An image forming apparatus comprising:
a image forming unit configured to form a toner image by developing an electrostatic latent image formed on an image carrier
using a toner and fixes the toner image to a recording medium;

a count unit configured to count a use amount of a consumption component or an apparatus which are used in the image forming
unit according to a image forming condition in the image forming unit; and

a count changing unit configured to determine a type of the toner used in the image forming unit, and changes a count method
of the count unit set according to the image forming condition in response to a determined result.

US Pat. No. 9,412,683

SEMICONDUCTOR DEVICE HAVING BARRIER METAL LAYER

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:
an interlayer insulating film which is formed on a substrate or on a conductive layer containing silicon formed on a substrate,
the interlayer insulating film having a hole reaching the substrate or the conductive layer;

a molybdenum containing layer formed on the substrate or in the conductive layer at a bottom portion of the hole;
a barrier metal layer formed on the molybdenum containing layer and on a side surface of the hole, a portion of the barrier
metal layer formed on the side surface containing at least molybdenum, a portion of the barrier metal layer formed on the
molybdenum containing layer including at least a molybdenum silicate nitride film; and

a plug material layer formed in the hole through the barrier metal layer.

US Pat. No. 9,289,983

INK JET HEAD

Kabushiki Kaisha Toshiba,...

1. An ink jet head comprising:
a pressure chamber which is filled with ink;
a capacitive-type actuator which changes capacitance of the pressure chamber by performing charging or discharging with a
series of charging and discharging sequence;

a plate having a plurality of nozzles which eject ink in the pressure chamber according to the change of the capacitance of
the pressure chamber;

a charging and discharging circuit which selectively charges or discharges the actuator depending on the input driving waveform;
and

a waveform generation circuit which outputs a driving waveform to the charging and discharging circuit so as to perform charging
by applying an intermediate voltage lower than a driving voltage which is a target voltage and then perform charging by applying
the driving voltage to the actuator, when charging the actuator, and to perform discharging by applying the intermediate voltage
and then perform discharging by applying a zero voltage to the actuator which is charged by the driving voltage, when discharging
the actuator,

wherein the time for applying the intermediate voltage to the actuator at a timing of ejecting the ink from the nozzles is
shorter than the time for applying the intermediate voltage to the actuator at other timings.

US Pat. No. 9,454,123

ERASING APPARATUS AND COOLING METHOD

KABUSHIKI KAISHA TOSHIBA,...

1. An erasing apparatus comprising:
a path along which a sheet is to be carried;
an erasing unit arranged on the path and configured to erase an image on the sheet by heating the sheet;
a fan configured to blow air to a position on the path that is downstream from the erasing unit in a sheet carrying direction;
and

a shutter disposed between the fan and the erasing unit and movable between a first position in which one end thereof is proximate
to the path and a second position in which the one end is away from the path.

US Pat. No. 9,409,432

MARKING APPARATUS AND COLOR ERASING APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. A marking apparatus, comprising:
a reading section configured to read an image including a first mark on a sheet, the first mark being formed with a color
erasable material in the margin area of the sheet to indicate used times of the sheet;

a storing section configured to store the read image data by the reading section;
a judging section configured to judge the reuse times of the sheet based on the read first mark;
a marking section configured to form a second mark in the margin area of the sheet with a color erasable material to indicate
the used times of the sheet is increased based on the judged result of the judging section; and

an erasing section configured to erase the image including at least the first mark on the sheet.

US Pat. No. 9,292,803

APPARATUS AND METHOD FOR PRIVACY-DRIVEN MODERATION OF METERING DATA

Kabushiki Kaisha Toshiba,...

1. A system comprising:
an input for connecting the system to a power supply via a smart meter such that the system is located on the consumer side
of the smart meter;

at least one further power source;
at least one power consumer being a building or house or part of a building or house;
an identifying unit arranged to identify, based on information originating from within the system, an ongoing and/or future
power consumption event by the at least one power consumer;

a power router comprising a controller and arranged to route power to the power consumer from at least one of the power supply
and the at least one further power source, the power router storing rules that define at least part of the routing operation
of the router; and

a load shape generator arranged to determine a target load shape that is in conformity with one or more of the stored rules
for use with a scheduled and/or a currently ongoing power consumption event, whereby the power consumption event has a load
signature;

wherein the power router is arranged to route power to said power consumer in accordance with the stored rules so that at
least a part of the power consumed by the power consumer during the power consumption event is provided by the at least one
power source, rather than through the input, in response to the identifying unit identifying said power consumption event,
whereby a modified load signature is generated based on the load signature of said power consumption event in accordance with
stored privacy rules by said power router enforcing the target load shape prior to the modified load signature being reported
by the smart meter.

US Pat. No. 9,294,648

IMAGE READING DEVICE

Kabushiki Kaisha Toshiba,...

1. An image reading device comprising:
a document table having a document read area;
an illumination unit that includes a light source configured to illuminate the document read area, and a light-guiding body
configured to allow light from the light source to be incident on both end portions extending in a main-scanning direction
and to scatter or reflect the light to be emitted toward the document read area;

an arc-shaped portion that is formed at both end portions of the light-guiding body;
a carriage that supports the illumination unit to be movable in a sub-scanning direction;
a hold-down member that holds down the both end portions of the light-guiding body towards the carriage and regulates movement
of the light-guiding body in the main-scanning direction; and

a photoelectric conversion unit configured to receive reflected light from a document in the document read area illuminated
by the illumination unit, and photoelectrically convert the light to output an electric signal,

wherein the light-guiding body of the illumination unit has a first surface configured to allow light from the light source
to be emitted toward the document read area, a second surface adjacent to the first surface and configured to allow the light
from the light source to be emitted in a direction different from the direction of the light emitted from the first surface,
and a third surface that faces the second surface and has a light scatter surface, and

wherein the arc-shaped portion is formed at both end portions of the second surface.

US Pat. No. 9,278,557

SHEET PROCESSING APPARATUS AND METHOD FOR PROCESSING SHEETS

Kabushiki Kaisha Toshiba,...

1. A sheet processing apparatus comprising:
a sheet conveying unit configured to convey sheets;
a first scanning unit configured to scan a surface of each of the sheets conveyed by the sheet conveying unit, and generate
a first image data for each of the sheets;

an erasing unit configured to carry out an erasing process on the surface of each of the sheets conveyed from the first scanning
unit;

a second scanning unit configured to scan the surface of each of the sheets conveyed from the erasing unit, and generate a
second image data for each of the sheets; and

a control unit configured to cause each of the sheets to be sorted based on a difference between the first image data and
the second image data thereof, wherein the control unit determines the difference by determining a difference between a first
number of pixels that have a color different from a color of the sheet in the first image data and a second number of pixels
that have a color different from a color of the sheet in the second image data.

US Pat. No. 9,411,309

IMAGE FORMING APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. An image forming apparatus comprising:
a fan provided in a housing; and
a duct provided in the housing and configured to guide, if the fan is driven, air flowing into the housing from an intake
port of the housing toward components in the housing, wherein

the duct includes a bent section that changes a flowing direction of the air,
the bent section includes: holes, a bottom surface in a gravity direction of the bent section, a first plane extending substantially
in a vertical direction, and a first corner located between the first plane and the bottom surface,

the first corner changes a flow of the air flowing downward to be directed substantially to a horizontal direction,
the bottom surface extends in a direction crossing the first plane, and
at least a part of the holes are provided in the bottom surface section of the bent section.

US Pat. No. 9,389,557

FIXING DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A fixing device comprising:
a fixing belt that includes a conductive layer;
an induced current generation section that opposes the fixing belt in a thickness direction and performs electromagnetic induction
heating on the conductive layer;

a first auxiliary heat generation section that opposes the induced current generation section with the fixing belt interposed
therebetween, the first auxiliary heat generation section opposes a sheet passing region of the fixing belt in a width direction,
and ferrite forms the first auxiliary heat generation section; and

a second auxiliary heat generation section that opposes the induced current generation section with the fixing belt interposed
therebetween, the second auxiliary heat generation section opposes a sheet non-passing region of the fixing belt in the width
direction, and a magnetic shunt alloy forms the second auxiliary heat generation section.

US Pat. No. 9,299,313

MEDICAL IMAGE DISPLAY APPARATUS AND PROGRAM

KABUSHIKI KAISHA TOSHIBA,...

1. A medical image display apparatus, comprising:
a control circuit configured to obtain information on a scan sequence and obtain a plurality of scan time information values,
each of the plurality of scan time information values being information of a time when scan data for each of a corresponding
plurality of reconstructed medical images were picked up in accordance with the scan sequence;

a memory configured to store the plurality of scan time information values obtained by the time information obtaining unit
in association with the corresponding plurality of reconstructed medical images; and

a display configured to simultaneously display the plurality of reconstructed medical images, each of which is associated
with the corresponding scan time information value of the plurality of scan time information values stored in the memory,
and a time chart indicating the scan sequence,

wherein the control circuit is further configured to, when a reconstructed medical image of the plurality of reconstructed
medical images displayed on the display is selected, display a marker indicating a time position on the time chart corresponding
to a scan time information value associated with the selected reconstructed medical image.

US Pat. No. 9,231,029

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor memory device comprising:
a plurality of global bit lines extending in a first direction and arranged with spacings in a second direction crossing the
first direction;

a plurality of word lines spaced in the first direction, extending in the second direction, and stacked via an interlayer
insulating layer in a third direction crossing the first direction and the second direction, the word lines including a first
word line and a second word line arranged adjacently to each other in the first direction;

a plurality of bit lines arranged with spacings in the second direction between the word lines, and extending in the third
direction, the bit lines including a first bit line and a second bit line arranged adjacently to each other in the first direction,
the first bit line provided between the first word line and the second word line, the first word line provided between the
first bit line and the second bit line;

a plurality of resistance change films provided between the word lines and the bit lines, the resistance change films including
a first resistance change film and a second resistance change film arranged adjacently to each other in the first direction,
the first word line provided between the first bit line via the first resistance change film and the second bit line via the
second resistance change film;

a plurality of semiconductor layers provided between the global bit lines and the bit lines;
a gate insulating film provided on a side surface of the semiconductor layers; and
a plurality of gate electrodes provided via the gate insulating film between the semiconductor layers in the second direction
and on the side surface of the semiconductor layers in the first direction, and extending in the second direction,

spacing in the first direction between the plurality of semiconductor layers being larger than spacing in the second direction
between the plurality of semiconductor layers,

the plurality of gate electrodes being separated in the first direction, and
in the first direction, a distance between the gate electrodes adjacently arranged being shorter than a distance between the
first bit line and the second bit line.

US Pat. No. 9,349,853

SEMICONDUCTOR TRANSISTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:
a first electrode;
a second electrode; and
a first semiconductor region of a first conductivity type provided between the first electrode and the second electrode;
a second semiconductor region of the first conductivity type provided between the first semiconductor region and the first
electrode, the second semiconductor region having a higher impurity concentration than the first semiconductor region;

a third semiconductor region of a second conductivity type provided between the first semiconductor region and the second
electrode;

a fifth semiconductor region of the second conductivity type provided between the first semiconductor region and the second
electrode;

a fourth semiconductor region of the first conductivity type provided between the third semiconductor region and the second
electrode and between the fifth semiconductor region and the second electrode, the fourth semiconductor region having a higher
impurity concentration than the first semiconductor region;

a third electrode in contact with the first semiconductor region, the third semiconductor region, and the fourth semiconductor
region via a first insulating film; and

a second insulating film in contact with the first semiconductor region, the fifth semiconductor region, and the fourth semiconductor
region,

an impurity concentration of a portion where the fifth semiconductor region is in contact with the second insulating film
is lower than an impurity concentration of a portion where the fifth semiconductor region on a side of the first electrode
is in contact with the first semiconductor region.

US Pat. No. 9,292,433

MEMORY DEVICE, HOST DEVICE, AND SAMPLING CLOCK ADJUSTING METHOD

Kabushiki Kaisha Toshiba,...

1. A sampling clock adjusting method for a host device connected to a memory device including a nonvolatile semiconductor
memory unit through signal lines, the host device including a host controller, a sampling clock adjustment unit, and a clock
unit configured to generate a clock signal, the method comprising:
setting, by the sampling clock adjustment unit, an initial value of a phase of a sampling clock signal determining a sampling
point at which the host device receives a signal from the memory device on the basis of a phase of the clock signal, wherein
the host controller performs control to send a command signal through a command line, receive a response signal through the
command line, send and receive a data signal through data lines, and send a clock signal through a clock line, and wherein
the memory device sends the signal in synchronization with the clock signal received from the host device;

sending, by the host device, a tuning command to the memory device through the command line;
sending, by the memory device upon receiving the tuning command, a first tuning signal and a second tuning signal for adjusting
the phase of the sampling clock signal, wherein a pattern of the first tuning signal and a pattern of the second tuning signal
are prestored in a memory device side signal pattern storage, and wherein the first tuning signal is sent through a first
signal line, the second tuning signal is sent through a second signal line, and a time period during which the first tuning
signal is sent and a time period during which the second tuning signal is sent overlap each other;

receiving, by the host device, the first tuning signal and the second tuning signal; and
comparing, by the host controller, patterns of the first tuning signal and the second tuning signal received with patterns
of the first tuning signal and the second tuning signal prestored in a host side signal pattern storage, and adjusting, by
the sampling clock adjustment unit, the phase of the sampling clock signal to an optimum sampling point based on a result
of the comparison.

US Pat. No. 9,246,085

SHAPING RERAM CONDUCTIVE FILAMENTS BY CONTROLLING GRAIN-BOUNDARY DENSITY

Intermolecular, Inc., Sa...

1. A device, comprising:
a first layer formed over a substrate, the first layer operable as a first electrode;
a second layer formed over the first layer, the second layer operable as a second electrode; and
a variable-resistance stack formed between the first layer and the second layer;
wherein the variable-resistance stack comprises
a first variable-resistance layer;
a second variable-resistance layer formed over the first variable-resistance layer;
wherein the first variable-resistance layer has a first grain boundary density; and
wherein the second variable-resistance layer has a second grain boundary density different from the first grain boundary density;
and

a third variable-resistance layer between the second variable-resistance layer and the second layer;
wherein the third variable-resistance layer has a third grain boundary density different from both the first grain boundary
density and the second grain boundary density; and

wherein the second grain boundary density is between the first grain boundary density and the third grain boundary density.

US Pat. No. 9,191,590

SIGNAL PROCESSING DEVICE AND IMAGING SYSTEM

Kabushiki Kaisha Toshiba,...

1. A signal processing device that processes a signal output from an imaging sensor that includes a light receiving area in
which a plurality of light receiving pixels is arranged and a light-shielded area in which a plurality of light-shielded pixels
is arranged, the device comprising:
a lead integration unit that integrates and averages, in a first integration region, signals of a plurality of first light-shielded
pixels in the light-shielded area;

a main integration unit that integrates and averages, in a second integration region that is determined based on a result
integrated and averaged by the lead integration unit, signals of a plurality of second light-shielded pixels in the light-shielded
area; and

a correction unit that determines a reference black level based on a result integrated and averaged by the main integration
unit and corrects a black level of a signal of a light receiving pixel using the determined reference black level.

US Pat. No. 9,046,862

IMAGE FORMING APPARATUS CONGIGURED TO FORM AN IMAGE BY USING A RECOLORABLE DECOLORABLE COLORANT AND UNDECOLORABLE COLORANT OR ANUNRECOLORABLE DECOLORABLE COLORANT AND FIX BOTH COLORANT AT THE SAME TIME, AND METHOD FOR REUSE OF SHE

Kabushiki Kaisha Toshiba,...

1. An image forming apparatus comprising:
an image forming section configured to form images on a sheet by using both a recolorable decolorable colorant and an undecolorable
colorant;

a fixing device configured to heat the sheet to fix the recolorable decolorable colorant and the undecolorable colorant on
the sheet at the same time; and

a fixing-temperature control section configured to perform temperature control for the fixing device and fix the recolorable
decolorable colorant and the undecolorable colorant on the sheet at a temperature higher than a decoloring start temperature
of the recolorable decolorable colorant to thereby fix the recolorable decolorable colorant on the sheet in a decolored state
and fix the undecolorable colorant on the sheet in a colored state.

US Pat. No. 9,304,455

IMAGE FORMING APPARATUS AND DECOLORING APPARATUS

Kabushiki Kaisha Toshiba,...

13. A method of evaluating a condition of a heating portion of an image processing apparatus configured to decolor an image
formed of a decolorable toner on a sheet, comprising:
providing a diagnosis image on both sides of a diagnosis sheet with the decolorable toner in a diagnosis mode;
passing the diagnosis sheet having the diagnosis images thereon past the heating portion of the image processing apparatus
while the heating portion is maintained at a decoloring temperature of the decolorable toner or higher;

imaging both sides of the diagnosis sheet after the diagnosis sheet is passed through the heating portion of the image processing
apparatus while the heating portion is maintained at the decoloring temperature of the decolorable toner or higher; and

determining a presence of a defect in the heating portion based upon a presence of a portion of the diagnosis image remaining
on at least one side of the diagnosis sheet.

US Pat. No. 9,298,160

IMAGE FORMING APPARATUS AND COOLING CONTROL METHOD FOR IMAGE FORMING APPARATUS

Kabushiki Kaisha Toshiba,...

1. An image forming apparatus comprising:
a printer portion which forms an image on a sheet based on an input print job;
a fan motor;
a counter which counts an operation time of the printer portion or a value which is replaced with the operation time of the
printer portion;

a timer which measures a printing start time and a printing completion time based on the print job; and
a control unit which controls the fan motor,
wherein the control unit calculates a time interval between print jobs from the difference between a printing completion time
of a first print job and a printing start time of a second print job based on the value which is measured by the timer when
the print jobs are continuously performed,

wherein the control unit resets the counter when the time interval exceeds a first threshold value, and
wherein the control unit starts driving of the fan motor when the operation time which is counted by the counter or the value
thereof is greater than or equal to a second threshold value.

US Pat. No. 9,285,706

TONER CARTRIDGE WITH MEMORY FOR IMAGE FORMING APPARATUS

Kabushiki Kaisha Toshiba,...

1. A toner cartridge for use with an image forming apparatus having an acquiring unit configured to acquire identification
data from the toner cartridge when the toner cartridge is mounted on the image forming apparatus; a reading unit configured
to read parameter information including image formation process parameters, from the toner cartridge when the acquired identification
data matches identifying data previously stored in the image forming apparatus, and not read the parameter information from
the toner cartridge when the acquired identification data does not match the identifying data, the toner cartridge comprising:
a memory storing the identification data of the toner cartridge and the parameter information including the image formation
process parameters dependent on toner characteristic or ambient conditions, the memory being configured to communicate with
the acquiring unit or the reading unit by wire.

US Pat. No. 9,270,260

DISTORTION COMPENSATION DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A distortion compensation device for compensating a distortion component generated in a nonlinear circuit having a nonlinear
input-output characteristic, comprising:
a predistorter configured to convert an input signal into an inverse characteristic signal by using a compensation coefficient
so that an estimation value of an inverse characteristic to the nonlinear input-output characteristic is given to the input
signal;

an estimator configured to generate the compensation coefficient based on the input signal, the inverse characteristic signal
and an output signal of the nonlinear circuit;

wherein the estimator includes:
a reference signal generation module configured to generate a reference signal including a difference between the inverse
characteristic signal and a signal of the distortion component, based on the input signal, the inverse characteristic signal
and the output signal of the nonlinear circuit; and

an estimation computing module configured to compute the compensation coefficient based on the input signal and the reference
signal.

US Pat. No. 9,160,534

AUTHENTICATOR, AUTHENTICATEE AND AUTHENTICATION METHOD

KABUSHIKI KAISHA TOSHIBA,...

1. An authentication method between an authenticate and an authenticator, the authenticatee comprising a memory and first
circuitry, and which stores in the memory a plurality of pieces of secret information XY and a plurality of pieces of secret
information XYE, which are created by encrypting the plurality of pieces of secret information XY, and the authenticator comprising second
circuitry, and which authenticates the authenticatee, the method comprising:
executing, by the authenticator, a decryption process on the secret information XYE that is received from the authenticatee, and retrieving the secret information XY from the decrypted secret information XYE;

receiving, by the authenticatee, a random number B that is generated by the authenticator, and loading the secret information
XY;

generating, by the authenticatee, a random number A and data ? (? having a probability ? of occurrence of 1 (?<0.5));
generating, by the authenticatee, a first random number D that is composed of at least a part of the generated random number
A and the received random number B;

generating, by the authenticatee, first data C by executing a compression operation with respect to at least a part of the
first random number D and the secret information XY;

transmitting, by the authenticatee, a calculated result Z from the data v and the first data C, to the authenticator;
generating, by the authenticator, a second random number D that is composed of at least a part of the generated random number
A and the received random number B;

generating, by the authenticator, second data C by executing a compression operation with respect to at least a part of the
second random number D and the secret information XY;

determining, by the authenticator, authenticity of the authenticatee by calculating a weighted value from the received calculated
result Z and the generated second data C; and

authenticating the authenticatee, by the authenticator, when the weighted value is less than a predetermined value.

US Pat. No. 9,365,068

IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD

KABUSHIKI KAISHA TOSHIBA,...

1. An image processing apparatus comprising:
an image processing unit that acquires, from a sheet, information that includes a printing ratio of an image printed on the
sheet;

a decoloring unit that decolors the image by heating the image at a decoloring temperature; and
a control unit that determines the decoloring temperature used for a decoloring process executed by the decoloring unit based
on the printing ratio.

US Pat. No. 9,335,694

IMAGE FORMING APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. An image forming apparatus comprising:
an image forming unit that forms an image on a sheet;
a heat source that heats the sheet at a control temperature according to a job type;
a storage unit including a job queue that registers jobs in a received order; and
a controller that, when a plurality of jobs that differ in the control temperature are registered in the job queue:
groups the lobs registered in the job queue into job groups that differ in the control temperature,
determines whether a speed of temperature increase of the heat source is larger than a speed of temperature decrease of the
heat source with respect to the corresponding control temperatures of the job groups,

changes an execution order of the job groups in the job queue so that a required time for execution of all the job groups
is shorter than any other execution order based on the determination of whether the speed of temperature increase is larger
than a speed of temperature decrease, and

executes the jobs registered in the job queue according to the changed order.

US Pat. No. 9,087,978

TRANSITION METAL OXIDE BILAYERS

Intermolecular, Inc., Sa...

1. A method of forming a semiconductor device, the method comprising:
forming a first layer on a substrate,
wherein the first layer comprises a first metal, a second metal, silicon, and oxygen,
forming a second layer on the first layer;
wherein the second layer comprises the first metal, the second metal, silicon, and oxygen;
wherein the first metal is different from the second metal; and
wherein one of the first layer or the second layer has a linear resistance and a sub-stoichiometric composition while another
one of the first layer or the second layer has a bistable resistance and a near-stoichiometric composition.

US Pat. No. 9,058,748

CLASSIFYING TRAINING METHOD AND APPARATUS USING TRAINING SAMPLES SELECTED AT RANDOM AND CATEGORIES

Kabushiki Kaisha Toshiba,...

1. A training apparatus comprising:
a training sample storage unit that stores therein a plurality of training samples that are classified into C (C?3) categories,
wherein categories of the plurality of categories are different from each other;

a selecting unit that performs, N (N?2) times, a selection process of selecting a plurality of groups each including one or
more training samples from the training sample storage unit, the one or more training samples included in each of the plurality
of groups being selected at random; and

a training unit that trains, each time the selection process is performed, a classifier Fi(x) for classifying the plurality
of groups selected in the selection process, where 1?i?N, and generates an evaluation metric, wherein

the evaluation metric is an array of classifiers F1(x), F2(x), through FN(x),
the evaluation metric outputs a feature value v(X) for an input data,
the feature value v(X) is an array of elements of an evaluation si,
the evaluation value si is an output of the classifier Fi(x) for the input data,

the evaluation si is a vector, and
the feature value v(X) indicates to which category the input data belongs among the C categories and one or more non-C categories.

US Pat. No. 9,442,435

FIXING DEVICE, IMAGE FORMING APPARATUS AND FIXING METHOD

KABUSHIKI KAISHA TOSHIBA,...

1. A fixing device, comprising:
an endless fixing belt configured to be movable;
a pressing roller configured to be movable with endless fixing belt;
a fixing pad configured to be contacted with an inner periphery of the fixing belt and be pressed against the pressing roller
to form a fixing nip;

a lubricant configured to be coated on an inner peripheral surface of the fixing belt;
an exciting coil configured to generate a magnetic field;
a magnetic shunt alloy member configured to abut along at least a part of the inner peripheral surface of the fixing belt;
a shield member provided to be facing the magnetic shunt alloy member and configured to shield the magnetic field generated
by the exciting coil at least at an upstream end of the shield member along a moving direction of the fixing belt; and

a flow-out prevention section configured to prevent the lubricant from flowing into a gap between the magnetic shunt alloy
member and the shield member, wherein the magnetic shunt alloy member includes a bent portion that widens a gap between the
magnetic shunt alloy member and the fixing belt, and narrows the gap between the magnetic shunt alloy member and the shield
member.

US Pat. No. 9,377,724

IMAGE FORMING APPARATUS AND METHOD USING DECOLORABLE INK

Kabushiki Kaisha Toshiba,...

1. An image forming apparatus comprising:
an electrographic printer which prints a first image using toner which is thermally non-decolorable;
a fixer which is located at a downstream of the electrographic printer in a conveyance direction and fixes the first image
to a first recording medium; and

an ink jet printer which prints a second image with four colors of decolorable ink on a second recording medium which is conveyed
in a common carrying path shared by the first recording medium.

US Pat. No. 9,178,140

MORPHOLOGY CONTROL OF ULTRA-THIN MEOX LAYER

Intermolecular, Inc., Sa...

1. A device comprising:
a first layer operable as a first electrode;
a second layer disposed over the first layer,
wherein the second layer comprises one of hafnium oxynitride, zirconium oxynitride, aluminum oxynitride, tantalum oxynitride,
hafnium nitride, zirconium nitride, silicon nitride, aluminum nitride, titanium nitride, vanadium nitride, niobium nitride,
or tungsten nitride,

wherein the second layer directly interfaces the first layer,
wherein a morphology of the first layer is the same as a morphology of at least a portion of the second layer directly interfacing
the first layer, and

wherein the morphology of the first layer is one of crystalline, polycrystalline, amorphous, or a combination thereof; and
a third layer operable as a second electrode,
wherein the second layer is disposed between the first layer and the third layer.

US Pat. No. 9,434,193

DECOLORING APPARATUS AND METHOD

KABUSHIKI KAISHA TOSHIBA,...

1. A decoloring apparatus, comprising:
a sheet conveying unit;
a scanner configured to scan an image on a sheet conveyed by the sheet conveying unit;
a decoloring unit positioned downstream of the scanner in a sheet conveying direction and configured to decolor the image
on the sheet conveyed through the sheet conveying unit;

a user interface including:
a resolution setting section configured to receive an input for setting a resolution of the image to be scanned by the scanner,
and

a processing mode setting section having a first section and a second section and configured to receive a selection to execute
scanning processing by the scanner in the first section and a selection to execute decoloring processing by the decoloring
unit in the second section; and

a controller configured to perform a mode limiting processing to
control the processing mode setting section to disable the selection of the second section if the resolution setting section
has received an input to set the resolution of the image higher than a predetermined resolution, and

control the resolution setting section to disable any input that sets the resolution higher than the predetermined resolution
if the processing mode setting section has received the selection to execute decoloring processing by the decoloring unit.

US Pat. No. 9,411,276

FIXING DEVICE AND FIXING TEMPERATURE CONTROL METHOD OF FIXING DEVICE

TOSHIBA TEC KABUSHIKI KAI...

1. A fixing device comprising:
an endless rotating body;
a plurality of heat-generating members for heating a medium, each heat-generating member being parallel, formed in a perpendicular
direction to a transporting direction of the medium, inclined from the transporting direction to a direction of a predetermined
angle, and divided by a predetermined length, and being disposed so as to come into contact with an inner side of the endless
rotating body;

a switching unit comprising a plurality of switching elements, each switching element being connected to each heat-generating
member, for switching individual conduction of these switching elements connected to heat-generating members corresponding
to a position through which the medium passes; and

pressing means for forming a nip by performing pressing and contact at a position of the plurality of heat-generating members,
and for nipping and carrying the medium in the transporting direction.

US Pat. No. 9,302,493

IMAGE ERASING APPARATUS AND IMAGE ERASING METHOD

Kabushiki Kaisha Toshiba,...

1. An image erasing apparatus, comprising:
a sheet supply section configured to supply a sheet;
at least one discharge tray configured to receive the sheet;
a first conveying path configured to convey the sheet from the sheet supply section toward the at least one discharge tray;
a reader arranged on the first conveying path and configured to read a surface of the sheet;
a second conveying path that branches from the first conveying path at a first position downstream of the reader in a sheet
conveying direction and that merges with the first conveying path at a second position between the sheet supply section and
the reader;

an erasing unit arranged on the second conveying path and configured to erase an image formed on the sheet with image erasable
material;

a switching section arranged on the first conveying path at the first position and configured to switch a conveyance path
of the sheet between the first conveying path towards the at least one discharge tray and the second conveying path towards
the erasing unit; and

a controller configured to control the first conveying path, the reader, the second conveying path, the erasing unit and the
switching section depending on a mode selected from one of an erasing only mode in which the sheet is subject to erasing processing
in the erasing unit and not subject to reading processing in the reader, a reading only mode in which the sheet is subject
to reading processing in the reader and not subject to erasing processing in the erasing unit, and a reading plus erasing
mode in which the sheet is subject to the erasing processing and the reading processing.

US Pat. No. 9,168,010

X-RAY IMAGING APPARATUS AND MEDICAL IMAGE PROCESSING APPARATUS

Kabushiki Kaisha Toshiba,...

1. An X-ray imaging apparatus comprising:
an imaging unit which includes an X-ray tube that emits an X-ray to a subject and an X-ray detector that is so disposed as
to face the X-ray tube;

an input unit which inputs a plurality of imaging conditions including a tube current and tube voltage of the X-ray tube,
and sets an imaging protocol of the imaging unit;

an image creation unit which calculates an exposed dose when at least the tube voltage or the tube current is varied, and
creates an index image that is made by overlapping an image showing the exposed dose depending on a setting values of the
tube current and tube voltage on a two-dimensional map that is represented by the tube voltage and the tube current; and

a display unit which displays the index image created by the image creation unit.

US Pat. No. 9,159,747

DISPLAY DEVICE, THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR

Kabushiki Kaisha Toshiba,...

1. A thin film transistor, comprising:
a substrate;
a first insulating layer having a first hydrogen concentration provided on the substrate;
a second insulating layer provided on the first insulating layer, the second insulating layer having a second hydrogen concentration
higher than the first hydrogen concentration;

a gate electrode provided on the second insulating layer;
a semiconductor layer of an oxide including at least one selected from indium, gallium, and zinc separated from the gate electrode
in a stacking direction from the substrate toward the second insulating layer, the semiconductor layer having a first portion,
a second portion separated from the first portion in a first direction perpendicular to the stacking direction, and a third
portion provided between the first portion and the second portion;

a gate insulation layer provided between the gate electrode and the semiconductor layer;
a first conductive portion electrically connected to one selected from the first portion and the second portion;
a second conductive portion electrically connected to other one selected from the first portion and the second portion; and
a third insulating layer covering a portion of the semiconductor layer other than the first portion and the second portion.

US Pat. No. 9,136,835

SWITCH CIRCUIT

Kabushiki Kaisha Toshiba,...

1. A switch circuit comprising:
a transmission unit configured to transmit a signal through a single transistor, in which a back gate and a source are connected
by way of a resistor; and

a back gate control unit configured to connect the back gate of the single transistor to a fixed potential when the single
transistor is turned OFF, and to separate the back gate of the single transistor from the fixed potential when the single
transistor is turned ON, wherein the source of the single transistor is connected to an input terminal of the transmission
unit, and the drain of the single transistor is connected to an output terminal of the transmission unit,

wherein a value of the resistor is set so that a parasitic capacitance of the back gate is ignorable on a transmission path
of the signal,

wherein the transmission unit includes
a first P-channel transistor,
a first N-channel transistor connected in parallel with the first P-channel transistor,
a first resistor connected between a back gate and a source of the first P-channel transistor, and
a second resistor connected between a back gate and a source of the first N-channel transistor, and
the back gate control unit includes
a second P-channel transistor configured to connect the back gate of the first P-channel transistor to a first fixed potential
based on an enable signal, and

a second N-channel transistor configured to connect the back gate of the first N-channel transistor to a second fixed potential
based on the enable signal,

wherein the source of the first P-channel transistor and the source of the first N-channel transistor are connected to an
input terminal of the transmission unit, and the drain of the first P-channel transistor and the drain of the first N-channel
transistor are connected to an output terminal of the transmission unit, and

wherein the enable signal is input to the gate of the first P-channel transistor and the gate of the second N-channel transistor;
and a signal, in which the enable signal is inverted, is input to the gate of the second P-channel transistor and the gate
of the first N-channel transistor, and further comprising an inverter configured to invert the enable signal, and a level
shifter, arranged at a pre-stage of the inverter and configured to convert amplitude of a control signal that controls the
back gate control unit.

US Pat. No. 9,377,730

IMAGE FORMING APPARATUS AND IMAGE FORMING METHOD

KABUSHIKI KAISHA TOSHIBA,...

1. An image forming apparatus for forming an image on a recording medium, comprising:
a fixing member to fix toner to the recording medium;
a heating control part to heat the fixing member to a specified temperature;
a measuring part to measure a temperature of the fixing member; and
a calculation part to calculate an arrival time required until the temperature of the fixing member reaches a target temperature
based on a difference between the target temperature at a warming-up end time of the fixing member and the temperature measured
by the measuring part, wherein

in response to a determination by the calculation part that the arrival time is shorter than a warm-up time required to warm
up the image forming apparatus except for the fixing device, the heating control part starts to heat the fixing member after
a specified time passes from a time when warming-up of the image forming apparatus is started.

US Pat. No. 9,318,565

POWER SEMICONDUCTOR DEVICE WITH DUAL FIELD PLATE ARRANGEMENT AND METHOD OF MAKING

Kabushiki Kaisha Toshiba,...

1. A method of making a semiconductor device, comprising:
providing a substrate;
forming a gate insulating layer on a surface of the substrate;
forming a plurality of gate electrodes on the gate insulating layer;
forming, by chemical vapor deposition, an insulating film overlying the gate electrodes and gate insulating layer;
annealing the substrate having the gate electrodes and gate insulating layer film formed thereon at a temperature sufficient
to increase the dielectric breakdown strength thereof;

etching source electrode openings, drain electrode openings, and field plate electrode openings partially inwardly of the
insulating layer, the field plate electrode opening overlying the gate electrode and extending therefrom in the direction
of the drain electrode openings;

etching the source and the drain electrode openings through a remaining insulating film thickness and the gate insulating
layer to the substrate, while simultaneously etching only that portion of the remaining insulating film thickness in the field
plate electrode opening at a location which overlies the gate electrode through the remaining insulating film to the gate
electrode;

simultaneously depositing metal into the source, drain, and field plate electrode openings, and over a surface of the remaining
insulating film to form a metal layer; and

pattern etching the metal layer overlying the remaining insulating film to isolate source electrodes in the source electrode
openings, first field plate electrodes in the field plate electrode openings and drain electrodes in the drain electrode openings
from one another.

US Pat. No. 9,246,091

RERAM CELLS WITH DIFFUSION-RESISTANT METAL SILICON OXIDE LAYERS

Intermolecular, Inc., Sa...

1. A device, comprising:
a first layer operable as a first electrode;
a second layer;
a third layer operable as a variable resistance layer switchable between a high resistance state and a low resistance state;
a fourth layer operable as a second electrode;a fifth layer operable as a defect reservoir,
wherein the fifth layer comprises mobile defects;
wherein the second layer and the third layer are between the first layer and the fourth layer;
wherein the first layer comprises a nitride of a metal; and
wherein the second layer comprises a compound oxide of the metal and silicon.

US Pat. No. 9,246,096

ATOMIC LAYER DEPOSITION OF METAL OXIDES FOR MEMORY APPLICATIONS

Intermolecular, Inc., Sa...

1. A semiconductor device comprising:
a first electrode;
a metal oxide film stack disposed on the first electrode,
wherein the metal oxide film stack comprises a first metal oxide film and a second metal oxide film,
wherein the first metal oxide film comprises a stoichiometric oxide of a metal,
wherein the second metal oxide film comprises a non-stoichiometric oxide of the metal,
wherein the metal is one of hafnium, zirconium, or titanium, and
wherein a stoichiometric ratio of oxygen to the metal in the non-stoichiometric oxide is between about 1.70 and 1.90;
a second electrode disposed on the metal oxide film stack such that the metal oxide film stack is disposed between the first
electrode and the second electrode; and

a coupling layer disposed between the first electrode and the metal oxide film stack.

US Pat. No. 9,226,033

INFORMATION PROCESSING APPARATUS AND METHOD FOR PROVIDING INFORMATION

Kabushiki Kaisha Toshiba,...

1. A system comprising:
a receiver device of a broadcast analysis system configured to receive, from a site on the Internet, a first set of messages
related to a first broadcast station, the first set of messages posted on the site respectively by users; and

a processor device of the broadcast analysis system configured to score at least a first message from the first set of messages,
wherein the messages from the first set of messages comprise characters, the score is, at least in part, calculated based
on a number of characters in the first message from the first set of messages and the score increases inversely to a number
of characters in the first message from the first set of messages, wherein a higher scored message comprises less characters
than a lower scored message, and the processor device is further configured to calculate a first evaluation value for content
data being broadcast by the first broadcast station based on scores for the first set of messages,

wherein the receiver device is further configured to receive, from the site, a second set of messages related to a second
broadcast station, the second set of messages posted on the site respectively by the users,

wherein the processor device is further configured to score at least a first message from the second set of messages, wherein
the messages from the second set of messages comprise characters, the score is, at least in part, calculated based on a number
of characters in the first message from the second set of messages and the score increases inversely to a number of characters
in the first message from the second set of messages, the processor further configured to calculate a second evaluation value
for content data being broadcast by the second broadcast station based on scores for the second set of messages, and

wherein the broadcast analysis system provides the first evaluation value and the second evaluation value to a user device
for display to a user.

US Pat. No. 9,070,589

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A nonvolatile semiconductor memory device, comprising:
a semiconductor substrate;
a first layer formed above the semiconductor substrate;
a first conductive layer, an inter electrode insulating layer, and a second conductive layer sequentially stacked above the
first layer;

a memory film formed on an inner surface of each of a pair of through holes provided in the first conductive layer, the inter
electrode insulating layer, and the second conductive layer and extending in a stacking direction;

a semiconductor layer formed on the memory film in the pair of through holes and partially crystallized; and
a metal layer filled in a connection hole that is provided in the first layer and connects lower end portions of the pair
of through holes, the metal layer being in contact with the semiconductor layer, and the metal layer separating a first portion
of the semiconductor layer in one of the pair of through holes and a second portion of the semiconductor layer in the other
of the pair of through holes.

US Pat. No. 9,054,307

RESISTIVE RANDOM ACCESS MEMORY CELLS HAVING METAL ALLOY CURRENT LIMITING LAYERS

Intermolecular, Inc., Sa...

1. A method for forming a resistive random access memory cell, the method comprising:
forming a resistive switching layer comprising a resistive switching material;
forming a current limiting layer,
the current limiting layer comprising one of chromium, titanium, or tantalum,
the current limiting layer having a breakdown voltage of at least 8V and a resistivity of at least 1 Ohm-cm in a direction
normal to the current limiting layer; and

forming an electrode layer.

US Pat. No. 9,530,881

SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:
a first semiconductor layer of a first-conductivity type having a first surface and a second surface opposing the first surface;
a second semiconductor layer of the first-conductive-type on the first surface of the first semiconductor layer;
a third semiconductor layer of a second-conductivity type on the second semiconductor layer;
a fourth semiconductor layer of the first-conductivity type on the third semiconductor layer;
a fifth semiconductor layer of the first-conductivity type on the second semiconductor layer;
a first electrode on the second semiconductor layer with an insulating film located therebetween, on the third semiconductor
layer with the insulating film located therebetween, and on the fourth semiconductor layer with the insulating film located
therebetween;

a second electrode on the fourth semiconductor layer; and
a third electrode separated from the second electrode in a second direction that is crossing a first direction that is orthogonal
to the second surface, wherein

the third electrode has a third surface contacting the first surface of the first semiconductor layer and a fourth surface
having a first portion contacting a side surface of the second semiconductor layer and a second portion contacting a first
surface of the fifth semiconductor layer, wherein the third electrode has a width in the second direction that decreases in
the first direction from a first depth to a second depth which is closer than the first depth to the first semiconductor layer,

an angle of the side surface of the second semiconductor layer with respect to the first surface of the first semiconductor
layer is greater than or equal to 90 degrees, and

a second surface of the fifth semiconductor layer intersects the first surface of the fifth semiconductor layer and contacts
the third electrode.

US Pat. No. 9,335,732

IMAGE FORMING APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. An image forming apparatus comprising:
an image forming device configured to form an image on a sheet;
a fixing unit configured to fix the image formed on the sheet by heating the sheet with the image formed thereon to a fixing
temperature;

a temperature sensor configured to detect an ambient temperature of the apparatus;
a humidity sensor configured to detect ambient humidity of the apparatus;
a scanner device configured to read an image on a document, the scanner device including a carriage moveable between a home
position and a predetermined position near the fixing unit and above the fixing unit; and

a control unit configured to:
determine whether an environment of the apparatus is a dew condensation environment, based on detection information of the
temperature sensor and the humidity sensor, and

when it is determined that the environment of the apparatus is the dew condensation environment, turn ON the fixing unit,
control a heating temperature of the fixing unit to be lower than the fixing temperature, and control a movement of the carriage
such that the carriage moves to the predetermined position.

US Pat. No. 9,330,481

MEDICAL IMAGE PROCESSING APPARATUS AND MEDICAL IMAGE PROCESSING METHOD

KABUSHIKI KAISHA TOSHIBA,...

1. A medical image processing apparatus which processes X-ray transmission data collected by an X-ray rotational photographing
mechanism, comprising:
a memory which stores a plurality of pieces of human anatomy figure image data collected by photographing a subject before
the injection of a contrast media at a plurality of projection angles and a plurality of pieces of contrast image data collected
by photographing the subject after the injection of the contrast media at the plurality of projection angles;

a subtraction unit which subtracts the contrast image data from the human anatomy figure image data, which are pieces of image
data having the same projection angle concerning the photography, to generate contrast blood vessel figure data;

a first reconfiguration unit implemented by circuitry which executes reconfiguration processing based on the plurality of
pieces of contrast blood vessel figure data generated by the subtraction unit to create contrast blood vessel figure three-dimensional
image data;

a second reconfiguration unit implemented by circuitry which executes reconfiguration processing based on the plurality of
pieces of human anatomy figure data to generate human anatomy figure three-dimensional image data;

a black-and-white reverse processing unit implemented by circuitry which executes black-and-white reverse processing with
respect to the contrast blood vessel figure three-dimensional image data to generate capillary blood flow vessel figure three-dimensional
image data for enhancing a display of blood flow in capillary blood vessels over arteries and veins; and

a combination processing unit implemented by circuitry which combines the human anatomy figure three-dimensional image data
with the capillary blood flow vessel figure three-dimensional image data to generate combined image data.

US Pat. No. 9,314,161

MOVING OBJECT CONTOUR EXTRACTION APPARATUS, LEFT VENTRICLE IMAGE SEGMENTATION APPARATUS, MOVING OBJECT CONTOUR EXTRACTION METHOD AND LEFT VENTRICLE IMAGE SEGMENTATION METHOD

Kabushiki Kaisha Toshiba,...

1. A moving object contour extraction apparatus for extracting from a three-dimensional image time series contours of a moving
object which performs a deforming motion, the three-dimensional image time series comprising a plurality of three-dimensional
images acquired at a plurality of time points, each of the three-dimensional images consisting of a plurality of parallel
two-dimensional image slices, and the two-dimensional image slices located at the same location in the plurality of three-dimensional
images forming an image slice time series, the apparatus comprising:
a contour acquisition unit configured to acquire a contour of the moving object in each image slice; and
a contour correction unit configured to correct the contours of the moving object in the image slices of at least one image
slice time series based on motion trend information of the moving object in each of a plurality of the image slice time series,
the contour correction unit comprising:

a motion trend determination unit configured to determine motion trend information of the moving object in each image slice
time series;

a similarity calculation unit configured to calculate a similarity between the motion trend information of the moving object
in each image slice time series and reference motion trend information of the moving object; and

a correction execution unit configured to correct the contours of the moving object in the image slices of a certain image
slice time series if the similarity between the motion trend information of the moving object in the certain image slice time
series and the reference motion trend information is lower than a predetermined threshold.

US Pat. No. 9,299,926

NONVOLATILE MEMORY DEVICE USING A TUNNEL OXIDE LAYER AND OXYGEN BLOCKING LAYER AS A CURRENT LIMITER ELEMENT

Intermolecular, Inc., Sa...

1. A nonvolatile memory element comprising:
a first layer operable as a first electrode;
a second layer operable as a second electrode;
a third layer disposed between the first layer and the second layer,
wherein the third layer is operable as a variable resistance layer and comprises a non-stoichiometric metal oxide;
a fourth layer operable as a current limiting layer,
wherein the fourth layer comprises second metal oxide,
wherein the fourth layer is disposed between the first layer and the third layer; and
a fifth layer disposed between the third layer the fourth layer,
wherein the fifth layer comprises a metal oxy-nitride and blocks oxygen migration between the third layer and the fourth layer,
wherein the fifth layer is amorphous or polycrystalline and has a grain size of 30 nanometers of less.

US Pat. No. 9,184,379

CAPPING THIN-FILM RESISTORS TO CONTROL INTERFACE OXIDATION

Intermolecular, Inc., Sa...

1. A device, comprising:
a substrate;
a first layer formed over the substrate, the first layer operable as a first electrode;
a second layer formed over the first layer, the second layer operable as a second electrode;
a third layer formed between the first layer and the second layer, the third layer operable as a variable-resistance layer;
a fourth layer formed between the first layer and the second layer, the fourth layer operable as a constant-resistance layer;
and

a fifth layer formed in contact with the fourth layer and one of the first layer or the second layer, the fifth layer operable
as a cap layer;

wherein the fourth layer comprises a first transition metal, a first additional element, and one of oxygen or nitrogen;
wherein the fifth layer comprises the first transition metal and a second additional element; and
wherein an atomic percentage (at %) oxygen at an interface between the fifth layer and the fourth layer is less than 5% of
an atomic percentage (at %) oxygen in the fourth layer.

US Pat. No. 9,164,896

MEMORY SYSTEM STORING MANAGEMENT INFORMATION AND METHOD OF CONTROLLING SAME

Kabushiki Kaisha Toshiba,...

1. A memory system comprising:
a nonvolatile memory;
a memory controller configured to perform data management in the nonvolatile memory based on one part of first management
information,

wherein the memory controller includes:
a management-information storing unit configured to store a first log created before updating the first management information
and a second log created after updating the first management information, and to store the first management information in
the nonvolatile memory as second management information; and

in a case of a power cut, the management-information storing unit is configured to store the first management information
as third management information in the nonvolatile memory.

US Pat. No. 9,478,355

METHOD OF MANUFACTURING A CPP DEVICE WITH A PLURALITY OF METAL OXIDE TEMPLATES IN A CONFINING CURRENT PATH (CCP) SPACER

TDK Corporation, Tokyo (...

1. A method of forming a confining current path (CCP) spacer in a magnetic sensor structure, comprising:
(a) forming a first copper layer on a ferromagnetic layer;
(b) forming an amorphous layer made of metal, alloy, or metal oxide on said first Cu layer;
(c) forming a second copper layer with a thickness of 0 to 6 Angstroms on the amorphous layer;
(d) depositing an oxidizable layer on the second copper layer;
(e) performing a pre-ion treatment (PIT) followed by an ion-assisted oxidation (IAO) to transform the amorphous layer and
at least a portion of the first copper layer into a first metal oxide template having segregated Cu metal paths therein, and
to transform the oxidizable layer into a second metal oxide template having segregated Cu metal paths formed therein; and

(f) depositing a third Cu layer on the second metal oxide template.

US Pat. No. 9,427,783

POSTAL MATTER EJECTION APPARATUS WITH GAP SETTING UNIT ACCORDING TO POSTAL MATTER THICKNESS

KABUSHIKI KAISHA TOSHIBA,...

1. A postal matter ejection apparatus comprising:
a character recognition unit configured to recognize characters on the postal matters;
an ejection unit which ejects the postal matters one-by-one from a supply base on which the postal matters are set and supplies
each postal matter from the supply base to a conveyance unit;

a detection unit which detects the postal matter ejected by the ejection unit;
a reflective sensor which detects a thickness of the postal matter detected by the detection unit;
a thickness storage unit which stores thickness information detected by the reflective sensor;
an acquisition unit which acquires from the thickness storage unit a thickness of a preceding postal matter delivered to the
conveyance unit immediately before the postal matter ejected by the ejection unit;

a setting unit which, for each postal matter of a plurality of postal matters in sequence ejected by the ejection unit, sets
a gap between the preceding postal matter and the postal matter ejected by the ejection unit in accordance with the thickness
of the preceding postal matter acquired by the acquisition unit; and

an adjustment unit which adjusts timing for delivering the postal matter detected by the detection unit to the conveyance
unit in accordance with the gap set by the setting unit in accordance with the measured thickness of the preceding postal
matter acquired by the acquisition unit, wherein

the reflective sensor detects a thickness of the postal matter before the postal matter is delivered at the timing adjusted
by the adjustment unit.

US Pat. No. 9,429,136

CONTROL SYSTEM OF VARIABLE SPEED PUMPED STORAGE HYDROPOWER SYSTEM AND METHOD OF CONTROLLING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

6. A method of controlling a variable speed pumped storage hydropower system including a secondary excitation device configured
to apply a current to a secondary winding of a generator-motor, a flow rate adjusting valve control unit configured to control
an opening of a flow rate adjusting valve that adjusts a flow rate of a pump-turbine directly connected with the generator-motor,
and a speed control unit configured to generate a secondary current active power component command value of a secondary excitation
device, the method comprising:
an optimization processing process of generating a generator-motor output command value based on a demanded generator-motor
output, and calculating and output a flow rate adjusting valve opening demand value and a first command value from a head
value and the generator-motor output command value, the first command value including a slip command value, a rotational speed
command value, an angular velocity command value, or a secondary frequency command value, by a control system;

a speed control process of generating a secondary current active power component command value of the secondary excitation
device based on the first command value;

an output compensation process of calculating a compensation value of the secondary current active power component command
value;

a mechanical output compensation process of calculating at least either a compensation value of the opening of the flow rate
adjusting valve or a compensation value of the generator-motor output from a result calculated in the output compensation
process; and

an output control process of generating a flow rate adjusting valve opening command value based on the generator-motor output
command value, the flow rate adjusting valve opening demand value, the compensation value calculated in the mechanical output
compensation process, and the output detection value of the generator-motor, and outputting the flow rate adjusting valve
opening command value to the flow rate adjusting valve control unit.

US Pat. No. 9,374,879

X-RAY EQUIPMENT

Kabushiki Kaisha Toshiba,...

1. X-ray equipment comprising:
a plurality of pressure rising units that are connected to a battery unit and generate direct current voltage, each of the
pressure rising units including a condenser;

a switching unit that switches over said plurality of pressure rising units and supplies said direct current voltage to a
X-ray generating unit; and

a switching control unit that transmits switching instructions to said switching unit for switching over said pressure rising
units after receiving voltage supply instructions with respect to the X-ray generating unit until said voltage supply instructions
terminate, wherein

said switching control unit controls the commencing of charging of a condenser that has been discharged to less than a predetermined
value in the pressure rising units in parallel to controlling the discharge of a condenser that has been charged to more than
the predetermined value inside the pressure rising units by said switching instructions; and

an X-ray tube that generates X-rays; and
a thermoelectricity converter that converts heat energy of the X-ray tube into electrical energy, wherein
said switching control unit uses the electrical energy converted by the thermoelectricy converter for charging of the discharged
condenser.

US Pat. No. 9,287,225

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Kabushiki Kaisha Toshiba,...

1. A method of manufacturing a semiconductor device, comprising:
forming an opening in a first substrate;
forming a stopper layer on a surface of the first substrate in a region surrounding the opening;
forming a first metal in the opening and on the stopper layer;
polishing the first metal with a first chemical mechanical polishing and stopping on the stopping layer to form a first connection
electrode in the first substrate;

polishing the first substrate using a second chemical mechanical polishing in which a polishing rate of the first metal is
less than that of a region surrounding the first connection electrode thereby causing the first connection electrode to protrude
from the first substrate;

stacking the first substrate and a second substrate that includes a second connection electrode such that the first and second
connection electrodes face each other; and

diffusion-bonding the first and second connection electrodes to each other by pressing and heating the first and second substrates
to a temperature at or below the melting point of the first metal.

US Pat. No. 9,279,991

LIQUID CRYSTAL OPTICAL ELEMENT AND IMAGE DISPLAY DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A liquid crystal optical element comprising:
a first substrate having first and second regions which are arranged to sandwich a boundary line;
a second substrate arranged in opposition to the first substrate;
a liquid crystal layer provided between the first and second substrates;
first electrodes provided in each of the first and second regions, the first electrodes extending in a first direction intersecting
with the boundary line, the first electrodes being arranged in a second direction intersecting with the first direction;

a first extension line electrically connected to the first electrodes and extending along the boundary line; and
second electrodes provided on the second substrate and arranged in opposition to the first and second regions,
wherein the first and second regions are arranged in a third direction, the third direction intersecting with the boundary
line, and

the first direction intersects with the third direction and the boundary line.

US Pat. No. 9,269,447

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A nonvolatile semiconductor memory device, comprising:
a cell array including a source line, a plurality of bit lines, a plurality of word lines intersecting the plurality of bit
lines, and a plurality of cell strings electrically connected between the source line and the plurality of bit lines, each
of the cell strings being configured from a plurality of memory cells connected in series to each be connected to one of the
word lines; and

a control unit that performs a data write/erase/read on the memory cells,
the cell array being divided into a plurality of blocks including a target block, each of the blocks including first through
N-th pages (where N is an integer of 2 or more), each of the pages being configured by a plurality of the memory cells connected
to one of the word lines,

the control unit executing the data write/read in a unit of the page, and executing the data erase in a unit of the block,
and

the control unit, in the data write, determining at least one of:
a first requirement that the number of times of the data read on first through n1-th pages (where n1 is an integer of 1 to N?1) of the target block executed after the most recent data erase on the target block, is less than
a reference number of times; and

a second requirement that the number of memory cells whose threshold voltage is higher than a reference voltage, of the plurality
of memory cells of a reference page of n1+1-th through N-th pages of the target block, is less than a reference number, and

when the determined requirement is satisfied, writing additional data to the n1+1-th through N-th pages of the target block.

US Pat. No. 9,192,356

ULTRASOUND DIAGNOSIS APPARATUS

Kabushiki Kaisha Toshiba,...

1. An ultrasound diagnosis apparatus that includes an ultrasound probe that transmits and receives ultrasound waves to and
from a subject, and generates and displays images based on reception results from the ultrasound probe, comprising:
a memory that stores association information indicating association of a diagnosis region of the subject with at least one
examination condition comprising at least one of image quality conditions, and an application used for diagnosis of the diagnosis
region;

a probe position sensor configured to obtain position information of the probe on a surface of the subject;
a detector configured to detect one diagnosis region based on the obtained position information of the ultrasound probe;
a user interface configured to input body-type information of the subject; and
processing circuity configured to select, from a plurality of possible examination conditions, at least one examination condition
associated with the at least one diagnosis region detected by the detector based on the association information stored in
said memory, and configured to perform the transmission and reception waves and the image generation based on the selected
at least one examination condition, and wherein

the association information includes:
first association information that associates positions in the real space with coordinates in a subject coordinate system
set for the subject; and

second association information that associates each of a plurality of diagnosis regions in the standard coordinate system
with the examination conditions, and wherein

the processing circuitry identifies coordinates in the standard coordinate system corresponding to the position detected by
the detector based on the first association information and the input body-type information, and selects examination conditions
corresponding to the region in the standard coordinate system containing the identified coordinates based on the second association
information.

US Pat. No. 9,199,500

IMAGE FORMING APPARATUS AND IMAGE ERASING APPARATUS

Kabushiki Kaisha Toshiba,...

1. An image forming apparatus, comprising:
a scanning unit configured to scan a surface of a sheet;
a controller configured to determine a number of times the surface of the sheet has been subject to an image erasing process
based on the scanned surface, and calculate a fee to be charged for forming a new image on the surface based on the determined
number; and

an image forming unit configured to form the new image on the surface of the sheet.

US Pat. No. 9,171,365

DISTANCE DRIVEN COMPUTATION BALANCING

Kabushiki Kaisha Toshiba,...

1. A method of reducing computation time in distance-driven reprojection from an image space having a plurality of pixels
for a scanning system, the scanning system including a detector having a plurality of detector elements, the method comprising:
determining, for a given view and for each detector element of the plurality of detector elements, a projection location of
each edge of the detector element onto a predetermined reference axis;

determining, for the given view and for each pixel of the plurality of pixels, a projection location of each edge of the pixel
onto the predetermined axis;

identifying, for each detector element, contributing pixels having corresponding pixel values that contribute to a detector
value of the detector element, based on the projection location of each edge of the detector element and the projection location
of each edge of the plurality of pixels;

scheduling parallel computations for the detector elements in each processing cycle of the scanning system, based on a number
of processors included in the scanning system; and

calculating, based on the scheduled parallel computations, the detector value of each detector element as a sum, over the
total number of contributing pixels, of the corresponding pixel values of the contributing pixels, each pixel value being
weighted by a corresponding weight.

US Pat. No. 9,134,419

ULTRASONIC DIAGNOSIS APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. An ultrasonic diagnosis apparatus, comprising:
a plurality of ultrasound transducers constructing a main array, the main array divided into sub arrays consisting of two
or more ultrasound transducers;

a control circuitry configured to
set an aperture consisting of some of the sub arrays, and
set a reception delay pattern with respect to each of the some sub arrays constructing the aperture;
a reception delay and adding circuitry configured to
perform a reception delay addictive processing for echo signals acquired through each of the some sub arrays constructing
the aperture using the set reception delay with respect to each of the some sub arrays constructing the aperture, and

output signals as a result of the reception delay additive processing; and
a reception processing circuitry configured to perform a beam forming by using the signals; wherein
the size of the aperture does not change during a single receiving period;
the reception delay pattern does not change during the single receiving period;
the reception delay pattern changes in response to the change of the size of the aperture; and
the reception delay pattern set to the sub array arranged inside of the aperture differs from the reception delay pattern
set to the sub array arranged outside of the aperture.

US Pat. No. 9,057,569

CERAMIC HEAT SINK MATERIAL FOR PRESSURE CONTACT STRUCTURE AND SEMICONDUCTOR MODULE USING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A ceramic heat sink material for a pressure contact structure configured by providing a resin layer on a ceramic substrate,
which is any one of a silicon nitride substrate, an aluminum oxide substrate, and an aluminum nitride substrate and has a
surface roughness Ra in a range of 0.1 to 5 ?m and a three-point bending strength of 300 MPa or more, wherein the resin layer
has durometer (Shore) hardness (A-type) of 70 or less, and an average value of gaps existing in an interface between the ceramic
substrate and the resin layer is 3 ?m or less.

US Pat. No. 9,420,725

AIR CONDITIONING APPARATUS AND AIR CONDITIONING CONTROL METHOD

Kabushiki Kaisha Toshiba,...

1. An air conditioning apparatus comprising:
an indoor unit that introduces at least one of outdoor air and return air from an air conditioning control target, and discharges
the introduced air to the air conditioning control target as supply air, and

an air conditioning controller; wherein
the indoor unit comprises:
a first space comprising an outdoor air introducing unit introducing the outdoor air, a first return air introducing unit
introducing the return air from the air conditioning control target, a humidifier, and a cooler; and

a second space comprising a second return air introducing unit introducing the return air; and
the air conditioning controller is configured to perform one or more processes in response to an air condition of the outdoor
air to control temperature and humidity of the supply air to be within a target range of temperature, absolute humidity, and
relative humidity that is set in advance; wherein

the one or more processes comprises any one of or a combination of:
controlling an outdoor air introduction rate based on an opening degree of the first return air introducing unit, the second
return air introducing unit, and the outdoor air introducing unit;

controlling a cooling quantity by the cooler; and
controlling a humidification quantity by the humidifier; and
when the air condition of the outdoor air corresponds to a first range, the air conditioning controller is configured:
to close the first return air introducing unit and open the outdoor air introducing unit and the second return air introducing
unit;

to cool and humidify, by the cooler and the humidifier, the outdoor air introduced from the opened outdoor air introducing
unit;

to mix the cooled and humidified outdoor air with the return air introduced from the opened second return air introducing
unit to generate the supply air of which temperature and humidity are within the target range; wherein

the first range is:
larger than an upper limit value of absolute humidity of the target range; and
equal to or less than a value of enthalpy corresponding to the upper limit value of the absolute humidity of the target range
and temperature of the return air.

US Pat. No. 9,292,732

IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD AND COMPUTER PROGRAM PRODUCT

Kabushiki Kaisha Toshiba,...

1. An image processing apparatus comprising:
circuitry that performs at least:
obtaining depth information for each position in an entire image within a frame; and
switching between a first sharpening process and a second sharpening process in accordance with whether the image contains
a predetermined area, the first sharpening process performing non-uniform sharpening on the entire image including the predetermined
area and any area other than the predetermined area on the basis of the depth information, the second sharpening process performing
uniform sharpening on the entire image including the predetermined area and any area other than the predetermined area.

US Pat. No. 9,281,345

RESISTANCE CHANGE TYPE MEMORY DEVICE WITH THREE-DIMENSIONAL STRUCTURE

Kabushiki Kaisha Toshiba,...

1. A non-volatile memory device comprising:
a first wiring extending in a first direction;
a second wiring extending in a second direction orthogonal to the first direction, and electrically connected to the first
wiring;

third wirings extending in a third direction orthogonal to the second direction, a pair of the third wirings being aligned
in the second direction on both sides of the second wiring, and facing each other across the second wiring;

a first memory provided between one wiring included in the pair of the third wirings and the second wiring; and
a second memory provided between another wiring included in the pair of the third wirings and the second wiring, and
the second wiring having a blocking portion between a first portion in contact with the first memory and a second portion
in contact with the second memory.

US Pat. No. 9,207,299

MAGNETIC RESONANCE IMAGING SYSTEM AND MAGNETIC RESONANCE IMAGING APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. A magnetic resonance imaging (MRI) apparatus configured for use with a separate heating device which heats a specific region
of an object to be examined in addition to any heat that may be inherently generated therein by an MR imaging process, said
MRI apparatus comprising:
MRI system components including at least one radio frequency (RF) coil coupled to an imaging volume within a static field
magnet and gradient field coils, and an MRI computer system coupled to control said components, said MRI computer system programmed
to:

execute a plurality of successive MRI data acquisition scan operations wherein gradient fields and RF fields are applied to
the object placed in the imaging volume and receive magnetic resonance RF signals generated in a specific region of the object;

control the plurality of MRI data acquisition scan operations in synchronism with each of successive heating cycles by the
separate heating device; and

generate measurement temperature data based on phase differences between magnetic resonance RF signals obtained by the plurality
of MRI data acquisition scan operations;

wherein
the plurality of MRI data acquisition scan operations are executed at least twice in a single heating cycle period and said
magnetic resonance RF signals are received at different timings in synchronization with heating cycles by the separate heating
device, and

(a) a reference temperature change pattern is generated based upon phase differences between said received magnetic resonance
RF signals at the different timings, said reference temperature change pattern corresponding to a temperature change of the
specific region with respect to a heating cycle by the separate heating device, and (b) a temperature change relating to the
specific region is subsequently estimated based upon (i) the reference temperature change pattern and (ii) the measurement
temperature data.

US Pat. No. 9,201,139

ULTRASONIC DIAGNOSTIC APPARATUS, ULTRASONIC IMAGE PROCESSING APPARATUS, AND MEDICAL IMAGE DIAGNOSTIC APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. An ultrasonic diagnostic apparatus, comprising:
an ultrasonic transmission/reception circuit configured to control repeated transmission of ultrasonic waves to a scan area,
which is a two-dimensional or three-dimensional area of an object to which a contrast medium is administered, throughout an
analysis period, control reception of reflected waves from the scan area, and acquire temporal sequence ultrasonic data corresponding
to the scan area;

a control processor configured to
generate a luminance time curve associated with at least one analysis area included in the scan area by using the temporal
sequence ultrasonic data in each phase in the analysis period,

determine a stagnant time of the contrast medium associated with said at least one analysis area using the generated luminance
time curve,

generate a plurality of temporal sequence images based on the temporal sequence ultrasonic data,
analyze a brightness value of at least one analysis area in each of the plurality of temporal sequence images,
determine the stagnant time corresponding to a period when the brightness value of the at least one analysis area is exceeding
a predetermined value,

assign a hue corresponding to the determined stagnant time for the at least one analysis area, and
generate a stagnant time image based on the hue; and
a display configured to display the stagnant time image.

US Pat. No. 9,150,114

STORAGE SYSTEM

Kabushiki Kaisha Toshiba,...

1. A storage system comprising:
a plurality of storage devices configured to execute communication at a predetermined communication speed;
a charge/discharge controller configured to convert a DC power output from the plurality of storage devices into a DC power
of a predetermined magnitude and output the DC power, and charge the storage devices with the DC power of the predetermined
magnitude;

an AC/DC converter configured to convert the DC power from the charge/discharge controller into an AC power, convert an AC
power supplied from a distribution system into a DC power and supply the DC power to the charge/discharge controller;

a controller configured to control the charge/discharge controller and the AC/DC converter;
a converter comprising a communication speed setting module configured to set a communication speed for communication with
the plurality of storage devices, and intervening between the plurality of storage devices and the charge/discharge controller;

an Ethernet communication line to which the converter and the controller are connected;
a second converter intervening between the charge/discharge controller and the Ethernet communication line, configured to
create an IP address of the charge/discharge controller;

a third converter intervening between the AC/DC converter and the Ethernet communication line, configured to create an IP
address of the AC/DC converter; and

connection units configured to make connection between the Ethernet communication line and an external device,
wherein each of the storage devices executes communication by using an IP address and the converter comprises an Ethernet
converter configured to create the IP address of each of the storage devices.

US Pat. No. 9,065,040

CONTROLLING COMPOSITION OF MULTIPLE OXIDES IN RESISTIVE SWITCHING LAYERS USING ATOMIC LAYER DEPOSITION

Intermolecular, Inc., Sa...

1. A device comprising:
a first layer comprising a first conductive material,
wherein the first layer is operable as a first electrode;
a second layer comprising a second conductive material,
wherein the second layer is operable as a second electrode; and
a third layer disposed between the first layer the second layer,
wherein the third layer is operable as a variable resistance layer switchable between a high resistance state and a low resistance
state,

wherein the third layer comprises a first nanolaminate structure and a second nanolaminate structure,
wherein each of the first nanolaminate structure comprises a first oxide of a first element and a second oxide of a second
element, and

wherein an average atomic ratio of the second element to the first element in the first nanolaminate structure is greater
than an average atomic ratio of the second element to the first element in the second nanolaminate structure.

US Pat. No. 9,311,033

IMAGE PROCESSING APPARATUS SYSTEM FOR STORING AND RETRIEVING SETTING INFORMATION

Kabushiki Kaisha Toshiba,...

1. An image processing apparatus comprising:
a processor configured as:
an authentication unit that authenticates a user and logs in the user when the user is authenticated,
an input unit that receives an input from the user indicating a setting for performing an image processing function of the
image processing apparatus,

a setting management unit that causes a storage unit to store setting information corresponding to the setting indicated by
the input from the user when the user logs out, and

a setting state control unit that retrieves the setting information of the user and sets a setting state of the image processing
apparatus for performing the image processing function according to the retrieved setting information when the authentication
unit logs in the user, wherein

the storage unit is selected by the setting management unit from one of an internal storage unit and an external storage unit,
based on a communication status between the image processing apparatus and the external storage unit.

US Pat. No. 9,189,848

MEDICAL IMAGE PROCESSING APPARATUS, MEDICAL IMAGE PROCESSING METHOD AND X-RAY IMAGING APPARATUS

Kabushiki Kaisha Toshiba,...

6. A medical image processing method comprising:
obtaining X-ray contrast image data and time-series frames of X-ray fluoroscopic image data;
detecting a first position of a marker from the X-ray contrast image data and a second position of the marker from a frame
of the X-ray fluoroscopic image data, the marker being attached to a device;

generating corrected X-ray contrast image data as mask image data, to be combined with each of the time-series frames of the
X-ray fluoroscopic image data, with a movement correction between the X-ray contrast image data and the frame of the X-ray
fluoroscopic image data, the first position after the movement correction being regarded to be same as the second position
after the movement correction; and

generating frames of X-ray image data for a display by combining the corrected X-ray contrast image data with each of the
time-series frames of the X-ray fluoroscopic image data.

US Pat. No. 9,065,064

MANUFACTURING METHOD AND MANUFACTURING APPARATUS OF FUNCTIONAL ELEMENT

KABUSHIKI KAISHA TOSHIBA,...

1. A manufacturing method for a functional element, comprising:
forming a first electrode and a second electrode facing the first electrode;
filling a gap between the first electrode and the second electrode with a solvent including hydrogen gas and organic molecules
dispersed therein; and

forming an organic layer containing the organic molecules between the first electrode and the second electrode.

US Pat. No. 9,050,058

X-RAY DIAGNOSTIC SYSTEM AND X-RAY DIAGNOSTIC METHOD

Kabushiki Kaisha Toshiba,...

1. An X-ray diagnostic system comprising:
a tube current setting section for setting a tube current for taking a scanogram of a subject;
an X-ray tube for radiating an X-ray to the subject on the basis of the tube current for taking the scanogram, the tube current
set by the tube current setting section;

an X-ray detector for detecting the X-ray radiated by the X-ray tube and transmitted through the subject;
a data collector for collecting X-ray dose distribution data, which shows the dose distribution of the X-ray detected by the
X-ray detector;

an image processor for creating the scanogram from the X-ray dose distribution data collected by the data collector;
a genuine data generator for generating genuine data showing the dose distribution of the X-ray detected by the X-ray detector,
from the scanogram created by the image processor, or from raw data produced in a process of creating the scanogram by the
image processor;

a threshold value setting section for setting a threshold value for the genuine data generated by the genuine data generator;
and

a tube current adjustor for adjusting a tube current for taking a tomographic image of the subject in accordance with a comparison
between the X-ray dose in the genuine data generated by the genuine data generator and the threshold value set by the threshold
value setting section.

US Pat. No. 9,413,729

SYMMETRIC ENCRYPTION APPARATUS AND STORAGE MEDIUM, AND SYMMETRIC DECRYPTION APPARATUS AND STORAGE MEDIUM

KABUSHIKI KAISHA TOSHIBA,...

1. A symmetric encryption apparatus comprising:
a storage unit configured to store a symmetric key formed from a plurality of elements of a first polynomial ring;
a plaintext acceptance unit configured to accept input of plaintext information;
a plaintext polynomial generation unit configured to generate a plaintext polynomial by embedding the plaintext information
whose input has been accepted in at least one of terms of a polynomial in a subspace of the first polynomial ring;

a mask polynomial generation unit configured to generate a mask polynomial having the symmetric key as a solution based on
a second commutative ring defined over the first polynomial ring; and

an encryption unit configured to generate a ciphertext using the plaintext polynomial and the mask polynomial.

US Pat. No. 9,367,076

SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor device, comprising a plurality of semiconductor chips disposed on a substrate,
one of the semiconductor chips comprising:
an internal power supply voltage generating circuit that generates an internal power supply voltage based on an external power
supply;

a power supply line that supplies the internal power supply voltage;
an internal power supply pad connected to the power supply line; and
a stabilizing capacitance connected to the power supply line, and
the internal power supply pad being electrically short-circuited with the internal power supply pad included in another semiconductor
chip.

US Pat. No. 9,274,066

METHOD FOR SPECTRAL CT LOCAL TOMOGRAPHY

Kabushiki Kaisha Toshiba,...

1. A method of performing spectral reconstruction for a region of interest (ROI) of an object, the method comprising:
designating the ROI within the object, the ROI being located within a scan field of view (FOV) of a combined third- and fourth-generation
computed tomography (CT) scanner, the CT scanner including a plurality of fixed photon-counting detectors (PCDs), and an X-ray
source that rotates in a trajectory about the object in synchronization with an energy-integrating detector;

determining, for each PCD of the plurality of PCDs, as a function of a position of the X-ray source along the trajectory,
an on/off timing schedule of the PCD, based on a size and location of the designated ROI;

performing a scan of the object by rotating the X-ray source and the energy-integrating detector to obtain a first data set
from the energy-integrating detector and a second data set from the plurality of PCDs, wherein the step of performing the
scan includes turning each PCD on and off according to the determined on/off timing schedule of the PCD; and

performing spectral reconstruction within the ROI using the first and second data sets to obtain spectral images of the ROI.

US Pat. No. 9,250,802

SHAPING DEVICE

Kabushiki Kaisha Toshiba,...

9. A shaping device comprising:
an acquiring unit configured to acquire a plurality of strokes handwritten by a user; and
a display unit configured to display a result of shaping the strokes into a target shape when there is a combination having
a first likelihood representing a probability that the combination related to the target graphic equal to or higher than a
first threshold and a second likelihood representing a probability that the combination related to an incomplete shape equal
to or lower than a second threshold in multiple combinations, the combination being one of multiple combinations of strokes,
each combination including one or more of the strokes.

US Pat. No. 9,089,253

ULTRASONIC DIAGNOSTIC APPARATUS AND METHOD OF CONTROLLING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. An ultrasonic diagnostic apparatus, comprising:
a scan controller configured to scan sub volumes, each sub volume being obtained by dividing a full 3D volume to be imaged,
while changing the sub volume every ECG trigger signal so as to acquire a plurality of data sets respectively corresponding
to a plurality of heart beats, each data set of the plurality of data sets corresponding to one of the plurality of heart
beats and including a plurality of sub data sets, each sub data set within the data set being acquired at a different time
phase; and

image generation circuitry configured
to select specific sub data sets, including one for each sub volume, for generating an image of the full 3D volume among the
acquired plurality of data sets by maximizing a spatial correlation between adjacent sub data sets in the specific sub data
sets, and

to connect the specific sub data sets to generate images of the full 3D volume at the different time phases.

US Pat. No. 9,913,367

WIRING BOARD AND METHOD OF MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A wiring board comprising:
a through via;
a first insulating film disposed around the through via;
a second insulating film disposed around the first insulating film, the second insulating film having a relative permittivity
lower than a relative permittivity of the first insulating film;

a third insulating film disposed around the second insulating film, the third insulating film having a relative permittivity
higher than the relative permittivity of the second insulating film; and

a resin disposed around the third insulating film, the resin including fillers.

US Pat. No. 9,416,683

CARBON DIOXIDE RECOVERY METHOD AND CARBON-DIOXIDE-RECOVERY-TYPE STEAM POWER GENERATION SYSTEM

KABUSHIKI KAISHA TOSHIBA,...

1. A carbon-dioxide-recovery-type steam power generation system, comprising:
a boiler that produces steam and generates an exhaust gas by combusting fuel;
a first turbine that is connected to a generator and is rotationally driven by the steam supplied from the boiler;
an absorption tower that is supplied with the exhaust gas from the boiler and allows carbon dioxide contained in the exhaust
gas to be absorbed into an absorption liquid;

a regeneration tower that is supplied with the absorption liquid absorbing the carbon dioxide from the absorption tower, discharges
a carbon dioxide gas from the absorption liquid, and discharges the carbon dioxide gas;

a reboiler that heats the absorption liquid from the regeneration tower and supplies the generated steam to the regeneration
tower;

a condenser that removes moisture from the carbon dioxide gas, discharged from the regeneration tower, by condensing the carbon
dioxide gas using a cooling medium;

a compressor that compresses the carbon dioxide gas from which the moisture is removed by the condenser; and
a second turbine that drives the compressor,
wherein steam produced by the cooling medium recovering the heat from the carbon dioxide gas in the condenser is supplied
to the first turbine or the second turbine.

US Pat. No. 9,391,070

SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor device comprising:
a first electrode;
a first region including
a first semiconductor layer of a first conductivity type provided on the first electrode,
a second semiconductor layer of a second conductivity type provided over the first semiconductor layer,
a third semiconductor layer of the first conductivity type provided on the second semiconductor layer,
a fourth semiconductor layer of the second conductivity type selectively provided on the third semiconductor layer, and
a gate electrode extending through the third semiconductor layer and the fourth semiconductor layer and terminating inwardly
of the second semiconductor layer, and separated from the second, third and fourth semiconductor layers by a gate insulating
film;

a second electrode provided on the fourth semiconductor layer; and
a second region adjacent to the first region, including
a fifth semiconductor layer of the second conductivity type provided between the first electrode and the second semiconductor
layer and adjacent to the first semiconductor layer,

a sixth semiconductor layer of the first conductivity type provided on the second semiconductor layer in contact with the
second electrode, and

a seventh semiconductor layer of the first conductivity type positioned in the second semiconductor layer and the sixth semiconductor
layer such that the furthest extent thereof inwardly of the second semiconductor layer is closer to the first electrode than
the bottom portion of the gate insulating film and the sixth semiconductor layer are.

US Pat. No. 9,330,443

NOISE REDUCTION IN IMAGE DOMAIN FOR SPECTRAL COMPUTED TOMOGRAPHY

KABUSHIKI KAISHA TOSHIBA,...

1. An apparatus, comprising:
processing circuitry configured to
obtain a plurality of basis images that are combined to generate a target image;
de-noise the basis images using a noise-reduction method to generate de-noised basis images;
calculate noise maps of the basis images by subtracting the de-noised basis images from the basis images;
calculate a weight for each of the noise maps using the target image and the calculated noise maps; and
generate a reduced-noise target image using the target image, the calculated noise maps, and the calculated weights.

US Pat. No. 9,293,212

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING A PLURALITY OF NAND STRINGS IN A MEMORY CELL ARRAY

KABUSHIKI KAISHA TOSHIBA,...

1. A nonvolatile semiconductor memory device comprising:
a memory cell array comprising a plurality of NAND strings arranged therein, each NAND string comprising a memory string comprising
a plurality of memory cells connected in series, and a first select transistor and a second select transistor connected to
respective two ends of the memory string,

a plurality of word lines connected to respective control gate electrodes of the memory cells;
a plurality of bit lines connected to respective first ends of the NAND strings;
a source line connected to second ends of the NAND strings; and
a control circuit performing reading of data of the memory cells,
the memory cell array comprising a ROM area for data read and a normal storage area capable of arbitrary write/erase of data,
the control circuit being configured to apply, when reading data of a first selected memory cell provided in the ROM area,
a first read voltage to a first selected word line connected to the first selected memory cell, and apply to a first non-selected
word line connected to a first non-selected memory cell provided in the ROM area, a first read pass voltage for rendering
conductive regardless of data held in the first non-selected memory cell, thus allowing for a ROM area reading operation of
reading a threshold voltage set in the first selected memory cell,

the control circuit being also configured to apply, when reading data of a second selected memory cell provided in the normal
storage area, a second read voltage to a second selected word line connected to the second selected memory cell, and apply
to a second non-selected word line connected to a second non-selected memory cell provided in the normal storage area, the
second non-selected memory cell storing data of a same bit number as data of the first non-selected memory cell, a second
read pass voltage for rendering conductive regardless of data held in the second non-selected memory cell, thus allowing for
a normal storage area reading operation of reading a threshold voltage set in the second selected memory cell, and

the first read pass voltage being lower than the second read pass voltage.

US Pat. No. 9,083,883

CAMERA MODULE, ELECTRONIC APPARATUS, AND PHOTOGRAPHING METHOD FOR IMAGE STABILIZATION AND INCREASING RESOLUTION

Kabushiki Kaisha Toshiba,...

1. A camera module comprising:
an image pickup optical system into which a lens is assembled;
an image sensor configured to take an image of an object imaged by the image pickup optical system;
an image stabilization section configured to perform an image stabilization by an adjustment of a position of the lens;
a resolution reconstruction section configured to perform a resolution reconstruction on the image obtained by an image-taking
by the image sensor;

a scaling section configured to perform a scaling on the image; and
a superposing section configured to superpose a plurality of images obtained by the image-taking,
wherein in an image-taking mode for obtaining a higher resolution than a resolution corresponding to pixel number of the image
sensor,

the image stabilization section adjusts the position of the lens such that a second image is moved by a movement less than
a length of one pixel relative to first image, the second image being obtained in succession to the first image after the
first image is obtained by the image-taking,

the resolution reconstruction section performs the resolution reconstruction on the first image and the second image,
the scaling section performs upscaling on the first image and the second image by the same scale factor,
the superposing section superposes the first image and the second image that have undergone the resolution reconstruction
and the upscaling,

the scaling section performs downscaling on an image obtained by the superposing to a size before the upscaling, and
in the case where the image stabilization section detects movement of the camera module upon adjusting the position of the
lens, the image stabilization section performs the image stabilization by deducting the movement.