US Pat. No. 10,642,685

CACHE MEMORY AND PROCESSOR SYSTEM

Kioxia Corporation, Toky...

1. A cache memory comprising:cache memory circuitry comprising a nonvolatile memory cell to store a data;
error correction circuitry to generate a redundancy code of the data stored in the nonvolatile memory cell;
a first redundancy code storage comprising a nonvolatile memory cell capable of storing the redundancy code generated by the error correction circuitry;
a second redundancy code storage comprising a volatile memory cell capable of storing the redundancy code from the first redundancy code storage; and
a copy address storage to store an address corresponding to data copied from the first redundancy code storage to the second redundancy code storage when the processor core restarts operation,
wherein the error correction circuitry comprises:
state determination circuitry to determine a state of whether a processor core is operating or stopped based on the address stored in the copy address storage; and
a redundancy code flow controller to control reading and writing of the redundancy code in the first redundancy code storage and the second redundancy code storage based on the state determined by the state determination circuitry,
wherein the second redundancy code storage is used for storing and reading the redundancy code during an operation of the processor core, and
wherein the redundancy code flow controller controls copying of the redundancy code from the second redundancy code storage into the first redundancy code storage when the processor core stops the operation, and then controls copying of the redundancy code from the first redundancy code storage into the second redundancy code storage when the processor core restarts the operation.

US Pat. No. 10,741,443

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Kioxia Corporation, Toky...

1. A semiconductor device comprising:a co-catalyst layer above a surface of a semiconductor substrate, the co-catalyst layer comprising a face-centered cubic structure or a hexagonal close-packed structure, or an amorphous structure or a microcrystalline structure, wherein the co-catalyst layer is configured such that a (111) face of the face-centered cubic structure or a (002) face of the hexagonal close-packed structure is to be oriented parallel to the surface of the semiconductor when the co-catalyst layer comprises the face-centered cubic structure or the hexagonal close-packed structure;
a catalyst layer on the co-catalyst layer, the catalyst layer comprising a face-centered cubic structure or a hexagonal close-packed structure, or an amorphous structure or a microcrystalline structure, wherein the catalyst layer is configured such that a (111) face of the face-centered cubic structure or a (002) face of the hexagonal close-packed structure is to be oriented parallel to the surface of the semiconductor when the catalyst layer comprises the face-centered cubic structure or the hexagonal close-packed structure; and
a graphene layer on the catalyst layer,
wherein the catalyst layer further comprises a multilayer structure in which a first material layer and a second material layer are alternately stacked, the first material layer includes a first material as a catalyst, the second material layer includes a second material having a melting point higher than that of the first material, and the second material forms a eutectic with the first material, or the second material forms complete soluble with the first material.

US Pat. No. 10,957,400

MEMORY SYSTEM

KIOXIA CORPORATION, Toky...

1. A memory system comprising:a plurality of memory cells in which data is stored; and
a memory controller that is configured to:
execute a first reference read operation of performing a read on the plurality of memory cells by using one or more first reference read voltages,
execute a first counting process of generating a first histogram indicating a number of memory cells in different threshold voltage bins based on a result of the first reference read operation,
execute a first estimation process of estimating one or more actual read voltages based on the first histogram and a first estimation function,
execute a first actual read operation of reading the data by using the one or more actual read voltages estimated by the first estimation process, and
execute a second estimation process and a second actual read operation when the first actual read operation fails,
wherein the second estimation process is a process of estimating the one or more actual read voltages by using a second estimation function different from the first estimation function, and
the second actual read operation is a process of reading the data by using the one or more actual read voltages estimated by the second estimation process.

US Pat. No. 10,912,199

RESISTIVE PCB TRACES FOR IMPROVED STABILITY

Kioxia Corporation, Toky...

1. A method of running a printed circuit board (PCB) trace on a PCB comprising a plurality of PCB layers, the method comprising:forming a conductive trace on at least one of the plurality of PCB layers;
coupling a first portion of the conductive trace to a capacitor formed on at least one of the plurality of PCB layers;
coupling a second portion, different from the first portion, of the conductive trace to a conductive material formed within a first via extending through two or more of the plurality of PCB layers; and
configurably setting a length of a conductive path of the conductive trace according to a predetermined impedance by either cutting at least one of a plurality of trace segments, electrically connecting two or more locations on the conductive trace with a bridge, or electrically connecting two or more of a plurality of disconnected trace segments,
wherein
the capacitor is separated laterally in a plan view at a first distance from the first via;
the length of the conductive trace in the plan view is greater than the first distance; and
the conductive path of the conductive trace of the length has the predetermined impedance.

US Pat. No. 10,748,791

CHEMICAL LIQUID TREATMENT APPARATUS AND CHEMICAL LIQUID TREATMENT METHOD

KIOXIA CORPORATION, Toky...

1. A chemical liquid treatment apparatus comprising:processing chambers;
a chemical liquid feeder configured to cyclically feed a chemical liquid into the processing chambers;
a controller, when using a chemical liquid in which an effect thereof varies with a chemical liquid discharge time, being configured to calculate a variation of the effect of the chemical liquid based on the chemical liquid discharge time and being configured to modify the chemical liquid discharge time for each of the processing chambers based on the calculated variation of the effect of the chemical liquid and a cumulative time of the chemical liquid discharge time;
a chemical valve configured to replenish the chemical liquid with a replenishing chemical liquid for recovering the effect of the chemical liquid;
wherein the cumulative time of the chemical liquid discharge time is a sum of a time of chemical liquid discharge for each of the processing chambers obtained by measuring the time of chemical liquid discharge in each of the processing chambers;
wherein the chemical liquid feeder includes a chemical liquid tank configured to store the chemical liquid, a pump configured to suck out the chemical liquid from the chemical liquid tank, a supply path configured to feed the chemical liquid sucked out of the pump into the processing chambers, and a return path configured to return the chemical liquid collected from the processing chambers to the chemical liquid tank;
wherein the variation in the effect of the chemical liquid is kept within a predetermined variation range by replenishing the chemical liquid with the replenishing chemical liquid provided from the chemical valve;
wherein the chemical valve includes a replenishing chemical liquid tank configured to store the replenishing chemical liquid, a replenishing chemical liquid supply path configured to feed the replenishing chemical liquid from the replenishing chemical liquid tank to the chemical liquid tank, and a valve provided to the replenishing chemical liquid supply path;
wherein the valve is configured to open/close to provide a predetermined amount of the replenishing chemical liquid from the replenishing chemical liquid tank to the chemical liquid tank when the effect of the chemical liquid has reached an upper limit;
wherein a chemical liquid supply time for the workpiece to be subjected to a next chemical liquid treatment is changed according to the variation over time in the effect of the supplied chemical liquid in etching the workpiece and the cumulative chemical liquid discharge time in the processing chambers;
wherein the controller configured to calculate a chemical liquid treatment time based on an etch amount of a workpiece and a function representing a relation between the cumulative time of the chemical liquid discharge time and an etch rate;
wherein the function representing the relation between the cumulative time of the chemical liquid discharge time and the etch rate is obtained and stored in advance by the controller;
wherein an amount of chemical liquid corresponding to modified chemical liquid treatment time is fed to the workpiece in the processing chambers by the chemical liquid feeder; and
wherein each of the processing chambers configured to process the workpiece by feeding the chemical liquid to the workpiece.

US Pat. No. 11,094,698

SEMICONDUCTOR STORAGE DEVICE

Kioxia Corporation, Toky...


1. A semiconductor storage device comprising:a plurality of first wires provided above a surface of a semiconductor substrate to extend in a first direction;
a plurality of second wires provided above the first wires to extend in a second direction crossing the first direction;
a plurality of capacitor elements arranged every other intersection region among intersection regions between the first wires and the second wires as viewed from above the surface of the semiconductor substrate; and
a plurality of transistors provided above the capacitor elements to correspond thereto, respectively, wherein
each of the transistors includes a semiconductor pillar,
the semiconductor pillar penetrates through a corresponding one of the first wires,
one end of the semiconductor pillar is electrically connected to a corresponding one of the second wires,
the other end of the semiconductor pillar is electrically connected to one end of a corresponding one of the capacitor elements,
the other ends of the capacitor elements are connected in common, and
a first distance between two of the capacitor elements, which are adjacent to each other in the first direction, is narrower than a second distance between two of the capacitor elements, which are adjacent to each other in the second direction.

US Pat. No. 10,964,377

SEMICONDUCTOR STORAGE DEVICE

KIOXIA CORPORATION, Toky...

1. A semiconductor storage device comprising:a plurality of memory transistors including first, second, and third memory transistors;
a plurality of bit lines including first, second, and third bit lines electrically connected to the first, second, and third memory transistors, respectively;
a word line electrically connected to the first, second, and third memory transistors; and
a control circuit configured to perform a program operation to write data to the plurality of memory transistors,
wherein the program operation for writing data to the second and third memory transistors includes
raising a first voltage applied to the first bit line at a first timing,
raising a second voltage applied to the word line at a second timing after the first timing,
raising a third voltage applied to the second bit line at a third timing after the second timing,
raising a fourth voltage applied to the third bit line at a fourth timing after the third timing, and
lowering the first voltage at a fifth timing after the fourth timing, and
the first voltage is raised to a first predetermined voltage, and each of the third and fourth voltages is raised to a second predetermined voltage that is smaller than the first predetermined voltage.

US Pat. No. 10,916,559

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Kioxia Corporation, Toky...

1. A nonvolatile semiconductor memory device comprising:a plurality of electrode layers stacked in a first direction, the plurality of electrode layers including a first electrode layer;
a second electrode layer provided above the plurality of electrode layers in the first direction;
a third electrode layer provided above the plurality of electrode layers in the first direction, the second electrode layer and the third electrode layer being arranged in a second direction perpendicular to the first direction and isolated from each other;
a first semiconductor layer penetrating through the plurality of electrode layers and the second electrode layer;
a first charge storage portion provided between the first semiconductor layer and the first electrode layer;
a second semiconductor layer penetrating through the plurality of electrode layers and the third electrode layer;
a second charge storage portion provided between the second semiconductor layer and the first electrode layer;
a third semiconductor layer penetrating through the plurality of electrode layers and the second electrode layer, the first semiconductor layer and the third semiconductor layer being arranged in a third direction, the third direction being perpendicular to the first direction and different from the second direction; and
a third charge storage portion provided between the third semiconductor layer and the first electrode layer.

US Pat. No. 11,114,170

MEMORY SYSTEM

KIOXIA CORPORATION, Toky...


1. A semiconductor memory device comprising:a memory cell array including a plurality of memory cells, each memory cell being capable of storing data;
a sense circuit configured to sense the data stored in a memory cell of the plurality of memory cells;
a first data latch configured to latch data sensed from the memory cell by the sense circuit;
a second data latch configured to receive the data from the first data latch;
a status register configured to store information indicating whether the semiconductor memory device is in a ready state or in a busy state;
an input/output circuit configured to output from the semiconductor memory device the data received from the second data latch and the information received from the status register; and
a control circuit configured to control the status register to store the information indicating the busy state upon receipt of a read command and to control the status register to store the information indicating the ready state, before completion of transfer of the data sensed from the memory cell from the first data latch to the second data latch.

US Pat. No. 11,042,310

READING OF START-UP INFORMATION FROM DIFFERENT MEMORY REGIONS OF A MEMORY SYSTEM

KIOXIA CORPORATION, Toky...


1. A memory system comprising:a nonvolatile memory including a first memory region and a second memory region, the first memory region storing start-up data, the start-up data being to be used by the nonvolatile memory to start up the nonvolatile memory; and
a controller configured to:instruct the nonvolatile memory to copy the start-up data from the first memory region to the second memory region; and
issue at least one of a first command and a second command to the nonvolatile memory, the first command designating no address, the second command designating a first address, wherein

the nonvolatile memory is configured to:in response to the first command, read the start-up data from the first memory region; and,
in response to the second command, read the start-up data from the second memory region at the first address.


US Pat. No. 11,016,663

MEMORY SYSTEM

KIOXIA CORPORATION, Toky...

1. A memory system comprising:a nonvolatile memory;
a controller that includes an interface circuit configured to control an access to the nonvolatile memory; and
a temperature sensor for measuring a temperature of the memory system,
wherein the controller is configured to:
acquire a first temperature from the temperature sensor,
acquire a first parameter set corresponding to the first temperature from parameter information including a plurality of parameter sets respectively corresponding to a plurality of temperatures, and
set the first parameter set in the interface circuit.

US Pat. No. 11,011,699

SEMICONDUCTOR STORAGE DEVICE

KIOXIA CORPORATION, Toky...

1. A semiconductor storage device comprising:a control circuit;
a first wiring extending in a first direction;
a second wiring and a third wiring, each extending in the first direction and being adjacent to the first wiring in a second direction intersecting the first direction;
a fourth wiring extending in the second direction;
a fifth wiring and a sixth wiring, each extending in the second direction and being adjacent to the fourth wiring in the first direction;
a plurality of memory cells each having one end connected to one of the first to third wirings and the other end connected to one of the fourth to sixth wirings;
a voltage output circuit configured to output a first voltage, a second voltage higher than the first voltage, a third voltage higher than the first voltage, a fourth voltage higher than the second voltage and the third voltage, and a fifth voltage higher than the fourth voltage; and
a voltage transfer circuit connected to the first to sixth wirings and the voltage output circuit,
wherein, at a predetermined timing of a write operation for memory cells connected to the first wiring and the fourth wiring, the control circuit is configured to:
transfer the first voltage to the first wiring;
transfer the fourth voltage to the second wiring;
transfer the second voltage to the third wiring;
transfer the fifth voltage to the fourth wiring;
transfer the third voltage to the fifth wiring; and
transfer the third voltage to the sixth wiring.

US Pat. No. 11,011,211

SEMICONDUCTOR STORAGE DEVICE

KIOXIA CORPORATION, Toky...

1. A semiconductor storage device, comprising:a memory cell array including a plurality of memory cells and a plurality of bit lines connected to the plurality of memory cells;
a plurality of sense amplifier units that are respectively connected to the plurality of bit lines and that each include a first transistor connected to one of the bit lines, a second transistor connected to the first transistor via a first wiring, a sense transistor including a gate electrode connected to the second transistor via a second wiring, a third wiring connected to the sense transistor, a first latch circuit connected to the third wiring, and a voltage transfer circuit configured to conduct the first wiring to a first voltage supply line or a second voltage supply line according to a value latched by the first latch circuit;
a fourth wiring commonly connected to the third wirings of the plurality of sense amplifier units;
a cache memory including a fifth wiring connected to the fourth wiring and a plurality of second latch circuits connected to the fifth wiring;
a third transistor connected to the first wiring of a first sense amplifier unit among the plurality of sense amplifier units and the fifth wiring of the cache memory; and
a fourth transistor connected to the first wiring of a second sense amplifier unit among the plurality of sense amplifier units and the second wiring of the first sense amplifier unit.

US Pat. No. 10,998,497

SEMICONDUCTOR MEMORY DEVICE

KIOXIA CORPORATION, Toky...

1. A semiconductor memory device comprising:a control circuit;
a plurality of first wirings;
a plurality of second wirings intersecting the plurality of first wirings; and
a plurality of memory cells formed between the plurality of first wirings and the plurality of second wirings,
wherein the control circuit is configured to:
supply, in a set operation, a set pulse between one of the plurality of first wirings and one of the plurality of second wirings,
supply, in a reset operation, a reset pulse between one of the plurality of first wirings and one of the plurality of second wirings, and
supply, in a first operation, a first pulse between one of the plurality of first wirings and one of the plurality of second wirings, and
wherein the first pulse has (1) an amplitude larger than a larger one of an amplitude of the set pulse or an amplitude of the reset pulse, or (2) the same amplitude as the larger amplitude, and
the first pulse has a pulse width larger than a pulse width of the reset pulse.

US Pat. No. 10,910,068

MEMORY SYSTEM AND NONVOLATILE MEMORY

KIOXIA CORPORATION, Toky...

1. A memory system comprising:a nonvolatile memory including a plurality of memory cells at intersection locations of a plurality of stacked word lines and a memory pillar passing through the plurality of word lines in a stacking direction, the plurality of word lines including a first group of word lines stacked above a second group of word lines in the stacking direction; and
a controller configured to read data of a first memory cell in a first read mode and to read data of a second memory cell in a second read mode different from the first read mode, wherein
the first memory cell is at an intersection location of a word line that is in a boundary area of the first and second groups of word lines and the memory pillar, and the second memory cell is at an intersection location of a word line that is not located in the boundary area, wherein
the boundary area that includes the word line is adjacent to a location of the memory pillar where a width of the memory pillar in a direction perpendicular to the stacking direction of the memory pillar discontinuously changes along the stacking direction.

US Pat. No. 10,890,539

SEMICONDUCTOR DEFECT INSPECTION APPARATUS

KIOXIA CORPORATION, Toky...

1. A semiconductor defect inspection apparatus for inspecting a specimen including a semiconductor substrate having a surface on which a predetermined pattern is formed, comprising:an excitation light irradiator configured to irradiate the specimen with excitation light along an optical path from the irradiator to the specimen and such that the excitation light is obliquely incident at a predetermined incident angle;
a first polarization converter, disposed in the optical path, configured to convert the excitation light into s-polarized light;
a detector configured to detect photoluminescence light generated from the specimen when the excitation light is incident on the specimen; and
a defect analysis detector configured to detect a dislocation defect by analyzing a photoluminescence image obtained by photoelectrically converting the photoluminescence light.

US Pat. No. 11,049,573

SEMICONDUCTOR STORAGE DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor storage device comprising:a first memory cell and a second memory cell which are connected to each other in series;
a first word line which is connected to the first memory cell;
a second word line which is connected to the second memory cell; and
a control circuit,
wherein the control circuit is configured to charge a first node while applying a second voltage to the second word line and a first voltage to the first word line, to charge a second node on the basis of a voltage of the charged first node, to discharge the second node while applying the second voltage to the second word line and a third voltage to the first word line, and to read data from the first memory cell on the basis of voltages of the charged and discharged second node.

US Pat. No. 11,049,877

SEMICONDUCTOR MEMORY

KIOXIA CORPORATION, Toky...


1. A semiconductor memory comprising:a substrate;
a first stacked body including an alternating stack of first insulators and first conductors above the substrate, the first stacked body including a first region, a second region, and a third region provided in this order along a first direction parallel to a surface of the substrate;
a second stacked body including an alternating stack of second insulators and second conductors above the substrate, the second stacked body including a fourth region, a fifth region, and a sixth region provided in this order along the first direction, the fourth region being adjacent to the first region in a second direction, the fifth region being adjacent to the second region in the second direction, the sixth region being adjacent to the third region in the second direction, the second direction being parallel to the surface of the substrate;
a plurality of first pillars, each of the first pillars extending through the second region of the first stacked body, and having memory cell regions at intersections with the first conductors;
a plurality of second pillars, each of the second pillars extending through the fifth region of the second stacked body, and having memory cell regions at intersections with the second conductors;
a third stacked body including an alternating stack of third insulators and third conductors above the substrate, the third stacked body including a seventh region, an eighth region, and a ninth region provided in this order along the first direction, the seventh region being adjacent to the fourth region in the second direction, the eighth region being adjacent to the fifth region in the second direction, the ninth region being adjacent to the sixth region in the second direction;
a fourth stacked body including an alternating stack of fourth insulators and fourth conductors above the substrate, the fourth stacked body including a tenth region, an eleventh region, and a twelfth region provided in this order along the first direction, the tenth region being adjacent to the seventh region in the second direction, the eleventh region being adjacent to the eighth region in the second direction, the twelfth region being adjacent to the ninth region in the second direction;
a plurality of third pillars, each of the third pillars extending through the eighth region of the third stacked body;
a plurality of fourth pillars, each of the fourth pillars extending through the eleventh region of the fourth stacked body;
a columnar first contact provided in the first region on a lowermost one of the first conductors of the first stacked body;
a columnar second contact provided in the seventh region on a lowermost one of the third conductors of the third stacked body; and
a columnar third contact provided in the tenth region on a lowermost one of the fourth conductors of the fourth stacked body, wherein
no columnar contact is provided in the fourth region on a lowermost one of the second conductors of the second stacked body,
the lowermost one of the first conductors in the first region and the lowermost one of the second conductors in the fourth region are connected to each other,
the lowermost one of the first conductors in the second region and the lowermost one of the second conductors in the fifth region are not connected to each other,
the lowermost one of the first conductors in the third region and the lowermost one of the second conductors in the sixth region are connected to each other,
the lowermost one of the third conductors in the seventh region and the lowermost one of the fourth conductors in the tenth region are not connected to each other,
the lowermost one of the third conductors in the eighth region and the lowermost one of the fourth conductors in the eleventh region are not connected to each other,
the lowermost one of the third conductors in the ninth region and the lowermost one of the fourth conductors in the twelfth region are connected to each other.

US Pat. No. 11,043,964

MEMORY SYSTEM, PACKET PROTECTION CIRCUIT, AND CRC CALCULATION METHOD

KIOXIA CORPORATION, Toky...


1. A memory system comprising:a storage device; and
a controller configured to control writing of data to the storage device and reading of data from the storage device based on a request from a host device, wherein
the controller includes a host interface unit that includes a packet protection circuit, and
the packet protection circuit includes a plurality of first CRC calculation circuits, each configured to calculate a CRC of M-byte data, where M is an integer greater than or equal to 1 and less than N, where N is an integer greater than or equal to 2, a first selector configured to output a CRC calculation result of one of the first CRC calculation circuits, and a second CRC calculation circuit configured to calculate a CRC of L-byte data, where L

US Pat. No. 11,024,510

PATTERN FORMING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

KIOXIA CORPORATION, Toky...

1. A pattern forming method, comprising:forming an organic layer on a first layer, the organic layer having a first region of a first thickness and a first width, a second region of a second thickness and a second width, and a third region between the first region and the second region, the third region having a third width and a third thickness that is less than each of the first thickness and the second thickness;
forming a second layer comprising silicon oxide on a surface of the organic layer in a process chamber of a reactive ion etching device; and
etching the third region using the second layer as a mask in the process chamber.

US Pat. No. 11,025,281

MEMORY SYSTEM

KIOXIA CORPORATION, Toky...

1. A memory system comprising:a nonvolatile memory, and
a memory controller configured to:
encode first XOR data generated by performing an exclusive OR operation on a plurality of pieces of user data in bit units, wherein a value of each bit of the XOR data is generated by performing an exclusive OR operation on values of bits that are at one of a plurality of bit positions of a piece of user data, generate codewords by encoding the plurality of pieces of user data and the generated XOR data, respectively, and store the plurality of codewords in the nonvolatile memory; and
perform a read operation by reading the plurality of codewords from the nonvolatile memory as a plurality of received words and decoding the received words,
wherein:
when the decoding of two or more of the received words fails, the memory controller generates second XOR data, wherein a value of each bit of the second XOR data is an exclusive OR of values of bits of decoded codewords, which were successfully decoded from the received words, and received words, which were not successfully decoded into decoded codewords, at one of a plurality of bit positions of the decoded codeword or the received word; and
when a value of a bit of the second XOR data indicates a probability of an error in one of the values of the bits from which the value of the bit was generated, the memory controller corrects the value of one of the bits corresponding to one of the received words whose decoding failed, and decodes the received word that has been corrected.

US Pat. No. 11,024,360

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

KIOXIA CORPORATION, Toky...

1. A semiconductor memory device comprising:a memory cell;
a word line connected to the memory cell;
a source line connected to the memory cell;
a bit line connected to the memory cell; and
a control circuit configured to perform a read operation on the memory cell by:
applying to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and
applying to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage and while applying the third voltage to the word line.

US Pat. No. 11,024,374

SEMICONDUCTOR MEMORY DEVICE

Kioxia Corporation, Toky...

1. A semiconductor memory device, comprising:a first wiring disposed at a first level parallel to a plane including a first direction and a second direction crossing the first direction, and the first wiring extending in the first direction;
a second wiring and a third wiring disposed at a second level parallel to the plane and extending in the first direction to be separate from each other, a position of the second level in a third direction that is perpendicular to the plane being different from a position of the first level in the third direction;
a plurality of fourth wirings disposed at a third level parallel to the plane and between the first level and the second level, the plurality of fourth wirings extending in the second direction;
a plurality of first resistive change elements disposed in intersection regions of the first wiring and the plurality of fourth wirings, each of the plurality of first resistive change elements including a first terminal and a second terminal, the first terminal being electrically connected to the first wiring, and the second terminal being electrically connected to a corresponding one of the plurality of fourth wirings;
a plurality of second resistive change elements disposed in intersection regions between the second wiring and the plurality of fourth wirings and between the third wiring and the plurality of fourth wirings, each of the plurality of second resistive change elements including a third terminal and a fourth terminal, the third terminal being electrically connected to a corresponding wiring selected from the second wiring and the third wiring, or the fourth terminal being electrically connected to a corresponding one of the plurality of fourth wirings;
a first driving circuit electrically connected to the first wiring, a second driving circuit electrically connected to the second wiring, and a third driving circuit electrically connected to the third wiring; and
a control circuit that controls the first driving circuit, the second driving circuit, and the third driving circuit, and also the plurality of fourth wirings,
the plurality of first resistive change elements being divided into a first group located on one side and a second group located on another side relative to a portion of the first wiring,
the plurality of second resistive change elements, the third terminal of each of which is electrically connected to the second wiring, being divided into a third group located on one side and a fourth group located on another side relative to a portion of the second wiring, and the plurality of second resistive change elements, the third terminal of each of which is electrically connected to the third wiring, being divided into a fifth group located on one side and a sixth group located on another side relative to a portion of the third wiring,
the control circuit selecting the first driving circuit to select the first wiring connected to the first driving circuit that is selected, selecting one of the plurality of first resistive change elements in the first group, selecting one of the plurality of first resistive change elements in the second group, during an operation to access the two first resistive change elements that are selected, providing addresses to be selected simultaneously to two of the plurality of fourth wirings, to which the second terminals of the two first resistive change elements that are selected are connected, and providing addresses to be selected simultaneously to the second wiring and the third wiring, to which the third terminals of two second resistive change elements are connected, the fourth terminals of the two second resistive change elements being connected to the two of the plurality of fourth wirings.

US Pat. No. 11,017,837

MEMORY SYSTEM

KIOXIA CORPORATION, Toky...

1. A memory system comprising:a semiconductor memory including a memory cell array, the memory cell array including a memory cell configured to hold data; and
a controller configured to issue a first read command sequence for reading the data from the memory cell after a lapse of a first time period from access to the semiconductor memory, and issue a second read command sequence after a lapse of a second time period from access to the semiconductor memory, the second time period being different from the first time period, wherein:
the memory cell is configured to hold the data of 2 bits or more;
when the controller issues the first read command sequence, the semiconductor memory applies a first voltage and a second voltage different from the first voltage to the memory cell;
when the controller issues the second read command sequence, the semiconductor memory applies a third voltage different from the second voltage, and a fourth voltage different from the first voltage and the third voltage to the memory cell;
the third voltage is more than the first voltage, and the fourth voltage is less than the second voltage; and
the first read command sequence and the second read command sequence read the same bits from the data of 2 bits or more held by the memory cell.

US Pat. No. 11,014,256

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Kioxia Corporation, Toky...

1. A semiconductor memory device, comprising:a source layer;
a lower stacked unit provided above the source layer, the lower stacked unit including a plurality of lower electrode layers alternately stacked in a stacking direction with a plurality of lower insulating layers therebetween;
an upper stacked unit provided above the lower stacked unit, the upper stacked unit including a plurality of upper electrode layers alternately stacked in the stacking direction with a plurality of upper insulating layers therebetween;
a bit line provided above the upper stacked unit;
a lower columnar part piercing the lower stacked unit in the stacking direction, the lower columnar part including a lower core insulator part and a lower tubular part extending inside the lower electrode layers in the stacking direction around an outer circumferential surface of the lower core insulator part;
an upper columnar part piercing the upper stacked unit in the stacking direction, the upper columnar part including an upper core insulator part and an upper tubular part extending inside the upper electrode layers in the stacking direction around an outer circumferential surface of the upper core insulator part; and
an intermediate portion provided above the lower stacked unit and below the upper stacked unit,
wherein a portion of the upper core insulator part overlaps with the lower tubular part when projected from the stacking direction, and
the upper core insulator part has a lower end portion at a height corresponding to the intermediate portion in the stacking direction and the lower end portion of the upper core insulator part overlaps with the lower tubular part when projected from the stacking direction.

US Pat. No. 11,011,484

SEMICONDUCTOR DEVICE HAVING FIRST AND SECOND TERMINALS

KIOXIA CORPORATION, Toky...

1. A semiconductor device comprising:a first substrate having a first surface;
a second substrate stacked on the first surface of the first substrate in a stacking direction, the second substrate having a second surface facing the first surface;
a plurality of first terminals provided on the first surface of the first substrate;
a plurality of second terminals provided on the second surface of the second substrate; and
a plurality of metallic portions respectively provided between the plurality of first terminals and the plurality of second terminals,
wherein, in a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction.

US Pat. No. 11,011,237

SEMICONDUCTOR MEMORY DEVICE WITH ERASE CONTROL

Kioxia Corporation, Mina...

1. A semiconductor memory device, comprising:a substrate;
a memory cell array comprising a plurality of conductive layers disposed in a first direction intersecting the substrate and each extending in a second direction intersecting the first direction, a semiconductor layer extending in the first direction and opposing the plurality of conductive layers, and charge accumulating sections respectively provided between the semiconductor layer and the plurality of conductive layers, the memory cell array including a plurality of memory cells formed in positions where the plurality of conductive layers and the semiconductor layer oppose, the plurality of memory cells being connected in series in the first direction to configure a memory string; and
a control circuit that executes an erase operation by which data stored in the plurality of memory cells is erased,
the plurality of conductive layers including: a first conductive layer; and a second conductive layer different from the first conductive layer,
the erase operation including an erase mode that executes a first erase flow in a state where the plurality of memory cells configuring the memory string have been simultaneously erased,
the first erase flow including:
a first write operation in which a first program voltage is applied to the plurality of conductive layers;
a first erase operation that is executed after the first write operation, and in which, while a first voltage is applied to the first conductive layer, a second voltage higher than the first voltage is applied to the second conductive layer; and
a second erase operation that is executed after the first erase operation, and in which, while the first voltage is applied to the second conductive layer, a third voltage higher than the first voltage is applied to the first conductive layer,
wherein
the control circuit, prior to the first erase flow, executes a pre-program operation on the plurality of memory cells configuring the memory string, and then executes a flash erase operation on the plurality of memory cells configuring the memory string by which the data stored in the plurality of memory cells is erased simultaneously.

US Pat. No. 11,011,239

SEMICONDUCTOR MEMORY

KIOXIA CORPORATION, Toky...

1. A semiconductor memory comprising:a plurality of first and second memory cells each having one of first, second, third, fourth, fifth, sixth, seventh, or eighth threshold voltages, the second threshold voltage being higher than the first threshold voltage, the third threshold voltage being higher than the second threshold voltage, the fourth threshold voltage being higher than the third threshold voltage, the fifth threshold voltage being higher than the fourth threshold voltage, the sixth threshold voltage being higher than the fifth threshold voltage, the seventh threshold voltage being higher than the sixth threshold voltage, and the eighth threshold voltage being higher than the seventh threshold voltage;
a first word line coupled to the first memory cells;
a second word line coupled to the second memory cells; and
a controller, wherein:
data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit are allocated to a plurality of combinations each comprising one of threshold voltages of a first memory cell and one of threshold voltages of a second memory cell,
in a read operation for a first page which includes the first bit, the controller reads first data from the first memory cells by applying at least one type of read voltage to the first word line, and externally outputs data of the first page which is confirmed based on the first data,
in a read operation for a second page which includes the second bit, the controller reads second data from the second memory cells by applying at least one type of read voltage to the second word line, and externally outputs data of the second page which is confirmed based on the second data, and
in a read operation for a third page which includes the third bit, the controller reads third data from the first memory cells by applying at least one type of read voltage to the first word line, and reads fourth data from the second memory cells by applying at least one type of read voltage to the second word line, and externally outputs data of the third page which is confirmed based on the third data and the fourth data.

US Pat. No. 10,998,055

SEMICONDUCTOR STORAGE DEVICE

Kioxia Corporation, Mina...

1. A semiconductor storage device comprising:a memory cell array including a plurality of memory cells;
a plurality of bit lines connected to the memory cell array;
a plurality of sense amplifier units provided to correspond to the plurality of bit lines and arranged in a matrix of M rows and N columns; and
a plurality of data latches provided to correspond to the plurality of sense amplifier units and arranged in a matrix of S rows and T columns,
wherein
M, N, S, and T are positive integers, satisfying MT, and S×T=M×N, and
a dimension of each of the sense amplifier units in an arrangement direction of the N columns is smaller than a dimension of each of the data latches in an arrangement direction of the T columns.

US Pat. No. 10,984,858

SEMICONDUCTOR STORAGE DEVICE

Kioxia Corporation, Mina...

1. A semiconductor storage device comprising:a memory cell array including a plurality of series-connected memory cell transistors each of which can be set to any of threshold voltages at a plurality of voltage levels;
a plurality of word lines connected to gates of the plurality of memory cell transistors, respectively;
a voltage generation circuit configured to generate,
a read voltage to be supplied to a selected word line to which a read-target memory cell transistor is connected among the plurality of word lines, the read voltage including at least two voltage levels of the plurality of voltage levels corresponding respectively to the threshold voltages, and
a first read-pass voltage to be supplied to an adjacent word line adjacent to the selected word line, the first read-pass voltage being higher than any of the at least two voltage levels of the read voltage:
a word line driver configured to, when reading data from the read-target memory cell among the plurality of memory cell transistors,
apply the read voltage to the selected word line for the at least two voltage levels; and
apply the first read-pass voltage to the adjacent word line,
such that, when the read voltage transitions among the at least two voltage levels, the read voltage is applied to the selected word line with a first kick voltage, and the first read-pass voltage is applied to the adjacent word line with a second kick voltage; and
a control circuit configured to set the first kick voltage and the second kick voltage for the at least two voltage levels of the read voltage.

US Pat. No. 10,985,027

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Kioxia Corporation, Mina...

1. A method for manufacturing a semiconductor device, the method comprising:forming a first layer on a semiconductor substrate, a surface of the first layer having a first plane of which distance from the semiconductor substrate is a first distance and a second plane of which distance from the semiconductor substrate is a second distance smaller than the first distance, and a difference between the first distance and the second distance being 30 nm or more;
performing planarization processing on the first layer to have the difference of less than 30 nm;
forming a second layer directly on the first layer after the performing the planarization processing;
supplying a resist on the second layer;
bringing a template having a pattern into contact with the resist to form a resist layer to which the pattern has been transferred; and
etching the second layer using the resist layer as a mask.

US Pat. No. 10,978,166

SEMICONDUCTOR MEMORY DEVICE

KIOXIA CORPORATION, Toky...

1. A semiconductor memory device comprising:a plurality of memory cells each capable of storing a plurality of bits of data;
a word line electrically connected to the plurality of memory cells; and
a controller configured to execute a write operation, wherein
in the write operation, the controller is configured to repeatedly execute a program loop including a program operation and a verify operation,
the controller is configured to:
execute a first program operation in which the a first program voltage is applied to the word line;
stop a first verify operation associated with the first program operation and started after the first program operation, upon reception of a first suspend command;
resume the first verify operation upon reception of a first resume command;
execute a second program operation in which the first program voltage is applied to the word line, after the resumed first verify operation;
stop a second verify operation associated with the second program operation and started after the second program operation, upon reception of a second suspend command;
resume the second verify operation upon reception of a second resume command; and
execute a third program operation in which a second program voltage higher than the first program voltage is applied to the word line, after the resumed second verify operation.

US Pat. No. 10,956,092

SEMICONDUCTOR STORAGE DEVICE

KIOXIA CORPORATION, Toky...

1. A semiconductor storage device comprising:first and second memory cells each including a variable-resistance element;
a write driver configured to apply a voltage to each of the first and second memory cells; and
a control circuit configured to concurrently perform an operation to read first data in the first memory cell and second data in the second memory cell, the operation to read the first data in the first memory cell including a first write operation for a first time length and the operation to read the second data in the second memory cell including a second write operation for a second time length, wherein
in the first write operation, the write driver applies, to the first memory cell, a first voltage for a third time length and a second voltage different from the first voltage for a fourth time length, and
in the second write operation, the write driver applies the first voltage to the second memory cell for a fifth time length longer than the third time length and longer than the fourth time length.

US Pat. No. 10,951,198

SEMICONDUCTOR INTEGRATED CIRCUIT, TRANSMISSION DEVICE, AND MEMORY DEVICE

Kioxia Corporation, Mina...

1. A semiconductor integrated circuit comprising:a clock supply circuit configured to be able to output a first clock and a second clock, the first clock having a first period, the second clock having a second period that is 1/m times the first period, where m is a natural number of 2 or more;
a first output circuit configured to output a first signal indicating content of data to an outside when a first operation is performed and output a second signal having a toggle pattern based on the first clock to the outside when a second operation is performed; and
a second output circuit configured to output an operation clock based on the first clock to the outside when the first operation is performed and output a sampling clock based on the second clock to the outside when the second operation is performed.

US Pat. No. 10,785,070

SEMICONDUCTOR INTEGRATED CIRCUIT AND RECEIVING APPARATUS

Kioxia Corporation, Mina...

1. A semiconductor integrated circuit comprising:an equalizer circuit;
a decision circuit configured to decide a bit value of a data signal;
a sampler unit including a plurality of sampler circuits, the sampler circuits having a plurality of different thresholds and electrically connected in parallel between the equalizer circuit and the decision circuit;
a determination circuit configured to determine a plurality of indexes indicating a degree of confidence of a plurality of output values from the plurality of sampler circuits based on the bit values of the data signals at a plurality of different past timings; and
an arithmetic circuit configured to compute a plurality of scores for a plurality of bit values that are candidates for a current data signal based on the plurality of determined indexes and a plurality of current output values from the plurality of sampler circuits,
wherein the decision circuit is configured to select one bit value from the plurality of candidate bit values using the scores.

US Pat. No. 11,075,220

SEMICONDUCTOR DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor device comprising:a first stacked body comprising a plurality of first conductive layers and a plurality of first insulating layers that are alternately stacked in a first direction;
a first columnar portion comprising a first semiconductor layer extending in the first stacked body in the first direction and a first memory layer located between the first semiconductor layer and at least one of the plurality of first conductive layers;
a second stacked body located above the first stacked body, the second stacked body comprising a plurality of second conductive layers and a plurality of second insulating layer that are alternately stacked in the first direction;
a second columnar portion comprising a second semiconductor layer extending in the second stacked body in the first direction and a second memory layer located between the second semiconductor layer and at least one of the plurality of second conductive layers;
an intermediate layer provided between the first stacked body and the second stacked body; and
a joining portion located between the first columnar portion and the second columnar portion within the intermediate layer, and including a third semiconductor layer in contact with the first semiconductor layer and the second semiconductor layer and a third memory layer in contact with the first memory layer and the second memory layer, wherein
the first columnar portion includes a first part facing a lowermost one of the plurality of first conductive layers and having a first width in a second direction crossing the first direction and a second part facing an uppermost one of the plurality of first conductive layers and having a second width in the second direction,
the second columnar portion includes a third part facing a lowermost one of the plurality of second conductive layers and having a third width in the second direction and a fourth part facing an uppermost one of the plurality of second conductive layers and having a fourth width in the second direction,
the joining portion has a fifth width in the second direction,
the second width is greater than the first width,
the fourth width is greater than the second width and the third width, and
the fifth width is greater than the second width and the third width.

US Pat. No. 11,075,122

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Kioxia Corporation, Mina...


1. A semiconductor device comprising:a semiconductor substrate including a first surface, a first contact part provided at a deeper level than the first surface, and a second contact part protruding up to a higher level than the first surface from the first contact part;
a stacked body in which insulating layers and electrode layers are alternately stacked on the first surface; and
a semiconductor film extending, on the second contact part, in the stacked body in a first direction perpendicular to the first surface, wherein
at an interface between the first contact part and the second contact part, a length of the first contact part in a second direction parallel to the first surface is larger than a length of the second contact part in the second direction,
wherein the second contact part includes tapered sidewall surfaces inclined such that a width of the second contact part in the second direction is larger as coming closer to the stacked body, and a (111) plane of a silicon crystal is exposed on the tapered sidewall surfaces.

US Pat. No. 11,062,770

MEMORY DEVICE

KIOXIA CORPORATION, Toky...


1. A memory device comprising:a first memory cell including a variable resistance element and a switching element;
a second memory cell including a variable resistance element and a switching element; and
a read and write circuit configured to perform, as a first access, a write operation or a read operation on the first memory cell, and make a second access after the first access, wherein
data is written into or read from the second memory cell as the second access, under a condition based on a type of the first access.

US Pat. No. 11,056,152

SEMICONDUCTOR MEMORY DEVICE

Kioxia Corporation, Mina...


1. A semiconductor memory device comprising:a memory cell array including a plurality of memory cells stacked above a substrate, and a plurality of word lines respectively coupled to gates of the plurality of memory cells and extending in a first direction; and
a first film including a first area above the memory cell array and a second area different from the first area, and having a compressive stress higher than silicon oxide,
wherein
in the first area, a plurality of first trenches extending in the first direction are aligned in a second direction that intersects the first direction, and
in the second area, a second trench in a mesh form is provided.

US Pat. No. 11,049,875

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Kioxia Corporation, Mina...


1. A semiconductor memory device, comprising:a first stacked body including a plurality of first conductive layers and a plurality of first insulating layers alternately stacked;
a second stacked body disposed above the first stacked body and including a plurality of second conductive layers and a plurality of second insulating layers alternately stacked;
a first memory hole extending in the first stacked body in a first direction that is a stacking direction of the first stacked body;
a second memory hole extending in the second stacked body in the first direction; and
a joint that communicates the first memory hole and the second memory hole,
wherein the joint comprises:
an inner wall surface having a plane continuous with an inner wall surface of the first memory hole,
a sidewall insulating layer disposed on the inner wall surface of the joint,
a first joint in which the sidewall insulating layer is disposed, the first joint having a diameter smaller than a diameter of an upper end of the first memory hole, and
a second joint disposed on the first joint and having a diameter larger than a diameter of a lower end of the second memory hole,
wherein the sidewall insulating layer is also disposed in the second joint;
an inner wall surface of the sidewall insulating layer disposed in the second joint has a diameter larger than the diameter of the lower end of the second memory hole.

US Pat. No. 10,950,307

SEMICONDUCTOR MEMORY DEVICE

KIOXIA CORPORATION, Toky...

1. A semiconductor memory device comprising:memory cells;
a first circuit that includes a first latch group including first and second data latch circuits and a second latch group including third and fourth data latch circuits; and
a control circuit configured to control a write operation during which first and second data to be written into the memory cells are stored in the first and second data latch circuits, respectively, wherein the first and second data are also stored in the third and fourth data latch circuits, respectively, while the first and second data stored in the first and second data latch circuits, respectively, are being written in the memory cells.

US Pat. No. 10,949,132

SEMICONDUCTOR STORAGE DEVICE

KIOXIA CORPORATION, Toky...

1. A semiconductor storage device comprising:a substrate;
a plurality of first wirings arranged above the substrate in a first direction intersecting a surface of the substrate and extending in a second direction intersecting the first direction;
a plurality of second wirings arranged above the substrate in the second direction and extending in the first direction;
a plurality of first variable resistance portions arranged between the plurality of first wirings and the plurality of second wirings;
a plurality of third wirings provided between the plurality of second wirings and the substrate, arranged in the second direction, and extending in a third direction intersecting the first and second directions;
a plurality of semiconductor portions each electrically connected to one end of one of the plurality of second wirings in the first direction and one of the plurality of third wirings;
a fourth wiring extending in the second direction and facing the plurality of semiconductor portions in the third direction;
a plurality of first insulating portions each provided between one of the plurality of semiconductor portions and the fourth wiring; and
a first contact electrically connected to an end of each of the plurality of first wirings in the second direction,
wherein the plurality of semiconductor portions include a first semiconductor portion and a second semiconductor portion closer to the first contact than the first semiconductor portion, and
a length in the second direction of one of the first insulating portions between the first semiconductor portion and the fourth wiring is greater than a length in the second direction of another one of the first insulating portions between the second semiconductor portion and the fourth wiring.

US Pat. No. 10,951,238

MEMORY SYSTEM AND METHOD FOR CONTROLLING NON-VOLATILE MEMORY

Kioxia Corporation, Mina...

1. A memory system comprising:a non-volatile memory; and
a memory controller configured to
generate an error correction code based on user data received from a host, the error correction code including a first symbol group and a second symbol group, the first symbol group being a set of symbols shared between a first component code and at least one of a third component code and a fourth component code, the second symbol group being a set of symbols shared between a second component code and at least one of the third component code and the fourth component code, and
store the error correction code in the non-volatile memory,
wherein the memory controller is configured to:
encode the first component code with a lower correction capability than the second component code,
encode the third component code with a lower correction capability than the fourth component code,
set a ratio of symbols shared between the second component code and the third component code in the second symbol group to be smaller than a ratio of symbols shared between the first component code and the third component code in the first symbol group, and
set a ratio of symbols shared between the second component code and the fourth component code in the second symbol group to be larger than a ratio of symbols shared between the first component code and the fourth component code in the first symbol group.

US Pat. No. 11,099,787

SEMICONDUCTOR MEMORY

KIOXIA CORPORATION, Toky...


1. A semiconductor memory comprising:a first plane that includes a first memory cell array including a first memory cell;
a first word line connected to a gate of the first memory cell;
a first bit line connected to one end of the first memory cell;
a second plane that includes a second memory cell array including a second memory cell;
a second word line connected to a gate of the second memory cell;
a second bit line connected to one end of the second memory cell;
an input output circuit configured to receive: a) a first command for the first plane to execute a first operation, the first operation including a first process, and b) a second command for the second plane to execute a second operation, the second operation including a second process;
a driver circuit configured to apply voltages to the first word line, the second word line, the first bit line and the second bit line; and
a control circuit that includes:a first circuit configured to store a first priority for the first operation performed on the first plane, and
a second circuit configured to store a second priority for the second operation performed on the second plane,
wherein the control circuit is configured to control the first operation and the second operation such that such that a timing of the first process in the first operation and a timing of the second process in the second operation are not overlapped, by delaying the first process or the second process based on the first priority and the second priority.


US Pat. No. 11,100,988

SEMICONDUCTOR MEMORY DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor memory device comprising:a substrate including a main surface extending in a first direction and a second direction that intersects the first direction;
a first memory cell array including a first conductive layer, a second conductive layer, a third conductive layer, a first memory cell, and a second memory cell, wherein,the first conductive layer is arranged on one side of a third direction that intersects the first direction and the second direction of the substrate, and extends in the first direction,
the second conductive layer is arranged on the one side of the third direction of the first conductive layer and extends in the second direction,
the third conductive layer is arranged on the one side of the third direction of the second conductive layer and extends in the first direction,
the first memory cell is arranged between the first conductive layer and the second conductive layer with respect to the third direction, and
the second memory cell is arranged between the second conductive layer and the third conductive layer with respect to the third direction;

a second memory cell array including a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a third memory cell, and a fourth memory cell, whereinthe fourth conductive layer is arranged on the one side of the third direction of the substrate and extends in the first direction,
the fifth conductive layer is arranged on the one side of the third direction of the fourth conductive layer and extends in the second direction,
the sixth conductive layer is arranged on the one side of the third direction of the fifth conductive layer and extends in the first direction,
the third memory cell is arranged between the fourth conductive layer and the fifth conductive layer with respect to the third direction, and
the fourth memory cell is arranged between the fifth conductive layer and the sixth conductive layer with respect to the third direction;

a first driver that applies a voltage to the first conductive layer and the fourth conductive layer;
a second driver that applies a voltage to the third conductive layer and the sixth conductive layer;
a first connection arranged between the first memory cell array and the second memory cell array with respect to the first direction, and extending in the third direction, the first connection electrically coupling the first conductive layer and the fourth conductive layer to the first driver; and
a second connection arranged between the first memory cell array and the second memory cell array with respect to the first direction, and extending in the third direction, the second connection electrically coupling the third conductive layer and the sixth conductive layer to the second driver.

US Pat. No. 11,082,069

DECODING SCHEME FOR ERROR CORRECTION CODE STRUCTURE IN DATA STORAGE DEVICES

Kioxia Corporation, Toky...


1. A method for decoding data stored in a non-volatile storage device, comprising:determining features for each of a plurality of component codes corresponding to the data by decoding each of the plurality of component codes;
determining an extrinsic value output for each of the component codes based on the features; and
after the extrinsic value output for each of the component codes is determined, decoding each of the plurality of component codes based on the extrinsic value outputs of all other component codes of the component codes, wherein each of the component codes depends on all other component codes.

US Pat. No. 11,074,178

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY

Kioxia Corporation, Mina...


1. A memory system connectable to a host, comprising:a nonvolatile memory including a plurality of blocks; and
a controller electrically connected to the nonvolatile memory and configured to control the nonvolatile memory,
wherein the controller is configured to:
receive a movement request from the host, the movement request designating a logical address of movement target data;
when update data corresponding to the designated logical address is not written to the nonvolatile memory by a write request from the host in a period from the reception of the movement request to start of movement of data corresponding to the designated logical address, execute a movement process of moving data stored in a physical address of the nonvolatile memory associated with the designated logical address to a movement destination block in the nonvolatile memory, the physical address being obtained by referring to a logical-to-physical address conversion table; and
when the update data is written to the nonvolatile memory in the period, not execute the movement process.

US Pat. No. 11,069,405

SEMICONDUCTOR MEMORY DEVICE

Kioxia Corporation, Toky...


1. A semiconductor memory device comprising:a plurality of first wirings disposed at a first level and extending in a first direction;
a second wiring and a third wiring disposed at a second level, a position of which in a second direction intersecting with the first direction is different from that of the first level, the second wiring and the third wiring extending in a third direction that intersects with the first direction and the second direction, and being separated from each other;
a plurality of first resistive change elements each including a first terminal and a second terminal and disposed between one of the first wirings and one of the second wiring and the third wiring, the first terminal being electrically connected to the one of the first wirings, and the second terminal being electrically connected to the one of the second wiring and the third wiring;
a fourth wiring disposed to be in contact with a face of the second wiring opposite to the first wirings and extending in the third direction;
a fifth wiring disposed to be in contact with a face of the third wiring opposite to the first wirings, extending in the third direction, and separated from the fourth wiring;
a plurality of sixth wirings disposed at a third level and extending in the first direction, the second level being between the first level and the third level;
a plurality of second resistive change elements each including a third terminal and a fourth terminal and disposed between one of the fourth wiring and the fifth wiring and one of the sixth wirings, the third terminal being electrically connected to the one of the fourth wiring and the fifth wiring, and the fourth terminal being electrically connected to the one of the sixth wirings;
a plurality of seventh wirings disposed to correspond to the sixth wirings and extending in the first direction, each of the seventh wirings being disposed to be in contact with a face of corresponding one of the sixth wirings opposite to the second resistive change elements;
an eighth wiring and a ninth wiring disposed at a fourth level, extending in the third direction, and separated from each other, the third level being between the fourth level and the second level;
a plurality of third resistive change elements each including a fifth terminal and a six terminal and disposed between one of the seventh wirings and one of the eighth wiring and the ninth wiring, the fifth terminal being electrically connected to the one of the seventh wirings, and the six terminal being electrically connected to the one of the eighth wiring and the ninth wiring;
a tenth wiring disposed to be in contact with a face of the eighth wiring opposite to the seventh wirings and extending in the third direction;
an eleventh wiring disposed to be in contact with a face of the ninth wiring opposite to the seventh wirings and extending in the third direction, and separated from the tenth wiring;
a plurality of twelfth wirings disposed at a fifth level and extending in the first direction, the fourth level being between the fifth level and the third level;
a plurality of fourth resistive change elements each including a seventh terminal and an eighth terminal and disposed between one of the tenth wiring and the eleventh wiring and one of the twelfth wirings, the seventh terminal being electrically connected to the one of the tenth wiring and the eleventh wiring, and the eighth terminal being electrically connected to the one of the twelfth wirings;
a plurality of thirteenth wirings disposed to correspond to the twelfth wirings and extending in the first direction, each of the thirteenth wirings disposed to be in contact with a face of corresponding one of the twelfth wirings opposite to the fourth resistive change elements;
a fourteenth wiring and a fifteenth wiring disposed at a sixth level, extending in the third direction, and separated from each other, the fifth level being between the sixth level and the fourth level, a region between the tenth wiring and the eleventh wiring, a region between the eighth wiring and the ninth wiring, a region between the fourth wiring and the fifth wiring, and a region between the second wiring and the third wiring being located at positions in the second direction from a portion of the fourteenth wiring;
a plurality of fifth resistive change elements each including a ninth terminal and a tenth terminal and disposed between one of the thirteenth wirings and one of the fourteenth wiring and the fifteenth wiring, the ninth terminal being electrically connected to the one of the thirteenth wirings, and the tenth terminal being electrically connected to the one of the fourteenth wiring and the fifteenth wiring;
a sixteenth wiring disposed to be in contact with a face of the fourteenth wiring opposite to the thirteenth wirings and extending in the third direction;
a seventeenth wiring disposed to be in contact with a face of the fifteenth wiring opposite to the thirteenth wirings and extending in the third direction, and separated from the sixteenth wiring;
a plurality of eighteenth wirings disposed at a seventh level and extending in the first direction, the sixth level being between the seventh level and the fifth level;
a plurality of sixth resistive change elements each including an eleventh terminal and a twelfth terminal and disposed between one of the sixteenth wiring and the seventeenth wiring and one of the eighteenth wirings, the eleventh terminal being electrically connected to the one of the sixteenth wiring and the seventeenth wiring, and the twelfth terminal being electrically connected to the one of the eighteenth wirings;
a first contact electrically connected to a portion of the third wiring;
a second contact electrically connected to an end of the ninth wiring on a side of the eighth wiring, and passing through the region between the fourth wiring and the fifth wiring and the region between the second wiring and the third wiring; and
a third contact electrically connected to the portion of the fourteenth wiring, and passing through the region between the tenth wiring and the eleventh wiring, the region between the eighth wiring and the ninth wiring, the region between the fourth wiring and the fifth wiring, and the region between the second wiring and the third wiring.

US Pat. No. 11,069,413

MEMORY SYSTEM AND NONVOLATILE MEMORY

Kioxia Corporation, Mina...


1. A memory system comprising:a nonvolatile memory including a plurality of blocks, each of the plurality of blocks including a plurality of memory cells: and
a memory controller configured to control operation of the nonvolatile memory, wherein
the nonvolatile memory is configured to:
receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation,
in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section, and
in response to receiving a third command from the memory controller during the execution of the first operation, execute a third operation for suspending the first operation after the given section. the third command being different from the second command, wherein
the memory controller is further configured to:
in response to occurrence of a request for another operation while the first operation is executed by the nonvolatile memory, selectively allow the nonvolatile memory to execute one of the second operation, the third operation, and continuance of the first operation, wherein
the memory controller is configured to:
allow the nonvolatile memory to execute the second operation when the number of erased blocks of the nonvolatile memory is A,
allow the nonvolatile memory to execute the third operation when the number of erased blocks of the nonvolatile memory is B where A>B, and
allow the nonvolatile memory to continue the first operation when the number of erased blocks of the nonvolatile memory is C where B>C.

US Pat. No. 11,125,775

PROBE AND MANUFACTURING METHOD OF PROBE FOR SCANNING PROBE MICROSCOPE

Kioxia Corporation, Toky...


1. A manufacturing method of a probe used for a scanning probe measuring apparatus, the method comprising:forming an insulating film on a surface of a probe provided on a base;
implanting metal ions into the insulating film; and
applying an electric field to the insulating film to concentrate the metal ions in the insulating film at a tip of the probe and form a metallic filament in the insulating film.

US Pat. No. 11,127,441

SEMICONDUCTOR STORAGE DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor storage device, comprising:a first input driver configured to receive a first signal from a memory controller;
a second input driver configured to receive a chip enable signal from the memory controller; and
a first control circuit configured to set the semiconductor storage device in an enabled state or a disabled state depending on whether or not the first signal which is received during a time period that starts with assertion of the chip enable signal and is prior to receipt of a command sequence, corresponds to a first chip address.

US Pat. No. 11,127,448

RESISTANCE CHANGE MEMORY DEVICE AND ASSOCIATED METHODS

KIOXIA CORPORATION, Toky...


1. A memory device comprising:a first resistance change memory element to which one of a first low-resistance state and a first high-resistance state is allowed to be set in accordance with a write current;
a first transistor including a first gate, a first source and a first drain and causing a current to flow through the first resistance change memory element in a first write period;
a voltage holding section holding a first voltage applied to the first gate in the first write period; and
a second transistor including a second gate, a second source and a second drain, in which the first voltage held in the voltage holding section is applied to the second gate, thereby causing a current to flow through the first resistance change memory element in a second write period after the first write period,
wherein the voltage holding section includes a capacitor provided at a wiring between the first gate and the second gate.

US Pat. No. 11,127,711

SEMICONDUCTOR DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor device comprising:a first wafer;
a first wiring layer provided in the first wafer;
a first insulating layer provided at a side of the first wiring layer along a first direction;
a first electrode, provided in the first insulating layer, that includes a first surface connected to the first wiring layer, a second surface spaced from the first surface along the first direction, a third surface spaced further from the first surface than the second surface along the first direction, a first side surface extended from the first surface to the second surface, and a fourth surface extended from the second surface to the third surface;
a second wafer;
a second wiring layer provided in the second wafer;
a second insulating layer provided at a side of the second wiring layer along the first direction that faces the side of the first wiring layer;
a second electrode, provided in the second insulating layer, that includes a fifth surface connected to the second wiring layer, a sixth surface spaced from the fifth surface along the first direction, a seventh surface spaced further from the fifth surface than the sixth surface along the first direction, the seventh surface being connected to the third surface, a second side surface extended from the fifth surface to the sixth surface, and an eighth surface extended from the sixth surface to the seventh surface; and
a first layer provided between the fourth surface and a portion of the first insulating layer that surrounds the fourth surface, and provided spaced from the third surface in the first direction.

US Pat. No. 11,127,470

SEMICONDUCTOR MEMORY DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor memory device comprising:a first bit line;
a first memory cell electrically coupled to the first bit line and configured to store at least two-bit data; and
a first sense amplifier configured to sense and store data read out to the first bit line, wherein:
the first sense amplifier includes a first latch circuit and a second latch circuit;
a data write operation is performed by repeating a loop including a program operation and a first verify operation;
in the program operation, each of the first and second latch circuits stores any one bit of the at, least two-bit data; and
in the first verify operation, data is exchanged between the first latch circuit and the second latch circuit when performing the first verify operation for a first data indicated by the at least two-bit data, and the first verify operation for a second data indicated by the at least two-bit data is performed without exchanging data between the first latch circuit and the second latch circuit.

US Pat. No. 11,127,476

MEMORY SYSTEM CONTROLLING A THRESHOLD VOLTAGE IN A READ OPERATION AND METHOD

Kioxia Corporation, Mina...


1. A memory system comprising:a first memory being nonvolatile, the first memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors configured to store data corresponding to a threshold voltage thereof;
a second memory configured to store a plurality of candidate values for a read voltage, each of the plurality of candidate values being associated with a determination reference value of a degree of stress that affects the threshold voltage; and
a memory controller configured to:
cause the first memory to execute a read operation to acquire data corresponding to the threshold voltage from the plurality of memory cell transistors on the basis of a result of comparison between the threshold voltage and a read voltage, wherein
the memory controller is further configured to:
determine the degree of stress of the plurality of memory cell transistors;
select a first candidate value from among the plurality of candidate values;
cause the first memory to execute the read operation using the first candidate value as the read voltage; and
in a case that the read operation using the first candidate value has failed,calculate a first divergence, the first divergence being a divergence between the determined degree of stress and the determination reference value of the degree of stress that is associated with the first candidate value; and
in a case that the first divergence is larger than a first threshold,select a second candidate value from among the plurality of candidate values, a divergence between the determined degree of stress and the determination reference value of the degree of stress that is associated with the second candidate value is smallest among divergences between the determined degree of stress and the determination reference value of the degree of stress that are respectively associated with unselected candidate values of the plurality of candidate values; and
cause the first memory to execute the read operation using the second candidate value as the read voltage.



US Pat. No. 11,127,753

SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE MANUFACTURING METHOD

Kioxia Corporation, Mina...


11. A method of manufacturing a semiconductor storage device, the method comprising:forming a stacked body in which a plurality of first insulating layers and a plurality of second insulating layers that is later replaced with conductive layers are alternately stacked;
forming a through hole penetrating an (n?1)th second insulating layer when counted from a lowermost second insulating layer of the plurality of second insulating layers where n is an integer of 2 or more;
forming, in the through hole, a region to be insulated from the (n?1)th conductive layer surrounding a periphery when the second insulating layers are replaced with the conductive layers;
forming, in the stacked body, a stepped portion in which ends of the plurality of second insulating layers are stepped; and
forming, above the region in the (n?1)th conductive layer, a contact to be connected to an n-th second insulating layer when counted from a lowermost second insulating layer of the plurality of second insulating layers.

US Pat. No. 11,127,754

SEMICONDUCTOR STORAGE DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor storage device comprising:a base body including a substrate, a semiconductor element on the substrate, a lower wiring layer above the semiconductor element in a thickness direction of the base body and connected to the semiconductor element, and a lower conductive layer above the lower wiring layer in the thickness direction;
a stacked body above the lower conductive layer and including an alternating stack of a plurality of conductive layers and a plurality of insulating layers that are alternately stacked;
a plurality of columns, each of the columns including a semiconductor body extending through the stacked body in a stack direction of the stacked body and electrically connected to the lower conductive layer, and a memory film having a charge trapping portion between the plurality of conductive layers and the semiconductor body; and
a plurality of first contacts extending through the stacked body into the base body in the stack direction and electrically connected to the lower wiring layer,
wherein the lower conductive layer is not provided around the first contacts.

US Pat. No. 11,126,770

METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, CIRCUIT DESIGN SYSTEM, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM

Kioxia Corporation, Mina...


1. A design method of a semiconductor integrated circuit using a design apparatus, the method comprising:creating pseudo-cell information for cells included in cell library information by a pseudo-cell information creation unit, the pseudo-cell information reflecting a degree of difficulty of pin access in connecting pins in the cells to wires;
employing one of the cells with a low difficulty of pin access with reference to the pseudo-cell information, in a timing optimization performed by a circuit design unit; and
conducting implementation design including (1) in performing the timing optimization, referring to the pseudo-cell information inputted in a design database provided for a design apparatus, and (2) after the timing optimization, referring to cell information which is registered in a cell library apparatus and that does not reflect the degree of difficulty of pin access.

US Pat. No. 11,120,883

SEMICONDUCTOR STORAGE DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor storage device comprising:a plurality of semiconductor pillars each extending above a substrate;
a first bit line electrically connected to a first semiconductor pillar of the plurality of semiconductor pillars;
a second bit line electrically connected to a second semiconductor pillar of the plurality of semiconductor pillars;
a third bit line electrically connected to a third semiconductor pillar of the plurality of semiconductor pillars;
a first word line at a first level above the substrate;
a second word line at the first level above the substrate and electrically isolated from the first word line;
a first cell transistor including a first part of the first semiconductor pillar that faces the first word line;
a second cell transistor including a second part of the first semiconductor pillar that faces the second word line;
a third cell transistor including a first part of the second semiconductor pillar that faces the first word line;
a fourth cell transistor including a second part of the second semiconductor pillar that faces the second word line;
a fifth cell transistor including a first part of the third semiconductor pillar that faces the first word line;
a sixth cell transistor including a second part of the third semiconductor pillar that faces the second word line;
a first select transistor between the first bit line and the first cell transistor;
a second select transistor between the first bit line and the second cell transistor;
a third select transistor between the second bit line and the third cell transistor;
a fourth select transistor between the second bit line and the fourth cell transistor;
a fifth select transistor between the third bit line and the fifth cell transistor;
a sixth select transistor between the third bit line and the sixth cell transistor, wherein
the first, third, and fifth select transistors are commonly controlled to be ON or OFF, and the second, fourth and sixth select transistors are commonly controlled to be ON or OFF, and
during a reading operation to read data from the first cell transistor, the first, third, and fifth select transistors are controlled to be ON, and the second, fourth, and sixth select transistors are controlled to be OFF, and a first voltage that is greater than or equal to zero voltage and less than a threshold voltage of the second cell transistor is applied to the second word line.

US Pat. No. 11,122,709

ELECTRONIC DEVICE

KIOXIA CORPORATION, Toky...


1. An electronic device comprising:a top plate having opposing first and second edges, opposing third and fourth edges that are perpendicular to the first and the second edges, a first portion with a first upper surface formed at an interior portion of the top plate and along the first, second, and fourth edges, and a second portion with a second upper surface at an elevation that is lower than an elevation of the first upper surface, the second upper surface being formed along an entire third edge of the top plate and to extend from the first edge of the top plate to the second edge of the top plate, the top plate further including at least one screw hole formed on the second portion;
a bottom plate provided under the top plate; and
a circuit board placed between the top plate and the bottom plate and mounted with an electronic component,
wherein the top plate further includes a rib on the first portion and a plurality of recessed portions formed on the rib, and
wherein the rib is at an elevation that is lower than the elevation of the first upper surface, and each of the plurality of recessed portions is at an elevation that is lower than the elevation of the rib.

US Pat. No. 11,121,710

SEMICONDUCTOR DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor device comprising:an input/output (IO) signal receiver circuit; and
a latch circuit connected to the IO signal receiver circuit,
wherein the latch circuit includesa first inverter configured to output a first signal based on an input signal received from the IO signal receiver circuit,
a second inverter configured to output a first clock signal based on a first strobe signal,
a third inverter configured to output a second clock signal based on a second strobe signal which is an inversion signal of the first strobe signal,
a fourth inverter configured to output an inversion signal of the first signal in accordance with the first and second clock signals,
a first delay circuit configured to output a third clock signal obtained by delaying the first strobe signal relative to the first clock signal,
a second delay circuit configured to output a fourth clock signal obtained by delaying the second strobe signal relative to the second clock signal, and
a data latch circuit configured to latch an output signal of the fourth inverter in accordance with the third and fourth clock signals, and

wherein:the data latch circuit includes a fifth inverter and a sixth inverter, the fifth inverter having an input terminal connected to an output terminal of the sixth inverter and an output terminal connected to an input terminal of the sixth inverter and the output terminal of the fourth inverter;
the output signal of the fourth inverter is latched at a non-inverted node of the data latch circuit that is connected to the output terminal of the fifth inverter and the input terminal of the sixth inverter and an inverted node of the latch circuit is connected to the output terminal of the sixth inverter and the input terminal of the fifth inverter; and
the sixth inverter is controlled in accordance with the third and fourth clock signals.


US Pat. No. 11,121,227

SEMICONDUCTOR MEMORY DEVICE

Kioxia Corporation, Toky...


1. A semiconductor memory device comprising:a semiconductor substrate;
a memory cell array disposed separately from the semiconductor substrate in a first direction intersecting with a surface of the semiconductor substrate; and
a first transistor array and a second transistor array disposed on the semiconductor substrate, wherein
the semiconductor substrate includes a first region to a fourth region arranged in order in a second direction intersecting with the first direction and a fifth region to an eighth region arranged in order in the second direction, wherein
in a third direction intersecting with the first direction and the second direction:the fifth region is adjacent to the first region;
the sixth region is adjacent to the second region;
the seventh region is adjacent to the third region; and
the eighth region is adjacent to the fourth region, wherein

the memory cell array includes:a plurality of first conducting layers extending in the second direction in the first region to the fourth region and laminated in the first direction;
a plurality of first semiconductor columns disposed in the first region, the plurality of first semiconductor columns extending in the first direction and being opposed to the plurality of first conducting layers;
a plurality of first connection contacts disposed in the second region, the plurality of first connection contacts extending in the first direction and being connected to the plurality of respective first conducting layers at one ends in the first direction;
a plurality of second semiconductor columns disposed in the fourth region, the plurality of second semiconductor columns extending in the first direction and being opposed to the plurality of first conducting layers;
a plurality of second conducting layers extending in the second direction in the fifth region to the eighth region and laminated in the first direction;
a plurality of third semiconductor columns disposed in the fifth region, the plurality of third semiconductor columns extending in the first direction and being opposed to the plurality of second conducting layers;
a plurality of second connection contacts disposed in the seventh region, the plurality of second connection contacts extending in the first direction and being connected to the plurality of respective second conducting layers at one ends in the first direction; and
a plurality of fourth semiconductor columns disposed in the eighth region, the plurality of fourth semiconductor columns extending in the first direction and being opposed to the plurality of second conducting layers, wherein

the first transistor array:is disposed in a region including the second region and the sixth region; and
includes a plurality of first transistors arranged in the second direction and a plurality of second transistors arranged in the second direction, wherein

the plurality of second transistors are adjacent to the plurality of first transistors in the third direction via insulating regions disposed on the surface of the semiconductor substrate, and
the plurality of first transistors and the plurality of second transistors are connected to the plurality of first conducting layers via the plurality of first connection contacts, wherein
the second transistor array:is disposed in a region including the third region and the seventh region; and
includes a plurality of third transistors arranged in the second direction and a plurality of fourth transistors arranged in the second direction, wherein

the plurality of third transistors are adjacent to the plurality of fourth transistors in the third direction via the insulating regions, and
the plurality of third transistors and the plurality of fourth transistors are connected to the plurality of second conducting layers via the plurality of second connection contacts.

US Pat. No. 11,120,979

TIME-OF-FLIGHT MASS SPECTROMETER AND TIME-OF-FLIGHT MASS SPECTROMETRY METHOD

KIOXIA CORPORATION, Toky...


1. A time-of-flight mass spectrometer comprising:an ion light source configured to generate an ionized particle by emitting an ion beam in a pulse form to a sample;
a mass spectrometry chamber that causes the ionized particle to fly;
a micro channel plate (MCP) ion measurer disposed in the mass spectrometry chamber to measure a mass by amplifying the flown ionized particle;
an MCP reference voltage source configured to apply a voltage to the MCP ion measurer; and
an MCP gain adjuster configured to adjust a gain of the voltage,
wherein the MCP gain adjuster is configured to adjust the gain of the voltage until a subsequent pulse is emitted after the ion light source emits a first pulse of the ion beam.

US Pat. No. 11,119,701

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY BY CONTROLLING THE WRITING OF DATA TO AND READING OF DATA FROM A PLURALITY OF BLOCKS IN THE NONVALATILE MEMORY

Kioxia Corporation, Mina...


1. A memory system connectable to a host, comprising:a nonvolatile memory including a plurality of blocks each including a plurality of pages, and enabling reading of data written in one page of the plurality of pages of each block after writing of data to one or more pages subsequent to the one page; and
a controller electrically connected to the nonvolatile memory and configured to write data to a plurality of write destination blocks allocated from the plurality of blocks, wherein
the controller is configured to:
in response to receiving a read command from the host, increment a first counter value corresponding to a first block having a block address allocated to a logical address of read target data specified by the received read command, wherein the first counter value is among a plurality of first counter values corresponding to the blocks;
read the read target data from the first block or a buffer depending on whether or not the read target data is readable from the first block, and decrement the first counter value corresponding to the first block after the reading has been finished, the buffer being a first buffer in the memory system or a write buffer of the host;
wherein in response to determining the first block is a first write destination block among the plurality of write destination blocks and the read target data is not readable from the first write destination block, increment a second counter value corresponding to the first write destination block among a plurality of second counter values corresponding to the plurality of write destination blocks, read the read target data from the buffer, and decrement the second counter value corresponding to the first write destination block after the reading has been finished; and
prohibit processing for transitioning a state of a block associated with an uncompleted read command to a state reusable as a new write destination block, on the basis of the plurality of first counter values, and prohibit release of a first region in the buffer, on the basis of the plurality of second counter values, the first region being a region that stores data being written or waiting to be written to a write destination block associated with an uncompleted read command that requires reading of data from the buffer.

US Pat. No. 11,120,842

MEMORY SYSTEM HAVING PLURAL CIRCUITS SEPARATELY DISPOSED FROM MEMORIES

KIOXIA CORPORATION, Toky...


1. A memory system comprising:a first substrate including a first signal terminal and a second signal terminal electrically connected to a bus;
a second substrate having first and second surfaces that are opposite to each other, the first surface facing a surface of the first substrate, the second substrate including:a first circuit in which a first switching element and a first resistor are connected in series between a first terminal and a second terminal, the first terminal connected to the first signal terminal, and
a second circuit in which a second switching element and a second resistor are connected in series between a third terminal and a fourth terminal, the third terminal connected to the second signal terminal;

a third substrate facing the second surface of the second substrate and including a first memory electrically connected to the second terminal;
a fourth substrate facing the second surface of the second substrate and including a second memory electrically connected to the fourth terminal; and
a controller electrically connected to the bus and configured to control the first and second switching elements.

US Pat. No. 11,120,858

MAGNETIC MEMORY

Kioxia Corporation, Toky...


1. A magnetic memory comprising:a first wiring;
a second wiring;
a first switching element disposed between the first wiring and the second wiring;
a first magnetic member extending in a first direction and disposed between the first switching element and the second wiring;
a third wiring disposed between the first magnetic member and the second wiring;
a first magnetoresistive element disposed between the third wiring and the second wiring; and
a second switching element disposed between the first magnetoresistive element and the second wiring.

US Pat. No. 11,120,866

MEMORY DEVICE

Kioxia Corporation, Toky...


1. A memory device comprising:a semiconductor substrate having a main surface, the main surface extending in a first direction and a second direction intersecting the first direction;
a first memory pillar including;a first variable resistance memory layer extending in a third direction intersecting the first direction and the second direction;
a first semiconductor layer extending in the third direction, the first semiconductor layer contacting with the first variable resistance memory layer; and
a first insulating layer extending in the third direction, the first insulating layer contacting with the first semiconductor layer;

a second memory pillar including;a second variable resistance memory layer extending in the third direction;
a second semiconductor layer extending in the third direction, the second semiconductor layer contacting with the second variable resistance memory layer; and
a second insulating layer extending in the third direction, the second insulating layer contacting with the second semiconductor layer;

a bit line extending in the first direction, the bit line connecting to one end of the first memory pillar and one end of the second memory pillar;
a first selecting gate line extending in the second direction, the first selecting gate line forming a first selecting transistor by being opposite to the first semiconductor layer through the first insulating layer;
a first word line extending in the second direction, the first word line forming a first memory cell by being opposite to the first variable resistance memory layer through the first semiconductor layer and the first insulating layer;
a second selecting gate line arranged at a same position as the first selecting gate line in the third direction, the second selecting gate line extending in the second direction, the second selecting gate line forming a second selecting transistor by being opposite to the second semiconductor layer through the second insulating layer;
a second word line arranged at a same position as the first word line in the third direction, the second word line extending in the second direction, the second word line forming a second memory cell by being opposite to the second variable resistance memory layer through the second semiconductor layer and the second insulating layer; and
a driver configured to supply voltages to each of the bit line, the first selecting gate line, the second selecting gate line, and the second word line at a writing operation; wherein
the driver sequentially supplies a first voltage, a second voltage higher than the first voltage, and the first voltage to the bit line, during the writing operation to the first memory cell;
the driver supplies a third voltage to the second word line and a fourth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if a data written in the first memory cell is a first data;
the driver supplies a fifth voltage to the second word line and a sixth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if the data written in the first memory cell is a second data different from the first data; and
at least the sixth voltage is larger than the fourth voltage or the fifth voltage is larger than the third voltage.

US Pat. No. 11,120,875

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH A PLURALITY OF MEMORY BLOCKS WITH MEMORY STRINGS AND A SHARED BLOCK DECODER TO ALLOW THE NUMBER OF SELECTION SIGNALS TO BE REDUCED

KIOXIA CORPORATION, Toky...


1. A memory device, comprising:a semiconductor substrate extending in a first direction and a second direction crossing the first direction;
a plurality of block units each including a plurality of blocks, each block including a plurality of memory strings, each memory string including a first transistor, a first memory cell transistor, a second memory cell transistor, and a second transistor, the first transistor and the first memory cell transistor being arranged relative to each other along a third direction crossing the first and second directions, the second transistor and the second memory being arranged relative to each other along the third direction;
a plurality of first select gate lines, each of the first select gate lines connected to a gate of a corresponding one of the first transistors in each block unit;
a plurality of second select gate lines, each of the second select gate lines connected to a gate of a corresponding one of the second transistors in each block unit;
a plurality of first word lines, each of the first word lines connected to gates of the first memory cell transistors of a corresponding one of the blocks in each block unit;
a plurality of second word lines, each of the second word lines connected to gates of the second memory cell transistor of a corresponding one of the blocks in each block unit;
a plurality of transfer transistors, each first select gate line, each second select gate line, each first word line, and each second word line respectively having one end of a transfer transistor connected thereto;
a plurality of block decoders having a selection signal output line respectively connected to gates of the transfer transistors connected to one of the block units; and
a voltage supply circuit having voltage supply lines connected to another end of the transfer transistor respectively connected to the first select gate lines and the second select gate lines of each of the block units.

US Pat. No. 11,113,222

NAND SWITCH

KIOXIA CORPORATION, Toky...


1. A memory system comprising:a controller configured with a first enable output and a data output;
a plurality of non-volatile storage devices, each configured with an enable input and a data input; and
a first switch configured between the controller and a first set of the plurality of non-volatile storage devices, witha first enable input that is connected to the first enable output of the controller,
a first data input that is connected to the data output of the controller,
a first data output that is connected to the data input of each of the first set of non-volatile storage devices, and
a plurality of enable outputs, each of the enable outputs being connected to the enable input of one of the first set of non-volatile storage devices,

wherein in response to the controller asserting the first enable output and transmitting select data which indicates one of the enable outputs of the first switch connected to an enable input of a first non-volatile storage device among the first set of non-volatile storage devices,the first switch enables a first communication path between the controller and the first non-volatile storage device, and transmits a command and an address of the first non-volatile storage device which are received from the controller, to a data input of the first non-volatile storage device.


US Pat. No. 11,112,344

PARTICLE MEASURING METHOD AND DETECTION LIQUID

Kioxia Corporation, Toky...


1. A particle measuring method comprising:irradiating a detection liquid whose solvent is a methyl salicylate with light;
converting scattered light from particles in the detection liquid into an electric signal by using photoelectric conversion after irradiating the detection liquid with the light; and
performing a particle measurement on the detection liquid by using the electric signal.

US Pat. No. 11,114,162

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING A FIRST MEMORY BUNCH AND A SECOND MEMORY BUNCH

Kioxia Corporation, Mina...


1. A semiconductor memory device comprising:a first memory bunch comprising:a first source line extending in a first direction and a second direction perpendicular to the first direction;
a first source side selecting gate transistor arranged on one side in a third direction intersecting the first direction and the second direction of the first source line;
a first source side selecting gate line connected to a gate of the first source side selecting gate transistor, the first source side selecting gate line extending in the first direction and the second direction;
a plurality of first non-volatile memory cells series connected to the first source side selecting gate transistor, the plurality of first non-volatile memory cells arranged on the one side in the third direction of the first source side selecting gate transistor;
a plurality of first word lines stacked in the third direction and each connected to a gate of a corresponding one of the plurality of first non-volatile memory cells, the plurality of first word lines extending in the first direction and the second direction;
a first drain side selecting gate transistor connected to one of the plurality of first non-volatile memory cells, the first drain side selecting gate transistor arranged on the one side in the third direction of the plurality of first non-volatile memory cells;
a first drain side selecting gate line connected to a gate of the first drain side selecting gate transistor, the first drain side selecting gate line extending in the first direction and the second direction; and
a first bit line connected to the first drain side selecting gate transistor, the first bit line arranged on the one side in the third direction of the first drain side selecting gate line, a longitudinal direction of the first bit line being in the second direction;

a second memory bunch comprising:a second source line extending in the first direction and the second direction, the second source line arranged on the one side in the third direction of the first bit line;
a second source side selecting gate transistor arranged on the one side in the third direction of the second source line;
a second source side selecting gate line connected to a gate of the second source side selecting gate transistor, the second source side selecting gate line extending in the first direction and the second direction;
a plurality of second non-volatile memory cells series connected to the second source side selecting gate transistor, the plurality of second non-volatile memory cells arranged on the one side in the third direction of the second source side selecting gate transistor;
a plurality of second word lines stacked in the third direction and each connected to a gate of a corresponding one of the plurality of second non-volatile memory cells, the plurality of second word lines extending in the first direction and the second direction and the plurality of second word lines overlapping with the plurality of first word lines in the third direction;
a second drain side selecting gate transistor connected to one of the plurality of second non-volatile memory cells, the second drain side selecting gate transistor arranged on the one side in the third direction of the plurality of second non-volatile memory cells;
a second drain side selecting gate line connected to a gate of the second drain side selecting gate transistor, the second drain side selecting gate line extending in the first direction and the second direction; and
a second bit line connected to the second drain side selecting gate transistor, the second bit line arranged on the one side in the third direction of the second drain side selecting gate line, a longitudinal direction of the second bit line being in the second direction;

a common bit line;
a first bit line transfer transistor connected between the common bit line and the first bit line; and
a second bit line transfer transistor connected between the common bit line and the second bit line.

US Pat. No. 11,106,128

METHOD FOR DESIGNING MASK SET, RECORDING MEDIUM, TEMPLATE, AND METHOD FOR MANUFACTURING TEMPLATE

Kioxia Corporation, Toky...


1. A method for manufacturing a template, comprising:designing a mask set by:determining a position of an imprint-alignment mark in a first region other than a chip region in an imprint region to be imprinted onto a substrate, the imprint-alignment mark being used for alignment during an imprint;
after determining the position of the imprint-alignment mark, setting a shape of the imprint region based on the position of the imprint-alignment mark, wherein the shape of the imprint region is set such that, when the imprint region is viewed from a top thereof, the imprint region being set to include an outer peripheral portion having an uneven portion with a protruding region and a depressed region, the uneven portion fitting one another between adjacent imprint regions; and
after setting the shape of the imprint region, determining a position of a pattern in a second region within the protruding region, the pattern being used in a process other than the imprint; and

manufacturing the template based on the mask set.

US Pat. No. 11,101,823

MEMORY SYSTEM

KIOXIA CORPORATION, Toky...


1. A memory system comprising:a non-volatile memory; and
a controller configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory, wherein
the iterative correction includes performing a first error correction on each of the plurality of frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame,
each of the plurality of frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction,
each of the second frames includes at least a first symbol and a second symbol,
the syndrome includes a first syndrome and a second syndrome, the second error correction being performed on the first symbols of the second frames using the first syndrome and on the second symbols of the second frames using the second syndrome,
the first syndrome contains information for correcting an error in a first one of the first symbols and information for correcting an error in a second one of the first symbols,
the second syndrome contains information for correcting an error in a first one of the second symbols and information for correcting an error in a second one of the second symbols,
the first one of the first symbols and the first one of the second symbols are parts of a third frame, the third frame being one of the second frames, and
the second one of the first symbols and the second one of the second symbols are parts of a fourth frame, the fourth frame being one of the second frames that is not the third frame.

US Pat. No. 11,100,031

MEMORY SYSTEM, SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD THEREFOR

KIOXIA CORPORATION, Toky...


1. A memory system comprising:a first nonvolatile memory;
a first bridge circuit connected to the first nonvolatile memory;
a second nonvolatile memory;
a second bridge circuit connected to the second nonvolatile memory and connected to the first bridge circuit; and
a controller connected to the first bridge circuit and configured to output, to the first bridge circuit, first data to be stored in the first nonvolatile memory and second data to be stored in the second nonvolatile memory, the first and second data being mapped to one or more multiplexing symbols, each of the multiplexing symbols including a pair of symbols corresponding to a pair of a most significant bit and a least significant bit, the first data being mapped to either one of the most significant bit and the least significant bit, the second data being mapped to the other of the most significant bit and the least significant bit,
wherein the first bridge circuit is configured toupon receipt of the multiplexing symbols, extract the first data from the multiplexing symbols,
store the first data in the first nonvolatile memory,
generate third data using either: one of a most significant bit and a least significant bit corresponding to each of the symbols to which the second data is mapped, or an inverted bit of the one of the most significant bit and the least significant bit, and insert the generated third data into the multiplexing symbols to which the first data was mapped, and
output to the second bridge circuit the multiplexing symbols into which the third data has been inserted.


US Pat. No. 11,100,961

SEMICONDUCTOR STORAGE DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor storage device comprising:a memory cell array above a semiconductor substrate and including a plurality of memory strings, each memory string including a first select gate transistor, a second select gate transistor, and a plurality of memory cell transistors between the first select gate transistor and the second select gate transistor;
a plurality of word lines, each of which extends in a first direction and a second direction crossing the first direction, wherein the word lines are stacked in a third direction crossing the first direction and the second direction, and are connected to gates of the memory cell transistors;
a plurality of bit lines connected to first ends of the memory strings, respectively;
a source line connected to second ends of the memory strings;
a row decoder including a plurality of transfer transistors having first ends connected to the word lines, respectively, and second ends connected to a plurality of voltage supply lines, respectively; and
a voltage generation circuit configured to supply a plurality of voltages to the voltage supply lines, respectively,
wherein the voltage generation circuit includesa first power supply node from which a first power supply voltage is supplied,
a second power supply node from which a second power supply voltage lower than the first power supply voltage is supplied,
a first regulator having a first voltage output node from which a first voltage is output to at least one of the voltage supply lines, and having a first signal output node from which a first signal corresponding to a voltage level at the first voltage output node is output,
a second regulator having a second voltage output node from which a second voltage is output to at least another one of the voltage supply lines, and having a second signal output node from which a second signal corresponding to a voltage level at the second voltage output node is output, and
a switch circuit havinga first transistor having a first end connected to the first voltage output node, a second end connected to the second voltage output node, and a gate connected to a first node,
a second transistor having a first end connected to the first node, a second end connected to the second power supply node, and a gate to which the first signal is supplied from the first signal output node, and
a third transistor having a first end connected to the first node, a second end connected to the second power supply node, and a gate to which the second signal is supplied from the second signal output node.



US Pat. No. 11,099,931

MEMORY SYSTEM

KIOXIA CORPORATION, Toky...


1. A memory system comprising:a semiconductor storage device that includes a plurality of memory cells each storing a plurality of bits of data and a word line connected to the plurality of memory cells; and
a memory controller includinga storage circuit that stores correction values for read voltages in association with the word line, and
a control circuit that is configured to select the word line and read data from the memory cells, perform a correction operation on the read data to determine a number of error bits in the data, determine the correction value for each read voltage based on the number of error bits in the data that has been read using the read voltage and a ratio of a lower tail fail bit count and an upper tail fail bit count in the data that has been read using the read voltage, and store the correction values for the read voltages in the storage circuit for subsequent read operations performed on the memory cells, wherein the lower tail fail bit count represents the number of memory cells in a first state having threshold voltages of a second state that is adjacent to the first state, and the upper tail fail bit count represents the number of memory cells in the second state having threshold voltages of the first state.


US Pat. No. 11,100,975

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ADJUSTING THRETHOLD VOLTAGE THEREOF

KIOXIA CORPORATION, Toky...


1. A semiconductor memory device comprising:a plurality of memory cells connected to a word line;
a circuit configured to apply a voltage to the word line;
a detection circuit configured to detect a first time difference from when a first signal of which a voltage is increased with a first single slope is applied to the word line to when a current flows through the memory cells in response to applying the first signal, and a second time difference from when a second signal of which a voltage is increased with a second single slope is applied to the word line to when a current flows through the memory cells in response to applying the second signal, the second slope being different from the first slope; and
a determination circuit configured to determine a threshold voltage of the memory cells based on a difference between the first time difference and the second time difference.

US Pat. No. 11,101,005

MEMORY DEVICE TO EXECUTE READ OPERATION USING READ TARGET VOLTAGE

KIOXIA CORPORATION, Toky...


1. A memory device comprising:a bit line;
a source line;
a first memory string including:a first select transistor connected to the bit line;
a first memory cell transistor disposed below the first select transistor;
a first junction portion disposed below the first memory cell transistor;
a second memory cell transistor disposed below the first junction portion; and
a second select transistor disposed below the second memory cell transistor and connected to the source line;

a second memory string including:a third select transistor connected to the bit line;
a third memory cell transistor disposed below the third select transistor;
a second junction portion disposed below the third memory cell transistor;
a fourth memory cell transistor disposed below the second junction portion; and
a fourth select transistor disposed below the fourth memory cell transistor and connected to the source line;

a first select gate line connected to a gate of the first select transistor;
a second select gate line connected to a gate of the second select transistor;
a third select gate line connected to a gate of the third select transistor;
a fourth select gate line connected to a gate of the fourth select transistor;
a first word line connected to a gate of the first memory cell transistor and a gate of the third memory cell transistor;
a second word line connected to a gate of the second memory cell transistor and a gate of the fourth memory cell transistor; and
a controller configured to execute a read operation, the read operation including a first phase and a second phase after the first phase,
wherein when the read operation for the first memory cell transistor is performed,during the first phase,


a first voltage is applied to the first select gate line, the second select gate line, and the third select gate line,
a second voltage lower than the first voltage and higher than a ground voltage is applied to the source line, and
a read pass voltage is applied to the first word line and the second word line, andduring the second phase,

the first voltage is applied to the first select gate line and the second select gate line, and
the second voltage is applied to the third select gate line and the source line,
the read pass voltage is applied to the second word line, and
a read target voltage lower than the read pass voltage is applied to the first word line, andwherein when the read operation for the second memory cell transistor is performed,during the first phase,


the first voltage is applied to the first select gate line,
the second select gate line, and the fourth select gate line,
the second voltage is applied to the source line, and
the read pass voltage is applied to the first word line and the second word line, andduring the second phase,

the first voltage is applied to the first select gate line and the second select gate line,
the second voltage is applied to the fourth select gate line and the source line,
the read pass voltage is applied to the first word line, and
the read target voltage is applied to the second word line.

US Pat. No. 11,101,008

SEMICONDUCTOR MEMORY DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor memory device comprising:a first memory transistor having a gate electrode;
a first word line connected to the gate electrode of the first memory transistor;
a peripheral circuit connected to the first word line; and
a plurality of electrodes connected to the peripheral circuit and configured to receive data input and provide data output, wherein
in response to a write command via the plurality of electrodes, the peripheral circuit is configured to:
execute a first write sequence including a first program operation of applying a first program voltage to the first word line at least one time when the write command is one of an n1-th write command to an n2-th write command corresponding to the memory transistor, each of the n1 and n2 being a natural number, n2 being greater than n1, and
execute a second write sequence including a second program operation of applying a second program voltage to the first word line at least one time when the write command is one of an (n2+1)-th write command to an n3-th write command corresponding to the memory transistor, n3 being a natural number greater than n2, wherein
the corresponding second program voltage in a k-th one of the second program operations of the second write sequence is less than the corresponding first program voltage in a k-th one of the first program operations in the first write sequence, k being a natural number,
wherein when at least one of the first write sequence or the second write sequence is executed m times, wherein m, a natural number, corresponds to a maximum number of times of the first program operation or the second program operation,
and wherein an average value of the second program voltage from a first second program operation to an m-th second program operation of the second write sequence is less than an average value of first program voltage from a first first program operation to an m-th first program operation of the first write sequence.

US Pat. No. 11,094,366

SYSTEMS AND METHODS TO CONTROL SEMICONDUCTOR MEMORY DEVICE IN VARIOUS TIMINGS

KIOXIA CORPORATION, Toky...


1. A semiconductor memory device comprising:a first memory cell;
a second memory cell;
a word line connected to the first memory cell and the second memory cell;
a first bit line connected to the first memory cell;
a second bit line connected to the second memory cell;
a first select transistor connected between the first memory cell and the first bit line;
a second select transistor connected between the second memory cell and the second bit line;
a first select gate line connected to the first select transistor;
a second select gate line connected to the second select transistor;
a controller configured to execute a write operation that includes a program operation, wherein
in the program operation, the controller is configured to apply a first voltage to the first select gate line and the second select gate line at a first timing, apply a second voltage lower than the first voltage to the first select gate line and the second select gate line at a second timing after the first timing, apply a third voltage higher than the second voltage to the word line at a third timing after the second timing, apply a fourth voltage to the first select gate line at a fourth timing after the second timing when the first memory cell is selected or to the second select gate line at the fourth timing when the second memory cell is selected, the fourth voltage between the first voltage and the second voltage, and apply a fifth voltage higher than the third voltage to the word line at a fifth timing after the third timing, and
in the program operation when the first memory cell is selected, a first time period being a difference between the second and third timings, and in the program operation when the second memory cell is selected, a second time period being a difference between the second and third timings, wherein the second time period is different from the first time period;
a substrate;
a first conductor layer provided in a first layer above the substrate and configured to function as the word line;
a second conductor layer in a second layer above the first layer, and configured to function as the first select gate line;
a third conductor layer provided in the second layer and separate from the second conductor layer, and configured to function as the second select gate line;
a first semiconductor layer penetrating the first conductor layer and the second conductor layer; and
a second semiconductor layer penetrating the first conductor layer and the third conductor layer;
wherein a first intersection portion of the first conductor layer and the second semiconductor layer functions as the first memory cell,
a second intersection portion of the second conductor layer and the first semiconductor layer functions as the first select transistor,
a third intersection portion of the first conductor layer and the second semiconductor layer functions as the second memory cell, and
a fourth intersection portion of the third conductor layer and the second semiconductor layer functions as the second select transistor,
wherein a resistance value of the second conductor layer is lower than a resistance value of the third conductor layer, and the first time period is shorter than the second time period.

US Pat. No. 11,094,380

SEMICONDUCTOR MEMORY DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor memory device comprising:a substrate having a horizontal surface;
a first bit line;
a first source line;
a memory block including a first memory string and a second memory string each electrically connected between the first bit line and the first source line,the first memory string including a first selection transistor and series-connected memory cell transistors that are vertically arranged and include a first memory cell transistor and a second memory cell transistor, and
the second memory string including a second selection transistor and series-connected memory cell transistors that are vertically arranged and include a third memory cell transistor and a fourth memory cell transistor;

a first select gate line connected to a gate of the first selection transistor;
a second select gate line connected to a gate of the second selection transistor;
a first word line connected to a gate of the first memory cell transistor and a gate of the third memory cell transistor;
a second word line connected to a gate of the second memory cell transistor and a gate of the fourth memory cell transistor; and
a state machine configured toupon receipt of an erase command from outside the semiconductor memory device, perform an erase operation on the first memory cell transistor, the second memory cell transistor, the third memory cell transistor, and the fourth memory cell transistor, the erase operation including an erase voltage apply operation and an erase verify operation subsequent to the erase voltage apply operation, wherein

in the erase verify operation subsequent to the erase voltage apply operation,at a first timing, a first voltage is applied to the first word line and the second word line, and a second voltage is applied to the first select gate line,
at a second timing after the first timing, the first voltage is applied to the first word line and the second word line, and a third voltage lower than the first voltage is applied to the first select gate line,
at a third timing after the second timing, the first voltage is applied to the first word line and the second word line, and the second voltage is applied to the second select gate line, and
at a fourth timing after the third timing, the first voltage is applied to the first word line and the second word line, and the third voltage is applied to the second select gate line.


US Pat. No. 11,093,149

METHOD TO EFFICIENTLY STORE OBJECT DATA OF AN OBJECT STORAGE SERVICE ON A MAGNETIC DISK DRIVE AND MAGNETIC SMR DISK DRIVE

KIOXIA CORPORATION, Toky...


1. A method of storing data in a data storage system that includes a first storage device, a non-volatile second storage device having lower speed of storing data than the first storage device, and a non-volatile third storage device having lower speed of storing data than the non-volatile second storage device, the non-volatile third storage device including at least one disk drive, the method comprising:receiving a key-value pair for storage from a client;
storing the received key-value pair into the first storage device;
recording, into the non-volatile second storage device, a mapping of a key of the key-value pair received and stored in the first storage device to a physical location in the non-volatile third storage device at which the key-value pair is to be stored;
returning an acknowledgement to the client upon storing the received key-value pair into the first storage device and recording the mapping into the second non-volatile storage device; and
storing the received key-value pair into the physical location in the non-volatile third storage device, after storing the received key-value pair into the first storage device and recording the mapping into the non-volatile second storage device.

US Pat. No. 11,093,173

MEMORY SYSTEM

Kioxia Corporation, Mina...


1. A memory system comprising:a plurality of memory cells; and
a memory controller configured to update a set value of a read voltage for the plurality of memory cells at a plurality of time points;
wherein the memory controller is configured to execute a first operation of observing an optimum value of the read voltage and updating the set value based on the observation result of the optimum value, at a predetermined time point of the plurality of time points, and
execute a second operation of updating the set value based on the set value updated at one previous time point without executing the observation of the optimum value, at a time point after one time point of the predetermined time point of the plurality of time points.

US Pat. No. 11,093,811

MEMORY CARD WITH MULTIPLE MODES, AND HOST DEVICE CORRESPONDING TO THE MEMORY CARD

Kioxia Corporation, Mina...


12. A host device comprising:a connector to be connected to a memory card;
a physical layer interface that transmits a first differential data signal to the connector via a first transmission path and receives a second differential data signal from the connector via a second transmission path;
a first capacitor provided to isolate DC current of the first transmission path;
a second capacitor provided to isolate DC current of the second transmission path; and
a controller;
wherein the connector has a shape complying with a first form factor compliant with a microSD card, a second form factor compliant with a standard-size SD card, or a third form factor encompassing the first form factor and encompassed in the second form factor,
wherein the connector includes:1st to Nth connector contact groups to be connected to 1st to Nth terminal groups on the memory card that comprises a 1st surface including first to Nth rows, where N is an integer of two or greater, a second surface facing the opposite side from the first surface, and the 1st to the Nth terminal groups placed in the 1st to the Nth rows, each of the 1st to the Nth rows being an area where three or more terminals are arranged in a linear fashion; and

1st to Nth connector terminal groups to connect the 1st to the Nth connector contact groups of the connector to the controller side,
wherein the 1st connector terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a first connector power supply terminal to which a first power supply voltage is applied, and
wherein Kth connector terminal group, where K is an integer no smaller than two and no greater than N, includes a terminal to which the first differential data signal is assigned and a terminal to which the second differential data signal is assigned.

US Pat. No. 11,086,718

MEMORY SYSTEM

KIOXIA CORPORATION, Toky...


8. A method of operating a memory system, the method comprising:writing a plurality of data bits temporarily stored in a buffer, to a nonvolatile memory;
writing a plurality of intermediate parity bits to the buffer but not to the nonvolatile memory, each of the plurality of intermediate parity bits associated with an error correction process on each of the plurality of data bits; and
writing, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

US Pat. No. 11,084,069

CHUCK CLEANER AND CLEANING METHOD

KIOXIA CORPORATION, Toky...


1. A cleaning method comprising:with a chuck cleaner including a support, an adhesive layer and a support substrate provided between the support and the adhesive layer, the support including first and second raised portions disposed at opposed perimeter portions thereof, a plurality of third raised portions, and a plurality of recessed portions defined between respective adjacent third raised portions as well as between the first and the second raised portions and the third raised portions, peripheral portions of the support substrate being fixed to the first and second raised portions of the support, a bottom surface of an inner region of the support substrate being adapted to engage an upper surface of each of the plurality of third raised portions in a first state and being spaced from the upper surface of each of the plurality of third raised portions in a second state, the support substrate including a first region fixed to the first raised portion, a second region fixed to the second raised portion, third regions provided between the first region and the second region and having variable distance from the third raised portions, a total area of the first raised portion, the second raised portion and the third raised portions being smaller than an area of the recessed portions when viewed from a first direction toward the first region from the first raised portion,
bringing the adhesive layer of the chuck cleaner in contact with a foreign matter adhering to a chuck part; and
separating the adhesive layer from the chuck part to move the foreign matter from the chuck part to the adhesive layer.

US Pat. No. 11,088,691

OSCILLATION CIRCUIT AND INTERFACE CIRCUIT

Kioxia Corporation, Mina...


1. An oscillation circuit comprising:a voltage generator configured to generate a linearly changing voltage, a voltage level of which linearly changes as time passes;
a first comparator configured to compare the linearly changing voltage with a first reference voltage;
a second comparator configured to compare the linearly changing voltage with a second reference voltage having a higher voltage level than the first reference voltage;
a time-to-digital converter configured to output a bit sequence signal in accordance with a time difference between a time when the first comparator detects that the linearly changing voltage matches the first reference voltage and a time when the second comparator detects that the linearly changing voltage matches the second reference voltage; and
an oscillator configured to generate an oscillation signal that oscillates at a frequency according to the bit sequence signal.

US Pat. No. 11,081,163

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND SEMICONDUCTOR STORAGE DEVICE

Kioxia Corporation, Mina...


1. An information processing apparatus, comprising:a connector into which a first-type semiconductor storage device operating with n types of power supply voltages supplied from outside or a second-type semiconductor storage device operating with m types of power supply voltages supplied from outside is capable of being placed, the m types of power supply voltages being less than the n types of power supply voltages, n being an integer of 2 or more, m being an integer of 1 or more and being less than n,
the information processing apparatus being configured to:
check whether or not a notch is formed at a predetermined position of a semiconductor storage device placed into the connector, when the information processing apparatus is configured to supply the m types of power supply voltages to the second-type semiconductor storage device;
supply no power supply voltages to the semiconductor storage device placed into the connector, when the notch is not formed at the predetermined position of the semiconductor storage device placed into the connector; and
supply the m types of power supply voltages to the semiconductor storage device placed into the connector, when the notch is formed at the predetermined position of the semiconductor storage device placed into the connector, wherein
the information processing apparatus is configured to:
when receiving a clock request signal to request a reference clock signal from the semiconductor storage device placed into the connector after supplying the m types of power supply voltages to the semiconductor storage device placed into the connector, supply the reference clock signal to the semiconductor storage device placed into the connector.

US Pat. No. 11,081,175

SEMICONDUCTOR DEVICE AND MEMORY DEVICE

Kioxia Corporation, Toky...


1. A semiconductor device comprising:first signal lines that transmit first signals;
second signal lines that receive the first signals; and
a first circuit including a first selector circuit, a second selector circuit, third signal lines, and fourth signal lines, the first selector circuit being coupled to the first signal lines, the second selector circuit being coupled to the second signal lines, the third signal lines being coupled between the first and second selector circuits, and the fourth signal lines being coupled between the first and second selector circuits, wherein
each of the third signal lines stores a corresponding one of the second signals, and
each of the fourth signal lines stores a corresponding one of the third signals,
the first circuit is configured to:count a first number of second signals equivalent to corresponding first signal of the first signals, with respect to the first and third signal lines;
count a second number of third signals equivalent to the corresponding first signal, with respect to the first and fourth signal lines; and
electrically couple either the third signal lines or the fourth signal lines to the first and second signal lines via the first and second selector circuits, based on a result of comparison between the first number and the second number.


US Pat. No. 11,081,183

MEMORY SYSTEM AND CONTROL METHOD OF MEMORY SYSTEM FOR CONTROLLING OF FIRST AND SECOND WRITING OPERATIONS

Kioxia Corporation, Mina...


1. A memory system comprising:a semiconductor memory device including a first memory string and a second memory string each including a plurality of memory cell transistors electrically coupled in series; and
a memory controller configured to instruct the semiconductor memory device to execute a write operation for writing data on any one of the memory cell transistors in the first memory string or in the second memory string, wherein
the first memory string and the second memory string are electrically coupled in parallel between a bit line and a source line, and electrically coupled to different word lines,
the write operation includes a first write operation and a second write operation executed after the first write operation, and
the memory controller is configured to instruct the semiconductor memory device to execute the first write operation on a second memory cell transistor in the second memory string between the first write operation on a first memory cell transistor in the first memory string and the second write operation on the first memory cell transistor.

US Pat. No. 11,081,188

SEMICONDUCTOR MEMORY DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor memory device comprising:a bit line;
a source line;
a memory cell connected between the bit line and the source line;
a word line connected to a gate of the memory cell; and
a controller configured to execute a read operation,
wherein in the read operation, the controller is configured to:apply a first read voltage and a second read voltage different from the first read voltage to the word line,
read data at each of a first time and a second time, the first time being a time at which the first read voltage is applied to the word line, and the second time being a time at which the second read voltage is applied to the word line,
apply a first voltage to the source line at each of the first time and the second time,
apply a second voltage higher than the first voltage to the source line during the application of the first read voltage to the word line and before the first time, and
apply a third voltage lower than the first voltage to the source line during the application of the second read voltage to the word line and before the second time.


US Pat. No. 11,081,526

NONVOLATILE MEMORY DEVICE

KIOXIA CORPORATION, Toky...


1. A nonvolatile memory device, comprising:a first wiring extending in a first direction;
a second wiring extending in a second direction that intersects with the first direction;
a third wiring extending in the second direction and spaced from the second wiring in the first direction;
an insulating layer including a first portion between the second wiring and the third wiring in the first direction and a second portion protruding from the first portion in a third direction beyond ends of the second and third wirings in the third direction, the third direction intersecting with the first and second directions; and
a chalcogenide layer between the first wiring and the second wiring, between first wiring and the third wiring, and between the first wiring and insulating layer, wherein
the chalcogenide layer includes a first layer portion between the first wiring and the second wiring, a second layer portion between the first wiring and the third wiring, and a third layer portion between the first wiring and the insulating layer, a concentration of a first element in the third layer portion being higher than a concentration of the first element in the first layer portion and a concentration of the first element in the second layer portion.

US Pat. No. 11,082,048

SEMICONDUCTOR INTEGRATED CIRCUIT, RECEIVING DEVICE, AND CONTROL METHOD OF RECEIVING DEVICE

Kioxia Corporation, Toky...


1. A semiconductor integrated circuit comprising:a determination circuit configured to generate first transition information, second transition information, and phase determination information, with respect to a signal level of a modulation signal, the modulation signal making transition between a first signal level, a second signal level, a third signal level, and a fourth signal level, the second signal level being a level higher than the first signal level, the third signal level being a level between the first signal level and the second signal level, the fourth signal level being a level between the third signal level and the second signal level, the first transition information indicating a state of a first transition edge of transition between the first signal level and the second signal level, the second transition information indicating a state of a second transition edge of transition between the third signal level and the fourth signal level, the phase determination information indicating a result of a phase determination of a clock signal; and
an estimation circuit configured to estimate a deviation between a timing of the first transition edge and a timing of the second transition edge according to the first transition information, the second transition information, and the phase determination information.

US Pat. No. 11,069,407

SEMICONDUCTOR MEMORY DEVICE

KIOXIA CORPORATION, Toky...


1. A semiconductor memory device, comprising:a plurality of first wirings,
a plurality of second wirings intersecting the plurality of first wirings, and
a plurality of memory cells, each of the plurality of memory cells being respectively formed between one of the plurality of first wirings and one of the plurality of second wirings, and including a variable resistance layer and a nonlinear element layer including chalcogen,
wherein the memory device is configured such that:in a set operation, a set pulse is supplied between one of the plurality of first wirings and one of the plurality of second wirings,
in a reset operation, a reset pulse is supplied between one of the plurality of first wirings and one of the plurality of second wirings,
in a first operation, a first pulse is supplied between one of the plurality of first wirings and one of the plurality of second wirings, and
the first pulse has an amplitude equal to or greater than the greater of an amplitude of the set pulse and an amplitude of the reset pulse and has a pulse width greater than a pulse width of the set pulse.


US Pat. No. 11,069,513

CHARGED PARTICLE BEAM APPARATUS

KIOXIA CORPORATION, Toky...


1. A charged particle beam apparatus comprising:a chamber configured to accommodate a sample with an inside of the chamber being decompressed;
a tube having an opening disposed in the chamber and configured to introduce a mixed gas, having a plurality of types of gases, in a direction towards the sample;
a first beam generator configured to emit a charged particle beam toward at least one of a region between an opening of the tube and the sample or a region of the sample against which the mixed gas collides; and
a mixed gas generator configured to provide the mixed gas to the tube,
wherein the opening of the tube has an elongated shape in a cross section in a direction substantially perpendicular to a flow direction of the mixed gas.