US Pat. No. 9,402,312

CIRCUIT ASSEMBLIES WITH MULTIPLE INTERPOSER SUBSTRATES, AND METHODS OF FABRICATION

Invensas Corporation, Sa...

1. A circuit assembly comprising:
a combined interposer comprising a plurality of constituent interposers, each constituent interposer comprising a substrate,
the substrates being laterally spaced from each other;

wherein the combined interposer comprises a first circuit layer comprising a circuitry and physically contacting a top surface
of two or more of the substrates, the circuitry comprising a circuit extending over at least two of said two or more of the
substrates;

wherein for each of two or more of the constituent interposers, the constituent interposer comprises a first constituent circuit
layer which is part of the first circuit layer, the first constituent circuit layer being present on a top surface of the
constituent interposer's substrate, the first constituent circuit layer comprising circuitry;

wherein the first circuit layer comprises first contact pads on top;
wherein the circuit assembly further comprises one or more circuit modules at least one of which comprises an integrated circuit,
the one or more circuit modules overlying the first circuit layer, each circuit module comprising one or more contact pads
attached to one or more first contact pads;

wherein at least a portion of at least one first contact pad overlies a gap separating at least two of the adjacent substrates
from each other.

US Pat. No. 9,123,780

METHOD AND STRUCTURES FOR HEAT DISSIPATING INTERPOSERS

Invensas Corporation, Sa...

1. A method for making an interconnect element, comprising:
depositing a thermally conductive layer on an in-process unit, the in-process unit including a semiconductor material layer
defining a surface and edges surrounding the surface, a plurality of conductive elements, each conductive element having a
first portion extending through the semiconductor material layer, a second portion extending from the surface of the semiconductor
material layer, and dielectric coatings extending over at least the second portion of each conductive element, each of the
conductive elements further including an edge surface and a end surface, the end surface being spaced apart from the surface
of the semiconductor material layer,

wherein the thermally conductive layer is deposited on the in-process unit at a thickness of at least 10 microns so as to
overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements
with the dielectric coatings positioned between the conductive elements and the thermally conductive layer, and

wherein the thermally conductive layer is deposited to extend along respective edge surfaces and end surfaces of the plurality
of conductive elements, and wherein the method further includes removing a portion of the thermally conductive layer that
extends along the end surface to expose the end surface at a surface of the thermally conductive layer.

US Pat. No. 9,153,517

ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED DIE ASSEMBLIES

Invensas Corporation, Sa...

1. A method for forming a connector on a die pad at a wafer level of processing, comprising:
forming a conformal electrically insulative coating overlying at least a front surface of the wafer, wherein the die pads
are exposed by openings in the conformal coating;

forming a channel defining an interconnect die edge and a void within the channel;
forming spots of a curable electrically conductive polymer material after forming the conformal electrically insulative coating,
wherein the spots are formed over the die pad and extending over the interconnect die edge and at least partially over the
void;

curing the conductive polymer material; and
in a wafer cutting procedure thereafter, severing the spots.

US Pat. No. 9,521,755

MULTILAYER WIRING BOARD FOR AN ELECTRONIC DEVICE

Invensas Corporation, Sa...

1. An electronic assembly comprising:
a flexible insulating film having a first major surface and a first patterned metal wiring film extending parallel to the
first major surface;

a semiconductor component positioned within the flexible insulating film and having a thickness of less than 50 micrometers;
a conductive interconnect extending through the flexible insulating film; a second patterned metal wiring film adjacent a
first external surface of the electronic assembly; and

a third patterned metal wiring film adjacent a second external surface of the electronic assembly,
wherein the second patterned metal wiring film is electrically coupled with the third patterned metal wiring film through
the conductive interconnect,

wherein the semiconductor component is coupled to the first patterned metal wiring film and at least one of the second patterned
metal wiring film or the third patterned metal wiring film, and

wherein the assembly includes a flexible portion and a rigid portion, the flexible portion including at least a portion of
the flexible insulating film extending beyond the rigid portion of the assembly, and

wherein the first patterned metal wiring film overlying the at least a portion of the flexible insulating film forms an external
edge of the assembly and wherein the at least a portion of the first patterned metal wiring film extending beyond the rigid
portion of the assembly is exposed.

US Pat. No. 9,099,482

METHOD OF PROCESSING A DEVICE SUBSTRATE

Invensas Corporation, Sa...

1. A method of processing a device substrate, comprising:
a) bonding a first surface of a device substrate to a carrier with a polymeric material or a dielectric material, wherein
the device substrate has a plurality of integral portions which are bounded at edges of each integral portion at dicing lanes
of the device substrate, wherein the integral portions are configured to be separated from one another by severing the device
substrate along the dicing lanes, wherein the device substrate has a plurality of first openings and a plurality of second
openings, the first and second openings extending from the first surface towards a second surface of the device substrate
opposite from the first surface, wherein the device substrate includes a plurality of electrically conductive columns extending
within the plurality of second openings extending in a direction of a thickness of the device substrate;

b) then removing material exposed at the second surface of the device substrate to cause at least some of the first openings
and at least some of the second openings to communicate with the second surface and at least some of the electrically conductive
columns to protrude from the second surface;

c) then exposing at least a portion of the polymeric material or the dielectric material disposed between the first surface
and the carrier substrate to a substance through at least some first openings to debond the device substrate from the carrier
substrate; and

(d) then separating the integral portions from one another by severing the debonded device substrate along the dicing lanes.

US Pat. No. 9,147,583

SELECTIVE DIE ELECTRICAL INSULATION BY ADDITIVE PROCESS

Invensas Corporation, Sa...

11. A method for forming a stacked die assembly, comprising:
providing semiconductor die having electrical interconnect pads arranged in an interconnect margin adjacent an interconnect
die edge;

stacking a plurality of said die such that the pads in successive die in the stack are arranged in a column;
and then selectively depositing electrical insulation via a nozzle on less than all of the interconnect pads in the column
such that at least some of the interconnect pads in the column are free from being electrically insulated without requiring
the deposited electrical insulation to be removed and the at least some interconnect pads are available for electrical connection
while other interconnect pads in the column are electrically insulated, the nozzle being controlled so that the dielectric
material flows from the nozzle during intervals when a flow axis of the nozzle is directed at a selected interconnect pad
in the column and does not flow from the nozzle during intervals when the flow axis is directed at an unselected interconnect
pad in the column; and

forming electrically conductive traces over the columns.

US Pat. No. 9,105,483

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

Invensas Corporation, Sa...

1. A microelectronic package comprising:
a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from
the first surface;

at least one microelectronic element overlying the first surface within the first region;
electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within
the second region, at least some of the conductive elements being electrically connected to the at least one microelectronic
element;

wire bonds, each defining a base joined to a respective one of the conductive elements, and each wire bond having a second
portion extending in a direction of a length of the respective wire bond away from the respective base, the second portion
extending upwardly relative to the at least one surface of the substrate at an angle between 25° and 90°, the wire bonds further
having ends remote from the substrate and remote from the bases, wherein at least one of the wire bonds has an axis defined
between the end and the base thereof and coincident with a side surface thereof, wherein the at least one of the wire bonds
in its entirety is positioned on one side of the axis thereof, wherein the end of the at least one of the wire bonds is defined
on a tip that is tapered in at least one direction extending beyond a cylindrical portion of the at least one of the wire
bonds immediately adjacent the tip but not in a direction opposite to the at least one direction extending beyond the cylindrical
portion, in which the tip has a centroid that is offset in a radial direction from an axis of the cylindrical portion of the
wire bond; and

a dielectric encapsulation layer extending from at least one of the first or second surfaces and covering portions of the
wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, the encapsulation
layer overlying at least the second region of the substrate, wherein unencapsulated portions of the wire bonds are defined
by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends.

US Pat. No. 9,111,671

ON-CHIP IMPEDANCE NETWORK WITH DIGITAL COARSE AND ANALOG FINE TUNING

INVENSAS CORPORATION, Sa...

1. A self calibrating resistance circuit, comprising:
a connection providing a signal from a reference resistor;
a resistor network coupled to said connection, wherein said resistor network provides a configurable resistance across said
connection, wherein said resistor network comprises a digital resistor network and an analog resistor network; and

control circuitry for configuring said configurable resistance based on a reference resistance of said reference resistor
by coarsely tuning said resistor network through said digital resistor network and fine tuning said resistor network through
said analog resistor network.

US Pat. No. 9,437,566

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

Invensas Corporation, Sa...

1. A method for attaching a first conductive component to a second conductive component, the method comprising:
(1) melting a first portion of a surface of the first conductive component without melting a second portion of the surface
of the first conductive component even though the second portion's melting temperature is no higher than the first portion's
melting temperature, wherein the second portion is continuous with the first portion;

(2) bringing the melted first portion into physical contact with the second conductive component and cooling the first portion
to form a conductive attachment between the first and second conductive components;

wherein the second portion is not melted in operations (1) and (2); and
wherein the first conductive component comprises a core having a higher melting temperature than the first portion of the
surface of the first conductive component.

US Pat. No. 9,153,533

MICROELECTRONIC ELEMENTS WITH MASTER/SLAVE CONFIGURABILITY

Invensas Corporation, Sa...

1. A semiconductor chip comprising:
a plurality of data lines connectable to an off-chip data bus for transmitting data signals between the semiconductor chip
and at least one other semiconductor chip;

a chip select control for designating the semiconductor chip as a master chip or as a slave chip; and
master chip circuitry configured to perform operations as a master chip in a state in which the chip select control designates
the semiconductor chip as a master chip, the master chip circuitry including circuits for converting between a first format
of first data signals on the data lines or on the data bus and a second format of second data signals at an external data
input-output interface of the semiconductor chip,

the semiconductor chip further comprising control logic coupled to receive an address and an output of the chip select control,
and a set of switches coupled between the data bus and the data lines of such chip configured to enable the transfer of signals
between the data bus and the data lines in a state in which the chip select control designates the semiconductor chip as a
master chip; and when the chip select control designates the semiconductor chip as a slave chip, to enable the transfer of
signals between the data bus and the data lines of the semiconductor chip only when the received address defines an address
within the semiconductor chip.

US Pat. No. 9,355,905

METHODS AND STRUCTURE FOR CARRIER-LESS THIN WAFER HANDLING

Invensas Corporation, Sa...

1. A method of forming a microelectronic assembly, comprising: removing material exposed at portions of a surface of a substrate
to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed
substrate, the supporting portions having a thickness greater than a thickness of the thinned portions, the thinned portions
including electrically conductive interconnects extending in a direction of the thickness of the thinned portions and exposed
at the surface; forming a dielectric layer on the thinned portions; forming openings extending through the dielectric layer,
the interconnects being exposed within the openings; depositing an electrically conductive material within the openings; and
removing material of the processed substrate thereby planarizing a surface of the dielectric layer relative to at least one
of the supporting portions or material of the processed substrate overlying the supporting portions.

US Pat. No. 9,095,074

STRUCTURE FOR MICROELECTRONIC PACKAGING WITH BOND ELEMENTS TO ENCAPSULATION SURFACE

Invensas Corporation, Sa...

1. A structure comprising:
a substrate having first and second oppositely facing surfaces and a plurality of electrically conductive elements at the
first surface;

wire bonds having bases joined to respective ones of the conductive elements at a first portion of the first surface and end
surfaces remote from the substrate and the bases, each of the wire bonds extending from the base to the end surface thereof;
and

a dielectric encapsulation element overlying and extending from the first portion of the first surface of the substrate and
separating the wire bonds from one another, the encapsulation element having a third surface facing away from the first surface
of the substrate and having an edge surface extending from the third surface towards the first surface, wherein unencapsulated
portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the
encapsulation element at the third surface;

wherein the encapsulation element at least partially defines a second portion of the first surface, the second portion being
other than the first portion of the first surface and having an area sized to accommodate a microelectronic element, and at
least some of the conductive elements at the first surface are at the second portion and configured for connection with the
microelectronic element.

US Pat. No. 9,318,467

MULTI-DIE WIREBOND PACKAGES WITH ELONGATED WINDOWS

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a substrate having first and second opposed surfaces, each extending in a first direction and a second direction transverse
to the first direction, the substrate having a first opening extending between the first and second surfaces and defining
first and second distinct parts each elongated along a first common axis extending in the first direction;

first and second microelectronic elements each having respective front surfaces facing the first surface of the substrate
and spaced apart from one another and a column of contacts at the respective front surface, the first and second microelectronic
elements each having a lateral edge extending in the second direction, the lateral edge of the first microelectronic element
confronting the lateral edge of the second microelectronic element, the column of contacts of the first microelectronic element
aligned with the first part of the first opening and extending in the first direction, the column of contacts of the second
microelectronic element aligned with the second part of the first opening and extending in the first direction;

a plurality of terminals exposed at the second surface, the terminals configured for connecting the microelectronic package
to at least one component external to the microelectronic package;

first electrical connections extending from at least some of the contacts of the first microelectronic element to at least
some of the terminals; and

second electrical connections extending from at least some of the contacts of the second microelectronic element to at least
some of the terminals.

US Pat. No. 9,343,398

BGA BALLOUT PARTITION TECHNIQUES FOR SIMPLIFIED LAYOUT IN MOTHERBOARD WITH MULTIPLE POWER SUPPLY RAIL

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a substrate comprising a dielectric element having a surface, terminals comprising at least first power terminals and other
terminals in an area array at the surface, contacts coupled with the terminals, and traces electrically coupling at least
some of the terminals with at least some of the contacts, each trace having a minimum lateral dimension parallel to the surface,
the substrate further comprising a power plane element electrically coupled to the first power terminals and having a minimum
lateral dimension parallel to the surface substantially greater than the minimum lateral dimension of each trace; and

a microelectronic element having element contacts electrically coupled with the terminals through the traces and the contacts
of the substrate,

wherein the area array has a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral
edge in a direction parallel to the surface, the terminals on opposite sides of the gap being spaced from one another by at
least 1.5 times a minimum pitch of the terminals, and the power plane element extends within the gap from at least the peripheral
edge at least to the first power terminals, each first power terminal separated from the peripheral edge by two or more of
the other terminals.

US Pat. No. 9,478,504

MICROELECTRONIC ASSEMBLIES WITH CAVITIES, AND METHODS OF FABRICATION

Invensas Corporation, Sa...

1. A fabrication method comprising:
obtaining a first structure comprising one or more cavities;
obtaining a second structure comprising a first microelectronic component and one or more second microelectronic components,
wherein:

the first microelectronic component comprises a first substrate, the first microelectronic component comprising first circuitry,
wherein the first substrate comprises a first side and one or more first holes in the first side;

each second microelectronic component comprises one or more respective second substrates, each second microelectronic component
comprising respective second circuitry, each second microelectronic component being attached to the first side of the first
substrate, wherein the second circuitry of at least one second microelectronic component is electrically coupled to the first
circuitry;

attaching the first structure to the second structure so that at least one second microelectronic component is located in
at least one of the one or more cavities and so that at least a portion of a sidewall of at least one of the one or more cavities
is located in a corresponding first hole such that at least a portion of a sidewall of the corresponding first hole extends
laterally along a straight line adjacent to at least one second microelectronic component located in said cavity, and such
that said at least a portion of a sidewall of at least one of the one or more cavities extends laterally along the portion
of the corresponding first hole.

US Pat. No. 9,281,296

DIE STACKING TECHNIQUES IN BGA MEMORY PACKAGE FOR SMALL FOOTPRINT CPU AND MEMORY MOTHERBOARD DESIGN

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a substrate comprising a dielectric element having first and second opposite surfaces, a plurality of peripheral edges extending
between the first and second surfaces defining a generally rectangular or square periphery of the substrate, and comprising
a plurality of contacts and terminals, the contacts being at the first surface, the terminals being at at least one of the
first or second surfaces, the terminals including first terminals and second terminals; and

first and second microelectronic elements in a stack on a same side of the first surface, each microelectronic element having
a face extending parallel to the first surface, a plurality of edges bounding the face, and a plurality of element contacts
at the face electrically coupled with the terminals through the contacts of the substrate, the element contacts of each microelectronic
element including first and second contacts electrically coupled to the respective first and second terminals, all of the
first contacts within a first connection region adjacent to a first edge of the edges of the respective microelectronic element,
and all of the second contacts within a second connection region adjacent to a second edge of the edges of the respective
microelectronic element opposite the first edge,

wherein each edge of each microelectronic element is oriented at an oblique angle with respect to the peripheral edges of
the substrate, and each of the first and second edges of the second microelectronic element are oriented at an angle between
60 degrees and 120 degrees relative to the first and second edges of the first microelectronic element, respectively,

wherein the first contacts and the first terminals are configured to carry data information including data signals, and the
second contacts and the second terminals are configured to carry address information, and

wherein a difference in total electrical length between a shortest lead and a longest lead extending between the first terminals
and the first contacts is less than 2% of an inverse of a frequency at which the microelectronic element is configured to
operate.

US Pat. No. 9,165,793

MAKING ELECTRICAL COMPONENTS IN HANDLE WAFERS OF INTEGRATED CIRCUIT PACKAGES

Invensas Corporation, Sa...

1. A method for making an integrated circuit package, the method comprising:
providing a handle wafer having a first region and a second region, the first region at least partially defining a cavity
within the handle wafer, the cavity defining the second region;

forming a capacitor in the first region of the handle wafer, the capacitor having a pair of electrodes, each electrode being
electroconductively coupled to a corresponding one of a pair of electroconductive pads, at least one of which is disposed
on a lower surface of the handle wafer in the first region thereof;

providing an interposer having an upper surface with an electroconductive pad and a semiconductor die disposed thereon, the
die having an integrated circuit (IC) formed therein, the IC being electroconductively coupled to a redistribution layer (RDL)
disposed on or within the interposer; and

bonding the lower surface of the handle wafer to the upper surface of the interposer such that the semiconductor die is disposed
below or within the cavity of the handle wafer and the at least one electroconductive pad of the handle wafer is electroconductively
bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

US Pat. No. 9,136,254

MICROELECTRONIC PACKAGE HAVING WIRE BOND VIAS AND STIFFENING LAYER

Invensas Corporation, Sa...

1. A microelectronic package comprising:
a component having a surface and a plurality of conductive elements at the surface;
a plurality of wire bonds having first ends joined to the conductive elements and second ends remote from the first ends,
the wire bonds having lengths between their respective first and second ends;

a dielectric stiffening layer overlying the conductive elements and the surface, and covering a first portion of the length
of each of the wire bonds; and

an encapsulation layer overlying the dielectric stiffening layer, in which the dielectric stiffening layer is stiffer and
other than the encapsulation layer, above the surface of the component and covering a second portion of the length of each
of the wire bonds, wherein second ends of the wire bonds are at least partially uncovered by the encapsulation layer at a
surface of the encapsulation layer above the dielectric stiffening layer and remote from the dielectric stiffening layer.

US Pat. No. 9,397,051

WARPAGE REDUCTION IN STRUCTURES WITH ELECTRICAL CIRCUITRY

Invensas Corporation, Sa...

1. A manufacturing method comprising:
obtaining a first structure comprising electrical circuitry, the first structure comprising a first surface and a second surface
opposite to the first surface, at least one of the first and second surfaces comprising a first area which is warped;

forming a first layer on the first surface to over-balance a warpage of the first area; and
processing the first layer to reduce the first area's warpage;
wherein:
the first layer is adhesively bonded to the first surface; and
processing the first layer comprises debonding the first layer at one or more selected locations.

US Pat. No. 9,252,116

SEMICONDUCTOR DIE MOUNT BY CONFORMAL DIE COATING

Invensas Corporation, Sa...

1. A method for affixing a die onto a support, comprising providing a first die having a conformal coating on a surface thereof,
providing a support having a conformal coating on a surface thereof, contacting a die attach area of the conformal coating
on the first die directly with a die mount region of the conformal coating on the support, wherein the conformal coatings
on the surfaces of the die and the support are of polyxylylene polymer material, and accomplishing adhesion of the die attach
area with the die mount region of the support by heating at least one of the die attach area of the conformal coating on the
first die or the die mount region of the conformal coating on the support to a temperature sufficient to affect adhesion.

US Pat. No. 9,165,911

MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF

Invensas Corporation, Sa...

1. A method of fabricating a microelectronic package comprising:
stacking a first microelectronic unit onto a second microelectronic unit,
the first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge
of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with
the first chip contacts,

the second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, an encapsulant
contacting an edge of the semiconductor chip of the second microelectronic unit and having a surface extending away from such
edge, the surfaces of the semiconductor chip and the encapsulant of the second microelectronic unit defining a face of the
second microelectronic unit; and

then forming bond wires electrically connecting the first unit contacts with package terminals at the face of the second microelectronic
unit, the package terminals being electrically connected with the second chip contacts through metallized vias and traces
formed in contact with the second chip contacts.

US Pat. No. 9,123,600

MICROELECTRONIC PACKAGE WITH CONSOLIDATED CHIP STRUCTURES

Invensas Corporation, Sa...

1. A microelectronic package comprising:
(a) a package substrate having upper and lower surfaces and terminals at the lower surface;
(b) first and second chips disposed above the package substrate, each of the first and second chips having a front face, a
rear face and contacts at the front face disposed in one or more columns extending in a column direction, the first and second
chips being offset from one another by a center-to-center offset distance in a lateral direction transverse to the column
direction;

(c) interconnect pads disposed in an elongated interconnect zone having a width less than the offset distance, the interconnect
pads facing toward the package substrate at least some of the interconnect pads being electrically connected to at least some
of the contacts of the first and second chips, at least some of the interconnect pads being electrically connected to at least
some of the terminals of the package substrate.

US Pat. No. 9,111,902

DIELECTRIC TRENCHES, NICKEL/TANTALUM OXIDE STRUCTURES, AND CHEMICAL MECHANICAL POLISHING TECHNIQUES

Invensas Corporation, Sa...

1. A structure comprising an integrated circuit comprising
a semiconductor substrate;
a first conductive feature overlying the semiconductor substrate;
one or more second conductive features overlying the semiconductor substrate;
one or more first dielectric trenches completely laterally surrounding the second conductive features and separating the second
conductive features from the first conductive feature;

wherein the first conductive feature completely laterally surrounds the first dielectric trenches;
a third conductive feature overlying the first and second conductive features and physically contacting each second conductive
feature;

one or more fourth conductive features overlying and physically contacting the first conductive feature;
one or more second dielectric trenches completely laterally surrounding the fourth conductive features and separating the
fourth conductive features from the third conductive feature, wherein the third conductive feature completely laterally surrounds
the second dielectric trenches;

third dielectric overlying the first conductive feature and separating the first conductive feature from the third conductive
feature;

wherein the third dielectric physically contacts the one or more first dielectric trenches.

US Pat. No. 9,390,998

HEAT SPREADING SUBSTRATE

Invensas Corporation, Sa...

1. An apparatus comprising:
a thermally conductive, electrically insulating solid;
a first electrically conductive coating mechanically coupled to a first edge of said solid;
a second electrically conductive coating mechanically coupled to a second edge of said solid;
wherein said first and said second electrically conductive coatings are electrically isolated from one another; and
wherein faces of said first electrically conductive coating, said second electrically conductive coating and said solid are
substantially coplanar.

US Pat. No. 9,330,954

SUBSTRATE-TO-CARRIER ADHESION WITHOUT MECHANICAL ADHESION BETWEEN ABUTTING SURFACES THEREOF

Invensas Corporation, Sa...

1. A method, comprising:
placing a substrate on a top surface of a support platform;
wherein a bottom surface of the substrate abuts the top surface of the support platform after placement without adhesive between
the bottom surface and the top surface;

depositing a material over and around the substrate and on the top surface of the support platform;
wherein the material is in contact with a side surface of the substrate to completely seal an interface as between the bottom
surface of the substrate and the top surface of the support platform to retain abutment of the top surface and the bottom
surface without adhesive therebetween;

removing an upper portion of the material;
thinning the substrate including removing more of the material;
back-end-of-line processing the substrate including forming one or more inter-level dielectrics and one or more levels of
metallization; and

dicing the substrate to provide dies.

US Pat. No. 9,331,043

LOCALIZED SEALING OF INTERCONNECT STRUCTURES IN SMALL GAPS

Invensas Corporation, Sa...

1. A microelectronic device, comprising:
a first substrate having a first surface;
first interconnects located on the first surface;
a second substrate having a second surface spaced apart from the first surface with a gap between the first surface and the
second surface;

second interconnects located on the second surface;
lower surfaces of the first interconnects and upper surfaces of the second interconnects being coupled to one another for
electrical conductivity between the first substrate and the second substrate;

a conductive collar around sidewalls of the first and second interconnects; and
a dielectric layer around the conductive collar.

US Pat. No. 9,299,398

RETENTION OPTIMIZED MEMORY DEVICE USING PREDICTIVE DATA INVERSION

Invensas Corporation, Sa...

1. A method comprising,
providing an addressable memory comprising a memory space;
configuring said addressable memory such that a majority of a plurality of memory cells in said memory space stores internal
data values in a preferred bias condition when a first external data state of one or more external data states is written
to said memory space, wherein said first external data state is opposite said preferred bias condition;

when an address of a memory cell to be written is coupled to a bit line that is further coupled to a positive side of a sense
amplifier, inverting a data input value of a data in signal to generate an inverted data input value; and

delivering said inverted data input value to said positive side.

US Pat. No. 9,287,216

MEMORY MODULE IN A PACKAGE

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a substrate having first and second opposed surfaces;
at least two pairs of microelectronic elements, each pair of microelectronic elements including an upper microelectronic element
and a lower microelectronic element, the pairs of microelectronic elements being fully spaced apart from one another in a
horizontal direction parallel to the first surface of the substrate, each lower microelectronic element having a front surface
facing the first surface of the substrate and a plurality of contacts at the front surface, the front surfaces of the lower
microelectronic elements being arranged in a single plane parallel to the first surface, a surface of each of the upper microelectronic
elements at least partially overlying a rear surface of the lower microelectronic element in its pair, the microelectronic
elements together configured to predominantly provide memory storage array function;

a plurality of terminals exposed at the second surface, the terminals configured for connecting the microelectronic package
to at least one component external to the microelectronic package; and

electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some
of the terminals,

wherein at least one of the upper or lower microelectronic elements of each pair of microelectronic elements at least partially
overlies an aperture extending between the first and second surfaces of the substrate, and wherein each aperture has a length
defining respective first and second axes, the first and second axes being transverse to one another.

US Pat. No. 9,263,394

MULTIPLE BOND VIA ARRAYS OF DIFFERENT WIRE HEIGHTS ON A SAME SUBSTRATE

Invensas Corporation, Sa...

1. An apparatus, comprising:
a substrate;
a first bond via array of first wire bond wires (“first wires”) extending from a surface of the substrate;
a second bond via array of second wire bond wires (“second wires”) extending from the surface of the substrate;
wherein the first bond via array and the second bond via array are external to the substrate;
wherein the first bond via array is disposed at least partially within the second bond via array;
wherein the first wires of the first bond via array are of a first height; and
wherein the second wires of the second bond via array are of a second height greater than the first height for coupling of
at least one die to the first bond via array at least partially disposed within the second bond via array.

US Pat. No. 9,257,396

COMPACT SEMICONDUCTOR PACKAGE AND RELATED METHODS

Invensas Corporation, Sa...

1. A method of forming a semiconductor package, comprising:
providing a substrate including one or more conductive elements disposed therein, wherein each conductive element extends
from a first surface of the substrate toward a second surface of the substrate opposite the first surface, and wherein each
conductive element extends beyond the second surface, the second surface comprising one or more substrate regions not occupied
by the one or more conductive elements;

attaching a first die within a first one of the one or more substrate regions at the second surface, such that each conductive
element extends beyond at least part of the first die at the second surface; and

forming one or more interconnect lines spaced from the second surface and coupling the first die to at least one of the one
or more conductive elements and to at least a conductive via through the first die.

US Pat. No. 9,362,204

TUNABLE COMPOSITE INTERPOSER

Invensas Corporation, Sa...

1. A method of fabricating a composite interposer, comprising:
uniting exposed surfaces of at least one of dielectric or semiconductor material of a substrate element and a support element
with one another,

the substrate element having first and second opposite surfaces defining a thickness of 200 microns or less, and having a
plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness,
the exposed surface of the at least one of dielectric or semiconductor material of the substrate element being the second
surface thereof,

the support element having a body having first and second opposite surfaces and a CTE of less than 12 ppm/° C., and having
openings extending between the first and second surfaces of the support element through a thickness of the body, the exposed
surface of the at least one of dielectric or semiconductor material of the support element being the second surface thereof;

forming electrically conductive vias extending within the openings and terminals exposed at the first surface of the support
element, the terminals being electrically connected with the contacts through the conductive vias and the electrically conductive
structure; and

forming a planar laminate conductor layer extending along the second surfaces of the substrate element and the support element,
the conductor layer providing direct electrical connection between the conductive vias and the electrically conductive structure.

US Pat. No. 9,312,175

SURFACE MODIFIED TSV STRUCTURE AND METHODS THEREOF

Invensas Corporation, Sa...

1. A fabrication method for a microelectronic element, the method comprising:
forming an opening extending from a first face of a substrate towards a second face of the substrate opposite thereto, wherein
a wall of the opening includes a dielectric region;

depositing a first metal within the opening so as to extend upwardly from a bottom of the opening towards the first face,
wherein a portion of the dielectric region remains exposed within the opening after depositing the first metal;

depositing a second metal within the opening, the second metal being different from the first metal; and
abrading the substrate from the second face to expose the first metal.

US Pat. No. 9,070,676

BOWL-SHAPED SOLDER STRUCTURE

Invensas Corporation, Sa...

1. An apparatus, comprising:
a substrate;
a first metal layer on the substrate, the first metal layer having an opening, the opening of the first metal layer having
a bottom and one or more sides extending from the bottom;

a second metal layer on the first metal layer;
the first metal layer and the second metal layer providing a bowl-shaped structure, an inner surface of the bowl-shaped structure
defined responsive to the opening of the first metal layer and the second metal layer thereon;

the opening of the bowl-shaped structure being configured to receive and at least partially retain bonding material during
reflow processing; and

the bottom of the bowl-shaped structure having a contour including a recess and a post, the post being a portion of the first
metal layer defined by the recess around the post.

US Pat. No. 9,640,282

FLEXIBLE I/O PARTITION OF MULTI-DIE MEMORY SOLUTION

Invensas Corporation, Sa...

1. A method of testing a microelectronic package configured to provide memory access, comprising:
energizing terminals of the microelectronic package, the microelectronic package having first and second microelectronic elements
each having memory storage array function and configured to provide access to memory storage array locations in the first
and second microelectronic elements,

the terminals including a plurality of first terminals configured to carry address information, a plurality of second terminals
configured to carry data signals, and one or more third terminals configured to receive a test mode input that reconfigures
the first and second microelectronic elements to permit simultaneous access to memory storage array locations in the first
and second microelectronic elements, the energizing including applying the test mode input to the one or more third terminals,
and

the second terminals including a first set of second terminals electrically coupled to the first microelectronic element and
not to the second microelectronic element, and a second set of second terminals electrically coupled to the second microelectronic
element and not to the first microelectronic element; and

while the test mode input is active, applying read and write test data signals simultaneously to the first and second sets
of second terminals, so as to simultaneously test read and write operation in each of the first and second microelectronic
elements.

US Pat. No. 9,412,646

VIA IN SUBSTRATE WITH DEPOSITED LAYER

Invensas Corporation, Sa...

1. A method of treating a microelectronic substrate, comprising:
forming an opening extending at least partially through a semiconductor region of the microelectronic substrate such that
a monocrystalline semiconductor material of the semiconductor region is exposed at an interior surface of the opening and
the interior surface has a surface roughness, the interior surface of the opening being comprised of a sidewall surface, a
bottom surface joined to the sidewall surface, and a plurality of recesses in at least the sidewall surface;

depositing a smoothing layer by:
exposing the opening to a vapor comprising a silicon-bearing material, wherein at least some silicon material from the silicon-bearing
material preferentially deposits in the plurality of recesses upon a decomposition of the silicon-bearing material, and

maintaining the interior surface at a temperature that enables at least a portion of the silicon material to crystallize onto
the monocrystalline semiconductor material as crystals of polysilicon preferentially filling-in the plurality of recesses
to provide the smoothing layer;

wherein the smoothing layer has an exposed surface with surface roughness less than the surface roughness of the interior
surface; and

forming an insulating layer overlying or integral with the smoothing layer within the opening.

US Pat. No. 9,365,947

METHOD FOR PREPARING LOW COST SUBSTRATES

Invensas Corporation, Sa...

1. A method of making a component comprising:
forming a mask over a first conductive portion of a conductive layer to expose a second conductive portion of the conductive
layer,

performing an electrolytic process to remove conductive material from a first region and a second region of the second conductive
portion, the second region aligned with the mask relative to an electric field applied by the electrolytic process, the second
region separating the first region of the second conductive portion from the first conductive portion, the electrolytic process
concentrated relative to the second region such that removal occurs at a relatively higher rate in the second region than
in the first region, wherein the second region of the second conductive portion is completely removed by the electrolytic
process to electrically isolate the first conductive portion from the first region of the second conductive portion so as
to form a plurality of conductive vias.

US Pat. No. 9,281,295

EMBEDDED HEAT SPREADER FOR PACKAGE WITH MULTIPLE MICROELECTRONIC ELEMENTS AND FACE-DOWN CONNECTION

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a substrate having terminals thereon configured for electrical connection with a component external to the package; a first
microelectronic element having a first face adjacent to and facing the substrate, a second face opposite the first face, and
an edge extending between the first and second faces;

a second microelectronic element having a face partially overlying and facing the second face of the first microelectronic
element, a plurality of contacts on the face of the second microelectronic element being disposed beyond the edge of the first
microelectronic element;

first and second sheet-like heat spreaders spaced apart from one another along a same plane and forming an opening therebetween,
the first heat spreader separating the first and second microelectronic elements; and

connections extending between the first and second heat spreaders, wherein the connections extend through the opening and
between the plurality of contacts and the terminals to electrically couple the second microelectronic element and the terminals.

US Pat. No. 9,123,555

CO-SUPPORT FOR XFD PACKAGING

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a dielectric element having first and second oppositely facing surfaces, and having first and second spaced apart apertures
each extending between the first and second surfaces;

a first microelectronic element having a front face facing said first surface, a rear face facing away from said first surface
and an edge extending between said front and rear faces, said first microelectronic element having contacts exposed at said
front face; and

a second microelectronic element having a front face partially overlying said rear face of said first microelectronic element
and facing said first surface, said second microelectronic element having contacts disposed in a central region of its front
face, said contacts disposed beyond said edge of said first microelectronic element,

said dielectric element having terminals at said second surface, said contacts of said first microelectronic element overlying
said first aperture and electrically coupled with said terminals, and said contacts of said second microelectronic element
overlying said second aperture and electrically coupled with said terminals,

said terminals including a plurality of first terminals between said first and second apertures configured to carry all data
signals for read and write access to random access addressable memory locations of memory storage arrays within the first
and second microelectronic elements.

US Pat. No. 9,373,585

POLYMER MEMBER BASED INTERCONNECT

INVENSAS CORPORATION, Sa...

1. A first structure comprising:
a substrate comprising a top surface and comprising circuitry with one or more contact pads at the top surface;
a first microelectronic component disposed on a first region of the substrate;
a plurality of first members disposed on a second region of the substrate, each first member comprising a dielectric core
comprising one or more polymers, each first member also comprising a plurality of conductive lines each of which extends on
a sidewall surface of the dielectric core of the first member and extends from the second region of the substrate to a top
of the first member, each conductive line being electrically connected to at least one said contact pad; and

wherein each conductive line comprises one or more contact pads for connecting the corresponding first member to one or more
second microelectronic components.

US Pat. No. 9,397,038

MICROELECTRONIC COMPONENTS WITH FEATURES WRAPPING AROUND PROTRUSIONS OF CONDUCTIVE VIAS PROTRUDING FROM THROUGH-HOLES PASSING THROUGH SUBSTRATES

Invensas Corporation, Sa...

15. A manufacturing method comprising:
providing a structure comprising:
a substrate comprising a top surface, a bottom surface, and one or more first through-holes each of which passes between the
top surface and the bottom surface;

one or more conductive vias protruding from the one or more first through-holes to form at each first through-hole a conductive
protrusion above the substrate;

after providing the structure, forming over the substrate, for each conductive protrusion protruding from a corresponding
first through-hole, a first conductive sleeve region wrapping around the conductive protrusion and extending at least along
a segment of the conductive protrusion, the first conductive sleeve region being electrically insulated from any conductive
protrusion protruding from the first through-hole above the substrate, the first conductive sleeve region comprising an inner
surface facing the conductive protrusion, an outer surface opposite to the inner surface, and a thickness which is a distance
between the inner and outer surfaces, a maximum value of the thickness being smaller than a length of the inner surface measured
along the segment.

US Pat. No. 9,385,036

RELIABLE PACKAGING AND INTERCONNECT STRUCTURES

Invensas Corporation, Sa...

1. A method of manufacturing a structure comprising a semiconductor device, the method comprising:
forming a first opening in a substrate, the first opening extending down into the substrate;
forming a first feature for an interconnect structure, the first feature being electrically conductive and having a sidewall
in the first opening; and

forming a second feature overlying the first feature and extending down into the first opening along the sidewall of the first
feature, the second feature comprising a first material different from any material in the sidewall and top of the first feature.

US Pat. No. 9,368,479

THERMAL VIAS DISPOSED IN A SUBSTRATE PROXIMATE TO A WELL THEREOF

Invensas Corporation, Sa...

1. An apparatus, comprising:
a three-dimensional stacked integrated circuit having at least a first die and a second die interconnected to one another
using die-to-die interconnects;

wherein a substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate
toward a well of the substrate without extending to the well and without extending through the substrate;

wherein a first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate
for conduction of heat away therefrom;

wherein the substrate has at least one through substrate via structure extending from the lower surface of the substrate to
an upper surface of the substrate;

wherein a second end of the at least one thermal via structure is coupled to at least one through die via structure of the
second die for thermal conductivity;

wherein the substrate is a semiconductor-on-insulator substrate having a buried dielectric layer; and
wherein the first end stops on the buried dielectric layer of the substrate.

US Pat. No. 9,287,195

STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS HAVING MODULO-X SYMMETRY FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a substrate having first and second opposed surfaces, the first surface having substrate contacts thereon;
a microelectronic element embodying a greater number of active devices to provide memory storage array function than any other
function, the microelectronic element having a rear face facing the first surface, a front face opposite the rear face, and
contacts on the front face electrically connected with the substrate contacts through conductive structure extending above
the front face;

a plurality of terminals at the second surface configured for connecting the microelectronic package with at least one component
external to the package, the terminals electrically coupled with the substrate contacts and including first and second groups
of data terminals, each of the first and second groups having at least eight data terminals disposed on first and second opposite
sides of an axis, respectively,

wherein each of the data terminals of the first and second groups are configured to carry data signals for read and write
access to random access addressable memory locations of a memory storage array within the microelectronic element, and the
data terminals of the first group have modulo-X symmetry about the axis with the second group of the data terminals, wherein
X is a whole number greater than 2.

US Pat. No. 9,224,431

STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS

Invensas Corporation, Sa...

1. A microelectronic structure, comprising:
active elements defining a memory storage array;
address input contacts for receipt of address information specifying locations within the storage array; and
data contacts configured for transferring data at least one of from the storage array or to the storage array,
the structure having a first surface and first and second peripheral edges each extending away from the first surface and
being opposite from one another, and the structure having terminals exposed at the first surface, the terminals including
first terminals and the structure being configured to provide address information received at the first terminals to the address
input contacts, each of at least some of the first terminals having a signal assignment including information to be transferred
to one or more of the address input contacts,

the first terminals including first and second duplicate sets thereof disposed on first and second opposite sides, respectively,
of a theoretical plane normal to the first surface, wherein signal assignments of the first terminals disposed on the first
side are symmetric about the theoretical plane with the signal assignments of the first terminals disposed on the second side,

the terminals further including first and second duplicate sets of second terminals coupled with the data contacts and exposed
at the first surface, wherein the first set of the first terminals are disposed between the first set of the second terminals
and the first peripheral edge, and the second set of the first terminals are disposed between the second set of the second
terminals and the second peripheral edge.

US Pat. No. 9,484,080

HIGH-BANDWIDTH MEMORY APPLICATION WITH CONTROLLED IMPEDANCE LOADING

Invensas Corporation, Sa...

1. A microelectronic assembly, comprising:
an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth
connection regions; and

first and second microelectronic packages, the first microelectronic package comprising first and second microelectronic elements
and the second microelectronic package comprising third and fourth microelectronic elements, each microelectronic element
electrically coupled to the address bus via the respective connection region,

wherein an electrical characteristic between the first and second connection regions is within a same tolerance of the electrical
characteristic between the second and third connection regions.

US Pat. No. 9,437,536

REVERSED BUILD-UP SUBSTRATE FOR 2.5D

Invensas Corporation, Sa...

1. A method of making an assembly, comprising:
forming a circuit structure defining oppositely-facing front and rear major surfaces, one of the front and rear surfaces being
mechanically coupled to a surface of a carrier, the forming of the circuit structure including:

forming a first dielectric layer mechanically coupled to the carrier, the first dielectric layer defining the front surface,
the first dielectric layer including front contacts at the front surface configured for joining with corresponding contacts
of one or more microelectronic elements, and first conductive traces supported by the first dielectric layer, at least some
of the first traces having maximum widths less than five microns, and

forming rear conductive elements at the rear surface electrically coupled with the front contacts through the first traces;
forming a substrate onto the rear surface of the circuit structure, the forming of the substrate including:
forming a dielectric element directly on the rear surface of the circuit structure, the dielectric element having first conductive
elements facing the rear conductive elements of the circuit structure and joined thereto, the dielectric element further including
second conductive traces supported by the dielectric element and electrically coupled with the first conductive elements,
at least some of the second conductive traces having maximum widths greater than five microns, and

forming terminals at a surface of the substrate facing away from the rear conductive elements, the terminals electrically
coupled with the second traces.

US Pat. No. 9,379,008

METAL PVD-FREE CONDUCTING STRUCTURES

Invensas Corporation, Sa...

1. A method of forming a structure, comprising:
depositing a first material comprising at least one of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As),
antimony (Sb), tellurium (Te), or cadmium (Cd) overlying a first surface of a barrier region, the barrier region overlying
a first surface of a semiconductor region;

depositing a second material comprising a first metal overlying the first surface of the barrier region; and
heat treating the first and second material to form an alloy region overlying the first surface of the barrier region.

US Pat. No. 9,379,074

DIE STACKS WITH ONE OR MORE BOND VIA ARRAYS OF WIRE BOND WIRES AND WITH ONE OR MORE ARRAYS OF BUMP INTERCONNECTS

Invensas Corporation, Sa...

1. An apparatus, comprising:
a substrate;
a first bond via array with first wire bond wires (“first wires”) each of a first length extending from a first surface of
the substrate;

an array of bump interconnects disposed on the first surface of the substrate;
a die interconnected to the substrate via the array of bump interconnects coupled to a first surface of the die; and
a second bond via array with second wire bond wires (“second wires”) each of a second length different than the first length
extending from a second surface of the die opposite the first surface of the die.

US Pat. No. 9,373,565

STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a microelectronic element having memory storage array function, the microelectronic element having one or more columns of
element contacts each column extending in a first direction along a face of the microelectronic element, such that an axial
plane extending in a direction normal to the face of the microelectronic element intersects the face of the microelectronic
element along a line extending in the first direction and centered relative to the one or more columns of element contacts;

packaging structure including:
a dielectric layer having a surface overlying the face of the microelectronic element and facing away from the face of the
microelectronic element, the surface of the dielectric layer extending from a first edge thereof to a second edge thereof
opposite from the first edge, the first and second edges extending in the first direction, wherein the surface of the dielectric
layer has first and second peripheral regions adjacent to the first and second edges, respectively, and a central region separating
the first and second peripheral regions and

a plurality of terminals exposed at the surface of the dielectric layer, at least some of the terminals being electrically
connected with the element contacts through traces extending along the dielectric layer and metallized vias extending from
the traces and contacting the element contacts, the terminals disposed at positions within a plurality of parallel columns
and being configured for connecting the microelectronic package to at least one component external to the microelectronic
package, the terminals including first terminals disposed within at least one column in the central region and second terminals
exposed at the surface of the dielectric layer in at least one of the peripheral regions, the first terminals being configured
to carry all address information usable by circuitry within the package to determine an addressable memory location from among
all the available addressable memory locations of a memory storage array within the microelectronic element, the second terminals
configured to carry second information, the second information being other than the information carried by the first terminals,
the second information including data signals,

wherein the central region is not wider than three and one-half times a minimum pitch between any two adjacent columns of
the terminals, and the axial plane intersects the central region.

US Pat. No. 9,368,478

MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURE THEREOF

Invensas Corporation, Sa...

14. A microelectronic assembly comprising:
a substrate having an opening extending between first and second oppositely facing surfaces of the substrate, the opening
elongated in a first direction; and

at least one microelectronic element having a front face facing and attached to the first surface of the substrate and a plurality
of contacts at the front face overlying the opening, the microelectronic element having first and second opposite peripheral
edges extending away from the front face,

wherein the first peripheral edge is aligned in the first direction with an inner edge of the opening,
wherein the opening extends beyond the second peripheral edge, and
the microelectronic assembly includes at least one vent extending from the opening beyond the first peripheral edge of the
microelectronic element.

US Pat. No. 9,142,511

STRUCTURES WITH THROUGH VIAS PASSING THROUGH A SUBSTRATE COMPRISING A PLANAR INSULATING LAYER BETWEEN SEMICONDUCTOR LAYERS

Invensas Corporation, Sa...

1. A structure comprising:
a planar insulating layer;
a first semiconductor layer overlying the planar insulating layer, the first semiconductor layer having a planar bottom surface
contacting a top surface of the planar insulating layer;

a second semiconductor layer underlying the planar insulating layer, the second semiconductor layer having a planar top surface
contacting a bottom surface of the planar insulating layer;

one or more through vias each of which passes through the planar insulating layer and the first and second semiconductor layers;
wherein each through via comprises:
a respective first via portion passing through the first semiconductor layer and having a first sidewall portion adjacent
to the planar insulating layer and provided by the first semiconductor layer;

a respective second via portion passing through the second semiconductor layer; and
a respective third via portion passing through the planar insulating layer;
wherein in at least one through via, at least adjacent to the planar insulating layer, the first via portion is wider than
the third via portion.

US Pat. No. 9,111,946

METHOD OF THINNING A WAFER TO PROVIDE A RAISED PERIPHERAL EDGE

Invensas Corporation, Sa...

1. A method of thinning an encapsulated component, comprising:
abrading a first area of a first surface of an encapsulated component to reduce a thickness of the encapsulated component
within the first area, the encapsulated component including:

an undiced semiconductor wafer comprising a plurality of semiconductor chips each being an integral portion of the wafer,
the wafer having a semiconductor region extending continuously within the plurality of semiconductor chips and an active wafer
surface defined by active surfaces of each of the semiconductor chips, the active wafer surface facing away from the first
surface, the wafer having an edge bounding the active wafer surface, wherein the active wafer surface comprises a semiconductor
device region and a peripheral portion extending from the edge of the wafer to the semiconductor device region,

a sacrificial structure overlying the semiconductor device region, and
an encapsulant contacting the peripheral portion of the active wafer surface and extending outwardly in first and second directions
beyond the edge of the wafer,

wherein an entire area of the active wafer surface is aligned with the first area in the first and second directions,
the abrading being performed such that after the abrading, a second area of the encapsulated component beyond the first area
has a thickness greater than the reduced thickness, wherein the second area is configured to fully support the abraded encapsulated
component in a state in which the encapsulated component is manipulated by handling equipment.

US Pat. No. 9,082,753

SEVERING BOND WIRE BY KINKING AND TWISTING

Invensas Corporation, Sa...

1. A method of forming an electrically conductive lead of a component, comprising:
using a bonding tool to bond a wire extending beyond a surface of a bonding tool to a metal surface;
drawing the bonding tool away from the metal surface while allowing the wire to extend farther from the surface of the bonding
tool;

clamping the wire to limit further extension of the wire beyond the surface of the bonding tool;
moving the bonding tool while the wire remains clamped such that the bonding tool imparts a kink to the wire at a location
where the wire is fully separated from any metal element other than the bonding tool; and

twisting the wire and tensioning the wire using the bonding tool such that the wire breaks at the kink to define an end, wherein
the lead comprises the wire extending from the metal surface to the end.

US Pat. No. 9,064,933

METHODS AND STRUCTURE FOR CARRIER-LESS THIN WAFER HANDLING

Invensas Corporation, Sa...

1. A method of forming a microelectronic assembly, comprising:
removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned
portions separated by integral supporting portions of the processed substrate, each of the integral supporting portions having
a width and a first thickness extending along the entire width, wherein the first thickness is greater than a thickness of
the thinned portions, at least some of the thinned portions each including a plurality of electrically conductive interconnects
extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and

removing fully the integral supporting portions of the substrate to sever the substrate into a plurality of individual thinned
portions, each individual thinned portion having a thickness less than the first thickness, at least some individual thinned
portions including the interconnects.

US Pat. No. 9,418,924

STACKED DIE INTEGRATED CIRCUIT

Invensas Corporation, Sa...

1. An apparatus, comprising:
a package substrate having a first plurality of via structures extending from a lower surface of the package substrate to
an upper surface of the package substrate;

a plurality of bond via array wires coupled to the first plurality of via structures at the lower surface of the package substrate;
a die having a second plurality of via structures extending to a lower surface of the die;
wherein the lower surface of the die faces the upper surface of the package substrate in an integrated circuit package;
wherein the package substrate does not include a redistribution layer; and
wherein the die and the package substrate are coupled to one another.

US Pat. No. 9,391,008

RECONSTITUTED WAFER-LEVEL PACKAGE DRAM

Invensas Corporation, Sa...

1. A microelectronic assembly comprising:
a first microelectronic package, wherein the first microelectronic package includes first and second encapsulated microelectronic
elements each including:

a semiconductor die having a front face extending in first and second lateral directions, a plurality of contacts on the front
face, a back face opposite the front face, and an edge surface extending between the front and back faces;

an encapsulant contacting at least the edge surface of the semiconductor die and extending in at least one of the lateral
directions from the edge surface; and

electrically conductive elements extending from the contacts of the semiconductor die and over the front face in at least
one of the lateral directions to locations overlying the encapsulant;

wherein the first and second microelectronic elements are affixed to one another by a bonding layer of dielectric material
which extends between and contacts dielectric material at the confronting surfaces of the first and second microelectronic
elements such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards
and adjacent to one of the front or back surfaces of the other of the first and second semiconductor dies and at least some
conductive elements of at least one of the microelectronic elements are adjacent the bonding layer, the encapsulants of the
first and second microelectronic elements defining first and second oppositely and outwardly facing surfaces, respectively,
remote from the bonding layer; and

a plurality of electrically conductive interconnects, each conductive interconnect extending through an opening having a continuous
interior surface extending from the first outwardly facing surface through the encapsulant of the first microelectronic element,
and through the bonding layer and the encapsulant of the second microelectronic element to the second outwardly facing surface,
wherein at least one of the conductive interconnects is electrically coupled with at least one of the conductive elements
at a location adjacent the bonding layer and thereby electrically connected with at least one semiconductor die of the first
and second microelectronic elements;

a second microelectronic package defining a first surface having terminals exposed thereon, a second surface having package
contacts exposed thereon, the second microelectronic package further including a microelectronic element electrically coupled
with the terminals and the package contacts; and

a plurality of conductive joining elements electrically coupled with confronting ends of the conductive interconnects of the
first microelectronic package and the terminals of the second microelectronic package,

wherein a first conductive interconnect of the conductive interconnects joined with a first conductive joining element of
the conductive joining elements is not electrically connected with either of the first or second microelectronic elements.

US Pat. No. 9,368,477

CO-SUPPORT CIRCUIT PANEL AND MICROELECTRONIC PACKAGES

Invensas Corporation, Sa...

1. A circuit panel having a major surface and a second surface opposite the major surface, the circuit panel comprising:
driving element contacts exposed at the major surface or second surface of the circuit panel, the driving element contacts
configured to connect to terminals exposed at a front surface of a driving element and electrically coupled to a microprocessor
or a direct memory access controller therein;

panel contacts exposed at a connection site of the major surface of the circuit panel and configured to be coupled to terminals
exposed at a front surface of a microelectronic package having one or two microelectronic elements including a memory storage
array, each of the microelectronic elements having address input element contacts electrically connected with the memory storage
array, the connection site defining a peripheral boundary on the major surface surrounding a group of the panel contacts that
is configured to be coupled to a single microelectronic package;

a plurality of conductors together comprising at least one bus, the conductors extending on or within the circuit panel in
one or more directions parallel to the major surface, the driving element contacts electrically coupled with the group of
the panel contacts through the plurality of conductors;

the group of the panel contacts including:
first, second, third, and fourth sets of first contacts, positions of the first set of first contacts being symmetric about
a theoretical plane normal to the major surface with positions of the second set of first contacts, positions of the third
set of first contacts being symmetric about the theoretical plane with positions of the fourth set of first contacts,

wherein each of the sets of first contacts is configured to carry all of the address information used within the microelectronic
package to specify a location within the memory storage array, wherein the conductors are configured to carry all of the address
information transferred between the driving contacts and the panel contacts, and wherein a total number of the address input
element contacts is less than a total number of the first contacts of the circuit panel;

wherein the terminals of the microelectronic package include first terminals configured to be coupled to the first and fourth
sets of first contacts, and no-connect terminals configured to be coupled to the second and third sets of first contacts,
each no-connect terminal being electrically insulated from the memory storage array within the microelectronic package, and

wherein a position of each first terminal on a first side of the theoretical plane is symmetric about the theoretical plane
with a position of a no-connect terminal on a second side of the theoretical plane opposite from the first side, and a position
of each first terminal on the second side is symmetric about the theoretical plane with a position of a no-connect terminal
on the first side.

US Pat. No. 9,433,093

HIGH STRENGTH THROUGH-SUBSTRATE VIAS

Invensas Corporation, Sa...

1. A component, comprising:
a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending
in a direction between the first and second surfaces, each conductive element containing an alloy of a metal material selected
from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of
Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth, wherein the conductive elements are filled
vias, and wherein at least one of the vias includes a concave face exposed at least one of the first and second surfaces of
the support structure and defining a first cavity within a portion of the at least one of the vias that defines a second cavity
with a second bonding metal mass disposed at least partially within the first cavity, wherein the first and second cavities
are laterally offset from one another.

US Pat. No. 9,252,127

MICROELECTRONIC ASSEMBLIES WITH INTEGRATED CIRCUITS AND INTERPOSERS WITH CAVITIES, AND METHODS OF MANUFACTURE

Invensas Corporation, Sa...

1. A method for fabricating a microelectronic assembly, the method comprising:
obtaining a first structure comprising:
a plurality of interposers overlying one another and comprising a first interposer and a second interposer, each of the first
and second interposers comprising a first side facing the other one of the first and second interposers and comprising a second
side opposite to the first side, wherein at least the first interposer comprises one or more first contact pads at its first
side; and

one or more first modules attached to the first interposer between the first and second interposers, at least one first module
comprising a semiconductor integrated circuit and comprising one or more contact pads electrically coupled to the integrated
circuit and to at least one first contact pad; and

wherein at least one of the first and second interposers comprises one or more first cavities, and at least part of each first
module is located in a respective first cavity; and

after obtaining the first structure, forming one or more first conductive vias each of which passes through at least part
of at least one of the first and second interposers to reach at least one respective first cavity and to physically contact,
or be capacitively coupled to, circuitry of at least one respective first module at least partially located in the respective
first cavity.

US Pat. No. 9,236,365

METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES

Invensas Corporation, Sa...

1. A method for forming a 3-D integrated circuit, comprising:
forming on separate substrates at least an active device chip, an isolator chip and an integrated passive device (IPD) chip,
wherein the substrates of at least two of such chips have one or more conductor filled vias extending there through and wherein
at least one of the one or more vias in the IPD chip is coupled to one or more integrated components on the substrate of the
IPD chip;

stacking the active device chip, the isolator chip and the IPD chip so that a first via in a first of the at least two chips
is aligned with a second via in another of the at least two chips, the first and second vias being two of the conductor filled
vias; and

bonding the active device chip, the isolator chip, and the IPD chip together so that the first and second vias are electrically
coupled.

US Pat. No. 9,076,785

METHOD AND STRUCTURES FOR VIA SUBSTRATE REPAIR AND ASSEMBLY

Invensas Corporation, Sa...

1. A component, comprising:
a substrate having a first surface, a second surface opposite from the first surface, and an opening extending between the
first and second surfaces, the opening having an inner wall extending between the first and second surfaces, a dielectric
material being exposed at the inner wall; and

an electrically conductive via, including:
a first portion including a first layer structure extending within the opening and at least partially along the inner wall,
the first layer structure contacting the dielectric material exposed at the inner wall, and a first principal conductor extending
within the opening and at least partially overlying the first layer structure within the opening, the first portion being
exposed at the first surface and having a concave lower surface located between the first and second surfaces, a center of
the concave lower surface being located closer to the first surface of the substrate than a periphery of the concave lower
surface; and

a second portion including a second layer structure extending within the opening and at least partially along the lower surface
of the first portion, the second layer structure contacting the dielectric material exposed at the inner wall and extending
into a concavity defined by the concave lower surface of the first portion, and a second principal conductor extending within
the opening and at least partially overlying the second layer structure within the opening, the second principal conductor
extending from the second layer structure towards the second surface, the second portion being exposed at the second surface.

US Pat. No. 9,601,398

THIN WAFER HANDLING AND KNOWN GOOD DIE TEST METHOD

Invensas Corporation, Sa...

1. A microelectronic assembly, comprising:
a first substrate having a plurality of spaced-apart recesses (“recesses”) therein as extending from a first surface thereof;
a second substrate having a plurality of spaced-apart solid metal pillars (“pillars”) exposed at a first surface thereof,
each pillar of the pillars extending into a corresponding one of the recesses and having a base adjacent the first surface
of the second substrate and an end remote from the base;

a plurality of bumps, each including a bond metal, respectively exposed at ends of the pillars, at least some of the bond
metal of each of the bumps at least partially disposed in corresponding ones of the recesses and solidified therein to engage
with a first portion of surface area of inner surfaces of the recesses for mechanical retention to in addition to electrical
conductivity with the first substrate;

wherein the first portion of the surface area of the inner surfaces of the recesses are wettable by the bond metal of the
plurality of bumps, and a second portion of the surface area of the inner surfaces of the recesses are non-wettable by the
bond metal of the bumps at the melting point of the bond metal;

a non-wettable layer disposed in the recesses corresponding to the second portion of the surface area of the inner surfaces
for being adjacent to the first surface of the first substrate and for separating the first portion of the surface area of
the inner surfaces of the recesses from the first surface of the first substrate to provide a non-wetting surface barrier
with respect to the bond metal after being reflowed for having the bond metal remain adjacent the first portion of the surface
area of the inner surfaces of the recesses after reflow; and

wherein the second portion of the surface area of the inner surfaces of the at least some of the recesses comprises a reentrant
surface prior to the bond metal being reflowed for mechanical retention of the first substrate and the second substrate to
one another after reflow of the bond metal.

US Pat. No. 9,252,122

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

Invensas Corporation, Sa...

1. A structure comprising:
a substrate having a first region and a second region, the substrate also having a first surface and a second surface remote
from the first surface;

electrically conductive elements exposed at the first surface of the substrate within the second region;
wire bonds having bases bonded to respective ones of the conductive elements and free ends remote from the substrate and remote
from the bases, at least one of the wire bonds having a shape such that the at least one wire bond defines an axis between
the free end and the base thereof coincident with a side surface of the at least one wire bond and such that the at least
one wire bond defines a plane, a bent portion of the at least one wire bond extending away from the axis within the plane,
wherein the entire at least one wire bond is positioned on one side of the axis and a substantially straight portion of the
at least one wire bond extends between the free end and the bent portion angled relative to the bent portion,

wherein the ends of the wire bonds are defined on tips of the wire bonds, the wire bonds defining respective first diameters
between the bases and the tips thereof, and the tips having at least one dimension that is smaller than the respective first
diameters of the wire bonds, wherein the tip of at least one wire bond of the wire bonds is tapered relative to a cylindrical
portion of the at least one wire bond and comprises first and second outer surfaces extending directly from an outer surface
of the cylindrical portion, wherein the cylindrical portion is integral with the tip of the at least one wire bond and the
tip of the at least one wire bond has a centroid which is offset in a radial direction from an axis of the cylindrical portion
extending from the base of the at least one wire bond; and

a dielectric encapsulation layer extending from at least one of the first or second surfaces and covering portions of the
wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, the encapsulation
layer overlying at least the second region of the substrate, wherein unencapsulated portions of the wire bonds are defined
by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends;

wherein the conductive elements are configured to couple the wire bonds to one or more microelectronic elements.

US Pat. No. 9,167,710

EMBEDDED PACKAGING WITH PREFORMED VIAS

Invensas Corporation, Sa...

1. A microelectronic assembly, comprising:
a microelectronic element having a front surface, edge surfaces bounding the front surface, and contacts at the front surface,
the microelectronic element having a first thickness extending in a first direction away from the front surface;

substantially rigid metal posts extending in the first direction, the posts disposed between at least one of the edge surfaces
and a corresponding edge of the microelectronic assembly, each metal post having a sidewall separating first and second end
surfaces of such metal post from one another in the first direction, wherein the sidewalls of the metal posts have a root
mean square (rms) surface roughness of less than about 1 micron;

a encapsulation having a second thickness extending in the first direction between first and second surfaces of the encapsulation,
the encapsulation contacting at least the edge surfaces of the microelectronic element and the sidewalls of the metal posts,
wherein the metal posts extend at least partly through the second thickness, and the encapsulation electrically insulates
adjacent metal posts from one another;

the microelectronic assembly having first and second sides adjacent the first and second surfaces of the encapsulation, respectively,
and having terminals at the first side;

an insulation layer overlying the first surface of the encapsulation at the first side and having a thickness extending away
from the first surface of the encapsulation,

connection elements extending away from the first end surfaces of the metal posts and through the thickness of the insulation
layer, the connection elements electrically connecting at least some of the first end surfaces with corresponding terminals,
wherein at least some connection elements have cross sections smaller than cross sections of the metal posts; and

an electrically conductive redistribution structure deposited on the first insulation layer, wherein the redistribution structure
electrically connects the terminals with corresponding first end surfaces of the metal posts through at least some of the
connection elements,

wherein at least some of the metal posts are electrically coupled with the contacts of the microelectronic element.

US Pat. No. 9,377,824

MICROELECTRONIC ASSEMBLY INCLUDING MEMORY PACKAGES CONNECTED TO CIRCUIT PANEL, THE MEMORY PACKAGES HAVING STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS

Invensas Corporation, Sa...

1. A microelectronic assembly, comprising:
a circuit panel having a first surface, a second surface opposite the first surface, and panel contacts exposed at each of
the first and second surfaces; and

first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces,
respectively,

the circuit panel electrically interconnecting at least some terminals of the first microelectronic package with at least
some corresponding terminals of the second microelectronic package, each of the first and second microelectronic packages
including:

a substrate having a first surface, a second surface opposite the first surface, a plurality of substrate contacts exposed
at the first surface, and first and second opposed edges between the first and second opposed surfaces, the first and second
edges extending in a first direction, the second surface having first and second peripheral regions adjacent to the first
and second edges, and a central region separating the first and second peripheral regions;

a microelectronic element having memory storage array function, the microelectronic element having a front face facing away
from the first surface of the substrate, the microelectronic element having one or more columns of element contacts exposed
at the front face;

conductive structure electrically connecting the element contacts with the substrate contacts; and
a plurality of parallel columns of terminals exposed at the second surface and electrically connected with the substrate contacts,
the terminals including first terminals in the central region of the second surface of the substrate, the first terminals
configured to carry address information, and second terminals at the second surface of the substrate in at least one of the
peripheral regions, the second terminals configured to carry second information, the second information being other than the
information carried by the first terminals, the second information including data signals.

US Pat. No. 9,165,906

HIGH PERFORMANCE PACKAGE ON PACKAGE

Invensas Corporation, Sa...

1. A microelectronic assembly, comprising:
a first package comprising a microelectronic element embodying a processor, the first package having processor package terminals
at a face thereof; and

a second package electrically connected to the first package, the second package comprising:
two or more microelectronic elements each having memory storage array function, each having an element face and a plurality
of contacts at the respective element face;

upper and lower opposite package faces each parallel to the element faces, the upper package face defined by a surface of
a dielectric layer overlying the element faces of the two or more microelectronic elements, wherein at least portions of inner
edges of respective microelectronic elements of the two or more microelectronic elements are spaced apart from one another,
so as to define a central region between the inner edges that does not overlie any of the element faces of the microelectronic
elements of the second package;

upper terminals at the upper package face, the upper terminals joined to the processor package terminals and electrically
connected with at least some of the contacts; and

lower terminals at the lower package face and configured for electrically connecting the assembly with a component external
thereto; and

electrically conductive structure aligned with the central region and extending through the second package to electrically
connect the lower terminals with at least one of: the upper terminals or the contacts,

wherein the two or more microelectronic elements comprise first, second, third, and fourth microelectronic elements, and
wherein the microelectronic elements have first, second, third, and fourth axes extending along the inner edge of the respective
first, second, third, and fourth microelectronic elements, the axes together defining a closed outer boundary of the central
region, the first and third axes being parallel to one another, and the second and fourth axes being transverse to the first
and third axes.

US Pat. No. 9,423,824

STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a substrate having first and second opposed surfaces, first and second opposed edges extending between the first and second
surfaces, and first and second apertures extending between the first and second surfaces, the apertures having first and second
parallel axes extending in directions of the lengths of the respective apertures, the second surface having a central region
between the first and second axes and first and second peripheral regions between the central region and the respective first
and second edges;

first and second microelectronic elements each having a surface facing the first surface of the substrate and contacts exposed
at the surface of the respective microelectronic element and aligned with at least one of the apertures, each microelectronic
element having memory storage array function;

terminals exposed at the second surface and configured for connecting the microelectronic package to at least one component
external to the microelectronic package; and

leads electrically connected between the contacts of each microelectronic element and the terminals, each lead having a portion
aligned with at least one of the apertures,

wherein the terminals include first terminals configured to carry address information, the first terminals including a first
set thereof disposed in the first peripheral region and a second set thereof disposed in the second peripheral region, and

wherein the first terminals of the first set are electrically connected with the first microelectronic element and not electrically
connected with the second microelectronic element, and the first terminals of the second set are electrically connected with
the second microelectronic element and not electrically connected with the first microelectronic element.

US Pat. No. 9,398,700

METHOD OF FORMING A RELIABLE MICROELECTRONIC ASSEMBLY

Invensas Corporation, Sa...

1. A method of forming a microelectronic assembly, comprising:
assembling first and second components to have first major surfaces of the first and second components facing one another
and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing
major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality
of first metal connection elements at the first major surface, the second component having a plurality of second metal connection
elements at the first major surface of the second component;

prior to assembling the first and second components, forming the first metal connection elements by a method comprising: forming
at least one of first metal vias extending in the first direction of the first thickness between first and second major surfaces
of the first component, or first metal pads at the first major surface of the first component, forming a first seed layer
overlying the first major surface of the first component and electrically connected to the at least one of the first metal
vias or first metal pads, and plating first plated metal regions above the at least one of first metal vias or first metal
pads, the first plated metal regions extending in the first direction at least above the first major surface of the first
component, the first seed layer electrically connecting each first plated metal region to a corresponding first metal via
or first metal pad;

plating a plurality of metal connector regions each connecting and extending continuously in the first direction between a
respective first surface of the first plated metal region and a corresponding second surface of the second metal connection
element opposite the respective first plated metal region, each metal connector region plated between corresponding exposed
portions of the first and second surfaces; and

removing portions of the first seed layer to electrically separate adjacent first metal connection elements.

US Pat. No. 9,378,985

METHOD OF THINNING A WAFER TO PROVIDE A RAISED PERIPHERAL EDGE

Invensas Corporation, Sa...

1. A method of forming a stacked wafer assembly, comprising:
manipulating at least one of first and second encapsulated components so as to assemble the first and second encapsulated
components to form an assembly in which surfaces of the first and second encapsulated components are juxtaposed with one another,
each of the first and second encapsulated components including an undiced semiconductor wafer comprising a plurality of semiconductor
chips each being an integral portion of the wafer, the wafer having a semiconductor material extending continuously within
the plurality of semiconductor chips and an active wafer surface defined by active surfaces of each of the semiconductor chips,
an encapsulant extending outwardly from the semiconductor chips in directions parallel to the common active surface, a first
area of each encapsulated component encompassing entire areas of the plurality of semiconductor chips of the respective encapsulated
component having a reduced thickness, wherein a second area of each encapsulated component disposed beyond the first area
has a thickness greater than the reduced thickness, the second area fully supporting the encapsulated component during the
manipulating; and

processing the assembly to remove at least the second area of each encapsulated component such that the processed assembly
has a thickness less than the sum of: the thicknesses of the encapsulated components within the respective second areas and
the distance between the juxtaposed surfaces of the encapsulated components.

US Pat. No. 9,355,996

MICROELECTRONIC PACKAGE WITH CONSOLIDATED CHIP STRUCTURES

Invensas Corporation, Sa...

1. A microelectronic package comprising:
(a) a package substrate having upper and lower surfaces and terminals at the lower surface;
(b) first and second chips disposed above the package substrate, each of the first and second chips having a front face, a
rear face and contacts at the front face disposed in one or more columns extending in a column direction, the first and second
chips being offset from one another by a center-to-center offset distance in a lateral direction transverse to the column
direction;

(c) interconnect pads disposed in an elongated interconnect zone having a width less than the offset distance, the interconnect
pads facing toward the package substrate at least some of the interconnect pads being electrically connected to at least some
of the contacts of the first and second chips, at least some of the interconnect pads being electrically connected to at least
some of the terminals of the package substrate

wherein each of the first and second chips has first and second edges extending in the column direction and the front surfaces
of the first and second chips are substantially coplanar with one another, the first edge of the first chip being juxtaposed
with the second edge of the second chip, the interconnect pads being disposed adjacent the juxtaposed first and second edges,

the microelectronic package further comprising redistribution traces extending from the interconnect pads toward the contacts
of the first and second chips, the interconnect pads being electrically connected to the contacts of the first and second
chips through the redistribution traces, and

wherein the package substrate has an aperture therein in alignment with the interconnect pads, the package further comprising
wire bonds extending through the aperture, the interconnect pads being connected to the terminals through the wire bonds.

US Pat. No. 9,241,420

IN-PACKAGE FLY-BY SIGNALING

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a package substrate having first and second oppositely facing surfaces, a plurality of first terminals at the second surface
of the package substrate and configured for connection with a component external to the package, the plurality of first terminals
configured to carry address information; and

first and second microelectronic elements each having a first face confronting the first surface of the substrate, each microelectronic
element including a memory storage array, and each microelectronic element having address inputs for receipt of address information
specifying locations within the memory storage array of the respective microelectronic element,

the package substrate further having a plurality of address lines electrically connected with the plurality of first terminals
and configured to carry address information to a first connection region on the substrate, the first connection region having
a first delay from the plurality of first terminals, the address lines being configured to carry the address information beyond
the first connection region at least to a second connection region on the substrate having a second delay from the plurality
of first terminals, wherein the address inputs of the first microelectronic element are coupled with each of the plurality
of address lines at the first connection region, and the address inputs of the second microelectronic element are coupled
with each of the plurality of address lines at the second connection region, wherein the second delay is greater than the
first delay; and

an encapsulant material overlying second faces of the first and second microelectronic elements that face away from the package
substrate.

US Pat. No. 9,460,758

SINGLE PACKAGE DUAL CHANNEL MEMORY WITH CO-SUPPORT

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a support element having first and second oppositely-facing surfaces and a plurality of substrate contacts at the first surface
or the second surface, the support element having oppositely-facing north and south edges adjacent to oppositely-facing east
and west edges each extending between the north and south edges;

zeroth, first, second, and third stacked microelectronic elements electrically coupled with the substrate contacts, each microelectronic
element having a memory storage array having one or more available addressable memory locations; and

terminals at the second surface electrically coupled with the microelectronic elements via the substrate contacts and arranged
at locations within a plurality of north and south rows of terminals extending parallel to and adjacent to the north and south
edges, respectively, and at locations within a plurality of east and west columns of terminals extending parallel to and adjacent
to the east and west edges, respectively,

the terminals including first terminals configured to carry first address information usable by a circuitry within the microelectronic
package to determine an addressable memory location from among all the available addressable memory locations of the memory
storage arrays of the microelectronic elements, and second terminals configured to carry second information other than the
first address information carried by the first terminals, the second information including data signals,

wherein a zeroth subset of the first and second terminals are electrically coupled to the zeroth and second microelectronic
elements, the first terminals of the zeroth subset being arranged within a first one of the north and south rows of terminals
and the second terminals of the zeroth subset being arranged within a second one of the north and south rows of terminals,
and

wherein a first subset of the first and second terminals are electrically coupled to the first and third microelectronic elements,
the first terminals of the first subset being arranged within a first one of the east and west columns of terminals and the
second terminals of the first subset being arranged within a second one of the east and west columns of terminals.

US Pat. No. 9,230,814

NON-VOLATILE MEMORY DEVICES HAVING VERTICAL DRAIN TO GATE CAPACITIVE COUPLING

INVENSAS CORPORATION, Sa...

1. A two terminal programmable non-volatile device, comprising:
a floating gate disposed vertically about a substrate in a vertical direction, wherein said floating gate comprises a first
side oriented in said vertical direction, a second side opposite to said first side and oriented in said vertical direction,
and a bottom portion oriented approximately perpendicular to said vertical direction;

a source region coupled to a first terminal and formed adjacent to said first side of said floating gate;
a drain region coupled to a second terminal and formed adjacent to said second side of said floating gate and opposite to
said source region; and

a channel coupling said source region and drain region;
wherein said floating gate is laterally disposed between said source region and said drain region;
wherein said drain region is capacitively coupled to said floating gate and wherein said drain region overlaps a sufficient
portion of said floating gate such that a programming voltage for said device applied to said second terminal of said drain
region can be imparted to said floating gate through capacitive coupling.

US Pat. No. 9,299,572

THERMAL VIAS DISPOSED IN A SUBSTRATE WITHOUT A LINER LAYER

Invensas Corporation, Sa...

1. An apparatus, comprising:
a substrate having formed therein a plurality of vias;
a liner layer located on the substrate including being located in a subset of the plurality of vias;
wherein at least one of the plurality of vias does not have the liner layer located therein;
a thermally conductive material disposed in the at least one of the plurality of vias without a liner layer to provide a thermal
via structure for conducting heat from one die to another die to conduct to a heat sink; and

a conductive material different than the thermally conductive material disposed in the subset of the plurality of vias having
the liner layer.

US Pat. No. 9,281,271

STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS HAVING MODULO-X SYMMETRY IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE

Invensas Corporation, Sa...

1. A microelectronic: package, comprising:
a microelectronic element having a face and a plurality of element contacts thereon, the microelectronic element embodying
a greater number of active devices to provide memory storage array function than any other function;

a substrate having first and second opposed surfaces, the substrate having a set of substrate contacts on the first surface
facing the element contacts of the microelectronic element and joined to the element contacts; and

a plurality of terminals at the second surface configured for connecting the microelectronic package with at least one component
external to the package, the terminals electrically coupled with the substrate contacts and including first and second groups
of data terminals, each of the first and second groups having at least eight data terminals disposed on first and second opposite
sides of an axis, respectively,

wherein each of the data terminals of the first and second groups are configured to carry data signals for read and write
access to random access addressable memory locations of a memory storage array within the microelectronic element, and the
data terminals of the first group have modulo-X symmetry about the axis with the second group of the data terminals, wherein
X is an integer.

US Pat. No. 9,059,181

WAFER LEVELED CHIP PACKAGING STRUCTURE AND METHOD THEREOF

Invensas Corporation, Sa...

1. A wafer-leveled chip package structure, comprising:
a wafer having a first surface, on which an integrated circuit pattern and a plurality of pads are formed, and a plurality
of through holes penetrating said wafer;

a plurality of first chips each having at least one pad on said first surface of said wafer, wherein said pads being mounted
on the surface of said first chips which are opposed to said wafer;

a first insulating layer formed on said first surface of said wafer, having a plurality of first conductive vias penetrating
said first insulating layer, wherein said first insulating layer covers said first chips and said integrated circuit pattern
of said wafer;

a conductive pattern layer formed on a surface opposed to said wafer of said first insulating layer, and said conductive pattern
layer is electrically connected with said first conductive vias;

wherein a second insulating layer is filled in said through holes and at least one second conducting via passes through said
second insulating layer, parts of said first conductive vias are connected with said pads of said wafer, parts of said first
conductive vias are connected with said pads of said first chips and part of said first conductive vias are connected with
said second conductive vias in said through holes;

a third insulating layer having a pattern formed on a surface of said first conductive pattern layer which is opposed to said
first insulating layer, wherein said third insulating layer protects said first conductive pattern layer; and

a plurality of second chips each having at least one pad on said third insulating layer, wherein said pad is disposed on the
surface of said second chips which is opposed to said third insulating layer.

US Pat. No. 9,397,041

MICROELECTRONIC ASSEMBLIES FORMED USING METAL SILICIDE, AND METHODS OF FABRICATION

Invensas Corporation, Sa...

1. A fabrication method comprising:
providing a first structure comprising circuitry comprising one or more contact pads each of which comprises metal;
providing a substrate comprising a first side comprising one or more silicon regions, the substrate also comprising a second
side opposite to the first side;

attaching the first structure to the substrate so that at least a portion of the metal of each contact pad reacts with at
least a portion of the silicon of a corresponding silicon region to form metal silicide;

forming one or more holes in the second side of the substrate, each hole reaching the metal silicide formed by reacting at
least a portion of the metal of the corresponding contact pad; and

forming a conductive via in each hole, the conductive via reaching at least one of the metal of the corresponding contact
pad and the corresponding metal silicide, the conductive via extending to the substrate's surface at the second side of the
substrate.

US Pat. No. 9,337,170

CONTACT ARRANGEMENTS FOR STACKABLE MICROELECTRONIC PACKAGE STRUCTURES

Invensas Corporation, Sa...

1. A microelectronic assembly, comprising:
a first substrate having a first and a second surface on opposite sides of the first substrate; and
a plurality of contact arrangements disposed on the first surface of the first substrate;
wherein the plurality of contact arrangements comprises:
first contacts disposed as a first ring array of the plurality of contact arrangements on the first surface;
second contacts disposed interior to the first contacts as a second ring array of the plurality of contact arrangements on
the first surface;

third contacts disposed interior to the second contacts as a third ring array of the plurality of contact arrangements on
the first surface;

fourth contacts disposed interior to the third contacts on the first surface as an innermost array of the plurality of contact
arrangements on the first surface;

wherein the first ring array, the second ring array, and the third ring array are concentric rings with the innermost array
in a first central region of the concentric rings;

wherein the first contacts and the fourth contacts are for interconnection with first microelectronic dies; and
wherein the second contacts and the third contacts are for interconnection with second microelectronic dies.

US Pat. No. 9,461,196

NON-CRYSTALLINE INORGANIC LIGHT EMITTING DIODE

Invensas Corporation, Sa...

1. An article of manufacture comprising:
a light emitting diode comprising:
a non-crystalline inorganic light emission layer; and
first and second semiconducting non-crystalline inorganic charge transport layers surrounding said light emission layer, wherein
said first and second semiconducting charge transport layers are doped to opposite conduction types.

US Pat. No. 9,425,167

STACKABLE MICROELECTRONIC PACKAGE STRUCTURES

Invensas Corporation, Sa...

1. A microelectronic assembly, comprising:
a first microelectronic package and a second microelectronic package overlying the first microelectronic package, each of
the first and second microelectronic packages including:

a substrate having first and second opposed surfaces, apertures extending between the first and second opposed surfaces, substrate
contacts disposed at the first surface, and an interconnect area disposed at the first surface;

first and second microelectronic elements each having element contacts facing the apertures and electrically connected with
corresponding substrate contacts disposed at the first surface, the first and second microelectronic elements being spaced
apart from one another by the interconnect area;

a dielectric layer overlying the first and second microelectronic elements and the interconnect area;
a plurality of package terminals at the second surface electrically interconnected with the substrate contacts for connecting
the package with a component external to the package;

a plurality of stack terminals disposed at the first surface and positioned within the interconnect area electrically connected
with the package terminals;

wherein conductive interconnects extend through the dielectric layer disposed within the interconnect area, the conductive
interconnects being joined to the stack terminals of the first microelectronic package and the stack terminals of the second
microelectronic package.

US Pat. No. 9,323,010

STRUCTURES FORMED USING MONOCRYSTALLINE SILICON AND/OR OTHER MATERIALS FOR OPTICAL AND OTHER APPLICATIONS

Invensas Corporation, Sa...

1. A method for fabricating an interposer for interfacing a plurality of waveguides to one or more transducers, the method
comprising:
forming a first cavity in a top surface of a substrate;
forming a first layer over the first cavity's bottom surface, with one or more gaps in the first layer's top surface;
forming a second layer in the one or more gaps, the second layer overlapping the first layer; and
removing at least part of the first layer to form a plurality of channels separated from each other by portions of the second
layer that are located in the one or more gaps, the second layer portions in the one or more gaps providing one or more spacers
in the first cavity, the one or more spacers at least partially covering the channels, wherein the plurality of channels are
for supporting the waveguides for transmitting electromagnetic waves, wherein the waveguides are to be coupled to the one
or more transducers;

wherein removing at least part of the first layer comprises removing at least part of the first layer from under the second
layer;

wherein the method further comprises:
forming one or more conductive paths passing through the substrate outside the cavity, each conductive path passing between
the top surface of the substrate and a bottom surface of the substrate;

attaching the one or more transducers above the substrate, each transducer extending over at least one said channel for being
optically coupled to at least one waveguide in the channel, each transducer being electrically coupled to at least one said
conductive path;

attaching a controller below the substrate, the controller being electrically coupled to each transducer by electrical circuitry
comprising at least one said conductive path.

US Pat. No. 9,196,588

EMI SHIELD

Invensas Corporation, Sa...

1. A method of forming a shielded component, comprising: forming an electrically conductive shield including an open pattern
of an electrically conductive material by depositing and curing a curable composition comprising electrically conductive particles
and a carrier material on first portions of a surface of a component and on at least one sidewall extending away from the
surface, such that at least second portions of the surface are free from the deposited composition, wherein the pattern of
the electrically conductive material includes a plurality of first lines of the electrically conductive material extending
in a first direction, and a plurality of second lines of the electrically conductive material extending in a second direction
transverse to the first direction such that at least some of the second lines cross at least some of the first lines and the
first and second lines surround open areas above at least some of the second portions.

US Pat. No. 9,349,614

DEVICE AND METHOD FOR LOCALIZED UNDERFILL

Invensas Corporation, Sa...

1. A semiconductor package, the package comprising:
a substrate comprising a plurality of contacts and a plurality of cavities separated by a plurality of mesas, each of the
contacts being located in a respective one of the cavities;

a plurality of dies mounted to the substrate using the plurality of contacts;
a plurality of channels interconnecting the cavities; and
an underfill material between the substrate and the dies;
wherein the underfill material is localized into a plurality of regions using the mesas.

US Pat. No. 9,349,669

REDUCED STRESS TSV AND INTERPOSER STRUCTURES

Invensas Corporation, Sa...

1. A method for making a microelectronic component, the method comprising:
providing a substrate comprising an opening in a top surface, the substrate forming part of the microelectronic component;
and

forming a conductive via in the opening, the conductive via forming at least part of circuitry of the microelectronic component;
wherein the opening comprises a first sidewall of a first material, and the conductive via comprises a second sidewall of
a second material;

wherein at least at one side of the opening, the first and second sidewalls are spaced from each other at the top surface
of the substrate but the first and second sidewalls meet below the top surface of the substrate at a meeting location, and
between the meeting location and the top surface of the substrate the first and second sidewalls are separated by a third
material which is a dielectric different from the first material.

US Pat. No. 9,293,641

INVERTED OPTICAL DEVICE

Invensas Corporation, Sa...

1. A method comprising:
attaching a plurality of piggyback substrates to a carrier wafer using a plurality of bond layers, wherein said plurality
of piggyback substrates are dissimilar in composition to said carrier wafer;

processing said plurality of piggyback substrates, while attached to said carrier wafer, to produce a plurality of light emitting
diodes;

attaching a flip wafer to said plurality of light emitting diodes, away from said carrier wafer; and
removing only said carrier wafer and plurality of bond layers.

US Pat. No. 9,214,455

STUB MINIMIZATION WITH TERMINAL GRIDS OFFSET FROM CENTER OF PACKAGE

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a substrate having a first surface and a second surface opposite one another with an aperture extending from the first surface
to the second surface, the aperture having an axis extending in a direction of a longest dimension of the aperture, the second
surface having a region disposed between the axis and an edge of the substrate;

a microelectronic element having a front surface facing the first surface of the substrate and a plurality of contacts associated
with the front surface of the microelectronic element aligned with the aperture;

a plurality of terminals associated with the second surface of the substrate for connecting the microelectronic package to
at least one component external to the microelectronic package;

leads passing through the aperture coupling the plurality of contacts of the microelectronic element and the plurality of
terminals of the substrate; and

wherein a portion of the plurality of terminals are in the region of the second surface of the substrate for carrying all
address signals for the microelectronic element provided to the microelectronic package.

US Pat. No. 9,484,325

INTERCONNECTIONS FOR A SUBSTRATE ASSOCIATED WITH A BACKSIDE REVEAL

Invensas Corporation, Sa...

1. An apparatus, comprising:
a post extending from a substrate;
the post including a conductor member and at least one liner layer;
an upper portion of each of the conductor member and the at least one liner layer extending above an upper surface of the
substrate;

an exterior surface of the at least one liner layer of the post associated with the upper portion being in contact with a
dielectric layer;

the dielectric layer being disposed on the upper surface of the substrate and adjacent to the at least one liner layer to
provide a dielectric collar for the post;

an exterior surface of the dielectric collar being in contact with a conductor layer;
the conductor layer being disposed adjacent to the dielectric collar to provide a metal collar for the post; and
a top surface of each of the conductor member, the at least one liner layer, the dielectric collar and the metal collar being
generally co-planar and providing a generally planar surface with a bond structure formed thereon for interconnection of the
metal collar and the conductor member, and the metal collar not being in direct contact with the at least one liner layer
and not being in direct contact with the conductor member of the post.

US Pat. No. 9,412,806

MAKING MULTILAYER 3D CAPACITORS USING ARRAYS OF UPSTANDING RODS OR RIDGES

Invensas Corporation, Sa...

8. A method for making a capacitor, the method comprising:
providing a substrate having a surface;
depositing a first electroconductive layer on the surface;
bonding an end of at least one upstanding wire to the first electroconductive layer;
coating the first electroconductive layer and the at least one wire with a dielectric layer; and
depositing a second electroconductive layer on the dielectric layer;
wherein the at least one wire comprises gold (Au), copper (Cu) or aluminum (Al); and
wherein the at least one wire is plated with palladium (Pd).

US Pat. No. 9,349,707

CONTACT ARRANGEMENTS FOR STACKABLE MICROELECTRONIC PACKAGE STRUCTURES WITH MULTIPLE RANKS

Invensas Corporation, Sa...

1. A microelectronic assembly, comprising:
a first substrate having a first and a second surface on opposite sides of the first substrate; and
a plurality of contact arrangements disposed on the first surface of the first substrate;
wherein the plurality of contact arrangements comprises:
first contacts disposed as a ring to provide a first array of the plurality of contact arrangements on the first surface;
second contacts disposed interior to the ring of the first contacts to provide a second array of the plurality of contact
arrangements on the first surface;

wherein the first contacts and the second contacts are for interconnection with first microelectronic dies and second microelectronic
dies;

wherein the second microelectronic dies are disposed below the first microelectronic dies in same a package as the first microelectronic
dies; and

wherein the first microelectronic dies and the second microelectronic dies include at least two ranks thereof for commonly
sharing the first contacts and the second contacts among the first microelectronic dies and the second microelectronic dies.

US Pat. No. 9,305,862

SUPPORT MOUNTED ELECTRICALLY INTERCONNECTED DIE ASSEMBLY

Invensas Corporation, Sa...

1. A device comprising
a support having electrical connection sites at a surface thereof, and
a stacked die assembly mounted onto the surface and electrically connected to one or more of the connection sites,
wherein each die in the stacked die assembly has peripheral interconnect terminals
each interconnect terminal electrically coupled with a die pad of a die of the stacked die assembly at an active side of the
die and

each interconnect terminal is disposed at or overlying the active side of the die to which the interconnect terminal is coupled,
wherein a plurality of die in the stack are electrically interconnected by a same line or a same trace of an electrically
conductive polymer or an electrically conductive ink, and

wherein the line or the trace of the electrically conductive polymer or the electrically conductive ink contacts the peripheral
interconnect terminals on each of the respective electrically interconnected plurality of die,

wherein the active side of at least a first die in the stack faces in a first direction, and the active side of at least a
second die faces in a second direction, opposite the first direction.

US Pat. No. 9,224,739

METHOD OF MAKING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING

Invensas Corporation, Sa...

1. A method of forming a multi-level one-time programmable (MOTP) memory cell incorporated on a silicon substrate with one
or more other additional logic and/or non-MOTP memory devices, characterized in that:
a. said MOTP memory cell has a drain region comprising first and second separate drains, each capacitively coupled to a floating
gate, first and second channel regions respectively for coupling the first drain region and the at least one separate second
drain region to a same source region, wherein the first and second channel regions are for conducting current between the
same source region and respectively the first drain region and the at least one separate second drain region;

b. any and all regions and structures of said MOTP memory cell are formed in common with corresponding regions and structures
used as components of the additional logic and/or non-MOTP memory devices; and

c. an amount of capacitive coupling between said floating gate and said drain region can be varied during a program operation
by applying first and second different voltages to said first and second drains, respectively, to store multiple bits of data
within a single MOTP memory cell.

US Pat. No. 9,076,594

CAPACITORS USING POROUS ALUMINA STRUCTURES

Invensas Corporation, Sa...

1. A capacitor, comprising:
a structure having first and second oppositely facing surfaces and a plurality of pores each extending in a first direction
from the first surface towards the second surface, and each having pore having insulating material extending along a wall
of the pore,

a first conductive portion comprising an electrically conductive material extending within at least some of the pores; and
a second conductive portion comprising a region of the structure consisting essentially of aluminum surrounding individual
pores of the plurality of pores, the second conductive portion electrically isolated from the first conductive portion by
the insulating material extending along the walls of the pores.

US Pat. No. 9,070,849

PARALLEL PLATE SLOT EMISSION ARRAY

Invensas Corporation, Sa...

13. A method comprising:
forming a light emitting diode structure on a substrate;
etching portions of said a light emitting diode structure to form a plurality of individual light emitting diode devices;
forming a first contact layer on the top of said plurality of individual light emitting diode devices;
forming a second contact layer on a flat substrate;
attaching said second contact layer to said first contact layer;
removing said substrate from said plurality of individual light emitting diode devices;
forming a third contact layer opposite said first contact layer on said plurality of individual light emitting diode devices;
patterning first photoresist onto said third contact;
patterning second photoresist in regions between said plurality of individual light emitting diode devices; and
filling regions between said plurality of individual light emitting diode devices and said second photoresist with a transparent
dielectric material.

US Pat. No. 9,293,386

INTERPOSERS WITH CIRCUIT MODULES ENCAPSULATED BY MOLDABLE MATERIAL IN A CAVITY, AND METHODS OF FABRICATION

Invensas Corporation, Sa...

1. A circuit assembly comprising a plurality of levels “Li” where Li varies from L0 through Ln, i being an integer varying from 0 to n, wherein n is an integer greater than one, the circuit assembly comprising
a substrate whose top side comprises a cavity comprising a bottom wall;
wherein the level L0 comprises:

the bottom wall;
a plurality of through-holes each of which passes through the bottom wall;
a plurality of conductors (“L0 conductors”) in respective through-holes;

wherein at least part of level L1 overlies at least part of level L0, and wherein level L1 comprises one or more circuit modules each of which has one or more contact pads each of which is electrically connected
to one or more L0 conductors;

wherein for each level Li other than L0 and L1:

at least part of level Li overlies at least part of level Li-1;

each level Li comprises one or more circuit modules each of which has one or more contact pads each of which is electrically
connected to one or more L0 conductors by one or more first electrically conductive paths lying in the cavity, each first electrically conductive path
passing through each level L1 through Li-1;

wherein at least one first electrically conductive path passes through more than one of the levels L1 through Ln-1.

US Pat. No. 9,615,456

MICROELECTRONIC ASSEMBLY FOR MICROELECTRONIC PACKAGING WITH BOND ELEMENTS TO ENCAPSULATION SURFACE

Invensas Corporation, Sa...

1. A microelectronic assembly comprising:
a substrate having first and second oppositely facing surfaces and a plurality of electrically conductive elements at the
first surface;

bond elements comprising wire bonds, the wire bonds having bases joined to respective ones of the conductive elements at a
first portion of the first surface and end surfaces remote from the substrate and the bases, each of the bond elements extending
from the base to the end surface thereof;

a first microelectronic element having a surface overlying the second surface and aligned in first and second directions parallel
to the second surface with at least some of the bases of the bond elements; and

an encapsulation element overlying the first portion of the first surface of the substrate and filling spaces between the
bond elements such that the bond elements are separated from one another by the encapsulation element, the encapsulation element
having a third surface facing away from the first surface of the substrate and having an edge surface extending from the third
surface towards the first surface, wherein unencapsulated portions of the bond elements are defined by at least portions of
the bond elements that are uncovered by the encapsulation element at the third surface,

wherein the encapsulation element at least partially defines a second portion of the first surface, the second portion being
other than the first portion of the first surface and having an area sized to accommodate an entire area of at least one second
microelectronic element, wherein at least some of the conductive elements at the first surface are at the second portion and
configured for connection with the at least one second microelectronic element.

US Pat. No. 9,508,638

MAKING ELECTRICAL COMPONENTS IN HANDLE WAFERS OF INTEGRATED CIRCUIT PACKAGES

Invensas Corporation, Sa...

1. An integrated circuit package comprising a first substrate and a second substrate bonded to the first substrate, with a
plurality of cavities enclosed by the first and second substrates, the plurality of cavities comprising one or more first
cavities and one or more second cavities;
wherein the second substrate comprises circuitry with first electroconductive pads in the first and second cavities, each
of the first and second cavities having at least one first electroconductive pad therein; and

wherein the integrated circuit package further comprises:
in each first cavity, at least one semiconductor die comprising an integrated circuit electroconductively coupled to at least
one first electroconductive pad in the first cavity; and

in each second cavity, at least one discrete electrical component electroconductively coupled to at least one first electroconductive
pad in the second cavity and comprising a conductive layer such that at least one of the following is true:

(i) the conductive layer is formed over a surface of the first substrate in the second cavity;
(ii) the conductive layer comprises at least a part of the surface of the first substrate in the second cavity.

US Pat. No. 9,502,347

MICROELECTRONIC ASSEMBLIES FORMED USING METAL SILICIDE, AND METHODS OF FABRICATION

Invensas Corporation, Sa...

1. A fabrication method comprising:
providing a first structure comprising circuitry comprising one or more contact pads each of which comprises metal;
providing a substrate comprising a first side comprising one or more silicon regions, the substrate also comprising a second
side opposite to the first side;

attaching the first structure to the substrate so that at least a portion of the metal of each contact pad reacts with at
least a portion of the silicon of a corresponding silicon region to form metal silicide;

forming one or more holes in the second side of the substrate, each hole reaching the metal silicide formed by reacting at
least a portion of the metal of the corresponding contact pad; and

forming a conductive via in each hole, the conductive via reaching at least one of the metal of the corresponding contact
pad and the corresponding metal silicide, the conductive via extending to the substrate's surface at the second side of the
substrate.

US Pat. No. 9,490,222

WIRE BOND WIRES FOR INTERFERENCE SHIELDING

Invensas Corporation, Sa...

1. An apparatus for a microelectronic package having protection from interference, comprising:
a substrate having an upper surface and a lower surface opposite the upper surface and having a ground plane;
a first microelectronic device coupled to the upper surface of the substrate;
wire bond wires coupled to the ground plane for conducting the interference thereto and extending away from the upper surface
of the substrate;

a first portion of the wire bond wires positioned to provide a shielding region for the first microelectronic device with
respect to the interference;

a second portion of the wire bond wires not positioned to provide the shielding region;
a second microelectronic device coupled to the substrate and located outside of the shielding region; and
a conductive surface over the first portion of the wire bond wires for covering the shielding region.

US Pat. No. 9,412,714

WIRE BOND SUPPORT STRUCTURE AND MICROELECTRONIC PACKAGE INCLUDING WIRE BONDS THEREFROM

Invensas Corporation, Sa...

1. A microelectronic package comprising:
a substrate having a first surface and a second surface remote from the first surface;
at least one microelectronic element overlying a portion of the first surface, thereby defining a first region thereof, wherein
a second region of the first surface is defined by another portion of the first surface disposed beyond the at least one microelectronic
element;

electrically conductive elements at the first surface of the substrate within the second region;
a support structure having a third surface and a fourth surface remote from the third surface, the support structure overlying
the second region of the first surface and not overlying the first region of the first surface, wherein the third surface
faces the first surface, the support structure having second and third electrically conductive elements exposed respectively
at the third and fourth surfaces, the second electrically conductive elements being electrically connected to the conductive
elements at the first surface of the substrate in the first region; and

wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to
respective ones of the second conductive elements and ends remote from the support structure and the bases,

an integral continuous encapsulation region contacting the support structure, the substrate and at least edge surfaces of
the wire bonds.

US Pat. No. 9,349,706

METHOD FOR PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE

Invensas Corporation, Sa...

1. A method of making a microelectronic assembly, comprising:
a) bonding a metal wire to a conductive element exposed at a first surface of a substrate, thereby forming a base of a wire
bond on the conductive element;

b) extending a length of the metal wire through a capillary of a bonding tool;
c) cutting the metal wire within the capillary at a location between a clamped portion of the metal wire within the bonding
tool and the base to at least partially define an end surface of the wire bond at a predetermined distance from the base of
the wire bond;

d) forming an end portion at the end surface having a cross-section wider than a cross-section of the wire bond; and
e) forming a dielectric encapsulation layer overlying the first surface of the substrate and defining a major surface spaced
apart from the first surface, wherein the encapsulation layer is formed so as to at least partially cover the first surface
of the substrate and a portion of the wire bond, such that an unencapsulated portion of the wire bond is defined by a portion
of the end portion,

wherein the wire bond has a first edge surface defined between the base and the end portion, the end portion has a second
edge surface that extends outward from the first edge surface of the wire bond below the major surface of the dielectric encapsulation
layer, and the dielectric encapsulation layer surrounds the second edge surface.

US Pat. No. 9,237,648

CARRIER-LESS SILICON INTERPOSER

Invensas Corporation, Sa...

1. A component, comprising:
a plurality of conductive elements at a first side of the component configured for connection with a plurality of corresponding
contacts of a microelectronic element;

a plurality of terminals at a second side of the component opposite the first side, the terminals configured for connection
with a plurality of corresponding contacts of a second component external to the component;

a first element having a coefficient of thermal expansion of less than 10 ppm/° C., the first element having a first surface
coincident with or adjacent to the first side of the component and a second surface opposite the first surface;

an insulating second element coupled to the second surface of the first element, the second element having a surface coincident
with or adjacent to the second side of the component and a plurality of openings extending from the surface towards the second
surface of the first element, the second element including insulating structure formed of at least one second material different
from a first material of which the first element is formed; and

a conductive structure extending through the openings in the second element and through the first element, the conductive
structure electrically connecting the plurality of terminals with the conductive elements, wherein the conductive structure
includes a conductive material extending within the opening and a metalized via extending within the first element in a first
direction of a thickness of the first element in contact with the conductive material.

US Pat. No. 9,214,454

BATCH PROCESS FABRICATION OF PACKAGE-ON-PACKAGE MICROELECTRONIC ASSEMBLIES

Invensas Corporation, Sa...

1. A microelectronic assembly, comprising:
first and second support elements each having a first surface facing in an outwardly direction of the assembly and each having
a second surface facing in an inwardly direction of the assembly towards the second surface of the other of the first and
second support elements respectively, and including at least one of: first terminals at the first surface of the first support
element, or second terminals at the first surface of the second support element;

electrically conductive first elements at the second surface of the first support element;
a patterned layer of photo-imageable material overlying the second surface of the first support element and having openings
aligned with the electrically conductive first elements, each opening having a cross-sectional dimension which is constant
or increasing with a height from the second surface of the first support element;

electrically conductive masses of bonding material electrically coupled with and projecting above the electrically conductive
first elements through the corresponding openings of the patterned layer, each mass having a cross-sectional dimension which
is defined by a cross-sectional dimension of the corresponding opening through which it projects;

a microelectronic element mounted to the second surface of one of the first or the second support elements;
electrically conductive second elements at the second surface of the second support element, the electrically conductive second
elements electrically coupled with the masses and electrically coupled with the first elements through the masses; and

an encapsulation overlying the second surface of the second support element, a surface of the patterned layer and contacting
at least some of the masses, the masses extending through at least a portion of the encapsulation.

US Pat. No. 9,583,671

QUANTUM EFFICIENCY OF MULTIPLE QUANTUM WELLS

Invensas Corporation, Sa...

1. A method comprising:
forming a stack of layers for a multiple quantum well semiconductor device on a substrate, said stack of layers comprising:
a p type layer;

an electron blocking layer in contact with said p type layer;
a plurality of quantum well periods in contact with said electron blocking layer, each of said quantum well periods comprising
a quantum well layer and a barrier layer that comprises a barrier layer p type doping concentration, and wherein said plurality
of quantum well periods comprise barrier layers of varying p type doping concentration;

an n-type layer in contact with said plurality of quantum well periods; and
etching said stack of layers such that said plurality of quantum well periods comprise said quantum well layers of varying
area.

US Pat. No. 9,583,417

VIA STRUCTURE FOR SIGNAL EQUALIZATION

Invensas Corporation, Sa...

1. An apparatus, comprising:
a substrate having a first surface and a second surface opposite the first surface, the first surface and second surface defining
a thickness of the substrate;

a via structure extending from the first surface of the substrate to the second surface of the substrate;
wherein the via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate
to the second surface provided by a conductive member of the via structure extending from the first terminal to the second
terminal;

wherein a barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate;
wherein the barrier layer includes a metal and a dielectric material for having a conductivity configured to offset a capacitance
between the conductive member and the substrate when a signal is passed through the via structure; and

wherein the barrier layer has a film resistivity equal to or less than approximately 0.5 Ohm-cm to provide a resistance in
parallel to the capacitance.

US Pat. No. 9,559,061

SUBSTRATE-TO-CARRIER ADHESION WITHOUT MECHANICAL ADHESION BETWEEN ABUTTING SURFACES THEREOF

Invensas Corporation, Sa...

1. An apparatus, comprising:
a substrate;
a support platform;
wherein a bottom surface of the substrate abuts a top surface of the support platform without adhesive therebetween;
a material disposed around the substrate and on the top surface of the support platform;
wherein the material is in contact with a side surface of the substrate to completely seal an interface as between the bottom
surface of the substrate and the top surface of the support platform to retain abutment of the top surface and the bottom
surface.

US Pat. No. 9,508,691

FLIPPED DIE STACKS WITH MULTIPLE ROWS OF LEADFRAME INTERCONNECTS

Invensas Corporation, Sa...

1. A stacked microelectronic assembly, comprising:
a plurality of stacked encapsulated microelectronic packages, each encapsulated microelectronic package comprising:
a microelectronic element having a front surface defining a plane, a plurality of edge surfaces extending away from the plane
of the front surface, the microelectronic element having a plurality of chip contacts at the front surface;

each package having a plurality of remote surfaces, and an encapsulation region contacting at least one edge surface of the
microelectronic element and extending away from the at least one edge surface to a corresponding one of the remote surfaces,
the encapsulation region having first and second oppositely-facing major surfaces, each major surface substantially parallel
to the plane of the microelectronic element; and

a plurality of first electrically conductive package contacts disposed within a first plane parallel to the first major surface
and a plurality of second electrically conductive package contacts disposed within a second plane parallel to the first plane
and displaced from the first package contacts, the first package contacts and the second package contacts being disposed at
a single one of the remote surfaces, the chip contacts electrically coupled with the package contacts,

the plurality of microelectronic packages stacked one above another in the stacked assembly such that the planes of the microelectronic
elements in each of the plurality of microelectronic packages are parallel with one another.

US Pat. No. 9,502,372

WAFER-LEVEL PACKAGING USING WIRE BOND WIRES IN PLACE OF A REDISTRIBUTION LAYER

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a microelectronic die having a first surface, a second surface opposite the first surface, and a sidewall surface between
the first and second surfaces;

a plurality of wire bond wires with proximal ends thereof coupled to either the first surface or the second surface of the
microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the
second surface, respectively, of the microelectronic die;

a portion of the plurality of wire bond wires extending outside a perimeter of the microelectronic die into a fan-out (“FO”)
region; and

a molding material for covering the first surface, the sidewall surface, and portions of the plurality of the wire bond wires
from the first surface of the microelectronic die to an outer surface of the molding material;

wherein the plurality of wire bond wires include both first directed wire bond wires extending to the FO region and second
directed wire bond wires extending to a fan-in (“FI”) region.

US Pat. No. 9,455,237

BOWL-SHAPED SOLDER STRUCTURE

Invensas Corporation, Sa...

1. A method, comprising:
obtaining a substrate having a first metal layer and a second metal layer;
wherein the second metal layer is disposed on the first metal layer;
forming a first mask on an upper surface of the second metal layer;
etching an opening in the second metal layer responsive to an opening in the first mask;
first plating of a lower surface and a sidewall surface in the opening in the second metal layer with a first metal;
second plating a second metal on the first metal;
removing the first mask;
forming a second mask in the opening and on a portion of the upper surface of the second metal layer surrounding the opening;
and

etching the second metal layer responsive to an opening in the second mask down to an etch stop layer to provide a bowl-shaped
structure.

US Pat. No. 9,443,837

Z-CONNECTION FOR A MICROELECTRONIC PACKAGE USING ELECTROLESS PLATING

Invensas Corporation, Sa...

1. A method of forming a substrate assembly, comprising:
assembling a first element and a substrate using an adhesive layer,
wherein the substrate consists essentially of dielectric material, has a first surface, a second surface opposite the first
surface, a substrate conductor and a contact at the first surface, and a terminal at the second surface for electrically interconnecting
the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically
connected with the terminal,

the first element consists essentially of dielectric material, has a first surface facing the first surface of the substrate
and a second surface opposite the first surface, a first conductor at the first surface, a second conductor at the second
surface, and interconnect structure extending through the first element electrically connecting the first and second conductors,
and

the adhesive layer bonding the first surfaces of the first element and the first surface of the substrate with one another,
such that at least portions of the first conductor and the substrate conductor are exposed beyond an edge of the adhesive
layer; and

connecting the first conductor and substrate conductor by electrolessly plating first and second metal regions onto the first
conductor and the substrate conductor such that the first and second plated metal regions merge together during the plating
to form a continuous electroless plated metal region extending between the first conductor and the substrate conductor and
extending to a height above the first surface of the substrate, wherein the height is less than a height of the second surface
of the first element above the first surface of the substrate.

US Pat. No. 9,355,997

INTEGRATED CIRCUIT ASSEMBLIES WITH REINFORCEMENT FRAMES, AND METHODS OF MANUFACTURE

Invensas Corporation, Sa...

2. An assembly comprising:
a first substrate comprising a first side and one or more first contact pads at the first side;
one or more modules attached to the first substrate, each said module comprising a semiconductor integrated circuit, each
said module comprising one or more contact pads each of which is attached to a respective first contact pad; and

one or more reinforcement frames attached to the first substrate, each said reinforcement frame comprising one or more openings,
at least part of each said module being located in a corresponding opening in a corresponding reinforcement frame;

wherein in at least one said reinforcement frame, at least one said opening comprises a through-hole; and
the assembly further comprises one or more heat sinks each of which overlies one or more of said through-holes in one or more
of said reinforcement frames, wherein at least one said heat sink overlying at least one said through-hole in at least one
said reinforcement frame is attached to the reinforcement frame and/or to at least one said module at least partially located
in the through-hole, each said heat sink having a higher thermal conductivity than each said reinforcement frame.

US Pat. No. 9,087,815

OFF SUBSTRATE KINKING OF BOND WIRE

Invensas Corporation, Sa...

1. A method of forming an electrically conductive lead of a component, comprising:
a) using a bonding tool to bond a wire extending beyond a surface of a bonding tool to a metal surface;
b) drawing the bonding tool away from the metal surface while allowing the wire to extend farther from the surface of the
bonding tool;

c) clamping the wire to limit further extension of the wire beyond the surface of the bonding tool;
d) moving the bonding tool while the wire remains clamped such that the bonding tool imparts a kink to the wire at a location
where the wire is fully separated from any metal element other than the bonding tool; and

e) tensioning the wire using the bonding tool such that the wire breaks at the kink to define an end, wherein the lead comprises
the wire extending from the metal surface to the end.

US Pat. No. 9,530,458

STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
one or more microelectronic elements comprising active elements defining a memory storage array and address inputs for receipt
of address information specifying locations within the storage array; and

a substrate having a first surface and terminals exposed at the first surface, the terminals including first terminals electrically
coupled with the address inputs to provide address information received at the first terminals to the address inputs, each
of at least some of the first terminals having a signal assignment including information to be transferred to one or more
of the address inputs,

the first terminals disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein
signal assignments of the first terminals disposed on the first side are symmetric about the theoretical plane with the signal
assignments of the first terminals disposed on the second side.

US Pat. No. 9,490,195

WAFER-LEVEL FLIPPED DIE STACKS WITH LEADFRAMES OR METAL FOIL INTERCONNECTS

Invensas Corporation, Sa...

1. A stacked microelectronic assembly, comprising:
a plurality of stacked encapsulated microelectronic packages, each encapsulated microelectronic package comprising:
a microelectronic element having a front surface defining a plane, a plurality of edge surfaces extending away from the plane
of the front surface, the microelectronic element having a plurality of chip contacts at the front surface;

an encapsulation region having a major surface substantially parallel to the plane of the microelectronic element and a plurality
of remote surfaces extending away from the major surface, and the encapsulation region extending from at least one edge surface
of the microelectronic element to at least one of the remote surfaces which overlies the edge surface; and

a plurality of electrically conductive package contacts at a single one of the remote surfaces spaced apart from the corresponding
adjacent edge surface of the microelectronic element of the package, the chip contacts electrically coupled with the package
contacts,

the plurality of microelectronic packages stacked one above another in the stacked assembly such that the planes of the microelectronic
elements are parallel to one another, and the major surfaces of the encapsulation regions of respective microelectronic packages
in the stacked assembly are oriented towards one another,

wherein the package contacts are configured for electrically connecting the microelectronic assembly with a corresponding
set of substrate contacts at a major surface of a substrate in a state in which the major surface of the substrate is oriented
at a substantial angle to the plane of each microelectronic element and is oriented towards each single remote surface of
each of the stacked microelectronic packages.

US Pat. No. 9,324,626

INTERPOSERS WITH CIRCUIT MODULES ENCAPSULATED BY MOLDABLE MATERIAL IN A CAVITY, AND METHODS OF FABRICATION

Invensas Corporation, Sa...

1. A circuit assembly comprising a plurality of levels “Li” where Li varies from L0 through Ln, i being an integer varying from 0 to n, wherein n is an integer greater than one, the circuit assembly comprising
a substrate whose top side comprises a cavity comprising a bottom wall;
wherein the level L0 comprises:

the bottom wall;
a plurality of through-holes each of which passes through the bottom wall;
a plurality of conductors (“L0 conductors”) in respective through-holes;

wherein at least part of level L1 overlies at least part of level L0, and wherein level L1 comprises one or more circuit modules each of which has one or more contact pads each of which is electrically connected
to one or more L0 conductors;

wherein for each level Li other than L0 and L1:

at least part of level Li overlies at least part of level Li-1;

each level Li comprises one or more circuit modules each of which has one or more contact pads each of which is electrically
connected to one or more L0 conductors by one or more first electrically conductive paths lying in the cavity, each first electrically conductive path
passing through each level L1 through Li-1;

wherein at least one first electrically conductive path passes through more than one of the levels L1 through Ln-1.

US Pat. No. 9,293,444

CO-SUPPORT FOR XFD PACKAGING

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a dielectric element having first and second oppositely facing surfaces, and having first and second spaced apart apertures
each extending between the first and second surfaces, the dielectric element further having first and second parallel edges
extending between the first and second surfaces, a first region of the second surface disposed between the first aperture
and the first edge, a second region of the second surface being disposed between the second aperture and the second edge;
and

first and second microelectronic elements each having a front face facing the first surface and a rear face facing away from
the first surface, each microelectronic element having contacts exposed at the respective front face,

the dielectric element having terminals at the second surface, the contacts of the first microelectronic element overlying
the first aperture and electrically coupled with the terminals, and the contacts of the second microelectronic element overlying
the second aperture and electrically coupled with the terminals,

wherein the terminals include first terminals and second terminals, the second terminals including at least some second terminals
configured to carry address information for specifying each individual addressable memory location within the memory storage
arrays,

the second terminals including a first group thereof disposed in the first region adjacent the first edge of the second surface,
and a second group thereof disposed in the second region adjacent the second edge of the second surface, the second terminals
configured to carry all of the address information usable by circuitry within the microelectronic package.

US Pat. No. 9,263,413

SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT

Invensas Corporation, Sa...

1. A microelectronic package comprising:
at least one microelectronic element;
first conductive elements including terminals exposed at a mounting surface of the package, at least some of the first conductive
elements being electrically connected to the at least one microelectronic element through vias integrally formed with the
first conductive elements;

wire bonds having bases joined to respective ones of the first conductive elements and adjacent a first surface of a dielectric
layer, the wire bonds having end surfaces remote from the bases, each of the wire bonds respectively defining an edge surface
extending between a base and an end surface respectively thereof; and

the dielectric layer having the first surface and a second surface remote from the first surface, at least a portion of the
first surface being exposed at the mounting surface of the package, the dielectric layer filling spaces between the wire bonds
separated from one another by the dielectric layer, wherein unencapsulated portions of the wire bonds at end surfaces thereof
being uncovered by the dielectric layer at the second surface thereof.

US Pat. No. 9,070,423

SINGLE PACKAGE DUAL CHANNEL MEMORY WITH CO-SUPPORT

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a support element having first and second oppositely-facing surfaces and a plurality of substrate contacts at the first surface
or the second surface, the support element having oppositely-facing north and south edges adjacent to oppositely-facing east
and west edges each extending between the north and south edges, the second surface having a southwest region encompassing
entire lengths of the south and west edges and extending in orthogonal directions from each of the south and west edges one-third
of each distance toward the north edge and toward the east edge, respectively;

zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, each microelectronic element
having a memory storage array and first and second columns of element contacts extending along a front face thereof adjacent
and parallel to first and second opposite edges of the front face, respectively, the first and second edges of the zeroth
microelectronic element adjacent the south and north edges, respectively, and the first and second edges of the first microelectronic
element adjacent the west and east edges, respectively; and

terminals at the second surface electrically coupled with the microelectronic elements via the substrate contacts, the terminals
including first terminals at the southwest region, the first terminals configured to carry address information usable by circuitry
within the microelectronic package to determine an addressable memory location from among all the available addressable memory
locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

US Pat. No. 9,601,467

MICROELECTRONIC PACKAGE WITH HORIZONTAL AND VERTICAL INTERCONNECTIONS

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a substrate having an upper surface and a lower surface opposite the upper surface;
a first wire bond wire of a first length coupled to the upper surface at a first end of the first wire bond wire;
a first bond mass coupled to a second end of the first wire bond wire;
a second wire bond wire of a second length coupled to the upper surface at a first end of the second wire bond wire;
a second bond mass coupled to a second end of the second wire bond wire;
the first wire bond wire and the second wire bond wire laterally jutting out horizontally away from the upper surface of the
substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second
wire bond wire; and

the first wire bond wire and the second wire bond wire being horizontal for the distance with respect to being co-planar with
the upper surface within +/?10 degrees.

US Pat. No. 9,508,689

ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED DIE ASSEMBLIES

Invensas Corporation, Sa...

1. A method for forming a connector on a die pad at a wafer level of processing, comprising
forming a channel defining an interconnect die edge of a first die of the wafer and an adjacent edge of a second die of the
wafer, wherein the interconnect die edge of the first die, the edge of the second die, and the channel therebetween have longest
dimensions extending in a first direction, and a width of the channel extends in a second direction from the interconnect
die edge to the adjacent edge of the second die;

forming an electrically insulative material overlying a front surface of the wafer, the interconnect die edge, and the edge
of the second die, the insulative material spanning an entire width of the channel;

forming spots of a curable electrically conductive material over die pads and extending over an interconnect die edge above
the channel;

curing the conductive material; and
in a wafer cutting procedure thereafter severing the spots.

US Pat. No. 9,508,629

MEMORY MODULE IN A PACKAGE

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a substrate having first and second opposed surfaces;
first, second, third, and fourth microelectronic elements, each microelectronic element having a front surface and a plurality
of contacts at the front surface, the front surfaces of the microelectronic elements being arranged in a single plane parallel
to the first surface, each microelectronic element having a column of contacts exposed at the respective front surface, the
column of contacts of the first, second, third, and fourth microelectronic elements arranged along respective first, second,
third, and fourth axes, the first and third axes being parallel to one another, the second and fourth axes being transverse
to the first and third axes;

a plurality of terminals exposed at the second surface, the terminals configured for connecting the microelectronic package
to at least one component external to the microelectronic package; and

electrical connections extending from at least some of the contacts of each of the microelectronic elements to at least some
of the terminals.

US Pat. No. 9,496,154

USE OF UNDERFILL TAPE IN MICROELECTRONIC COMPONENTS, AND MICROELECTRONIC COMPONENTS WITH CAVITIES COUPLED TO THROUGH-SUBSTRATE VIAS

Invensas Corporation, Sa...

1. A manufacturing method comprising:
obtaining a first microelectronic component comprising one or more first cavities and, for each first cavity, at least one
first contact pad recessed in the first cavity, the first cavity comprising a void above the first contact pad;

attaching an underfill tape to the first microelectronic component, the underfill tape at least partially covering each first
cavity's void; and

attaching a second microelectronic component to the first microelectronic component with the underfill tape between the first
and second microelectronic components, wherein the second microelectronic component comprises one or more protruding second
contact pads, and during the attaching of the second microelectronic component, each second contact pad enters a respective
first cavity through the underfill tape and bonds to a respective first contact pad;

wherein during the attaching of the second microelectronic component, at least one second contact pad pushes the underfill
tape into the respective first cavity's void and stretches the underfill tape inside the respective first cavity's void.

US Pat. No. 9,490,230

SELECTIVE DIE ELECTRICAL INSULATION BY ADDITIVE PROCESS

Invensas Corporation, Sa...

1. A method for forming a stacked die assembly, comprising:
on a plurality of die, electrically insulating a selected interconnect pad of a plurality of interconnect pads exposed at
a selected region of a die by selectively applying a dielectric material onto the selected interconnect pad in the selected
region of the die by selectively depositing at least one of a spot or a line of dielectric material via a nozzle onto the
selected region of the die, the selectively depositing leaving nonselected interconnect pads exposed and free from depositing
of the dielectric material thereon, such that the nonselected interconnect pads are available for electrical interconnection
without requiring the deposited dielectric material to be removed from the nonselected interconnect pads, the nozzle being
controlled so that the dielectric material flows from the nozzle during intervals when a flow axis of the nozzle is directed
at the selected interconnect pad and does not flow from the nozzle during intervals when the flow axis is directed at an unselected
interconnect pad; and

stacking the plurality of die such that front sides of the die are arranged in a plurality of parallel planes, wherein at
least some of the interconnect pads are aligned in respective columns extending transverse to the parallel planes,

wherein in the stacked die assembly, at least one nonselected interconnect pad in a column is available for electrical interconnection
and the selected interconnect pads in the same column are electrically insulated.

US Pat. No. 9,356,006

BATCH PROCESS FABRICATION OF PACKAGE-ON-PACKAGE MICROELECTRONIC ASSEMBLIES

Invensas Corporation, Sa...

1. A method of fabricating a microelectronic assembly, comprising:
joining first and second subassemblies to form an assembly, the assembly comprising a first support element and a second support
element, the first support element having an outwardly-facing first surface facing a first direction, and the second support
element having an outwardly-facing first surface facing a second direction opposite from the first direction, the first support
element having electrically conductive first elements at an inwardly-facing second surface thereof, and the second support
element having electrically conductive second elements at an inwardly-facing second surface thereof, at least one microelectronic
element being mounted overlying the second surface of one of the first and second support elements, a patterned layer of photo-imageable
material overlying the second surface of one of the first or second support elements, the patterned layer having openings
with cross-sectional dimensions which are constant or increase with height from the surface of the respective support element
over which the patterned layer lies, and the assembly further comprising masses of bonding material extending from the first
elements through the respective openings and electrically coupled with the respective second elements, the masses having cross-sectional
dimensions defined by the cross-sectional dimensions of the respective openings; and

flowing an encapsulant into a space between the first and second subassemblies to form an encapsulation contacting surfaces
of at least portions of the masses.

US Pat. No. 9,226,396

POROUS ALUMINA TEMPLATES FOR ELECTRONIC PACKAGES

Invensas Corporation, Sa...

1. An interposer, comprising:
a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction
from the first surface towards the second surface, wherein alumina extends along a wall of each pore;

a plurality of electrically conductive connection elements extending in the first direction, the connection elements consisting
essentially of aluminum and being electrically isolated from one another by at least the alumina extending along the walls
of the pores;

a first conductive path provided at the first surface for connection with a first component external to the interposer; and
a second conductive path provided at the second surface for connection with a second component external to the interposer,
wherein the first and second conductive paths are electrically connected through at least some of the connection elements,
and

wherein at least some of the pores are disposed adjacent one another in annular patterns, and at least some of the annular
patterns encompass connection elements of the plurality of connection elements and the alumina extending along the walls of
the pores of the at least some annular patterns electrically isolates respective connection elements from one another.

US Pat. No. 9,515,024

STRUCTURES WITH THROUGH VIAS PASSING THROUGH A SUBSTRATE COMPRISING A PLANAR INSULATING LAYER BETWEEN SEMICONDUCTOR

Invensas Corporation, Sa...

1. A manufacturing method comprising:
(1) obtaining a structure comprising:
a planar insulating layer having a first planar surface and a second planar surface opposite to the first planar surface;
a first semiconductor layer having a planar surface contacting the first planar surface of the planar insulating layer; and
a second semiconductor layer having a planar surface contacting the second planar surface of the planar insulating layer;
(2) forming one or more through vias each of which passes through the first and second semiconductor layers and the planar
insulating layer; and

(3) forming a conductor in each through via, the conductor providing a conductive path in the through via between the first
and second semiconductor layers;

wherein each through via comprises:
a respective first via portion passing through the first semiconductor layer and formed in operation (2) by removing part
of the first semiconductor layer from a side opposite to the second semiconductor layer; and

a respective second via portion passing through the second semiconductor layer and formed in operation (2) by removing part
of the second semiconductor layer from a side opposite to the first semiconductor layer;

wherein in each through via, the conductor comprises a first conductor portion present in the respective first via portion
but not in the respective second via portion, and comprises a second conductor portion present in the respective second via
portion but not in the respective first via portion;

wherein the method further comprises thinning the second semiconductor layer before forming any second via portion but after
forming each first via portion and each first conductor portion.

US Pat. No. 9,484,379

REAR-FACE ILLUMINATED SOLID STATE IMAGE SENSORS

Invensas Corporation, Sa...

1. A microelectronic unit comprising:
a semiconductor element having a front surface and a rear surface remote from the front surface;
a packaging layer attached to the front surface of the semiconductor element;
a layer including adhesive material attaching the semiconductor element to the packaging layer,
wherein the semiconductor element includes a light detector disposed adjacent to the front surface and aligned with a portion
of the rear surface to receive light through the rear surface, wherein the light detector includes a plurality of light detector
elements arranged in an array, wherein a conductive contact of the semiconductor element has a first surface and a second
surface remote from the first surface, wherein the conductive contact is disposed within the adhesive material and has an
opening extending from the first surface through the conductive contact towards the second surface, the conductive contact
being a single layer bond pad having a single thickness; and

a conductive interconnect extending through the packaging layer and the opening of the conductive contact from the first surface
towards the second surface so as to contact a wall surface of the conductive contact, at least a portion of the conductive
interconnect being exposed at a surface of the microelectronic unit.

US Pat. No. 9,455,162

LOW COST INTERPOSER AND METHOD OF FABRICATION

Invensas Corporation, Sa...

1. A method for making an interposer comprising:
forming a conductive layer contacting a replicate such that a shape of a surface of the conductive layer conforms to a shape
of the contacted portion of the replicate, the conductive layer having a base and a plurality of conductive posts projecting
away from the base, each conductive post having a post end opposite the base;

attaching a support layer to the replicate to provide support to the replicate during at least one processing step;
forming a dielectric layer covering the base and separating adjacent ones of the posts from each other; and
removing a portion of the conductive layer to insulate at least one post from at least one other post, a remaining portion
of the conductive layer forming at least one via;

forming a second conductive layer contacting the replicate such that a shape of a surface of the second conductive layer conforms
to a shape of the contacted portion of the replicate, the second conductive layer having a second base and a plurality of
second conductive posts projecting away from the second base, each second conductive post having a second post end opposite
the second base, the second conductive layer contacting the replicate on a side of the replicate opposite the conductive layer;

removing the replicate from the support layer;
forming a first conductive coating over at least a portion of the conductive posts of the conductive layer; and
forming a second conductive coating onto the base of the conductive layer,
wherein the first and second conductive coatings are electrically connected through the conductive layer.

US Pat. No. 9,401,288

LOW CTE INTERPOSER

Invensas Corporation, Sa...

1. A method for making an interconnection component, comprising the steps of:
forming a redistribution layer on an in-process unit, the in-process unit including a first support portion having a plurality
of openings extending from a first surface of the first support portion in a direction substantially perpendicular thereto,
and the redistribution layer including routing circuitry in registration with the plurality of openings;

joining a second support portion having first and second opposed major surfaces defining a thickness therebetween with the
in-process unit such that the redistribution layer is disposed between the first and second support portions; and

filling the first openings with a conductive material to form first conductive vias extending through the first support portion
connected with the routing circuitry of the redistribution layer, and forming second conductive vias in the second support
portion extending through the second support portion substantially perpendicular to the major surfaces and such that each
of the second conductive vias has a first end and a second end, the first and second ends of the second conductive vias being
substantially flush with the respective first and second surfaces of the second support portion, such that the first conductive
vias extend through the first support portion and the second conductive vias extend through the second support portion, the
first and second vias being electrically connected through the redistribution layer,

wherein at least the second support portion is made from a semiconductor material, and wherein forming at least the second
conductive vias includes forming holes in the second support portion defining a hole wall, depositing a dielectric lining
along the hole wall, and filling the remainder of the hole with a conductive metal.

US Pat. No. 9,219,050

MICROELECTRONIC UNIT AND PACKAGE WITH POSITIONAL REVERSAL

Invensas Corporation, Sa...

1. A semiconductor package comprising:
(a) a first chip having oppositely-directed front and rear surfaces, left and right edges spaced apart from one another in
a lateral direction and bounding the front and rear surfaces; and left and right columns of contacts at the front surface
extending in a column direction transverse to the lateral direction; and

(b) interconnect pads overlying the front surface of the first chip, the interconnect pads being connected to at least some
of the contacts, the interconnect pads and the contacts or the interconnect pads alone forming an array of external connection
elements such that a first set of the external connection elements including at least some contacts of the right column or
interconnect pads connected to contacts of the right column is disposed to the left of a second set of the external connection
elements including at least some contacts of the left column or interconnect pads connected to contacts of the left column;

(c) a package substrate, the first chip being disposed above the package substrate with the front surface of the first semiconductor
chip facing upwardly away from the package substrate;

(d) left leads extending from the first set of the external connection elements over the left edge of the first semiconductor
chip to the package substrate;

(e) right leads extending from the second set of the external connection elements over the right edge of the first semiconductor
chip to the package substrate, the package further comprising

a second chip having oppositely-directed front and rear surfaces, left and right edges spaced apart from one another in a
lateral direction and bounding the front and rear surfaces; and contacts at the front surface, the first and second chips
being disposed in a stack with the rear surfaces of the chips facing one another, the front surface of the second chip facing
downwardly toward the package substrate so that the left edge of the first chip and the right edge of the second chip define
a left side of the stack and the right edge of the first chip and the left edge of the second chip define a right side of
the stack,

wherein the package substrate has a plurality of terminals for electrically connecting the package with a component external
to the package, the terminals including common terminals, each common terminal being electrically coupled with a contact of
the first chip and a contact of the second chip, wherein at least some of the common terminals are electrically coupled with
at least some of the contacts on the first chip through the left and right leads, wherein at least some of the electrical
connections between the common terminals and contacts of the first chip include the interconnect pads.

US Pat. No. 9,640,236

REDUCED LOAD MEMORY MODULE USING WIRE BONDS AND A PLURALITY OF RANK SIGNALS

Invensas Corporation, Sa...

1. A memory system, comprising:
a first memory module and a second memory module coupled to a same memory channel for sharing the memory channel;
each of the first memory module and the second memory module, comprising:
a circuit platform;
a plurality of memory chips coupled to the circuit platform;
wherein each memory chip of the plurality of memory chips has a plurality of memory dies;
at least one controller coupled to the circuit platform and further coupled to the plurality of memory chips for communication
with the plurality of memory dies thereof;

wherein the at least one controller is for receiving chip select signals to provide a plurality of rank select signals in
excess of the chip select signals;

wherein the plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for
coupling the circuit platform for communicating via a memory channel; and

wherein the load is sufficiently reduced for having at least the first memory module and the second memory module share the
memory channel;

wherein a memory chip of the first memory module and a memory chip of the second memory module are commonly coupled to receive
an N-bit rank select signal of the plurality of rank select signals for sharing the memory channel;

wherein a first portion of the N-bit rank select signal is for a front/reverse-side select signal;
wherein a second portion of the N-bit rank select signal is for a local-chip select signal; and
wherein a third portion of the N-bit rank select signal is for a die select signal.

US Pat. No. 9,620,436

LIGHT EMITTING DIODE DEVICE WITH RECONSTITUTED LED COMPONENTS ON SUBSTRATE

Invensas Corporation, Sa...

1. A method of joining multiple light emitting diode (LED) components, the method comprising:
testing a wafer for a known good die (KGD)-LED component;
flip chip bonding multiple KGD-LED components onto a substrate, the substrate includes redistribution layers (RDLs) that facilitate
electrical connections between the KGD-LED components and an operating device; and

under-filling a gap and spaces in between the KGD-LED components with a transparent material, wherein the transparent material
is transparent to a light wavelength emitted by the LED components and has a refractive index close to a refractive index
of the substrate that is transparent.

US Pat. No. 9,615,451

POROUS ALUMINA TEMPLATES FOR ELECTRONIC PACKAGES

Invensas Corporation, Sa...

1. An interposer, comprising:
a region having first and second oppositely facing surfaces and a plurality of pores each extending in a first direction from
the first surface towards the second surface, and having alumina extending along a wall of the each pore,

a plurality of connection elements extending in the first direction and formed in some of the plurality of pores, each connection
element comprising an electrically conductive material extending into one pore, the connection elements being electrically
isolated from one another by at least the alumina extending along the walls of the pores;

a first conductive path provided at the first surface for connection with a first component external to the interposer; and
a second conductive path provided at the second surface for connection with a second component external to the interposer,
wherein the first and second conductive paths are electrically connected through at least some of the connection elements,
and

at least some of the pores are disposed adjacent one another such that regions of the alumina which extend along the walls
of directly adjacent pores are merged together in a common electrically isolating region surrounding and electrically isolating
each of a plurality of the electrically conductive connection elements from one another.

US Pat. No. 9,601,454

METHOD OF FORMING A COMPONENT HAVING WIRE BONDS AND A STIFFENING LAYER

Invensas Corporation, Sa...

1. A method of forming a component, comprising:
forming a plurality of wire bonds, each having a first end bonded to a conductive element of a plurality of conductive elements
at a surface of the component, wherein the wire bonds have second ends remote from the first ends, the wire bonds having lengths
between their respective first and second ends;

forming a first layer covering a first portion of the length of each wire bond;
inserting the second ends of the wire bonds into a removable film;
then forming a second layer overlying the first layer and covering a second portion of the length of each wire bond; and
then removing the removable film from the wire bonds,
wherein the second ends of the wire bonds are uncovered by the second layer at a surface of the second layer above the first
layer and remote from the first layer, and

wherein the first layer increases stiffness of the wire bonds.

US Pat. No. 9,601,474

ELECTRICALLY STACKABLE SEMICONDUCTOR WAFER AND CHIP PACKAGES

Invensas Corporation, Sa...

1. A stackable unit for a chip scale package capable of being built-up from multiple stacked instances of the stackable unit,
each stackable unit comprising:
a substrate composed of a first semiconductor material;
multiple chips composed of a second semiconductor material adhered to a first surface of the first semiconductor material;
a first insulating layer surmounting the first surface of the first semiconductor material and the multiple chips;
conductive vias through the first insulating layer in electrical communication with the first semiconductor material and the
multiple chips;

a first conductive pattern layer surmounting the first insulating layer and electrically connecting at least some of the conductive
vias;

at least one opening at a second surface of the first semiconductor material etched through an entire thickness of the first
semiconductor material;

an inlay of an insulating material in the at least one opening; and
multiple separate conductive vias in the inlay of each single opening, each of the multiple separate conductive vias connected
to a conductive via in the first insulating layer to provide an individual conductive via through an entire thickness of the
stackable unit.

US Pat. No. 9,583,411

FINE PITCH BVA USING RECONSTITUTED WAFER WITH AREA ARRAY ACCESSIBLE FOR TESTING

Invensas Corporation, Sa...

1. A method for simultaneously making a plurality of microelectronic units, comprising the steps of:
providing an electrically conductive redistribution structure on a carrier and providing a plurality of microelectronic element
attachment regions spaced apart from one another in at least a first direction parallel with a surface of the carrier;

forming a plurality of electrically conductive connector elements between adjacent attachment regions, each connector element
having a first end, a second end and edge surfaces extending vertically between the first and second ends, the first end of
each connector element being adjacent the redistribution structure and the second end of each connector element at a height
greater than 50 microns above the carrier;

forming a dielectric encapsulation between adjacent edge surfaces of the connector elements;
further processing including singulating to form a plurality of microelectronic units, each microelectronic unit including
a microelectronic element having a first face which faces away from the redistribution structure, and the microelectronic
element having element contacts at the first face which are configured for joining with corresponding component contacts of
a component external to the microelectronic unit through electrically conductive masses in a state in which the element contacts
are juxtaposed with the corresponding component contacts.

US Pat. No. 9,530,945

INTEGRATED CIRCUIT DEVICE

Invensas Corporation, Sa...

1. A packaged optoelectronic chip comprising:
a die including at least one of a radiation emitter and a radiation receiver, the die including a first surface, a second
opposed surface, edge surfaces extending in a direction away from the first surface, and bond pads exposed at the first surface
of the die;

a transparent packaging layer overlying one of the first and second surfaces of the die, the transparent packaging layer having
an inner surface facing the die, an opposed outer surface, and a plurality of edges, the plurality of edges defining a step
and each of the plurality of edges having surfaces facing an exterior of the chip package, at least some of the plurality
of edges extending at least partially between the inner and outer surfaces of the transparent packaging layer, the at least
some of the plurality of edges including a first edge surface bounding an exterior perimeter of the inner surface and a second
edge surface bounding an exterior perimeter of the outer surface; and

an opaque layer covering a portion of the transparent packaging layer adjacent at least one of the plurality of edges of the
transparent packaging layer.

US Pat. No. 9,595,511

MICROELECTRONIC PACKAGES AND ASSEMBLIES WITH IMPROVED FLYBY SIGNALING OPERATION

Invensas Corporation, Sa...

1. A microelectronic assembly, comprising:
a circuit panel having panel contacts at a major surface thereof, and electrically conductive elements configured to conduct
signals of a common signaling bus, the electrically conductive elements coupled with respective sets of the panel contacts
at respective first and second connection regions at the major surface; and

a microelectronic unit comprising a plurality of microelectronic packages, each package having a surface and a plurality of
terminals at the surface, the terminals of the respective package coupled with the respective set of panel contacts,

each package comprising a microelectronic element having a front surface and element contacts at the front surface, each microelectronic
element including a memory storage array, wherein the front surface of the microelectronic element is disposed at a substantial
angle relative to a plane defined by the major surface of the circuit panel; and
the at least one microelectronic unit further comprising a plurality of delay elements thereon, each delay element electrically
coupled with a signaling path of the common signaling bus extending on the microelectronic unit between a first terminal of
a first package coupled to a panel contact at the first connection region, and a second terminal of the microelectronic unit
coupled to a panel contact at the second connection region, the signaling path electrically coupled to the microelectronic
element of the first package between the first terminal and the second terminal, whereby each delay element is configured
to increase a total electrical length along the signaling path between the first connection region and a connection region
at which a package adjacent to the first package is electrically coupled.

US Pat. No. 9,589,879

SUBSTRATES WITH THROUGH VIAS WITH CONDUCTIVE FEATURES FOR CONNECTION TO INTEGRATED CIRCUIT ELEMENTS, AND METHODS FOR FORMING THROUGH VIAS IN SUBSTRATES

Invensas Corporation, Sa...

1. A structure comprising:
(1) a substrate having a first side and a second side opposite to the first side, the substrate comprising a first material;
(2) a through via passing through the first material of the substrate between the first and second sides, the through via
having a first segment and a second segment joining the first segment inside the substrate, the first segment extending from
the first side to the second segment, the second segment extending from the first segment to the second side, the first segment
having an end adjacent to the second segment, the second segment having an end adjacent to the first segment;

wherein when viewed from the first side, said end of the first segment completely laterally surrounds said end of the second
segment but is laterally spaced from said end of the second segment;

(3) a conductive feature passing through the through via and forming at least a part of a conductive path provided for connection
to a circuit element of an integrated circuit, the conductive feature comprising:

a first conductive section present in the first segment;
a second conductive section present in the second segment and extending into the first segment, wherein when viewed from the
first side, a portion of the second conductive section in the first segment spreads laterally beyond said end of the second
segment; and

a first conductive layer separating the first conductive section from the second conductive section and present in the first
segment but not in the second segment, the first conductive layer being a material not present in the first segment in the
first and second conductive sections.

US Pat. No. 9,583,456

MULTIPLE BOND VIA ARRAYS OF DIFFERENT WIRE HEIGHTS ON A SAME SUBSTRATE

Invensas Corporation, Sa...

1. An apparatus, comprising:
a substrate;
first wire bond wires (“first wires”) in a first region, the first wires extending from a surface of the substrate;
second wire bond wires (“second wires”) in a second region, the second wires extending from the surface of the substrate;
wherein the first wires and the second wires are external to the substrate;
wherein the first region is disposed at least partially within the second region;
wherein the first wires are of a first height; and
wherein the second wires are of a second height greater than the first height for coupling of at least one electronic component
to the first wires.

US Pat. No. 9,558,964

METHOD OF FABRICATING LOW CTE INTERPOSER WITHOUT TSV STRUCTURE

Invensas Corporation, Sa...

1. A method of fabricating a microelectronic assembly, comprising:
forming an encapsulant filling spaces between adjacent ones of electrically conductive elements projecting upwardly above
a second surface of a dielectric region, the second surface opposite from a first surface of the dielectric region which faces
and is supported on a supporting structure, wherein a plurality of traces electrically connected with the conductive elements
and extend in at least one direction parallel to the second surface, the encapsulant having a surface overlying and facing
away from the second surface, wherein ends of the conductive elements are at the surface of the encapsulant;

and then removing at least a portion of the thickness of the supporting structure in a direction towards the first surface
of the dielectric region, wherein a plurality of contacts are at the first surface of the dielectric region, the contacts
electrically coupled with the conductive elements;

and then assembling a microelectronic element having a face and a plurality of element contacts at the face, the assembling
performed such that the element contacts face and are joined to the plurality of contacts at the first surface of the dielectric
region, thereby electrically interconnecting the element contacts with the contacts at the first surface of the dielectric
region,

wherein the encapsulant has a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least
one of the dielectric region or the microelectronic element.

US Pat. No. 9,524,883

HOLDING OF INTERPOSERS AND OTHER MICROELECTRONIC WORKPIECES IN POSITION DURING ASSEMBLY AND OTHER PROCESSING

Invensas Corporation, Sa...

1. A manufacturing method comprising:
obtaining a microelectronic workpiece comprising a first side and a second side opposite to the first side, the workpiece
comprising first circuitry comprising a plurality of first conductive features each of which forms a protrusion on the first
side;

obtaining a first structure comprising a first plurality of holes;
placing the first structure between the workpiece's first side and a holding stage of a holder so that each of said protrusions
enters a respective one of the holes and at least two protrusions enter respective different holes, with the first structure
being in a first position relative to the workpiece without being bonded to the first structure;

operating the holder to create an attraction force that holds the workpiece on the first structure in the first position without
separately bonding the workpiece to the first structure;

with the workpiece being in the first position, processing the second side of the workpiece;
after processing the second side of the workpiece, operating the holder to diminish the attraction force; and then
separating the workpiece from the first structure.

US Pat. No. 9,524,947

MICROELECTRONIC INTERCONNECT ELEMENT WITH DECREASED CONDUCTOR SPACING

Invensas Corporation, Sa...

1. A method of forming a microelectronic interconnect element, comprising:
(a) given a layered element including a first thin exposed metal layer having a first thickness, a second exposed metal layer
having a second thickness substantially greater than the first thickness, and a removable layer sandwiched between the first
thin exposed metal layer and second exposed metal layers, plating a plurality of first metal lines onto a first surface of
the first thin exposed metal layer;

(b) forming a dielectric layer overlying the plurality of first metal lines;
(c) removing at least the second exposed metal layer and the removable layer to expose a second surface of the first thin
exposed metal layer;

(d) plating a plurality of second metal lines onto the second surface of the first thin exposed metal layer; and
(e) removing at least a portion of the first thin exposed metal layer exposed between the plurality of first metal lines and
plurality of second metal lines.

US Pat. No. 9,515,053

MICROELECTRONIC PACKAGING WITHOUT WIREBONDS TO PACKAGE SUBSTRATE HAVING TERMINALS WITH SIGNAL ASSIGNMENTS THAT MIRROR EACH OTHER WITH RESPECT TO A CENTRAL AXIS

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a microelectronic element having a face and clement contacts exposed at the face, the microelectronic element having memory
storage array function;

a substrate having first and second opposed surfaces, the substrate having a set of substrate contacts exposed at the first
surface facing the element contacts of the microelectronic element and joined to the element contacts; and

terminals exposed at the second surface configured for connecting the microelectronic package with at least one component
external to the package, the terminals electrically connected with the substrate contacts and including first terminals, the
first terminals including a first set disposed on a first side of a theoretical axis and a second set disposed on a second
side of the theoretical axis opposite from the first side, each of the first and second sets being configured to carry address
information,

the terminals including second terminals, the second terminals including a third set disposed on the first side of the theoretical
axis and a fourth set disposed on the second side of the theoretical axis, each of the third and fourth sets being configured
to carry second information, the second information being other than the information carried by the first terminals, the second
information including data signals, wherein the first and second sets separate the third and fourth sets from one another,

wherein the signal assignments of the first terminals in the first set are a mirror image of the signal assignments of the
first terminals in the second set.

US Pat. No. 9,502,390

BVA INTERPOSER

Invensas Corporation, Sa...

1. An interposer, comprising:
a dielectric encapsulation having first and second oppositely-facing surfaces at which electrical connection can be made to
respective first and second external components; and

a plurality of wire bonds each separated from one another by the encapsulation, each wire bond having first and second opposite
extremities not fully covered by the encapsulation at the first and second surfaces, respectively, and an edge surface between
the first and second extremities contacted by the encapsulation and separated from the edge surfaces of adjacent wire bonds
by the encapsulation, at least one of the extremities of each wire bond being a base of such wire bond, each base being a
portion of the respective wire bond other than a cylindrically shaped shaft,

the interposer having first and second opposite sides, first contacts and second contacts at the first and second opposite
sides, respectively, for electrical connection with the first and second external components, respectively, the first contacts
being electrically connected with the second contacts through the wire bonds, the base of each wire bond contacting an adjacent
surface of a corresponding one of the first contacts or second contacts, the first and second contacts each configured to
be electrically connected with the first and second external components by a conductive bond material,

wherein one of the extremities of each wire bond opposite from the respective base is an end of such wire bond, and the encapsulation
has a recess extending from at least one of the first and second surfaces adjacent the end of each of at least some of the
wire bonds, each recess configured to receive the conductive bond material.

US Pat. No. 9,496,242

STACKABLE MICROELECTRONIC PACKAGE STRUCTURES

Invensas Corporation, Sa...

1. A microelectronic assembly, comprising:
a first microelectronic package and a second microelectronic package overlying the first microelectronic package, each of
the first and second microelectronic packages including:

first and second microelectronic elements, each having element contacts;
an interconnect area disposed between the first and second microelectronic elements;
a dielectric layer encapsulating the interconnect area and at least portions of the first and second microelectronic elements;
a plurality of package terminals electrically interconnected with the element contacts for connecting the package with a component
external to the package;

a plurality of stack terminals positioned within the interconnect area and electrically interconnected with the package terminals;
redistribution traces disposed at a surface of the dielectric layer and positioned at least partially within the interconnect
area, the redistribution traces electrically interconnecting the package terminals, the stack terminals, and the element contacts;
and

elongated conductive interconnects extending through the dielectric layer within the interconnect area, the conductive interconnects
joining the stack terminals and package terminals of the first microelectronic package and the stack terminals and package
terminals of the second microelectronic package.

US Pat. No. 9,583,426

MULTI-LAYER SUBSTRATES SUITABLE FOR INTERCONNECTION BETWEEN CIRCUIT MODULES

Invensas Corporation, Sa...

1. A method comprising fabricating one or more first multi-layer substrates for respective one or more members each of which
is operable to function at least as an interconnection substrate for providing interconnections between circuit modules, each
member comprising a plurality of contact pads for connection to the circuit modules, wherein said fabricating comprises:
forming a stack of first layers to provide a multi-layer structure, the multi-layer structure comprising circuitry comprising
a transistor;

separating the multi-layer structure into a plurality of multi-layer pieces at least one of which is a first multi-layer substrate
which comprises a part of each first layer and comprises the transistor, the first layers' parts extending to a first side
of the first multi-layer substrate, the multi-layer substrate comprising at least part of the circuitry which is accessible
from the first side of the first multi-layer substrate.

US Pat. No. 9,530,749

COUPLING OF SIDE SURFACE CONTACTS TO A CIRCUIT PLATFORM

Invensas Corporation, Sa...

1. An apparatus, comprising:
a microelectromechanical system component having a lower surface, an upper surface, first side surfaces, and second side surfaces;
wherein surface area of the first side surfaces is greater than surface area of the second side surfaces;
the microelectromechanical system component having a plurality of wire bond wires attached to and extending away from a first
side surface of the first side surfaces;

the plurality of wire bond wires having attached thereto solder balls at distal ends of the plurality of wire bond wires with
respect the first side surface; and

wherein the wire bond wires are self-supporting and cantilevered with respect to the first side surface of the first side
surfaces with the solder balls attached thereto.

US Pat. No. 9,741,620

STRUCTURES AND METHODS FOR RELIABLE PACKAGES

INVENSAS CORPORATION, Sa...

1. A method of forming a plurality of packages, the method comprising:
etching one or more cavities in a first side of a substrate device, the substrate device including conductive vias formed
in a substrate;

mounting chip devices to the first side of the substrate device to electrically contact the conductive vias;
depositing an encapsulation layer over the chip devices and filling the cavities;
planarizing a second side to reveal the conductive vias on the second side; and
singulating through the cavities to form said packages separated from each other, with each package having one or more of
said chip devices mounted on a respective singulated substrate device.

US Pat. No. 9,659,848

STIFFENED WIRES FOR OFFSET BVA

Invensas Corporation, Sa...

1. A component, comprising:
a generally planar element having oppositely-facing first and second surfaces extending in first and second transverse directions,
the generally planar element having a plurality of contacts at the first surface;

a reinforcing dielectric layer overlying the first surface of the generally planar element;
an encapsulation overlying the reinforcing dielectric layer, the encapsulation having a major surface facing away from the
first surface of the generally planar element; and

a plurality of wire bonds, each wire bond having a base joined with a contact of the plurality of contacts, and a tip remote
from the base at the major surface of the encapsulation, the wire bonds having first portions extending within at least a
portion of the reinforcing dielectric layer and second portions extending within the encapsulation, the first portions of
at least some of the wire bonds having bends that change an extension direction of the respective wire bond in at least one
of the first and second directions,

wherein the reinforcing dielectric layer has protruding regions surrounding respective wire bonds of the plurality of wire
bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than
portions of the reinforcing dielectric layer between adjacent ones of the protruding regions, the peak heights of the protruding
regions coinciding with points of contact between the reinforcing dielectric layer and individual ones of the wire bonds.

US Pat. No. 9,646,946

FAN-OUT WAFER-LEVEL PACKAGING USING METAL FOIL LAMINATION

Invensas Corporation, Sa...

1. A wafer-level package, comprising:
an integrated circuit die including metallic pillars;
at least a layer of a B-stage material occupying at least part of a volume between the metallic pillars of the integrated
circuit die;

predetermined holes in the B-stage material approximating a placement of the metallic pillars;
a patterned metal foil adhered by the B-stage material to the integrated circuit die or to a mold material of the wafer-level
package, the metal foil in conductive contact with the metallic pillars;

wherein the metal foil is patterned to create metal traces for relocating conductive contacts fanned in or fanned-out from
the metallic pillars; and

wherein the B-stage material comprises a compliant epoxy to reduce an interface stress between the metallic pillars and the
integrated circuit die at a fan-out boundary or a fan-in boundary of the wafer-level package.

US Pat. No. 9,607,928

METHOD AND STRUCTURES FOR VIA SUBSTRATE REPAIR AND ASSEMBLY

Invensas Corporation, Sa...

1. A method of fabricating a component, comprising:
forming a first layer structure being electrically conductive and extending within an opening in a substrate, the opening
extending from a first surface of the substrate towards a second surface opposite from the first surface, the opening having
an inner wall extending away from the first surface and a bottom remote from the first surface, a dielectric material being
exposed at the inner wall, the first layer structure extending at least partially along the inner wall, the first layer structure
contacting the dielectric material exposed at the inner wall, the first layer structure having a lower edge located between
the first and second surfaces of the substrate;

exposing the opening at the second surface of the substrate by processing applied to the substrate from above the second surface;
forming a second layer structure in contact with the lower edge of the first layer structure and in contact with a portion
of the dielectric material exposed at the inner wall, the second layer structure being electrically conductive and extending
at least partially along the inner wall; and

forming a principal conductor at least partially overlying the first layer structure and the second layer structure, the principal
conductor being exposed at the first and second surfaces of the substrate.

US Pat. No. 9,570,385

METHOD FOR FABRICATION OF INTERCONNECTION CIRCUITRY WITH ELECTRICALLY CONDUCTIVE FEATURES PASSING THROUGH A SUPPORT AND COMPRISING CORE PORTIONS FORMED USING NANOPARTICLE-CONTAINING INKS

Invensas Corporation, Sa...

1. A manufacturing method comprising:
(1) forming at least part of interconnection circuitry, said at least part of the interconnection circuitry comprising a core
portion and an electrically conductive layer overlaying at least part of the core portion and substantially conforming to
the core portion, wherein forming the at least part of the interconnection circuitry comprises:

depositing ink onto a substrate, the ink comprising conductive nanoparticles carried by a non-gaseous fluid carrier, the conductive
nanoparticles joining together to form the core portion, the core portion comprising one or more elongated segments above
the substrate; and

forming the electrically conductive layer over at least said part of the core portion to increase the electrical conductance
of at least one conductive feature, the electrically conductive layer covering an entire longitudinal surface of each elongated
segment;

(2) forming a support that fills, at least up to a level above each elongated segment, a region above the substrate around
each elongated segment, the support not completely covering said at least part of the interconnection circuitry to allow at
least each elongated segment to be electrically contacted from above the support;

wherein the interconnection circuitry comprises one or more electrically conductive features passing through the support to
interconnect circuits from a first side of the support to a second side of the support.

US Pat. No. 9,553,071

MULTI-CHIP PACKAGE WITH INTERCONNECTS EXTENDING THROUGH LOGIC CHIP

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a substrate having first and second oppositely-facing surfaces, a plurality of substrate contacts at the first surface and
a plurality of terminals at the second surface;

a first microelectronic element having a front surface and first contacts at its front surface, a rear surface opposite the
front surface, a semiconductor region between the front and rear surfaces, and electrically conductive interconnects extending
through the semiconductor region in a direction from the rear surface to the front surface, the first contacts facing and
joined with the substrate contacts;

a second microelectronic element having a front surface and second contacts at its front surface, the front surface and the
second contacts of the second microelectronic element partially overlying the rear surface of the first microelectronic element,

wherein the second contacts are electrically coupled with the substrate contacts through the interconnects, and
at least a portion of the rear surface of the first microelectronic element is uncovered by the second microelectronic element.

US Pat. No. 9,551,083

PADDLE FOR MATERIALS PROCESSING

Invensas Corporation, Sa...

1. A paddle for an electrochemical processing system, comprising:
a housing;
wherein the housing has a back portion and a front portion spaced apart from one another;
wherein the housing has a first side portion and a second side portion spaced apart from one another;
wherein the housing has a first end portion and a second end portion spaced apart from one another;
a first fin disposed laterally along a first external surface of the first side portion and offset and coupled to the first
external surface to define a first passageway between the first external surface of the first side portion and a first internal
surface of the first fin for flow of an electrolyte through the first passageway;

a second fin disposed laterally along a second external surface of the second side portion and offset and coupled to the second
external surface to define a second passageway between the second external surface of the second side portion and a second
internal surface of the second fin for flow of the electrolyte through the second passageway;

ingress openings of the first passageway and the second passageway being wider than egress openings of the first passageway
and the second passageway, respectively; and

the egress openings of the first passage way and the second passageway being proximate to or defined by the front portion
of the housing.

US Pat. No. 9,543,277

WAFER LEVEL PACKAGES WITH MECHANICALLY DECOUPLED FAN-IN AND FAN-OUT AREAS

Invensas Corporation, Sa...

1. A fan-out microelectronic package, comprising:
a microelectronic element having a face defining a plane, a plurality of bond pads at the face, and a plurality of edge surfaces
each extending in a direction transverse to the plane;

a dielectric element including a monolithic dielectric region of molded dielectric material or glass, the dielectric element
having one or more edge surfaces each juxtaposed with or contacting a corresponding edge surface of the microelectronic element,
a plurality of terminals and contacts at a major surface of the dielectric element overlying the monolithic dielectric region,
each terminal configured to connect with a component external to the package, the terminals coupled with the contacts through
traces supported on the dielectric element; and

a plurality of bond wires of extruded metal wire each having a first end joined with a bond pad of the plurality of bond pads
and a second end joined with a contact of the plurality of contacts and crossing over the corresponding edge surfaces of the
microelectronic element and the dielectric element, wherein at least some of the terminals are electrically coupled with at
least some of the bond pads through the bond wires.

US Pat. No. 9,536,862

MICROELECTRONIC ASSEMBLIES WITH INTEGRATED CIRCUITS AND INTERPOSERS WITH CAVITIES, AND METHODS OF MANUFACTURE

Invensas Corporation, Sa...

1. A microelectronic assembly comprising:
a plurality of interposers overlying one another and comprising a set of at least two interposers each of which comprises
one or more first contact pads;

a plurality of first modules each of which is attached to at least one of the interposers and comprises a respective semiconductor
integrated circuit and one or more contact pads each of which is electrically coupled to the integrated circuit and connected
to a respective first contact pad, wherein each interposer in the set has a first contact pad connected to a contact pad of
a first module;

wherein at least one of the interposers comprises one or more first cavities, and at least part of each first module is located
in at least one respective first cavity;

wherein the microelectronic assembly further comprises:
one or more first conductive vias each of which passes through at least part of at least respective one of the interposers
and reaches at least one respective first cavity and physically contacts, or is capacitively coupled to, circuitry of at least
one respective first module at least partially located in the respective first cavity;

one or more second conductive vias each of which has a segment which at least partially passes through at least respective
two of the interposers outside of any first cavity which have respective first conductive vias.

US Pat. No. 9,832,887

MICRO MECHANICAL ANCHOR FOR 3D ARCHITECTURE

Invensas Corporation, Sa...

1. A method of forming a component, comprising:
forming metal anchoring elements at a first surface of a support element having oppositely facing first and second surfaces,
the support element having a thickness extending in a first direction between the first and second surfaces, wherein each
anchoring element has an overhang surface, the metal anchoring elements comprising metal elements that are each supported
by a structure, each metal element having an upper surface facing away from the first surface and a lower surface remote from
the upper surface, wherein a portion of the lower surface, which extends beyond the structure which supports each metal element
respectively, defines the overhang surface;

then forming posts in corresponding openings of a mold overlying the anchoring elements respectively, the posts having first
ends proximate the first surface and second ends disposed above the first ends respectively and above the first surface,

wherein a laterally extending portion of each post contacts at least a first area of the overhang surface of the anchoring
element respectively; and

removing the mold to expose the posts above the first anchoring elements, wherein each said post projects above an exterior
surface of the component and is configured for insertion into and electrical connection with a corresponding electrically
conductive socket at an exterior surface of a separate second component which surface faces the exterior surface of the component,
wherein the component and the separate second component are each one of a microelectronic element, package substrate, interposer
or circuit panel, and

wherein the overhang surface of the anchoring element resists axial and shear forces applied to the posts at positions above
the anchoring elements, the axial and shear forces including those caused by removal of the mold.

US Pat. No. 9,741,649

INTEGRATED INTERPOSER SOLUTIONS FOR 2D AND 3D IC PACKAGING

INVENSAS CORPORATION, Sa...

26. An integrated circuit (IC) package, comprising:
a first substrate having a backside surface and a top surface with a cavity disposed therein, the cavity having a floor defining
a front side surface;

a plurality of first electroconductive contacts disposed on the front side surface;
a plurality of second electroconductive contacts disposed on the back side surface;
a plurality of first electroconductive elements penetrating through the first substrate and coupling selected ones of the
first and second electroconductive contacts to each other;

one or more first dies each of which contains an IC electroconductively coupled to corresponding ones of the first electroconductive
contacts, an entire top surface of each first die being coplanar with all of the top surface of the first substrate outside
the cavity;

a second substrate having a bottom surface permanently attached to the top surface of the first substrate outside the cavity,
the first and second substrates fully enclosing each first die; and

a dielectric material disposed in the cavity and encapsulating each first die.

US Pat. No. 9,735,084

BOND VIA ARRAY FOR THERMAL CONDUCTIVITY

Invensas Corporation, Sa...

1. A microelectronic device, comprising:
a substrate having a first upper surface and a first lower surface;
an integrated circuit die having a second upper surface and a second lower surface;
interconnects coupling the first upper surface of the substrate to the second lower surface of the integrated circuit die
for electrical communication therebetween;

a bond via array having proximal ends of wire bond wires thereof ball bonded to the second upper surface for conduction of
heat away from the integrated circuit die to and through the wire bond wires of the bond via array to the second upper surface;
and

a molding material disposed in the bond via array with distal ends of the wire bond wires of the bond via array extending
at least to a superior surface of the molding material.

US Pat. No. 9,698,131

METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES

Invensas Corporation, Sa...

1. A structure comprising circuitry for operation at one or more frequencies at least as high as a radio frequency, the circuitry
comprising:
one or more active devices; and
one or more passive devices electrically coupled to the one or more active devices;
wherein the structure comprises:
a first semiconductor substrate comprising at least part of the one or more active devices;
a second semiconductor substrate overlying the first semiconductor substrate and supporting at least part of the one or more
passive devices located over the second semiconductor substrate; and

a third semiconductor substrate located between the first and second semiconductor substrates;
wherein the circuitry further comprises one or more conductive paths passing through the second and third semiconductor substrates
and electrically coupling the one or more passive devices to the one or more active devices;

wherein the third semiconductor substrate is a semiconductor material reducing electromagnetic coupling between the one or
more passive devices and the one or more active devices at least at one of the one or more frequencies; and

wherein the second semiconductor substrate is a semiconductor material reducing electromagnetic coupling between the one or
more passive devices and the one or more active devices at least at one of the one or more frequencies.

US Pat. No. 9,646,917

LOW CTE COMPONENT WITH WIRE BOND INTERCONNECTS

Invensas Corporation, Sa...

1. A method of fabricating a component, comprising:
forming a structure including:
providing a first element having a plurality of wire bonds extending upwardly away from the first element; and
then inserting the wire bonds into one or more openings in a second element consisting essentially of a material having a
coefficient of thermal expansion (“CTE”) of less than 10 parts per million per degree Celsius (“ppm/° C.”),

wherein each of the plurality of wire bonds extends in an axial direction within an opening of the one or more openings in
the second element, and each of the plurality of wire bonds is spaced at least partially apart from a wall of the opening
within which it extends, the structure having first contacts at a first surface of the component and second contacts at a
second surface of the component facing in a direction opposite from the first surface, wherein electrical paths between the
first contacts and the second contacts extend through the wire bonds.

US Pat. No. 9,666,521

ULTRA HIGH PERFORMANCE INTERPOSER

Invensas Corporation, Sa...

1. An interconnection component for use in a microelectronic assembly, comprising:
a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in
a first direction therefrom by a thickness of the semiconductor material layer;

at least two metalized vias, each extending through the semiconductor material layer and having a first end at the first surface
and a second end at the second surface, a first pair of the at least two metalized vias being spaced apart from each other
in a second direction orthogonal to the first direction; and

a first insulating via in the semiconductor material layer extending from the first surface toward the second surface, the
first insulating via being positioned such that a geometric center of the first insulating via is between first and second
planes that are orthogonal to the second direction and that pass through first and second respective vias of the first pair
of the at least two metalized vias; and

a dielectric material at least partially filling the first insulating via or at least partially enclosing a void in the first
insulating via,

wherein the first insulating via extends through at least half of the thickness of the semiconductor material layer, and the
first insulating via has a width in a third direction perpendicular to the second direction, the width being equal to or greater
than a distance between the first pair of the at least two metalized vias.

US Pat. No. 9,633,975

MULTI-DIE WIREBOND PACKAGES WITH ELONGATED WINDOWS

Invensas Corporation, Sa...

1. A microelectronic package, comprising:
a substrate having first and second opposed surfaces, each extending in a first direction and a second direction transverse
to the first direction, the substrate having a first opening extending between the first and second surfaces and defining
first and second distinct parts each elongated along a first common axis extending in the first direction;

first and second microelectronic elements each having a front surface facing the first surface of the substrate and a column
of contacts at the respective front surface, the column of contacts of the first microelectronic element aligned with the
first part of the first opening and extending in the first direction, the column of contacts of the second microelectronic
element aligned with the second part of the first opening and extending in the first direction;

a plurality of terminals exposed at the second surface, the terminals configured for connecting the microelectronic package
to at least one component external to the microelectronic package;

first electrical connections aligned with the first part of the first opening extending from at least some of the contacts
of the first microelectronic element to at least some of the terminals; and

second electrical connections aligned with the second part of the first opening extending from at least some of the contacts
of the second microelectronic element to at least some of the terminals.

US Pat. No. 9,524,943

COMPACT SEMICONDUCTOR PACKAGE AND RELATED METHODS

Invensas Corporation, Sa...

1. An integrated circuit package, comprising:
a substrate having a first surface and a second surface opposite the first surface;
one or more conductive elements passing through the substrate, wherein the one or more conductive elements extend from the
first surface of the substrate toward the second surface of the substrate, and wherein the one or more conductive elements
extend beyond the second surface of the substrate, the second surface comprising one or more regions not occupied by the one
or more conductive elements;

a first component comprising a die, the first component comprising one or more contact areas for contacting a circuitry of
the die, the first component being attached within a first one of the one or more regions at the second surface, the first
component not laterally extending beyond the one or more regions;

a first dielectric layer overlying the second surface but not covering the one or more contact areas and the one or more conductive
elements, wherein the second surface is covered by a solid surface spaced from the substrate and comprising at least parts
of top surfaces of (a) the first dielectric layer, (b) the one or more contact areas of the first component, and (c) the one
or more conductive elements; and

one or more interconnect lines overlying the solid surface and coupling at least one said contact area of the first component
to at least one of the one or more conductive elements.

US Pat. No. 9,496,243

MICROELECTRONIC ASSEMBLY WITH OPPOSING MICROELECTRONIC PACKAGES EACH HAVING TERMINALS WITH SIGNAL ASSIGNMENTS THAT MIRROR EACH OTHER WITH RESPECT TO A CENTRAL AXIS

Invensas Corporation, Sa...

1. A microelectronic assembly, comprising:
a circuit panel having first and second opposed surfaces and first and second panel contacts at the first and second surfaces,
respectively; and

a first microelectronic package having a plurality of terminals mounted to the first panel contacts,
a second microelectronic package having a plurality of terminals mounted to the second panel contacts,
each of the first and second microelectronic packages including:
a substrate having first and second opposed surfaces, the first surface having substrate contacts thereon;
a microelectronic element having memory storage array function, the microelectronic element having a rear face facing the
first surface, a front face opposite the rear face, and contacts on the front face electrically connected with the substrate
contacts through conductive structure extending above the front face,

the plurality of terminals on the second surface configured for connecting the microelectronic package with at least one component
external to the package, the plurality of terminals electrically coupled with the substrate contacts and including first terminals
disposed at locations within first and second sets, each set of first terminals distributed at at least eight different positions
within a column of at least one column extending in a first direction, the first terminals of each of the first and second
sets being configured to carry address information usable by circuitry within the package to determine an addressable memory
location from among all the available addressable memory locations of a memory storage array within the microelectronic element,

wherein the signal assignments of the first terminals in the first set are symmetric about an axis extending in the first
direction with the signal assignments of the first terminals in the second set,

the terminals further including first and second groups of second terminals, each of the first and second groups of second
terminals having at least eight data terminals disposed on first and second opposite sides of the axis, respectively,

wherein each group of the second terminals being distributed at at least four different positions within a row of at least
one row extending in a second direction transverse to the first direction, and each of the data terminals of the first and
second groups is configured to carry a data signal for read and write access to locations of a memory storage array within
the microelectronic element, and each data terminal of the first group has modulo-X symmetry about the axis with each data
terminals of the second group, wherein X is a whole number greater than 2.

US Pat. No. 9,812,185

DRAM ADJACENT ROW DISTURB MITIGATION

Invensas Corporation, Sa...

1. A method for mitigating data loss in a memory array with addressable rows, wherein each addressable row requires regular
refresh operations, wherein each addressable row is physically adjacent to at least one other addressable row, and wherein
the memory array is coupled (i) to a decoder further coupled to address inputs, and (ii) to command circuitry further coupled
to command inputs, the method comprising:
(A) monitoring the command inputs to detect row activate commands;
(B) monitoring the address inputs to detect a sequence of active row addresses, each active row address associated with a
row activate command;

(C) identifying one or more detected row addresses by presenting the sequence of active row addresses to a first filter coupled
to the address inputs, the first filter detecting when an active row address occurs at a more frequent rate than a predetermined
maximum rate; and

(D) presenting each detected row address to a second filter coupled to the first filter, wherein:
(i) upon a first detection of a detected row address that row address is stored in a tracked address memory location, each
tracked address memory location being coupled to a first associated counter and a second associated counter, each counter
having a stored value,

(ii) the first associated counter and the second associated counter are both reset when the detected row address is first
stored in the tracked address memory location,

(iii) upon a subsequent detection of the detected row address in the tracked memory address location the first associated
counter is incremented, and

(iv) upon detection of every detected row address the second associated counter is incremented, and
(v) wherein:
if the value in any first counter exceeds a first predetermined value,
then a non-regular data loss mitigation refresh operation is performed for the one or more addressable rows physically adjacent
to detected row address stored in the associated tracked memory address location.

US Pat. No. 9,773,723

SSI POP

Invensas Corporation, Sa...

1. An assembly, comprising:
a first microelectronic package, including a substrate having a plurality of first contacts at a first or second surface thereof
and a plurality of second contacts at the first surface thereof, and a first microelectronic element having a plurality of
element contacts at a front surface thereof, the first contacts electrically coupled with the element contacts of the first
microelectronic element; and

a circuit structure having a first surface facing at least a portion of the first surface of the substrate with the first
microelectronic element between the circuit structure and the substrate, the circuit structure comprising a plurality of dielectric
layers and electrically conductive features therein, the circuit structure having a maximum thickness of less than 50 microns
in a direction normal to the first surface of the circuit structure,

the electrically conductive features including a plurality of bumps at the first surface of the circuit structure facing the
second contacts of the substrate and joined thereto, and a plurality of circuit structure contacts at a second surface of
the circuit structure opposite the first surface thereof configured for connection with contacts of a component external to
the assembly, the electrically conductive features including a plurality of traces coupling at least some of the bumps with
the circuit structure contacts,

wherein at least one of: the bumps, or connections between the bumps and the second contacts of the substrate comprises a
bond material, the assembly further comprising an underfill mechanically reinforcing the connections between the bumps of
the circuit structure and the second contacts, the underfill having a composition different from a composition of the substrate,
and different from a composition of the circuit structure.

US Pat. No. 9,741,696

THERMAL VIAS DISPOSED IN A SUBSTRATE PROXIMATE TO A WELL THEREOF

Invensas Corporation, Sa...

1. An apparatus, comprising:
a three-dimensional stacked integrated circuit having a first die;
wherein a substrate of the first die has at least one thermal via structure extending from a first surface of the substrate
toward a well of the substrate without extending to the well and without extending through the substrate;

wherein a first end of the at least one thermal via structure is proximate to the well of the substrate for conduction of
heat away therefrom through the at least one thermal via structure to a second end of the at least one thermal via structure;

wherein the substrate includes a semiconductor-on-insulator substrate having a buried dielectric layer; and
wherein the first end stops on the buried dielectric layer of the substrate.

US Pat. No. 9,728,495

RECONFIGURABLE POP

Invensas Corporation, Sa...

1. A stacked microelectronic assembly, comprising:
first and second microelectronic packages arranged in a stacked configuration, each of the microelectronic packages having:
a lower package face and an upper package face opposite the lower package face, lower terminals at the lower package face,
and upper terminals at the upper package face;

a microelectronic element having memory storage array function and contacts at an element face thereof; and
conductive interconnects each electrically connecting at least one lower terminal with at least one upper terminal, at least
some of the conductive interconnects electrically connected with the contacts of the microelectronic element, the conductive
interconnects including: first conductive interconnects configured to carry address information, second conductive interconnects
configured to carry data information to and from the microelectronic elements, and no connect conductive interconnects that
are electrically insulated from the microelectronic element within the respective microelectronic package,

wherein each of the first conductive interconnects of the first microelectronic package overlies and is electrically connected
with a corresponding one of the first conductive interconnects of the second microelectronic package having the same signal
assignment, and

wherein each second conductive interconnect of the first microelectronic package overlies and is electrically connected with
a no-connect conductive interconnect of the second microelectronic package, and each second conductive interconnect of the
second microelectronic package underlies and is electrically connected with a no-connect conductive interconnect of the first
microelectronic package.

US Pat. No. 9,728,527

MULTIPLE BOND VIA ARRAYS OF DIFFERENT WIRE HEIGHTS ON A SAME SUBSTRATE

Invensas Corporation, Sa...

1. A method, comprising:
obtaining a substrate;
feeding wire from a wire spool control head for:
forming a first bond via array of first wire bond wires (“first wires”) extending from a surface of the substrate having rows
and columns of the first wires; and

forming a second bond via array of second wire bond wires (“second wires”) extending from the surface of the substrate having
rows and columns of the second wires;

wherein the first bond via array and the second bond via array are external to the substrate;
wherein the first bond via array is disposed within a region of the second bond via array;
wherein the first wires of the first bond via array are of a first height; and
wherein the second wires of the second bond via array are of a second height greater than the first height for a package-on-package
configuration;

wherein a first pitch of the first wires of the first bond via array is less than 0.5 mm; and
wherein a second pitch of the second wires of the second bond via array is a range of approximately 0.01 to 0.5 mm.

US Pat. No. 9,633,971

STRUCTURES AND METHODS FOR LOW TEMPERATURE BONDING USING NANOPARTICLES

Invensas Corporation, Sa...

1. A method of making an assembly, comprising:
forming a first conductive element at a first surface of a substrate of a first component, the first conductive element extending
in a direction away from the first surface;

forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, the conductive
nanoparticles having long dimensions smaller than 100 nanometers;

juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major
surface of a substrate of a second component, with the conductive nanoparticles disposed in a bond region between the surfaces
of the first and second conductive elements; and

elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature
at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive
elements,

wherein the first conductive element is one of a plurality of first conductive elements at the first surface, and the second
conductive element is one of a plurality of second conductive elements at the major surface, corresponding surfaces of the
first and second conductive elements being juxtaposed with one another, and

wherein the juxtaposing step includes compressing thicknesses of the bond regions by different distances among different ones
of the juxtaposed first and second conductive elements, the thickness of the bond region varying among the different ones
of the juxtaposed first and second conductive elements by up to 3 microns so as to accommodate non-coplanarity of the top
surfaces of at least some of the first conductive elements.

US Pat. No. 9,633,979

MICROELECTRONIC ASSEMBLIES HAVING STACK TERMINALS COUPLED BY CONNECTORS EXTENDING THROUGH ENCAPSULATION

Invensas Corporation, Sa...

17. A method of fabricating a microelectronic assembly, comprising:
joining first and second subassemblies to form an assembly,
the assembly having terminals at a first outwardly facing surface of the assembly and electrically conductive elements at
a second outwardly facing surface of the assembly opposite from the first surface,

wherein at least one of the subassemblies has at least one microelectronic element mounted to an inwardly facing second surface
thereof, the microelectronic element being electrically coupled to the at least one subassembly, the first subassembly including
a first support element, and the second subassembly including a second support element, and

the first and second subassemblies including first connectors and second connectors, respectively, projecting above the inwardly
facing second surface of such support element towards the inwardly facing second surface of the other support element, and

each of at least some of the terminals is electrically coupled with an electrically conductive element of the electrically
conductive elements through a first connector of said first connectors and a second connector of said second connectors, and

dielectric reinforcing collars surrounding portions of connectors of one or more of: the first connectors, or the second connectors,
wherein during joining of the first and second subassemblies, first connectors are joined with second connectors and the dielectric
collars substantially prevent collapse of the connectors reinforced thereby, such that the assembly has increased height and
connections between the first and second support elements have increased aspect ratio; and

flowing an encapsulant into a space between the first and second support elements to form an encapsulation, the encapsulation
separating at least portions of individual pairs of an electrically coupled first and second connectors from one another.

US Pat. No. 9,831,302

MAKING ELECTRICAL COMPONENTS IN HANDLE WAFERS OF INTEGRATED CIRCUIT PACKAGES

Invensas Corporation, Sa...

1. An integrated circuit package comprising a first substrate and a second substrate bonded to the first substrate, with a
plurality of cavities enclosed by the first and second substrates, the plurality of cavities comprising one or more first
cavities and one or more second cavities;
wherein the second substrate comprises circuitry with first electroconductive pads in the first and second cavities, each
of the first and second cavities having at least one first electroconductive pad therein; and

wherein the integrated circuit package further comprises:
in each first cavity, at least one semiconductor die comprising an integrated circuit electroconductively coupled to at least
one first electroconductive pad in the first cavity; and

in each second cavity, at least one discrete electrical component electroconductively coupled to at least one first electroconductive
pad in the second cavity and comprising a conductive layer such that at least one of the following is true:

(i) the conductive layer is formed over a surface of the first substrate in the second cavity;
(ii) the conductive layer comprises at least a part of the surface of the first substrate in the second cavity.

US Pat. No. 9,824,974

INTEGRATED CIRCUIT ASSEMBLIES WITH RIGID LAYERS USED FOR PROTECTION AGAINST MECHANICAL THINNING AND FOR OTHER PURPOSES, AND METHODS OF FABRICATING SUCH ASSEMBLIES

INVENSAS CORPORATION, Sa...

5. An assembly comprising:
a first structure comprising first circuitry comprising one or more first contact pads at a top of the first structure;
one or more modules attached to a top surface of the first structure and electrically connected to at least one first contact
pad, at least one module comprising at least one semiconductor integrated circuit;

a first layer formed on the top surface of the first structure; and
a second layer overlying the first layer, wherein the second layer has a lower room-temperature elastic modulus than the first
layer;

wherein at least one of the following is true:
(a) the first layer is inorganic;
(b) the first layer is a material different from any material found at an interface between the first structure and at least
one of the one or more modules;

(c) the first layer covers all of that portion of said top surface which is not occupied by the one or more modules;
(d) the one or more modules comprise one or more first modules, the assembly comprising underfill between the first structure
and each first module, the underfill extending laterally beyond each first module, and the first layer covers all of that
portion of said top surface which is not occupied by the one or more modules and not covered by the underfill;

wherein the first structure is an interposer, and the first circuitry further comprises one or more second contact pads at
a bottom of the interposer;

wherein for a coefficient of thermal expansion (CTE) in an XY plane extending along the interposer, the XY CTE of the interposer
is closer to the XY CTE of the first layer than to the XY CTE of the second layer.

US Pat. No. 9,824,999

SEMICONDUCTOR DIE MOUNT BY CONFORMAL DIE COATING

Invensas Corporation, Sa...

1. A method for affixing a die onto a support, comprising: placing the die onto the support; providing a standoff between
a die attach surface of the die and a die mount surface of the support; and conformally coating to coat at least the die attach
surface of the die and the die mount surface of the support including forming a polymer in situ with vapor deposition in a
space between the die attach surface of the die and the die mount surface of the support.