US Pat. No. 9,508,660

MICROELECTRONIC DIE HAVING CHAMFERED CORNERS

Intel Corporation, Santa...

1. A microelectronic device, comprising:
a microelectronic die having an active surface, an opposing back surface, and at least two adjacent sides, wherein each of
the adjacent sides extend between the microelectronic die active surface and the microelectronic die back surface;

wherein the microelectronic die includes a chamfered corner comprising at least one chamfering side extending between the
at least two adjacent sides; and

wherein the microelectronic die includes a build-up layer comprising a plurality of dielectric layers with a plurality of
conductive traces between the plurality of dielectric layer and a plurality of conductive vias extending between the plurality
of conductive traces through the plurality of dielectric layers and wherein the at least one chamfering side extends between
the microelectronic die active surface and the microelectronic die back surface including extending through the build-up layer.

US Pat. No. 9,423,895

DUAL TOUCH SURFACE MULTIPLE FUNCTION INPUT DEVICE

Intel Corporation, Santa...

1. An apparatus comprising:
a first housing;
a second housing coupled to the first housing, the first housing and the second housing being rotatable between an open configuration
and a closed configuration; and

a touch input device supported by the first housing, wherein the touch input device includes a first touch surface layer configured
to have a first active touch surface responsive to the first housing and the second housing being in the open configuration,
and a second touch surface layer configured to have a second active touch surface responsive to the first housing and the
second housing being in the closed configuration, wherein the first active touch surface is configured to be smaller than
the second active touch surface, wherein the first active touch surface is configured to include a touchpad area, and wherein
the touchpad area is marked on the first touch surface layer by a change in surface texture on the first touch surface layer;
and

wherein the touchpad area includes a touchpad activation area smaller than the touchpad area, and wherein the touchpad area
is activated responsive to a user touch within the touchpad activation area; and

wherein the first touch surface layer is further configured to include a gesture area separate from the touchpad area and
positioned along an outside edge of the first touch surface layer and wherein the gesture area is separate from the touchpad
area by a distance greater than a width of the gesture area.

US Pat. No. 9,287,196

RESONANT CLOCKING FOR THREE-DIMENSIONAL STACKED DEVICES

Intel Corporation, Santa...

1. An apparatus comprising:
a stack including a plurality of integrated circuit die layers including at least a first die layer and an adjacent second
die layer, each die layer including an active metal side and an opposite RDL (re-distribution layer); and

a plurality of through silicon vias including a first set of through silicon vias formed through the first die layer and a
second set of through silicon vias formed through the second die layer, wherein each of the first set of through silicon vias
includes an inductive structure and each of the second set of through silicon vias includes a capacitive structure;

wherein the apparatus includes a plurality of resonant circuits to carry clock signals, each of the resonant circuits including
a first through silicon via of the first set of through silicon vias used as an inductive circuit element of the resonant
circuit and a second through silicon via of the second set of through silicon vias used as a capacitive circuit element of
the resonant circuit, the first through silicon via of each resonant circuit being coupled with the respective second through
silicon via of the resonant circuit via the RDL of the first die layer;

wherein each of the first set of through silicon vias is utilized both for transport of the clock signals between die layers,
including transport of clock signals from the first die layer to the second die layer, and for the generation of inductance
for the respective resonant circuit; and

wherein each of the resonant circuits is shared between the first die layer and the second die layer, a clock grid of the
first die layer resonating at a same frequency and being synchronous with a clock grid of the second die layer.

US Pat. No. 9,584,164

DIGITAL INTENSIVE HYBRID ADC/FILTER FOR LNA-FREE ADAPTIVE RADIO FRONT-ENDS

Intel Corporation, Santa...

1. A mixer-first receiver device of a mobile device comprising:
an antenna port configured to receive an analog signal;
a radio-frequency (RF)-frontend coupled to the antenna port and comprising a low noise amplifier free mixer-first front end
configured to selectively filter the analog signal for a bandwidth selection; and

a digital baseband interface coupled to the RF-frontend;wherein the RF-frontend comprises:
a coarse grain component, configured to generate a coarse grain frequency quantization for processing the analog signal to
a digital signal, comprising:

a mixer component, coupled to the antenna port, configured to down-convert the analog signal to a baseband signal and provide
the baseband signal to a signal path; and

a hybrid analog-to-digital converter (ADC) filtering component, coupled to the mixer component via the signal path, comprising
a plurality of switching capacitor arrays having switching capacitor banks configured to adaptively generate a discrete-time
filtering operation of the baseband signal and concurrently generate a conversion of the baseband signal to the digital signal
in a same clock period, based on one or more criteria.

US Pat. No. 9,286,224

CONSTRAINING PREFETCH REQUESTS TO A PROCESSOR SOCKET

Intel Corporation, Santa...

1. A processor comprising:
at least one core including one or more execution units, a first cache memory and a first cache control logic, wherein the
first cache control logic is to generate a first prefetch request to prefetch first data, wherein the first prefetch request
is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory, based on a first
indicator of the first prefetch request to indicate that the first prefetch request is to be handled in a single level of
a cache memory hierarchy.

US Pat. No. 9,173,221

APPARATUS, SYSTEM AND METHOD OF ESTABLISHING A WIRELESS BEAMFORMED LINK

INTEL CORPORATION, Santa...

1. An apparatus comprising:
a wireless communication controller to control a first wireless communication device to communicate millimeter-wave (mmWave)
signals with a second wireless communication device over a mmWave frequency band, the mmWave signals including signals transmitted
according to a plurality of different transmit (Tx) beamforming settings, said wireless communication controller is to control
said first wireless communication device to communicate feedback information, which is based on said mmWave signals, over
a non-mmWave frequency band, and to control said first wireless communication device to establish with said second wireless
communication device a beamformed link over said mmWave frequency band, said beamformed link using a Tx beamforming setting,
which is determined based on the feedback information.

US Pat. No. 9,563,579

METHOD, APPARATUS, SYSTEM FOR REPRESENTING, SPECIFYING AND USING DEADLINES

Intel Corporation, Santa...

1. An apparatus comprising:
a plurality of intellectual property (IP) blocks of a semiconductor device coupled to a fabric, wherein at least some of the
plurality of IP blocks include a deadline logic to generate a deadline value based at least in part on a global clock value
from the fabric to indicate a maximum latency before completion of a memory request and to communicate the memory request
to the fabric, the memory request including the deadline value.

US Pat. No. 9,332,643

INTERCONNECT ARCHITECTURE WITH STACKED FLEX CABLE

INTEL CORPORATION, Santa...

1. A stacked flex cable assembly comprising:
a first flex cable;
a second flex cable on the first flex cable;
a connector electrically coupled to the first flex cable and to the second flex cable;
a substrate electrically coupled to the connector;
the first flex cable including a plurality of electrically conductive vias electrically coupled to the second flex cable and
to the connector;

wherein the first flex cable is positioned between the connector and the second flex cable; and
wherein the connector is positioned between the substrate and the first flex cable.

US Pat. No. 9,067,958

SCALABLE AND HIGH YIELD SYNTHESIS OF TRANSITION METAL BIS-DIAZABUTADIENES

Intel Corporation, Santa...

1. A method for forming a transition metal bis-diazabutadiene comprising:
reacting in a first step, in the absence of a reducing agent, a diazabutadiene (DABD) with a transition metal halide and forming
a DABD-metal halide complex, wherein said DABD has the following structure:


wherein R1 is a C1-C12 alkyl group, amine or a C6-C18 aryl group and R2 is hydrogen, a C1-C10 alkyl, a C6-C18 aryl group, amino, C1-C12 alkylamino or a C2-C24 dialkylamino group;

said formed DABD-metal halide complex has the following structure:

wherein R1 is a C1-C12 alkyl group, amine or a C6-C18 aryl group and R2 is hydrogen, a C1-C10 alkyl, a C6-C18 aryl group, amino, C1-C12 alkylamino or a C2-C24 dialkylamino group, X is Cl or Br and M is a transition metal;

reacting in a second step said DABD-metal halide complex with additional DABD in the presence of a reducing agent and forming
a transition metal bis-diazabutadiene of the following structure:


wherein R1 is a C1-C12 alkyl group, amine or a C6-C18 aryl group and R2 is hydrogen, a C1-C10 alkyl, a C6-C18 aryl group, amino, C1-C12 alkylamino or a C2-C24 dialkylamino group and M is a transition metal;

wherein said yield of the transition metal bis-diazabutadiene is at or greater than 85%.

US Pat. No. 9,288,933

METAL INJECTION MOLDED HEAT DISSIPATION DEVICE

Intel Corporation, Santa...

1. A base plate for dissipating heat, wherein the base plate is coupled with micro-fins and is a metal injection molded plate,
and the base plate is coupled with an integrated heat spreader, wherein the integrated heat spreader and the micro fins dissipate
heat from the microelectronic package.

US Pat. No. 9,142,001

PERFORMANCE ALLOCATION METHOD AND APPARATUS

Intel Corporation, Santa...

1. An apparatus, comprising:
a graphics processing unit (GPU) to receive data from a processor and, based on the received data, to generate rendered frames;
circuitry to monitor a rate that frames are rendered and utilization of the GPU, wherein, based on the rate and the GPU utilization,
the circuitry to increase a frequency of the processor; and

wherein, based on the rate exceeding a threshold rate value and the GPU utilization falling below a threshold utilization
value, the circuitry to increase the frequency of the processor and to reduce a frequency of the GPU.

US Pat. No. 9,124,972

VOICE-BEARING LIGHT

Intel Corporation, Santa...

1. An apparatus, comprising:
an enclosure having an opening to a cavity;
a device to emit light at the bottom of the cavity; and
a cover over the light-emitting device to diffuse the light;
wherein an angle theta between a top surface of the cover and a projection line drawn from an edge of the opening to an opposite
edge of the light-emitting device enables light emitted through the opening to be visible to a speaker only when the speaker's
mouth is within a sensitivity region of a microphone.

US Pat. No. 9,153,583

III-V LAYERS FOR N-TYPE AND P-TYPE MOS SOURCE-DRAIN CONTACTS

Intel Corporation, Santa...

1. A semiconductor integrated circuit, comprising:
a substrate having a number of channel regions;
a gate electrode above each channel region, wherein a gate dielectric layer is provided between each gate electrode and a
corresponding channel region;

p-type source/drain regions comprising silicon in the substrate and adjacent to a corresponding channel region;
n-type source/drain regions comprising silicon in the substrate and adjacent to a corresponding channel region;
a doped III-V semiconductor material layer on at least a portion of the p-type source/drain regions and a portion of the n-type
source/drain regions; and

a metal contact on the III-V semiconductor material layer.

US Pat. No. 9,455,726

XOR (EXCLUSIVE OR) BASED TRIANGULAR MIXING FOR DIGITAL PHASE CONTROL

Intel Corporation, Santa...

1. A method for a linear control circuit, comprising:
generating a digital N-bit linear count;
routing the least significant M bits [(M?1):0] for linear control for fine delay mixing of a phase compensation loop;
routing the most significant (N?M) bits [(N?1):M] for linear control for coarse control of a delay chain for the phase compensation
loop; and

performing a bitwise XOR (exclusive OR) of bit M with each of bits [(M?1):0] to generate M linear control bits as the linear
control for fine delay mixing, the M linear control bits to generate a linear control count having a triangular contour, where
the linear control count repeatedly, continuously counts from 0 to (2M?1) to 0.

US Pat. No. 9,433,132

RECIRCULATING DIELECTRIC FLUID COOLING

Intel Corporation, Santa...

1. An apparatus for immersion cooling comprising:
a plurality of trays, each tray of the plurality of trays to hold one or more circuit boards and having a first opening to
allow dielectric fluid to be injected into the tray, and a second opening, to allow for escape of the dielectric fluid out
of the tray;

a fluid circulation system including:
a catchment area, disposed below the plurality of trays, to collect the dielectric fluid that escapes from the plurality of
trays; and

a distribution manifold having a plurality of injection ports disposed above or adjacent to respective trays of the plurality
of trays, the distribution manifold coupled with the catchment area, to deliver the dielectric fluid collected in the catchment
area back to the plurality of trays via the injection ports; and

a pump coupled with the catchment area and the distribution manifold, the pump to deliver the dielectric fluid collected in
the catchment area to the distribution manifold at a rate equal to or greater than a rate at which the dielectric fluid escapes
from the plurality of trays.

US Pat. No. 9,320,149

BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING A RELEASE LAYER

Intel Corporation, Santa...

1. An apparatus, comprising:
a first substrate;
a release layer coupled with the first substrate above the first substrate;
a resin layer coupled with the release layer above the release layer;
a metal film coupled with the resin layer, above the resin layer at a bottom surface of the metal film, the metal film including
a cavity therein, the cavity extending from a top surface of the metal film through the bottom surface of the metal film to
the resin layer;

a microelectronic die coupled with the metal film in the cavity; and
a first bumpless buildup layer substrate coupled with an active surface of the die above the die
wherein the first substrate includes a first substrate cavity extending from a top surface of the first substrate and into
the first substrate, the release layer is situated in the first substrate cavity, and the resin layer is situated in the first
substrate cavity, and

wherein a top surface of the first resin layer is generally co-planar with a top surface of the first substrate.

US Pat. No. 9,288,813

MULTI-RADIO CONTROLLER AND METHODS FOR PREVENTING INTERFERENCE BETWEEN CO-LOCATED TRANSCEIVERS

Intel Corporation, Santa...

1. User Equipment (UE) comprising:
a multi-radio controller for controlling a Wi-Fi transceiver and a LTE transceiver, the multi-radio controller configured
to:

determine a duration of a transmission opportunity (TXOP) based on an active period interval of the LTE transceiver;
configure a triggering frame to indicate that the Wi-Fi transceiver is granting permission to an access point to send data
in accordance with a reverse direction (RD) protocol, the triggering frame to indicate at least a duration of the TXOP; and

transmit the triggering frame within the TXOP immediately after an active period of the LTE transceiver,
wherein the duration of he TXOP is determined prior to configuration and transmission of the triggering frame.

US Pat. No. 9,141,454

SIGNALING SOFTWARE RECOVERABLE ERRORS

Intel Corporation, Santa...

1. A processor comprising:
a first unit to detect a poison error;
a programmable indicator to determine whether the poison error is signaled as a machine check error or as one of a fault and
a system management interrupt; and

a second unit to signal the poison error as one of a fault and a system management interrupt responsive to the programmable
indicator and to store a continuability indicator to indicate whether an instruction thread including an instruction that
caused the poison error is continuable.

US Pat. No. 9,383,803

PRIORITY BASED APPLICATION EVENT CONTROL (PAEC) TO REDUCE POWER CONSUMPTION

Intel Corporation, Santa...

1. An apparatus comprising:
a processor; and
logic to allow one or more of a plurality of applications to be executed based on policy information, corresponding to the
plurality of applications, and after the processor is to exit a low power consumption state,

wherein the policy information is to indicate which one of the plurality of applications is to be awakened after the processor
exits the low power consumption state, wherein the logic is to prioritize which of the one or more of the plurality of applications
are to be allowed to wake the processor from the low power consumption state.

US Pat. No. 9,372,524

DYNAMICALLY MODIFYING A POWER/PERFORMANCE TRADEOFF BASED ON PROCESSOR UTILIZATION

Intel Corporation, Santa...

1. A processor comprising:
a plurality of cores and a power controller, the power controller including a logic having circuitry to dynamically update
a power management policy for a system including the processor from a power saving biased policy to a performance biased policy
when a utilization of the processor exceeds a threshold level, wherein the logic is to dynamically tune a loadline from the
power saving biased policy to the performance biased policy when a ratio of a duration of a maximum performance state residency
of the plurality of cores during an evaluation interval to a duration of an active state residency of the plurality of cores
during the evaluation interval exceeds the threshold level.

US Pat. No. 9,154,157

SEARCH UNIT TO ACCELERATE VARIABLE LENGTH COMPRESSION/DECOMPRESSION

Intel Corporation, Santa...

1. A method for performing efficient operations to compress or decompress data, the method comprising:
receiving, at a processor core, data comprising a table to be searched;
sorting, at the processor core, the table data by a search column;
populating, in a search unit within the processor core, a look-up table with the sorted table data;
receiving, at the search unit, data for processing, wherein the data for processing comprises a plurality of symbols;
for each symbol in the data for processing:
searching, with the search unit, the look-up table for a match to the symbol;
identifying, with the search unit, a matching row of the look-up table;
adding, at the processor core, a portion of the matching row to a data stream for output;
transmitting, from the search unit, the output data stream to a receiver, wherein the output data represents a transformation
of the data for processing into compression values or decompression values corresponding to the data for processing.

US Pat. No. 9,155,082

INTERFERENCE MITIGATION IN THE CONTEXT OF HETEROGENEOUS NETWORKS WITH COORDINATED TRANSMISSION POINTS WITH A COMMON TRANSMISSION POINT IDENTITY

INTEL CORPORATION, Santa...

1. A computer program product comprising a non-transitory computer usable medium having a computer readable program code embodied
therein, the computer readable program code adapted to be executed to implement instructions for a method for mitigating interference
across clusters of wireless transmission points, comprising:
configuring, at a Down Link (DL) transmission point, a Relative Narrowband Transmit Power (RNTP) message indicating a first
set of resource blocks at which the DL transmission point is set to transmit with a power that is one of at a power threshold
and above a power threshold and a second set of resource blocks at which the DL transmission point is set to transmit with
a power less than the power threshold;

identifying an attribute of the DL transmission point corresponding to the RNTP message distinct from a common Cell-IDentification
(Cell-ID) of a Coordinated Multi Point (CoMP) cluster to which the DL transmission point pertains, the common Cell-ID also
pertaining to at least one other transmission point in the CoMP cluster; and

sending the RNTP message via a backhaul link to at least one additional transmission point to enable at least one additional
transmission point to schedule a wireless mobile device near a boundary for the DL transmission point on a resource block
within a same frequency range as a resource block for which the DL transmission point is set to transmit with a power of less
than the power threshold.

US Pat. No. 9,116,849

COMMUNITY-BASED DE-DUPLICATION FOR ENCRYPTED DATA

Intel Corporation, Santa...

15. A method for retrieving content from a content data server in a data de-duplication system, the method comprising:
receiving, by a computing device and from the content data server, (i) encrypted blocks of a fragmented file, (ii) a keyed
hash associated with each of the encrypted blocks, and (iii) a member identification for each encrypted block that identifies
a computing device that has previously stored the corresponding encrypted block on the content data server;

receiving, by the computing device, an encrypted file decryption key for each of the encrypted blocks from a key server in
response to transmitting the keyed hash and the member identification associated with each corresponding encrypted block to
the key server;

transmitting, by the computing device, each received encrypted file decryption key that is encrypted with a member encryption
key corresponding to another member device, other than the computing device, to the another member device for decryption with
a member decryption key of the another member device;

receiving, by the computing device and from the another member device, the decrypted file decryption key corresponding to
the each received encrypted file decryption key that is encrypted with the member encryption key of the another member device;

decrypting, by the computing device, each encrypted file decryption key that is encrypted with a member encryption key of
the computing device with a corresponding member decryption key of the computing device; and

decrypting, by the computing device, each of the encrypted blocks using the decrypted file decryption key associated with
each corresponding encrypted block.

US Pat. No. 9,426,914

FILM INSERT MOLDING FOR DEVICE MANUFACTURE

Intel Corporation, Santa...

1. A method of constructing a device comprising:
forming a film into a shape that defines an interior region;
disposing an electronic component within the interior region of the film;
incorporating an additive into a thermo-set resin, wherein the additive is configured to absorb, store and distribute heat
generated by the electronic component during operation of the device, and wherein the resin includes a castable material;

substantially filling the interior region of the film with the thermo-set resin, wherein the thermo-set resin encompasses
the electronic component; and

hardening the thermo-set resin.

US Pat. No. 9,326,422

TECHNIQUES FOR COMPUTING DEVICE COOLING USING A SELF-PUMPING FLUID

INTEL CORPORATION, Santa...

1. An apparatus, comprising:
one or more heat-generating components;
a housing forming a cavity including the one or more heat-generating components;
a self-pumping cooling fluid arranged in the cavity, the self-pumping cooling fluid comprising a slurry of microencapsulated
phase change material (mPCM) particles suspended in a working fluid and arranged to circulate throughout the cavity; and

a fluid container arranged inside the cavity to contain the self-pumping cooling fluid, the fluid container arranged to funnel
the mPCM particles to a position near the one or more heat-generating components.

US Pat. No. 9,204,378

WIRELESS NETWORK CONNECTIVITY ENHANCEMENTS

Intel Corporation, Santa...

1. A computing device, comprising:
processing circuitry to maintain channel information for wireless channels used by one or more preferred wireless networks;
a wireless network adapter to perform a reduced wireless network scan, wherein the reduced wireless network scan uses the
channel information to scan the wireless channels used by the preferred wireless networks and to refrain from scanning other
wireless channels used by non-preferred wireless networks; and

wherein the reduced wireless network scan disregards channel information from a subset of the preferred wireless networks
based on at least one of location, computing device usage, or network characteristics, to scan the wireless channels used
by preferred wireless networks not in the subset and to refrain from scanning other wireless channels used by preferred wireless
networks in the subset.

US Pat. No. 9,152,420

BITSTREAM BUFFER MANIPULATION WITH A SIMD MERGE INSTRUCTION

Intel Corporation, Santa...

1. A system comprising:
a processor comprising:
a plurality of registers;
an instruction decoder to decode a shift right merge instruction indicating a first 32-bit source operand and a second 32-bit
source operand, the first 32-bit source operand including a first four 8-bit byte data elements, the second 32-bit source
operand including a second four 8-bit byte data elements; and

an execution unit coupled with the instruction decoder and the plurality of registers, the execution unit in response to the
shift right merge instruction to:

shift the second 32-bit source operand right by one byte;
merge a least significant 8-bit byte data element of the first 32-bit source operand into a most significant byte position
of the shifted second 32-bit source operand to generate a result; and

store the result in a 32-bit destination indicated by the shift right merge instruction;
a Bluetooth universal asynchronous receiver/transmitter (UART) interface coupled to communicate with the processor;
a universal serial bus (USB) interface coupled to communicate with the processor;
a synchronous dynamic random access memory (SDRAM) control interface coupled to communicate with the processor; and
a flash interface coupled to communicate with the processor.

US Pat. No. 9,059,715

VOLTAGE LEVEL SHIFT WITH INTERIM-VOLTAGE-CONTROLLED CONTENTION INTERRUPT

Intel Corporation, Santa...

1. A system, comprising:
a voltage level shift circuit to shift input logical states from an input voltage swing to an output voltage swing;
a controllable contention interrupter to selectively interrupt contention within the voltage level shift circuit; and
an interrupt controller to shift the input logical states from the input voltage swing to an interim voltage swing, and control
the contention interrupter with the logical states having the interim voltage swing;

wherein a lower limit of the interim voltage swing is equal to a lower limit of the output voltage swing; and
wherein an upper limit of the interim voltage swing is equal to an upper limit of the input voltage swing.

US Pat. No. 9,184,502

ANTENNA INTEGRATED INTO A TOUCH SENSOR OF A TOUCHSCREEN DISPLAY

Intel Corporation, Santa...

1. A mobile computing device, comprising:
a casing;
a radio frequency transmitter disposed inside the casing;
a radio frequency receiver disposed inside the casing;
a touch-screen display disposed inside the casing and comprising:
a display screen;
a touch sensor disposed adjacent the display screen and comprising:
a first and second layer, wherein the first and second layers comprise a metalized border area at least partially bordering
a transparent conductive layer, the metalized border area forming electrodes for detecting a location of a touch on the touch
screen display, the first layer disposed above the second layer such that the metalized border area of the first layer faces
the metalized border area of the second layer; and

a far-field antenna, formed from first and second portions of the metalized border area from the first and second layers respectively,
wherein the far-field antenna is operatively coupled with the radio frequency transmitter and the radio frequency receiver.

US Pat. No. 9,143,944

SECURE PEER-TO-PEER NETWORK SETUP

Intel Corporation, Santa...

1. A network apparatus comprising:
a hardware processor to communicate with a first master device, receive an image associated with a user of the first master
device and receive encoded data in a two-dimensional (2D) barcode, wherein the encoded data comprise at least user information
associated with the first master device including a user identifier, a device identifier, or both; and

network information including a network identifier, a password, and a profile lifetime value, wherein the password is a share
secret among three or more devices of a peer-to-peer network if the peer-to-peer network is fully connected rather than a
star topology peer-to-peer network; and

a display unit operable to display at least part of the user information and the network information encoded in the 2D barcode
to a first user and the image for the user to verify an identity of the first master device, wherein the processor is operable
to initiate a peer-to-peer network setup with the first master device based at least on a response from the first user verifying
the network information encoded in the 2D barcode.

US Pat. No. 9,054,742

ERROR AND ERASURE DECODING APPARATUS AND METHOD

Intel Corporation, Santa...

11. A method, comprising:
generating, by a memory controller, a plurality of partial syndromes for a codeword;
generating, by the memory controller, an erasure locator polynomial for the codeword;
generating, by the memory controller, modified partial syndromes based at least in part on the plurality of partial syndromes
and the erasure locator polynomial of the codeword; and

generating, by the memory controller, an error locator polynomial using no more than last (2t?B) partial syndromes of the
modified partial syndromes, for error and erasure decoding of the codeword, wherein t is a number of correctable errors, and
B is a number of erasures.

US Pat. No. 9,245,694

SOLID-STATE SUPERCAPACITOR

The Regents of the Univer...

1. A solid-state supercapacitor comprising:
a first electrode comprising a first conductive supporting structure and a first array of conductive quasi-one-dimensional
structures that extend from the first conductive supporting structure;

a second electrode comprising a second conductive supporting structure and a second array of conductive quasi-one-dimensional
structures that extend from the second conductive supporting structure; and

a solid-state ionogel structure disposed between the first electrode and the second electrode, wherein:
the solid-state ionogel structure prevents direct electrical contact between the first electrode and the second electrode;
and

the solid-state ionogel structure substantially fills voids within and between the first array of conductive quasi-one-dimensional
structures and the second array of conductive quasi-one-dimensional structures.

US Pat. No. 9,198,121

SYSTEMS AND METHODS FOR SELECTIVE SCANNING BASED ON RANGE AND MOVEMENT

INTEL CORPORATION, Santa...

1. A method of scanning for access points (APs), the method comprising:
measuring a variable related to range and movement of a mobile device, the mobile device executing code to perform the measuring,
the variable including received signal strength indications (RSSI);

analyzing whether the variable is significant enough to trigger a first scan request, the mobile device executing code to
perform the analyzing;

scanning for APs in response to the first scan request, the mobile device executing code to perform the scanning;
wherein analyzing further includes that when the RSSI is greater than a first range threshold, a scan interval is set to refrain
from scanning and the mobile device waits for further received signal strength measurements.

US Pat. No. 9,489,198

METHOD AND APPARATUS FOR PERFORMING LOGICAL COMPARE OPERATIONS

Intel Corporation, Santa...

1. A method comprising:
receiving in a processor, a first single instruction multiple data (SIMD) coprocessor comparison instruction to compare a
first plurality of packed single-precision floating point (SPFP) data elements with a second plurality of SPFP data elements;

receiving in a processor, a second SIMD coprocessor comparison instruction to compare a third plurality of packed data elements
with a fourth plurality of packed data elements; and

responsive to said second SIMD coprocessor comparison instruction, setting at least one bit of data to indicate a result of
the second SIMD coprocessor comparison instruction, wherein the at least one bit of data is to control operation of a branch
instruction.

US Pat. No. 9,369,912

COMMUNICATION PATH SWITCHING FOR MOBILE DEVICES

INTEL CORPORATION, Santa...

1. User equipment (UE) comprising:
logic, at least a portion of which comprises circuitry, to:
exchange second communication path availability information between the UE and another UE, wherein the exchange is to send
and receive session initiation protocol (SIP) messages comprising the second communication path availability information over
a first communication path;

change a communication session by re-routing traffic flows to the second communication path based on the second communication
path availability information;

in response to changing the communication session, send to and receive from the other UE data corresponding to a first traffic
flow over the second communication path, wherein the first traffic flow comprises an existing traffic flow and wherein the
data of the existing traffic flow is switched from the first communication path to the second communication path;

in response to determining that the UE is outside a proximity services (ProSe) communication path range of the other UE, initiate
re-routing of traffic flows back to the first communication path.

US Pat. No. 9,158,705

STRIDE-BASED TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHING WITH ADAPTIVE OFFSET

Intel Corporation, Santa...

1. A processing device, comprising:
a data prefetcher to generate a data prefetch address based on at least one of a linear address, a stride, or a prefetch distance,
the data prefetch address associated with a data prefetch request;

a translation lookaside buffer (TLB) prefetch address computation component communicably coupled to the data prefetcher, the
TLB prefetch address computation component to generate a TLB prefetch address based on at least one of the linear address,
the stride, the prefetch distance, or an adaptive offset; and

a cross page detection component communicably coupled to the data prefetcher and the TLB prefetch address computation component,
the cross page detection component to:

determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address;
and

cause a TLB prefetch request to be written to a TLB request queue based on determining that the data prefetch address or the
TLB prefetch address cross the page boundary associated with the linear address, the TLB prefetch request for translation
of an address of a linear page number (LPN) that is based on at least one of the data prefetch address or the TLB prefetch
address.

US Pat. No. 9,129,817

MAGNETIC CORE INDUCTOR (MCI) STRUCTURES FOR INTEGRATED VOLTAGE REGULATORS

Intel Corporation, Santa...

1. A semiconductor package, comprising:
a package substrate;
a semiconductor die coupled to a first surface of the package substrate, the semiconductor die having a first plurality of
metal-insulator-metal (MIM) capacitor layers thereon; and

a magnetic core inductor (MCI) die coupled to a second surface of the package substrate, the MCI die comprising one or more
slotted inductors and having a second plurality of MIM capacitor layers thereon.

US Pat. No. 9,119,313

PACKAGE SUBSTRATE WITH HIGH DENSITY INTERCONNECT DESIGN TO CAPTURE CONDUCTIVE FEATURES ON EMBEDDED DIE

INTEL CORPORATION, Santa...

1. A package assembly comprising:
a package substrate having a die mounted on a surface of the package substrate;
a bridge embedded inside the package substrate, the bridge including a bridge substrate, wherein the bridge substrate includes
a first surface and a second surface opposite the first surface, wherein the first surface is disposed closer to the surface
of the package substrate than the second surface, and wherein a distance between the first and second surfaces defines a substrate
thickness; and

an interconnect structure including a substantially conically shaped via extending through the first surface into the bridge
substrate at a depth that is less than half of the substrate thickness, to interface with a conductive feature disposed on
or beneath the first surface of the bridge substrate, wherein the via is filled with a conductive material to form a conductive
pillar on top of the via, wherein the conductive pillar protrudes through the surface of the package substrate, and wherein
a diameter of the conductive pillar is smaller than a diameter of a base of the conically shaped via formed on the surface
of the package substrate,

wherein the interconnect structure is to route electrical signals between the conductive feature and the die mounted on the
surface of the package substrate.

US Pat. No. 9,112,669

FEEDBACK SCHEME FOR MU-MIMO

INTEL CORPORATION, Santa...

1. A method to manage feedback in a communication system, the method comprising:
sending a sounding package to a mobile station of a group of mobile stations over an antenna array of a multiple user multiple
input multiple output (MU-MIMO) system, the sounding package to include multiple feedback parameters for feedback from the
mobile station, the feedback parameters to comprise a feedback type and a feedback dimension; and

receiving a feedback matrix from the mobile station in accordance with the feedback type and the feedback dimension of the
sounding package.

US Pat. No. 9,451,696

EMBEDDED ARCHITECTURE USING RESIN COATED COPPER

INTEL CORPORATION, Santa...

1. An assembly comprising:
a carrier structure;
a resin coated copper layer positioned on the carrier structure, the resin coated copper layer including a first layer comprising
a resin and a second layer comprising copper, the first layer bonded to the second layer, the first layer positioned between
the carrier structure and the second layer;

an opening extending through the second layer of the resin coated copper layer;
a die positioned in the opening, the die positioned on the first layer comprising a resin, the die including a first surface
and a second surface opposite the first surface, the first surface positioned between the carrier structure and the second
surface, the first surface defining a total first surface area, wherein the first layer comprising a resin is positioned between
the first surface and the carrier structure across the total first surface area and

a plurality of dielectric layers and metal interconnections positioned on the second layer and on the die.

US Pat. No. 9,451,716

SERVICEABLE CHASSIS FOR DEVICES

Intel Corporation, Santa...

1. A serviceable chassis, comprising:
a first housing, wherein the first housing includes a locking arm; and
a second housing, wherein the second housing includes:
a locking cam; and
a cord, wherein the cord is attached to the locking cam and can rotate the locking cam to engage and disengage the locking
arm and couple and uncouple the first housing to the second housing.

US Pat. No. 9,147,638

INTERCONNECT STRUCTURES FOR EMBEDDED BRIDGE

Intel Corporation, Santa...

1. A package assembly comprising:
a bridge interconnect structure including a die contact and electrical routing features to route electrical signals between
a first die and a second die;

an electrically insulative layer disposed on the bridge interconnect structure; and
a die interconnect of the first die or the second die disposed on and electrically coupled with the die contact, the die interconnect
including a pillar structure that extends through the electrically insulative layer and protrudes beyond a surface of the
electrically insulative layer.

US Pat. No. 9,124,457

FREQUENCY DOMAIN EQUALIZATION FOR WIRELESS COMMUNICATION

INTEL CORPORATION, Santa...

1. An apparatus comprising:
a pre-decoding equalizer to determine a plurality of filter weights by applying both a blind-equalization and a least-mean-squares
(LMS) equalization to a wireless communication signal received over a wireless communication channel;

a channel estimator to estimate a channel frequency response of the channel based on the filtering weights, the channel frequency
response including a plurality of channel coefficients corresponding to a respective plurality of channel subcarriers, the
plurality of channel coefficients satisfying a criterion relating to a peak threshold and a width threshold; and

a turbo-equalization scheme including a decoder to decode the wireless communication signal and a turbo equalizer to equalize
the decoded wireless communication signal using the estimated channel frequency response.

US Pat. No. 9,402,264

METHODS TO TRANSPORT INTERNET TRAFFIC OVER MULTIPLE WIRELESS NETWORKS SIMULTANEOUSLY

Intel Corporation, Santa...

1. A wireless communication device, comprising:
at least two receivers that are configured to receive a respectively selected portion of a downlink data flow signal from
a corresponding different wireless network, the downlink data flow signal comprising a single downlink data flow being associated
with an Internet-Protocol-based services application, and

a processor coupled to the at least two receivers and configured to combine the respectively received portions of the downlink
data flow signal to form the single downlink data flow associated with the Internet-Protocol-based services application, and
providing the formed single downlink data flow to a client entity associated with the processor;

wherein a first one of the at least two receivers is configured to receive a first selected portion of the downlink data flow
comprising a first group of data packets from a first wireless network, the first group of data packets comprising a first
predetermined number of consecutively arranged data packets, and

wherein a second one of the at least two receivers is configured to receive a second selected portion of the downlink data
flow comprising a second group of data packets from a second wireless network, the second group of data packets comprising
a second predetermined number of consecutively arranged data packets, and

wherein the first one and the second one of at least two receivers are configured to receive the first group of data packets
and the second group of data packets as an alternating arrangement in the downlink data flow.

US Pat. No. 9,313,811

WIRELESS STATION AND METHODS FOR TOF POSITIONING USING REVERSE-DIRECTION GRANT

Intel Corporation, Santa...

1. A method for time-of-flight (ToF) positioning performed by an initiating station, the method comprising:
transmitting a message M1 carrying a high-throughput control (HTC) field, the HTC field including a reverse direction grant (RDG) indication, the RDG
indication granting permission to a responding station to send information back to the initiating station, the message M1 being a timing measurement action frame;

receiving an acknowledgement (ACK) frame to acknowledge receipt of the message M1, the ACK frame carrying an HTC field that includes an indication to indicate whether a separate frame is to follow the ACK
frame; and

receiving a message M2 from the responding station, the message M2 including timing measurement information from at least at one of a current and a previous ToF message exchange.

US Pat. No. 9,215,649

TECHNIQUES FOR ASSISTED NETWORK ACQUISITION

INTEL CORPORATION, Santa...

1. An apparatus, comprising:
a wireless transceiver;
a processor circuit communicatively coupled to the wireless transceiver; and
a memory unit communicatively coupled to the processor circuit, the memory unit to store a network locator application operative
on the processor circuit to locate a network for a remote device, the network locator application comprising:

a network detector component operative to receive network information for multiple wireless networks via the wireless transceiver;
a network selector component operative to select a target network for the remote device from the multiple wireless networks
based on the network information, receive one or more candidate network identifiers from the network detector component, compare
the candidate network identifiers with a list of remote network identifiers representing wireless networks accessible by the
remote device, detect a match between a candidate network identifier and a remote network identifier, and select a target
network identifier for the target network corresponding to the matched network identifiers; and

a network notifier component operative to send network configuration information for the target network to the remote device.

US Pat. No. 9,210,024

METHODS AND ARRANGEMENTS FOR CHANNEL UPDATES IN WIRELESS NETWORKS

Intel Corporation, Santa...

1. A method to perform channel updates with shifting pilot tones, the method comprising:
receiving an orthogonal frequency division multiplexing transmission with pilot tones shifting locations periodically between
symbol indices of orthogonal frequency division multiplexing symbols;

determining channel information from the pilot tones that excludes channel information for the pilot tones that are located
adjacent to part of a transmission bandwidth, which is not used to transmit data tones, comprising a direct current tone or
edge tones; and

performing channel updates based upon the channel information.

US Pat. No. 9,485,734

WIRELESS COMMUNICATION SYSTEM METHOD FOR SYNCHRONIZING BLUETOOTH DEVICES BASED ON RECEIVED BEACON SIGNALS

Intel Corporation, Santa...

7. A system to synchronize a Low-Energy Bluetooth (BLE) device, comprising:
a memory;
a first radio to communicate in compliance with a first wireless communication protocol and a second radio to communicate
in compliance with second wireless communication protocol;

one or more processors and circuitry to synchronize communication with another apparatus in compliance with a first wireless
communication protocol, the circuitry configured to:

determine a first time-offset value from an Access Point broadcast beacon signal in compliance with a second wireless communication
protocol;

select an event time window as a function of the first time-offset value; and
conduct communication with the other apparatus in compliance with the first wireless communication protocol during the event
time window;

wherein the circuitry is further configured to determine the first time-offset as a function of one or more least significant
bits of a shared time data (N0) communicated by the broadcast beacon signal.

US Pat. No. 9,402,228

MECHANISMS FOR ROAMING BETWEEN 3GPP OPERATORS AND WLAN SERVICE PROVIDERS

Intel Corporation, Santa...

1. One or more non-transitory computer-readable media comprising instructions to cause a user equipment (UE), when executed
by one or more processors of the UE, to:
compare a network access identifier (NAI) realm received from an access point (AP) of a wireless local access network (WLAN)
to one or more selection policy parameters of a third generation partnership project (3GPP) network, wherein the NAI realm
identifies the WLAN as associated with a service provider of the 3GPP network; and

associate with the AP based on the comparison.

US Pat. No. 9,390,795

INTEGRATED SETBACK READ WITH REDUCED SNAPBACK DISTURB

Intel Corporation, Santa...

1. An apparatus comprising:
read circuitry, to apply a read voltage to a phase change memory (PCM) cell;
setback circuitry coupled to the read circuitry, to apply a setback pulse to the PCM cell in response to the application of
the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than
a second period of time for a regular set pulse that is to transition the PCM cell from an amorphous state to a crystalline
state; and

sense circuitry coupled to the setback circuitry, to sense, concurrently with application of the setback pulse, whether the
PCM cell is in the amorphous state or the crystalline state.

US Pat. No. 9,369,856

SERVICE OF AN EMERGENCY EVENT BASED ON PROXIMITY

Intel Corporation, Santa...

1. A computing device associated with a non-emergency vehicle and configured to facilitate communication of an emergency event
to an emergency service, the computing device comprising:
an emergency event manager configured to:
receive, from at least one component of the non-emergency vehicle, an indication that an emergency event has occurred at the
non-emergency vehicle;

locate at least one mobile computing device in proximity to the non-emergency vehicle; and
send a notification of the emergency event over a network for receipt by the at least one mobile computing device for transmission
by the at least one mobile computing device over an emergency communications channel to at least one emergency responder.

US Pat. No. 9,313,779

UPLINK CONTROL INFORMATION TRANSMISSION WITH LARGE NUMBER OF BITS

Intel Corporation, Santa...

1. An apparatus comprising:
uplink control information (UCI) circuitry to generate UCI that includes one or more sets of periodic channel state information
(p-CSI) that respectively correspond with one or more serving cells or with one or more CSI processes;

feedback circuitry coupled with the UCI circuitry, the feedback circuitry to:
determine a number of encoded bits to convey the UCI;
select an encoding scheme from a plurality of encoding schemes based on the number of encoded bits and a number of the one
or more serving cells; and

encode the UCI with the encoding scheme for transmission using physical uplink control channel (PUCCH) format 3.

US Pat. No. 9,270,698

FILTER FOR NETWORK INTRUSION AND VIRUS DETECTION

Intel Corporation, Santa...

1. A method to perform string matching for network packet inspection, the method comprising:
configuring a set of H slice circuits, each ith slice circuit of the set of H slice circuits being configured to perform the steps of:

independently storing an ith input window of Wi bytes of data from an input data stream;

padding the Wi bytes of data if necessary, and multiplying the Wi bytes of data by a Galois-field polynomial modulo an irreducible Galois-field polynomial combined with a randomly generated
polynomial multiplier to generate an ith hash index;

accessing a storage location of a memory corresponding to the ith hash index to generate an ith slice-hit signal of a set of H slice-hit signals; and

providing the ith slice-hit signal to an AND-OR logic array as one of the set of H slice-hit signals; and

configuring the AND-OR logic array to receive the set of H slice-hit signals and to combine the set of H slice-hit signals
into a match result.

US Pat. No. 9,220,081

ACCESS POINT LOCATION DISCOVERY IN UNMANAGED NETWORKS

Intel Corporation, Santa...

1. A method for Access Point location discovery in an unmanaged network, the method comprising:
scanning, by an interested Access Point (AP), a neighboring AP for a Media Access Control (MAC) address and radio channel
belonging to the neighboring AP;

querying, by the interested AP from the neighbor AP, a location of the neighboring AP using the scanned MAC address and radio
channel;

receiving, at the interested AP from the neighboring AP, the location of the neighboring AP;
performing, by the interested AP, a Fine Timing Measurement (FTM) by calculating a Time-of-Flight (TOF) distance measurement;
validating, at the interested AP, the received location of the neighboring IP against the ToF distance measurement; and
assigning a reliability grade to a location according to the number of times the same AP was reported with the same location
by different APs in a network.

US Pat. No. 9,081,709

VIRTUALIZABLE AND FORWARD-COMPATIBLE HARDWARE-SOFTWARE INTERFACE

Intel Corporation, Santa...

1. An I/O apparatus comprising a non-transitory machine-readable medium to record functional descriptive material, which if
accessed by a machine causes the machine to:
queue a plurality of commands, from a first function driver that is either one of a physical function driver or a virtual
function driver, into a first command queue;

fetch a first command of the plurality of commands from the first command queue to a device firmware in the I/O apparatus;
access an actions table stored on the I/O apparatus with the device firmware to determine a type of action, through which
the first function driver is permitted to perform the first command;

wherein upon determining the type of action, through which the first function driver is permitted to perform the first command,
if the type of action is a correction, said functional descriptive material further causes the machine to:

trap the first command;
correct the first command to generate a corrected command; and
queue a first event from the device firmware into a first event queue responsive to the first command.

US Pat. No. 9,491,881

MICROELECTRONIC SOCKET COMPRISING A SUBSTRATE AND AN INSULATIVE INSERT MATED WITH OPENINGS IN THE SUBSTRATE

Intel Corporation, Santa...

1. A microelectronic socket, comprising:
a conductive socket substrate having a first surface, a second surface, and a plurality of openings extending from the conductive
socket substrate first surface to the conductive socket second surface, wherein the conductive socket substrate comprises
a non-conductive core and a conductive material on an exterior surface of the non-conductive core;

an insulative insert comprising a base portion having a first surface and a second surface, and a plurality of projections
extending from the insulative insert base portion second surface, wherein the insulative insert is mated with the conductive
socket substrate such that each of the plurality of insulative insert projections resides within a corresponding conductive
socket substrate opening;

a plurality of vias, wherein at least one of the plurality of vias extends from the insulative base portion first surface
through one of the plurality of insulative insert projections;

a plurality of contacts, wherein at least one of the plurality of contacts resides within at least one of the plurality of
vias; and

wherein the conductive socket substrate has a thickness defined between the conductive socket first surface and the conductive
socket second surface and wherein at least one of the plurality of insulative insert projections has a height less than the
conductive socket substrate thickness defining a recess, and further comprising a second conductive material disposed within
the recess to form an electrical connection between one of the contacts and the conductive socket substrate.

US Pat. No. 9,398,699

DUAL EPOXY DIELECTRIC AND PHOTOSENSITIVE SOLDER MASK COATINGS, AND PROCESSES OF MAKING SAME

Intel Corporation, Santa...

1. An apparatus comprising:
a microelectronic device mounting substrate that includes a bond pad with a side wall thereof and an upper surface thereof;
a dielectric first layer disposed on the microelectronic device mounting substrate, wherein the dielectric first layer abuts
the bond pad side wall and a portion of the bond pad upper surface;

a solder mask second layer disposed on the dielectric first layer;
a uniform recess through the solder mask second layer and the dielectric first layer that exposes the portion of the bond
pad upper surface, wherein the uniform recess comprises the dielectric first layer having a sidewall that has a pitch angle
and the solder mask second layer having a sidewall that has a pitch angle, wherein the sidewall of the solder mask second
layer extends completely through the solder mask second layer to the sidewall of the dielectric first layer, wherein the sidewall
of the dielectric first layer extends from the sidewall of the solder mask second layer to the bond pad upper surface, and
wherein the sidewall pitch angle of the dielectric first layer differs from the sidewall pitch angle of the solder mask second
layer;

an electrical connection disposed in the recess and in physical contact with the sidewall of the dielectric first layer and
with the sidewall of the solder mask second layer, and in electrical contact with the bond pad; and

a microelectronic device including an active surface, wherein the active surface faces the bond pad upper surface, and wherein
the active surface is bonded to the electrical connection.

US Pat. No. 9,280,507

HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER

INTEL CORPORATION, Santa...

1. An apparatus comprising:
a synchronization counter to locally align signaling by a particular device with signaling in a system comprising one or more
other devices communicatively coupled by an interconnect; and

a layered stack comprising physical layer logic, link layer logic, and protocol layer logic, wherein the physical layer logic
is implemented at least in part in hardware and is to:

synchronize a reset of the synchronization counter to an external deterministic signal globally maintained for the system;
and

synchronize entry into a link transmitting state with the deterministic signal based on the synchronization counter.

US Pat. No. 9,408,216

DYNAMIC BANDWIDTH ALLOCATION TO TRANSMIT A WIRELESS PROTOCOL ACROSS A CODE DIVISION MULTIPLE ACCESS (CDMA) RADIO LINK

Intel Corporation, Santa...

1. An apparatus comprising:
circuitry to establish a network layer connection with a subscriber unit;
circuitry to allocate a plurality of code division multiple access (CDMA) channels for the network layer connection with the
subscriber unit, wherein the plurality of CDMA channels includes a data traffic channel comprising a channel bandwidth;

circuitry to queue a request to allocate the plurality of CDMA channels for the network layer connection if either the channel
bandwidth for the data traffic channel or any of the plurality of CDMA channels are unavailable;

circuitry to receive data from the subscriber unit indicating that the subscriber unit has entered an idle state in response
to the request to allocate the plurality of CDMA channels being queued; and

circuitry to receive data from the subscriber unit indicating an expiration of a traffic timer related to the data traffic
channel, and to release the data channel comprising the channel bandwidth while the network layer connection with the subscriber
unit is maintained,

wherein the circuitry to allocate the plurality of CDMA channels further includes circuitry to receive a network layer message
that includes channel selection information for a channel multiplexer that selects among control and data traffic channels
based on the channel selection information.

US Pat. No. 9,402,251

ENHANCED PHYSICAL DOWNLINK CONTROL CHANNEL SCRAMBLING AND DEMODULATION REFERENCE SIGNAL SEQUENCE GENERATION

INTEL CORPORATION, Santa...

1. An apparatus to be employed in an enhance node B (eNB), the apparatus comprising:
scrambling circuitry to receive a bit sequence that includes downlink control information (DCI) to be transmitted on an enhanced
physical downlink control channel (EPDCCH) and to scramble the bit sequence based on a cell identifier to provide a scrambled
bit sequence; and

modulating circuitry coupled with the scrambling circuitry to receive the scrambled bits and to modulate the scrambled bits,
with a quadrature phase shift keying modulation scheme, to provide a block of complex-valued modulation symbols,

wherein the cell identifier is a virtual cell identifier;
the DCI is to be transmitted in a first EPDCCH set;
the virtual cell identifier corresponds to the first EPDDCH set; and
the scrambling circuitry is to scramble the DCI bits based on a scrambling initialization seed cint given by

cint=?ns/2?*29+NIDePDCCH where ns is a slot number within a radio frame and NIDePDCCH is the virtual cell identifier.

US Pat. No. 9,240,621

MICRO-STRIP CROSSTALK COMPENSATION USING STUBS

Intel Corporation, Santa...

8. A system comprising:
a synchronous dynamic random access memory;
a memory controller; and
a plurality of micro-strip conductors coupled to the memory and the memory controller, each conductor having a compensating
portion coupled with a remaining portion, the compensating portion including a plurality of stubs to compensate for crosstalk
in the remaining portion, wherein a first stub of the plurality of stubs nearest to the remaining portion and a second stub
of the plurality of stubs farthest from the remaining portion sandwich all remaining stubs of the plurality of stubs, wherein
the second stub is adjacent to a stub only in a direction facing the remaining portion towards the first stub, and wherein
a length of the compensating portion from the first stub to the second stub is less than a length of the remaining portion.

US Pat. No. 9,122,464

METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENERGY EFFICIENT PROCESSOR THERMAL THROTTLING USING DEEP POWER DOWN MODE

Intel Corporation, Santa...

1. A method comprising:
detecting that a temperature of a processor is greater than a first threshold, while the processor is performing processing
of data in an active processor power state;

based on detecting, changing a processor power state of the processor from the active processor power state to a zero processor
power state by power gating the processor;

after changing a processor power state of the processor from an active processor power state to the zero processor power state,
then detecting that a temperature of the processor is less than a second threshold, wherein the second threshold is less than
the first threshold; and

based on detecting that the temperature of the processor is less than the second threshold, changing the processor power state
from the zero processor power state to an active processor power state to cause the processor to process data, wherein the
first threshold is based on a thermal design of a device into which the processor is installed; and wherein the second threshold
is based on causing a time period of the zero processor power state to have a proportional relationship with a time period
of the active processor power state.

US Pat. No. 9,166,849

LARGE DELAY CYCLIC DELAY DIVERSITY (CDD) PRECODER FOR OPEN LOOP MULTIPLE-INPUT MULTIPLE-OUTPUT (MIMO)

INTEL CORPORATION, Santa...

1. A method for precoding for spatial multiplexing in an open-loop multiple-input multiple-output (MIMO) mobile communication
system, comprising:
receiving an input vector block from a layer mapper, wherein the input vector block includes user equipment-specific reference
signals (UE-RSs) or data in a physical downlink shared channel (PDSCH); and

generating a large delay cyclic delay diversity (CDD) vector block from the input vector block using a precoder configured
for large delay CDD on an antenna port, wherein the data is resource element mapped with UE-RSs or channel-state information
reference signals (CSI-RSs) in a physical resource block (PRB).

US Pat. No. 9,510,378

SYSTEMS AND METHODS FOR IMPLEMENTING A PEER-TO-PEER CONNECTION

INTEL CORPORATION, Santa...

1. A method comprising:
receiving, by a wireless interface module of a first device, a wireless connection request from an application on the first
device to connect to a second device;

receiving, by the wireless interface module, an indication from the second device to connect to the first device;
determining, by the wireless interface module computer processor, that the wireless connection request is an initial wireless
connection request;

generating, by the wireless interface module, a wireless connection protocol in response to the wireless connection request
and using a set of procedures that account for a first state associated with the first device based on the determination of
an initial wireless connection request, a second state associated with the second device, a first configuration of the first
device, and a second configuration of the second device, wherein the wireless connection request is independent of the first
state or the second state;

providing the wireless connection protocol to a wireless communications system on the first device to initiate a wireless
connection;

providing a wireless connection initiation message to the application;
establishing the wireless connection based at least in part on the wireless connection protocol; and
providing a wireless connection message to the application.

US Pat. No. 9,420,707

SUBSTRATE FOR INTEGRATED CIRCUIT DEVICES INCLUDING MULTI-LAYER GLASS CORE AND METHODS OF MAKING THE SAME

Intel Corporation, Santa...

1. A substrate comprising:
a core including of a number of discrete amorphous solid glass layers, the core having a first surface and an opposing second
surface;

a number of conductors extending through the core from the first surface to the second surface;
at least one dielectric layer and at least one metal layer disposed at the first surface of the core, wherein the at least
one metal layer at the first surface is electrically coupled with at least one of the conductors;

at least one dielectric layer and a least one metal layer disposed at the second surface of the core, wherein the at least
one metal layer at the second surface is electrically coupled with at least one of the conductors.

US Pat. No. 9,332,551

OPPORTUNISTIC RESOURCE SHARING BETWEEN DEVICES

INTEL CORPORATION, Santa...

1. A method, comprising:
broadcasting a resource share identity message, the resource share identity message to include an indication of a request
for resource configuration information;

receiving by a transceiver a set of resource configuration information from multiple devices, each of the sets of resource
configuration information including one or more operational parameters;

identifying, by a processor circuit, a set of homogeneous device resources implemented by the multiple devices based in part
on the sets of resource configuration information received by the transceiver;

selecting a shared homogeneous device resource of a first one of the multiple devices to share between the multiple devices
based in part on filtering the set of homogeneous device resources based on the one or more operational parameters;

sending a first control signal to the first one of the multiple devices, the first control signal to include an indication
to turn on the shared homogenous device resource of the first one of the multiple devices and to enable sharing of the shared
homogenous device resource with other ones of the multiple devices; and

sending a second control signal to at least a second one of the multiple device, the second control signal to include an indication
to turn off the shared homogenous device resource of the second one of the multiple devices and to enable sharing of the shared
homogeneous device resource of the first one of the multiple devices.

US Pat. No. 9,226,225

OVERHEAD-FREE PROVISIONING OF ROAMING WIFI NETWORKS

Intel Corporation, Santa...

1. A method, comprising:
scanning, by one or more computer processors, a primary repository for a first primary wireless profile corresponding to a
first wireless network;

determining, by the one or more computer processors, that the first primary wireless profile is stored in the primary repository;
executing, by the one or more computer processors, a primary connection cycle for the first wireless network responsive to
determining that the first primary wireless profile is stored in the primary repository, wherein executing the primary connection
cycle comprises attempting to establish a first connection between a wireless device and the first wireless network using
the first primary wireless profile;

determining, by the one or more computer processors, that the primary connection cycle has failed to establish the first connection
between the wireless device and the first wireless network;

scanning, by the one or more computer processors, the primary repository for a second primary wireless profile corresponding
to a second wireless network;

determining, by the one or more computer processors, that the primary repository does not store the second primary wireless
profile;

scanning, by the one or more computer processors, a secondary repository for a secondary wireless profile corresponding to
the second wireless network;

determining, by the one or more computer processors, that the secondary wireless profile is stored in the secondary repository;
executing, by the one or more computer processors, a secondary connection cycle for the second wireless network responsive
to determining that the secondary wireless profile is stored in the secondary repository, wherein executing the secondary
connection cycle comprises attempting to establish a second connection between the wireless device and the second wireless
network using the secondary wireless profile;

determining, by the one or more computer processors, that the secondary connection cycle has successfully established the
second connection between the wireless device and the second wireless network; and
storing, by the one or more computer processors, the secondary wireless profile in the primary repository.

US Pat. No. 9,153,552

BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING AN INTEGRATED HEAT SPREADER

Intel Corporation, Santa...

1. A method of forming a microelectronic die package, comprising:
stacking a lower die surface of a microelectronic die onto a heat spreader in thermal communication with the heat spreader;
forming a cavity through the heat spreader, wherein the cavity forms a direct interface with a portion of the lower die surface
of the microelectronic die;

forming an encapsulation material around the microelectronic die and the heat spreader;
building up a plurality of build-up layers onto an upper die surface of the microelectronic die, opposite the lower die surface;
and

forming a plurality of conductive traces disposed on the build-up layers in electrical communication with an active region
of the microelectronic die.

US Pat. No. 9,099,581

RE-ENTRANT MIRROR PHOTODETECTOR WITH WAVEGUIDE MODE FOCUSING

Intel Corporation, Santa...

1. A semiconductor photonic integrated circuit (I/C), comprising:
a waveguide integrated within a semiconductor substrate layer of the I/C, the waveguide horizontally constrained by parallel
oxide structures on either side of a semiconductor material of the semiconductor substrate layer, the waveguide having a waveguide
width defined by the parallel oxide structures, where an optical signal is to propagate horizontally along the waveguide;

a photodetector structure integrated within the semiconductor substrate layer of the I/C, and not within the waveguide defined
by the parallel oxide structures;

a focusing mirror to focus light of the optical signal to a redirected width smaller than the waveguide width and redirect
the light of the optical signal to propagate horizontally along a plane parallel to a surface of the semiconductor substrate
layer to exchange the light of the optical signal between the waveguide and the photodetector structure; and

multiple photodetector electrical contacts to operate the photodetector structure, the multiple photodetector electrical contacts
including a first photodetector electrical contact and a second photodetector electrical contact arranged on opposite sides
of the photodetector structure along a line extending athwart a length of the photodetector structure, wherein light redirected
by the focusing mirror propagates along the length of the photodetector structure, and wherein a distance between the first
photodetector electrical contact and the second photodetector electrical contact is greater than the waveguide width.

US Pat. No. 9,516,792

ULTRASOUND ASSISTED IMMERSION COOLING

Intel Corporation, Santa...

1. An apparatus comprising:
a tank to hold a dielectric fluid and one or more heat-generating components; and
a transducer located external to and coupled with the tank, the transducer to generate an ultrasound wave that controls movement
of the dielectric fluid at a location within a vicinity of at least one of the one or more heat-generating components within
the tank.

US Pat. No. 9,510,133

MULTI-RAT CARRIER AGGREGATION FOR INTEGRATED WWAN-WLAN OPERATION

INTEL CORPORATION, Santa...

1. An apparatus of a dual mode base station that includes a wireless wide area network (WWAN) access point that is integrated
with a wireless local area network (WLAN) access point, the apparatus comprising circuitry configured to:
perform, via the WWAN access point of the dual mode base station, a Third Generation Partnership Project (3GPP) Release 8,
9 or 10 attach procedure with a WWAN radio of a dual mode user equipment (UE);

perform, via the WWAN access point of the dual mode base station, a WLAN carrier aggregation capability exchange with the
WWAN radio of the dual mode UE, wherein the WWAN access point receives a WLAN carrier aggregation capability of the dual mode
UE during the WLAN carrier aggregation capability exchange;

determine, at the dual mode base station, whether to turn on the WLAN access point that is integrated in the dual mode base
station based on the WLAN carrier aggregation capability to enable WLAN carrier aggregation, wherein traffic for the dual
mode UE is offloaded from the WWAN access point to the WLAN access point when the WLAN access point is turned on at the dual
mode base station; and

obtain information when the WLAN access point is turned on, wherein the information is related to channel interference within
a coverage area of the dual mode base station and a number of WLAN deployments.

US Pat. No. 9,479,933

METHOD, APPARATUS AND SYSTEM OF COMMUNICATION OVER MULTIPLE FREQUENCY BANDS

INTEL CORPORATION, Santa...

1. A wireless communication device comprising:
at least two radios configured to communicate over at least two different frequency bands; and
a station management entity (SME) component operably coupled to the at least two radios, the SME component configured to manage
parallel and simultaneous operation of the at least two radios, said SME component configured to coordinate a setup, a tear
down and a transfer of a fast session transfer (FST) session from a first frequency band or channel to a second frequency
band or channel, wherein each of said at least two radios has a Media Access Control (MAC) sublayer, each MAC sublayer has
a separate MAC Service Access Point (SAP), and wherein each MAC SAP is controlled by a separate and independent Robust Security
Network Association (RSNA) key management entity, when transparent FST is not used.

US Pat. No. 9,313,747

STRUCTURED CODEBOOK FOR UNIFORM CIRCULAR ARRAY (UCA)

Intel Corporation, Santa...

1. A method comprising:
receiving, by user equipment, UE, from an enhanced node B, eNB, station of a wireless communication network, a Channel State
Information Reference Signal, CSI-RS, for the UE to perform channel measurements of multiple antennas of the eNB station,
wherein the multiple antennas are configured in one or more circular arrays;

performing, by the UE, channel measurements of the multiple antennas of the eNB station using the received CSI-RS;
determining, by the UE, a code word based on the channel measurements, the code word being stored in a first codebook stored
at the HE and designed for a circular antenna array;

sending, by the UE to the eNB station, a value that is an index of the code word for the eNB station to identify the code
word in a second codebook stored at the eNB station.

US Pat. No. 9,363,702

METHOD AND SYSTEM FOR ENABLING DEVICE-TO-DEVICE COMMUNICATION

Intel Corporation, Santa...

1. A method performed by a first user equipment (UE) for modifying a device-to-device (D2D) communication session with a second
UE, the method comprising:
locally producing a change determination that a resource allocation between the first user equipment and the second user equipment
should be changed;

sending one or more D2D uplink frames to the second UE;
sending a first timeslot assignment (TA) message arranged to indicate to the second UE a transmission window for consecutive
D2D frames, wherein the transmission window includes consecutive uplink frames and downlink frames to be communicated between
the first UE and the second UE;

receiving one or more D2D downlink frames from the second UE; and
sending a second TA message to the second UE to dynamically re-allocate the number of D2D frames between the first UE and
the second UE;

wherein the change determination is produced based on an assessment of uplink D2D and downlink D2D asymmetry in an ongoing
D2D session, and wherein the second TA message includes an indication of change in ratio of uplink and downlink frames to
correspond to the uplink D2D and downlink D2D asymmetry.

US Pat. No. 9,345,045

METHODS AND ARRANGEMENTS FOR ADAPTIVE DELAY CONTROL

Intel Corporation, Santa...

1. A method to coordinate transmissions of communication devices on a wireless network, the method comprising:
determining, by a first communications device, a delay, wherein the delay indicates a period of time during which other communications
devices associated with the wireless network perform clear channel assessment prior to transmitting and after changing from
a doze state to an awake state, wherein the delay indicates the period of time during which each of the other communications
devices perform the clear channel assessment absent detection of a frame sequence with a network allocation vector that results
in the network allocation vector being set, wherein determination of the delay is based upon information related to communications
between the first communications device and the other communications devices;

generating, by the first communications device, a frame comprising the delay; and
transmitting, by the first communications device, the frame.

US Pat. No. 9,516,755

MULTI-CHANNEL MEMORY MODULE

Intel Corporation, Santa...

1. A memory module, comprising:
a memory card having a plurality of sides;
a first plurality of memory devices disposed on a side of the memory card;
a second plurality of memory devices disposed on the side of the memory card;
a first plurality of memory module electrical terminals to couple the first plurality of memory devices to a computing device
printed circuit board (PCB); and

a second plurality of memory module electrical terminals to couple the second plurality of memory devices to the computing
device PCB, wherein the first and second plurality of memory module electrical terminals extend from different other sides
of the memory card such that the first plurality of memory module electrical terminals and the second plurality of memory
module electrical terminals do not face a same direction and wherein the first plurality of memory module electrical terminals
and the second plurality of memory module electrical terminals do not lie substantially higher than respective heights of
the first and second plurality of memory devices so that the memory module maintains a low profile.

US Pat. No. 9,433,017

POWER-EFFICIENT MEDIA ACCESS TECHNIQUES FOR WIRELESS NETWORKS

INTEL CORPORATION, Santa...

1. An apparatus, comprising:
an access selection module to:
identify a timing format comprising a first time interval and a second time interval select a channel access technique from
two or more channel access techniques based on a timing format,

select a first channel access technique during the first time interval, the first channel access technique to:
determine whether a randomly generated value is greater than or equal to an access probability,
in response to determining that the randomly generated value is great than or equal to the access probability, perform carrier
sensing, and

in response to determining that the randomly generated value is less than the access probability, forego performing carrier
sensing, and

select a second channel access technique during the second time interval; and
a transceiver to access a channel according to the first channel access technique during the first time interval and the second
channel access technique during the second time interval.

US Pat. No. 9,395,788

POWER STATE TRANSITION ANALYSIS

Intel Corporation, Santa...

1. A computing device for analyzing power state transitions, the computing device comprising:
a processor;
a data storage having stored thereon (i) power state records comprising transition data indicative of transitions of the processor
between power states and (ii) target residency data that identifies, for each power state of a plurality of power states of
the processor, an amount of time required in the corresponding power state to result in a conservation of power; and

a power state analysis module to (i) determine a power state entered by the processor and a duration of the power state entered
based on the power state records and (ii) determine, based on the determined power state entered and the target residency
data for the processor, whether the duration in the power state entered exceeds a duration of time required in another power
state of the plurality of power states to result in a conservation of power to determine an accuracy of a power state selection
of the processor, wherein the processor consumes less power in the another power state than in the power state entered.

US Pat. No. 9,345,104

DISPLAY BACKLIGHT POWER CONSUMPTION

Intel Corporation, Santa...

1. A system comprising:
a display panel having a backlight voltage regulator with an input;
a narrow voltage direct current (NVDC) charger having an input and an output;
an internal battery coupled to the output of the NVDC charger; and
a power management apparatus including,
a first path coupled to the output of the NVDC charger and the input of the backlight voltage regulator, and
a second path coupled to the input of the NVDC charger and the input of the backlight voltage regulator, wherein the second
path is to bypass current around the NVDC charger and to the input of the backlight voltage regulator if a voltage supplied
by an external power source to the input of the NVDC charger exceeds a voltage of the internal battery.

US Pat. No. 9,497,720

APPARATUS, METHOD AND SYSTEM OF SYNCHRONIZING BETWEEN WIRELESS COMMUNICATION DEVICES

INTEL CORPORATION, Santa...

1. A wireless communication device comprising:
a clock to count a local time;
a controller to count a virtual master clock corresponding to a group of wireless communication devices according to master
clock information defining said virtual master clock, the controller to determine a time drift between said local clock and
said virtual master clock, and to determine said virtual master clock based on said local time and the time drift; and

a radio to communicate with one or more devices of the group of wireless communication devices a synchronization frame including
a master clock time stamp of said virtual master clock.

US Pat. No. 9,280,510

INTER-CHIP COMMUNICATIONS WITH LINK LAYER INTERFACE AND PROTOCOL ADAPTOR

Intel Corporation, Santa...

1. An interface between units in a device, comprising:
a link layer system interface to:
communicate between a system and an external device; and
sequence data packets; and
a protocol adaptor to:
function as an intermediate unit between the link layer system interface and a plurality of low power, serial, embedded clock
physical layer interfaces;

translate responses at a lower power for inter-chip communications between each connected interface; and
wherein at least two of the plurality of low power, serial, embedded clock physical layers are used to provide a multi-lane
configuration.

US Pat. No. 9,282,564

SIMULTANEOUS TRANSMIT AND RECEIVE (STR) STRUCTURES IMMUNE TO PHASE AND AMPLITUDE IMBALANCES

Intel Corporation, Santa...

1. An echo-canceler for a simultaneous transmit and receive (STR) system, comprising:
at least three phase shifters, each respective phase shifter being coupled to a transmit signal of the STR system to generate
an output signal comprising a selected phase shift with respect to the transmit signal, the transmit signal comprising a 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) transmit signal;

a weight calculation unit coupled to the output signal of each respective phase shifter, each weight calculation unit to generate
a corresponding amplitude-weight signal for the output signal of the phase shifter;

a variable attenuator to attenuate the output signal of each respective phase shifter based on the corresponding amplitude-weight
signal to form an echo-cancelation signal component corresponding to the phase shifter; and

a first summer to sum the respective echo-cancelation signal components into a received signal containing an echo signal to
form an echo-canceled signal.

US Pat. No. 9,510,306

METHOD AND SYSTEM FOR COEXISTENCE OF MULTIPLE COLLOCATED RADIOS

INTEL CORPORATION, Santa...

1. An apparatus, comprising:
a set of co-located transceivers comprising three or more transceivers each operable to communicate via a wireless communications
standard different from each other transceiver;

a driver to output an enable signal when a first transceiver of the set of co-located transceivers is active, the enable signal
to cause the first transceiver to output a first frame synchronization input signal; and

a real-time frame synchronization module operable on a processor circuit to receive the first frame synchronization input
signal to delineate first receive and first transmit periods of a radio frame of the first transceiver, and generate a frame
synchronization signal to align receive and transmit periods of each of a multiplicity of additional transceivers of the set
of co-located transceivers to the respective first receive and first transmit periods of the first transceiver such that the
respective receive periods of the multiplicity of additional transceivers comprise durations matching a duration of the first
receive period and the respective transmit periods of the multiplicity of additional transceivers comprise durations matching
a duration of the first transmit period, the alignment to reduce interference between communications of the first transceiver
and communications of the multiplicity of additional transceivers.

US Pat. No. 9,479,332

KEY REVOCATION IN SYSTEM ON CHIP DEVICES

Intel Corporation, Santa...

1. An apparatus comprising:
a storage device, coupled to a processor, to store an identifier of an Original Equipment Manufacturer (OEM) and key versioning
information corresponding to the OEM,

wherein the key versioning information is to be updated by a security engine, coupled to the processor, in response to a determination
that a first OEM key certificate has been replaced with a second OEM key certificate and a determination that the second OEM
key certificate is newer than the first OEM key certificate, wherein the storage device is to comprise a dynamic fuse set
to store the key versioning information or a static fuse set to provide stock keeping unit identification, wherein the security
engine is to determine whether the second OEM key certificate is signed by a System On Chip (SOC) manufacturer prior to updating
a portion of the storage device.

US Pat. No. 9,280,168

LOW-POWER, HIGH-ACCURACY CURRENT REFERENCE FOR HIGHLY DISTRIBUTED CURRENT REFERENCES FOR CROSS POINT MEMORY

Intel Corporation, Santa...

1. A current reference source, comprising:
a current source to generate a first current;
a converter to generate a first voltage signal based on the first current, the converter comprising:
a first active device to generate a second current based on the first current, the first active device comprising a first
terminal, a second terminal and a third terminal, the first terminal being coupled to the second terminal,

a first degeneration-resistance device comprising a first terminal and a second terminal, the first terminal of the first
degeneration-resistance device being coupled to the first active device, and the second terminal of the first degeneration-resistance
device being coupled to a first power supply voltage, and

a first buffer comprising an input and an output, the input of the first buffer being coupled to the first active device,
the first voltage signal being formed between the output of the first buffer and a first terminal of the first power supply.

US Pat. No. 9,058,494

METHOD, APPARATUS, SYSTEM, AND COMPUTER READABLE MEDIUM TO PROVIDE SECURE OPERATION

Intel Corporation, Santa...

1. An apparatus to provide secure operation comprising:
at least one processor;
at least one memory, the at least one memory comprising instructions that when executed by the processor, cause the apparatus
to perform, at least, the following:

receive an enclave program for operation in an enclave;
identify at least one shared object dependency of the enclave program; and
determine whether the shared object dependency corresponds to an enclave shared object or a non-enclave shared object; and
an enclave dynamic linker comprising instructions that when executed by the processor, cause the apparatus to perform, at
least, the following:

cause association between the shared object dependency and the enclave shared object in response to a determination that the
shared object dependency corresponds to the enclave shared object; and

cause association between the shared object dependency and an enclave-loadable non-enclave shared object in response to a
determination that the shared object dependency corresponds to the non-enclave shared object;

wherein the enclave-loadable non-enclave shared object is a trampoline shared object;
wherein, when the shared object dependency corresponds to the non-enclave shared object, the instructions, when executed,
cause the apparatus to invoke the trampoline shared object in response to invocation of the shared object dependency;

wherein invocation of the trampoline shared object comprises replication of data associated with a function call associated
with the trampoline shared object from at least one enclave memory to at least one non-enclave memory;

wherein invocation of the trampoline shared object causes transfer of operation from the enclave to a non-enclave-loadable
shared object associated with the trampoline shared object; and

wherein causation of transfer of operation to the non-enclave-loadable shared object comprises invocation of an enclave proxy,
the enclave proxy to send a directive that identifies the non-enclave-loadable shared object to the enclave loader.

US Pat. No. 9,521,751

WEAVED ELECTRICAL COMPONENTS IN A SUBSTRATE PACKAGE CORE

Intel Corporation, Santa...

1. A circuit board comprising:
a circuit board pattern including a non-conductive board pattern of non-conductive strands woven between a component pattern
of conductive strands; wherein the component pattern includes both of (a) co-axial strands having a dielectric material between
a solid conductor material wire and an outer shield cylinder of conductor material surrounding the solid conductor material
wire and (b) an inductor pattern of solid conductor material wires;

cured resin impregnated within the circuit board pattern;
a top planar surface of the circuit board pattern;
a bottom planar surface of the circuit board pattern;
a first plurality of contacts formed on the top planar surface and coupled to the solid conductor material wire and to the
outer shield cylinder of conductor material of the co-axial strands; and

a second plurality of contacts formed on the top planar surface and electrically coupled to the solid conductor material wires
of the inductor pattern.

US Pat. No. 9,526,175

SUSPENDED INDUCTOR MICROELECTRONIC STRUCTURES

Intel Corporation, Santa...

1. A microelectronic structure, comprising:
a microelectronic substrate having an opening therein; and
a microelectronic package having at least one inductor electrically attached thereto, wherein the microelectronic package
is electrically attached to the microelectronic substrate, wherein the at least one inductor extends at least partially into
the microelectronic substrate opening, and wherein the microelectronic package comprises a microelectronic device attached
to a first surface of an interposer and the at least one inductor attached to a second surface of the interposer.

US Pat. No. 9,456,405

USER EQUIPMENT AND METHODS FOR OPERATION IN COVERAGE ENHANCEMENT MODE WITH PHYSICAL RANDOM ACCESS CHANNEL PREAMBLE

Intel Corporation, Santa...

1. A User Equipment (UE) to operate in accordance with a physical random access channel (PRACH), the UE comprising a memory
arranged to store instructions and hardware processing circuitry coupled to the memory that upon execution of the instructions
is arranged to:
determine a coverage enhancement category for the UE based on downlink channel statistics related to reception of downlink
signals at the UE from an Evolved Node-B (eNB) and an uplink-downlink imbalance parameter related to uplink reception at the
eNB; and

select, for use in a coverage enhancement mode, a PRACH preamble from a set of candidate PRACH preambles based on the determined
coverage enhancement category for the UE,

wherein at least some of the candidate PRACH preambles span a different number of sub-frames.

US Pat. No. 9,281,318

THREE DIMENSIONAL MEMORY STRUCTURE

Intel Corporation, Santa...

1. An integrated circuit comprising:
a substrate;
a conductive source layer positioned proximate a first surface of the substrate;
a pillar of semiconductor material electrically coupled to the conductive source layer;
two or more stacked memory cells comprising channels that are formed in the pillar, wherein a segment of the pillar of semiconductor
material extends beyond the two or more stacked memory cells; and

a field effect transistor (FET) formed proximate to the two or more stacked memory cells, and having a channel that is formed
in said pillar, wherein the FET comprises an exposed portion of the segment of the pillar extending beyond the two more stacked
memory cells

the pillar having a first cross-sectional area where the channel of the FET is formed, and a second cross-sectional area where
the channels of the two or more stacked memory cells are formed.

US Pat. No. 9,538,624

DISPLAY BACKLIGHT MODULATION

INTEL CORPORATION, Santa...

1. An apparatus to degrade a portion of recorded images of copyrighted material, the apparatus comprising:
a control module to degrade only a portion of recorded images at a time by selectively controlling the illumination of a first
backlight to illuminate a first portion of a liquid crystal display and a second backlight to illuminate a second portion
of the liquid crystal display, wherein in an enabled state, the control module is configured to turn the first backlight on
and off at a first frequency during a first period while the second backlight is not being turned on and off at a second frequency
and turn the second backlight on and off at a second frequency during a second period while the first backlight is not being
turned on and off at the first frequency where the first frequency is a non-harmonic frequency associated with known recording
frequencies of recording devices and the second frequency is a non-harmonic frequency associated with known recording frequencies
of recording devices, the second frequency being different than the first frequency, wherein the control module is in the
enabled state in response to receiving an indication that recorded image degradation is desired.

US Pat. No. 9,526,180

REDUCING DIELECTRIC LOSS IN SOLDER MASKS

Intel Corporation, Santa...

3. An apparatus comprising:
a mixer configured to generate a material to be used as a solder mask for a circuit board, wherein the material includes a
mixture of epoxy and a relatively low loss tangent material, wherein the relatively low loss tangent material comprises hollow
glass micro-balloons and wherein a percentage of the hollow glass micro-balloons of the mixture is proportional to a reduction
of loss tangent of the mixture.

US Pat. No. 9,299,161

METHOD AND DEVICE FOR HEAD TRACKING AND COMPUTER-READABLE RECORDING MEDIUM

Intel Corporation, Santa...

1. A method for performing head tracking, comprising:
receiving an input of at least two images including a facial area, wherein the at least two images include a first and a second
image; and tracking a movement of the facial area, comprising:

comparing a rotation angle of the facial area, of at least the second image, with a predetermined angle range;
if the rotation angle of the facial area is within the predetermined angle range from a front side, searching for a location
change of feature points within the facial area through a comparison with a template learned in advance; and

if the rotation angle of the facial area is beyond the predetermined angle range from the front side, searching for a location
change of feature points within the facial area through a comparison with the facial area of the at least first image frame
previously inputted.

US Pat. No. 9,295,085

COMMUNICATION SYSTEM AND METHOD OF DATA TRANSMISSION FOR A MEDIUM ACCESS CONTROL LAYER

Intel Corporation, Santa...

1. A method of data communication for a media access control (MAC) layer, including:
Initiating, by a mobile station (MS), an access attempt;
transmitting a probe to a base station (BS), wherein the probe includes a preamble, header information and data frames;
decoding the header information and the data frames;
generating, by the BS, a selective acknowledgement (SACK) message; and
transmitting the SACK message to the MS,
wherein the header information includes a first type header and a second type header, the BS establishes a buffer according
to a MOBILE_ID defined in the first type header and generates the SACK message after both of the first type header and the
second type header are decoded.

US Pat. No. 9,288,800

WIRELESS COMMUNICATIONS SYSTEM THAT SUPPORTS MULTIPLE MODES OF OPERATION

Intel Corporation, Santa...

15. A method for transmitting performed by a base transceiver station, the method comprising:
transmitting data over a downlink channel in accordance with a selected one of a plurality of transmission modes, the base
transceiver station being configurable to transmit data in accordance with each of the transmission modes; and

selecting one of the transmission modes for the data transmission based at least in part on feedback reported by a subscriber
unit,

wherein the transmission modes include at least a single antenna mode, a transmit diversity mode, and a spatial multiplexing
mode, and

wherein the selecting switches between the transmission modes.

US Pat. No. 9,632,862

ERROR HANDLING IN TRANSACTIONAL BUFFERED MEMORY

Intel Corporation, Santa...

1. An apparatus comprising:
a receiver to receive a read request from a host device;
a transmitter to send data from a memory buffer device to a host device over a link, wherein the data is responsive to the
read request and is to be further processed by the host device before being forwarded to another device;

an error detector to determine an error in the data, wherein the error is determined after at least a portion of the data
is sent from the memory buffer device to the host device; and

transaction cancellation logic to send a read response cancellation signal to the host device to indicate the error to the
host device, wherein the read response cancellation signal is to be sent subsequent to at least a portion of the data being
sent from the memory buffer device to the host device, and the read response cancellation signal is to cancel further transmission
of the data by the host device while not halting operation of the host device.

US Pat. No. 9,596,766

METHOD OF MANUFACTURING A CIRCUIT BOARD

Intel Corporation, Santa...

1. A method of manufacturing a circuit board comprising: adding a resin;
forming first and second fiberglass fibers; and
forming first and second signal line traces capable of transmitting electrical signals; wherein a ratio between fiberglass
and resin material near the first signal line trace is
similar to a ratio between fiberglass and resin material near the second signal line trace, and a shape formed between the
first and second signal line traces when crossing near the first and second fiberglass is in a non-rectilinear shape, and
wherein the first and second signal line traces are to be used to conduct differential mode signaling.

US Pat. No. 9,563,429

COALESCING ADJACENT GATHER/SCATTER OPERATIONS

Intel Corporation, Santa...

1. A processor comprising:
a plurality of 64-bit general-purpose registers;
a plurality of 128-bit single instruction, multiple data (SIMD) registers;
a data cache to cache data;
an instruction cache to cache instructions;
an instruction fetch unit coupled to the instruction cache to fetch the instructions;
a decode unit coupled to the instruction fetch unit, the decode unit to decode the instructions, including a first instruction,
the first instruction to indicate a 128-bit operand size, the first instruction having a first field to specify a first 128-bit
SIMD source register of the plurality of 128-bit SIMD registers, the first instruction having a second field to specify a
64-bit general-purpose register of the plurality of 64-bit general-purpose registers to store a base address, and the first
instruction to indicate a data element width of 64-bits; and

an execution unit coupled to the decode unit, coupled to the plurality of 128-bit SIMD registers, and coupled to the plurality
of 64-bit general-purpose registers, the execution unit to execute the first instruction to:

store a first structure and a second structure to a memory based on the base address, a first 64-bit data element of the first
structure to include a first 64-bit data element of the first 128-bit SIMD source register, which is to be from least significant
bits of the first 128-bit SIMD source register, a second 64-bit data element of the first structure to include a first 64-bit
data element of a second 128-bit SIMD source register, which is to be from least significant bits of the second 128-bit SIMD
source register, a third 64-bit data element of the first structure to include a first 64-bit data element of a third 128-bit
SIMD source register, which is to be from least significant bits of the third 128-bit SIMD source register, wherein the first,
second, and third 64-bit data elements of the first structure are to be consecutive data elements in the memory, a first 64-bit
data element of the second structure to include a second 64-bit data element of the first 128-bit SIMD source register, a
second 64-bit data element of the second structure to include a second 64-bit data element of the second 128-bit SIMD source
register, and a third 64-bit data element of the second structure to include a second 64-bit data element of the third 128-bit
SIMD source register, wherein the first, second, and third 64-bit data elements of the second structure are to be consecutive
data elements in the memory.

US Pat. No. 9,076,019

METHOD AND APPARATUS FOR MEMORY ENCRYPTION WITH INTEGRITY CHECK AND PROTECTION AGAINST REPLAY ATTACKS

Intel Corporation, Santa...

1. A method comprising:
generating, by a processor, a message-authentication code (MAC) for a block of data associated with an application;
providing, in a processor, a plurality of counters, each counter associated with one of a plurality of MAC cache lines in
a memory;

encrypting, by the processor, the MAC, the MAC encrypted using a tweak, the tweak including a cache line identifier for the
MAC cache line to store the MAC and a timestamp value read from the counter associated with the MAC cache line;

storing, by the processor, the block of data in a cache line of the memory; and
storing, by the processor, the MAC in a MAC cache line in the memory, the memory separate from the processor.

US Pat. No. 9,516,752

UNDERFILL DEVICE AND METHOD

Intel Corporation, Santa...

1. An underfill, comprising:
a single material compliant polymer underfill film including a first surface and a second surface, wherein the underfill film
includes a eradiated microstructure;

a first adhesive coupled the first surface and a second adhesive coupled to the second surface;
a first peel off layer coupled to the first adhesive and a second peel off layer coupled to the second adhesive; and
at least one conductive through thickness plug attached to and passing through the single material compliant polymer underfill
film.

US Pat. No. 9,565,787

HEAT DISSIPATION DEVICE LOADING MECHANISMS

Intel Corporation, Santa...

1. A heat dissipation device loading mechanism, comprising:
a loading mechanism body; and
at least one outrigger pivotally attached with a pivot pin to the loading mechanism body, wherein the outrigger is pivotal
between a first position and a second position; and

a position retention mechanism, separate from the pivot pin, retain the at least one pivotal outrigger in a position at or
between the first position and the second position, wherein the position retention mechanism comprises a plurality of pins
extending from at least one of the at least one pivotal outrigger and the loading mechanism body, and an opening in at least
one pivotal outrigger and the loading mechanism body, wherein a first pin of the plurality of pins is inserted into the opening
when the at least one pivotal outrigger is in the first position, and, wherein a second pin of the plurality of pins is inserted
into the opening when the at least one pivotal outrigger is in the second position.

US Pat. No. 9,554,468

PANEL WITH RELEASABLE CORE

Intel Corporation, Santa...

1. A panel comprising:
a base including a first recess therein;
a first inner foil situated in the recess;
a first adhesive layer situated on the first inner foil and in the recess;
a first outer conductive foil releasably coupled to the first inner conductive foil through the adhesive layer, the first
outer conductive foil situated at least partially in the recess and including a width that is substantially the same as a
width of the first inner foil;

a second dielectric material situated on the first outer conductive foil; and
an outermost conductive foil situated on the second dielectric material, wherein a width of the outermost conductive foil
is substantially the same as a width of the base, wherein the second dielectric material and the outermost conductive foil
both individually overlay the entire outer conductive foil and all exposed portions of a surface of the base.

US Pat. No. 9,516,628

METHOD AND APPARATUS FOR COORDINATION OF SELF-OPTIMIZATION FUNCTIONS IN A WIRELESS NETWORK

Intel Corporation, Santa...

1. A network manager (NM) comprising:
a self-optimized network (SON) coordination function to prevent a conflict and to provide resolution to the conflict cause
by an operation of one SON function at the same time when another SON function is to operate on an enhanced Node B (eNodeB)
of a plurality of enhanced node Bs (eNodeBs); wherein, the SON coordination function is to coordinate SON functions which
include at least an energy saving management (ESM) function, a cell outage compensation (COC) function or a coverage and a
capacity optimizing (CCO) function based on a SON coordination state, the SON coordination state being a state of SON functions,
wherein the SON coordination state is one of

a first state indicating that a respective eNodeB of the plurality of eNodeBs is already providing coverage for other eNodeBs
of the plurality of eNodeBs that are switched off for energy-saving purposes by an ESM SON function,

a second state indicating that a respective eNodeB of the plurality of eNodeBs is already providing coverage of a neighboring
eNodeB that is in outage, and

a third state indicating that a respective eNodeB of the plurality of eNodeBs is updating the configuration parameters in
a respective cell.

US Pat. No. 9,357,576

AUTOMATIC PAIRING FOR PORTABLE COMPUTING DEVICES

Intel Corporation, Santa...

1. An apparatus to facilitate pairing in a portable computing device comprising: an embedded controller; an input/output (IO)
controller coupled to the embedded controller; a first wireless communication component coupled to the IO controller; a processor
coupled to the first wireless communication component, the processor to receive a dock event notification, wherein an identifier
from a base device is received via one or more of the embedded controller, the IO controller, or the first wireless communication
component to initiate automatic pairing between the portable computing device and a second wireless communication component
in the base device; a first docking port to connect with a second docking port on the base device; and a first electrical
communication path between the first docking port and the embedded controller and a second electrical communication path between
the first docking port and the processor wherein the first electrical communication path forms part of an out-of-band channel
for transmission of the identifier.

US Pat. No. 9,313,814

ESTABLISHING WIRELESS COMMUNICATION VIA PROXIMITY DETECTION

Intel Corporation, Santa...

1. A user device, comprising:
a radio transceiver;
a proximity transponder having a plurality of inductive coils;
at least one processor; and
at least one memory storing instructions, that when executed by the at least one processor, causes that at least one processor
to:

detect, by the proximity transponder via the plurality of inductive coils, a magnetic field emitted from a base station;
transmit, by the proximity transponder to the base station in response to the magnetic field, identification information,
wherein the identification information identifies radio communication information associated with the radio transceiver;

receive, from the base station, a verification of the identification information, wherein the verification of the identification
information comprises a request from the base station to establish a radio connection with the base station using the radio
communication information; and

establish, by the radio transceiver based at least in part on the verification, the radio connection with the base station.

US Pat. No. 9,306,390

DISTRIBUTED ELECTROSTATIC DISCHARGE PROTECTION FOR AN ON-PACKAGE INPUT/OUTPUT ARCHITECTURE

Intel Corporation, Santa...

1. An apparatus comprising:
an input/output (I/O) pad;
a first pair of diodes coupled with the pad and between a supply voltage and a ground potential;
a resistive element coupled to the pad and with a second pair of diodes coupled between the supply voltage and the ground
potential;

a first set of single-ended transmitter circuits on a first die;
a first set of single-ended receiver circuits on a second die, wherein the receiver circuits have a termination circuit comprising
an inverter and a resistive feedback element; and

a plurality of conductive lines between the first set of transmitter circuits and the first set of receiver circuits, wherein
the lengths of the plurality of conductive lines are matched.

US Pat. No. 9,292,221

BI-DIRECTIONAL COPYING OF REGISTER CONTENT INTO SHADOW REGISTERS

INTEL CORPORATION, Santa...

1. A processor comprising:
a plurality of registers;
a shadow register file with a plurality of shadow registers;
a control register; and
copy circuitry coupled to the plurality of registers, the shadow register file and the control register, to copy content from
some or all of a range of the plurality of registers to a shadow range of the shadow register file in a first or second selected
direction of the shadow registers, wherein the first or second selected direction of the shadow registers is to be based at
least in part on a value to be stored in the control register.

US Pat. No. 9,563,431

TECHNIQUES FOR COOPERATIVE EXECUTION BETWEEN ASYMMETRIC PROCESSOR CORES

INTEL CORPORATION, Santa...

1. An apparatus to control flows of execution comprising:
a lower power core of a processor component, the lower power core comprising a first instruction pipeline and the lower power
core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in
the first instruction pipeline to perform a first task of handling an interrupt; and

a higher function core of the processor component, the higher function core comprising a second instruction pipeline and the
higher function core to, following the performance of the first task, schedule execution of instructions of a second task
of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction
pipeline, the first task more time-sensitive than the second task.

US Pat. No. 9,299,602

ENABLING PACKAGE-ON-PACKAGE (POP) PAD SURFACE FINISHES ON BUMPLESS BUILD-UP LAYER (BBUL) PACKAGE

Intel Corporation, Santa...

1. A method of manufacturing an integrated circuit (IC) package, the method comprising:
providing a package core with a plurality of package-on-package (PoP) pad locations formed on the package core, wherein the
plurality of PoP pad locations are plated with an etch layer of conductive material;

plating a sub-surface finish being a group-10 element onto the etch layer at the PoP pad locations;
forming at least one build-up layer including interconnects formed therein over a die disposed on the package core and the
PoP pad locations; and

exposing the PoP pad locations on a side opposing the build-up layer.

US Pat. No. 9,591,195

PLATFORM ARCHITECTURE FOR ACCELERATED CAMERA CONTROL ALGORITHMS

Intel Corporation, Santa...

1. A platform for image processing with digital camera control algorithms, the platform comprising:
a camera control bus to couple with one or more camera hardware module (CM);
a soft real-time (SRT) camera controller including logic circuitry to:
generate a frame-based series of CM control parameter values, the frame-based series associated with a window spanning a predetermined
number of consecutive image data frames to be exposed by a CM at a frame rate; and

a hard real-time (HRT) camera controller coupled to both the SRT controller and the camera control bus, the HRT controller
including logic circuitry to:

receive the control parameter values intermittently from the SRT controller; and
output the control parameter values to the control bus in synchronization with actions of a CM associated with exposing consecutive
image data frames.

US Pat. No. 9,554,472

PANEL WITH RELEASABLE CORE

Intel Corporation, Santa...

1. A panel comprising:
a substantially rectangular base including a carbon impregnated with at least one of an epoxy and a resin;
an inner foil mechanically coupled to the base;
an outer conductive foil situated over and releasably coupled to the inner foil; and
connective material coupling the inner foil and the outer conductive foil only near edges of the outer conductive foil and
the inner foil.

US Pat. No. 9,431,274

METHOD FOR REDUCING UNDERFILL FILLER SETTLING IN INTEGRATED CIRCUIT PACKAGES

Intel Corporation, Santa...

1. A method comprising:
providing a first integrated circuit, IC, substrate and a second IC substrate coupled by an interconnect structure;
providing an underfill, UF, material comprising a combination of resin and filler particles;
depositing the UF material between the first IC substrate and the second IC substrate;
reducing settling of the filler particles by reducing an electrostatic charge of the filler particles within the deposited
UF material; and

curing the deposited UF material.

US Pat. No. 9,368,208

NON-VOLATILE LATCH USING MAGNETO-ELECTRIC AND FERRO-ELECTRIC TUNNEL JUNCTIONS

Board of Regents, The Uni...

1. A non-volatile memory circuit comprising:
a first access transistor, a second access transistor, a first inverter having a first n-type transistor and a first p-type
transistor, a second inverter having a second n-type transistor and a second p-type transistor, at least one magnetic device,
and a programming logic,

wherein the first access transistor connects a bit line to a first output node of the first inverter under control of a word
line coupled to a gate of the first access transistor,

wherein the second access transistor connects a bit bar line to a second output node of the second inverter under control
of the word line coupled to a gate of the second access transistor,

wherein the first output node is coupled to a second input node of the second inverter and the second output node is coupled
to a first input node of the first inverter,

wherein the at least one magnetic device is coupled to the first n-type transistor and the second n-type transistor, and
wherein the programming logic is coupled to at least one of the first output node and the second output node to program the
at least one magnetic device,

wherein the at least one magnetic device comprises a first magneto-electric device and a second magneto-electric device, wherein
a first bottom electrode of the first magneto-electric device receives an output of the programming logic coupled to the first
output node, wherein a second bottom electrode of the second magneto-electric device receives an output of the programming
logic coupled to the second output node, wherein a first free ferromagnetic (FM) layer of the first magneto-electric device
and a second free FM layer of the second magneto-electric device are coupled to each other, wherein a first pinned FM layer
having a first polarity is coupled to the first n-type transistor, and wherein a second pinned FM layer having a second polarity
opposite the first polarity is coupled to the second n-type transistor.

US Pat. No. 9,337,661

POWER MANAGEMENT SYSTEM AND METHOD

Intel Corporation, Santa...

1. An apparatus comprising:
a storage area to store instructions; and
a controller to control power in a first device based on the instructions,
wherein the controller to determine a first connection state of the first device and to determine a second connection state
of the first device,

the controller to generate one or more first control signals based on the determined first connection state, and the controller
to generate one or more second control signals based on the determined second connection state, the one or more first control
signals to control one or more first switch devices and the one or more second control signals to control one or more second
switch devices to combine power from a first power source and a second power source for a hybrid power operation;

wherein the first connection state of the first device is based on whether a second device is coupled to the first device;
wherein: the first device comprises a tablet, the tablet including the controller to generate the one or more first control
signals to control the one or more first switch devices on the tablet, and the second device comprises a base removably coupled
to the tablet;

and wherein the second connection state to be based on coupling of an AC adaptor to the first device.

US Pat. No. 9,506,984

PROTOCOL BASED AUTOMATED TESTER STIMULUS GENERATOR

Intel Corporation, Santa...

1. A system on chip (SOC) testing apparatus comprising:
an input interface;
a protocol decode agent that receives transmission signals into the input interface, the protocol decode agent generates testing
stimuli for a SOC based on the transmission signals;

an output interface;
a test vector generator that receives the testing stimuli from the protocol decode agent and supplies the testing stimuli
as digital signals to the output interface; and

a SOC connected to the input interface and the output interface, wherein the SOC includes a physical layer that supplies the
transmission signals to the input interface and receives tester stimuli from the output interface, wherein the SOC includes
a protocol block that receives testing stimuli from the physical layer and delivers transmissions signals to the physical
layer.

US Pat. No. 9,456,451

METHOD AND SYSTEM FOR MANAGING RADIO RESOURCES IN A TIME-SLOTTED COMMUNICATION SYSTEM

Intel Corporation, Santa...

1. A method of managing radio resources in time division duplex wireless communications comprising:
receiving a radio resource request from a user;
obtaining a quality of service (QoS) classification of the user, wherein the QoS classification is based on a user's subscription
status, geographic information, and a user's subscriber classification;

defining a plurality of time slot designations, wherein each time slot designation has an associated QoS level and capacity;
mapping the user to one of the time slot designations based on the QoS classification of the user; and
determining whether to initiate handover (HO) in response to the user crossing a boundary between cells, wherein HO is performed
if a target cell provides sufficient resources and, if the target cell does not provide sufficient resources to service a
high-QoS user in response to detecting congestion in the high-QoS time slot designation, freeing high capacity time slots
to be able to accept incoming high-QoS users, wherein incoming balanced user requests are accepted by adjusting QoS requirements
in order to not congest the system, and incoming high capacity requests are rejected in response to detecting congestion in
the high-QoS time slot designation, and determining whether to adjust a data rate and high QoS time slots are given a guaranteed
bit rate plus a predefined margin, balanced time slots are given a guaranteed bit rate, and high capacity time slots are not
guaranteed a bit rate, wherein:

on a condition that congestion is detected on the mapped time slot designation, dynamically adjusting a number of time slots
assigned to each time slot designation, wherein if congestion occurs with high QoS time slots, increasing the number of high
QoS time slots available and decreasing the number of high capacity time slots available and, if necessary, the number of
balanced time slots available after exhaustion of the available high capacity time slots, and if congestion occurs with balanced
time slots, increasing the number of balanced time slots available, and decreasing the number of high capacity time slots
available,

on a condition that HO initiation is determined, releasing high capacity time slots and adjusting QoS requirements of balanced
time slot requests;

on a condition that the processing of data packets is required, adjusting delay and jitter for processing data packets, based
on the time slot designation, and

on condition that the data rate adjustment is required, adjusting the bit rate based on the time slot designation.

US Pat. No. 9,215,701

RANDOM ACCESS CHANNEL ENHANCEMENTS FOR LTE DEVICES

Intel Corporation, Santa...

1. A device operating as user equipment (UE) in a Long Term Evolution LTE network, comprising:
an RF transceiver for providing an LTE air interface for communicating with a base station operating as an enhanced/evolved
Node B (eNB);

processing circuitry interfaced to the RF transceiver and arranged to, when not connected to the eNB so that no PUCCH (physical
uplink control channel) resources have been allocated for transmitting scheduling requests and when a packet aggregation mode
is entered:

start a packet aggregation timer;
inhibit the UE from transmitting on a physical random access channel (PRACH) for the purpose of transmitting uplink packets
having a relaxed latency requirement, referred to as background packets, until expiration of the packet aggregation timer;

buffer the background packets; and,
upon expiration of the packet aggregation timer, request uplink resources from the eNB via a random access procedure to transmit
the buffered packets.

US Pat. No. 9,159,714

PACKAGE ON WIDE I/O SILICON

Intel Corporation, Santa...

6. An apparatus comprising:
a die comprising a device side and an opposite backside, a first plurality of contacts on the backside and a plurality of
through vias from the device side to the first plurality of contacts and a different second plurality of contacts on one of
the backside of the die and on at least two opposing sidewalls of the die;

a secondary die coupled to the first plurality of contacts;
a carrier comprising on a device side of the die at least one patterned layer of conductive material disposed in a first dielectric
material, a first plurality of carrier contact points operable for mounting the carrier to a substrate, and a second plurality
of carrier contact points on a side opposite a side of the first plurality of carrier contact points, at least ones of the
second plurality of carrier contact points coupled to the second plurality of contacts of the die, wherein the carrier comprises
a second dielectric material disposed between respective ones of the second plurality of contacts of the die and the second
plurality of carrier contact points, the second dielectric material embedding at least opposing sides of the secondary die;
and

a tertiary die coupled to the second plurality of contacts.

US Pat. No. 9,603,276

ELECTRONIC ASSEMBLY THAT INCLUDES A PLURALITY OF ELECTRONIC PACKAGES

Intel Corporation, Santa...

1. An electronic assembly comprising:
a frame formed from a unitary piece of material;
a first electronic package mounted on the frame, the first electronic package including a first pin grid array;
a second electronic package mounted on the frame and separated laterally from the first electronic package, the second electronic
package including a second pin grid array, the frame laterally surrounding the first and second electronic package; and

an actuation mechanism on the frame, the actuation mechanism being configured to simultaneously move the first electronic
package and the second electronic package laterally relative to the frame during operation of the actuation mechanism.

US Pat. No. 9,299,672

CONTACT PADS FOR INTEGRATED CIRCUIT PACKAGES

INTEL CORPORATION, Santa...

1. A contact pad on a substrate of an integrated circuit (IC) package, the contact pad comprising: a metal projection portion
having a solder contact surface; and a metal recess portion having a solder contact surface, wherein the solder contact surface
of the metal recess portion is spaced away from the solder contact surface of the metal projection portion and is disposed
closer to the substrate, and wherein a footprint of the metal recess portion includes a wave pattern shape of the integrated
circuit.

US Pat. No. 9,603,247

ELECTRONIC PACKAGE WITH NARROW-FACTOR VIA INCLUDING FINISH LAYER

Intel Corporation, Santa...

1. An electronic package, comprising:
an electrically conductive pad;
a first package insulator layer including a substantially non-conductive material; and
a first via, formed within the package insulator layer, electrically coupled to a front side of the electrically conductive
pad, the first via comprising:

a nickel conductor extending vertically through at least part of the package insulator layer and having a first end coupled
to the electrically conductive pad and a second end opposite the first end;

a finish layer coupled to the second end of the conductor, the finish layer including a gold compound
an embedded bridge within the electronic package;
a second package insulator layer between a backside of the electrically conductive pad and the embedded bridge; and
a copper via formed through the second package insulator layer, and coupled between the backside of the electrically conductive
pad and the embedded bridge.

US Pat. No. 9,563,425

INSTRUCTION AND LOGIC TO PROVIDE PUSHING BUFFER COPY AND STORE FUNCTIONALITY

Intel Corporation, Santa...

1. A processor comprising:
a first hardware thread and a second hardware thread;
a cache to store cache coherent data in a cache line for a shared memory address accessible by said second hardware thread;
a decode stage to decode a first instruction for execution by said first hardware thread, the first instruction specifying
a source vector data operand, said shared memory address as a destination operand, and one or more owners of said shared memory
address; and

one or more execution units, responsive to the decoded first instruction, to:
copy data from the source vector data operand to the cache coherent data in the cache line for said shared memory address
accessible by said second hardware thread in the cache when said one or more owners includes said second hardware thread,
wherein corresponding vector elements from the vector source data operand are copied to adjacent sequential element locations
starting at the shared memory address until the most significant vector destination element location is filled.

US Pat. No. 9,294,562

PEER TO PEER NETWORKING AND SHARING SYSTEMS AND METHODS

Intel Corporation, Santa...

1. At least one non-transitory storage medium having instructions stored thereon for causing a system to perform a method
comprising a first compute node:
establishing a persistent control path with a second compute node;
establishing an on-demand data path with the second compute node;
communicating control information to the second compute node via the persistent control path while simultaneously communicating
content to the second compute node via the on-demand data path; and

promptly disabling the established on-demand data path after communicating the content to the second compute node while simultaneously
maintaining the persistent control path after communicating the control information to the second compute node.

US Pat. No. 9,280,162

METHOD AND APPARATUS FOR MINIMIZING WITHIN-DIE VARIATIONS IN PERFORMANCE PARAMETERS OF A PROCESSOR

Intel Corporation, Santa...

1. An apparatus comprising:
a bias generator to generate a bias signal which is directly distributed to at least two sets of transmitters; and
a feedback mechanism to process output signals, of the at least two sets of transmitters, to generate a feedback signal for
the bias generator, wherein the feedback signal is applied by the bias generator to adjust the bias signal.

US Pat. No. 9,615,483

TECHNIQUES AND CONFIGURATIONS ASSOCIATED WITH A PACKAGE LOAD ASSEMBLY

Intel Corporation, Santa...

1. An apparatus comprising:
a frame to form a perimeter around a die area of a package substrate, a first surface of the frame to contact a surface of
the package substrate around an entirety of the perimeter formed around the die area; and

a plurality of deformable members disposed on a second surface of the frame, the second surface disposed opposite to the first
surface, the plurality of deformable members to be coupled with a base of a heat sink to distribute a force applied between
the heat sink and the package substrate, via the frame, and deform under application of the force to allow the base of the
heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.

US Pat. No. 9,397,641

APPARATUS AND METHOD FOR LOW POWER FULLY-INTERRUPTIBLE LATCHES AND MASTER-SLAVE FLIP-FLOPS

Intel Corporation, Santa...

1. A latch comprising:
a first AND-OR-invert (AOI) logic gate; and
a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective
first and second keeper devices coupled to a power supply node;

first and second n-type devices coupled in series;
a third n-type device coupled to the second n-type device at a storage node; and
first and second p-type devices coupled in parallel, the first and second p-type devices coupled to the storage node and the
first keeper device, wherein the second n-type device and the first p-type device have their respective gate terminals coupled
to a data node.

US Pat. No. 9,357,582

SIMULTANEOUS SECONDARY-CELL RELEASE FOR LICENSED SHARED ACCESS

Intel Corporation, Santa...

1. A User Equipment (UE) comprising a processor and transceiver configured to:
receive, on a Licensed Shared Access (LSA) frequency band, a broadcast paging message indicating transmission of a System
Information Block 2 (SIB2) carrying Radio Resource Control (RRC) connection information in a next modification period;

receive, in the next modification period on the LSA frequency band, the SIB2, wherein the RRC connection information comprises a list of excluded Secondary-Cell(s) (SCells); and

reconfigure the RRC connection information to release SCells identified in the list of excluded SCells.

US Pat. No. 9,304,731

TECHNIQUES FOR RATE GOVERNING OF A DISPLAY DATA STREAM

INTEL CORPORATION, Santa...

1. A method, comprising:
determining, by a processor circuit, a target display data transmission rate for one or more displays;
generating, by a digital differential analyzer (DDA) communicatively coupled to the processor circuit, an actual display data
transmission rate for one or more display data packets based on the target display data transmission rate;

transmitting the one or more display data packets based on the actual display data transmission rate;
accumulating a difference between the actual display data transmission rate and the target display data transmission rate
for the one or more display data packets, the display data packets comprising a display data packet stream, the display data
packet stream comprising one or more display data transmission lanes;

receiving one or more display data source streams; and
processing the one or more display data source streams to form the display data packet stream, each of the one or more display
data transmission lanes in the display data packet stream corresponding to a different one of the one or more display data
source streams.

US Pat. No. 9,060,313

ACKNOWLEDGEMENT SIGNALING IN A WIRELESS COMMUNICATIONS NETWORK

Intel Corporation, Santa...

1. A method to facilitate provision of acknowledgement signals for use by user equipments (UEs) operating in a wireless communications
network, the method comprising:
transmitting, by an evolved node B (eNodeB), radio resource control (RRC) signals indicating inclusion of an enhanced physical
hybrid automatic repeat request (ARQ) indicator channel (e-PHICH) in a radio frame; and

configuring, by the eNodeB, the radio frame including the e-PHICH, wherein at least one subframe of the radio frame includes
a first layer of a resource block (RB) associated with a first UE and a second layer of the RB associated with a second UE,
and wherein the first layer of the RB includes a physical downlink control channel (PDCCH) control region in a Slot 0 of the subframe and a first enhanced PDCCH (e-PDCCH) allocation in the Slot 0 and in a Slot 1 of the subframe, and wherein the e-PHICH allocation is included in at least the Slot 1 of the subframe of the first layer of the RB; and wherein a second layer of the RB includes a second e-PDCCH allocation in
a second portion of the Slot 0 and in the Slot 1 of the subframe;

wherein the RRC signals assign a same user equipment-reference signal (UE-RS) code division multiplexing (CDM) group to decode
both the e-PHICH allocation and the first e-PDCCH allocation; and

wherein a first resource element (RE) set for the e-PHICH allocation in the first layer of the RB is orthogonal with a first
RE set for the first e-PDCCH allocation provided in the first layer of the RB and a second RE set for the second e-PDCCH allocation
provided in the second layer of the RB.

US Pat. No. 9,609,782

RACK ASSEMBLY STRUCTURE

INTEL CORPORATION, Santa...

1. A rack assembly, comprising:
a plurality of sleds with individual sleds including one or more compute nodes; and
a networking element coupled with a sled of the plurality of sleds to communicatively connect the sled to one or more other
components of the rack assembly via an optical communication system, wherein the optical communication system includes an
external optical cable to communicatively connect the networking element with the rack assembly, and an optical module to
communicatively connect the networking element with the rack assembly via a switch component of the networking element, and
to communicatively connect with the external optical cable via an optical jumper cable; and

a patch panel, wherein the external optical cable is to communicatively connect the networking element with the patch panel
of the rack assembly.

US Pat. No. 9,485,854

ABSORBING TERMINATION IN AN INTERCONNECT

Intel Corporation, Santa...

23. A computing apparatus, comprising:
a processor;
a memory coupled with the processor; and
a printed circuit board (PCB) assembly coupled with the processor and memory, the PCB assembly comprising:
a substrate;
at least one interconnect comprising a transmission line formed in the substrate to route an electrical signal within the
PCB, wherein at least one end of the transmission line reaches a surface of the PCB and is coupled with a connecting component
that comprises a connector slot disposed on the surface of the PCB, wherein the connector slot is to receive a corresponding
connecting element of an insertable component to be coupled with the PCB assembly, wherein at least a surface of the connecting
element that faces the connector slot is directly covered with an absorbing material that is disposed to be in direct contact
with at least a portion of the connector slot to at least partially absorb a portion of the electrical signal.

US Pat. No. 9,059,854

PROTOCOL FOR AUTHENTICATING FUNCTIONALITY IN A PERIPHERAL DEVICE

Intel Corporation, Santa...

1. A peripheral device comprising:
a hardware port to removably connect the peripheral device to a bus of a computing device, the peripheral device to provide
a peripheral function to the computing device when connected to the computing device;

a storage device to store a private key associated with the apparatus, the private key being one of multiple private keys
that are associated with a corresponding public key, the public key to authenticate the multiple private keys, each one of
the multiple private keys associated with a different peripheral device, the private key corresponding to a set of specific
functions that the peripheral device is designed to provide; and

the hardware port to send a message encrypted with the private key to the computing device, the computing device to identify
functionality characteristics of the peripheral device by applying the public key to the message and successfully authenticating
the peripheral device, the hardware port to receive authorization from the computing device to provide the functionality characteristics
for the peripheral device in response to the computing device's successful authenticating of the peripheral device.

US Pat. No. 9,535,782

METHOD, APPARATUS AND SYSTEM FOR HANDLING DATA ERROR EVENTS WITH A MEMORY CONTROLLER

Intel Corporation, Santa...

1. A memory controller comprising:
scrubber logic comprising circuitry to perform a first patrol scrub of a plurality of active segments of a memory, and to
perform a second patrol scrub of one or more segments of the memory while the one or more segments are each available as a
spare segment for the plurality of active segments; and

sparer logic comprising circuitry to receive an indication of a first uncorrectable error event detected based on the first
patrol scrub, wherein, of a first handler process and a second handler process, the sparer logic to signal only the first
handler process in response to the indication of the first uncorrectable error event, the sparer logic further to receive
an indication of a second uncorrectable error event detected based on the second patrol scrub, wherein, of the first handler
process and the second handler process, the sparer logic to signal only the second handler process in response to the indication
of the second uncorrectable error event.

US Pat. No. 9,497,785

TECHNIQUES FOR EXCHANGING BEAMFORMING INFORMATION FOR A DUAL CONNECTION TO USER EQUIPMENT

INTEL CORPORATION, Santa...

1. An apparatus comprising:
a processor circuit for a small cell base station;
a request component for execution by the processor circuit to receive a beam activation request message from user equipment
(UE) via a backhaul channel coupled with a macro cell base station, the beam activation request message including information
to initiate configuration of a first wireless link as a beam-formed wireless link between UE and the small cell base station;

a response component for execution by the processor circuit to cause a beam activation response message destined for the UE
to be transmitted via the backhaul channel coupled with the macro cell base station, the beam activation response message
including beamforming configuration data for the UE to configure transceiver circuitry for the beam-formed wireless link with
the small cell base station; and

an establish component for execution by the processor circuit to cause an exchange of beam training information between the
UE and the small cell base station to establish the beam-formed wireless link as a first connection of a dual connection that
has a second connection over a second wireless link with the macro cell base station, the UE capable of accessing a network
via the dual connection with the macro cell base station serving as a primary cell and the small cell base station serving
as a secondary cell.

US Pat. No. 9,473,878

APPARATUS, METHOD AND SYSTEM OF MANAGING A WEARABLE DEVICE ENSEMBLE

INTEL CORPORATION, Santa...

1. A wearable device comprising:
a memory to store a plurality of device identifiers of a plurality of wearable devices belonging to a wearable device ensemble;
a human body communication (HBC) transceiver to communicate over an HBC network via a body of a user, said HBC transceiver
to receive via said HBC network one or more detected identifiers of one or more detected wearable devices on said body; and

an ensemble manager to manage said wearable device ensemble, and to generate an alert based on a comparison between said one
or more detected identifiers and said plurality of device identifiers.

US Pat. No. 9,280,492

SYSTEM AND METHOD FOR A LOAD INSTRUCTION WITH CODE CONVERSION HAVING ACCESS PERMISSIONS TO INDICATE FAILURE OF LOAD CONTENT FROM REGISTERS

Intel Corporation, Santa...

1. A processor comprising:
an instruction unit to receive a first instruction, wherein the first instruction is to have a source operand to indicate
a source location and a destination operand to indicate a destination location; and

an execution unit to execute the first instruction, wherein execution of the first instruction includes checking, by the processor,
the access permissions of the source location and loading content from the source location into the destination location,
wherein execution of the first instruction succeeds in loading content from the source location into the destination register
if the access permissions of the source location indicate that the content is executable and execution of the first instruction
fails to load content from the source location into the destination register if the access permissions indicate that the content
is not executable.

US Pat. No. 9,280,509

DATA INTERFACE SLEEP MODE LOGIC

INTEL CORPORATION, Santa...

1. An apparatus comprising:
a rising edge detector to detect a rising edge in a signal;
a falling edge detector to detect a falling edge in the signal;
a counter to begin a count to a first value in response to the falling edge detector detecting the falling edge in the signal;
at least one delay unit to delay a start of the count after the falling edge detector detects the falling edge; and
an output unit to generate a sleep signal after the first value is reached when the rising edge detector does not detect the
rising edge in the signal.

US Pat. No. 9,262,163

REAL TIME INSTRUCTION TRACE PROCESSORS, METHODS, AND SYSTEMS

Intel Corporation, Santa...

1. A processor comprising:
at least a first logical processor; and
real time instruction trace (RTIT) logic coupled with the first logical processor, the RTIT logic including:
RTIT packetizer logic to generate RTIT packets for the first logical processor, the RTIT packets to indicate a flow of software
executed by the first logical processor;

an RTIT queue corresponding to the first logical processor, the RTIT queue coupled with the RTIT packetizer logic, the RTIT
queue to store the RTIT packets; and

RTIT queue contents transfer logic coupled with the RTIT queue, the RTIT queue contents transfer logic to transfer the RTIT
packets to memory, wherein the RTIT queue contents transfer logic is implemented predominantly in firmware.

US Pat. No. 9,420,634

USER EQUIPMENT HAVING VIRTUAL MOBILE TERMINALS

Intel Corporation, Santa...

1. A user equipment comprising:
a radio transceiver to communicatively couple the user equipment to a radio access network;
a first virtual mobile terminal to establish a first connection with the radio access network via the radio transceiver;
a second virtual mobile terminal to establish a second connection with the radio access network via the radio transceiver,
wherein the first connection is active concurrent with the second connection to enable transmission or reception of first
data via the first connection simultaneously with transmission or reception of second data via the second connection,

wherein:
the first virtual mobile terminal is configured to use a first communication protocol stack including layer 2 and higher protocol
layers including a first radio resource control (RRC) layer;

the second virtual mobile terminal is configured to use a second communication protocol stack including layer 2 and higher
protocol layers including a second RRC layer; and

both the first virtual mobile and the second virtual mobile terminal are configured to use a common physical layer; and
a combined RRC layer to manage radio procedures of the radio access network for both the first and second virtual mobile terminals,
the combined RRC layer to include state machines that are supersets of state machines of the first and second RRC layers.

US Pat. No. 9,413,364

APPARATUS AND METHOD FOR CLOCK SYNCHRONIZATION FOR INTER-DIE SYNCHRONIZED DATA TRANSFER

Intel Corporation, Santa...

21. An apparatus comprising:
a first phase interpolator;
a delay estimator to be coupled to first and second interconnects and to the first phase interpolator, wherein the delay estimator
is to generate an output according to an estimate of a propagation delay of the first and second interconnects; and

a control logic coupled to the first phase interpolator and to the delay estimator, wherein the control logic is to cause
the first phase interpolator to adjust a parameter according to the output of the delay estimator.

US Pat. No. 9,402,233

DISTRIBUTED ANTENNA SYSTEM AND METHOD FOR ENHANCED POSITIONING

Intel Corporation, Santa...

1. An enhanced Node-B (eNB) to operate as part of a distributed antenna system (DAS) comprising one or more nodes having a
same cell identifier (ID) and operating within a same cell as the eNB, the eNB arranged to:
transmit a user equipment (UE)-specific reference signal and a cell-specific reference signal;
configure one or more of the other nodes of a cell to transmit UE-specific reference signals, each of the UE-specific reference
signals transmitted by each of the one or more of the other nodes being distinguishable from each of the UE-specific reference
signals transmitted by each other node of the one or more of the other nodes and from the UE-specific reference signal that
is transmitted by the eNB, the nodes comprising remote radio heads (RRHs); and

receive location estimate information from a UE that is determined at least in part from the UE-specific reference signals
and the cell-specific reference signal, wherein each of the UE-specific reference signals comprises a channel state information
reference signal (CSI-RS) and the cell-specific reference signal comprises a positioning reference signal (PRS), wherein the
location estimate information comprises an initial location estimate obtained using the received PRS and a PRS received from
one or more other cells, an update of the initial location estimate obtained using the received CSI-RS from the eNB and the
CSI-RSs received from the RRHs of the cell, and feedback indicative of channel estimations, obtained using the CSI-RS from
the eNB and the CSI-RSs from one or more of the RRHs, for use by the eNB and the RRHs for cooperative orthogonal frequency
division multiple access (OFDMA) transmissions.

US Pat. No. 9,391,637

ERROR CORRECTING CODE SCHEME UTILIZING RESERVED SPACE

Intel Corporation, Santa...

1. A method comprising:
maintaining a reserved cache line in a plurality of cache lines to store error correcting code (ECC) data, wherein the reserved
cache line does not have a virtual memory address and the plurality of cache lines other than the reserved cache line have
a virtual memory address;

in response to detection of a data failure associated with one of the plurality of cache lines other than the reserved cache
line, moving ECC data of the one cache line from a memory device into the reserved cache line, the reserved cache line in
a second memory device, and moving data of the one cache line into the memory device.

US Pat. No. 9,332,452

RADIO COMMUNICATION DEVICES AND METHODS FOR CONTROLLING A RADIO COMMUNICATION DEVICE

Intel Deutschland GmbH, ...

1. A radio communication device comprising:
a measurement circuit configured to measure a first reception quality of a first signal from another radio communication device
in a first sub-band and configured to measure a second reception quality of a second signal from the other radio communication
device in a second sub-band different from the first sub-band and configured to measure a third reception quality of a third
signal from the other radio communication device in the first sub-band;

a transmitter configured to transmit first information related to the measured first reception quality;
a determiner configured to determine whether the first information related to the measured first reception quality is valid
or invalid based on the measured third reception quality; and

the transmitter further configured to transmit to the other radio communication device second information related to the measured
second reception quality and third information indicating the determined validity or invalidity of the first information related
to the measured first reception quality.

US Pat. No. 9,298,911

METHOD, APPARATUS, SYSTEM, AND COMPUTER READABLE MEDIUM FOR PROVIDING APPARATUS SECURITY

INTEL CORPORATION, Santa...

1. An apparatus comprising:
at least one processor; and
at least one memory, the at least one memory comprising instructions that when executed by the at least one processor, cause
the apparatus to perform, at least, the following:

receive, at a security module, policy information associated with at least one security exception, wherein the policy information
includes program dependent policy information associated with a program and based, at least in part, on one or more operational
characteristics of the program, one of the operational characteristics including one of a number of external interfaces of
the program, accessibility of code paths to manipulation by data passed through one or more of the external interfaces, a
quality of code in the program, or a performance sensitivity of the program, and wherein the policy information comprises
information indicative of a level of risk associated with the program;

determine that the at least one security exception should be monitored based, at least in part, on the program dependent policy
information;

send a directive to an exception handler to provide an indication if the at least one security exception occurs;
receive the indication, from the exception handler, that the at least one security exception occurred;
determine, at the security module, an operation associated with the at least one security exception and based, at least in
part, on the policy information; and

cause, by the security module, the operation to be performed, based at least in part, on a determination that the at least
one security exception occurred.

US Pat. No. 9,270,386

ERROR DETECTING AND CORRECTING STRUCTURED LIGHT PATTERNS

INTEL CORPORATION, Santa...

1. An imaging system comprising:
a light source;
a patterned mask that is patterned with a coded word which includes an error-correcting code (ECC), wherein the patterned
mask is configured to transmit light emitted by the light source, wherein the transmitted light is structured light that is
encoded with the coded word; and

an imaging input device which is configured to receive the structured light.

US Pat. No. 9,189,302

TECHNIQUE FOR MONITORING ACTIVITY WITHIN AN INTEGRATED CIRCUIT

Intel Corporation, Santa...

1. A processor comprising:
at least one processor core;
hardware-specific monitor logic to monitor hardware-specific events;
a software-accessible register that is to have a plurality of bits, the software-accessible register accessible to software,
wherein each of the plurality of bits is to correspond at a given time to a different software event, wherein a first bit
in the software-accessible register is to store an indication of an occurrence of a corresponding software event in the software
and is to be written by the software when the corresponding software event has occurred in the software to indicate that the
corresponding software event has occurred, and wherein a second bit in the software-accessible register is to store an indication
of an occurrence of a corresponding combination of events including a corresponding software event in the software and a corresponding
hardware-specific event to be monitored by the hardware-specific monitor logic; and

an event counter including hardware, the event counter coupled with the software-accessible register and with the hardware-specific
monitor logic, the event counter to count events associated with the second bit, wherein the event counter is to one of: (1)
start to count after the second bit is set, and stop counting after the second bit is cleared; and (2) count a number of times
the second bit is one of set to 1 and cleared to 0.

US Pat. No. 9,591,758

FLEXIBLE ELECTRONIC SYSTEM WITH WIRE BONDS

Intel Corporation, Santa...

1. An apparatus comprising:
a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit and a
second plurality of bond pads proximate a second edge of the first rigid circuit, wherein the first edge and the second edge
of the first rigid circuit share a common vertex;

a second rigid circuit comprising a third plurality of bond pads proximate to a first edge of the second rigid circuit, the
second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge
of the first rigid circuit;

a third rigid circuit comprising a fourth plurality of bond pads proximate a first edge of the third rigid circuit, the first
edge of the third rigid circuit facing the second edge of the first rigid circuit;

a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and
mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the third plurality of bond pads
such that the first rigid circuit is free to rotate with respect to the second rigid circuit about a rotational axis generally
parallel to the first edge of the first rigid circuit;

a second plurality of wire bonded wires, each wire bonded wire of the second plurality of wire bonded wires electrically and
mechanically connected to a bond pad of the second plurality of bond pads and a bond pad of the fourth plurality of bond pads;
and

a flexible carrier, wherein the first rigid circuit, second rigid circuit, and third rigid circuit are situated on the flexible
carrier.

US Pat. No. 9,563,437

TECHNOLOGIES FOR PRE-MEMORY PHASE INITIALIZATION OF A COMPUTING DEVICE

Intel Corporation, Santa...

1. A computing device for pre-memory phase initialization, the computing device comprising:
a boot management module to execute basic input/output system instructions in response to a startup of the computing device;
a memory detection module to detect the presence of a memory of a Peripheral Component Interconnect Express (PCIe) card of
the computing device for memory access prior to initialization of a main memory of the computing device; and

a memory initialization module to (i) initialize, in response to detection of the memory of the PCIe card, the memory of the
PCIe card as temporary random-access memory for the memory access prior to initialization of the main memory, and (ii) copy
the basic input/output system instructions from a non-volatile memory of the computing device to the temporary random-access
memory of the PCIe card for execution,

wherein the boot management module is further to execute the copied basic input/output system instructions from the temporary
random-access memory of the PCIe card to boot a component of the computing device.

US Pat. No. 9,292,468

PERFORMING FREQUENCY COORDINATION IN A MULTIPROCESSOR SYSTEM BASED ON RESPONSE TIMING OPTIMIZATION

Intel Corporation, Santa...

11. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the
machine to perform a method comprising:
receiving a first response in a first logic of a processor responsive to sending a memory access request to a first memory
coupled to the processor and receiving a second response in the first logic responsive to sending a snoop request to a remote
processor coupled to the processor;

updating a first counter and a second counter based on a delay between receipt of the first response and receipt of the second
response; and

providing data obtained responsive to the memory access request to a requester.

US Pat. No. 9,176,537

CONNECTOR ASSEMBLY FOR AN ELECTRONIC DEVICE

Intel Corporation, Santa...

1. An electronic device, comprising:
a connector assembly positioned within at least a portion of a recess of the electronic device and in engagement with a hinge
assembly of the electronic device, wherein the connector assembly includes:

a first assembly to receive a connector; and
a second assembly to receive an identification module that is to provide an association between a user and the electronic
device.

US Pat. No. 9,622,350

METHOD OF FORMING A CIRCUIT BOARD

Intel Corporation, Santa...

1. A method of forming a circuit board upon which to mount an integrated circuit chip, the method comprising:
forming a first interconnect zone on a surface of the circuit board, the first interconnect zone having a first area on the
surface of the circuit board, the first interconnect zone including a first plurality of contacts having a first pitch at
the surface of the circuit board; and

forming a second interconnect zone on the surface of the circuit board, the second interconnect zone having a second area
on the surface of the circuit board, the second area having an inner perimeter surrounding all sides of an outer perimeter
of the first area on the surface, the second interconnect zone including a second plurality of contacts or traces having a
second pitch at the surface of the circuit board, wherein the first pitch is a distance from a center of one contact of the
first plurality of contacts to a center of an adjacent contact of the first plurality of contacts; and the second pitch is
a distance from a center of a first contact or trace of one of the second plurality of contacts or traces to a center of an
adjacent contact or trace of the second plurality of contacts or traces, and wherein the first pitch is smaller than the second
pitch.

US Pat. No. 9,609,765

CHASSIS OF ELECTRONIC DEVICE

Intel Corporation, Santa...

3. An electronic device to receive power, comprising:
a circuit board to receive a plurality of electrical components, and the circuit board to have a ground area; and
a chassis to support components, the chassis to include:
an inner metal layer to form an inner structure of the chassis;
a first insulating layer on a first portion of the inner metal layer;
a second insulating layer on a second portion of the inner metal layer;
a first connecting metal layer on the first insulating layer, the first connecting metal layer to be connected to the ground
area of the circuit board; and

a second connecting metal layer on the second insulating layer, the second connecting metal layer to be connected to the ground
area of the circuit board, wherein the inner metal layer, the first insulating layer and the first connecting metal layer
to form a first capacitive device.

US Pat. No. 9,504,159

CIRCUIT COMPONENT BRIDGE DEVICE

Intel Corporation, Santa...

1. A bridge device, comprising:
a first via of a bridge device, the first via of the bridge device having a short via stub or no via stub, the first via of
the bridge device to be communicatively coupled to a first via of a printed circuit board (PCB);

a second via of the bridge device, the second via of the bridge device having a short via stub or no via stub, the second
via of the bridge device to be communicatively coupled to a second via of the PCB; and

a trace of the bridge device to communicatively couple the first via of the bridge device to the second via of the bridge
device, wherein each of the short via stubs is defined as a portion of a via having a resonance frequency that is higher than
a Nyquist frequency multiplied by a multiplier that is greater than one.

US Pat. No. 9,395,762

HINGE CONFIGURATION FOR AN ELECTRONIC DEVICE

Intel Corporation, Santa...

1. An electronic device, comprising:
a hinge assembly to removably couple a portion of the electronic device to an accessory, wherein the hinge assembly is to
allow a rotation around an axis of the portion in relation to the accessory when the portion is coupled to the accessory,
the hinge assembly includes a snap to provide a retention force between the portion and the accessory when the portion is
coupled to the accessory, the hinge assembly includes a toothed disc to mate with the accessory to resist rotation between
the portion and the accessory when the portion is coupled to the accessory, and the toothed disc is centered on the axis.

US Pat. No. 9,148,792

DYNAMIC CERTIFICATION SYSTEM FOR WIRELESS SPECTRUM SHARING

Intel Corporation, Santa...

1. A device, comprising:
a communication module to communicate via at least a wireless communication; and
a dynamic certification module to manage operation of the communication module based on a certification, the certification
allowing the communication module to operate in shared wireless spectrum based on at least one of time, device location or
frequency bands;

wherein:
the certification comprises at least one of an electronic certification document or electronic token received in the device
from a cloud spectrum broker/licensed shared access (CSB/LSA) controller;

the dynamic certification module is further to receive a response message from the CSB/LSA controller, the response message
comprising at least available certification information including for each available certification at least a certification
ID, certification validity information and certification region information; and

the dynamic certification module is further to determine if any of the available certifications are usable by the device for
operating in the shared wireless spectrum, and if any of the available certifications are determined to be usable by the device,
to cause an available certification request message to be transmitted to the CSB/LSA controller, the available certification
request message including at least one certification ID corresponding to an available certification.

US Pat. No. 9,648,733

METHOD OF FORMING A SUBSTRATE CORE STRUCTURE USING MICROVIA LASER DRILLING AND CONDUCTIVE LAYER PRE-PATTERNING AND SUBSTRATE CORE STRUCTURE FORMED ACCORDING TO THE METHOD

Intel Corporation, Santa...

1. A multilayer substrate core structure including:
a starting insulating layer having a first side with a first planar surface and an opposite second side with a second planar
surface;

a first patterned conductive layer on the first planar surface of the first side of the starting insulating layer, and a second
patterned conductive layer on the second planar surface of the second side of the starting insulating layer;

a first supplemental insulating layer on the first patterned conductive layer and on the first planar surface of the first
side of the starting insulating layer;

a second supplemental insulating layer on the second patterned conductive layer and on the second planar surface of the second
side of the starting insulating layer;

a first supplemental patterned conductive layer on the first supplemental insulating layer;
a second supplemental patterned conductive layer on the second supplemental insulating layer; and
a set of conductive vias provided in corresponding via openings extending from the second supplemental patterned conductive
layer to the first supplemental patterned conductive layer, the via openings further extending through the first patterned
conductive layer and the second patterned conductive layer, the via openings having a conical configuration providing a wider
opening in the first patterned conductive layer than in the second patterned conductive layer, wherein at least one conductive
via of the set of conductive vias is in electrical contact with the first and second supplemental patterned conductive layers
and with the first and second patterned conductive layers, and wherein the at least one conductive via completely fills the
corresponding via opening and has the conical configuration.

US Pat. No. 9,439,208

SCHEDULING REQUESTS FOR WIRELESS COMMUNICATION DEVICES RUNNING BACKGROUND APPLICATIONS

Intel Corporation, Santa...

1. An apparatus comprising:
communications circuitry configured to communicate with a plurality of user equipments (UEs) over a wireless communication
network; and

scheduling circuitry coupled with the communications circuitry and configured to:
receive, from a first set of UEs of the plurality of UEs, an indicator that the first set of UEs are in a background mode
in which individual UEs of the first set of UEs run one or more background applications and no active applications, wherein
the one or more background applications do not interact with respective users of the individual UEs of the first set of UEs
while the individual UEs are in the background mode; and

assign a scheduling request (SR) allocation to the individual UEs of the first set of UEs based on the indicator that the
first set of UEs are in the background mode, the SR allocations of the individual UEs including resource elements in a common
resource block of a channel, wherein the common resource block is designated for SR allocations of UEs that are in the background
mode.

US Pat. No. 9,411,601

FLEXIBLE BOOTSTRAP CODE ARCHITECTURE

Intel Corporation, Santa...

1. A device, comprising:
equipment to provide functionality in the device;
an operating system (OS) to facilitate operation of the equipment; and
boot circuitry to:
determine, following activation of the device, if the boot circuitry includes at least one flexible boot (FB) circuit;
if it is determined that the boot circuitry includes at least one FB circuit, cause the at least one FB circuit to interact
with at least one of the equipment or the OS, generate device-specific boot operations based on the interaction and perform
the device-specific boot operations; and

perform default boot operations if it is determined that the boot circuitry does not include at least one FB circuit.

US Pat. No. 9,411,651

RDMA (REMOTE DIRECT MEMORY ACCESS) DATA TRANSFER IN A VIRTUAL ENVIRONMENT

Intel Corporation, Santa...

13. A method comprising:
presenting an interface associated with a virtual machine monitor, the interface to facilitate transferring of data from a
first application buffer memory space of a first virtual machine to a second application buffer memory space of a second virtual
machine, the first virtual machine executing a first operating system, the second virtual machine executing a second operating
system, the interface being accessible by the operating systems, the transferring comprising bypassing use of the operating
systems and directly transferring the data from the first application buffer memory space to the second application buffer
memory space without buffering the data, the first application buffer memory space being comprised in a first application,
the second application buffer memory space being comprised in a second application, the first application being comprised
in the first virtual machine, the second application being comprised in the second virtual machine; and

establishing corresponding queue pairs associated with the first and second virtual machines to facilitate the transferring.

US Pat. No. 9,281,401

TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS

INTEL CORPORATION, Santa...

1. An apparatus, comprising:
a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material;
a gate plug disposed between a first portion of a first individual line of the individual lines and a second portion of the
first individual line to isolate gate electrode material of a first transistor device from gate electrode material of a second
transistor device;

a contact electrode material disposed between the first individual line and a second individual line of the individual lines,
wherein at least a portion of the contact electrode material is in direct contact with the gate plug; and

a contact plug disposed between the first individual line and the second individual line to isolate source or drain contacts
of the first transistor device from source or drain contacts of the second transistor device, wherein the contact plug comprises
a first electrically insulative material and the gate plug comprises a second electrically insulative material that has a
different chemical composition than the first electrically insulative material.

US Pat. No. 9,241,282

MINIMIZATION OF DRIVE TESTS UPLINK MEASUREMENTS

Intel Deutschland GmbH, ...

1. An apparatus comprising:
one or more non-transitory, computer readable media including instructions; and
one or more processors coupled with the one or more non-transitory, computer-readable media to execute the instructions to
cause an access node of a radio access network to:

separate a network measurement configuration command into at least first network measurement parameters and second network
measurement parameters, wherein the second network parameters include a first parameter to turn on or off uplink received
interference power (RIP) measurements on a physical layer and a second parameter to provide a threshold value;

forward the first network measurement parameters of the network measurement configuration command over an air interface to
a user equipment to perform first network measurements on downlink communication channels;

receive, from the user equipment, the first network measurements on downlink communication channels to form first network
measurement results;

perform, based on the second network measurement parameters, second network measurements on uplink communication channels
to form second network measurement results, the second network measurement results to include a measured value of RIP;

compare the measured value to the threshold value; and
transmit the second network measurement results to a core network entity based on comparison of the measured value to the
threshold value.

US Pat. No. 9,172,788

DISABLING OF WIRELESS TRANSMISSION OF WIRELESS COMMUNICATION DEVICES USING MESSAGES

INTEL CORPORATION, Santa...

1. An electronic device, comprising:
a memory unit; and
logic including hardware to generate a disabling message to cause disabling of at least a portion of a wireless transceiver
of a communication device that is within a threshold proximity to the electronic device, the disabling message configured
to cause said disabling for a predetermined time period, and the disabling message to be wirelessly transmitted based on the
predetermined time period.

US Pat. No. 9,111,939

METALLIZATION OF FLUOROCARBON-BASED DIELECTRIC FOR INTERCONNECTS

Intel Corporation, Santa...

1. An apparatus comprising:
a semiconductor substrate;
a device layer disposed on the semiconductor substrate, the device layer including one or more transistor devices; and
an interconnect layer disposed on the device layer, the interconnect layer comprising
a fluorocarbon-based dielectric material, and
one or more interconnect structures configured to route electrical signals to or from the one or more transistor devices,
the one or more interconnect structures comprising cobalt (Co), or ruthenium (Ru), or combinations thereof, wherein an individual
interconnect structure of the one or more interconnect structures comprises:

a bulk portion comprising copper (Cu); and
a barrier liner disposed between the bulk portion and the fluorocarbon-based dielectric material, the barrier liner comprising
the Co, or the Ru, or combinations thereof, wherein the barrier liner comprises titanium nitride (TiN) doped with the Co,
or the Ru, or combinations thereof.

US Pat. No. 9,554,454

DEVICES AND METHODS TO REDUCE DIFFERENTIAL SIGNAL PAIR CROSSTALK

Intel Corporation, Santa...

1. A device comprising:
a first pair of differential signal lines comprising a first signal line and a second signal line proximate the first signal
line, the first signal line and the second signal line separated from each other along a first line;

a second pair of differential signal lines comprising a third signal line proximate a fourth signal line, the third signal
line and the fourth signal line separated from each other along a second line generally perpendicular to the first line;

a third pair of differential signal lines including a fifth signal line electrically coupled to the first signal line and
a sixth signal line electrically coupled to the second signal line, wherein the fifth and sixth signal lines are separated
from each other along a line parallel to the first line; and

a fourth pair of differential signal lines including a seventh signal line electrically coupled to the third signal line and
an eighth signal line electrically coupled to the fourth signal line, wherein the seventh and eighth signal lines are separated
from each other along a line parallel to the second line;

wherein the first second, third and fourth airs of differential signal lines are on a same surface of the device.

US Pat. No. 9,497,713

ACCURATE UPLINK POWER CONTROL FOR COMP AND C-RAN

Intel Corporation, Santa...

1. A user equipment (UE) arranged to communicate with an enhanced Node B (eNB) that includes a set including multiple reception
points (RPs), the UE comprising:
a transceiver configured to,
send an uplink power reference signal to the multiple reception points (RPs) of the set of RPs;
receive from the eNB, identification of a subset of the set that includes multiple RPs, the subset including two or more RPs
from the set of RPs, and identification of a downlink reference signal power level for each reference signal to be used by
an RP of the identified subset;

receive downlink reference signals from RPs of the identified subset; and
a processor configured to,
determine a path loss estimate for each received downlink reference signal received from an identified RP of the identified
subset, based at least in part upon the downlink reference signal power level identified for the RP from which the reference
signal is received; and

determine an uplink power level that is a function of the path loss estimates determined for the downlink signals received
from the RPs of the identified subset;

wherein the transceiver and the processor are further configured to,
use the determined uplink power level during communication with the identified RPs.

US Pat. No. 9,471,583

DATA RACE ANALYSIS WITH IMPROVED DETECTION FILTERING

Intel Corporation, Santa...

1. A method, comprising:
receiving a list of two or more data race analysis targets for a computer program, wherein said data race analysis targets
comprise at least one of a source file name, source file line, function name, or variable name;

generating a data race filter for each of said received data race analysis targets, wherein generating said data race filter
set includes:

determining compilands for each of said two or more data race analysis targets;
determining functions contained within each of said compilands;
determining memory address ranges for each function contained within each of said compilands;
removing duplicate memory addresses contained within each of said memory address ranges; and
merging said memory address ranges into a merged list;
in response to generating said data race filter, performing a runtime analysis on said computer program using said data race
filter, said run time analysis includes:

identifying a memory access at a memory address; and
searching said merged list for said memory address; and
in response to said memory address being in said merged list, performing a data race analysis on said memory access.

US Pat. No. 9,389,274

ALTERNATING CURRENT COUPLED ELECTRONIC COMPONENT TEST SYSTEM AND METHOD

Intel Corporation, Santa...

1. An electrical circuit, comprising:
a capacitive element configured to be coupled in series with an electronic package component;
a path resistance electrically coupled to the capacitive element: a driver configured to electrically charge the capacitive
element; and

a voltage detector coupled to the capacitive element and configured to identify a condition of the electronic package component
based on a measured voltage of the capacitive element;

wherein the voltage detector is a component of a decay detector configured to identify the condition of the electronic package
component based on a time for a charge on the capacitive element as coupled in series with the electronic package component
to decay to a predetermined threshold;

wherein the charge on the capacitive element decays to the predetermined threshold in a first time when the electronic package
component has a resistance of approximately zero (0) Ohms and a second time greater than the first time when the electronic
package component has a resistance of greater than zero (0) Ohms;

wherein the first time is indicative of the electronic package component being conforming and the second time is indicative
of the electronic package component being nonconforming.

US Pat. No. 9,378,788

NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE SAME

INTEL CORPORATION, Santa...

1. An apparatus, comprising:
one or more bitlines;
a write driver, coupled to the one or more bitlines, to drive at least one of the one or more bitlines in response to logical
combinations of a write enable signal and a data signal;

a bias capacitor coupled to the one or more bitlines and having an input terminal and an output terminal; and
a multiplexer coupled with the output terminal and the one or more bitlines, wherein the multiplexer is to selectively couple
the output terminal with one of the one or more bitlines in response to one or more of the data signal and an inverted version
of the data signal, the bias capacitor to transfer charge between the input terminal and the output terminal to selectively
drive the coupled one of the one or more bitlines to a negative voltage level in response to a drive signal, wherein the drive
signal is coupled with the input terminal and is a delayed version of the write enable signal.

US Pat. No. 9,305,194

ONE-TOUCH INPUT INTERFACE

INTEL CORPORATION, Santa...

1. A one-touch input interface comprising:
a hybrid Body-Area-Network (BAN) Near-Field-Communication (NFC) module to receive NFC information from a NFC device via a
body of a user, said hybrid BAN NFC module comprises a first BAN electrode configured to be in contact with a first area of
a hand of said user, and a second BAN electrode configured to be in contact with a second area of said hand; and

a fingerprint sensor to sense a fingerprint of said user,
wherein said hybrid BAN NFC module and said fingerprint sensor are to receive said NFC information and to sense said fingerprint
during a touch of said one-touch interface by said user, wherein said hybrid BAN NFC module is configured to be in contact
with the hand of said user, when said fingerprint sensor is to be in contact with a finger of said hand.

US Pat. No. 9,244,496

HINGE CONFIGURATION FOR AN ELECTRONIC DEVICE

Intel Corporation, Santa...

1. An electronic device, comprising:
a hinge assembly to selectively secure a portion of the electronic device to an accessory, wherein:
the hinge assembly is to allow a rotation of the portion in relation to the accessory,
the hinge assembly includes at least one disc to receive at least one segment of the accessory as the hinge assembly is engaged
to secure the portion of the electronic device to the accessory,

the at least one disc includes one or more magnetic rings in the portion, and
the accessory includes one or more magnetic bands to attract the one or more magnetic rings.
US Pat. No. 9,096,953

METHOD FOR HIGH THROUGHPUT, HIGH VOLUME MANUFACTURING OF BIOMOLECULE MICRO ARRAYS

INTEL CORPORATION, Santa...

1. An apparatus configured to make a biomolecule microarray without human intervention, the apparatus comprising a track system,
the track system being configured for inline processing and comprising a spacer attachment module adapted to attach a linker
to a substrate surface of the biomolecule microarray, a coupling module adapted to couple a molecule to the linker, the molecule
being a nucleotide or an amino acid and respectively being capable of forming an amide bond or a phosphodiester bond when
the molecule is not bound to a protecting group that respectively prevents the formation of the amide or phosphodiester bond,
the molecule being bound to the protecting group, and a deprotection module adapted to create deprotection of the protecting
group with a radiation exposure of about 1-50 mJ/cm2;
wherein the deprotection of the protecting group is by generating photo acid in a photoresist comprising poly methyl methacrylate,
Bis(4-tert-butylphenyl)iodonium triflate and isopropylthioxanthenone in propylene glycol methyl ether acetate.

US Pat. No. 9,048,875

CONSERVING COMPUTING RESOURCES DURING ERROR CORRECTION

Intel Corporation, Santa...

1. A system, comprising:
a channel; and
an iterative decoder to decode encoded data on the channel, the iterative decoder configured to:
generate a set of m tuples A, each tuple in set A including a symbol comprising a group of bits of the encoded data and a
probability associated with the symbol; and

decode the encoded data using the set of m tuples, including allocating fewer bits to storage of a probability associated
with a first tuple of the set A than are allocated for storage of a probability associated with a second tuple of the set
A.

US Pat. No. 9,395,806

METHOD AND APPARATUS FOR A POWER-EFFICIENT FRAMEWORK TO MAINTAIN DATA SYNCHRONIZATION OF A MOBILE PERSONAL COMPUTER TO SIMULATE A CONNECTED SCENARIO

Intel Corporation, Santa...

1. A computer comprising:
a display which is operable to turn off;
logic, at least partially implemented in hardware, which is operable to:
control the display;
check for one or more updates to one or more application data associated with one or more applications, the one or more application
data stored on the computer, wherein at least one check is performed while the computer is in a sleep state; and

update the one or more application data stored on the computer in response to the check finding one or more updates to the
one or more application data stored on the computer, wherein the update is performed while the computer is in a sleep state;
and

a wireless device for allowing the computer to receive data associated with the one or more updates while the computer is
in the sleep state.

US Pat. No. 9,351,121

PEER-BASED COLLABORATIVE DISCOVERY AND SIGNALING OF ANOTHER DEVICE IN LIMITED-SIGNAL AREAS

Intel Corporation, Santa...

1. A method comprising: initiating a sensing mode in a seek mobile device in response to receiving an indication that a location
of a lost mobile device is unknown; capturing, by said seek mobile device, first position data if a signal from the lost device
is detected, capturing, by said seek mobile device, second position data in response to losing the signal from the lost device;
and determining, by said seek device, an estimated location of the lost device based on the first position data and the second
position data, wherein the lost device is located in an area of limited or no connectivity and the seek device is moving through
the area.

US Pat. No. 9,258,344

MULTI-HOP SINGLE SIGN-ON (SSO) FOR IDENTITY PROVIDER (IDP) ROAMING/PROXY

Intel Corporation, Santa...

1. An apparatus, comprising:
one or more non-transitory, computer-readable media having instructions; and
one or more processors coupled with the one or more non-transitory, computer-readable media, the one or more processors to
execute the instructions to cause a first identity provider (IdP), which provides a first identity associated with a user,
to operate as a proxy, for a second IdP that provides a second identity associated with the user, to enable the second identity
to be used to obtain authorized access to a service of a service provider that recognizes the first identity,

wherein the service provider is distinct from the first and second IdPs and to operate as the proxy to enable the second identity
to be used to obtain authorized access to the service, the first IdP is to:

receive, from a user equipment (UE), an authentication request for the service, wherein the authentication request is redirected
from the service provider to the apparatus;

send, based on the authentication request, a communication directly to the second IdP to initiate an authentication process
with the second IdP using the second identity; and

if the second identity is determined by the first IdP to be authenticated by the authentication process, send to the service
provider through the UE an assert message associated with the first identity to enable the authorized access to the service.