US Pat. No. 9,148,024

APPARATUSES, SYSTEMS, AND METHODS FOR A MONOTONIC TRANSFER FUNCTION IN WIRELESS POWER TRANSFER SYSTEMS

Integrated Device Technol...

1. A power-transmitting device, comprising:
a frequency generator configured to generate a power-transmit frequency; and
a transmit resonance circuit operably coupled to the power-transmit frequency and comprising:
a transmit coil configured to generate a near-field electromagnetic radiation at a coupling frequency for coupling to a receive
coil within a coupling region of the transmit coil; and

a transmit resonance adjuster operably coupled to the transmit coil and comprising one or more components to generate at least
some of a capacitive portion of the transmit resonance circuit, the one or more components configured to adjust the coupling
frequency to be sufficiently less than the power-transmit frequency such that a monotonic transfer function is developed between
the power-transmit frequency and a power-receiving device bearing the receive coil positioned in the coupling region.

US Pat. No. 9,059,778

FREQUENCY DOMAIN COMPRESSION IN A BASE TRANSCEIVER SYSTEM

Integrated Device Technol...

1. In a base transceiver system of a wireless communication network, a method for transferring signal data from a radio frequency
(RF) unit to a baseband processor over a serial data link, wherein the RF unit is connected to an antenna to receive an analog
signal, the analog signal representing a plurality of antenna-carrier channels, the RF unit including an analog to digital
converter (ADC) that converts the analog signal to a digital signal and a digital down converter (DDC) that downconverts the
digital signal to a plurality of baseband channels, each baseband channel corresponding to one of the antenna-carrier channels
and having a sequence of signal samples, wherein each signal sample includes an in-phase (I) sample and a quadrature (Q) sample,
wherein the baseband processor performs signal processing operations on the signal samples received from the RF unit, the
method comprising:
compressing the signal samples of each baseband channel at the RF unit, wherein for each baseband channel the compressing
comprises:

computing a frequency domain transform of a plurality of the signal samples of each baseband channel at the RF unit to form
a plurality of frequency domain coefficients, wherein the frequency domain coefficients include a real component and an imaginary
component for each of a plurality of frequency bins;

attenuating one or more of the frequency domain coefficients in accordance with an attenuation profile of a plurality of attenuation
profiles to form a plurality of attenuated coefficients, wherein the attenuation profile specifies attenuation levels corresponding
to the frequency bins;

encoding the attenuated coefficients to form compressed coefficients;
measuring an output bit rate of the compressed coefficients;
determining an error between the output bit rate and a target bit rate; and
adjusting at least one of the attenuation levels based on the error by selecting a different attenuation profile based on
the error between the output bit rate and a target bit rate;

formatting the compressed coefficients of the plurality of baseband channels for transfer over the serial data link; and
transferring the compressed coefficients over the serial data link.

US Pat. No. 9,525,408

HIGH SPEED, LOW POWER, ISOLATED MULTIPLEXER

INTEGRATED DEVICE TECHNOL...

1. A multiplexer comprising:
a first multiplexer comprising:
a first output;
a first input circuit that receives a first input;
a first selection circuit that enables and disables the first input circuit to provide the first input to the first output;
a first disabling circuit that additionally disables the first input circuit also disabled by the first selection circuit;
a second input circuit that receives a second input;
a second selection circuit that enables and disables the second input circuit to provide the second input to the first output;
a second disabling circuit that additionally disables the second input circuit also disabled by the second selection circuit;
and

a third disabling circuit that additionally disables the first and second input circuits when the first and second input circuits
are disabled by the first and second selection circuits.

US Pat. No. 9,369,270

DUAL-COUPLED PHASE-LOCKED LOOPS FOR CLOCK AND PACKET-BASED SYNCHRONIZATION

INTEGRATED DEVICE TECHNOL...

1. An integrated circuit device, comprising:
a pair of coupled phase-locked loops including a first phase-locked loop responsive to a first clock and a second phase-locked
loop configured to track the first clock through the first phase-locked loop when said second phase-locked loop is disposed
in a holdover mode of operation and in a locked mode of operation, said first phase-locked loop comprising a first loop filter
and a first oscillator responsive to a first output signal generated by the first loop filter and said second phase-locked
loop comprising a second loop filter responsive to a second output signal generated by the first loop filter;

wherein the first loop filter comprises a low-pass filter; and
wherein said first phase-locked loop is configured to support a first programmable mode whereby the first and second output
signals generated by the first loop filter are equivalent and a second programmable mode whereby the second output signal
is generated by the low-pass filter but the first output signal is not.

US Pat. No. 9,065,459

CLOCK GENERATION CIRCUITS USING JITTER ATTENUATION CONTROL CIRCUITS WITH DYNAMIC RANGE SHIFTING

Integrated Device Technol...

1. An apparatus comprising:
a phase locked loop (PLL) circuit configured to generate a PLL output signal from an oscillator signal and controlled based
on a control signal applied to a control input of the PLL circuit; and

an adaptive control circuit configured to generate a measure of a difference between an input clock signal and the PLL output
signal and to apply an offset to the measure to generate the control signal, wherein the offset varies based on a relationship
of the measure to a reference, wherein the adaptive control circuit is configured to generate the measure at a greater rate
than an update rate of the offset.

US Pat. No. 9,154,147

SYSTEMS AND METHODS FOR ESTIMATION OF OFFSET AND GAIN ERRORS IN A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER

INTEGRATED DEVICE TECHNOL...

1. A time-interleaved analog-to-digital converter system comprising:
a plurality of digitizer channels;
an offset error estimation unit coupled between a first channel and a second channel of the plurality of channels, the offset
error estimation unit including a subtractor that determines a difference between a sign of a first signal from the first
channel and a sign of a second signal of the second channel and an integrator coupled to integrate the difference and provide
an offset error; and

a gain error estimation unit coupled between the first channel and the second channel.

US Pat. No. 9,479,182

METHODS AND APPARATUS FOR SYNCHRONIZING OPERATIONS USING SEPARATE ASYNCHRONOUS SIGNALS

INTEGRATED DEVICE TECHNOL...

1. A method of synchronizing operations between integrated circuits, comprising:
transmitting a first periodic reference signal from a first transmitter associated with a first integrated circuit of a first
system, to a receiver associated with a second integrated circuit of a second system;

receiving a second periodic reference signal from a second transmitter associated with a third integrated circuit of the second
system;

receiving at the first system a first phase difference determined by the second system, wherein the first phase difference
is determined between the first periodic reference signal at the second system and the second periodic reference signal at
the second system;

determining a second phase difference at the first system, wherein the second phase difference is determined between the first
periodic reference signal at the first system and the second periodic reference signal at the first system; and

determining a difference between the first phase difference and the second phase difference.

US Pat. No. 9,374,078

MULTI-BIT CELL ATTENUATOR

INTEGRATED DEVICE TECHNOL...

1. A device comprising:
a step attenuator having a range of attenuation levels and comprising a first cell, where a cell is selectable to provide
one or more cell attenuation levels;

the first cell comprising:
a plurality of first attenuation arms between node set A; and
a plurality of second attenuation arms between node set B,
where node set A and node set B are different, and
where each of the plurality of first attenuation arms and each of the plurality of second attenuation arms are selectable
to enable or disable them independently in the step attenuator in a plurality of different combinations comprising at least
one of the plurality of first attenuation arms and at least one of the plurality of second attenuation arms to provide a plurality
of first cell attenuation levels,

wherein the first cell is configured for hybrid intra cell operation or in combination with at least one other cell for hybrid
inter cell operation that reduces binary operated glitches and thermometer operated insertion loss in the intra cell or inter
cell operation.

US Pat. No. 9,407,268

LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) DRIVER WITH DIFFERENTIAL OUTPUT SIGNAL AMPLITUDE REGULATION

INTEGRATED DEVICE TECHNOL...

1. A method of regulating an output voltage amplitude of a low voltage differential signaling (LVDS) driver, the method comprising:
receiving a differential output signal from a switched-polarity current generator of an LVDS driver at an output voltage amplitude
regulator of an LVDS driver;

detecting an output voltage amplitude of the differential output signal;
detecting a common mode voltage of the differential output signal;
subtracting the common mode voltage from the output voltage amplitude;
comparing the output voltage amplitude to a reference voltage at the output voltage amplitude regulator after the subtracting
the common mode voltage from the output voltage amplitude; and

regulating a steering current of the LVDS driver based upon the comparison between the output voltage amplitude and the reference
voltage to regulate an amplitude of the differential output signal at one or more loads of the LVDS driver.

US Pat. No. 9,236,967

METHODS OF PACKET-BASED SYNCHRONIZATION IN NON-STATIONARY NETWORK ENVIRONMENTS

INTEGRATED DEVICE TECHNOL...

1. A method of packet-based synchronization in non-stationary network environments, comprising:
accumulating timestamps transmitted in packets between master and slave devices, which are synchronized with respective master
and slave clocks and separated from each other by a packet network;

determining whether first timestamps accumulated in a first direction (master-to-slave) across the packet network demonstrate
that a first packet delay variation (PDV) sequence observed from the first timestamps is stationary, using a first statistics-based
stationarity-check algorithm for the first direction; and

estimating at least one of frequency skew and phase offset between the master and slave clocks from the first timestamps accumulated
in the first direction;

wherein in the event the first packet delay variation (PDV) sequence observed from the first timestamps is not stationary,
then said determining is followed by accumulating additional timestamps transmitted in packets between the master and slave
devices and then determining whether second timestamps accumulated in a second direction (slave-to-master) demonstrate that
a second packet delay variation (PDV) sequence observed from the second timestamps is stationary, using a second statistics-based
stationarity-check algorithm for the second direction that is different from the first statistics-based stationarity-check
algorithm.

US Pat. No. 9,118,333

SELF-ADAPTIVE MULTI-MODULUS DIVIDERS CONTAINING DIV2/3 CELLS THEREIN

INTEGRATED DEVICE TECHNOL...

1. An integrated circuit device, comprising:
a multi-modulus divider comprising a cascaded chain of div2/3 cells configured to support a chain length control operation
that precludes generation of an intermediate divisor in response to a change in value of a chain length control byte during
an update time interval and freezes one or more of the div2/3 cells not participating in a divide-by-N operation in a power
saving mode of operation, where N is a positive integer greater than one; each of a plurality of the div2/3 cells in the cascaded
chain has a first terminal responsive to a respective bit of the chain length control byte and a second terminal responsive
to a respective bit of a multi-bit stage number control (SNC) byte; and each of a plurality of bits of the SNC byte is derived
exclusively from a respective Boolean combination of a plurality of bits of the chain length control byte.

US Pat. No. 9,336,896

SYSTEM AND METHOD FOR VOLTAGE REGULATION OF ONE-TIME-PROGRAMMABLE (OTP) MEMORY PROGRAMMING VOLTAGE

INTEGRATED DEVICE TECHNOL...

1. A method of providing a programming voltage to a one-time-programmable (OTP) memory of an integrated circuit, the method
comprising:
receiving an external voltage, having an external voltage level, at a supply voltage pin of an integrated circuit, the external
voltage level equal to a normal operating voltage level for the integrated circuit or to an OTP programming voltage level
for an OTP memory of the integrated circuit;

if the external voltage level received at the supply voltage pin is the normal operating voltage level for the integrated
circuit, providing the external voltage to the OTP memory of the integrated circuit and to internal circuitry of the integrated
circuit; and

if the external voltage level received at the supply voltage pin is an OTP programming voltage level, providing the external
voltage to the OTP memory of the integrated circuit and regulating the external voltage level to the normal operating voltage
level of the integrated circuit to establish a normal operating voltage and providing the normal operating voltage to the
internal circuitry of the integrated circuit.

US Pat. No. 9,236,873

FRACTIONAL DIVIDER BASED PHASE LOCKED LOOPS WITH DIGITAL NOISE CANCELLATION

Integrated Device Technol...

1. A phase-locked loop (PLL) integrated circuit, comprising:
a fractional divider configured to generate a periodic PLL output signal in response to a first periodic reference signal,
said fractional divider comprising a digital control circuit responsive to a digital control input signal and a multi-modulus
divider (MMD) responsive to the first periodic reference signal and a first digital control output signal generated by said
digital control circuit;

a feedback divider (FD) configured to generate a periodic FD output signal in response to a periodic MMD output signal generated
by the MMD;

a digital phase detector (PD) configured to generate a PD output signal in response to the FD output signal and a second periodic
reference signal, which are received at respective first and second inputs thereof; and

a digital loop filter configured to generate the digital control input signal in response to the phase detector output signal
as modified by a noise cancellation signal that is generated by said digital control circuit to at least partially compensate
for non-random deterministic noise in the MMD output signal.

US Pat. No. 9,203,769

METHOD AND APPARATUS FOR CONGESTION AND FAULT MANAGEMENT WITH TIME-TO-LIVE

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
a plurality of ingress ports, wherein each of said plurality of ingress ports has a plurality of ingress buffers:
a switch fabric having a plurality of crosspoint buffers, wherein one or more of said plurality of ingress ports is in operative
communication with one or more of said plurality of crosspoint buffers;

a plurality of egress ports, wherein each of said plurality of egress ports has a plurality of egress buffers, wherein one
or more of said plurality of egress ports is in operative communication with one or more of said plurality of crosspoint buffers;

a time-to-live logic block for each of said plurality of egress ports and in operative communication with said each of said
plurality of egress ports; and

a set of time-to-live registers for each of said time-to-live logic block for each of said plurality of egress ports and in
operative communication with said each of said time-to-live logic block.

US Pat. No. 9,398,489

METHOD AND APPARATUS FOR CONTEXT BASED DATA COMPRESSION IN A COMMUNICATION SYSTEM

INTEGRATED DEVICE TECHNOL...

1. A system comprising:
a compressed data packet generator configured to compress a plurality of uncompressed signal streams based upon one or more
compression parameters associated with each of the plurality of uncompressed signal streams to form a plurality of compressed
signal streams;

a dynamic context resource module coupled to the compressed data packet generator and configured to measure a compression
performance level of a most recent compressed data packet of each of the plurality of compressed signal streams to generate
a signal stream compression performance level for each of the plurality of compressed signal streams, to calculate one or
more dynamic compression performance indicators from each of the measured signal stream compression performance levels and
a desired performance level; and

a compression parameter estimation module coupled to the dynamic context resource module, the compression parameter estimation
module including a plurality of compression parameter estimation paths, operating in parallel, each of the plurality of compression
parameter estimation paths comprising a filter and an encoded packet size and energy calculator, the compression parameter
estimation module configured to use the plurality of compression parameter estimation paths and the one or more dynamic compression
performance indicators to determine one or more adjusted compression parameters if the corresponding compressed signal stream
does not exhibit the desired performance level, the one or more adjusted compression parameters applied to the corresponding
uncompressed signal stream during the compression of the next uncompressed data packet of the corresponding uncompressed signal
stream.

US Pat. No. 9,397,151

PACKAGED INTEGRATED CIRCUITS HAVING HIGH-Q INDUCTORS THEREIN AND METHODS OF FORMING SAME

INTEGRATED DEVICE TECHNOL...

1. A packaged integrated circuit, comprising:
an integrated circuit substrate; and
a packaging cap bonded to an upper surface of said integrated circuit substrate, said packaging cap having a recess therein
that at least partially defines an interior of a sealed cavity extending between said packaging cap and the upper surface
of said integrated circuit substrate and is at least partially lined with at least one segment of an inductor, which is exposed
to the sealed cavity;

wherein said packaging cap comprises a magnetic material therein that increases an effective inductance of the inductor relative
to an otherwise equivalent packaging cap and inductor combination that is devoid of the magnetic material;

wherein the inductor and the magnetic material are electrically disconnected from each other; and
wherein the sealed cavity extends between the magnetic material and the upper surface of said integrated circuit substrate.

US Pat. No. 9,055,472

TRANSMISSION OF MULTIPROTOCOL DATA IN A DISTRIBUTED ANTENNA SYSTEM

Integrated Device Technol...

1. A gateway arranged for an addressed packet protocol including packets having destination addresses and a time division
multiplexed container protocol configured for a communication with an access point, the gateway comprising:
a plurality of data ports, including a first port configured for data communications according to the addressed packet protocol
with end stations accessible through the access point, a second port configured for data communications according to the time
division multiplexed container protocol and a third port configured for data communications according to the time division
multiplexed container protocol between the gateway and the access point; and

a processor coupled to the plurality of data ports, the processor including logic to process downlink data packets from the
addressed packet protocol carrying destination addresses of the end stations accessible through the access point and downlink
containers including signal samples from the time division multiplexed container protocol, the logic further configured to
map the downlink data packets and the signal samples to one or more downlink mixed-data frames, the one or more downlink mixed-data
frames having a frame structure in accordance with the time division multiplexed container protocol, each of the one or more
downlink mixed-data frames including a first set of output containers, in a user data portion of the one or more downlink
mixed-data frames, carrying respective bits of the data bits of the downlink data packets and a second set of output containers,
in a user data portion of the one or more downlink mixed-data frames, carrying respective groups of the signal samples from
the downlink containers, and the processor further configured to transmit the downlink mixed-data frames on the third port.

US Pat. No. 9,236,871

DIGITAL FILTER FOR PHASE-LOCKED LOOP INTEGRATED CIRCUITS

Integrated Device Technol...

1. A phase-locked loop integrated circuit, comprising:
an analog-to-digital converter (ADC) responsive to a control voltage at an input thereof;
a digital-to-analog converter (DAC) having an input responsive to an ADC output signal generated at an output of said ADC,
said DAC input directly receiving a digital signal that retains all material digital information contained in the ADC output
signal; and

an impedance element having real and reactive components, a first current carrying terminal electrically coupled to an output
of said DAC and a second current carrying terminal electrically shorted to the input of said ADC, said first current carrying
terminal directly receiving an analog signal that retains all material analog information contained in a DAC output signal
generated at the output of said DAC.

US Pat. No. 9,112,410

APPARATUSES AND SYSTEM HAVING SEPARATE POWER CONTROL AND TIMING CONTROL OF A POWER CONTROL SYSTEM AND RELATED METHOD

INTEGRATED DEVICE TECHNOL...

1. A power control device, comprising:
a power control chip, including:
a power control module configured to:
generate a power stage control signal indicating an offset between an output voltage and a reference voltage;
externally transmit the power stage control signal to an external power stage having a timing control module that is physically
separate from the power control module and external to the power control chip, the power stage control signal being a non-PWM
signal that is sufficient for use by the timing control module to determine a duty cycle of PWM timing signals driving the
external power stage; and

modulate the power stage control signal to include power stage control information and clock synchronization information within
a single signal, wherein the power stage control information is used by the timing control module to determine the duty cycle
of the PWM timing signals, and the clock synchronization information is used by the external power stage to operate according
to a master clock; and

an output pin through which the power stage control signal is transmitted.

US Pat. No. 9,485,688

METHOD AND APPARATUS FOR CONTROLLING ERROR AND IDENTIFYING BURSTS IN A DATA COMPRESSION SYSTEM

INTEGRATED DEVICE TECHNOL...

1. A method for data compression and decompression in a communication system, the method comprising:
specifying a packet size variable for a data compression session, the packet size variable identifying the number of signal
samples in an uncompressed data packet of the data compression session;

specifying a packet size usage variable for the data compression session, the packet size usage variable indicating if the
packet size of the uncompressed data packets of the data compression session is static or dynamic;

receiving a data burst at a compressor during the data compression session, the data burst comprising a plurality of uncompressed
data packets, each of the uncompressed data packets comprising a plurality of signal samples;

generating a start of burst parameter and a packet size parameter for each of the plurality of uncompressed data packets;
and

compressing the plurality of uncompressed data packets of the data burst to generate a plurality of compressed data packets,
each of the plurality of compressed data packets comprising a header and a payload, the header of each of the plurality of
compressed data packets comprising the start of burst parameter for the uncompressed data packet, the packet size parameter
for the uncompressed data packet and a synchronization field, the synchronization field identifying the start of the compressed
data packet, wherein the packet size parameter and the synchronization field from the header of each of the plurality of compressed
data packets are used to reestablish synchronization between the compressor and a decompressor when a synchronization error
occurs.

US Pat. No. 9,369,139

FRACTIONAL REFERENCE-INJECTION PLL

INTEGRATED DEVICE TECHNOL...

1. A low noise fractional reference-injection phase locked loop (FRIPLL), comprising:
a ring voltage controlled oscillator (VCO);
a fractional interpolative frequency divider (FIFD), an output of the ring VCO is input to the FIFD;
a signal comparison circuit receives a reference clock signal and a further delayed output of the FIFD, the signal comparison
circuit produces a control voltage signal in response to a phase difference between the reference clock signal and the further
delayed output of the FIFD, the control voltage signal is input to the ring VCO to control a ring VCO frequency; and

an oscillator control circuit has a first input and a second input, the first input is a first delayed output of the FIFD
and the second input is the reference clock signal, the oscillator control circuit generates a realignment signal which is
used to realign a state transition in the ring VCO output signal to the reference clock signal when the ring VCO output signal
is in a low state, realignment occurs repeatedly at a frequency of the reference clock signal, wherein oscillator phase noise
is reduced because of the realignment of the state transition.

US Pat. No. 9,166,835

SYSTEMS AND METHODS FOR PEAK DETECTION IN AUTOMATIC GAIN CONTROL CIRCUITS IN HIGH-SPEED WIRELINE COMMUNICATIONS

INTEGRATED DEVICE TECHNOL...

1. A system for peak detection in high-speed wireline communications, the system comprising:
a reference generator configured to generate a reference signal;
an error amplifier coupled to an output of the reference generator to receive the reference signal, the error amplifier also
receiving an input signal;

an operational amplifier coupled to the error amplifier, the operational amplifier configured to generate one or more pulses
based on a comparison of the reference signal and the input signal; and

a pulse counter coupled to an output of the operational amplifier, the pulse counter counting the one or more pulses received
in an operational clock cycle of the pulse counter.

US Pat. No. 9,136,764

APPARATUSES AND SYSTEM AND METHOD FOR AUTO-CONFIGURATION OF A POWER CONTROL SYSTEM

Integrated Device Technol...

1. A power control device, comprising:
a power control module configured to generate a power stage control signal indicating an offset between an output voltage
and a reference voltage, and to externally transmit the power stage control signal to an external power stage having a timing
control module that is physically separate from the power control module, the output voltage generated by the external power
stage to power a load; and

an auto-configuration module configured to communicate with the external power stage and request auto-configuration information
from the external power stage.

US Pat. No. 9,444,566

METHODS OF PERFORMING TIME-OF-DAY SYNCHRONIZATION IN PACKET PROCESSING NETWORKS

INTEGRATED DEVICE TECHNOL...

1. A method of performing time-of-day synchronization in a packet processing network, comprising:
accumulating timestamps transmitted in packets between master and slave devices, which are synchronized with respective master
and slave clocks;

determining whether first timestamps accumulated in a first direction across the packet network demonstrate that a first packet
delay variation (PDV) sequence observed from the first timestamps is stationary;

adjusting a phase offset between the master and slave clocks using a time-of-day estimation algorithm, said adjusting comprising
determining a location-dependent statistic of the first PDV sequence; and

comparing a distribution of the first PDV sequence against distributions associated with a library of stored PDV sequences
to determine a match therebetween.

US Pat. No. 9,270,280

HALF-INTEGER FREQUENCY DIVIDERS THAT SUPPORT 50% DUTY CYCLE SIGNAL GENERATION

INTEGRATED DEVICE TECHNOL...

1. A frequency divider, comprising:
a multi-modulus divider comprising a cascaded chain of div2/3 cells, which is responsive to a multi-bit modulus control signal;
a phase control circuit configured support half-integer frequency division by said multi-modulus divider by providing an input
terminal of said multi-modulus divider with a periodically phase-flipped input signal having a first frequency; and

a duty-cycle adjustment circuit configured to adjust a duty cycle of a divider output signal generated at an output terminal
of said multi-modulus divider and driving said phase control circuit with a control signal that synchronizes timing of the
periodically phase-flipped input signal.

US Pat. No. 9,143,346

METHOD AND APPARATUS FOR A CONFIGURABLE PACKET ROUTING, BUFFERING AND SCHEDULING SCHEME TO OPTIMIZE THROUGHPUT WITH DEADLOCK PREVENTION IN SRIO-TO-PCIE BRIDGES

INTEGRATED DEVICE TECHNOL...

1. A method for bridging between a Serial RapidIO® (SRIO) port and a PCI Express® (PCIe) port the method comprising:
checking for a backpressure for packet types denoted Messaging Response (MR), Maintenance Write Response (MWR), Doorbell Maintenance
(DB), Messaging (M), Posted (P), Completion (CPL), Non-Posted (NP), and RFDID where RFDID is: R: Reserved Ftype 0, 1, 3, 4, 12, 14; F: Flow control (Ftype 7); D: Data Streaming Ftype 9; ID: Implementation Defined (Ftype 15) on said SRIO port;

when there is said backpressure for packet types then passing packet types to said PCIe port based on predefined rules during
dequeue operations in said SRIO port,

wherein said dequeue operations uses a dequeue block directly coupled to a circular-reorder queue (CRQ), said CRQ implemented
in hardware and having a last-free-location pointer to an open location in said CRQ, a next-to-send pointer in said CRQ, a
first-free-location pointer in said CRQ, and a last-packet-enqueued pointer in said CRQ, and wherein said CRQ has an acknowledgement
identification for each of said received packet types; and

when there is no said backpressure for packet types then dequeuing packets strictly in a time ordered sequence in said SRIO
port wherein said dequeue packets uses a dequeue block directly coupled to a circular-reorder queue (CRQ), said CRQ implemented
in hardware and having a last-free-location pointer to an open location in said CRQ, a next-to-send pointer in said CRQ, a
first-free-location pointer in said CRQ, and a last-packet-enqueued pointer in said CRQ.

US Pat. No. 9,092,217

POWER MANAGEMENT INTEGRATED CIRCUIT USING A FLEXIBLE SCRIPT-BASED CONFIGURATOR AND METHOD FOR POWER MANAGEMENT

Integrated Device Technol...

1. A power management integrated circuit, comprising:
a microprocessor;
a non-volatile memory accessible by the microprocessor for storing programs executable by the microprocessor;
a random access memory accessible by the microprocessor; and
a plurality of power regulators providing a plurality of regulated output voltages from the power management integrated circuit,
each power regulator being coupled to a register-controlled bus and thereby to the microprocessor and at least one power regulator
providing a regulated output voltage to an external device, and wherein an external interface allows the external device to
directly communicate through the register-controlled bus to the plurality of power regulators such that each power regulator
is controllable by the microprocessor and the external device over the register-controlled bus,

wherein the microprocessor accesses a scripted configuration file descriptive of power requirements of a system in which the
power management integrated circuit is deployed,

wherein each of the plurality of power regulators is provided a register address and the microprocessor and the external device
control register contents sent to the register address through the register-controlled bus; and
wherein the microprocessor controls the plurality of power regulators during a power-up sequence of the external device, and
the external device controls the plurality of power regulators after the power-up sequence.

US Pat. No. 9,935,591

METHOD AND APPARATUS FOR CURRENT STEERING IN HIGH SENSITIVITY, HIGH LINEARITY AND LARGE DYNAMIC RANGE HIGH SPEED TRANS-IMPEDANCE AMPLIFIERS

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a core trans-impedance amplifier (TIA), wherein the core TIA includes:
an input for receiving an input signal;
gain control circuitry;
feedback loop circuitry;
an output for outputting an output signal;
a second stage amplifier configured to receive the output signal of the core TIA and further configured to output a second stage amplifier output signal; and
an output buffer configured to receive the second stage amplifier output signal,
wherein the gain control circuitry is configured to receive and perform gain control on the input signal by steering current in at least one of a first direction and a second direction using one or more electrical components, and
wherein the feedback loop circuitry is arranged between the gain control circuitry and the input, and is configured to maintain constant feedback voltage of the core TIA.

US Pat. No. 9,431,968

METHODS AND APPARATUSES FOR SLEW RATE ENHANCEMENT OF AMPLIFIERS

INTEGRATED DEVICE TECHNOL...

1. A circuit to enhance slew rate, comprising:
an amplifier comprising a positive input operably coupled to a first side of an amplifier differential pair, a negative input
operably coupled to a second side of the amplifier differential pair, and an output;

a first slew direction enhancer comprising a first differential pair, wherein the first differential pair has a first transistor
and a second transistor, is operably coupled to the positive input and the negative input is configured to cause the first
slew direction enhancer to provide additional current for the first side of the amplifier differential pair during an offset
in a first direction between the positive input and the negative input, and wherein a gate length of the first transistor
is shorter than a gate length of the second transistor to detect the offset in the first direction after the amplifier differential
pair detects the offset in the first direction; and

a second slew direction enhancer comprising a second differential pair operably coupled to the positive input and the negative
input, wherein the second differential pair is configured to cause the second slew direction enhancer to provide additional
current for the second side of the amplifier differential pair during an offset in a second direction between the positive
input and the negative input.

US Pat. No. 9,313,300

METHODS AND APPARATUSES FOR A UNIFIED COMPRESSION FRAMEWORK OF BASEBAND SIGNALS

INTEGRATED DEVICE TECHNOL...

1. A method to compress data for transmission over a serial data link, the method comprising:
distributing a target compression ratio across a plurality of processes, wherein a parameter estimation processor assigns
a compression ratio contribution to each process and a sum of the compression ratio contributions is approximately equal to
the target compression ratio;

resampling input data in a first process to generate resampled input data, the resampling accomplishes a first compression
ratio contribution toward achieving the target compression ratio;

attenuating the resampled input data to generate attenuated resampled input data, the attenuating accomplishes a second compression
ratio contribution toward achieving the target compression ratio;

removing redundancy from the attenuated resampled input data to generate shortened attenuated resampled input data, the removing
accomplishes a third compression ratio contribution toward achieving the target compression ratio, a shortened attenuated
resampled input data results from the removing; and

encoding the shortened attenuated resampled input data in a fourth process to generate encoded compressed data, the encoding
accomplishes a fourth compression ratio contribution toward achieving the target compression ratio, encoded compressed data
results from the encoding, wherein degradation of the encoded compressed data is reduced by the distributing.

US Pat. No. 9,445,536

CRYSTAL OSCILLATOR FABRICATION METHODS USING DUAL-DEPOSITION OF MOUNTING CEMENT AND DUAL-CURING TECHNIQUES

INTEGRATED DEVICE TECHNOL...

1. A crystal oscillator fabrication method, comprising:
depositing electrically conductive mounting cement onto first and second electrically conductive mounting pads on a substrate
to thereby define first and second electrode adhesion bumps thereon;

electrically connecting first and second electrodes of a crystal oscillator to the first and second mounting pads, respectively,
by contacting the first and second electrodes to the first and second electrode adhesion bumps, respectively; then

curing the first and second electrode adhesion bumps; then
depositing electrically conductive mounting cement onto the first electrode and onto a portion of the first electrode adhesion
bump to thereby define a top electrode adhesion extension; and then

curing the top electrode adhesion extension.

US Pat. No. 9,090,451

MICROELECTROMECHANICAL RESONATORS HAVING OFFSET [100] AND [110] CRYSTAL ORIENTATIONS

INTEGRATED DEVICE TECHNOL...

1. A thin-film piezoelectric-on-silicon (TPoS) resonator containing a single resonating element therein, comprising:
a substrate; and
a resonator body suspended over said substrate by at least a first pair of fixed tethers that attach to first and second ends
of said resonator body, said resonator body comprising monocrystalline silicon having a [100] crystallographic orientation
offset by ┬▒? degrees relative to a nodal line of said resonator body when said resonator body is operating at a resonant frequency,
where ? is a real number in a range from about 5 to about 19 and has a value selected to generally passively minimize a total
frequency variation range (TFVR) associated with the TPoS resonator when operating at the resonant frequency, and the nodal
line corresponds to the tether-to-tether axis extending between the first and second ends of said resonator body.

US Pat. No. 9,369,149

METHOD AND APPARATUS FOR EFFICIENT BASEBAND UNIT PROCESSING IN A COMMUNICATION SYSTEM

INTEGRATED DEVICE TECHNOL...

1. A method for processing data in a baseband unit of a communication system, the method comprising:
receiving compressed data at a baseband unit, the compressed data received from at least one radio unit, wherein the baseband
unit is separated from the at least one radio unit;

coupling the compressed data to a switch of the baseband unit;
distributing the compressed data to one of a plurality of network server or storage cards of the baseband unit through the
switch when the compressed data is to be stored;

determining if one or more of a plurality of baseband processing cards of the baseband unit are capable of performing decompression
of the compressed data;

if one or more of the plurality of baseband processing cards are not capable of performing decompression of the compressed
data, running the switch at a first speed to decompress the compressed data at the switch and to distribute the decompressed
data to one of the plurality of baseband processing cards of the baseband unit through the switch;

if one or more of the plurality of baseband processing cards are capable of performing decompression of the compressed data,
running the switch at a second speed to distribute the compressed data to one of the plurality of baseband processing cards
of the baseband unit through the switch, wherein the second speed is lower than the first speed, and decompressing the compressed
data at the one of the plurality of baseband processing cards of the baseband unit; and

processing the decompressed data at one of the plurality of baseband processing cards.

US Pat. No. 9,306,537

INTEGRATED CIRCUIT DEVICE SUBSTRATES HAVING PACKAGED CRYSTAL RESONATORS THEREON

INTEGRATED DEVICE TECHNOL...

1. An integrated circuit device, comprising:
an integrated circuit substrate having an at least two piece package thereon, said package having a hermetically sealed cavity
therein and a crystal resonator within the cavity, said crystal resonator comprising a crystal blank and first and second
electrodes on first and second opposing sides of the crystal blank;

wherein said package comprises a base having a recess therein and a cap hermetically sealed to the base, said cap having first
and second electrical traces thereon, which are electrically connected to the first and second electrodes of the crystal resonator,
respectively, and exposed to an interior of the cavity; and

wherein the base comprises at least first and second electrically conductive vias therein that are electrically connected
to the first and second electrical traces, respectively, by a pair of electrically conductive solder connectors, which extend
across the cavity from the first and second electrically conductive vias in the base to the first and second electrical traces
on the cap.

US Pat. No. 9,240,803

COMPRESSION OF BASEBAND SIGNALS IN BASE TRANSCEIVER SYSTEM PROCESSORS

INTEGRATED DEVICE TECHNOL...

1. A baseband processor for a wireless communication network, comprising:
an interface for a bi-directional serial data channel carrying serial data streams including corresponding incoming and outgoing
sequences of data structures, at least some of the data structures in the sequence holding compressed in-phase (I) and quadrature
(Q) signal samples for a plurality of baseband antenna-carrier channels of the wireless communication network;

logic coupled to the interface to assemble the outgoing sequences of data structures from a plurality of sequences of compressed
I and Q signal samples corresponding to the plurality of baseband antenna-carrier channels, and to disassemble the incoming
sequences of data structures, to recover a plurality of sequences of compressed I and Q signal samples corresponding to the
plurality of baseband antenna-carrier channels;

compression and decompression logic arranged to compress I and Q signal samples of the plurality of baseband antenna-carrier
channels to provide the sequences of compressed I and Q signal samples for outgoing sequences, and arranged to decompress
the sequences of compressed I and Q signal samples to provide decompressed I and Q signal samples of the plurality of baseband
antenna-carrier channels for incoming sequences; and

a signal processor coupled to the compression and decompression logic including logic to process decompressed sequences of
I and Q signal samples for respective baseband antenna-carrier channels of the plurality of baseband antenna-carrier channels
to form corresponding uplink subscriber signals for transmission on an external network, and logic to process downlink subscriber
signals for corresponding channels to provide sequences of I and Q signal samples of the plurality of baseband antenna-carrier
channels.

US Pat. No. 9,184,659

SELF-ADAPTIVE CURRENT-MODE-CONTROL CIRCUIT FOR A SWITCHING REGULATOR

INTEGRATED DEVICE TECHNOL...

1. A current-mode-control circuit for a switching regulator, comprising:
a first transistor coupled to a power supply voltage and to a first node; a second transistor coupled to the first node; an
inductor coupled between the first node and an output of the current-mode control circuit; a slope compensation generation
circuit coupled to the output of the current-mode control circuit through a feedback loop, and generating a slope compensation
current proportional to the output of the current-mode-control circuit, related the slope compensation generation circuit
comprising: a math operation circuit receiving the output of the current control circuit; a slope voltage formation circuit,
different from the math operation circuit, coupled to the math operation circuit; and a voltage-to-current conversion circuit
coupled to the slope voltage formation circuit; an inductor current sense circuit coupled to the first node, and configured
to calculate a current through the inductor and output an inductor sense current; and a pulse-width modulation (PWM) control
circuit having an output and an inverted output, an input of the inductor current sense circuit being coupled to the output
of the PWM control circuit and a gate of the first transistor and a gate of the second transistor being coupled to the inverted
output of the PWM control circuit, the PWM control circuit receiving the output of the current-mode-control circuit, the slope
compensation generation current, and the inductor sense current as inputs; and wherein the math operation circuit is configured
to solve the following equation: Se >0.5*Sf(x1, x2, . . ., xi), wherein Se is an output to the slope voltage formation circuit, Sf(x1, x2, . . ., xi) is an inductor current falling slope function for determining a falling slope Sf based on the output of the current
control circuit, the output of the current control circuit represented by x 1, x2, . . ., xi.

US Pat. No. 9,490,828

INTEGRATED CIRCUITS HAVING MULTIPLE DIGITALLY-CONTROLLED OSCILLATORS (DCOS) THEREIN THAT ARE SLAVED TO THE SAME LOOP FILTER

INTEGRATED DEVICE TECHNOL...

1. A phase-locked loop (PLL) integrated circuit, comprising:
a frequency control circuit configured to generate a control signal in response to a first periodic reference signal; and
a plurality of digitally-controlled oscillators (DCOs) configured to generate a respective plurality of periodic PLL output
signals of different frequency in response to a second periodic reference signal, said plurality of DCOs comprising respective
scaling circuits therein that are each responsive to the control signal.

US Pat. No. 9,450,648

APPARATUS, SYSTEM, AND METHOD FOR DETECTING A FOREIGN OBJECT IN AN INDUCTIVE WIRELESS POWER TRANSFER SYSTEM

INTEGRATED DEVICE TECHNOL...

1. An inductive wireless power transfer device, comprising:
a transmitter configured to transfer power to a receiver in a coupling region by generating a wireless power signal in the
coupling region in response to an input signal;

a current sensor configured to measure a direct current (DC) current of the input signal;
a voltage sensor configured to measure a DC voltage of the input signal; and
control logic coupled to the current and voltage sensors and configured to:
determine, based on the measured DC current and DC voltage of the input signal, an input power of the input signal while power
is being transferred to the receiver via the wireless power signal;

determine a transmitter power loss of the transmitter;
determine a receiver power loss of the receiver;
determine an output power of an output signal at the receiver based on information received from the receiver;
determine a coupling coefficient power loss in the coupling region between the transmitter and the receiver;
determine a foreign object power loss based on the input power, the transmitter power loss, the receiver power loss, the output
power, and the coupling coefficient power loss;

determine a presence of a foreign object within the coupling region based on the foreign object power loss;
reduce a strength of the wireless power signal when the foreign object power loss is above a first predetermined threshold
and below a second predetermined threshold; and

stop generating the wireless power signal when the foreign object power loss is above the second predetermined threshold.

US Pat. No. 9,419,588

OUTPUT DRIVER HAVING OUTPUT IMPEDANCE ADAPTABLE TO SUPPLY VOLTAGE AND METHOD OF USE

INTEGRATED DEVICE TECHNOL...

2. An output driver to provide a constant output impedance in response to a plurality of different power supply voltage level
inputs, the output driver comprising:
a plurality of individual driver circuits, each one of the plurality of individual driver circuits configured to provide a
plurality of predetermined output impedances in response to a plurality of power supply voltage level inputs, wherein each
of the plurality of individual driver circuits includes activation circuitry coupled an output of the decoder, and driver
circuitry coupled to the activation circuitry and to an output of the output driver; and

a decoder coupled to each of the plurality of individual driver circuits, the decoder for receiving a digital codeword representative
of a voltage level of a power supply coupled to the output driver, the decoder for decoding the digital codeword and for activating
one or more of the individual driver circuits based upon the decoded digital codeword, the activation of the one more individual
driver circuits to provide a constant output impedance from the output driver in response to the voltage level of the power
supply coupled to the output driver, wherein the constant output impedance is a combination of the predetermined output impedances
of the activated individual driver circuits.

US Pat. No. 9,240,792

MONOLITHIC CLOCK GENERATOR AND TIMING/FREQUENCY REFERENCE

Integrated Device Technol...

1. A periodic signal generator, comprising:
a resonant LC tank circuit configured to generate a periodic reference signal at a first frequency at a differential output
thereof; and

a temperature-responsive frequency compensation module electrically coupled to the differential output of said resonant LC
tank circuit, said temperature-responsive frequency compensation module comprising:

first and second arrays of switchable capacitive modules that are electrically coupled to first and second nodes of the differential
output of said resonant LC tank circuit, respectively, and responsive to a temperature dependent control voltage and a plurality
of switching coefficients; and

a temperature dependent voltage control module configured to generate the temperature dependent control voltage, said temperature
dependent voltage control module comprising a temperature dependent current source electrically coupled to a first node of
a current mirror and a bank of switchable resistive modules electrically coupled to a second node of the current mirror;

wherein each of the first and second arrays of switchable capacitive modules comprises a respective binary-weighted array
of fixed capacitors and a binary-weighted array of voltage-controlled variable capacitors that are responsive to the plurality
of switching coefficients;

wherein each of the fixed capacitors in the binary-weighted array of fixed capacitors is associated with a corresponding voltage-controlled
variable capacitor in the binary-weighted array of voltage-controlled variable capacitors;

wherein within each of the switchable capacitive modules, either the corresponding fixed capacitor or the corresponding voltage-controlled
variable capacitor is active, but not both at the same time; and

wherein when a voltage-controlled variable capacitor is active it has a first terminal responsive to the temperature dependent
control voltage and when a voltage-controlled variable capacitor is inactive its first terminal is responsive to a fixed voltage.

US Pat. No. 9,215,296

METHOD AND APPARATUS FOR EFFICIENT RADIO UNIT PROCESSING IN A COMMUNICATION SYSTEM

INTEGRATED DEVICE TECHNOL...

12. An apparatus for processing data in a radio unit of a communication system, the apparatus comprising:
a radio unit processing and control unit having a distributed switch, the distributed switch further configured to:
receive data at one or more interfaces of the distributed switch, the received data to be transmitted to one or more internal
resources of the radio unit, wherein each of the interfaces has an associated interface bandwidth and an associated operating
frequency and each of the internal resources has an associated resource bandwidth;

operate the one or more interfaces of the distributed switch at the operating frequency associated with the one or more interfaces
of the distributed switch if the received data is decompressed data and operating the one or more interfaces of the distributed
switch at a reduced operating frequency if the received data is compressed data;

operate the one or more interfaces to match the interface bandwidth of the one or more interfaces to the resource bandwidth
of the one or more internal resources; and

distribute the received data at the one or more interfaces to the one or more internal resources of the radio unit through
the distributed switch at the operating frequency if the received data is decompressed data and distributing the receive data
at the one or more interfaces to the one or more internal resources of the radio unit through the distributed switch at the
reduced operating frequency if the received data is compressed data, wherein the one or more internal resources includes a
memory storage module selected from the group consisting of an on-chip memory storage module and an off-chip memory storage
module, the distributed switch configured to distribute at least some of the received data to the memory storage module.

US Pat. No. 9,203,933

METHOD AND APPARATUS FOR EFFICIENT DATA COMPRESSION IN A COMMUNICATION SYSTEM

INTEGRATED DEVICE TECHNOL...

8. A compressor configured to compress data in a communication system, the compressor comprising:
a compression parameter estimation module configured to receive an uncompressed data packet comprising a plurality of signal
samples, the compression parameter estimation module including a plurality of compression parameter estimation paths operating
in parallel, and an analysis and decision module configured to identify the compression parameter estimation path of the plurality
of compression parameter estimation paths that most closely meets a desired performance level to estimate at least one compression
parameter, each of the plurality of compression parameter estimation paths including a filter, an encoder and an entropy calculation
and reduction module;

a compressed data packet generator coupled to the compression parameter estimation module, the compressed data packet generator
configured to receive the at least one estimated compression parameter and configured to compress the uncompressed data packet
using the at least one estimated compression parameter to generate a compressed data packet; and

a performance level monitor coupled to the compressed data packet generator and to the compression parameter estimation module,
the performance level monitor configured to monitor the performance level of the compressed data packet to determine if the
compressed data packet exhibits a desired performance level, configured to identify at least one compression adjustment parameter
if the compressed data packet does not exhibit the desired performance level and configured to provide the at least one compression
adjustment parameter to the compression parameter estimation module if the compressed data packet does not exhibit the desired
performance level.

US Pat. No. 9,438,252

INTEGRATED CIRCUITS HAVING LOW POWER, LOW INTERFERENCE AND PROGRAMMABLE DELAY GENERATORS THEREIN AND METHODS OF OPERATING SAME

INTEGRATED DEVICE TECHNOL...

1. A programmable delay generator, comprising:
a calibration circuit comprising a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein,
said DCO having a frequency set by a first control signal generated by said calibration circuit during a calibration operation;
and

a delay line having a second plurality of delay stages therein that are replicas of the first plurality of delay stages within
said DCO and responsive to a second control signal generated by said calibration circuit upon conclusion of the calibration
operation when said DCO is powered-down into an inactive state.

US Pat. No. 9,240,892

METHOD AND APPARATUS FOR REDUCTION OF COMMUNICATIONS MEDIA ENERGY CONSUMPTION

INTEGRATED DEVICE TECHNOL...

1. A method comprising:
receiving a source digital string of data for transmission, said source digital string of data having no interference;
detecting a sequence in said source digital string of data for transmission that has a predetermined period of periodicity
that would result in a transmission of said source digital string of data for transmission being above a predetermined energy
threshold; and

replacing said source digital string of data for transmission with a low power source digital string of data for transmission,
said low power source digital string of data having no interference wherein said low power source digital string of data for
transmission has a predetermined period of periodicity that would result in a transmission of said low power source digital
string of data for transmission being below a predetermined low energy threshold.

US Pat. No. 9,124,286

PROTECTION FOR ANALOG TO DIGITAL CONVERTERS

INTEGRATED DEVICE TECHNOL...

1. A pipeline analog-to-digital converter, comprising:
at least one stage receiving an input voltage and producing outputs of a residue voltage and a digital signal, the at least
one stage comprising:

a first circuit receiving the input voltage and producing an output of the digital signal and one or more maximum signal when
the input voltage exceeds a reference voltage;

a decoder coupled to the first circuit, the decoder configured to output a reset signal when a predetermined number of maximum
signals are received; and

a second circuit coupled to the decoder and the first circuit, the second circuit receiving the input voltage, the digital
signal, and the reset signal when output, and configured to output the residue voltage, wherein the second circuit is configured
to not output the residue voltage when the reset signal is output and received.

US Pat. No. 9,118,295

SYSTEMS AND METHODS FOR ADAPTIVE EQUALIZATION CONTROL FOR HIGH-SPEED WIRELINE COMMUNICATIONS

INTEGRATED DEVICE TECHNOL...

1. A receiver comprising:
a variable gain amplifier;
an equalizer peaking amplifier coupled serially with the variable gain amplifier;
a regulated amplifier coupled serially with the variable gain amplifier and the equalizer peaking amplifier, the regulated
amplifier providing an output that has a swing value matched to a reference voltage; and

an adaptation block coupled to the variable gain amplifier, the equalizer peaking amplifier, and the regulated amplifier,
the adaptation block including a digital finite state machine that provides a first gain signal to the variable gain amplifier
and a second gain signal to the equalizer peaking amplifier, the first gain signal being determined based in part on the reference
voltage;

wherein:
the digital finite state machine ends adaptation and locks the regulated amplifier and the equalizer peaking amplifier when
a lock condition is satisfied, the lock condition being satisfied when the first gain signal and the second gain signal each
remain within a defined range over a select number of cycles;

the digital finite state machine executes an automatic gain loop algorithm to provide the first gain signal and a boost loop
algorithm to provide the second gain signal;

the automatic gain loop algorithm is provided with an input signal having a first digital value when a peak value at an input
to the regulated amplifier is greater than the reference voltage and a second digital value when the peak value is less than
the reference voltage;

the boost loop algorithm is provided with an input signal having the first digital value when a rectified input to the regulated
amplifier is less than a rectified output of the regulated amplifier and the second digital value when the rectified input
is greater than the rectified output; and

the automatic gain loop algorithm and the boost loop algorithm each include the steps of:
starting the loop by initializing a gain value and setting a cycle number to 0; sampling the respective input signal of the
loop algorithm;

if the input signal is the first digital value, and the gain value is not saturated, incrementing the gain value;
if the input signal is the first digital value, and the gain value is saturated, retaining the gain value;
if the input signal is the second digital value, and the gain value is not saturated, decrementing the gain value;
if the input signal is the second digital value, and the gain value is saturated, decrementing the gain value;
determining whether a look loop condition is satisfied;
if the lock loop condition is satisfied, end adjustment of the equalization;
if the lock loop condition is not satisfied, determining whether a time-out condition is satisfied,
if the time-out condition is satisfied, end equalization; and
if the time-out condition is not satisfied, increment the cycle number and return to sample input signal.

US Pat. No. 9,812,903

SYSTEM AND METHOD FOR WIRELESS POWER TRANSFER USING A TWO HALF-BRIDGE TO ONE FULL-BRIDGE SWITCHOVER

Integrated Device Technol...

1. A wireless power transfer system comprising:
a controller;
first and second transmitters coupled to the controller, the first and second transmitters being coupled to one another by
an electrical connection; and

a switch coupled between the electrical connection and a voltage rail;
wherein:
when the switch is closed, the controller operates the first and second transmitters in a two half-bridge mode; and
when the switch is open, the controller operates the first and second transmitters in a one full-bridge mode.

US Pat. No. 9,653,147

ASYMMETRICAL EMPHASIS IN A MEMORY DATA BUS DRIVER

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
an interface configured to generate a memory signal that carries read data from a memory channel; and
a circuit configured to modify a read signal that transfers said read data across a read line to a memory controller, wherein
a filter delays said memory signal to generate a delayed signal, a driver amplifies said memory signal to generate said read
signal, and said driver modifies said read signal with a de-emphasis on each pull up of said memory signal and a pre-emphasis
on each pull down of said memory signal based on said delayed signal.

US Pat. No. 9,431,838

APPARATUSES AND RELATED METHODS FOR CHARGING CONTROL OF A SWITCHING VOLTAGE REGULATOR

INTEGRATED DEVICE TECHNOL...

1. A charging system, comprising:
a charging controller configured to:
generate a control signal indicating a first level of an output current generated by a switching voltage regulator for charging
an energy storage device;

determine that an output voltage exceeded a predetermined threshold; and
generate the control signal indicating a new level of the output current that is reduced from the first level;
a driver coupled with the charging controller, the driver configured to receive the control signals and generate a plurality
of switching control signals; and

valley shut off circuitry operably coupled with an output latch configured to transmit the control signals to the driver,
wherein the valley shut off circuitry is configured to shut off the control signal when the output current is discontinuous.

US Pat. No. 9,478,599

INTEGRATED CIRCUIT DEVICE SUBSTRATES HAVING PACKAGED INDUCTORS THEREON

INTEGRATED DEVICE TECHNOL...

1. An integrated circuit device, comprising:
an integrated circuit substrate having an at least two piece package thereon comprising a base and a cap sealed to the base,
said package having a sealed cavity therein and a patterned metal inductor and electrically conductive ground shield in the
cavity, said inductor comprising a metal layer patterned on an upper surface of the base and having at least a first terminal
electrically coupled to a portion of said integrated circuit substrate by an electrically conductive via, which extends at
least partially through the package;

wherein the cap has a concave-shaped recess therein that faces the inductor and the electrically conductive ground shield
covers an entirety of the concave-shaped recess in the cap and is electrically coupled to a portion of said integrated circuit
substrate by an electrically conductive ground via in the base.

US Pat. No. 9,431,955

MONOLITHIC COMPOSITE RESONATOR DEVICES WITH REDUCED SENSITIVITY TO ACCELERATION AND VIBRATION

INTEGRATED DEVICE TECHNOL...

1. An integrated circuit device, comprising:
a pair of serially-connected crystal resonators arranged as a first crystal resonator configured to support a fundamental
resonance mode in response to an input signal and a second crystal resonator configured to support a third or higher overtone
resonance mode in response to a signal generated at an output terminal of the first crystal resonator; and

a first negative impedance converter (NIC) having an input terminal electrically connected to an input terminal of the first
crystal resonator and an output terminal electrically connected to one of the output terminal of the first crystal resonator
and the output terminal of the second crystal resonator.

US Pat. No. 9,362,928

LOW-SPURIOUS FRACTIONAL N-FREQUENCY DIVIDER AND METHOD OF USE

INTEGRATED DEVICE TECHNOL...

1. A method for mitigating fractional spurious signals in an output signal of a fractional N-frequency divider, the method
comprising:
generating, by an accumulator of a fractional N-frequency divider, a substantially jitter-free calibration time window defined
by a carryout signal of the accumulator, a multi-modulus frequency divider output signal of the fractional N-frequency divider
and a fraction word input to the accumulator;

determining a period of a first oscillator circuit by counting the number of cycles of the first oscillator circuit during
the calibration time window;

calibrating a second oscillator circuit relative to the first oscillator by adjusting a period of the second oscillator circuit
until a difference between the period of the first oscillator circuit and a period of the second oscillator circuit is equal
to a desired differential period between the first oscillator circuit and the second oscillator circuit;

calculating, for each of a plurality of accumulator control words from the accumulator, a calibration control word using the
first oscillator circuit, the calibrated second oscillator circuit and a phase compensation circuit of the fractional N-frequency
divider; and

calibrating the phase compensation circuit of the fractional N-frequency divider using the calibration control word to modify
each of the plurality of accumulator control words to generate a modified control word that is used to reduce the fractional
spurious signals in the output signal of the fractional N-frequency divider.

US Pat. No. 9,859,901

BUFFER WITH PROGRAMMABLE INPUT/OUTPUT PHASE RELATIONSHIP

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
a phase locked loop circuit including a phase comparator for generating a signal indicative of a phase difference between
a signal presented to a first input of the phase comparator and a signal presented to a second input of the phase comparator;

a first delay element for contributing delay to the signal provided to the first input of the phase comparator;
a second delay element for contributing delay to the signal provided to the second input of the phase comparator, wherein
a delay contributed by at least one of the first delay element and the second delay element varies in accordance with an associated
delay control value; and

a microcontroller coupled to the first delay element and to the second delay element, wherein the microcontroller generates
the associated delay control value, wherein the phase locked loop circuit, the first delay element, the second delay element
and the microcontroller reside on a same semiconductor substrate.

US Pat. No. 9,500,707

METHOD AND APPARATUS FOR USING TESTER CHANNEL AS DEVICE POWER SUPPLY

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
a voltage and current driver, said voltage and current driver having a first tester channel input, said voltage and current
driver having a power supply input, and said voltage and current driver having an output;

a current to voltage converter, said current to voltage converter having an input, and said current to voltage converter having
an output;

a bypass unit for bypassing said current to voltage converter such that said current to voltage converter when bypassed receives
no current, said bypass unit having an input, and said bypass unit having an output;

a power supply port, said power supply port for supplying power to a device under test;
said voltage and current driver output operatively coupled to said current to voltage converter input and to said bypass input;
and

said power supply port coupled to said current to voltage converter output and to said bypass output.

US Pat. No. 9,485,053

LONG-DISTANCE RAPIDIO PACKET DELIVERY

INTEGRATED DEVICE TECHNOL...

1. A RapidIO device comprising:
a switch fabric; and
a port coupled to the switch fabric, the port configured to establish a serial link with RapidIO endpoints, configured to
assign the same acknowledgement identifier to three or more contiguous packets and generate a link cyclical redundancy check
(CRC) value for each of the three or more contiguous packets that is computed to include the value of an acknowledgement identifier
header prepended to each of the three or more contiguous packets, and the port configured to append each link CRC value to
a corresponding one of the three or more contiguous packets and sequentially output the three or more contiguous packets having
the same acknowledgement identifier on the serial link.

US Pat. No. 9,442,167

METHOD AND APPARATUS FOR USING TESTER CHANNEL AS DEVICE POWER SUPPLY

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
a voltage and current driver, said voltage and current driver having a first tester channel input, said voltage and current
driver having a power supply input, and said voltage and current driver having an output;

a current to voltage converter, said current to voltage converter having an input, and said current to voltage converter having
an output;

a bypass unit for bypassing said current to voltage converter, said bypass unit having an input, and said bypass unit having
an output;

a power supply port, said power supply port for supplying power to a device under test;
said voltage and current driver output operatively coupled to said current to voltage converter input and to said bypass input;
and

said power supply port coupled to said current to voltage converter output and to said bypass output, and wherein said voltage
and current driver has a unity voltage gain from said first tester channel input to said voltage and current driver output
when said bypass unit bypasses said current to voltage converter.

US Pat. No. 9,332,629

FLIP CHIP BUMP ARRAY WITH SUPERIOR SIGNAL PERFORMANCE

INTEGRATED DEVICE TECHNOL...

1. A circuit assembly comprising:
a printed circuit board;
a package substrate electrically connected to the printed circuit board, the package substrate including a package body; and
a pin array that electrically connects the package body to the integrated circuit, the pin array including (i) a first pin
set that is rectangular tube shaped and includes a plurality of signal pins and a plurality of non-signal pins that are alternatingly
interspersed around the rectangular tube shaped first pin set; and (ii) a second pin set that is rectangular tube shaped and
that encircles the first pin set, wherein the second pin set includes a plurality of signal pins and a plurality of non-signal
pins that are alternatingly interspersed around the rectangular tube shaped second pin set; wherein each non-signal pin is
either a ground pin or a power pin; and wherein each pin set includes four corner pins, and wherein each corner pin of each
pin set is a signal pin; and

an integrated circuit including a circuit body; and a bump array that is electrically connected to the pin array of the package
substrate, the bump array including (i) a first bump set that is rectangular tube shaped and includes a plurality of signal
bumps and a plurality of non-signal bumps that are alternatingly interspersed around the rectangular tube shaped first bump
set; and (ii) a second bump set that is rectangular tube shaped and that encircles the first bump set, wherein the second
bump set includes a plurality of signal bumps and a plurality of non-signal bumps that are alternatingly interspersed around
the rectangular tube shaped second bump set; wherein each non-signal bump is either a ground bump or a power bump; and wherein
each bump set includes four corner bumps, and wherein each corner bump of each bump set is a signal bump.

US Pat. No. 10,014,721

APPARATUS, SYSTEM, AND METHOD FOR BACK-CHANNEL COMMUNICATION IN AN INDUCTIVE WIRELESS POWER TRANSFER SYSTEM

Integrated Device Technol...

1. An inductive wireless power transfer device, comprising: a transmitter, comprising:a transmit coil configured to generate a wireless power signal to a coupling region in response to an input voltage, the transmitter including an inverter configured to generate a time varying current through the transmit coil responsive to a DC signal as the input voltage, the inverter including a switch network; and
a modulator configured to modulate the wireless power signal and encode data with the wireless power signal to establish a back-channel communication link from the transmitter to a receiver,
wherein the modulator is configured to adjust a control characteristic of the inverter to modulate the wireless power signal and encode data with the wireless power signal, the control characteristic being a combination of a switching frequency of the switch network and a duty cycle of switches of the switch network.

US Pat. No. 9,455,045

CONTROLLING OPERATION OF A TIMING DEVICE USING AN OTP NVM TO STORE TIMING DEVICE CONFIGURATIONS IN A RAM

INTEGRATED DEVICE TECHNOL...

1. A method for controlling operation of a timing device comprising:
receiving input at the timing device, the input including a start address and an end address;
when the input includes a burn address, reading configuration data from a Random Access Memory (RAM) beginning at an address
in the RAM corresponding to the burn address and burning the configuration data read from RAM into a one time programmable
non volatile memory (OTP NVM) at a location in the OTP NVM corresponding to the start address and the end address; and

when the input includes a read start address, reading the configuration data from the OTP NVM beginning at a location in the
OTP NVM corresponding to the start address and ending at a location in the OTP NVM corresponding to the end address and storing
the configuration data read from the OTP NVM into the RAM beginning at an address in the RAM corresponding to the read start
address.

US Pat. No. 9,362,924

METHOD AND APPARATUS FOR FAST FREQUENCY ACQUISITION IN PLL SYSTEM

INTEGRATED DEVICE TECHNOL...

1. A method for fast acquisition and lock of a phase locked loop comprising:
using a time to digital converter to measure a phase difference between a feedback clock signal and a reference clock signal
in said phase locked loop; and

using a cycle slip detection logic to determine a relationship between said feedback clock signal and said reference clock
signal in said PLL.

US Pat. No. 9,264,027

PROCESS COMPENSATED DELAY

INTEGRATED DEVICE TECHNOL...

1. A method comprising using a varactor and generating a delay based primarily on electron mobility, wherein said using a
varactor is using a varactor fabricated on an integrated circuit, wherein said generating a delay further comprises utilizing
a current source said current source directly coupled to said varactor fabricated on said integrated circuit, wherein said
current source is fabricated on said integrated circuit, and further comprising shunting directly across said varactor on
said integrated circuit using a transistor.

US Pat. No. 9,506,817

TEMPERATURE DETECTION METHOD AND DEVICE WITH IMPROVED ACCURACY AND CONVERSION TIME

INTEGRATED DEVICE TECHNOL...

1. A method comprising:
sampling a temperature sensor to generate first, second, third and fourth samples respectively based on a first, second, third
and fourth stimulus, where a difference between a first stimulus difference and a second stimulus difference is non-zero,
the first stimulus difference comprising a difference between the second and first stimulus and the second stimulus difference
comprising a difference between the fourth and third stimulus; and

generating a signal proportional to temperature from the first, second, third and fourth samples, where the signal is defined
as a difference between a first sample difference and a second sample difference, the first sample difference comprising a
difference between the second sample and the first sample, the second sample difference comprising a difference between the
fourth sample and the third sample, and where the signal is defined to cancel parasitic components in the first, second, third
and fourth samples.

US Pat. No. 9,490,805

LOW POWER DRIVER WITH PROGRAMMABLE OUTPUT IMPEDANCE

INTEGRATED DEVICE TECHNOL...

1. A programmable low power driver, comprising:
a first driver output;
a first programmable driver leg having a pull-up half and a pull-down half, the pull-up half is electrically coupled between
a supply voltage and the first driver output, the pull-up half is electrically coupled to receive a signal and a first control
signal, the pull-down half is electrically coupled between an internal ground and the first driver output, the pull-down half
is electrically coupled to receive an inversion of the signal and the first control signal;

a second programmable driver leg having a pull-up half and a pull-down half, the pull-up half is electrically coupled between
the supply voltage and the first driver output, the pull-up half is electrically coupled to receive the signal and a second
control signal, the pull-down half is electrically coupled between the internal ground and the first driver output, the pull-down
half is electrically coupled to receive the inversion of the signal and the second control signal;

the first programmable driver leg contributes to an output impedance of the first driver output when the first control signal
is high and does not contribute to the output impedance of the first driver output when the first control signal is low; and

the second programmable driver leg contributes to the output impedance of the first driver output when the second control
signal is high and does not contribute to the output impedance of the first driver output when the second control signal is
low.

US Pat. No. 9,654,121

CALIBRATION METHOD AND APPARATUS FOR PHASE LOCKED LOOP CIRCUIT

INTEGRATED DEVICE TECHNOL...

1. An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured
to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator
configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable
frequency oscillator, and a divider that is configured to divide the fast clock signal by a divisor (N) so as to generate
the feedback clock signal, the integrated circuit device comprising:
a calibration circuit coupled to receive the reference clock signal and the fast clock signal and to provide a frequency band
selection signal to the variable frequency oscillator, the calibration circuit including:

a counting circuit operable for counting a number of cycles of the fast clock signal over a period of time defined by a number
of cycles (M) of the reference clock signal; and

a selection block operable for performing a convergence test using the counted number of fast clock cycles, N, and M, wherein
the selection block generates the frequency band selection signal in accordance with the results of the convergence test to
select a next candidate calibrated frequency band.

US Pat. No. 9,515,510

APPARATUSES AND METHODS FOR OVER-TEMPERATURE PROTECTION OF ENERGY STORAGE DEVICES

INTEGRATED DEVICE TECHNOL...

1. A charging system, comprising:
a temperature sensor thermally coupled with an energy storage device and configured for generating a temperature signal responsive
to a temperature of the energy storage device;

a circuit temperature sensor on a semiconductor device configured for generating a circuit temperature signal responsive to
a temperature of the semiconductor device;

a charge adjuster operably coupled to the temperature sensor and the circuit temperature sensor, the charge adjuster configured
to:

determine when the temperature signal or the circuit temperature signal indicates an over-temperature condition;
decrement a down counter based on the determination; and
generate a desired current signal based on a value of the down counter;
a comparator configured for comparing a current level signal to the desired current signal to generate a charge adjustment
signal, the current level signal indicating a level of charge current being supplied to the energy storage device; and

a charge controller on the semiconductor device and configured for generating and adjusting a current of a charging signal
for charging the energy storage device responsive to the charge adjustment signal.

US Pat. No. 9,281,831

DIGITAL EXTRACTION AND CORRECTION OF THE LINEARITY OF A RESIDUE AMPLIFIER IN A PIPELINE ADC

INTEGRATED DEVICE TECHNOL...

1. A pipeline analog-to-digital converter, comprising:
a stage, the stage including a residue amplifier that amplifies a residual voltage generated by the stage to obtain an amplified
residual voltage;

a backend digitizer that digitizes the amplified residual voltage to generate a digitized residual; and
a digital correction circuit that determines an operating zone from a plurality of zones of a transfer function that is associated
with the digitized residual by comparing the digitized residual with operating parameters of the operating zone and corrects
the digitized residual according to which operating zone the digitized residual is found.

US Pat. No. 9,583,175

RECEIVER EQUALIZATION CIRCUIT WITH CROSS COUPLED TRANSISTORS AND/OR RC IMPEDANCE

INTEGRATED DEViCE TECHNOL...

1. An apparatus comprising:
a first circuit configured to (a) buffer write signals presented on a data bus connected between a memory channel and a memory
controller, (b) buffer read signals presented on said data bus and (c) condition said write signals, wherein said conditioning
is implemented by (i) converting said write signals to a first differential write signal on a first differential write line
and a second differential write signal on a second differential write line and (ii) connecting (a) a negative impedance and
(b) a series combined resistive and capacitive load between said first and said second differential write lines; and

a second circuit configured to (a) convert said first and said second differential write signals to a single-ended write signal
and (b) present said single-ended write signal to said memory channel.

US Pat. No. 9,503,059

INTEGRATED CIRCUIT DEVICES HAVING OSCILLATOR CIRCUITS THEREIN THAT SUPPORT FIXED FREQUENCY GENERATION OVER PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS

INTEGRATED DEVICE TECHNOL...

1. An oscillator circuit, comprising:
a reference voltage generator configured to generate a reference voltage across a resistor therein;
a comparator configured to generate a differential clock signal at an output thereof;
first and second switched capacitor circuits comprising matching first and second trim capacitors therein, respectively, said
first and second switched capacitor circuits configured to periodically drive respective first and second input terminals
of said comparator at a first voltage level in an alternating back-and-forth sequence, in response to the reference voltage
and a pair of switching signals derived from the differential clock signal; and

a voltage buffer configured to drive a shared reference node that is common to the first and second switched capacitor circuits
in response to the reference voltage.

US Pat. No. 9,479,177

SELF-CALIBRATING FRACTIONAL DIVIDER CIRCUITS

INTEGRATED DEVICE TECHNOL...

1. A fractional divider (FD) circuit, comprising:
a multi-modulus divider (MMD) configured to generate a periodic output signal in response to a periodic reference signal and
a modulus control signal having a value that sets a frequency division ratio to be applied to the periodic reference signal;

a phase correction circuit configured to generate an FD output signal in response to the MMD output signal and a corrected
multi-bit phase correction control signal during an active mode of operation and further configured to generate an FD output
signal in response to the MMD output signal and a preliminary multi-bit phase correction control signal during a calibration
mode of operation; and

a control circuit configured to generate the modulus control signal, the preliminary multi-bit phase correction control signal
and the corrected multi-bit phase correction control signal during the active mode of operation, said control circuit further
configured to perform a self-calibration of said phase correction circuit during the calibration mode of operation by generating
a mapping relationship between each of a plurality of preliminary multi-bit phase correction control values, which assume
a high degree of phase correction linearity within said phase correction circuit, and a corresponding plurality of corrected
multi-bit phase correction control values, which account for phase correction nonlinearity within said phase correction circuit
as manufactured and operated during the active mode of operation.

US Pat. No. 9,837,714

EXTENDING BEAMFORMING CAPABILITY OF A COUPLED VOLTAGE CONTROLLED OSCILLATOR (VCO) ARRAY DURING LOCAL OSCILLATOR (LO) SIGNAL GENERATION THROUGH A CIRCULAR CONFIGURATION THEREOF

Integrated Device Technol...

13. A wireless communication system comprising:
a beamforming system comprising:
a VCO array comprising a plurality of individual VCOs configured to generate LO signals separated in phase based on varying
voltage levels of voltage control inputs thereto, the individual VCOs of the VCO array being coupled to one another in a closed,
circular configuration to increase phase difference between the phase separated LO signals generated by the individual VCOs
compared to a linear configuration of the VCO array, and each individual VCO of the coupled VCO array being electrically coupled
to one individual VCO at an input thereof and to another individual VCO from an output thereof;

an antenna array comprising a plurality of antenna elements;
a plurality of mixers, each of which is configured to mix an output of the each individual VCO of the coupled VCO array with
a signal from an antenna element of the antenna array to introduce differential phase shifts in signal paths coupled to the
antenna elements during performing beamforming with the antenna array,

wherein two or more VCOs of the coupled VCO array are injection locked to each other; and
an independent reference frequency source to control operating frequency of the coupled VCO array; and
a receiver channel configured to receive a combined output of the plurality of mixers of the beamforming system.

US Pat. No. 10,135,431

FAST-RESPONSE REFERENCE-LESS FREQUENCY DETECTOR

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a first circuit configured to generate an intermediate signal in response to an input clock signal operating at a frequency, wherein (i) said first circuit modifies said input clock signal according to a threshold frequency to generate a waveform for said intermediate signal and (ii) said waveform of said intermediate signal has at least one of (a) pulses and (b) a steady state; and
a second circuit configured to generate a control signal in response to said intermediate signal, wherein (i) said second circuit modifies said intermediate signal to generate said control signal, (ii) said control signal has (a) a first state when said intermediate signal has said pulses and (b) a second state when said intermediate signal has said steady state and (iii) a width of said pulses is based on said threshold frequency.

US Pat. No. 9,853,632

SIGNAL DRIVER SLEW RATE CONTROL

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
a first circuit configured to (i) generate a plurality of delayed signals each as a copy of an input signal shifted in time
by a sequence of respective delays based on a control signal and (ii) change a number of driver signals that are active during
each delay in said sequence of respective delays based on said input signal and said plurality of delayed signals to control
a slew rate of an output signal; and

a second circuit configured to drive said output signal in response to said driver signals, wherein (i) an initial delay in
said sequence of respective delays has a fixed duration that maintains said slew rate of said output signal at a constant
rate until said output signal crosses a threshold voltage and (ii) at least one subsequent delay after said initial delay
in said sequence of respective delays has a programmable duration that adjusts said slew rate of said output signal after
said output signal has crossed said threshold voltage.

US Pat. No. 9,793,708

OVERVOLTAGE PROTECTION CIRCUITS AND METHODS OF OPERATING SAME

Integrated Device Technol...

15. A packaged integrated circuit device, comprising:
an integrated circuit substrate electrically coupled to a plurality of electrical conductors extending, which extend through
an integrated circuit package containing the integrated circuit substrate; and

an overvoltage protection circuit on the integrated circuit substrate, said overvoltage protection circuit comprising:
an overvoltage detection circuit having a first and second terminals electrically coupled to first and second power supply
conductors extending though the integrated circuit package, respectively, said overvoltage detection circuit configured to
generate a clamp activation signal in response to detecting an excessive overvoltage between the first and second power supply
conductors; and

a voltage clamping circuit electrically coupled to an output of said overvoltage detection circuit and the first power supply
conductor, said voltage clamping circuit configured to sink current from the first power supply conductor in-sync with a transition
of the clamp activation signal from a first logic state to a second logic state.

US Pat. No. 9,899,908

HIGH FREQUENCY WIRELESS POWER RECTIFIER STARTUP CIRCUIT DESIGN

Integrated Device Technol...

1. A rectifier, comprising:
a first transistor and a second transistor coupled in series between a rectifier output and a ground, wherein a first AC input
is coupled to a first node between the first transistor and the second transistor;

a third transistor and a fourth transistor coupled in series between the rectifier output and the ground, wherein a second
AC input is coupled to a second node between the third transistor and the fourth transistor;

a first control circuit coupled between a gate of the first transistor and a gate of the fourth transistor to control operation
of the first and the fourth transistors; and

a first startup circuit coupled between the gate of the first transistor and the first node, the first startup circuit controlling
the gate of the first transistor in a startup time period prior to an operating period of the rectifier,

wherein the first startup circuit comprises:
a first control transistor coupled between the gate of the first transistor and the first node;
a resistive element coupled to a gate of the first control transistor; and
a second control transistor coupled between the gate of the first control transistor and the first node, a gate of the second
control transistor coupled to the first control circuit, and

wherein the first control transistor is turned on by the resistive element during the startup time period and turned off by
the second control transistor during the operating period.

US Pat. No. 9,865,315

COMPENSATION OF DETERMINISTIC CROSSTALK IN MEMORY SYSTEM

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
a detector circuit configured to (i) identify a start of a command sequence associated with a write access to a memory system
and (ii) generate a control signal indicating a start of a plurality of strobe edges in a strobe signal associated with said
start of said command sequence; and

a receiver circuit configured to initialize an equalizer circuit in response to said control signal, wherein said equalizer
circuit is configured to compensate for crosstalk coupled from said strobe edges in said strobe signal on a data strobe line
to a data signal on a data line to provide an increased margin.

US Pat. No. 9,590,637

HIGH-SPEED PROGRAMMABLE FREQUENCY DIVIDER WITH 50% OUTPUT DUTY CYCLE

INTEGRATED DEVICE TECHNOL...

1. An integrated circuit device comprising:
a multiplexer having a first input terminal coupled to receive a first integer value (M) and a second input terminal for receiving
a second integer value that is M plus a least significant bit (LSB), the multiplexer configured to alternately output M and
the second integer value;

a multi-modulus divider coupled to the multiplexer for receiving the output of the multiplexer and having a clock input for
receiving a clock signal, the multi-modulus divider operable to alternately generate an output pulse at M input clock cycles
and at M+LSB clock cycles;

a divide-by-two counter having an input coupled to the output of the multi-modulus divider, the divide-by-two counter operable
to divide the output of the multi-modulus divider to generate a divided clock signal having a frequency equal to 2M+LSB; and

duty cycle correction logic coupled to the output of the divide by two counter, the duty cycle correction logic configured
to correct the duty cycle of the divided clock signal to a fifty percent duty cycle when the LSB is odd.

US Pat. No. 9,935,470

SYSTEM AND METHOD FOR WIRELESS POWER TRANSFER USING A POWER CONVERTER WITH A BYPASS MODE

Integrated Device Technol...

1. A power converter comprising:a pulsed switch;
a capacitor configured to supply a drive voltage to the pulsed switch;
a bootstrap circuit configured to charge the capacitor when the power converter operates in a switched mode of operation, wherein the pulsed switch is operated at less than 100% duty cycle; and
a charge pump circuit configured to charge the capacitor when the power converter operates in a bypass mode of operation, wherein the pulsed switch is operated at 100% duty cycle.

US Pat. No. 9,673,638

APPARATUS AND METHOD FOR A SWITCHING POWER CONVERTER

INTEGRATED DEVICE TECHNOL...

1. A power converter, comprising:
a first terminal configured to receive an input voltage;
a charging converter coupled in a current path from the first terminal to a second terminal and including a first switch and
configured to:

provide power from a power source to a rechargeable storage unit that is internal to the power converter during a charging
mode; and

provide power from the rechargeable storage unit to an external electronic device that is externally connected to the power
converter during an on-the-go mode;

a system power converter coupled in a current path from the second terminal to a third terminal, the system power converter
including a second switch and configured to:

provide power to internal system components of the power converter from the rechargeable storage unit and an input power source;
and

control logic coupled to the charging converter and the system power converter and configured to control the charging converter
and the system power converter by:

determining whether a short exists;
distinguishing whether the short exists at the first terminal or the third terminal using a current sensor;
in response to detecting a short at the first terminal, causing the charging converter to open the first switch; and
in response to detecting a short at the third terminal, causing the system power converter to open the second switch.

US Pat. No. 9,865,328

NULLIFYING INCORRECT SAMPLED DATA CONTRIBUTION IN DECISION FEEDBACK EQUALIZER AT RESTART OF FORWARDED CLOCK IN MEMORY SYSTEM

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
a detector circuit configured to (i) identify a start of a command sequence associated with a directed access to a memory
system and (ii) generate a control signal indicating detection of a non-consecutive clock associated with said start of said
command sequence; and

a data buffer circuit configured to initialize a condition of a receiver circuit in response to said control signal prior
to reception of a first data bit associated with said command sequence to provide an increased margin, wherein said data buffer
circuit generates one or more tap enable signals configured to determine a number of clock cycles during which a contribution
of one or more taps of a decision feedback equalizer (DFE) of said receiver circuit are delayed.

US Pat. No. 9,837,864

APPARATUSES AND WIRELESS POWER TRANSMITTERS HAVING MULTIPLE TRANSMIT COILS AND RELATED METHOD

Integrated Device Technol...

1. A wireless power enabled apparatus, comprising:
a wireless power transmitter, including:
a plurality of transmit coils configured to generate a wireless power signal for wireless power transfer to a wireless power
receiver;

a bridge inverter configured to generate an AC signal to pass through the plurality of transmit coils; and
a switching circuit operably coupled with the plurality of transmit coils and configured to enable and disable each of the
plurality of transmit coils responsive to control signals from a transmitter controller, wherein the switching circuit includes:

a first plurality of switches serially coupled on opposing sides of a first transmit coil of the plurality of transmit coils;
a first plurality of clamp elements, each clamp element coupled across a respective switch of the first plurality of switches
and configured to extract energy away from the first transmit coil;

a second plurality of switches serially coupled on opposing sides of a second transmit coil of the plurality of transmit coils;
and

a second plurality of clamp elements, each clamp element coupled across a respective switch of the second plurality of switches
and configured to extract energy away from the second transmit coil.

US Pat. No. 9,667,168

SYSTEM AND METHOD FOR SYNCHRONOUS RECTIFICATION WITH ENHANCED DETECTION OF SMALL CURRENTS

INTEGRATED DEVICE TECHNOL...

1. An synchronous rectifier circuit comprising:
a direct current (DC) load coupled between a DC output node and a ground node;
an alternating current (AC) source applying an AC waveform to an AC input node;
an upper switch coupled between the DC output node and the AC input node; and
a lower switch coupled between the AC input node and the ground node;
wherein the synchronous rectifier circuit is configured to operate in multiple states based on a load current of the DC load,
the multiple states including:

a first state, wherein in the first state, the upper switch is turned on and the lower switch is turned off;
a second state, wherein in the second state, the upper switch is turned off and the lower switch is turned on; and
a third state, wherein in the third state, the upper switch is turned off and the lower switch is operated in an enhanced
detection mode, wherein a voltage of the AC input node is more sensitive to changes in the load current in the third state
than in the second state;

wherein the synchronous rectifier circuit transitions from the first state to the second state when the voltage of the AC
input node decreases below a first threshold voltage, from the second state to the third state when the voltage of the AC
input node increases above a second threshold voltage, and from the third state to the first state when the voltage of the
AC input node increases above a third threshold voltage.

US Pat. No. 9,581,973

DUAL MODE CLOCK USING A COMMON RESONATOR AND ASSOCIATED METHOD OF USE

INTEGRATED DEVICE TECHNOL...

15. A method of generating a dual mode clock output signal, the method comprising:
coupling a resonator to a first oscillator circuit of a first clock circuit, the first clock circuit for generating a first
clock signal having a first frequency in response to the resonator;

coupling the resonator to a second oscillator circuit of a second clock circuit, the second clock circuit for generating a
second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock
signal is determined by a programmable frequency divider of the second clock circuit;

coupling a clock mode control circuit to the first clock circuit and the second clock circuit; and
operating the clock mode control circuit to gradually switch the resonator between the first oscillator circuit and the second
oscillator circuit to generate a dual mode clock output signal.

US Pat. No. 9,905,287

ASYMMETRICAL EMPHASIS IN A MEMORY DATA BUS DRIVER

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
an interface configured to generate a read signal that carries read data from a memory channel; and
a circuit configured to (i) modify said read signal with a de-emphasis on each pull up of said read signal and a pre-emphasis
on each pull down of said read signal and (ii) transfer said read signal as modified to a memory controller.

US Pat. No. 9,628,255

METHODS AND APPARATUS FOR TRANSMITTING DATA OVER A CLOCK SIGNAL

INTEGRATED DEVICE TECHNOL...

1. A method of operating a clock circuit in a first system, comprising:
transmitting a clock signal of the clock circuit, from a transmitter of the first system to a receiver of a second system,
wherein a first repeating edge of respective ones of clock cycles within the clock signal repeats at a predetermined constant
frequency within the clock signal to synchronize operations of the second system; and

varying, by the first system, a second edge of at least one of the clock cycles within the clock signal to transmit a data
transmission within the clock signal.

US Pat. No. 10,075,207

GAAS/SIGE-BICMOS-BASED TRANSCEIVER SYSTEM-IN-PACKAGE FOR E-BAND FREQUENCY APPLICATIONS

INTEGRATED DEVICE TECHNOL...

1. An e-band transceiver comprising a transmitter circuit and a receiver circuit, wherein the transmitter circuit comprises:a surface mounted technology (SMT) module including:
a silicon-germanium (SiGe) bipolar plus CMOS (BiCMOS) converter, a gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) output amplifier coupled to the SiGe BiCMOS converter, and a microstrip/waveguide interface coupled to the GaAs pHEMT output amplifier; and
a non-volatile memory configured to store calibration data, wherein said calibration data (i) allows a chip by chip calibration and (ii) avoids a calibration rejection procedure.

US Pat. No. 9,948,112

APPARATUSES AND RELATED METHODS FOR DETECTING COIL ALIGNMENT WITH A WIRELESS POWER RECEIVER

Integrated Device Technol...

1. A wireless power enabled apparatus, comprising:a wireless power receiver, including:
a receive coil configured to generate an AC power signal responsive to wireless power received from a wireless power transmitter; and
a control logic configured to:
determine an efficiency of wireless power transfer between a transmit coil and the receive coil; and
determine an amount of positional misalignment of the receive coil with respect to the transmit coil, when the receive coil is in a near field zone of the transmit coil, based at least on the determined efficiency.

US Pat. No. 10,312,961

TRANSCEIVER RESONANT RECEIVE SWITCH

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:an input port;
an output port; and
a resonant receive switch circuit coupled between the input port and the output port, said resonant receive switch circuit comprising a switch and an input matching circuit, wherein (i) said switch is ac coupled between said input port and said output port, (ii) when said switch is in a non-conducting state, a signal at the input port is passed to the output port, and (iii) when said switch is in a conducting state, the signal at the input port is reflected.

US Pat. No. 9,553,602

METHODS AND SYSTEMS FOR ANALOG-TO-DIGITAL CONVERSION (ADC) USING AN ULTRA SMALL CAPACITOR ARRAY WITH FULL RANGE AND SUB-RANGE MODES

Integrated Device Technol...

1. An apparatus comprising:
a comparator, the comparator is configured with a first high input, a first low input, and is configure to receive a clock
signal;

a logic/latch block, the logic/latch block is configured to receive the clock signal and an output from the comparator, the
logic/latch block is configured to output a control signal and a digital N-bit output signal; and

a first local charge-averaging capacitor array (LCACA), the first LCACA is configured to receive the control signal and a
reference voltage, an output of the first LCACA is coupled to the first low input, the first LCACA is divided into a high
sub-array and a low sub-array, the high sub-array to be pre-charged to a high reference voltage and the low sub-array to be
pre-charged to a low reference voltage, the high reference voltage is greater than the low reference voltage, wherein in operation
an analog signal is input to the first high input and the digital N-bit output signal is the digital conversion of the analog
signal.

US Pat. No. 10,311,940

NULLIFYING INCORRECT SAMPLED DATA CONTRIBUTION IN DECISION FEEDBACK EQUALIZER AT RESTART OF FORWARDED CLOCK IN MEMORY SYSTEM

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a receiver circuit comprising a decision feedback equalizer (DFE); and
a data buffer circuit configured to initialize a condition of said receiver circuit in response to a control signal prior to reception of a command sequence associated with a directed access to a memory system, wherein (i) said control signal indicates detection of a non-consecutive clock associated with a start of said command sequence and (ii) said data buffer circuit generates one or more tap enable signals configured to determine a number of clock cycles during which a contribution of one or more taps of said decision feedback equalizer (DFE) are delayed.

US Pat. No. 10,103,690

PHASE, AMPLITUDE AND GATE-BIAS OPTIMIZER FOR DOHERTY AMPLIFIER

INTEGRATED DEVICE TECHNOL...

1. A device comprising:a signal path splitter providing a split signal path comprising a signal path A split into N-paths comprising a signal path B and a signal path C with a symmetry relationship, a phase relationship and a polarity relationship between the signal paths B and C that are selectively reconfigurable by a reconfigurable symmetry, a reconfigurable phase and a reconfigurable path; and
a reconfigurable symmetry providing selective reconfiguration of the symmetry relationship between the signal paths B and C by providing selective amplification or attenuation;
a reconfigurable phase providing selective reconfiguration of the phase relationship between the signal paths B and C; and
a reconfigurable path providing selective reconfiguration of the polarity relationship between the signal paths B and C.

US Pat. No. 9,954,541

BULK ACOUSTIC WAVE RESONATOR BASED FRACTIONAL FREQUENCY SYNTHESIZER AND METHOD OF USE

INTEGRATED DEVICE TECHNOL...

1. A frequency synthesizer comprising:a first phase locked loop (PLL) circuit, the first PLL circuit comprising a first voltage controlled oscillator (VCO) having a bulk acoustic wave (BAW) resonator and a first fractional feedback divider circuit, the first PLL circuit coupled to receive a reference frequency signal from a reference oscillator and to output a first tuned frequency signal; and
a first plurality of integer divider circuits coupled to receive the first tuned frequency signal of the first PLL circuit, each of the first plurality of integer divider circuits to provide one of a plurality of output frequency signals of the frequency synthesizer wherein a ratio of the frequency tuning range of the BAW resonator to a center frequency of the BAW resonator is a minimum ratio for the plurality of output frequency signals.

US Pat. No. 9,860,535

METHOD FOR TIME-DEPENDENT VISUAL QUALITY ENCODING FOR BROADCAST SERVICES

INTEGRATED DEVICE TECHNOL...

1. A method, comprising:
enabling a pre-filtering of images before encoding the images based on a first profile;
encoding the images based on the first profile during a first time period;
changing to a second profile associated with a second time period;
disabling the pre-filtering of the images before encoding the images based on the second profile; and
encoding the images based on the second profile during the second time period, wherein (i) each profile determines one or
more resources configured to be applied to the images before generating an encoded bitstream and (ii) the first profile provides
higher visual quality of the encoded images than the second profile.

US Pat. No. 9,852,039

PHASE LOCKED LOOP (PLL) TIMING DEVICE EVALUATION SYSTEM AND METHOD FOR EVALUATING PLL TIMING DEVICES

INTEGRATED DEVICE TECHNOL...

1. A method for evaluating Phase Locked Loop (PLL) timing devices comprising:
providing an evaluation board including a PLL-timed physical device, an input and output circuit, connector receptacles and
control logic;

providing PLL cards configured to be inserted into at least two of the connector receptacles, each of the PLL cards including
a PLL timing device;

providing one or more backplane emulator card configured to be inserted into one of the connector receptacles, the backplane
emulator card having electrical characteristics emulating a portion of a communication system extending between phase locked
loop timing devices of the communication system; and

wherein different PLL cards and different backplane emulator cards can be coupled to the connector receptacles to emulate
different configurations of the communication system.

US Pat. No. 9,553,485

APPARATUS, SYSTEM, AND METHOD FOR DETECTING A FOREIGN OBJECT IN AN INDUCTIVE WIRELESS POWER TRANSFER SYSTEM BASED ON INPUT POWER

INTEGRATED DEVICE TECHNOL...

1. An inductive wireless power transfer device, comprising:
a transmitter configured to generate an electromagnetic field to a coupling region for providing energy transfer to a wireless
power receiving apparatus, wherein the transmitter includes control logic configured to:

determine a first input power of the transmitter from a ping generated during a sleep mode;
determine a presence of a foreign object within the coupling region in response to a comparison of the first input power to
a first desired threshold;

reduce a frequency of the ping in response to determining the presence of the foreign object; and
transmit the ping at the reduced frequency.

US Pat. No. 10,108,567

MEMORY CHANNEL SELECTION CONTROL

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a first circuit comprising (i) a controller port and (ii) a plurality of memory ports;
a second circuit comprising (i) an input port and (ii) a plurality of output ports; and
a channel decoder configured to (A) decode a selection signal and (B) select (i) one of said plurality of memory ports and (ii) one of said plurality of output ports in response to said decoded selection signal, wherein (i) said selection signal is received by (a) said controller port and said channel decoder in a first mode and (b) said input port and said channel decoder in a second mode, (ii) said first circuit implements a first multiplexer path operating at a first speed, (iii) said second circuit implements a second multiplexer path operating at a second speed and (iv) said first speed is greater than said second speed.

US Pat. No. 10,063,397

METHOD AND APPARATUS FOR NOVEL ADAPTIVE EQUALIZATION TECHNIQUE FOR SERIALIZER/DESERIALIZER LINKS

INTEGRATED DEVICE TECHNOL...

1. A method for adaptive equalization of a serializer/deserializer (SERDES) link comprising in order:(a) resetting AC gains to zero for a receiver coupled to said SERDES link;
(b) resetting DC gains to zero for said receiver coupled to said SERDES link;
(c) nulling out any amplifier offsets;
(d) detecting a frequency of a signal on said SERDES link at said receiver;
(e) when said frequency of said signal has high frequency energy adjusting said AC gains;
(f) when said frequency of said signal has low frequency energy adjusting said DC gains; and
(g) when said frequency of said signal has no frequency energy continuing at (d).

US Pat. No. 9,791,503

PACKAGED OSCILLATORS WITH BUILT-IN SELF-TEST CIRCUITS THAT SUPPORT RESONATOR TESTING WITH REDUCED PIN COUNT

Integrated Device Technol...

1. A packaged integrated circuit device, comprising:
an oscillator circuit having a resonator associated therewith, which is configured to generate a periodic reference signal;
and

a built-in self-test (BIST) circuit electrically coupled to first and second terminals of the resonator during an operation
by said BIST circuit to test for a presence of at least one failure mode associated with the resonator.

US Pat. No. 9,614,508

SYSTEM AND METHOD FOR DESKEWING OUTPUT CLOCK SIGNALS

INTEGRATED DEVICE TECHNOL...

1. A method for deskewing output clock signals, the method comprising:
determining, at a clock generator, a transit time of each of a plurality of traces, each of the plurality of traces coupled
between one of a plurality of clock generator outputs and one of a plurality of clock receivers;

determining a longest transit time of the transit times of each of the plurality of traces;
determining a difference between the longest transit time and the transit time of each of the plurality of traces to identify
a time delay for each of the plurality of clock generator outputs; and

adding the time delay for each of the plurality of clock generator outputs to a output clock signal transmitted from each
of the plurality of clock generator outputs.

US Pat. No. 9,583,155

SINGLE-ENDED SIGNAL SLICER WITH A WIDE INPUT VOLTAGE RANGE

Integrated Device Technol...

1. An apparatus comprising:
a first circuit configured to (i) reduce a current value in a sequence of input values that have been carried on a single-ended
line of a data bus coupled to a memory channel to generate a reduced version of said current value, and (ii) reduce a first
reference voltage to generate a second reference voltage;

a second circuit configured to slice said current value with respect to said first reference voltage to generate a first intermediate
value; and

a third circuit configured to slice said reduced version of said current value with respect to said second reference voltage
to generate a second intermediate value, wherein said first intermediate value and said second intermediate value define a
sliced value of said current value.

US Pat. No. 9,543,960

MULTI-STAGE FREQUENCY DIVIDERS HAVING DUTY CYCLE CORRECTION CIRCUITS THEREIN

INTEGRATED DEVICE TECHNOL...

1. A multi-stage frequency divider, comprising:
a divider circuit responsive to a periodic reference signal to be divided, said divider circuit having at least first and
second integer dividers therein, which are electrically coupled in a cascaded arrangement so that the second integer divider
receives, at an input thereof, an intermediate divider signal derived from a first output of the first integer divider;

a duty cycle enhancement circuit configured to generate an intermediate output signal having an N/N+1 duty cycle in response
to at least first and second output signals generated by said divider circuit, where: (i) N is a positive integer and 2N+1
equals a product of a first divide value of the first integer divider and a second divide value of the second integer divider,
and (ii) at least one of the first and second output signals has a duty cycle less than the N/N+1 duty cycle; and

a duty cycle correction circuit configured to generate a periodic output signal having a uniform duty cycle and a period equal
to the product times a period of the periodic reference signal, in response to the intermediate output signal having the N/N+1
duty cycle.

US Pat. No. 10,320,381

REDUCED VSWR SWITCHING

INTEGRATED DEVICE TECHNOL...

1. A device comprising:a switch configured to mitigate variation in switch impedance during a switch transition from a start state to an end state by stepping the switch a plurality of times through a sequence of steps during the switch transition that step the switch through a sequence of different states from the start state to at least one intermediate state to the end state, wherein the start and end states are static states of the switch and the at least one intermediate state is at least one non-static transitional state of the switch.

US Pat. No. 10,135,955

METHODS AND APPARATUSES FOR A UNIFIED COMPRESSION FRAMEWORK OF BASEBAND SIGNALS

Integrated Device Technol...

1. A method to control compression of data for transmission over a serial data link, the method comprising:adjusting, at a parameter estimation processor, a target compression ratio by a first compression ratio to determine a remaining compression ratio, wherein the first compression ratio was performed by a resampling operation;
estimating, at the parameter estimation processor, a set of compression parameters that are used to achieve the remaining compression ratio, the set of compression parameters includes N attenuation values, a filter order and a type of encoding; and
sending the set of compression parameters to a data sample compressor, the data sample compressor applies the compression parameters to a packet of input data and outputs a plurality of compressed data words, and wherein an attenuator of the data sample compressor divides the packet of input data into N segments and applies an attenuation value from the set of N attenuation values to the data samples in one of the N segments.

US Pat. No. 10,132,650

APPARATUSES AND RELATED METHODS FOR DETECTING MAGNETIC FLUX FIELD CHARACTERISTICS WITH A WIRELESS POWER TRANSMITTER

Integrated Device Technol...

1. A wireless power transmitter, comprising:a transmit coil configured to generate a wireless power signal for wireless power transfer to a wireless power receiver;
at least one secondary sensing coil positioned adjacent to, coplanar with, and positioned outside of the transmit coil and configured to generate a signal responsive to a magnetic flux field generated during the wireless power transfer; and
control logic operably coupled with the at least one secondary sensing coil, the control logic configured to detect a misalignment between the transmit coil and the wireless power receiver responsive to detecting distortion in the magnetic flux field from the signal received from the at least one secondary sensing coil.

US Pat. No. 10,082,823

OPEN LOOP SOLUTION IN DATA BUFFER AND RCD

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:an open loop circuit configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal; and
a delay circuit configured to (i) generate said delayed version of said strobe signal in response to (a) said strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit, (ii) adjust a delay of transferring a data signal through said apparatus in response to (a) said delay amount and (b) said in-phase clock signal and (iii) present said in-phase clock signal and said data signal to a host interface, wherein (A) said data signal is received from said memory interface and (B) said delay of transferring said data signal is implemented to keep a latency of a data transfer within a pre-defined range.

US Pat. No. 10,063,303

FAST MEMORY ACCESS CONTROL FOR PHASE AND GAIN

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a switching circuit configured to generate a plurality of control signals in response to an enable signal, wherein (i) a sequence of pulses is generated in said control signals in response to a plurality of cycles of said enable signal and (ii) a single one of said pulses is generated in a single one of said control signals at a time during each of said cycles of said enable signal is; and
a plurality of registers hardwired as a plurality of subsets, wherein (i) each of said subsets of said registers is configured to (a) receive a corresponding one of said control signals, (b) buffer a plurality of setting values received from a memory and (c) present said setting values from said registers to a plurality of transceiver circuits while said corresponding one of said control signals is in an active state, (ii) said setting values comprise a plurality of phase values and a plurality of gain values used in said transceiver circuits to steer a radio frequency beam and (iii) said transceiver circuits are updated with said setting values from said registers within a predetermined time after each transition of one of said control signals to said active state.

US Pat. No. 10,027,986

APPARATUSES AND METHODS FOR FILTERING NOISE FROM A VIDEO SIGNAL

INTEGRATED DEVICE TECHNOL...

1. An apparatus, comprising:a noise filter system configured to (i) filter noise from a frame of a video signal based on a noise level of the frame to provide a filtered video signal, (ii) select macroblocks of the frame that have an associated weighted activity to variance ratio that exceeds a threshold value and (iii) calculate the noise level of the frame based on estimated noise levels of each of the selected macroblocks of the frame; and
an encoder configured to encode the filtered video signal to provide a compressed bitstream,
wherein (i) the associated weighted activity to variance ratio is determined based on (a) an individual activity value multiplied by a multiplier and (b) an individual variance value,
(ii) the individual activity value of each macroblock of the frame is based on absolute differences between neighboring pixels of the macroblock,
(iii) the individual variance value of each macroblock of the frame is based on (a) a sum of absolute differences in pixel intensity and (b) an average pixel intensity of the macroblock,
(iv) the estimated noise levels of one of the selected macroblocks of the frame is selected from (a) a minimum of half of an activity of the macroblock, (b) half of an activity of a reference macroblock of another frame, and (c) a sum of absolute pixels differences between the macroblock and the reference macroblock; and
(v) the reference macroblock is one of (a) a collocated macroblock of the another frame or (b) a motion-compensated reference macroblock of the another frame.

US Pat. No. 9,897,976

FRACTIONAL DIVIDER USING A CALIBRATED DIGITAL-TO-TIME CONVERTER

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
a first control circuit (i) comprising a plurality of capacitances and (ii) configured to generate an output clock signal
in response to a divided clock signal, a first feedback signal and a second feedback signal;

a second control circuit configured to generate said first feedback signal and an error signal in response to said divided
clock signal and a state signal;

a first feedback circuit configured to generate said state signal in response to said output clock signal; and
a second feedback circuit configured to generate said second feedback signal in response to said error signal, wherein (i)
one or more of said capacitances are engaged to add a delay to one or more edges of said output clock signal, (ii) a number
of said capacitances engaged is selected to reduce jitter on said output clock signal, and (iii) said capacitances are used
each cycle to calibrate said output clock signal.

US Pat. No. 9,847,112

SYNCHRONIZATION OF DATA TRANSMISSION WITH A CLOCK SIGNAL AFTER A MEMORY MODE SWITCH

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
a transmitter configured to transmit data stored in a memory; and
a controller configured to (i) train one or more transmit parameters of said transmitter to synchronize transmission of said
data with a clock signal while in a first mode, (ii) save said transmit parameters in response to a command received while
said transmitter is in said first mode, and (iii) configure said transmitter to transmit said data while in a second mode
using said transmit parameters as learned while in said first mode.

US Pat. No. 9,780,449

PHASE SHIFT BASED IMPROVED REFERENCE INPUT FREQUENCY SIGNAL INJECTION INTO A COUPLED VOLTAGE CONTROLLED OSCILLATOR (VCO) ARRAY DURING LOCAL OSCILLATOR (LO) SIGNAL GENERATION TO REDUCE A PHASE-STEERING REQUIREMENT DURING BEAMFORMING

Integrated Device Technol...

15. A wireless communication system comprising:
a beamforming system comprising:
a plurality of VCOs forming a coupled VCO array, each VCO of the plurality of VCOs being configured to have a reference input
signal injected therein to reduce a level of injection energy required therefor compared to injecting the reference input
signal at an end of the coupled VCO array, and the reference input signal being configured to control operating frequency
of the coupled VCO array;

an antenna array comprising a plurality of antenna elements;
a plurality of mixers, each of which is configured to mix an output of the each VCO of the plurality of VCOs forming the coupled
VCO array with a signal from an antenna element of the antenna array to introduce differential phase shifts in signal paths
coupled to the antenna elements during performing beamforming with the antenna array; and

a phase shift circuit utilized at least one of: between individual VCOs of the coupled VCO array and in a path of injection
of the reference input signal into at least one VCO of the individual VCOs to reduce a phase-steering requirement of the coupled
VCO array during the beamforming; and

a receiver channel configured to receive a combined output of the plurality of mixers of the beamforming system.

US Pat. No. 10,027,989

METHOD AND APPARATUS FOR PARALLEL DECODING

INTEGRATED DEVICE TECHNOL...

1. An apparatus, comprising:an entropy pre-processing unit configured to (i) receive a bitstream, wherein the bitstream is linearly encoded, (ii) determine dependencies between a plurality of frames of the bitstream, to (iii) determine slice location data within the bitstream based on the dependencies between the frames, (iv) identify, based on the slice location data and the dependencies between the frames, a plurality of groups of slices in the bitstream, wherein (a) at least one of the groups comprises one of the slices that was encoded independent of all other slices and (b) at least another one of the groups comprises a plurality of the slices that were encoded with a dependency upon each other;
a plurality of transcoding units configured to (i) each receive the bitstream and the slice location data and (ii) separate the identified groups from the bitstream; and
a plurality of decoders configured to decode in parallel two or more of the slices within the groups separated from the bitstream, wherein (i) a first decoder is configured to decode a first group and (ii) a second decoder is configured to decode, in parallel with the first decoder, a second group.

US Pat. No. 9,921,891

LOW LATENCY INTERCONNECT INTEGRATED EVENT HANDLING

INTEGRATED DEVICE TECHNOL...

1. A method comprising:
receiving from a source an N-bit Event ID at an interrupt controller;
using said interrupt controller to address an N-bit address into an array of event entries;
sending from said interrupt controller an add query entry to an event queue manager;
using said event queue manager to access an array of ready queues; and
wherein said receiving from said source, said using said interrupt controller, said sending from said interrupt controller,
and said using said event queue manager are all done in hardware without using an operating system.

US Pat. No. 9,859,950

WIRELESS POWER RECEIVER WITH MAGNETIC DATA TRANSACTION CAPABILITY

Integrated Device Technol...

1. A dual purpose receiver/transmitter, comprising:
a coil;
a rectifier circuit coupled to the coil, the rectifier circuit including first and second transistors coupled in series between
a power line and a ground line with a first end of the coil coupled between the first and second transistors, and third and
fourth transistors coupled in series between the power line and the ground line with a second end of the coil coupled between
the third and fourth transistors through a first capacitor;

a data transmission circuit including a first switch coupled to the second end of the coil; and
a controller coupled to the rectifier circuit and the data transmission circuit, the controller configured to provide control
signals to the rectifier circuit and to the data transmission circuit to rectify wireless power received by the coil in a
wireless power receive mode and configured to provide control signals to each of the first, second, third, and fourth transistors
of the rectifier circuit and the first switch of the data transmission circuit to provide current to the coil according to
data in a data transmission mode,

wherein the controller operates in a data transmission mode by closing the first switch and modulating current through the
coil by providing gate signals in a non-overlapping fashion to the first transistor and the second transistor according to
the data.

US Pat. No. 9,837,203

APPARATUSES HAVING DIFFERENT MODES OF OPERATION FOR INDUCTIVE WIRELESS POWER TRANSFER AND RELATED METHOD

INTEGRATED DEVICE TECHNOL...

1. A first inductive wireless power enabled device coupled to a first battery, comprising:
a transceiver including a full-bridge circuit operable as a full-bridge inverter and a full-bridge rectifier, the full-bridge
circuit including a plurality of first switches coupled in a full-bridge configuration with a resonant tank circuit, wherein
the transceiver is coupled to the first battery through a second switch;

a charger coupled between the transceiver and the first battery through a third switch, wherein the charger is arranged in
parallel with the second switch; and

control logic configured to:
detect a presence of a second inductive wireless power enabled device coupled to a second battery;
determine which of the first and second batteries has a higher remaining charge;
while the first battery has the higher remaining charge, drive the plurality of first switches to operate the resonant tank
circuit in a transmit mode, close the second switch, and open the third switch; and

while the second battery has the higher remaining charge, drive the plurality of first switches to operate the resonant tank
circuit in a receive mode, open the second switch, and close the third switch.

US Pat. No. 9,712,041

APPARATUSES AND METHODS FOR OVER-CURRENT PROTECTION OF DC-DC VOLTAGE CONVERTERS

INTEGRATED DEVICE TECHNOL...

1. An apparatus, comprising:
a peak current protection circuit including:
a current sensing circuit configured to sense an operating current of a DC-DC converter; and
an over-current detector operably coupled with the current sensing circuit, the over-current detector comprising:
a first circuit to generate a first voltage based on the sensed operating current and a voltage level of an input signal of
the DC-DC converter (VIN);

a second circuit to generate a second voltage based on a voltage level of an output signal from the DC-DC converter (VOUT)
and a reference current (IREF); and

a comparator having a first input for receiving the first voltage, a second input for receiving the second voltage, and an
output for providing an over-current detect signal based on a comparison of the first voltage and the second voltage, the
over-current detect signal indicating whether the sensed operating current exceeds a peak current level which is proportional
to the IREF;

wherein one or more parameters of the over-current detector are selected such that when the first voltage is equal to the
second voltage a contribution of the VOUT to the first voltage is equal to a contribution of the VOUT to the second voltage
so that the over-current detect signal is independent of the VOUT.

US Pat. No. 9,698,787

INTEGRATED LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) AND HIGH-SPEED CURRENT STEERING LOGIC (HCSL) CIRCUIT AND METHOD OF USE

INTEGRATED DEVICE TECHNOL...

1. An integrated circuit comprising:
a low voltage differential signaling (LVDS) output circuit;
a high-speed current steering logic (HCSL) output circuit;
a bias control circuit;
a programmable voltage reference circuit coupled to the bias control circuit;
an output stage circuit coupled to the HCSL output circuit;
a first plurality of switches to switchably couple the bias control circuit to the LVDS output circuit; and
a second plurality of switches to switchably couple the bias control circuit to the output stage circuit and to the HCSL output
circuit.

US Pat. No. 9,640,278

TESTABILITY/MANUFACTURING METHOD TO ADJUST OUTPUT SKEW TIMING

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
an output driver circuit configured to (i) receive a data input signal, an input clock signal, and a first control signal
and (ii) generate a data output signal and an output clock signal, wherein said data output signal is a delayed version of
said data input signal and a length of delay between said data input signal and said data output signal is determined in response
to said first control signal; and

a trimming circuit configured to be enabled during production testing by a command received by said apparatus from automated
test equipment and to generate said first control signal in response to a second control signal, wherein said data input signal
is generated during said production testing in response to a test pattern and a test clock received by said apparatus from
said automated test equipment and said trimming circuit is enabled to (i) vary a value of said first control signal to minimize
a phase difference between said data output signal and said output clock signal, (ii) determine whether the apparatus passes
or fails said production test based upon a trimming result, and (iii) notify the automated test equipment about the pass or
fail status of the apparatus under test.

US Pat. No. 9,542,991

SINGLE-ENDED SIGNAL EQUALIZATION WITH A PROGRAMMABLE 1-TAP DECISION FEEDBACK EQUALIZER

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
a first circuit configured to (i) receive a sequence of input values that have been carried on a single-ended line of a data
bus coupled to a memory channel, (ii) slice a previous input value of said sequence of input values to generate a previous
output value, (iii) slice a current input value of said sequence of input values to generate a current output value, and (iv)
present said current output value on a differential line, wherein said previous input value precedes said current input value
in said sequence of input values; and

a second circuit configured to decode said previous input value based on a tap coefficient value to generate a plurality of
feedback values suitable to reduce an inter-symbol interference in said current input value caused by said previous input
value.

US Pat. No. 10,075,284

PULSE WIDTH MODULATION (PWM) TO ALIGN CLOCKS ACROSS MULTIPLE SEPARATED CARDS WITHIN A COMMUNICATION SYSTEM

INTEGRATED DEVICE TECHNOL...

1. A method for phase alignment of a clock signal at a plurality of line cards, the method comprising:receiving a pulse-width modulated (PWM) clock signal from each of the plurality of line cards at a timing device;
monitoring each of the PWM clock signals from each of the plurality of line cards;
locking a first digital phase-locked loop (DPLL) circuit to a highest priority PWM clock signal that is not experiencing a failure to generate a PWM clock output signal;
determining a propagation delay for each of a plurality of line cards following a round-robin approach at the timing device, the timing device coupled to each of the plurality of line cards over a backplane;
determining, at the timing device, a phase delay correction for each of the plurality of line cards based upon the determined propagation delay for each of the plurality of line cards;
encoding the phase delay correction for each of the plurality of line cards into the PWM clock output signal to generate a phase delay correction encoded PWM clock output signal for each of the plurality of line cards; and
transmitting the phase delay correction encoded PWM clock output signal to each of the plurality of line cards following the round-robin approach.

US Pat. No. 10,075,749

TRANSPORT STREAM MULTIPLEXERS AND METHODS FOR PROVIDING PACKETS ON A TRANSPORT STREAM

INTEGRATED DEVICE TECHNOL...

1. A method, comprising:reading a metadata array at a position indicated by an index pointer, wherein a release time stamp is stored at the position in the metadata array;
assigning an assigned release time stamp to a transport stream packet based on the release time stamp stored at the position indicated by the index pointer; and
providing, using a transport stream multiplexer, the transport stream packet on the transport stream at a time corresponding to the assigned release time stamp.

US Pat. No. 9,979,290

DUAL USE BOOTSTRAP DRIVER

Integrated Device Technol...

1. A switching regulator, comprising:a high switch coupled between an input voltage and a switched output;
a low switch coupled between the switched output and a ground; and
a ringing switch coupled between a capacitor and the switched output,
wherein the ringing switch is closed prior to transition into a tristate where both the high switch and the low switch are open.

US Pat. No. 9,905,995

ADJUSTABLE TERMINATION CIRCUIT FOR HIGH SPEED LASER DRIVER

Integrated Device Technol...

1. A circuit comprising:
a high speed laser driver circuit;
a semiconductor laser electrically connected to the high speed laser driver circuit; and
an adjustable termination circuit electrically connected between the high speed laser driver circuit and the semiconductor
laser, wherein the adjustable termination circuit is configured to control an output impedance seen by the semiconductor laser
as a function of an input current provided to the adjustable termination circuit,

wherein the adjustable termination circuit comprises an operational amplifier configured to drive an input offset voltage,
across inputs to the operational amplifier, to zero,

wherein one of the inputs to the operational amplifier is electrically connected in series between a power source and an offset
resistor,

wherein the power source is configured to provide an input current to the offset resistor, thereby generating the input offset
voltage across the inputs of the operational amplifier, and

wherein the operational amplifier comprises an output electrically connected to a base terminal of a transistor, wherein an
emitter terminal of the transistor is electrically connected to a termination resistor.

US Pat. No. 9,847,869

FREQUENCY SYNTHESIZER WITH MICROCODE CONTROL

Integrated Device Technol...

1. A method for controlling a frequency synthesizer system, the method comprising:
setting the frequency synthesizer system to operate in a microcode mode, the frequency synthesizer system including a data
memory circuit having a master stage, a slave stage and a switch that extends between the master stage and the slave stage;

programming the frequency synthesizer system for microcode execution of a plurality of microcode instructions by disabling
the switch, loading a plurality of microcode instructions into the master stage of the data memory circuit and storing a sequence
of addresses for the plurality of microcode instructions in a memory of the frequency synthesizer system; and

executing the plurality of microcode instructions at the frequency synthesizer system to control one or more behaviors of
one or more programmable circuits of the frequency synthesizer system.

US Pat. No. 9,589,626

SINGLE-ENDED MEMORY SIGNAL EQUALIZATION AT POWER UP

Integrated Device Technol...

1. An apparatus comprising:
a first circuit configured to buffer an input signal received as a single-ended signal from a data bus connected between a
memory channel and a memory controller; and

a second circuit configured to equalize said input signal relative to a reference voltage to generate a differential signal,
wherein said reference voltage is isolated from said second circuit in response to a transition from a power down condition
to a power on condition.

US Pat. No. 9,553,954

METHOD AND APPARATUS UTILIZING PACKET SEGMENT COMPRESSION PARAMETERS FOR COMPRESSION IN A COMMUNICATION SYSTEM

Integrated Device Technol...

1. A method for data compression in a communication system, the method comprising:
receiving an uncompressed data packet at a compressor of a communication system, the uncompressed data packet comprising a
plurality of signal samples;

identifying a desired compression ratio for the uncompressed data packet;
measuring the energy variation of the uncompressed data packet;
segmenting the uncompressed data packet into a plurality of packet segments based on the measured energy variation, wherein
each of the plurality of packet segments comprises one or more signal samples and wherein packet segments having a lower measured
energy variation have more signal samples than packet segments having a higher measured energy variation;

estimating at least one packet segment compression parameter for each of the plurality of packet segments based upon the desired
compression ratio;

compressing each of the plurality of packet segments using the at least one estimated packet segment compression parameter
for the packet segment to generate a compressed packet; and

embedding the at least one estimated packet segment compression parameter into the compressed packet.

US Pat. No. 10,063,274

METHOD TO BUILD ASYMMETRICAL TRANSMIT/RECEIVE SWITCH WITH 90 DEGREES IMPEDANCE TRANSFORMATION SECTION

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:an input port;
an output port;
a common port;
a first impedance matching network coupled between said input port and said common port;
a second impedance matching network coupled between said common port and said output port;
a first switch circuit coupled between said input port and a circuit ground potential; and
a second switch circuit coupled between said output port and said circuit ground potential, wherein (i) said first impedance matching network provides a first impedance when said first switch circuit is in a non-conducting state and said second switch circuit is in a conducting state, (ii) said second impedance matching network provides a second impedance when said first switch circuit is in a conducting state and said second switch circuit is in a non-conducting state, and (iii) the first impedance and the second impedance are asymmetrical.

US Pat. No. 10,032,497

FLEXIBLE POINT-TO-POINT MEMORY TOPOLOGY

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a plurality of memory devices; and
a control circuit comprising a duplex registered clock driver and a plurality of duplex data buffers, each configured to operate with two channels, said control circuit configured to enable a plurality of access modes for said plurality of memory devices, wherein (i) in a one-channel mode all of said memory devices are accessed using a single selectable channel, (ii) in a two-channel mode a first portion of said plurality of memory devices is accessed using a first channel and a second portion of said plurality of memory devices is accessed using a second channel, and (iii) each of said duplex data buffers comprises one or more control ports, a first input/output port for communicating with a system bus using said first channel, a second input/output port for communicating with said system bus using said second channel, a third input/output port for communicating with said first portion of said plurality of memory devices, and a fourth input/output port for communicating with said second portion of said plurality of memory devices.

US Pat. No. 9,998,180

APPARATUSES AND RELATED METHODS FOR MODULATING POWER OF A WIRELESS POWER RECEIVER

Integrated Device Technol...

1. A wireless power enabled apparatus, comprising:a wireless power receiver, including:
a resonant tank configured to generate an AC power signal responsive to an electromagnetic field, wherein the AC power signal fluctuates among a range of voltages during operation, wherein a high end of the range is greater than or equal to 4 times a low end of the range;
a rectifier including a plurality of switches configured to receive the AC power signal and generate a DC output power signal at a rectified voltage level, wherein the plurality of switches enter a breakdown state when the rectified voltage level reaches a breakdown voltage level that is less than or equal to 1.6 times a desired voltage level; and
control logic configured to monitor a voltage of the wireless power receiver, detect a trend in the monitored voltage, and select an overlap delay such that the plurality of switches are temporarily enabled at the same time, the overlap delay being selected based on the trend to maintain the rectified voltage level near the desired voltage level without exceeding the breakdown voltage level.

US Pat. No. 9,979,237

ADAPTIVE RESONANT TOPOLOGY APPLICATION IN WEARABLE DEVICES

Integrated Device Technol...

1. A device, comprising:a receive coil for receiving power from a transmit coil, the receive coil having an inner diameter, an outer diameter, and a thickness;
one or more sensors located within the inner diameter of the receive coil;
a first transistor coupled between a first side of the receive coil and ground;
a second transistor coupled between a second side of the receive coil and ground; and
a receive switching circuit coupled to gates of the first transistor and the second transistor, the receive switching circuit adaptively switching the first transistor and the second transistor such that the receive coil operates at a resonant frequency of the transmit coil.

US Pat. No. 9,794,087

ASYMMETRIC ON-STATE RESISTANCE DRIVER OPTIMIZED FOR MULTI-DROP DDR4

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
a plurality of driver circuits configured to drive a read line in response to a memory signal and a reference voltage to transfer
read data across said read line to a memory controller; and

a plurality of control registers configured to enable a first number of said driver circuits to operate solely as pull up
drivers and a second number of said driver circuits to operate solely as pull down drivers, wherein (a) a pull up strength
and a pull down strength of said memory signal is configured in response to how many of said plurality of driver circuits
are enabled as said pull up drivers and said pull down drivers, respectively, and (b) said plurality of driver circuits and
said plurality of control registers implement an asymmetric voltage swing of said read line about a voltage level that is
half of said reference voltage by setting said first number different from said second number.

US Pat. No. 9,577,438

WIRELESS POWER SYSTEM

INTEGRATED DEVICE TECHNOL...

1. A transmitter for wireless power transfer, comprising:
a TX coil;
a capacitor coupled across the TX coil;
at least one inductor coupled between a power source and the TX coil;
a pair of switching FETs including a first switching FET coupled between a first side of the capacitor and ground and a second
switching FET coupled between a second side, opposite the first side, of the capacitor and ground, the gates of the first
switching FET and the second switching FET being driven to provide an oscillating current through the TX coil,

wherein the gate of the first switching FET is switched from off to on and the gate of the second switching FET is switched
from on to off when a first voltage across the second switching FET decreases to zero volts; and

a resonant frequency shifting circuit coupled between drains of the first switching FET and the second switching FET, the
resonant frequency shifting circuit being driven by a modulator.

US Pat. No. 9,551,805

APPARATUS, SYSTEM, AND METHOD FOR DETECTING A FOREIGN OBJECT IN AN INDUCTIVE WIRELESS POWER TRANSFER SYSTEM VIA COUPLING COEFFICIENT MEASUREMENT

INTEGRATED DEVICE TECHNOL...

1. An inductive wireless power device, comprising:
a transmitter configured to generate an electromagnetic field to a coupling region for wireless power transfer to a receiver;
a predefined coupling coefficient for the wireless power transfer; and
a control logic configured to determine a coupling coefficient of the wireless power transfer when the receiver is within
the coupling region by detecting a change in a wireless power transfer characteristic caused by the receiver at a first time
and a second time, and to determine a presence of a foreign object within the coupling region responsive to a comparison of
the determined coupling coefficient and the predefined coupling coefficient for the wireless power transfer.

US Pat. No. 10,110,209

PROCESS COMPENSATED DELAY

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising a positive temperature coefficient bandgap reference coupled to a positive input of an operational amplifier, an output of said operational amplifier coupled to a first transistor gate, a source of said first transistor directly coupled to a negative input of said operational amplifier and a drain of a second transistor, a drain of said first transistor coupled to a current mirror, a thick oxide nMOS varactor coupled to said current mirror.

US Pat. No. 10,084,457

FREQUENCY SYNTHESIZER WITH TUNABLE ACCURACY

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a first circuit configured to generate a first code by counting a number of cycles of an input clock signal during a period, wherein (a) said period is determined by (i) an output clock signal and (ii) a second code, and (b) said second code (i) is read from a memory internal to said first circuit and (ii) has a variable multi-bit value;
a second circuit configured to generate a third code by a delta-sigma modulation of said first code; and
a third circuit configured to generate said output clock signal (i) in response to said third code and (ii) within a frequency accuracy determined by a current value of said second code.

US Pat. No. 9,991,818

APPARATUSES AND RELATED METHODS FOR A WIRELESS POWER RECEIVER USING COUPLED INDUCTORS

Integrated Device Technol...

1. A wireless power receiver, comprising:one or more receive coils configured to generate an AC power signal responsive to a wireless power signal;
two or more inductors configured with tightly coupled windings that share a common leakage inductance;
two or more switching circuits, each switching circuit operably coupled to a corresponding one of the two or more inductors; and
control logic configured to operate switches of the two or more switching circuits such that each of the two or more switching circuits and its corresponding one of the two or more inductors are operated to shift between an energy storage mode for one or more phases of a switching period and an energy transfer mode for other phases of the switching period and the phases combine to comprise an entirety of the switching period;
wherein a pattern of the one or more energy storage mode phases and the one or more energy transfer mode phases for each of the two or more switching circuits and its corresponding one of the two or more inductors during the switching period is different from patterns of the one or more energy storage mode phases and the one or more energy transfer mode phases of others of the two or more switching circuits and their one of the two or more inductors during the switching period.

US Pat. No. 9,954,516

TIMING DEVICE HAVING MULTI-PURPOSE PIN WITH PROACTIVE FUNCTION

Integrated Device Technol...

1. A timing device comprising:an input terminal;
an output terminal;
a data storage device configured to store one or more operating mode selection bit; and
a first periodic signal generator operable to generate a first periodic signal having a first frequency at an output thereof;
a second periodic signal generator operable to generate a second periodic signal having a second frequency at an output thereof, the second frequency lower than the first frequency; and
selection logic electrically coupled to the input terminal, the output terminal, the data storage device, the first periodic signal generator and the second periodic signal generator, the selection logic configured to receive the one or more operating mode selection bit from the data storage device, and when the configuration data indicates a first operating mode the selection logic configured to output the first periodic signal at the output terminal as long as a crystal clock feedback signal is received at the input terminal and output the second periodic signal at the output terminal when the crystal clock feedback signal is not received at the input terminal, and when the one or more operating mode selection bit indicates a second operating mode the selection logic configured to output the first periodic signal as long as a output enable signal is received at the input terminal and not provide any output at the output terminal when the output enable signal is not received at the input terminal.

US Pat. No. 9,898,060

SYSTEM AND METHOD FOR WIRELESS POWER TRANSFER USING AUTOMATIC POWER SUPPLY SELECTION

INTEGRATED DEVICE TECHNOL...

1. An electronic system comprising:
an electronics module;
a primary power supply that receives power from a primary external power source and supplies the received power to the electronics
module when operative;

a secondary power supply that receives power from a secondary external power source and supplies the received power to the
electronics module when operative; and

a selection module having first and second input rails coupled to the primary and secondary power supplies, respectively,
an output rail coupled to the electronics module, a first switch coupled between the first input rail and the output rail,
and a second switch coupled between the second input rail and the output rail; wherein:

when the primary power supply is operative, the selection module selects the primary power supply to supply power to the electronics
module and disables the secondary power supply, wherein the first switch is closed and the second switch is open;

when the primary power supply is not operative and the secondary power supply is operative, the selection module selects the
secondary power supply to supply power to the electronics module, wherein the first switch is open and the second switch is
closed; and

when the secondary power supply is disabled, the secondary power supply disables the secondary external power source;
and wherein when the first or second switch is open, reverse leakage current is blocked from flowing from the output rail
towards the input rail corresponding to the open switch.

US Pat. No. 9,838,016

ADAPTIVE HIGH-SPEED CURRENT-STEERING LOGIC (HCSL) DRIVERS

Integrated Device Technol...

1. An integrated circuit device, comprising:
a first driver having a first pair of differential output terminals and a first common-mode sensing terminal associated with
the first pair of differential output terminals;

a second driver having a second pair of differential output terminals and a second common-mode sensing terminal associated
with the second pair of differential output terminals;

a comparator configured to compare first and second common-mode voltage signals developed at the first and second common-mode
sensing terminals, respectively; and

a reference signal generator configured to provide said first and second drivers with a reference voltage having a magnitude
that varies in response to changes in a signal generated at an output terminal of said comparator.

US Pat. No. 9,831,882

FAST-RESPONSE HYBRID LOCK DETECTOR

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:
an analog circuit configured to generate an enable signal in response to (i) a first comparison of a width of an up pulse
and a pre-determined width and (ii) a second comparison of a width of a down pulse and said pre-determined width, wherein
(a) said up pulse and said down pulse are generated in response to a comparison of a feedback signal and a reference signal
and (b) said enable signal is active when both said first comparison and said second comparison are within a pre-determined
threshold; and

a digital circuit configured to generate an output signal representing a lock status between (i) said feedback signal and
(ii) said reference signal, wherein (A) said lock status is determined (a) during a decision window based on a number of pulses
of said reference signal and (b) when said enable signal is active, and (B) said decision window is repeated periodically
until said enable signal is not active.

US Pat. No. 9,495,285

INITIATING OPERATION OF A TIMING DEVICE USING A READ ONLY MEMORY (ROM) OR A ONE TIME PROGRAMMABLE NON VOLATILE MEMORY (OTP NVM)

INTEGRATED DEVICE TECHNOL...

1. A timing device comprising:
a timing device circuit for generating at least one timing signal:
a static random access memory (SRAM) coupled to the timing device circuit;
a read only memory (ROM) having a first timing device configuration stored therein;
a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration; and
selection logic having an output coupled to the SRAM and having a first input coupled to the ROM and a second input coupled
to the OTP NVM, the selection logic operable to receive input indicating whether the SRAM is to be loaded from the ROM or
the OTP NVM, and operable to load either the first timing device configuration from the ROM or the second timing device configuration
from the OTP NVM based on the input.

US Pat. No. 9,692,394

PROGRAMMABLE LOW POWER HIGH-SPEED CURRENT STEERING LOGIC (LPHCSL) DRIVER AND METHOD OF USE

INTEGRATED DEVICE TECHNOL...

1. An integrated circuit comprising:
a voltage regulator circuit including a voltage comparator and a native source follower transistor;
a programmable low power high-speed current steering logic (LPHCSL) driver circuit comprising a plurality of selectable output
driver legs and a plurality of programmable resistors; and

a common supply voltage coupled to the voltage regulator circuit, the voltage comparator, the native source follower transistor
and to the programmable LPHCSL driver circuit.

US Pat. No. 10,146,722

METHOD AND APPARATUS FOR OPERATING OF A PCIE RETIMER OVER OPTICAL CABLE

INTEGRATED DEVICE TECHNOL...

1. A method comprising:communicating an Optical Idle ordered set during Electrical Idle in a flowing LTSSM states in a Peripheral Component Interconnect Express (PCIe) protocol, wherein said Optical Idle ordered set keeps an optical link active during data rate changes;
wherein said Optical Idle ordered set is for either:
a 8b10b COM, IDL, IDL, EIE is COM=K28.5, EIE=K28.7, and IDL=K28.3; or
a 128b130b is Symbols 0-7=0x66, Symbols 8, 10, 12, 14=0x00, and Symbols 9, 11, 13, 15=0xFF.

US Pat. No. 9,954,398

SUPPRESSION OF AUDIBLE HARMONICS IN WIRELESS POWER RECEIVERS

Integrated Device Technol...

1. A wireless power enabled apparatus, comprising:a wireless power receiver, including:
a receive coil configured to generate an AC power signal responsive to a wireless power signal at a frequency;
a rectifier configured to receive the AC power signal and generate a DC rectified power signal relative to a rectified ground;
a regulator operably coupled with the rectifier to receive the DC rectified power signal and generate an output voltage; and
a damping circuit operably coupled between the DC rectified power signal and the rectified ground and in parallel with the regulator, the damping circuit configured to suppress harmonics of the frequency that produce audible harmonics at the wireless power receiver by providing a damping impedance for the DC rectified power signal at the harmonics of the frequency, the harmonics of the frequency producing the audible harmonics at some loads on the regulator.

US Pat. No. 9,929,568

METHODS AND APPARATUSES FOR POWER CONTROL DURING BACKSCATTER MODULATION IN WIRELESS POWER RECEIVERS

INTEGRATED DEVICE TECHNOL...

1. A wireless power receiver, comprising:a receive coil configured to generate an AC power signal responsive to a wireless power signal;
a rectifier configured to receive the AC power signal and generate a DC rectified power signal;
a power transistor operably coupled in a pass-transistor configuration and comprising an input node to receive the DC rectified power signal and an output node to provide an output power signal, the power transistor configured to operate in a substantially constant current mode during a communication period employing backscatter modulation on the receive coil;
a compensation current source coupled to the output node of the power transistor and configured to maintain a substantially constant voltage on the output power signal by adjusting a current through the compensation current source; and
a control logic coupled to the output node of the power transistor and configured to enable the compensation current source during the communication period.

US Pat. No. 10,103,711

CONSTANT IMPEDANCE SWITCH

INTEGRATED DEVICE TECHNOL...

1. A device comprising:a switch comprising a plurality of variable impedances configured to dynamically manage switch impedance during a first switching event by stepping a variable impedance in the plurality of variable impedances through an impedance sequence that changes the variable impedance a plurality of times to a plurality of different discrete impedance values during the first switching event to maintain the switch impedance during the first switching event, where the first switching event comprises a single state transition of the switch from a first state to a second state.

US Pat. No. 10,057,601

METHODS AND APPARATUSES FOR FILTERING OF RINGING ARTIFACTS POST DECODING

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a decode module configured to (i) receive a bitstream, (ii) generate a block by decoding the bitstream and (iii) extract a quantization parameter used to encode the block from the bitstream;
a maximum difference module coupled to the decode module, and configured to (i) receive the block and the quantization parameter from the decode module, and (ii) determine a first threshold of the block based on a plurality of pixels in the block and the quantization parameter; and
a de-ringing filter module coupled to the maximum difference module and the decode module, and configured to (i) receive the first threshold from the maximum difference module, (ii) receive the block from the decode module, (iii) determine a second threshold based on the first threshold, wherein the second threshold is higher than the first threshold, (iv) determine a weighting factor for a first pixel among the pixels in the block based on a comparison of (a) an absolute difference between the first pixel and a second pixel among the pixels in the block with (b) the first threshold and the second threshold and (v) filter the second pixel based on the weighting factor.

US Pat. No. 9,553,570

CRYSTAL-LESS JITTER ATTENUATOR

Integrated Device Technol...

1. An integrated circuit to remove jitter from a clock signal, comprising:
an integrated circuit die, further comprising:
a signal comparator, the signal comparator is configured to determine a frequency difference between a jittery input clock
signal and a correction signal, wherein the signal comparator is a frequency comparator that counts a first number of clock
cycles occurring on the correction signal within a fixed time window, and the frequency comparator counts a second number
of clock cycles occurring on the jittery input clock signal within the fixed window of time;

a digital low pass filter, the digital low pass filter is coupled to receive and filter the frequency difference and to provide
a filtered output signal;

a free running crystal-less oscillator, the free running crystal-less oscillator produces a reference signal; and
a fractional output divider, the fractional output divider is coupled to the free running crystal-less oscillator and the
digital low pass filter, the fractional output divider utilizes the filtered output signal to establish a value to divide
a frequency of the reference signal by to obtain a clean output clock signal, the clean output clock signal is fed back to
the signal comparator as the correction signal.

US Pat. No. 10,241,538

RESYNCHRONIZATION OF A CLOCK ASSOCIATED WITH EACH DATA BIT IN A DOUBLE DATA RATE MEMORY SYSTEM

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:an input interface comprising a plurality of input stages each configured to (i) receive (a) a data signal and (b) a clock signal through a first clock tree and (ii) present an intermediate signal;
an output interface comprising a plurality of output stages each configured to (i) receive said intermediate signal from one of said input stages, (ii) receive an adjusted clock signal and (iii) present an output signal; and
an adjustment circuit comprising a plurality of adjustment components each configured to (i) receive said clock signal through a second clock tree, (ii) receive a reference clock signal, and (iii) generate said adjusted clock signals presented to each of said output stages, wherein (a) said adjustment circuit is located near said output interface, and (b) each of said adjustment components is configured to resynchronize said clock signal for each respective bit transmitted from said input interface to said output interface to reduce a bit to bit delay caused by said clock tree.

US Pat. No. 10,021,409

APPARATUSES AND METHODS FOR ESTIMATING BITSTREAM BIT COUNTS

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:an encoder circuit configured to encode a plurality of syntax elements according to a first entropy encoding technique to generate an encoded bitstream;
an estimator circuit configured to generate an estimated bit count corresponding to the syntax elements (i) as if the syntax elements were encoded with a second entropy encoding technique and (ii) based solely on the syntax elements, wherein the generation of the estimated bit count includes (a) generating first information in response to modes and a spatial context, (b) generating second information and third information in response to the syntax elements and the spatial context, (c) reading a plurality of intermediate counts from a plurality of lookup tables based on the first information, the second information and the third information and (d) summing the intermediate counts to generate the estimated bit count;
a mode decision circuit configured to adjust the encoding of the syntax elements according to the first entropy encoding technique in response to the estimated bit count; and
a transcoder circuit (i) coupled to the encoder circuit and (ii) configured to generate a transcoded bitstream according to the second entropy encoding technique by transcoding the encoded bitstream, wherein an actual bit rate of the transcoded bitstream is controlled based on the estimated bit count.

US Pat. No. 10,320,376

FREQUENCY DIVIDER WITH SELECTABLE FREQUENCY AND DUTY CYCLE

Integrated Device Technol...

1. A frequency divider system comprising:a split-divisor frequency divider module that receives a clock signal and generates an output signal based on a first divisor and a second divisor, the clock signal and output signal each having rectangular waveforms characterized by a respective frequency and pulse width;
wherein:
the frequency of the output signal is a selectable integer fraction of the frequency of the clock signal, the frequency of the output signal being selected based on a sum of the first and second divisors;
the pulse width of the output signal is a selectable integer number of clock cycles of the clock signal, the pulse width of the output signal being selected based on at least one of the first divisor and the second divisor;
a fractional pulse width adjuster module, the fractional pulse width adjuster module is configured to adjust the pulse width of a split-divisor frequency divider module output signal by a fraction of an input clock cycle; and
a high frequency bypass module, the high frequency bypass module configured to bypass one or more stages of the frequency divider,
wherein the split-divisor frequency divider module comprises:
a selector module configured to select between the first and second divisors based on a control input, the control input being coupled to the output signal of the split-divisor frequency divider module;
an integer divider configured to generate pulses every N2 clock cycles, where N2 is set to one of the first and second divisors selected by the selector module; and
a toggle module configured to toggle the output signal at each low-to-high or high-to-low transition of the pulses generated by the integer divider.

US Pat. No. 10,312,736

WIRELESS POWER TRANSMITTER

Integrated Device Technol...

1. A wireless power transmitter, comprising:a resonant circuit, the resonant circuit including a transmit coil;
a transformer with a primary inductor and a secondary inductor connected to the resonant circuit, the primary inductor including a center tap, a first end tap, and a second end tap;
a switching circuit that alternately couples the first end tap and the second end tap to ground; and
a regulator coupled to the center tap, the regulator configured to control a power level of power transmitted by the transmit coil, in response to power requirements received from a wireless power receiver and errors detected in a current level of the primary inductor.

US Pat. No. 10,313,565

METHODS AND APPARATUSES FOR EDGE PRESERVING AND/OR EDGE ENHANCING SPATIAL FILTER

INTEGRATED DEVICE TECHNOL...

1. A method for edge preserving, comprising the steps of:generating a plurality of absolute pixel value differences between a target pixel and each pixel of a set of pixels surrounding the target pixel using a filter circuit;
comparing each of the absolute pixel value differences to a first threshold and second threshold, wherein the first threshold is different than the second threshold;
generating a plurality of weighting factors corresponding to the pixels in the set of pixels based on the comparisons, wherein the weighting factors are set to (i) a first value where a corresponding one of the absolute pixel value differences is less than a first threshold, (ii) a second value where the corresponding absolute pixel value difference is greater than a second threshold and (iii) a third value in a range of values between the first value and the second value where the corresponding absolute pixel value difference is between the first threshold and the second threshold;
generating a plurality of weighted pixels by multiplying the weighting factors by the pixels in the set of pixels;
generating a filtered pixel by filtering the target pixel based on the weighted pixels, wherein the filtering reduces random noise from frames while maintaining one or more edges in the frames; and
generating a bitstream by encoding the filtered pixel using an encoder circuit.

US Pat. No. 10,284,015

WIRELESS POWER TRANSMITTER

Integrated Device Technol...

1. A wireless resonant transmission unit, comprising:a first inductor with a center tap, a first end tap and a second end tap;
a first transistor coupled between the first end tap and a ground;
a second transistor coupled between the second end tap and the ground;
a pre-regulator coupled to provide current to the center tap, the pre-regulator configured to control the current through the first inductor to control a power transmitted by a transmit coil, in response to power requirements received from a wireless power receiver and errors detected in a current level of the first inductor; and
a resonant circuit with the transmit coil magnetically coupled to the first inductor,
wherein gates of the first transistor and the second transistor are driven to transmit power with the resonant circuit to the wireless power receiver.

US Pat. No. 10,230,956

APPARATUSES AND METHODS FOR OPTIMIZING RATE-DISTORTION OF SYNTAX ELEMENTS

INTEGRATED DEVICE TECHNOL...

1. An encoder comprising:a DC optimization block, comprising
a forward quantization block configured to quantize a current differentially coded syntax element,
a difference block configured to generate a differentially coded syntax element differential by subtracting a previous differentially coded syntax element from the current differentially coded syntax element,
a candidate generation block configured to generate a plurality of candidates corresponding to respective differential levels of the differentially coded syntax element differential, each of the plurality of candidates based, at least in part, on the differentially coded syntax element differential and providing a respective rate-distortion cost, wherein (a) the respective rate-distortion cost comprises a sum of (i) a rate cost determined for each candidate and (ii) a distortion cost determined for each candidate, and (b) the distortion cost is determined by adding the previous differentially coded syntax element to each candidate, inverse quantizing the sum of the previous differentially coded syntax element and each candidate, squaring, and multiplying by an inverse lambda factor of the encoder, and
a best cost block coupled to the candidate generation block and configured to select a candidate of the plurality of candidates according to one or more criteria, wherein the plurality of candidates are simultaneously considered by the best cost block; and
an AC quantization block configured to receive a plurality of AC coefficients and quantize the plurality of AC coefficients.

US Pat. No. 9,954,581

APPARATUSES AND RELATED METHODS FOR COMMUNICATION WITH A WIRELESS POWER RECEIVER

INTEGRATED DEVICE TECHNOL...

1. An apparatus for wireless power transfer, the apparatus comprising:a wireless power receiver, including:
a receive coil configured to generate an AC power signal responsive to a wireless power signal;
a rectifier coupled to the receive coil and configured to receive the AC power signal and generate a DC rectified power signal;
a first regulator coupled with the rectifier to receive the DC rectified power signal and generate an output power signal;
a second regulator coupled with the rectifier to receive the rectified power signal and generate an output voltage;
a secondary storage device coupled with the second regulator to receive the output voltage of the second regulator; and
control logic coupled to the second regulator and configured to communicate a wireless communication signal across the receive coil by adjusting an impedance of the second regulator;
wherein an impedance of the first regulator is independent of said communicating the wireless communication signal;
wherein the control logic is coupled to the first regulator to control the first regulator to generate the output power signal; and
the control logic is configured to communicate the wireless communication signal across the receive coil by adjusting the impedance of the second regulator but not the first regulator.

US Pat. No. 10,313,470

HIERARCHICAL CACHING AND ANALYTICS

INTEGRATED DEVICE TECHNOL...

1. A system comprising:at least one end-node implementing a first stage of a multi-stage hierarchical analytics and caching technique, wherein said end-node is configured to communicate directly with one or more other end-nodes via one or more wireless links;
at least one edge node implementing a second stage of the multi-stage hierarchical analytics and caching technique, wherein said edge node is configured to communicate directly with one or more end nodes and one or more other edge nodes via wireless links; and
an edge cloud video headend implementing a third stage of the multi-stage hierarchical analytics and caching technique and configured to communicate with one or more of said end-nodes and one or more of said edge nodes, wherein said edge cloud video headend is configured to communicate with said one or more edge nodes using cable interconnections, optical interconnections, and wireless interconnections, the at least one end-node, the at least one edge node, and the edge cloud video headend each comprise an analytics and caching module/server that includes a flexible computing engine configured to implement low latency remote memory and storage access acceleration and predictive traffic shaping, and a low latency switching fabric performs predictive routing of packets using a destination ID assigned to each node and maps the destination ID to individual wavelengths of the optical interconnections.

US Pat. No. 10,306,484

LONG RANGE BEAMFORMING AND STEERING IN WIRELESS COMMUNICATION LINKS

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a transceiver circuit comprising a plurality of fed channels configured to generate a plurality of signals;
an antenna comprising a plurality of antenna arrays configured to generate a plurality of beams in response to said signals, wherein each of said antenna arrays (i) comprises a plurality of subarrays and (ii) is coupled to said fed channels of said transceiver circuit; and
a focus array comprising a plurality of focal zones configured to reflect said beams into a beam zone, wherein (i) each of said beams is steerable by said antenna to one of said focal zones at a time, (ii) said focal zones redirect said beams to a plurality of locations within said beam zone, (iii) each of said focal zones is associated with a respective one of said locations within said beam zone, (iv) said transceiver circuit is further configured to steer one or more of said beams among different ones of said focal zones of said focus array to coarsely redirect said one or more beams to different ones of said locations in said beam zone and (v) adjust one or more respective phase centers of said one or more beams to finely steer said one or more beams within said locations.

US Pat. No. 10,277,907

RATE-DISTORTION OPTIMIZERS AND OPTIMIZATION TECHNIQUES INCLUDING JOINT OPTIMIZATION OF MULTIPLE COLOR COMPONENTS

INTEGRATED DEVICE TECHNOL...

1. A video encoder comprising:a transform circuit configured to transform a residual representation of a video signal in a spatial domain to a plurality of first transform coefficients in a frequency domain and a first color domain, wherein the video signal will be encoded in the first color domain; and
an optimizer circuit configured to (i) generate a plurality of additional transform coefficients in the frequency domain and the first color domain by interpolating the first transform coefficients, (ii) generate a plurality of second transform coefficients by converting the first transform coefficients and the additional transform coefficients from the first color domain to a second color domain, wherein (a) the second color domain is different than the first color domain and (b) the video signal will be displayed in the second color domain, (iii) generate a plurality of candidate transform coefficients from each one of the second transform coefficients and (iv) generate a plurality of optimized transform coefficients from the first transform coefficients and the additional transform coefficients using a cost calculation based on rate and distortion, wherein the cost calculation includes a combination of distortion metrics calculated from the second transform coefficients and the candidate transform coefficients.

US Pat. No. 10,235,295

SCALABLE COHERENT APPARATUS AND METHOD

INTEGRATED DEVICE TECHNOL...

1. A transaction identification mapping for coherent RapidIO memory transactions between a plurality of external hardware processing elements comprising:for a Request Class Packet Type 2 encoding the 8-bit srcTID (source transaction identification) as a combination of bits from a 4-bit AXI ID (advanced extensible interface identification) and an 8-bit AXI ID; and
for a Response Class Packet Type 13 decoding the targetTID (target transaction identification) into a combination of bits for a 4-bit AXI ID and an 8-bit AXI ID.

US Pat. No. 10,236,870

SIGNAL DRIVER SLEW RATE CONTROL

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a first circuit configured to generate an intermediate signal by delaying an input signal by a programmable duration;
a second circuit configured to (i) generate a plurality of delayed signals each as a copy of said intermediate signal shifted in time by a sequence of respective delays based on a control signal, and (ii) change a number of driver signals that are active during each delay in said sequence of respective delays based on said plurality of delayed signals to control a slew rate of an output signal, wherein each delay in said sequence of respective delays except an initial delay has another programmable duration controlled by said control signal over a range of durations; and
a third circuit configured to drive said output signal in response to said driver signals.

US Pat. No. 10,230,476

METHOD AND APPARATUS FOR FLEXIBLE COHERENT AND SCALE-OUT COMPUTING ARCHITECTURE

INTEGRATED DEVICE TECHNOL...

1. A system for communicating and switching in a scale-out architecture comprising:a first functional unit, the first functional unit comprising one or more systems on a chip (SoC), each SoC having one or more integrated photonic interfaces;
a second functional unit, the second functional unit being a switch, the switch having one or more integrated photonic interfaces;
one of the first functional unit integrated photonic interfaces coupled to one of the second functional unit integrated photonic interfaces thereby forming a photonics link; andwherein the first functional unit comprises:one or more processing units, wherein each processing unit includes a central processor unit (CPU) coupled to a bus;
one or more accelerator functions coupled to the bus;
a flexible fabric controller coupled to the bus and coupled to a first input of a multiplexer/demultiplexer; and
a fixed input output controller coupled to the bus and coupled to a second input of the multiplexer/demultiplexer.

US Pat. No. 10,211,720

WIRELESS POWER TRANSMITTER HAVING LOW NOISE AND HIGH EFFICIENCY, AND RELATED METHODS

Integrated Device Technol...

1. A wireless power transmitter, comprising:a bridge inverter including
a first switch and a second switch coupled together with a first switching node therebetween, the first and second switches being in series between a first terminal and a second terminal, the first and second terminals to receive, at the first and second terminals, a DC power signal comprising a first terminal voltage and a second terminal voltage lower in magnitude than the first terminal voltage; and
a first capacitor coupled between the first switching node and a first voltage;
wherein the first switch is controlled by a first control signal, and the second switch is controlled by a second control signal;
control logic configured to generate the first and second control signals to complementarily open and close the first switch and the second switch according to an operating frequency to generate an AC power signal from the DC power signal, the control logic generating the first and second control signals complimentarily opening and closing the first switch and the second switch with a first delay between generating the first control signal to open the first switch and generating the second control signal to close the second switch, and with a second delay between generating the second control signal to open the second switch and generating the first control signal to close the first switch; and
a resonant tank operably coupled to the first switching node of the bridge inverter, the resonant tank configured to receive the AC power signal and generate an electromagnetic field responsive thereto;
wherein each of the first and second delays is sufficient to prevent the first switch and the second switch being closed at the same time, a first switching node voltage increasing above the first terminal voltage during the second delay and decreasing below the second terminal voltage during the first delay;
wherein a capacitance of the first capacitor is sufficient to lengthen, by a factor of at least 7.5, a length of time for the first switching node voltage to reach the first terminal voltage during the second delay.

US Pat. No. 10,211,843

FAST-RESPONSE HYBRID LOCK DETECTOR

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:an analog circuit configured to (i) receive pulses generated in response to a comparison of a feedback signal and a reference signal, (ii) filter said pulses when a frequency of said feedback signal is close to a frequency of said reference signal and (iii) generate an enable signal in response to said filtered pulses; and
a digital circuit configured to generate an output signal representing a lock status between (i) said feedback signal and (ii) said reference signal, wherein (A) said lock status is determined (a) during a decision window based on a number of pulses of said reference signal and (b) when said enable signal is active and (B) said decision window is repeated periodically until said enable signal is not active.

US Pat. No. 10,198,200

COMMAND SEQUENCE RESPONSE IN A MEMORY DATA BUFFER

INTEGRATED DEVICE TECHNOL...

1. A method for responding to a command sequence, comprising the steps of:receiving a signal from a host carrying a plurality of commands in said command sequence;
detecting a start of a current command of said commands associated with a targeted access from said host to a memory system;
detecting a non-consecutive clock associated with said start of said current command; and
generating a control signal in an active state to indicate detection of said non-consecutive clock associated with said start of said current command.

US Pat. No. 10,200,050

AUTO-PHASE-SHIFTING AND DYNAMIC ON TIME CONTROL CURRENT BALANCING MULTI-PHASE CONSTANT ON TIME BUCK CONVERTER

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a first circuit configured to (a) generate an output signal with a regulated voltage and (b) maintain a constant switch frequency having a first on time and a first off time; and
a second circuit configured to (a) generate a shifted signal based on a phase delay with respect to said output signal and (b) maintain a shifted frequency having a second on time and a second off time, wherein (i) said second on time follows said first on time by a constant amount of said phase delay, (ii) said second on time is based on (a) said first on time and (b) transient conditions of a load, (iii) said apparatus implements an automatic phase shift adjustment, (iv) a current sensing comparison is performed within a decision window during said first off time and said second off time and (v) said current sensing comparison implements a cycle-by-cycle current comparison between a current of said output signal and a current of said shifted signal to (i) determine said second on time of said second circuit and (ii) perform a tuning operation to achieve inductor current balancing.

US Pat. No. 10,199,818

SYSTEM AND METHOD FOR WIRELESS POWER TRANSFER USING OVER-VOLTAGE PROTECTION

Integrated Device Technol...

1. An over-voltage protection system comprising:a switch coupled between a power source and a load;
a detection circuit configured to detect an onset of an over-voltage event at the load; and
a driver circuit coupled to the switch and the detection circuit, wherein the driver circuit includes:
a boost sub-circuit that provides a low-resistance path for opening the switch in a boost mode, the boost mode being triggered by the onset of the over-voltage event and having a predetermined duration; and
a steady state sub-circuit that provides a high-resistance path for holding the switch open during steady state operation when the boost mode ends,
wherein the driver circuit is a pull-up driver circuit coupled between a gate of the pass-gate transistor and a source of the pass-gate transistor, the source of the pass-gate transistor being coupled to the power source, the pull-up driver circuit further including a current mirror coupled between the gate and the source of the pass-gate transistor, the current mirror generating a current between the gate and the source of the pass-gate transistor that matches a current drawn by the boost sub-circuit and the steady state sub-circuit.

US Pat. No. 10,199,865

HIGH EFFICIENCY WIRELESS POWER SYSTEM

Integrated Device Technol...

1. A transmitter for wireless transfer, comprising:a rectifier that receives an AC voltage and provides a DC voltage;
a first capacitor that receives and smooths the DC voltage;
a regulator that receives the DC voltage and outputs a regulated DC voltage; and
a wireless transmitter that receives the regulated DC voltage and transmits wireless power, the wireless transmitter comprising:
a transmitting coil with a center tap, a first side, and a second side;
an inductor coupling the input voltage to the center tap;
a second capacitor coupled between the first and second side;
a first switch, coupled between the first side and ground;
a second switch, coupled between the second side and ground; and
a controller that is configured to operate the first and second switches in an adaptive self-resonance mode when the wireless transmitter is coupled to and transmits power to a wireless receiver that operates in the adaptive self-resonance mode;
wherein in the adaptive self-resonance mode, in each period of time of a plurality of successive periods of time, one of the first and second switches is on and the other one of the first and second switches is off, and a voltage across the other one of the first and second switches becomes non-zero in the period of time but returns to zero by the end of the period of time;
wherein the voltages across both of the first and second switches are zero at the end of each said period of time; and
wherein the first and second switches are both switched by the controller at the end of each said period of time, when the voltages across both of the first and second switches are zero.

US Pat. No. 10,325,637

FLEXIBLE POINT-TO-POINT MEMORY TOPOLOGY

INTEGRATED DEVICE TECHNOL...

1. A method of enabling a point-to-point memory topology comprising the steps of:when two memory modules are installed, enabling a first access mode where a plurality of memory devices on each memory module are accessed via a plurality of duplex data buffers on each memory module using a single selectable channel, and said plurality of duplex data buffers on each memory module use a different channel; and
when a single memory module is installed, installing a connection bridge board and enabling a second access mode where a first portion of said plurality of memory devices is accessed via a first portion of said duplex data buffers of said single memory module using a first channel and a second portion of said plurality of memory devices is accessed via a second portion of said duplex data buffers of said single memory module using a second channel.

US Pat. No. 10,311,926

COMPENSATION OF DETERMINISTIC CROSSTALK IN MEMORY SYSTEM

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a detector circuit configured to generate a control signal indicating a start of a plurality of strobe edges in a strobe signal; and
a receiver circuit configured to initialize an equalizer circuit in response to said control signal, wherein said equalizer circuit is configured to compensate a data signal for crosstalk coupled from said strobe edges to said data signal.

US Pat. No. 10,304,520

HIGH SIGNAL VOLTAGE TOLERANCE IN SINGLE-ENDED MEMORY INTERFACE

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a line-termination circuit configured to generate a data signal in response to an input signal, wherein (i) said input signal resides in a first voltage domain, (ii) said input signal is single-ended and (iii) said data signal is generated in said first voltage domain; and
a continuous-time linear equalizer circuit configured to generate an intermediate signal by equalizing said data signal relative to a reference voltage, wherein (i) said continuous-time linear equalizer circuit operates in a second voltage domain and (ii) said first voltage domain is higher than said second voltage domain.

US Pat. No. 10,264,261

ENTROPY ENCODING INITIALIZATION FOR A BLOCK DEPENDENT UPON AN UNENCODED BLOCK

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a memory configured to buffer a picture of a video signal, the picture comprising a plurality of blocks; and
an encoder configured to (i) receive the picture from the memory, (ii) generate a plurality of initial entropy states of the blocks by an initial encoding of the picture, (iii) store the initial entropy states in the memory, (iv) receive a first unencoded one of the blocks of the picture from the memory, wherein the first unencoded block was dependent on a second unencoded one of the blocks of the picture during the initial encoding, (v) receive the initial entropy states from the memory, (vi) initialize an entropy encoder circuit within the encoder in accordance with a first one of the initial entropy states from the initial encoding that corresponds to the first unencoded block and (vii) generate a portion of a bitstream by a final encoding of the first unencoded block based on the first initial entropy state prior to initializing the entropy encoder circuit to a second one of the initial entropy states to final encode the second unencoded block.

US Pat. No. 10,264,542

WIRELESSLY SYNCHRONIZED CLOCK NETWORKS

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a first independently clocked device comprising a first clock generator, a first frequency synthesizer, and a transmitter circuit, wherein (i) said first clock generator is configured to generate a first clock signal, (ii) said first clock signal provides internal clocking for said first independently clocked device, (iii) said first frequency synthesizer is configured to generate a synchronization signal in response to said first clock signal, and (iv) said transmitter circuit is configured to wirelessly transmit a broadcast signal communicating only said synchronization signal; and
a plurality of second independently clocked devices, each second independently clocked device comprising a respective receiver circuit, a respective second frequency synthesizer, and a respective second clock generator, wherein (i) said respective receiver circuit is configured to receive said broadcast signal transmitted by said transmitter circuit and present a recovered synchronization signal to an input of said respective second clock generator, (ii) said respective second clock generator is configured to generate a respective intermediate clock signal and synchronize said respective intermediate clock signal with said recovered synchronization signal, and (iii) said second frequency synthesizer is configured to generate a respective second clock signal that provides internal clocking for said second independently clocked device, wherein said respective second clock signals of said second independently clocked devices are synchronized to said first clock signal of said first independently clocked device in response to said recovered synchronization signal.

US Pat. No. 10,261,539

SEPARATE CLOCK SYNCHRONOUS ARCHITECTURE

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a plurality of independently clocked devices, each having a respective local clock generator, wherein each of said respective local clock generators comprises (i) a reference clock generator configured to generate a local reference clock signal in response to a control signal and (ii) a synchronization control circuit configured to generate said control signal in response to said local reference clock signal and a low frequency synchronization signal; and
a low frequency beacon, said low frequency beacon communicating said low frequency synchronization signal to each of said independently clocked devices, wherein said respective local clock generators of said plurality of independently clocked devices are synchronized using said low frequency synchronization signal.

US Pat. No. 10,171,268

ASYMMETRIC ON-STATE RESISTANCE DRIVER OPTIMIZED FOR MULTI-DROP DDR4

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a plurality of driver circuits configured to drive a read line in response to a memory signal and a reference voltage; and
a control registers block configuring said plurality of driver circuits to implement an asymmetric voltage swing of said read line about a voltage level that is half of said reference voltage.

US Pat. No. 10,404,216

RF AMPLIFIER LINEARITY ENHANCEMENT WITH DYNAMICALLY ADJUSTED VARIABLE LOAD

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:an amplifier having a predefined linear range; and
a shunt load circuit connected to an output, an input, or between gain stages of said amplifier, wherein the shunt load circuit sets a predefined load resistance level when a level of a signal presented at a node formed by interconnection of the shunt load circuit and the amplifier is below a predefined value and dynamically varies the load resistance level in response to said level of said signal presented at said node formed by interconnection of the shunt load circuit and the amplifier rising above the predefined value, extending linearity of the amplifier beyond the predefined range.

US Pat. No. 10,320,234

MULTIMODE WIRELESS POWER RECEIVERS AND RELATED METHODS

Integrated Device Technol...

1. A wireless power receiver, comprising:a resonant tank configured to generate an AC power signal responsive to an electromagnetic field transmitted by a wireless power transmitter;
a rectifier configured to receive the AC power signal and generate a DC output power signal; and
control logic configured to:
transmit a first message using a first encoding scheme to the wireless power transmitter;
in response to the wireless power receiver not receiving a first response to the first message, transmit a second message using a second encoding scheme to the wireless power transmitter;
receive a second response to the second message from the wireless power transmitter;
determine a type of the wireless power transmitter based on having received the second response to the second message using the second encoding scheme and using a wireless power transmitter type detector that is configured to determine the type of the wireless power transmitter responsive to an input of the rectifier and the DC output power signal;
adjust one or more control signals of the rectifier based on the determined type of the wireless power transmitter; and
cause the resonant tank to reconfigure and adjust a resonant frequency of the resonant tank to match an operating frequency of the wireless power transmitter based on the determined type of the wireless power transmitter.