US Pat. No. 9,362,240

ELECTRONIC DEVICE

Infineon Technologies Aus...

1. An electronic device, comprising:
a substrate;
a first semiconductor element comprising one or more first contact elements, the first semiconductor element arranged on the
substrate;

a second semiconductor element comprising one or more second contact elements, the second semiconductor element arranged on
the substrate; and

a bonding clip electrically connecting one or more of the first and second contact elements on the first and second semiconductor
elements to the substrate,

wherein the first semiconductor element and the second semiconductor element are arranged on opposite sides of the substrate,
wherein the substrate comprises a leadframe or a direct bonded copper substrate.

US Pat. No. 9,263,440

POWER TRANSISTOR ARRANGEMENT AND PACKAGE HAVING THE SAME

INFINEON TECHNOLOGIES AUS...

1. A power transistor arrangement, comprising:
a carrier comprising at least a main region and a first terminal region and a second terminal region, the main region, the
first terminal region and the second terminal region being electrically isolated from each other;

a first power transistor having a control electrode and a first power electrode and a second power electrode, the first power
transistor being arranged over the main region of the carrier such that the first power electrode of the first power transistor
is facing towards the main region of the carrier and is electrically coupled to the main region of the carrier;

a second power transistor having a control electrode and a first power electrode and a second power electrode,
the second power transistor being arranged over the first terminal region and the second terminal region such that the control
electrode of the second power transistor and the first power electrode of the second power transistor are facing towards the
terminal regions of the carrier,

wherein the control electrode of the second power transistor is electrically coupled to the first terminal region of the carrier,
and wherein the first power electrode of the second power transistor is electrically coupled to the second terminal region
of the carrier;

wherein the control electrode of the first power transistor is electrically coupled to one of the first terminal region and
the second terminal region; and

wherein the second power electrode of the first power transistor and the second power electrode of the second power transistor
are electrically coupled with each other.

US Pat. No. 9,467,061

SYSTEM AND METHOD FOR DRIVING A TRANSISTOR

Infineon Technologies Aus...

1. A circuit for driving a control terminal of a switching transistor, the circuit comprising:
a driver comprising an output configured to be coupled to the control terminal of the switching transistor, a first power
supply terminal configured to be coupled to a first terminal of a floating power supply, a second power supply terminal configured
to be coupled to a second terminal of the floating power supply, and a switching input terminal configured to receive a switching
signal; and

a bias circuit having an output terminal configured to be coupled to a common-mode control terminal of the floating power
supply, wherein the bias circuit is configured to provide a time dependent common-mode voltage to the floating power supply.

US Pat. No. 9,065,275

DRIVING CIRCUIT FOR AN ELECTRIC MOTOR

INFINEON TECHNOLOGIES AUS...

1. A circuit arrangement, comprising:
a bridge circuit comprising at least two switches connected in series;
a bridge node arranged between the at least two switches, wherein the bridge node is configured to provide a phase voltage;
an electric motor comprising at least one phase winding coupled with the bridge node;
a decoupling switch connected between the bridge node and the electric motor;
a controller coupled with the decoupling switch and with the at least two switches, wherein in an error case the controller
is configured to switch off the at least two switches, to determine whether a predefined condition is satisfied, and to one
of

switching off the decoupling switch, wherein the switching off of the decoupling switch is delayed with respect to the switching
off of the at least two switches in case the predefined condition is not satisfied; and

switching off the at least two switches and the decoupling switch simultaneously, in case the predefined condition is satisfied;
wherein the controller is configured to determine that the predefined condition is satisfied when the decoupling switch may
be switched off without suffering permanent damage from the current applied to it at the time when the at least two switches
are switched off.

US Pat. No. 9,147,631

SEMICONDUCTOR POWER DEVICE HAVING A HEAT SINK

Infineon Technologies Aus...

1. A semiconductor device, comprising:
an electrically conducting carrier having a mounting surface;
a metal block having a first surface facing the carrier and a second surface facing away from the electrically conducting
carrier;

a semiconductor power chip disposed over the second surface of the metal block, the semiconductor power chip having a first
surface which faces the second surface of the metal block and a second surface opposite the first surface; and

a contact clip electrically and mechanically connected to a load electrode of the semiconductor power chip, the load electrode
being arranged at the second surface of the power semiconductor chip.

US Pat. No. 9,420,731

ELECTRONIC POWER DEVICE AND METHOD OF FABRICATING AN ELECTRONIC POWER DEVICE

Infineon Technologies Aus...

1. An electronic device, comprising:
a power module comprising a first main surface and a second main surface opposite to the first main surface, wherein at least
a portion of the first main surface is a heat dissipating surface without electrical power terminal functionality;

a first porous metal layer arranged on the portion of the first main surface;
a chip carrier; and
a power semiconductor chip mounted on the chip carrier, wherein the chip carrier is exposed at the portion of the first main
surface of the power module,

wherein the chip carrier comprises a metal bonded ceramic substrate or a leadframe.

US Pat. No. 9,099,441

POWER TRANSISTOR ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME

INFINEON TECHNOLOGIES AUS...

15. A package, comprising:
a power transistor arrangement, comprising:
a carrier;
a first power transistor comprising a first chip having a control electrode and a first power electrode and a second power
electrode, wherein the control electrode and the second electrode are at a first side of the first chip and the first electrode
is at a second side of the first chip that is opposite to the first side;

a second power transistor comprising a second chip having a control electrode and a first power electrode and a second power
electrode, wherein the control electrode and the second electrode are at a first side of the second chip and the first electrode
is at a second side of the second chip that is opposite to the first side;

wherein the first power transistor and the second power transistor are arranged next to each other on the carrier such that
the control electrode of the first power transistor and the control electrode of the second power transistor are facing towards
the carrier;

wherein the first power electrode of the first power transistor and the first power electrode of the second power transistor
are facing away from the carrier; and

wherein the first power electrode of the first power transistor and the first power electrode of the second power transistor
are electrically coupled with each other by means of an electrically conductive coupling structure;

package terminals configured to receive electrical signals from outside the package;
wherein the electrically conductive coupling structure is electrically isolated from the package terminals.

US Pat. No. 9,263,425

SEMICONDUCTOR DEVICE INCLUDING MULTIPLE SEMICONDUCTOR CHIPS AND A LAMINATE

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a laminate;
a first power semiconductor chip at least partly embedded in the laminate;
a second power semiconductor chip at least partly embedded in the laminate;
a control semiconductor chip configured to control at least one of the first power semiconductor chip and the second power
semiconductor chip, the control semiconductor chip mounted on a first main surface of the laminate; and

a first electrical contact arranged on the first main surface of the laminate, wherein the control semiconductor chip is electrically
coupled to the first electrical contact.

US Pat. No. 9,479,067

SYSTEM AND METHOD FOR A SWITCHED-MODE POWER SUPPLY

Infineon Technologies Aus...

1. A method of operating a switched-mode power supply, the method comprising:
detecting a voltage decrease in a secondary winding of a transformer comprising detecting a first voltage transient using
a sensor capacitively coupled to a node between the secondary winding of the transformer and a secondary switch coupled to
the secondary winding; and

turning on the secondary switch based on when the first voltage transient is detected;
detecting a voltage increase in the secondary winding comprising detecting a second voltage transient using the sensor, and
detecting a current transient through a clamping circuit coupled to an input of the sensor; and

inhibiting the secondary switch when the second voltage transient and the current transient are detected.

US Pat. No. 9,171,841

FIELD PLATE TRENCH TRANSISTOR AND METHOD FOR PRODUCING IT

Infineon Technologies Aus...

1. A semiconductor transistor including a field plate trench transistor comprising:
a trench structure;
a field electrode structure embedded in the trench structure, the field electrode structure being electrically insulated from
a semiconductor body by an insulation structure; and

a voltage divider between a source terminal and a drain terminal,
the voltage divider including a series circuit comprising at least one resistor and at least one diode, the series circuit
being connected between the source and drain terminals, wherein

the field electrode structure is electrically connected to the voltage divider, and the at least one diode is a body substrate
diode.

US Pat. No. 9,450,494

INDUCTIVE COMPENSATION BASED CONTROL OF SYNCHRONOUS RECTIFICATION SWITCH

Infineon Technologies Aus...

1. An electronic device, comprising:
a synchronous rectification circuit comprising an actively controlled switching element through which resonant current flows
during operation, the actively controlled switching element being disposed in a package which adds stray inductance to a main
current path of the synchronous rectification circuit; and

a fixed inductor magnetically coupled to the stray inductance or an additional inductance in series with the stray inductance
so that the fixed inductor is not in the main current path of the synchronous rectification circuit and change in current
through the inductance to which the fixed inductor is magnetically coupled induces a reference voltage at the fixed inductor
which is in phase with a zero crossing point of the resonant current at different switching frequencies of the actively controlled
switching element.

US Pat. No. 9,411,355

CONFIGURABLE SLOPE TEMPERATURE SENSOR

Infineon Technologies Aus...

1. An apparatus, comprising:
a proportional-to-absolute-temperature (PTAT) current generator coupled to a strategic node and arranged to generate a PTAT
current;

a shifting resistance coupled to the strategic node and arranged to pass a shifting current, the shifting current representative
of a desired translation of a voltage response; and

an amplifying resistance coupled to the strategic node and arranged to pass an amplifying current comprising the shifting
current subtracted from the PTAT current, the amplifying resistance forming the voltage response via the amplifying current,
the voltage response having a determined slope and/or a determined translation, based on the amplifying current.

US Pat. No. 9,373,566

HIGH POWER ELECTRONIC COMPONENT WITH MULTIPLE LEADFRAMES

Infineon Technologies Aus...

1. An electronic component, comprising:
a semiconductor die having a first surface, the first surface comprising a first current electrode and a control electrode;
a die pad comprising a first surface;
a plurality of leads, and
a gull-wing shaped conductive element coupled to a first lead of the plurality of leads by a spot weld connection,
wherein the first current electrode is mounted on the die pad and the gull-wing shaped conductive element is coupled between
the control electrode and the first lead,

wherein the gull-wing shaped conductive element comprises a first end having a first surface that is substantially coplanar
with the first surface of the die pad,

wherein the semiconductor die extends between the die pad and the first end of the gull-wing shaped conductive element,
wherein the gull-wing shaped conductive element is provided as a separate piece from the first lead of the plurality of leads,
wherein the die pad has an L-shaped configuration in plan view.

US Pat. No. 9,490,244

INTEGRATED CIRCUIT COMPRISING A CLAMPING STRUCTURE AND METHOD OF ADJUSTING A THRESHOLD VOLTAGE OF A CLAMPING TRANSISTOR

Infineon Technologies Aus...

1. An integrated circuit, comprising:
a load transistor including first and second load terminals and a load control terminal;
a clamping structure comprising a clamping transistor, the clamping transistor including first and second clamping transistor
load terminals and a control gate terminal, wherein the clamping transistor is electrically coupled between the load control
terminal and the first load terminal and a clamping voltage of the load transistor is determined by a threshold voltage Vth
of the clamping transistor, and wherein the clamping transistor comprises a control gate electrode electrically connected
to the control gate terminal and a charge storage structure between the control gate electrode and a semiconductor body.

US Pat. No. 9,338,848

MULTI-FUNCTION PIN FOR LIGHT EMITTING DIODE (LED) DRIVER

Infineon Technologies Aus...

1. A light emitting diode (LED) driver comprising:
an input pin that receives a current flowing through one or more LEDs into the LED driver; and
a controller configured to determine whether a voltage at an external node that is external to the LED driver is beginning
to oscillate based on a voltage at the input pin that receives the current in the LED driver, and determine whether the current
flowing through the one or more LEDs has reached an amplitude of zero based on the voltage at the same input pin.

US Pat. No. 9,084,382

METHOD OF EMBEDDING AN ELECTRONIC COMPONENT INTO AN APERTURE OF A SUBSTRATE

Infineon Technologies Aus...

1. A method, comprising:
depositing a first set of one or more forms onto a surface of a first conductive layer;
depositing a first layer of dielectric material onto the first conductive layer, around the first set of one or more forms;
depositing a spacer layer having one or more apertures onto the dielectric material and the one or more forms; and
placing one or more electrical components into the one or more apertures in the spacer layer, the one or more electrical components
arranged to be electrically coupled to a portion of the first conductive layer via one or more apertures formed in the first
layer of dielectric material, based on the first set of one or more forms.

US Pat. No. 9,324,823

SEMICONDUCTOR DEVICE HAVING A TAPERED GATE STRUCTURE AND METHOD

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a semiconductor body having a first surface;
a first trench formed in the semiconductor body, the first trench comprising first and second sidewalls extending from the
first surface in a vertical direction and a first trench bottom extending between the first and second sidewalls in a first
lateral direction;

a field dielectric filling the first trench; and
a second trench formed within the first trench in the field dielectric comprising inner and outer sidewalls,
wherein first and second sidewalls of the first trench and the inner and outer sidewalls of the second trench extend along
the semiconductor body in a second lateral direction that is perpendicular to the first lateral direction and perpendicular
to the vertical direction, and

wherein the second trench comprises a widened portion adjacent to a narrow portion in the second lateral direction, wherein,
in the widened portion, the inner and outer sidewalls extend the parallel to the first sidewall in the second lateral direction,
and wherein, in the narrow portion, one of the inner and outer sidewalls is non-perpendicular and non-parallel to the first
sidewall in the second lateral direction.

US Pat. No. 9,324,817

METHOD FOR FORMING A TRANSISTOR DEVICE HAVING A FIELD ELECTRODE

Infineon Technologies Aus...

1. A method for forming a transistor device, the method comprising
forming a field electrode arrangement by forming a trench in a first surface of a semiconductor body, forming a protection
layer on sidewalls of the trench in an upper trench section, forming a dielectric layer on a bottom of the trench and on sidewall
sections uncovered by the protection layer, and forming a field electrode at least on the dielectric layer;

forming a gate electrode and a gate electrode dielectric horizontally spaced apart from the field electrode arrangement with
respect to the first surface;

forming a body region adjacent the gate electrode and dielectrically insulated from the gate electrode by the gate dielectric;
and

forming a source region in the body region.

US Pat. No. 9,196,560

SEMICONDUCTOR DEVICE HAVING A LOCALLY REINFORCED METALLIZATION STRUCTURE AND METHOD FOR MANUFACTURING THEREOF

Infineon Technologies Aus...

1. A method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate comprising an active area formed in the semiconductor substrate and an edge termination
area formed in the semiconductor substrate and laterally surrounding the active area;

forming a first metal layer structure on a first side of the semiconductor substrate, wherein the first metal layer structure
comprises at least a lower metal layer extending from the active area to the edge termination area and at least an upper metal
layer comprising at least a first metal portion in the active area and at least a second metal portion in the edge termination
area;

forming a plating mask on the first metal layer structure to cover the second metal portion while leaving at least a portion
of the first metal portion uncovered;

plating a second metal layer structure at least on and in ohmic contact with the first metal portion, wherein the plating
mask covers the second metal portion during plating of the second metal layer structure; and

etching the lower metal layer of the first metal layer structure using at least the upper metal layer as etching mask after
plating the second metal layer structure;

wherein the second metal layer structure, the first metal portion of the upper metal layer and a portion of the lower metal
layer form together a common metallization structure in the active area of the semiconductor device.

US Pat. No. 9,368,617

SUPERJUNCTION DEVICE AND SEMICONDUCTOR STRUCTURE COMPRISING THE SAME

Infineon Technologies Aus...

2. A superjunction device, which comprises:
a drain region of a first conduction type;
a body region of a second conduction type;
a drift region located between said body region and said drain region, the drift region comprises first regions of a first
conduction type and second regions of a second conduction type arranged alternately along a direction being perpendicular
to the direction from the body region to the drain region;

a plurality of trench gate structures, each of them comprising a trench extending into said drift region from an upper surface
of said body region and a gate electrode in said trench surrounded by a first dielectric layer filling said trench, thereby
defining a vertical interface between the first dielectric layer and the body region having an interface length,

wherein a summation of the interface lengths defined by each of the plurality of trench gate structures comprises a total
interface length of the superjunction device; and

a source region of a first conduction type embedded into said body region;
wherein there is no source region along at least 10% of the total interface length between the first dielectric layer and
the body region,

wherein there is no source region on both sides of at least 10% of said plurality of trench gate structures.

US Pat. No. 9,293,998

BUCK-FLYBACK CONVERTER

Infineon Technologies Aus...

1. A two-transistor flyback converter, comprising:
a transformer having a primary side and a secondary side;
a first transistor connected between an input voltage source and a first terminal of the primary side;
a second transistor connected between ground and a second terminal of the primary side;
a diode directly connected between the first terminal of the primary side and ground; and
wherein the first transistor and the diode are operated as a buck converter,
wherein the second transistor is operated as a flyback converter,
wherein the first and second transistors are switched on and off simultaneously and with no current return from the primary
side to the input voltage source when the input voltage source is less than a reflected voltage from the secondary side,

wherein the reflected voltage is set such that a summation of the reflected voltage and a voltage spike caused by leakage
inductance of the transformer is smaller than the input voltage.

US Pat. No. 9,361,179

RELIABLE DATA TRANSMISSION WITH REDUCED BIT ERROR RATE

Infineon Technologies Aus...

1. A system comprising:
a recipient configured to receive data frames from at least one transmission line, wherein the recipient is configured to
determine a recipient check sum based on a plurality of corresponding data frames that are received from the at least one
transmission line;

a check sum comparing unit configured to receive and to compare the recipient check sum with a corresponding sender check
sum determined by a sender transmitting the data frames received at the recipient and;

a switch coupled to an output of the recipient and coupled to be activated upon receipt of a signal; and
a safety circuit coupled to the check sum comparing unit, wherein the safety circuit is configured to transmit a deactivation
signal configured to prevent the switch from conducting a ON current if the check sums compared are not equal.

US Pat. No. 9,455,631

CURRENT ESTIMATION FOR A CONVERTER

Infineon Technologies Aus...

1. A current estimation circuitry for a converter, comprising:
an integrator for integrating a voltage across an inductor of the converter,
a current sense unit for obtaining a signal that is associated with the current flowing through at least one of electronic
switches of the converter,

a control unit for adjusting at least two parameters of the integrator based on comparing an output of the integrator with
the signal provided by the current sense unit.

US Pat. No. 9,048,303

GROUP III-NITRIDE-BASED ENHANCEMENT MODE TRANSISTOR

Infineon Technologies Aus...

1. A Group III-nitride-based enhancement mode transistor, comprising a heterojunction fin structure, wherein side faces and
a top face of the heterojunction fin structure are covered by a p-type Group III-nitride layer.

US Pat. No. 9,219,144

SEMICONDUCTOR DEVICE INCLUDING A TRENCH IN A SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a semiconductor substrate;
a first trench extending into or through the semiconductor substrate from a first side,
a semiconductor layer adjoining the semiconductor substrate at the first side, wherein the semiconductor layer caps the first
trench at the first side; and

a contact at a second side of the semiconductor substrate opposite to the first side,
wherein the semiconductor substrate includes p-type dopants and n-type dopants, wherein a concentration of the p-type dopants
is lower than the concentration of the n-type dopants, and wherein a profile of concentration of the n-type dopants decreases
from a sidewall of the first trench into the semiconductor substrate along a lateral direction parallel to the first side.

US Pat. No. 9,142,987

BATTERY MODULE WITH CONVERTER AND DECOUPLING SWITCH

INFINEON TECHNOLOGIES AUS...

18. An arrangement comprising:
a first battery module comprising:
a first connection;
a second connection;
an energy store having a positive connection and a negative connection, wherein the positive connection of the energy store
is connected to the first connection and the negative connection of the energy store is connected to the second connection;

a first compensation connection;
a second compensation connection;
a boost converter having a first converter output and a second converter output, wherein the first converter output of the
boost converter is coupled to the first compensation connection and the second converter output of the boost converter is
coupled to the second compensation connection, wherein the boost converter is configured to draw energy from the energy store
and to provide the energy to the first and second converter outputs of the boost converter in the form of current; and

a decoupling switch having a first connection directly connected to the first compensation connection and a second connection
directly connected to the second compensation connection; and

a second battery module coupled in series with the first battery module, the second battery module comprising:
a third connection;
a fourth connection;
a second energy store having a positive connection and a negative connection, wherein the positive connection of the second
energy store is connected to the third connection and the negative connection of the second energy store is connected to the
fourth connection;

a third compensation connection;
a fourth compensation connection;
a second boost converter having a first converter output and a second converter output, wherein the first converter output
of the second boost converter is coupled to the third compensation connection and the second converter output of the second
boost converter is coupled to the fourth compensation connection, wherein the second boost converter is configured to draw
energy from the second energy store and to provide the energy to the second boost converter outputs in the form of current;
and

a second decoupling switch having a first connection directly connected to the third compensation connection and a second
connection directly connected to the fourth compensation connection, wherein

the first connection of the first battery module is directly connected to the fourth connection of the second battery module,
and

the first compensation connection of the first battery module and the first connection of the decoupling switch are directly
connected to the fourth compensation connection of the second battery module and the second connection of the second decoupling
switch.

US Pat. No. 9,642,289

POWER SUPPLY AND METHOD

Infineon Technologies Aus...

1. A power supply comprising:
a plurality of electronic components comprising one or more of a rectifier and a switching transistor;
an input port configured to receive electrical energy from a power source; and
a circuit board comprising a cavity, wherein at least one of the rectifier and the switching transistor is embedded in the
cavity, and wherein the cavity is arranged proximal to the input port such that least a portion of thermal energy generated
by one or more of the rectifier and the switching transistor is dissipated from the power supply by way of the input port.

US Pat. No. 9,572,207

DIMMING RANGE EXTENSION

Infineon Technologies Aus...

1. An electronic circuit, comprising:
a transformer of a drive circuit;
a detection portion of a bleeder circuit, the detection portion connected to a secondary winding of the transformer and configured
to detect an average voltage of the secondary winding; and

a current sink portion of the bleeder circuit, the current sink portion connected to the detection portion and configured
to reduce a drive current associated with the drive circuit, based on the average voltage of the secondary winding detected
by the detection portion, the drive current arranged to energize a load.

US Pat. No. 9,281,413

ENHANCEMENT MODE DEVICE

Infineon Technologies Aus...

1. An enhancement mode device, comprising:
a floating gate structure, the floating gate structure comprising:
a first bottom dielectric layer;
a second bottom dielectric layer on the first bottom dielectric layer;
a conductive floating gate on the second bottom dielectric layer;
a Group III-nitride-based channel layer; and
a Group III-nitride-based barrier layer arranged on the Group III-nitride-based channel layer,
wherein a heterojunction is formed between the Group III-nitride-based barrier layer and the Group III-nitride-based channel
layer.

US Pat. No. 9,083,243

PROTECTION CIRCUIT FOR PROTECTING A HALF-BRIDGE CIRCUIT

INFINEON TECHNOLOGIES AUS...

1. A method, comprising:
periodically alternately switching first and second switches for a switched-on duration; and
counting periodically recurring intervals of time during which a voltage across a resistor exceeds a threshold value at least
once.

US Pat. No. 9,313,052

METHOD AND APPARATUS FOR SIGNAL TRANSMISSION

Infineon Technologies Aus...

1. A signal transmission arrangement comprising:
a receiver circuit configured to be coupled to output terminals of a first signal transmission channel, and configured to
be coupled to output terminals of a second signal transmission channel, wherein the first signal transmission channel is configured
to be coupled to a transmitter and the second signal transmission channel is configured to be open-ended or terminated by
a passive component at an input terminal to the second signal transmission channel, wherein

the receiver circuit is configured to detect information signal pulses and interference signal pulses on the first signal
transmission channel and to provide a receiver output signal based only on the information signal pulses from the first signal
transmission channel,

the receiver circuit is configured to detect interference signal pulses on the second signal transmission channel and also
to ignore corresponding detected interference signal pulses on the first signal transmission channel occurring within a given
time window before or after an interference signal pulse on the second signal transmission signal has been detected.

US Pat. No. 9,275,862

COMPENSATION DEVICES

Infineon Technologies Aus...

1. A method comprising:
forming an n/p-codoped calibration layer on a substrate; and
adjusting supply of n-dopant and p-dopant based on a net doping of the n/p-codoped calibration layer.

US Pat. No. 9,257,549

SEMICONDUCTOR FIELD EFFECT POWER SWITCHING DEVICE

Infineon Technologies Aus...

1. A semiconductor device comprising:
a semiconductor body comprising a first surface, a first semiconductor region of a first conductivity type and a second semiconductor
region of a second conductivity type, the first semiconductor region and the second semiconductor region forming a pn-junction;

a source metallization arranged on the first surface; and
a trench extending from the first surface into the semiconductor body and comprising, in a horizontal plane substantially
parallel to the first surface, a first trench portion and a second trench portion,

the first trench portion comprising a sidewall adjacent to the second semiconductor region, an insulating layer arranged on
the side wall, the insulating layer adjoining the first semiconductor region and the second semiconductor region, and a gate
electrode connected to the source metallization; the second trench portion comprising a conductive plug which is connected
to the source metallization and to the second semiconductor region.

US Pat. No. 9,252,263

MULTIPLE SEMICONDUCTOR DEVICE TRENCHES PER CELL PITCH

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a plurality of field plate trenches formed in a semiconductor substrate;
a plurality of gate trenches formed in the semiconductor substrate and spaced apart from the field plate trenches; and
a plurality of device cells having a cell pitch defined by a distance from one side of a field plate trench to the same side
of an adjacent field plate trench, each device cell comprising a first doped region of a first conductivity type and a second
doped region of a second conductivity type adjacent the first doped region in a part of the semiconductor substrate disposed
between the adjacent field plate trenches that define the cell pitch,

wherein at least some of the device cells have more than one gate trench per cell pitch,
wherein at least some of the device cells that have more than one gate trench per cell pitch include only a single type of
gate trench that comprises a gate conductor disposed in a gate trench.

US Pat. No. 9,318,549

SEMICONDUCTOR DEVICE WITH A SUPER JUNCTION STRUCTURE HAVING A VERTICAL IMPURITY DISTRIBUTION

Infineon Technologies Aus...

1. A super junction semiconductor device comprising:
an impurity layer of a first conductivity type formed in a semiconductor portion having a first surface and a second surface
parallel to the first surface;

a super junction structure between the first surface and the impurity layer, the super junction structure comprising first
columns of the first conductivity type and second columns of a second, opposite conductivity, wherein a sign of a compensation
rate between the first and second columns changes along a vertical extension of the columns perpendicular to the first surface;

a body zone of the second conductivity type formed between the first surface and one of the second columns at least partially
in the vertical projection of the second columns; and

a field extension zone of the second conductivity type electrically connected to the body zone and arranged in the vertical
projection of one of the first or the second columns, wherein an area impurity density in the field extension zone is between
1×1012 and 5×1012 cm?2, and a mean net impurity concentration in the field extension zone is higher than in a directly adjoining section of the
second columns and lower than in the body zone.

US Pat. No. 9,093,836

METHOD FOR CONTROLLING A TRANSISTOR AND CONTROL CIRCUIT

Infineon Technologies Aus...

1. A method for pulsed control of a transistor which has a control terminal and a load path that is connected in series with
a load, the method comprising:
controlling the transistor with a control pulse of a first type, that has a first control level at least for a first time
duration before a control pulse of a second type that has a second control level, the second control level being higher than
the first control level;

evaluating a voltage across the load path of the transistor; and
terminating the pulsed control when the voltage across the load path exceeds a predefined threshold value.

US Pat. No. 9,391,604

METHODS FOR MONITORING FUNCTIONALITY OF A SWITCH AND DRIVER UNITS FOR SWITCHES

Infineon Technologies Aus...

1. A gate driver unit comprising:
an input stage;
an output stage;
a read/write interface; and
a monitoring stage;
wherein the input stage is configured to receive digital control signals from an external system controller and forward the
digital control signals to the output stage and the monitoring stage;

wherein the read/write interface is configured to receive configuration data and forward the configuration data to the monitoring
stage;

wherein the monitoring stage is configured to capture and evaluate signals of a power switch connected to the gate driver
unit and synchronize the evaluation of the signals of the power switch to the digital control signals;

and
wherein the evaluation of the signals and the synchronization of the evaluation are based on the configuration data, and the
configuration data comprise a value specifying a time delay from a transition time of at least one digital control signal
to a time at which the monitoring stage captures and evaluates the signals of the power switch.

US Pat. No. 9,123,791

SEMICONDUCTOR DEVICE AND METHOD

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a first compound semiconductor material comprising a first doping concentration;
a second compound semiconductor material on the first compound semiconductor material, the second compound semiconductor material
comprising a different material than the first compound semiconductor material;

a control electrode;
at least one buried semiconductor material region comprising a second doping concentration different from the first doping
concentration, wherein the at least one buried semiconductor material region is disposed in the first compound semiconductor
material in a region other than a region of the first compound semiconductor material being covered by the control electrode,
and

a first current electrode and a second current electrode, wherein in a lateral direction, the at least one buried semiconductor
material region is arranged between the first current electrode and the control electrode.

US Pat. No. 9,064,887

FIELD-EFFECT SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Infineon Technologies Aus...

1. A field-effect semiconductor device, comprising:
a semiconductor body of a first band-gap material and having a main surface, the semiconductor body comprising in a cross-section
which is substantially vertical to the main surface:

a drift region of a first conductivity type;
a first channel region of the first conductivity type and adjoining the drift region;
a first gate region forming a first pn-junction with the first channel region;
a first body region arranged below the first gate region and forming a second pn-junction with the first channel region such
that the first channel region is arranged between the first pn-junction and the second pn-junction; and

a first source region of the first conductivity type, having a higher maximum doping concentration than the first channel
region and adjoining the first channel region; and

an anode region of a second band-gap material having a lower band-gap than the first band-gap material, the anode region being
of a second conductivity type and forming a heterojunction with the drift region, wherein the heterojunction and the first
source region do not overlap when viewed from above.

US Pat. No. 9,385,599

CONVERTER CIRCUIT AND METHOD FOR CONVERTING AN INPUT VOLTAGE TO AN OUTPUT VOLTAGE USING A WHITE NOISE GENERATOR

INFINEON TECHNOLOGIES AUS...

1. A converter circuit, comprising:
a switch circuit configured to provide an output voltage to a load;
a control circuit comprising an analogue control portion and a digital control portion;
a noise generator configured to generate white noise using a sigma delta converter having more than one feedback loop; and
wherein at least one zero of the sigma delta converter is near to the load resonance frequency;

wherein the noise generator is configured to supply the generated white noise to the digital control portion of the control
circuit; and

wherein the control circuit is configured to control the switch circuit based on the white noise.

US Pat. No. 9,370,069

MULTI-FUNCTION PIN FOR LIGHT EMITTING DIODE (LED) DRIVER

Infineon Technologies Aus...

1. A light emitting diode (LED) driver comprising:
an input pin that receives a current flowing through one or more LEDs into the LED driver; and
a controller configured to determine whether a voltage at an external node that is external to the LED driver is beginning
to oscillate based on a voltage at the input pin that receives the current in the LED driver, and determine whether the current
flowing through the one or more LEDs has reached an amplitude of zero based on the voltage at the same input pin.

US Pat. No. 9,300,215

DIMMABLE LED POWER SUPPLY WITH POWER FACTOR CONTROL

Infineon Technologies Aus...

1. A power supply circuit comprising:
a control unit configured to be coupled to a semiconductor switch connected to a primary winding of a transformer, wherein
the control unit is configured to

control a switching operation of the semiconductor switch dependent on a rectified alternating line voltage and a current
sense signal dependent on a current of the primary winding of the transformer,

compare the current sense signal with a time-varying reference signal representing the rectified alternating line voltage,
determine a switch-off instant of the semiconductor switch dependent on the comparing the current sense signal with the time-varying
reference signal, and

drive the semiconductor switch such that a short-term average of the current of the primary winding follows the rectified
alternating line voltage to provide a power factor correction.

US Pat. No. 9,171,728

METHOD FOR FORMING A POWER SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A method for forming a semiconductor device, the method comprising:
providing a semiconductor body which comprises a main surface and a first n-type semiconductor region;
forming a trench which extends from the main surface into the first n-type semiconductor region; and
forming a dielectric layer comprising fixed negative charges on a surface of the trench, comprising performing at least one
atomic layer deposition using an organometallic precursor.

US Pat. No. 9,236,800

SYSTEM FOR BALANCING CURRENT SUPPLIED TO A LOAD

Infineon Technologies Aus...

1. A system for balancing current supplied by a plurality of regulators coupled to a load, the system comprising:
a current sensor operable to measure an average load current supplied by each regulator;
a current share circuit operable to determine an overall average current to be shared by the plurality of regulators, and
compare each average load current with the overall average current to be shared by the plurality of regulators; and

a digital compensator operable to adjust an output current of one or more of the plurality of regulators so that the plurality
of regulators supply the same current to the load.

US Pat. No. 9,391,149

SEMICONDUCTOR DEVICE WITH SELF-CHARGING FIELD ELECTRODES

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a drift region of a first doping type;
a junction between the drift region and a device region;
a plurality of field electrode structures spaced apart from each other in a current flow direction of the semiconductor device
in the drift region, each of the plurality of field electrode structures comprising:

a field electrode; and
a coupling region of a second doping type complementary to the first doping type, the coupling region being electrically coupled
to the device region and coupled to the field electrode of each of the plurality of field electrode structures,

wherein each of the plurality of field electrode structures further comprises:
a field electrode dielectric adjoining the field electrode, arranged between the field electrode and the drift region, and
having an opening; and

at least one of a field stop region and a generation region.

US Pat. No. 9,312,334

SEMICONDUCTOR COMPONENT

Infineon Technologies Aus...

1. A semiconductor component comprising:
a semiconductor body having a cell region and an edge region, which semiconductor body, at least in the cell region, contains
a drift zone of a first conduction type in a front side of the semiconductor body and is provided with at least one zone of
the first conduction type and at least one zone of a second conduction type in a rear side; and

wherein a laterally delimited further zone of the second conduction type is arranged directly in front of the at least one
zone of the first conduction type.

US Pat. No. 9,356,130

HEMT WITH COMPENSATION STRUCTURE

Infineon Technologies Aus...

1. A high electron mobility transistor, comprising:
a source, a gate and a drain;
a first III-V semiconductor region having a first conductive channel controllable by the gate between the source and drain;
a second III-V semiconductor region below the first III-V semiconductor region, the second III-V semiconductor region having
a second conductive channel connected to the source or drain and not controllable by the gate; and

a compensation structure interposed between the first and second III-V semiconductor regions so that the first and second
III-V semiconductor regions are spaced apart from one another by the compensation structure, the compensation structure having
a different band gap than the first and second III-V semiconductor regions.

US Pat. No. 9,231,100

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A semiconductor device, being at least partially formed in a semiconductor substrate, the semiconductor substrate comprising
a first and a second main surface, the first and the second main surfaces being opposed to each other, the semiconductor device
comprising a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion,
the cell field portion comprising at least a transistor, the contact area comprising:
a connection substrate portion insulated from other substrate portions and comprising a part of the semiconductor substrate,
the connection substrate portion not being electrically coupled to a component of the cell field portion by means of the semiconductor
substrate;

an electrode adjacent to the second main surface and in contact with the connection substrate portion; and
a metal layer disposed over the first main surface, the connection substrate portion being electrically coupled to the metal
layer to form a contact between the electrode and the metal layer.

US Pat. No. 9,281,392

CHARGE COMPENSATION STRUCTURE AND MANUFACTURING THEREFOR

Infineon Technologies Aus...

1. A charge-compensation semiconductor device, comprising:
a rated breakdown voltage;
a semiconductor body comprising a first surface, an edge delimiting the semiconductor body in a horizontal direction substantially
parallel to the first surface, an active area, and a peripheral area arranged between the active area and the edge;

a source metallization arranged on the first surface; and
a drain metallization arranged opposite to the source metallization,in a vertical cross-section substantially orthogonal to the first surface the semiconductor body further comprising:
an intrinsic semiconductor region arranged in the peripheral area; and
a plurality of first pillar regions alternating with second pillar regions in the active area and the peripheral area, the
first pillar regions having a higher doping concentration than the intrinsic semiconductor region, the first pillar regions
being in Ohmic contact with the drain metallization, the second pillar regions of the active area being in Ohmic contact with
the source metallization via respective body regions having a higher doping concentration than the second pillar regions,
at least a majority of the second pillar regions of the peripheral area adjoining a connecting region which is of the same
conductivity type as the second pillar regions and has a lower doping concentration than an adjoining outermost of the body
regions, between adjacent first pillar regions and second pillar regions a respective pn-junction being formed, at least one
of an outermost of the first pillar regions and an outermost of the second pillar regions forming an interface with the intrinsic
semiconductor region at a horizontal position where a voltage at the first surface is at least about a fifth of the rated
breakdown voltage when the rated breakdown voltage is applied between the source metallization and the drain metallization.

US Pat. No. 9,263,369

CHIP ARRANGEMENT, WAFER ARRANGEMENT AND METHOD OF MANUFACTURING THE SAME

INFINEON TECHNOLOGIES AUS...

1. A chip arrangement, comprising:
a first chip comprising a semiconductor substrate and having a first chip side and a second chip side opposite the first chip
side and at least one contact on its second chip side;

a second chip comprising a semiconductor substrate and having a first chip side and a second chip side opposite the first
chip side and at least one contact on its first chip side;

wherein the second chip side of the first chip and the second chip side of the second chip are facing each other;
a first electrically conductive structure extending from the at least one contact of the first chip from the second chip side
of the first chip through the first chip to the first chip side of the first chip so that the first electrically conductive
structure extends at least through the semiconductor substrate of the first chip; and

a second electrically conductive structure extending from the at least one contact of the second chip from the first chip
side of the second chip through the second chip and through the first chip to the first chip side of the first chip so that
the first second conductive structure extends at least through the semiconductor substrates of the first and second chips.

US Pat. No. 9,269,961

LITHIUM BATTERY, METHOD FOR MANUFACTURING A LITHIUM BATTERY, INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT

Infineon Technologies Aus...

1. A lithium battery, comprising:
a silicon substrate;
a cathode over the silicon substrate;
an anode integrally formed with the silicon substrate;
a separator element disposed between the cathode and the anode; and
an electrolyte.

US Pat. No. 9,294,006

POWER CONVERTER CIRCUIT WITH AC OUTPUT

Infineon Technologies Aus...

1. A power converter circuit, comprising:
a synchronization circuit configured to generate at least one synchronization signal as a rectified alternating signal;
at least one series circuit comprising a plurality of converter units configured to output an overall output current; and
an unfolding circuit configured to convert the overall output current received from the series circuit into an alternating
output current, wherein at least one of the plurality of converter units is configured to generate an output current such
that at least one of a frequency and a phase of the generated output current is dependent on the synchronization signal.

US Pat. No. 9,276,097

GATE OVERVOLTAGE PROTECTION FOR COMPOUND SEMICONDUCTOR TRANSISTORS

Infineon Technologies Aus...

1. A transistor device, comprising:
a compound semiconductor body;
a drain disposed in the compound semiconductor body;
a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region;
a gate operable to control the channel region; and
a gate overvoltage protection device connected between the source and the gate and comprising p-type and n-type silicon-containing
semiconductor material,

wherein the compound semiconductor body comprises a doped SiC substrate and a SiC epitaxial layer on the doped SiC substrate,
the source is electrically connected to the doped SiC substrate through a conductive via disposed in a first trench extending
through the SiC epitaxial layer to the doped SiC substrate, the gate overvoltage protection device is disposed in a second
trench extending through the SiC epitaxial layer to the doped SiC substrate, the second trench is insulated from the SiC epitaxial
layer, and the gate overvoltage protection device comprises alternating regions of p-type and n-type SiC.

US Pat. No. 9,263,443

SEMICONDUCTOR DEVICE INCLUDING A NORMALLY-OFF TRANSISTOR AND TRANSISTOR CELLS OF A NORMALLY-ON GAN HEMT

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a first semiconductor die including a normally-off transistor; and
a second semiconductor die including a plurality of transistor cells of a normally-on GaN HEMT, one of a source terminal and
a drain terminal of the normally-off transistor being electrically coupled to a gate terminal of the normally-on GaN HEMT,
the other one of the source terminal and the drain terminal of the normally-off transistor being electrically coupled to one
of a source terminal and a drain terminal of the normally-on GaN HEMT,

wherein the second semiconductor die further includes:
a gate resistor electrically coupled between the gate terminal of the normally-on transistor and respective gates of the plurality
of transistor cells; and

a voltage clamping element electrically coupled between the gate terminal and the one of the source terminal and the drain
terminal of the normally-on GaN HEMT.

US Pat. No. 9,293,533

SEMICONDUCTOR SWITCHING DEVICES WITH DIFFERENT LOCAL TRANSCONDUCTANCE

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a semiconductor substrate comprising an outer rim, a plurality of switchable cells defining an active area, and an edge termination
region arranged between the switchable cells defining the active area and the outer rim, wherein each of the switchable cells
comprises a body region, a gate electrode structure and a source region;

a source metallization in ohmic contact with the source regions of the switchable cells; and
a gate metallization in ohmic contact with the gate electrode structures of the switchable cells,
wherein the active area defined by the switchable cells comprises at least a first switchable region having a first transconductance
and at least a second switchable region having a second transconductance which is different from the first transconductance

wherein the second switchable region is arranged between the gate metallization and the first switchable region, wherein the
second transconductance of the second switchable region is lower than the first transconductance of the first switchable region,
and

wherein a ratio of the area of the second switchable region to the total area of the switchable regions is in a range from
5% to 50%.

US Pat. No. 9,159,796

METHOD FOR PROTECTING A SEMICONDUCTOR DEVICE AGAINST DEGRADATION AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE PROTECTED AGAINST HOT CHARGE CARRIERS

Infineon Technologies Aus...

1. A method for protecting a semiconductor device against degradation of its electrical characteristics, comprising:
providing a semiconductor device comprising a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor
interface, the first semiconductor region comprising majority charge carriers of a first charge type, and the charged dielectric
layer comprising fixed charges of the first charge type; and

configuring a charge carrier density per area of the fixed charges such that the charged dielectric layer is shielded against
entrapment of hot majority charge carriers generated in the first semiconductor region.

US Pat. No. 9,263,545

METHOD OF MANUFACTURING A HIGH BREAKDOWN VOLTAGE III-NITRIDE DEVICE

Infineon Technologies Aus...

1. A method of manufacturing a semiconductor device, the method comprising:
forming a semiconductor body including a compound semiconductor material on a substrate, the compound semiconductor material
having a channel region;

forming a source region extending to the compound semiconductor material;
forming a drain region extending to the compound semiconductor material and spaced apart from the source region by the channel
region; and

forming an insulating region buried in the semiconductor body below the channel region between the compound semiconductor
material and the substrate in an active region of the semiconductor device such that the channel region is uninterrupted by
the insulating region, the active region including the source, the drain and the channel region, the insulating region being
discontinuous over a length of the channel region between the source region and the drain region.

US Pat. No. 9,124,189

CONVERTER WITH GALVANIC ISOLATION

INFINEON TECHNOLOGIES AUS...

1. A converter comprising
a transformer providing a galvanic isolation between a primary side and a secondary side of the converter;
at least one switching element;
a converter control unit comprising
a first pin for controlling the at least one switching element and
a second pin
for detecting a current signal in the at least one switching element during a first phase; and
for detecting an output voltage signal of the secondary side of the converter and an information regarding a current in a
secondary winding of the transformer during a second phase;

wherein the output voltage signal of the secondary side of the converter and the information regarding the current in the
secondary winding of the transformer during the second phase are detected by an additional winding of the transformer that
is fed via a series connection of a diode and a resistor to the second pin.

US Pat. No. 9,245,943

SEMICONDUCTOR BODY WITH STRAINED MONOCRYSTALLINE REGION

Infineon Technologies Aus...

1. A semiconductor body composed of a semiconductor material, comprising:
a first monocrystalline region of the semiconductor material having a first lattice constant along a reference direction;
a second monocrystalline region of the semiconductor material having a second lattice constant, which is different than the
first lattice constant, along the reference direction; and

a third, strained monocrystalline region between the first region and the second region,
wherein the first monocrystalline region has a first crystal orientation and the second monocrystalline region has a second
crystal orientation, which is different than the first crystal orientation.

US Pat. No. 9,350,342

SYSTEM AND METHOD FOR GENERATING AN AUXILIARY VOLTAGE

Infineon Technologies Aus...

1. A circuit comprising:
a first normally-on transistor having a drain coupled to a first switching output node;
a normally-off transistor having a drain coupled to a source of the first normally-on transistor;
a driver circuit configured to receive a switching signal, the driver circuit having an output coupled to a gate of the first
normally-on transistor; and

a second normally-on transistor having a drain terminal coupled to a supply node, a gate terminal coupled to the output of
the driver circuit, and a source terminal configured to provide an auxiliary voltage.

US Pat. No. 9,318,483

REVERSE BLOCKING TRANSISTOR DEVICE

Infineon Technologies Aus...

1. A transistor device comprising at least one transistor cell, the at least one transistor cell comprising:
a drift region, a source region, a body region arranged between the source region and the drift region, and a drain region,
wherein the drift region is arranged between the body region and the drain region;

a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric;
a channel region of a doping type complementary to a doping type of the drain region that is arranged between the drift region
and the drain region;

a drift control region adjacent the drift region and dielectrically insulated from the drift region and the channel region
by a drift control region dielectric; and

a first switch coupled between the drift control region and the drain region.

US Pat. No. 9,397,208

COMPOUND SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A semiconductor device, comprising:
A first III-nitride material;
a second III-nitride_material on the first III-nitride_material, the second III-nitride material comprising a different bandgap
than the first III-nitride material and wherein a two-dimensional electron gas (2DEG) extends along an interface between the
first and second III-nitride materials; and

a buried field plate disposed in the first III-nitride material and electrically connected to a terminal of the semiconductor
device, the 2DEG being interposed between the buried field plate and the second III-nitride material.

US Pat. No. 9,267,972

INTEGRATED GALVANICALLY ISOLATED METER DEVICES AND METHODS FOR MAKING INTEGRATED GALVANICALLY ISOLATED METER DEVICES

Infineon Technologies Aus...

1. An integrated meter device comprising:
a low side unit configured to operate with a first voltage;
an intermediate unit configured to operate with a second voltage;
a first magnetic transfer unit galvanically isolating the intermediate unit from the low side unit;
a high side unit configured to operate with a third voltage; and
a second magnetic transfer unit galvanically isolating the intermediate unit from the high side unit,
wherein the high side unit comprises an energy transfer unit, a power management unit and a control unit, wherein the energy
transfer unit is configured to receive energy via the second magnetic transfer unit, wherein the power management unit is
configured to control power of the high side unit, wherein the control unit is configured to control sensed data related to
at least one parameter of a power line,

wherein the high side unit is configured to measure the at least one parameter of the power line,
wherein the first voltage, the second voltage and the third voltage are different,
wherein the high side unit and the second magnetic transfer unit are arranged in a first chip, wherein the intermediate unit
and the first magnetic transfer unit are arranged in a second chip, wherein the low side unit is arranged in a third chip,
and wherein all three chips are disposed on a carrier and encapsulated in a package.

US Pat. No. 9,263,529

SEMICONDUCTOR DEVICE WITH VERTICALLY INHOMOGENEOUS HEAVY METAL DOPING PROFILE

Infineon Technologies Aus...

1. A semiconductor device having a thickness L comprising:
a p-doped region;
an n-doped region; and
a vertically inhomogeneous heavy metal doping profile comprising a first heavy metal doping concentration greater than C1
across a first depth region of a thickness greater than L/6 and a second heavy metal doping concentration smaller than C2
across a second depth region of a thickness greater than L/6, wherein C1>3×C2, and

wherein the semiconductor device is a PIN diode.

US Pat. No. 9,202,910

LATERAL POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A LATERAL POWER SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A lateral power semiconductor device, comprising:
a semiconductor body having a first surface and a second surface opposite the first surface;
a first main electrode comprising at least two sections arranged on the first surface;
a second main electrode arranged on the first surface and between the two sections of the first main electrode;
a plurality of switchable semiconductor cells arranged between a respective one of the two sections of the first main electrode
and the second main electrode and configured to provide a controllable conductive path between the first main electrode and
the second main electrode; and

at least one curved semiconductor portion between the first main electrode and the second main electrode with increasing doping
concentration from the first main electrode to the second main electrode.

US Pat. No. 9,153,674

INSULATED GATE BIPOLAR TRANSISTOR

Infineon Technologies Aus...

1. An insulated gate bipolar transistor, comprising:
a transistor cell area including source, body regions, and gates and a junction termination area at a first side of a semiconductor
zone of a first conductivity type;

an emitter region of a second conductivity type at a second side of the semiconductor zone, the emitter region being opposed
to the cell area region;

at least one second region of the second conductivity type at the second side of the semiconductor zone, wherein the at least
one second region is opposed to and covered by the cell area region and each of the at least one second region is disposed
at a lateral distance from the emitter region and has a lateral dimension smaller than the emitter region, and wherein the
at least one second region is configured to inject charge carriers into the semiconductor zone via a terminal at the second
side; and

a third region of the second conductivity type at the second side of the semiconductor zone, the third region being arranged
in an area including at least part of both the emitter region and the at least one second region, and wherein a maximum dopant
concentration of the third region is smaller than the maximum dopant concentration of the emitter region,

wherein the at least one second region is arranged between the emitter region and the junction termination area; and
wherein each of the emitter region, the at least one second region and the third region extend from a common surface at the
second side into the semiconductor zone.

US Pat. No. 9,344,006

DRIVING CIRCUIT FOR A TRANSISTOR

INFINEON TECHNOLOGIES AUS...

1. A driving circuit for a transistor, comprising: a transistor comprising a control terminal and an emitter terminal; a diode;
a capacitor with a first terminal and a second terminal, wherein the first terminal is coupled to the control terminal and
the second terminal is coupled to a reference potential via the diode; and a resistor, which is coupled in parallel to the
capacitor; wherein the driving circuit is coupled between the control terminal and the emitter terminal; wherein the capacitance
value of the capacitor is larger than a sum of parasitic capacitances of the driving circuit at least by a factor of 5.

US Pat. No. 9,257,424

SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a composite semiconductor body, comprising:
a high voltage depletion-mode transistor; and
a low voltage enhancement-mode transistor, the high voltage depletion-mode transistor being stacked on the low voltage enhancement-mode
transistor so that an interface is formed between the high voltage depletion-mode transistor and the low voltage enhancement-mode
transistor, wherein the low voltage enhancement-mode transistor is wider than the high voltage depletion-mode transistor such
that the low voltage enhancement-mode transistor has an exposed surface uncovered by the high voltage depletion-mode transistor
and which extends along said interface, and wherein the low voltage enhancement-mode transistor comprises a current path coupled
in series with a current path of the high voltage depletion-mode transistor and a control electrode arranged at the interface,
and

an additional electrode that contacts a source of the high voltage depletion-mode transistor at a side of the high voltage
depletion-mode transistor facing away from the interface, the additional electrode extending along an edge face of the high
voltage depletion-mode transistor and onto the exposed surface of the low voltage enhancement-mode transistor so as to contact
a drain of the low voltage enhancement-mode transistor.

US Pat. No. 9,172,363

DRIVING AN MOS TRANSISTOR WITH CONSTANT PRECHARGING

Infineon Technologies Aus...

1. A method, comprising:
switching on an MOS transistor by precharging an input capacitance of the MOS transistor with a substantially constant amount
of charge in a precharging phase, and charging the input capacitance with a controlled charging current after the precharging
phase;

generating, with a current source controller, a current source control signal, such that a controlled current source provides
substantially constant amount of charge in the precharging phase and provides the controlled charging current after the precharging
phase;

wherein generating the current source control signal includes generating the current source control signal with a first signal
level for a predefined time period, and generating the current source control signal with a second signal level different
from the first signal level after the predefined time period.

US Pat. No. 9,054,123

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A method for forming a semiconductor device, comprising:
providing a wafer comprising an upper surface and a plurality of semiconductor mesas extending to the upper surface, adjacent
pairs of the semiconductor mesas of the plurality of semiconductor mesas being separated from each other by at least one of
a trench extending from the upper surface into the wafer, and a non-semiconductor region arranged on a side-wall of the trench;

forming a first support structure comprising a first material above the upper surface and adjoining the plurality of semiconductor
mesas at the upper surface so that the adjacent pairs of the semiconductor mesas are bridged by the first support structure;

forming a second support structure comprising a second material above the upper surface and adjoining the plurality of semiconductor
mesas at the upper surface so that the adjacent pairs of the semiconductor mesas are bridged by the second support structure,
the second material being different from the first material;

removing the first support structure; and
at least partly removing the second support structure.

US Pat. No. 9,231,565

CIRCUIT WITH A PLURALITY OF BIPOLAR TRANSISTORS AND METHOD FOR CONTROLLING SUCH A CIRCUIT

Infineon Technologies Aus...

1. A method for operating a circuit, the circuit comprising a first node, a second node and a plurality of bipolar transistors
coupled in parallel between the first node and the second node, the method comprising in one drive cycle:
switching on bipolar transistors of a first group of the plurality of bipolar transistors, the first group comprising a first
subgroup and a second subgroup and each of the first subgroup and the second subgroup comprising one or more of the bipolar
transistors;

switching off the bipolar transistors of the first subgroup at the end of a first time period; and
switching off the bipolar transistors of the second subgroup at a time instant before the end of the first time period,
wherein the plurality of bipolar transistors have their load paths coupled in parallel.

US Pat. No. 10,440,825

CHIP CARD MODULE AND METHOD FOR PRODUCING A CHIP CARD MODULE

Infineon Technologies Aus...

1. A chip card module, comprising:a chip card module contact array having six contact pads that are arranged in a first row and a second row, each of the first row and the second row comprising three contact pads, the three contact pads of the first row being arranged in accordance with positions for contacts C1, C2, and C3 in ISO 7816-2, and the three contact pads of the second row being arranged in accordance with positions for contacts C5, C6, and C7 in ISO 7816-2, and
three additional contact pads that are arranged between the two rows;
wherein each additional contact pad is electrically conductively connected to a respective associated contact pad from a row from the two rows; and
at least one chip;
wherein the at least one chip is electrically conductively connected to each of the associated contact pads by each respective additional contact pad electrically conductively connected to the associated contact pad;
wherein the chip card module further comprises a main region and a removable region removable from the chip card module;
wherein the at least one chip, three contact pads from the first row and the three additional contact pads are arranged in the main region and the three contact pads from the second row are arranged in the removable region.

US Pat. No. 9,257,503

SUPERJUNCTION SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THEREOF

Infineon Technologies Aus...

1. A method of forming a superjunction device, comprising:
forming at least one trench in a first surface of a first semiconductor layer of a first doping type, and a semiconductor
mesa region adjoining the at least one trench;

forming a second semiconductor layer at least on sidewalls and a bottom of the at least one trench; and
etching the second semiconductor layer by filling the at least one trench with an etchant, and applying a voltage between
the first semiconductor layer and the etchant such that a space charge region expands in the second semiconductor layer and
in the first semiconductor layer;

wherein the voltage is adjusted such that there is a first region in the semiconductor mesa region that is free of the space
charge region when the voltage is applied.

US Pat. No. 9,252,251

SEMICONDUCTOR COMPONENT WITH A SPACE SAVING EDGE STRUCTURE

Infineon Technologies Aus...

1. A semiconductor component comprising:
a semiconductor body comprising a first side and a second side, and a first semiconductor layer having a basic doping of a
first conductivity type;

at least one active component zone of a second conductivity type, which is complementary to the first conductivity type, in
the first semiconductor layer;

a cell array with a plurality of trenches, each trench including a field electrode and a field electrode dielectric, wherein
in the cell array the at least one active component zone of the second conductivity type is electrically connected to an electrode,
the cell array including an edge region, wherein the edge region of the cell array includes at least an outermost trench of
the cell array and a trench of the cell array adjacent to the outermost trench; and

at least one cell array edge zone of the second conductivity type, the at least one cell array edge zone arranged only in
the edge region of the cell array at least partially below and having an interface with at least one trench in the edge region
of the cell array, wherein the cell array edge zone is spaced apart from the first side of the semiconductor body,

wherein the semiconductor component is implemented as a MOS transistor and comprising in the inner region a plurality of transistor
cells, each transistor cell comprising: a source zone of a first conductivity type, a drift zone of the first conductivity
type, and a body zone of the second conductivity type between the source zone and the drift zone; a gate electrode being disposed
adjacent to the body zone and being insulated against the body zone by a gate dielectric, and wherein the gate electrodes
of the transistor cells are arranged in the same trenches as the field electrodes, the field electrodes extending deeper into
the semiconductor body than the gate electrodes.

US Pat. No. 9,285,399

SWITCHING REGULATOR CYCLE-BY-CYCLE CURRENT ESTIMATION

Infineon Technologies Aus...

1. A method of estimating cycle average current for an output phase of a switching regulator during pulse width modulation
(PWM) cycles of the switching regulator, each PWM cycle having an on-portion and an off-portion, the method comprising:
measuring a low-side transistor current of the output phase during the off-portion for each PWM cycle;
estimating a pulse width for the on-portion for the present PWM cycle;
estimating a cycle average current for the present PWM cycle based on the low-side transistor current measured during the
off-portion for the immediately preceding PWM cycle and the pulse width estimate for the on-portion for the present PWM cycle;

comparing the cycle average current estimated for each PWM cycle to a measured phase current for the same PWM cycle upon completion
of that PWM cycle to generate a prediction error;

incorporating the cycle average current estimate into a response of the switching regulator; and
compensating for the prediction error so that a steady-state response of the switching regulator is unaffected by the prediction
error.

US Pat. No. 9,209,292

CHARGE COMPENSATION SEMICONDUCTOR DEVICES

Infineon Technologies Aus...

1. A field-effect semiconductor device, comprising:
a semiconductor body comprising a first surface, an edge delimiting the semiconductor body in a direction substantially parallel
to the first surface, an active area, and a peripheral area arranged between the active area and the edge;

a source metallization arranged on the first surface; and
a drain metallization,
in the active area the semiconductor body further comprising:
a plurality of drift portions of a first conductivity type alternating with compensation regions of a second conductivity
type, the drift portions comprising a first maximum doping concentration and being in Ohmic contact with the drain metallization,
the compensation regions being in Ohmic contact with the source metallization,

in the peripheral area the semiconductor body further comprising:
a second semiconductor region in Ohmic contact with the drift portions and comprising a second maximum doping concentration
of dopants of the first conductivity type, the second maximum doping concentration being lower than the first maximum doping
concentration of the drift portions by a factor of at least five;

a first edge termination region of the second conductivity type in Ohmic contact with the source metallization and adjoining
the second semiconductor region, and

a second edge termination region of the first conductivity type comprising a fourth maximum doping concentration higher than
the second maximum doping concentration, the second edge termination region being in Ohmic contact with the drain metallization,
adjoining the first edge termination region, and being arranged between the first edge termination region and the first surface.

US Pat. No. 9,195,251

CONTROLLED POWER FACTOR CORRECTION CIRCUIT

INFINEON TECHNOLOGIES AUS...

1. A circuit arrangement, comprising:
a first AC input node and a second AC input node;
a first electronic switching device coupled between the first AC input node and an output node;
a second electronic switching device coupled between the second AC input node and the output node;
an inductor coupled between the first electronic switching device and the second electronic switching device;
a controller configured to control the first electronic switching device and the second electronic switching device to
in a first mode, provide a first current path from the first AC input node to the output node via the first electronic switching
device and the inductor, in a first current flow direction through the inductor; and

in a second mode, provide a second current path from the second AC input node to the output node via the second electronic
switching device and the inductor, in a second current flow direction through the inductor, the second current flow direction
being different from the first current flow direction.

US Pat. No. 9,397,517

CABLE COMPENSATION BY ZERO-CROSSING COMPENSATION CURRENT AND RESISTOR

Infineon Technologies Aus...

1. A method comprising:
delivering a first level of output voltage to a rechargeable battery from a battery charger, wherein the rechargeable battery
is coupled to the battery charger by a charging cable; and

applying, in response to an indication of an altered output voltage, a compensation current to one or more elements of the
battery charger including a zero crossing (ZC) pin and a selected resistor, wherein the selected resistor is defined based
on the charging cable coupling the battery charger to the rechargeable battery;

wherein applying the compensation current to the ZC pin and the selected resistor causes an adjustment of the output voltage
from the first level of output voltage to a second level of output voltage corresponding to the voltage drop from an impedance
of the charging cable.

US Pat. No. 9,202,909

POWER MOSFET SEMICONDUCTOR

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a source metallization;
a source region of a first conductivity type, the source region being connected to the source metallization;
a body region of a second conductivity type adjacent to the source region;
a drift region of a first conductivity type adjacent to the body region;
a third conductive region of a second conductivity type buried within the drift region; and
a trench extending from the source region through the body region and at least to the third conductive region; the trench
adjoining the third conductive region and including a conductive plug and an insulating layer, which is arranged between the
conductive plug and the body region, the conductive plug forming at least a portion of an Ohmic connection between the source
metallization and the third conductive region; the conductive plug, the insulating layer and the body region forming a field
effect structure.

US Pat. No. 9,065,339

METHODS AND APPARATUS FOR VOLTAGE REGULATION WITH DYNAMIC TRANSIENT OPTIMIZATION

Infineon Technologies Aus...

1. A method of dynamic transient optimization in a voltage regulator, the method comprising:
measuring a voltage error in the voltage regulator;
setting an excursion signal at a first value when the voltage error exceeds a positive amplitude threshold and setting the
excursion signal at a second value different than the first value when the voltage error exceeds a negative amplitude threshold,
such that the excursion signal changes from the first value to the second value only when the voltage error changes from exceeding
the positive amplitude threshold to exceeding the negative amplitude threshold and changes from the second value to the first
value only when the voltage error changes from exceeding the negative threshold to exceeding the positive threshold, so as
to define a window for which the excursion signal changes from one of the values to the other value so long as the voltage
error changes from exceeding one of the amplitude thresholds to exceeding the other amplitude threshold;

measuring a frequency of the excursion signal between changes in the excursion signal; and
providing a corrective action if the frequency exceeds a frequency threshold,
wherein one or both of the amplitude thresholds are programmable,
wherein the frequency threshold is programmable.

US Pat. No. 9,310,445

POWER SOURCE ARRANGEMENT AND METHOD OF DIAGNOSING A POWER SOURCE ARRANGEMENT

Infineon Technologies Aus...

1. A circuit arrangement comprising:
a power source arrangement comprising output terminals and a plurality of n power sources connected in series between the
output terminals, wherein n?2; and

a diagnostic circuit coupled to the power source arrangement,
the diagnostic circuit configured to select at least two different groups of power sources from the power source arrangement,
the diagnostic circuit configured to measure a voltage of each of the at least two different groups between the output terminals,
wherein during the measurement of the voltage of one group of the power sources of the power source arrangement that do not
belong to the one group are bypassed, and

the diagnostic circuit configured to compare the at least two measured voltages obtained through measuring the voltage of
each of the at least two groups or to compare at least two voltages dependent on these at least two measured voltages, wherein,
when a difference between two of the measured voltages or between two of the voltages dependent on the measured voltages is
higher than a threshold value, the diagnostic circuit is

a) configured to select at least two different groups of power sources from a group that has a lowest voltage;
b) configured to measure the voltage of each group between the output terminals, wherein during the measurement of the voltage
of one group the power sources of the power source arrangement that do not belong to the one group are bypassed; and

c) configured to compare the at least two measured voltages obtained through measuring the voltage of each group, or to compare
two voltages dependent on the at least two measured voltages.

US Pat. No. 9,142,447

SEMICONDUCTOR HAVING OPTIMIZED INSULATION STRUCTURE AND PROCESS FOR PRODUCING THE SEMICONDUCTOR

Infineon Technologies Aus...

1. A semiconductor having an insulation structure including a plurality of insulation regions comprising:
at least one of the insulation regions disposed at a surface of a semiconductor substrate, the at least one insulation region,
relative to the surface of a directly adjacent region of the semiconductor substrate, both extending into and projecting out
of the semiconductor substrate;

wherein an edge region of the insulation regions has a flank in a transition between the at least one insulation region and
the semiconductor substrate, said flank being a steep flank having a lateral extent of less than 50 nm from the surface of
the directly adjacent region to a top side or an underside of the insulation region; and

wherein at least one subregion of the semiconductor substrate includes a silicon oxide insulation region and a silicon nitride
insulation region, and wherein the silicon oxide insulation region and the silicon nitride insulation region partially overlap
one another laterally in an overlapping region, so that outside of the overlapping region a vertical line extending perpendicularly
to the surface of the semiconductor substrate intersects only the silicon oxide insulation region or the silicon nitride insulation
region but not both the silicon oxide insulation region and the silicon nitride insulation region.

US Pat. No. 9,190,480

METHOD AND CONTACT STRUCTURE FOR COUPLING A DOPED BODY REGION TO A TRENCH ELECTRODE OF A SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

10. A method of forming a semiconductor device in a semiconductor body comprising a first surface, a second surface opposite
the first surface, an edge extending between the first and second surfaces, an active device region spaced inward from the
edge and comprising at least one active semiconductor device, and an edge termination region between the active device region
and the edge, the method comprising:
forming a trench extending from the first surface into the semiconductor body in the edge termination region, the trench comprising
sidewalls and an electrode insulated from the surrounding semiconductor body;

forming a first doped region of a first conductivity type extending from the first surface into the semiconductor body in
the edge termination region, the first doped region having a planar surface disposed along the first surface that adjoins
one of the trench sidewalls at a corner of the trench sidewall and the first surface and a side surface extending from the
corner along the trench sidewall;

forming a first interconnect contacting the trench electrode;
forming a second interconnect contacting the outer surface and the side surface of the first doped region; and
forming an edge region contact adjacent to the first and second interconnects and electrically coupling the first doped region
to the trench electrode, the edge region contact having a bottom surface that is coplanar with the first surface from an edge
of the edge region contact to the corner.

US Pat. No. 9,699,868

SINGLE ISOLATION ELEMENT FOR MULTIPLE INTERFACE STANDARDS

Infineon Technologies Aus...

1. A device comprising:
a transformer configured to electrically isolate one or more components of the device from a communication bus; and
a controller configured to receive data and transmit data via the communication bus, wherein the controller is operable to
communicate via a plurality of communication standards that include at least one analog unidirectional communication standard
and at least one digital bidirectional communication standard, and wherein both the received data and the transmitted data
pass through the transformer.

US Pat. No. 9,337,748

SYSTEM AND METHOD FOR A DC-TO-DC POWER CONVERTER WITH INVERTER STAGE COUPLED TO THE DC INPUT

Infineon Technologies Aus...

1. An inverter circuit comprising:
a direct current (DC), DC-to-DC power converter configured to receive an input energy from a DC device via a first, positive
input terminal and a second, negative input terminal and to convert a first portion of the input energy to a higher voltage
DC energy;

a first inverter stage wherein:
the first inverter stage is a two-level bridge,
a first input of the first inverter stage is coupled to a first positive DC voltage output of the DC-to-DC power converter,
a second input of the first inverter stage is coupled to the second, negative input terminal of the DC-to-DC power converter,
and

an output of the first inverter stage is coupled to a first grid terminal; and
a second inverter stage wherein:
the second inverter stage comprises a three level bridge,
a first input of the second inverter stage is coupled to the first positive DC voltage output of the DC-to-DC power converter,
a second input of the second inverter stage is coupled to a positive output of the DC device,
a third input of the second inverter stage is coupled to a negative output of the DC device, and
an output of the second inverter stage is coupled to a second grid terminal.

US Pat. No. 9,269,711

SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. An integrated circuit, comprising:
a first transistor at least partially formed in a semiconductor substrate, the first transistor comprising a first body region
and a first gate electrode;

a plurality of second transistors connected in series to form a series circuit, the series circuit being connected in series
with the first transistor and implementing an active drift zone field effect transistor, at least one of the second transistors
comprising:

a first ridge and a second ridge extending from a first main surface of the semiconductor substrate, the first and second
ridges running in a first direction;

a second body region of at least one of the second transistors being disposed in a portion of the semiconductor substrate
between the first ridge and the second ridge, the first and second ridges being connected with the second body region; and

a second gate electrode of said one of the second transistors being disposed adjacent to the second body region, the second
gate electrode running in the first direction.

US Pat. No. 9,178,016

CHARGE PROTECTION FOR III-NITRIDE DEVICES

Infineon Technologies Aus...

29. A method of manufacturing a semiconductor device, the method comprising:
forming a III-nitride semiconductor substrate having a two-dimensional charge carrier gas at a depth from a main surface of
the III-nitride semiconductor substrate;

forming a surface protection layer on the main surface of the III-nitride semiconductor substrate, the surface protection
layer having charge traps in a band gap which exist at room temperature operation of the semiconductor device;

forming a contact in electrical connection with the two-dimensional charge carrier gas in the III-nitride semiconductor substrate;
forming a charge protection layer on the surface protection layer, the charge protection layer comprising an oxide and shielding
the surface protection layer under the charge protection layer from radiation with higher energy than the bandgap energy of
silicon nitride; and

forming an interlayer dielectric on the surface protection layer, wherein the charge protection layer is formed in the interlayer
dielectric so that only part of the interlayer dielectric separates the charge protection layer from the surface protection
layer.

US Pat. No. 9,112,021

HIGH VOLTAGE BIPOLAR TRANSISTOR WITH TRENCH FIELD PLATE

Infineon Technologies Aus...

1. A method of manufacturing a bipolar transistor structure, comprising:
forming an epitaxial layer on a semiconductor substrate;
forming a bipolar transistor device in the epitaxial layer, the bipolar transistor device comprising a base in the epitaxial
layer, a collector including a portion of the epitaxial layer between the substrate and the base, and an emitter in the epitaxial
layer adjacent the base so that the base is interposed between the collector and the emitter in a direction perpendicular
to a main surface of the substrate;

forming a trench structure in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device,
the trench structure including a field plate spaced apart from the epitaxial layer by an insulating material;

connecting a base contact to a base of the bipolar transistor device; and
connecting an emitter contact to an emitter of the bipolar transistor device so that the emitter contact and the base contact
are isolated from one another.

US Pat. No. 10,117,321

DEVICE INCLUDING A PRINTED CIRCUIT BOARD AND A METAL WORKPIECE

Infineon Technologies Aus...

1. A device, comprising:a first semiconductor package, comprising a semiconductor chip, an encapsulation material at least partly covering the semiconductor chip, and a contact element electrically coupled to the semiconductor chip and protruding out of the encapsulation material;
a printed circuit board, wherein the first semiconductor package is mounted on the printed circuit board and the contact element of the first semiconductor package is electrically coupled to the printed circuit board; and
a first metal workpiece mounted on the printed circuit board and adjacent to the first semiconductor package, wherein the first metal workpiece is electrically coupled to the contact element of the first semiconductor package and configured to provide a direct electrical connection between the contact element of the first semiconductor package and a second contact element of a second semiconductor package that is mounted on the printed circuit board, wherein the first semiconductor package is arranged over a first location on the printed circuit board and the second semiconductor package is arranged over a second location on the printed circuit board that is different than the first location.

US Pat. No. 9,312,760

SWITCHED-MODE POWER CONVERTER WITH SPLIT PARTITIONING

Infineon Technologies Aus...

1. A power converter comprising:
a FET or SFET type die including one or more FET or SFET type switches coupled to a switching node of a power stage; and
a CMOS type die including:
one or more CMOS type switches coupled to the switching node of the power stage;
one or more sense lines contained to the CMOS type die to prevent electromagnetic interference associated with the one or
more FET or SFET type switches of the FET or SFET type die, the one or more sense lines being configured to transmit a sense-FET
current sensing signal associated with the one or more CMOS type switches; and

a controller unit configured to control the one or more FET or SFET type switches and the one or more CMOS type switches of
the power stage based at least in part on the sense-FET current sensing signal that is transmitted by the one or more sense
lines to produce a power output at the switching node of the power stage.

US Pat. No. 9,287,354

SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING IT

Infineon Technologies Aus...

1. A semiconductor component comprising:
a semiconductor body having:
a first electrode electrically connected to a first zone of the semiconductor body; a second electrode electrically connected
to a second zone of the semiconductor body, the first electrode being arranged on a top side of the semiconductor body and
the second electrode being arranged on a rear side of the semiconductor body;

a drift path region arranged in the semiconductor body between the first electrode and the second electrode;
a cell region having:
a main cell region with main cells; and
an auxiliary cell region with at least one auxiliary cell;
wherein a first trench depth for a field plate in the main cell region is smaller than a second trench depth for a field plate
in the auxiliary cell region, wherein the cell region includes a highly doped substrate, and wherein a pedestal region is
disposed on the highly doped substrate, only in the main cell region.

US Pat. No. 9,054,040

MULTI-DIE PACKAGE WITH SEPARATE INTER-DIE INTERCONNECTS

Infineon Technologies Aus...

1. A multi-die package, comprising:
a substrate having a plurality of conductive regions;
a first semiconductor die having first and second opposing sides, a first electrode at the first side connected to a first
one of the conductive regions, and a second electrode at the second side;

a second semiconductor die having first and second opposing sides, a first electrode at the first side connected to a second
one of the conductive regions, and a second electrode at the second side;

a first metal layer extending from a periphery region of the substrate to over the first die, the first metal layer having
a generally rectangular cross-sectional area and connecting one of the conductive regions in the periphery region of the substrate
to the second electrode of the first die; and

a second metal layer separate from the first metal layer and extending over the first and second dies, the second metal layer
having a generally rectangular cross-sectional area and connecting the second electrode of the first die to the second electrode
of the second die.

US Pat. No. 9,355,957

SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT PLUGS

Infineon Technologies Aus...

1. A semiconductor device, comprising:
subsurface structures extending from a main surface into a semiconductor portion, each subsurface structure comprising a gate
electrode dielectrically insulated from the semiconductor portion;

alignment plugs in a vertical projection of the subsurface structures;
contact spacers extending along sidewalls of the alignment plugs tilted to the main surface; and
contact plugs directly adjoining semiconductor mesas between the subsurface structures, the contact plugs provided between
opposing ones of the contact spacers;
wherein the alignment plugs comprise (i) gate contact spacers of a first auxiliary material along sidewalls of the contact
spacer opposite to the contact plugs and (ii) gate contacts between the gate contact spacers assigned to a respective subsurface
structure.

US Pat. No. 9,059,155

CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME

INFINEON TECHNOLOGIES AUS...

1. A chip package comprising:
a metallic chip carrier;
at least one chip carried by the metallic chip carrier;
encapsulation material encapsulating the at least one chip and the metallic chip carrier;
a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least
one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip;

at least one contact hole extending through the encapsulation material to electrically couple the at least one chip with the
at least one of the plurality of redistribution layers; and

an electrically conductive layer disposed over the metallic chip carrier opposite the plurality of redistribution layers.

US Pat. No. 9,419,513

POWER FACTOR CORRECTOR TIMING CONTROL WITH EFFICIENT POWER FACTOR AND THD

Infineon Technologies Aus...

1. A device for controlling switch timing in a power factor correction timing switch, the device configured to:
receive one or more indications of one or more power factor correction circuit parameters;
determine a switch delay time based at least in part on the one or more power factor correction circuit parameters; and
generate an indication of a switch on time for the power factor correction timing switch, wherein the switch on time is based
at least in part on the switch delay time,

wherein the switch on time is further varied based at least in part on compensating for a switch delay time corresponding
to a discrete number of (N+½) oscillations in an inductor current, where N is an integer.

US Pat. No. 9,444,363

CIRCUIT ARRANGEMENT WITH A RECTIFIER CIRCUIT

Infineon Technologies Aus...

1. A circuit arrangement, comprising:
a first rectifier circuit comprising a load path and a voltage tap;
a second rectifier circuit comprising a load path and a drive input, and configured to be switched on and off by a drive signal
received at the drive input; and

a drive circuit comprising a first supply input coupled to the voltage tap of the first rectifier circuit and a first drive
output coupled to the drive input of the second rectifier circuit,

wherein the load path of the first rectifier circuit and the load path of the second rectifier circuit are coupled to a common
circuit node, and

wherein the drive circuit is configured to drive at least the second rectifier circuit using electrical power received from
the voltage tap of the first rectifier circuit.

US Pat. No. 9,425,788

CURRENT SENSORS AND METHODS OF IMPROVING ACCURACY THEREOF

Infineon Technologies Aus...

7. A circuit comprising:
a three terminal power transistor; and
a four terminal sense transistor comprising a field plate, wherein a drain terminal of the four terminal sense transistor
is coupled to a drain terminal of the three terminal power transistor, wherein a gate terminal of the four terminal sense
transistor is coupled to a gate terminal of the three terminal power transistor, wherein the field plate is capacitively coupled
to a drift region of the four terminal sense transistor, and wherein the field plate is not coupled to the other terminals
of the four terminal sense transistor.

US Pat. No. 9,337,824

DRIVE CIRCUIT WITH ADJUSTABLE DEAD TIME

Infineon Technologies Aus...

1. A drive circuit, comprising:
a first input terminal configured to receive a first input signal;
a first output terminal configured to provide a first drive signal;
a second output terminal configured to provide a second drive signal; and
a mode selection terminal configured to have a mode selection element connected thereto;
wherein the drive circuit is configured to generate the first and second drive signals dependent on the first input signal
such that there is a dead time between a time when one of the first and second drive signals assumes an off-level and a time
when the other one of the first and second drive signals assumes an on-level; and

wherein the drive circuit is further configured to evaluate at least one electrical parameter of the mode selection element
and is configured to adjust a maximum signal level of the first drive signal and a maximum signal level of the second drive
signal dependent on the evaluated parameter and to adjust the dead time dependent on the evaluated parameter.

US Pat. No. 9,293,528

FIELD-EFFECT SEMICONDUCTOR DEVICE AND MANUFACTURING THEREFOR

Infineon Technologies Aus...

1. A field-effect semiconductor device, comprising:
a semiconductor body comprising a first surface, an edge delimiting the semiconductor body in a direction substantially parallel
to the first surface, an active area, and a peripheral area arranged between the active area and the edge;

a source metallization arranged on the first surface; and
a drain metallization opposite to the source metallization,
in the peripheral area the semiconductor body comprising a low-doped semiconductor region having a first average concentration
of dopants of a first conductivity type,

in a vertical cross-section substantially orthogonal to the first surface the semiconductor body further comprising:
a plurality of pillar regions of the first conductivity type alternating with pillar regions of a second conductivity type
in the active area, the pillar regions of the first conductivity type being in Ohmic contact with the drain metallization,
the pillar regions of the second conductivity type being in Ohmic contact with the source metallization; and

at least one auxiliary pillar region arranged in the peripheral area and comprising dopants of the first conductivity type
and dopants of the second conductivity type, the at least one auxiliary pillar region having an average concentration of the
dopants of the first conductivity type larger than the first average concentration.

US Pat. No. 9,287,376

METHOD OF MANUFACTURING A GATE TRENCH WITH THICK BOTTOM OXIDE

Infineon Technologies Aus...

1. A method of manufacturing an insulated gate trench, the method comprising:
forming a first dielectric layer on a semiconductor substrate;
forming a hardmask on the first dielectric layer;
etching a trench into the semiconductor substrate through an opening in the hardmask and the first dielectric layer, the trench
having sidewalls and a bottom;

lining the sidewalls and bottom of the trench with a second dielectric layer without an intervening oxide layer along the
sidewalls and bottom of the trench;

removing the second dielectric layer from at least part of the bottom of the trench to expose part of the semiconductor substrate;
oxidizing the exposed part of the semiconductor substrate to form an oxide region at the bottom of the trench; and
subsequently forming a gate dielectric on the sidewalls and bottom of the trench and a gate electrode in the trench without
a separate field electrode in the trench.

US Pat. No. 9,287,404

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH LATERAL FET CELLS AND FIELD PLATES

Infineon Technologies Aus...

1. A semiconductor device, comprising:
buried field plate stripes in a first area of a semiconductor portion, wherein longitudinal axes of the field plate stripes
run parallel to a first lateral direction parallel to a first surface of the semiconductor portion; and

buried cell stripes spaced from the buried field plate stripes along the first lateral direction, comprising first cell insulators
in the first area, comprising buried gate electrodes in a second area adjoining the first area in the first lateral direction
and devoid of buried gate electrodes in the first area,

wherein gate dielectrics thinner than the first cell insulators dielectrically insulate the buried gate electrodes from semiconductor
fins formed between neighboring cell stripes.

US Pat. No. 9,184,255

DIODE WITH CONTROLLABLE BREAKDOWN VOLTAGE

Infineon Technologies Aus...

1. A diode, comprising:
a semiconductor body;
a first emitter region of a first conductivity type;
a second emitter region of a second conductivity type;
a base region arranged between the first and second emitter regions and having a lower doping concentration than the first
and second emitter regions;

a first emitter electrode only electrically coupled to the first emitter region;
a second emitter electrode in electrical contact with the second emitter region;
a control electrode arrangement comprising a first control electrode section, and a first dielectric layer arranged between
the first control electrode section and the semiconductor body; and

at least one pn junction extending to the first dielectric layer or arranged distant to the first dielectric layer by less
than 250 nm;

wherein the base region has a length in the vertical direction of the semiconductor body that is a shortest distance between
the first emitter region and the second emitter region; and

wherein a distance between the first control electrode section and the second emitter region is less than 75% of the length
of the base region.

US Pat. No. 9,431,484

VERTICAL TRANSISTOR WITH IMPROVED ROBUSTNESS

Infineon Technologies Aus...

1. A transistor comprising:
a semiconductor body having a first horizontal surface that is a major surface of the semiconductor body;
a drift region arranged in the semiconductor body;
trenches disposed in the semiconductor body, the trenches extending parallel relative to each other along a first lateral
direction that is parallel to the first horizontal surface of the semiconductor body;

a plurality of gate electrodes, wherein each of the plurality of gate electrodes is disposed in a corresponding one of the
trenches;

body regions arranged between the trenches; and
source regions arranged between the trenches,
wherein the body regions are arranged between the drift region and the source regions in a vertical direction of the semiconductor
body,

wherein, in the first horizontal surface, the source regions and the body regions are arranged alternately in the first lateral
direction, wherein at least one of the body regions is arranged between two of the source regions in the first lateral direction
and at least one of the source regions is arranged between two of the body regions in the first lateral direction, and

wherein a source electrode is electrically connected to the source regions and the body regions in the first horizontal surface,
wherein the source electrode comprises electrode sections extending through the source regions into the body regions.

US Pat. No. 10,426,028

PRINTED CIRCUIT BOARD WITH INSULATED METAL SUBSTRATE MADE OF STEEL

Infineon Technologies Aus...

1. A power electronic device, comprisingan Insulated Metal Substrate Printed Circuit Board (IMS PCB)
a power semiconductor device package comprising a lead frame, a semiconductor die, and an electrically insulating housing;
the lead frame having a rigid configuration and being made of a lead frame material having a first thermal expansion coefficient,
wherein the semiconductor die is enclosed within the housing;
wherein the semiconductor die comprises a first terminal;
wherein the lead frame comprises a contact with a first end that is enclosed within the housing and a second end that is exposed from the housing,
wherein the contact is electrically connected to the first terminal, and
wherein the semiconductor device package is mounted on top of the IMS PCB with the second end of the contact directly facing and electrically contacting the IMS PCB,
wherein the IMS PCB comprises an insulated metal substrate made of a substrate material having a second thermal expansion coefficient within a range of 60% to 140% of the first thermal expansion coefficient.

US Pat. No. 9,488,995

VOLTAGE CONVERTER AND VOLTAGE CONVERSION METHOD HAVING MULTIPLE CONVERTER STAGES

INFINEON TECHNOLOGIES AUS...

1. A voltage converter comprising:
a first converter stage comprising a unipolar transistor coupled to a first inductive storage element, wherein the first converter
stage is configured to provide a first output power signal comprising a first output voltage and a first output current;

a second converter stage comprising a bipolar transistor coupled to a second inductive storage element, wherein the second
converter stage is configured to provide a second output power comprising a second output current and a second output voltage,
wherein a third output power comprises a third output current and a third output voltage, and wherein the third output current
is a sum of the first output current and the second output current; and

a control circuit configured to control the voltage converter comprising the first output current and the second output current,
wherein the first output current is higher than the second output current when the third output current is within a first
range, wherein the second output current is higher than the first output current when the third output current is within a
second range, wherein the third output current has a third range that is within both the first range and the second range,
wherein the first output current and the second output current are equal when the third output current is within in the third
range, and wherein at least one of the first output current and the second output current increases as the third output current
increases.

US Pat. No. 9,385,111

ELECTRONIC COMPONENT WITH ELECTRONIC CHIP BETWEEN REDISTRIBUTION STRUCTURE AND MOUNTING STRUCTURE

Infineon Technologies Aus...

1. An electronic component, the electronic component comprising:
an electrically conductive mounting structure;
an electrically conductive carrier structure, on which the electrically conductive mounting structure is arranged:
an electronic chip on the mounting structure;
an electrically conductive redistribution structure on the electronic chip;
a periphery connection structure electrically coupled to the redistribution structure and being configured for connecting
the electronic component to an electronic periphery;

the mounting structure being a contract structure such that the electronic chip is double sided electrically coupled via the
mounting structure on the one side and the redistribution structure on the other side;

wherein the periphery connection structure is configured as at least one electrically conductive leg, in particular a plurality
of electrically conductive legs and

wherein each of the at least one leg has a first connection portion and an opposing second connection portion, the first connection
portion being electrically connected to the redistribution structure, and the second connection portion being configured for
being plugged into a plug-in position of a board as the electronic periphery.

US Pat. No. 9,070,789

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A method for producing a plurality of semiconductor device chips, comprising:
applying an epitaxial layer to a semiconductor wafer, wherein the epitaxial layer is doped less highly than the semiconductor
wafer and drift zones of the semiconductor device;

anisotropic etching of column-shaped structures in the epitaxial layer;
applying a material including a first conductivity type at least on the inner side of the etched structures;
diffusing at least a part of the material including the first conductivity type into the surrounding semiconductor material;
applying a material including a second conductivity type complementary to the first conductivity type at least on the inner
side of the etched structures;

diffusing at least a part of the material including the second conductivity type into the surrounding semiconductor material;
filling the remaining etched structures;
structuring the semiconductor wafer to produce semiconductor device chips with at least one charge carrier storage region
and with at least one front-sided cell region and at least one anode region and with a drift region.

US Pat. No. 9,443,972

SEMICONDUCTOR DEVICE WITH FIELD ELECTRODE

Infineon Technologies Aus...

1. A method of producing a semiconductor device, the method comprising:
providing a semiconductor body having a first surface and a dielectric layer arranged on the first surface;
forming at least one first trench in the dielectric layer, the at least one first trench extending to the semiconductor body
and defining a dielectric mesa region in the dielectric layer;

forming a second trench in the dielectric layer, distant to the at least one first trench, leaving portions of the dielectric
layer immediately adjacent the second trench in the dielectric mesa region, wherein the second trench is formed such that
a bottom of the second trench is arranged within the dielectric layer;

forming a semiconductor layer in the at least one first trench, on regions of the semiconductor body that are not covered
by the dielectric layer in the at least one first trench; and

forming a field electrode in the second trench.

US Pat. No. 9,318,446

METAL DEPOSITION ON SUBSTRATES

Infineon Technologies Aus...

11. A device comprising:
a semiconductor wafer;
an isolation layer substantially limited to a peripheral region of the semiconductor wafer; and
a metal layer over a side of the semiconductor wafer, the metal layer being at least partially adjacent the isolation layer.

US Pat. No. 9,291,653

SYSTEM AND METHOD FOR A PHASE DETECTOR

Infineon Technologies Aus...

1. A method of detecting a phase difference between a first signal and a second signal, the method comprising:
latching, using a first gated latch circuit, a state of the first signal using the second signal as a clock to produce a first
latched signal, wherein the first gated latch circuit is transparent when the second signal is asserted, and the first gated
latch circuit stores a value of the first signal when the second signal is not asserted;

latching, using a second gated latch circuit, a state of the second signal using the first signal as a clock to produce a
second latched signal, wherein the second gated latch circuit is transparent when the first signal is asserted, and the second
gated latch circuit stores a value of the second signal when the first signal is not asserted; and

summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading
or lagging the second signal.

US Pat. No. 9,112,022

SUPER JUNCTION STRUCTURE HAVING A THICKNESS OF FIRST AND SECOND SEMICONDUCTOR REGIONS WHICH GRADUALLY CHANGES FROM A TRANSISTOR AREA INTO A TERMINATION AREA

INFINEON TECHNOLOGIES AUS...

1. A super junction semiconductor device, comprising:
a super junction structure including first and second areas alternately arranged along a first lateral direction and extending
in parallel along a second lateral direction; each one of the first areas includes a first semiconductor region of a first
conductivity type; each one of the second areas includes, along the first lateral direction, an inner area between opposite
second semiconductor regions of a second conductivity type opposite to the first conductivity type; and wherein

a width w1 of the first semiconductor region in a transistor cell area is greater than in an edge termination area, and a width w2 of each one of the second semiconductor regions in the transistor cell area is greater than in the edge termination area.

US Pat. No. 9,048,091

METHOD AND SUBSTRATE FOR THICK III-N EPITAXY

Infineon Technologies Aus...

1. A method of manufacturing an III-N substrate, the method comprising:
bonding a Si substrate to a support substrate, the Si substrate having a (111) growth surface facing away from the support
substrate;

thinning the Si substrate at the (111) growth surface to a thickness of 100 ?m or less; and
forming III-N material on the (111) growth surface of the Si substrate after the Si substrate is thinned,
wherein the support substrate has a coefficient of thermal expansion more closely matched to that of the III-N material than
the Si substrate.

US Pat. No. 9,450,055

OPERATIONAL GALLIUM NITRIDE DEVICES

Infineon Technologies Aus...

1. A power circuit comprising:
two or more input terminals that are each directly coupled to a source that is configured to produce power for a load;
two or more output terminals that are each directly coupled to the load;
a semiconductor body, the semiconductor body comprising:
a common substrate; and
a Gallium Nitride (GaN) based substrate including one or more GaN devices adjacent to a front side of the common substrate,
wherein the one or more GaN devices comprise one or more gate terminals configured to receive a gate control signal from one
or more drivers and one or more load terminals; and

a node electrically coupled to a back side of the common substrate, wherein the node is connected to a constant potential
that is equal to or more negative than a lowest potential at the two or more output terminals of the power circuit.

US Pat. No. 9,349,680

CHIP ARRANGEMENT AND METHOD OF MANUFACTURING THE SAME

Infineon Technologies Aus...

1. A chip arrangement comprising:
a carrier; and
at least two chips arranged over the carrier each chip comprising a top surface, a bottom surface and a lateral sidewall extending
therebetween;

wherein a continuous insulating layer is arranged between the carrier and at least one of the at least two chips, and further
vertically extends between the lateral sidewalls of the at least two chips.

US Pat. No. 9,305,917

HIGH ELECTRON MOBILITY TRANSISTOR WITH RC NETWORK INTEGRATED INTO GATE STRUCTURE

Infineon Technologies Aus...

1. A high electron mobility transistor, comprising:
a buffer region;
a barrier region adjoining and extending along the buffer region, the buffer and barrier regions being formed from semiconductor
materials having different band-gaps such that an electrically conductive channel comprising a two-dimensional charge carrier
gas arises at an interface between the buffer and barrier regions due to piezoelectric effects; and

a gate structure being configured to control a conduction state of the channel, the gate structure comprising an electrically
conductive gate electrode, a first doped semiconductor region, a second doped semiconductor region, and a resistor,

wherein the first doped semiconductor region is in direct electrical contact with a first section of the gate electrode;
wherein the second doped semiconductor region is in direct electrical contact with a second section of the gate electrode,
wherein the first and second doped semiconductor regions have opposite conductivity types and form a p-n junction with one
another, and

wherein the first and second sections of the gate electrode are electrically coupled to one another by the resistor.

US Pat. No. 9,219,143

SEMICONDUCTOR DEVICE AND SUPER JUNCTION SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR MESAS

Infineon Technologies Aus...

1. A semiconductor device, comprising:
semiconductor mesas of a first conductivity type extending between a first surface and a bottom plane of a semiconductor portion;
and

a semiconductor structure of a second, complementary conductivity type extending along sidewalls of the semiconductor mesas
and outwardly from the semiconductor mesas,

wherein a thickness of the semiconductor structure has a local maximum value at a first distance to both the first surface
and the bottom plane.

US Pat. No. 9,059,637

SYSTEM AND METHOD FOR CALIBRATING A POWER SUPPLY

Infineon Technologies Aus...

1. A method of calibrating a power supply, wherein the method comprises:
coupling a reference load to an output of the power supply;
setting an output voltage of the power supply to a first output voltage;
measuring a current delivered to the reference load;
determining a second derivative of the measured current with respect to the output voltage of the power supply;
increasing the output voltage of the power supply until the second derivative crosses a first threshold, wherein the determined
second derivative crosses the first threshold when the output of the power supply is at a second output voltage; and

setting the power supply to operate at the second output voltage.

US Pat. No. 9,054,182

SEMICONDUCTOR DEVICE WITH FIELD ELECTRODE AND METHOD

Infineon Technologies Aus...

2. A method for producing a controllable semiconductor device comprising:
providing a semiconductor body;
forming a first trench system comprising a plurality of longish segments each of which extends in a first lateral direction
and run substantially parallel to one another;

filling the first trench system at least partially with a first conductive material to form a first plurality of longish segments
which are permanently electrically connected to one another and form a single field electrode;

forming a second trench system comprising a plurality of longish segments each of which extend in a second lateral direction
and run substantially parallel to one another, wherein the second lateral direction runs non-parallel to the first lateral
direction; and

filling the second trench system at least partially with a second conductive material to form a second plurality longish segments
which are permanently electrically connected to one another to form a single control electrode.

US Pat. No. 9,484,400

METHOD OF FORMING A SUPER JUNCTION SEMICONDUCTOR DEVICE HAVING STRIPE-SHAPED REGIONS OF THE OPPOSITE CONDUCTIVITY TYPES

Infineon Technologies Aus...

1. A method of forming a super junction semiconductor device, the method comprising:
forming at least a portion of a drift layer on a doped layer of a first conductivity type;
implanting first dopants of a first conductivity type and second dopants of a second conductivity type into the drift layer
using one or more implant masks with openings to form stripe-shaped first implant regions of the first conductivity type,
stripe-shaped second implant regions of the second conductivity type in alternating order and a circumferential implant zone
of the first conductivity type that encloses the stripe-shaped first and second regions, wherein the stripe-shaped second
implant regions are separated from the stripe-shaped first implant regions and from the circumferential implant zone at uniform
distances;

performing a heat treatment for controlling a diffusion of dopants from the implant regions to form stripe-shaped first regions
of the first conductivity type and stripe-shaped second regions of the second conductivity type.

US Pat. No. 9,406,550

INSULATION STRUCTURE FORMED IN A SEMICONDUCTOR SUBSTRATE AND METHOD FOR FORMING AN INSULATION STRUCTURE

Infineon Technologies Aus...

1. A method, comprising:
forming a trench in a semiconductor fin, the semiconductor fin comprising active regions of at least two semiconductor devices,
the trench extending from a first surface into the semiconductor fin, the trench having a first width in a horizontal direction
of the semiconductor fin; and

forming a void spaced apart from the first surface in a vertical direction of the semiconductor fin, the void having a second
width in a horizontal direction that is greater than the first width,

wherein the trench and the void are arranged adjacent to each other in the vertical direction,
wherein the trench and the void form an insulation structure that dielectrically insulates the active regions of neighboring
semiconductor devices of the semiconductor fin.

US Pat. No. 9,184,277

SUPER JUNCTION SEMICONDUCTOR DEVICE COMPRISING A CELL AREA AND AN EDGE AREA

Infineon Technologies Aus...

1. A super junction semiconductor device, comprising:
one or more doped zones formed in a cell area;
a doped layer of a first conductivity type; and
a drift layer arranged in a vertical direction between the doped layer and the one or more doped zones, the drift layer comprising
first regions of the first conductivity type and second regions of a second conductivity type opposite to the first conductivity
type; wherein

portions of the first and second regions in the cell area are stripe-shaped and extend from one side of the cell area to an
opposite side of the cell area,

in an edge area surrounding the cell area the first regions include first portions separating the second regions in a first
direction and second portions separating the second regions in a second direction orthogonal to the first direction, wherein
the first and second directions are both lateral directions, perpendicular to the vertical direction, the second regions in
the edge area are separated from the second regions in the cell area, and the first and second portions are arranged such
that a longest second region in the edge area is at most half as long as a longest one of the second regions in the cell area;
and

a coupling element between at least one of the second regions of the cell area and at least one of the second regions of the
edge area,

wherein the coupling element is controllable and operable to electrically couple the at least one of the second regions of
the cell area and the one of the second regions of the edge area in a first state and to electrically decouple them in a second
state.

US Pat. No. 9,110,480

VOLTAGE RAMP CIRCUITRY AND VOLTAGE RAMP METHODS FOR VOLTAGE REGULATORS

Infineon Technologies Aus...

1. A method of adjusting a voltage, comprising:
producing a voltage ramp starting at a first voltage and ending at a second voltage;
compensating the voltage ramp according to a compensation parameter, wherein the compensation parameter is configured to compensate
for a circuit parameter;

outputting a voltage according to the compensated voltage ramp; and
compensating the voltage ramp for a second compensation parameter,
wherein at least one of:
the first compensation parameter is applied and substantially optimized for a positively-sloped voltage ramp and the second
compensation parameter is substantially optimized for a negatively-sloped voltage ramp; and

the first compensation parameter corresponds to an output capacitor equivalent series resistance voltage drop and the second
circuit parameter corresponds to an output capacitor current.

US Pat. No. 9,356,118

METALIZATION OF A FIELD EFFECT POWER TRANSISTOR

Infineon Technologies Aus...

1. A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically
conducting or doped semiconductor substrate, wherein the lateral semiconductor layers have different band gaps such that a
two-dimensional electron gas can form in a semiconductor depletion layer of each lateral semiconductor layer, wherein the
two-dimensional electron gas can flow between source electrode contact areas and drain electrode contact areas upon application
of a voltage between source and drain through the lateral semiconductor depletion layers, wherein current intensity in a channel
region between the source electrode contact areas and the drain electrode contact areas is controllable via gate electrode
contact areas by means of a gate voltage, wherein a metalization of the source electrode contact areas, a metalization of
the drain electrode contact areas and a metalization of the gate electrode contact areas are on a semiconductor surface of
the semiconductor layers and have a plurality of metalization layers, between which insulation layers are arranged in a lateral
direction, wherein the metalization layers both for the source electrode metalization and for the drain electrode metalization
have a comb structure with contact fingers, wherein the contact fingers of the source electrode metalization and of the drain
electrode metalization intermesh in a spaced-apart fashion and each contact finger has a contact finger foot and a contact
finger tip, wherein a width of the contact finger foot is greater than a width of the contact finger tip.

US Pat. No. 9,338,849

SPATIAL INTENSITY DISTRIBUTION CONTROLLED FLASH

Infineon Technologies Aus...

1. A camera device, comprising:
a flash module that includes an LED matrix comprising a plurality of LED elements; and
an LED control unit that:
determines a spatial intensity distribution of light to be output by the LED matrix; and
controls the LED matrix to output light with the determined spatial intensity distribution in a substantially instantaneous
burst of light to illuminate one or more objects by causing at least a first LED element of the LED matrix to output light
of a first intensity, and causing at least a second LED element of the LED matrix to output light of a second intensity different
than the first intensity,

wherein:
the device determines a first distance between the device and a first object to be captured in an image and a second distance
between the device and a second object to be captured in the image; and

in response to the device determining the first and second distances, the LED control unit causes at least a first LED element
of the LED matrix to output the light of the first intensity to illuminate the first object at a first location at the first
distance from the device,

wherein the LED control unit causes at least a second LED element of the LED matrix to output light of a second intensity
to illuminate the second object at a second location different than the first location at the second distance from the device,
and

wherein the light from at least the first LED element illuminates the first object at the first location simultaneously with
the light from at least the second LED element illuminating the second object at the second location.

US Pat. No. 9,209,793

BOOTSTRAP CIRCUITRY FOR AN IGBT

Infineon Technologies Aus...

1. A bootstrap circuit for providing a drive voltage to a high-side transistor of a half-bridge arrangement, the bootstrap
circuit comprising a buck-boost circuit configured to provide a negative drive voltage for turning the high-side transistor
off via a negative supply node, wherein the buck-boost circuit comprises a first capacitor coupled between an output node
of the half-bridge arrangement and the negative supply node, an inductor having a first terminal coupled to the output node
of the half-bridge arrangement, and a diode coupled between a second terminal of the inductor and the negative supply node.

US Pat. No. 9,134,743

LOW-DROPOUT VOLTAGE REGULATOR

Infineon Technologies Aus...

13. A low-dropout voltage regulator comprising:
a power transistor configured to receive an input voltage and to provide a regulated output voltage at an output voltage node,
the power transistor comprising a control electrode configured to receive a driver signal;

a reference circuit configured to generate a reference voltage;
a feedback network coupled to the power transistor and configured to provide a first feedback signal and a second feedback
signal, the first feedback signal representing the output voltage and the second feedback signal representing an output voltage
gradient; and

an error amplifier configured to receive the reference voltage and the first feedback signal representing the output voltage,
the error amplifier configured to generate the driver signal dependent on the reference voltage and the first feedback signal,
wherein the error amplifier comprises an output stage which is biased with a bias current responsive to the second feedback
signal, and wherein the bias current is configured to be set using a current mirror that receives, as input current, a reference
current and that provides, as output current, the bias current, which is responsive to the reference current, wherein:

the current minor comprises an input transistor receiving the reference current and an output transistor providing the bias
current, the input and the output transistors having control terminals for controlling current flow through the respective
transistor;

the control terminal of the input transistor is coupled to the output voltage node via a capacitor; and
the control terminal of the input transistor and the control terminal of the output transistor are coupled via a resistor.

US Pat. No. 9,112,053

METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE INCLUDING A DIELECTRIC LAYER

Infineon Technologies Aus...

1. A method for producing a semiconductor device with a dielectric layer, the method comprising:
providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom
and a sidewall;

forming a first dielectric layer on the sidewall in a lower portion of the first trench;
forming a first plug in the lower portion of the first trench so as to cover the first dielectric layer, the first plug leaving
an upper portion of the sidewall uncovered;

forming a sacrificial layer on the sidewall in the upper portion of the first trench;
forming a second plug in the upper portion of the first trench;
removing the sacrificial layer, so as to form a second trench having sidewalls and a bottom;
forming a second dielectric layer in the second trench and extending to the first dielectric layer; and
forming a source region and a body region in the second plug.

US Pat. No. 9,054,515

CURRENT MEASUREMENT AND OVERCURRENT DETECTION

Infineon Technologies Aus...

1. A system comprising:
an isolation device that includes an electrical conductor and a current sensor, wherein the current sensor is configured to
output a signal indicative of an amount of current flowing through the electrical conductor; and

a current diagnostic circuit configured to:
determine a voltage level across the electrical conductor of the isolation device; and
determine a supplemental measurement of an amount of current flowing through the electrical conductor based on the determined
voltage, wherein the supplemental measurement is supplemental to a measurement of the amount of current flowing through the
electrical conductor determined using the sensor of the isolation device.

US Pat. No. 9,322,858

SYSTEM AND METHOD FOR A PHASE DETECTOR

Infineon Technologies Aus...

1. A method of detecting a phase difference between a first signal and a second signal, the method comprising:
latching, using a first gated latch circuit, a state of the first signal using the second signal as a clock to produce a first
latched signal, wherein the first gated latch circuit is transparent when the second signal is asserted, and the first gated
latch circuit stores a value of the first signal when the second signal is not asserted;

latching, using a second gated latch circuit, a state of the second signal using the first signal as a clock to produce a
second latched signal, wherein the second gated latch circuit is transparent when the first signal is asserted, and the second
gated latch circuit stores a value of the second signal when the first signal is not asserted; and

summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading
or lagging the second signal.

US Pat. No. 9,171,787

PACKAGED SEMICONDUCTOR DEVICE HAVING AN EMBEDDED SYSTEM

Infineon Technologies Aus...

1. A packaged device, comprising:
a carrier comprising a first carrier contact;
a first electrical component, the first electrical component having a first top surface and a first bottom surface, the first
electrical component comprising a first component contact disposed on the first top surface, the first bottom surface being
connected to the carrier;

an embedded system comprising a second electrical component, an interconnect element, and a first connecting element, the
embedded system having a system bottom surface, wherein the system bottom surface comprises a first system contact, and the
second electrical component having a second top surface, wherein the second top surface comprises a first component contact,
wherein

the first system contact is connected to the first component contact by the interconnect element and the first component contact
of the second electrical component is connected to the first carrier contact by means of the first connecting element.

US Pat. No. 9,277,606

PROPAGATION DELAY COMPENSATION FOR FLOATING BUCK LIGHT EMITTING DIODE (LED) DRIVER

Infineon Technologies Aus...

1. A device configured to control a semiconductor light source, the device comprising:
a peak detector;
a variable gain amplifier coupled to the peak detector and configured to amplify an output of the peak detector; and
a gain selector, coupled to the variable gain amplifier and configured to control the variable gain amplifier by varying the
gain of the variable gain amplifier based on an on time of a signal.

US Pat. No. 10,566,260

SMD PACKAGE WITH TOP SIDE COOLING

Infineon Technologies Aus...

1. A package enclosing a power semiconductor die, the package having a package body with a package top side, a package footprint side and package sidewalls, the package sidewalls extending from the package footprint side to the package top side, wherein the die has a first load terminal and a second load terminal and is configured to block a blocking voltage applied between said load terminals, wherein the package comprises:a lead frame structure configured to electrically and mechanically couple the package to a support with the package footprint side facing to the support, the lead frame structure comprising at least one first outside terminal extending out of one of the package sidewalls and electrically connected with the first load terminal of the die;
a top layer arranged at the package top side and being electrically connected with the second load terminal of the die; and
a heat spreader arranged external of the package body and in electrical contact with the top layer, with a bottom surface of the heat spreader facing to the top layer,
wherein the heat spreader further has a top surface, an area of the top surface being greater than an area of the bottom surface,
wherein the package body is made of a molding mass,
wherein the molding mass spatially confines the top layer at the package top side.

US Pat. No. 9,166,000

POWER SEMICONDUCTOR DEVICE WITH AN EDGE TERMINATION REGION

Infineon Technologies Aus...

1. A power semiconductor device, comprising:
a semiconductor substrate;
an active device region disposed in the semiconductor substrate;
an edge termination region spaced laterally outward from the active device region in the semiconductor substrate;
a first trench disposed in the edge termination region and having an inner sidewall, an outer sidewall and a bottom, the inner
sidewall spaced closer to the active device region than the outer sidewall; and

a second trench spaced laterally outward from the first trench in the edge termination region, the second trench extending
further into the semiconductor substrate than the first trench and having a sidewall which outwardly faces the outer sidewall
of the first trench and is doped opposite as the inner sidewall and the bottom of the first trench.

US Pat. No. 9,082,746

METHOD FOR FORMING SELF-ALIGNED TRENCH CONTACTS OF SEMICONDUCTOR COMPONENTS AND A SEMICONDUCTOR COMPONENT

INFINEON TECHNOLOGIES AUS...

1. A method for producing a semiconductor component, comprising:
providing a semiconductor arrangement comprising: a semiconductor body comprising a first semiconductor material extending
to a first surface and at least one trench extending from the first surface, the at least one trench comprising a conductive
region insulated from the semiconductor body and arranged below the first surface;

forming a second insulation layer on the first surface comprising a recess that overlaps in a projection onto the first surface
with the conductive region;

forming a mask region in the recess; and
etching the second insulation layer selectively to the mask region and the semiconductor body to expose the semiconductor
body at the first surface;

depositing a third insulation layer on the first surface; and
etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the at least one
trench is exposed at the first surface.

US Pat. No. 9,437,548

CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME

INFINEON TECHNOLOGIES AUS...

1. A chip package comprising:
a metallic chip carrier;
at least one chip carried by the metallic chip carrier;
encapsulation material encapsulating the at least one chip and the metallic chip carrier;
a first redistribution layer disposed over the at least one chip over a side of the at least one chip facing away from the
metallic chip carrier;

a second redistribution layer disposed over the at least one chip over the side of the at least one chip facing away from
the metallic chip carrier and disposed over the first redistribution layer; and

at least one contact hole extending through the encapsulation material to electrically couple the at least one chip with the
first redistribution layer and/or the second redistribution layer;

wherein the second redistribution layer comprises a surface facing away from the at least one chip that is at least partially
exposed.

US Pat. No. 9,099,391

SEMICONDUCTOR PACKAGE WITH TOP-SIDE INSULATION LAYER

Infineon Technologies Aus...

1. A semiconductor package, comprising:
a base;
a die attached to the base;
a lead;
a connector electrically connecting the lead to the die;
a mold compound encapsulating the die, the connector, at least part of the base, and part of the lead so that the lead extends
outward from the mold compound; and

an electrical insulation layer separate from the mold compound and comprising a different material than the mold compound,
the electrical insulation layer being attached to a single side of the mold compound over the connector, the electrical insulation
layer having a fixed, defined thickness so that the package has a guaranteed minimum spacing between an apex of the connector
and a surface of the electrical insulation layer facing away from the connector.

US Pat. No. 9,086,705

CHARGE RECOVERY IN POWER CONVERTER DRIVER STAGES

Infineon Technologies Aus...

1. A power converter, comprising:
a first transistor operable to source current to a load when switched on;
a second transistor operable to freewheel inductor current or sink current from the load when switched on; and
a driver circuit operable to switch the first transistor on and the second transistor off during a first period, switch the
first transistor off and the second transistor on during a third period after the first period, and connect a gate of the
first transistor to a gate of the second transistor during a second period between the first and third periods when the gates
of the first and second transistors are floating.

US Pat. No. 9,076,763

HIGH BREAKDOWN VOLTAGE III-NITRIDE DEVICE

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a semiconductor body including a compound semiconductor material on a substrate, the compound semiconductor material having
a channel region;

a source region extending to the compound semiconductor material;
a drain region extending to the compound semiconductor material and spaced apart from the source region by the channel region;
and

an insulating region buried in the semiconductor body below the channel region between the compound semiconductor material
and the substrate in an active region of the semiconductor device such that the channel region is uninterrupted by the insulating
region, the active region including the source, the drain and the channel region, the insulating region being discontinuous
over a length of the channel region between the source region and the drain region.

US Pat. No. 9,501,075

LOW-DROPOUT VOLTAGE REGULATOR

Infineon Technologies Aus...

1. A method of operating a low-dropout voltage regulator, the method comprising:
receiving a first feedback signal at a feedback network from a transistor coupled to an output of the low-dropout voltage
regulator, the first feedback signal representing an output voltage at the output;

generating a second feedback signal at the feedback network, the second feedback signal comprising a time derivative of the
output voltage;

receiving a reference voltage and the first feedback signal at an error amplifier;
generating, at the error amplifier, a drive signal for the transistor dependent on the reference voltage and the first feedback
signal; and

biasing an output stage of the error amplifier with a bias current proportional to the second feedback signal.

US Pat. No. 9,449,847

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE BY THERMAL TREATMENT WITH HYDROGEN

Infineon Technologies Aus...

1. A method of manufacturing a semiconductor device, comprising:
forming semiconductor elements extending between a front surface and a rear side of a semiconductor layer by:
forming a porous area at a surface of a semiconductor body, wherein the semiconductor body includes a porous structure in
the porous area;

forming the semiconductor layer on the porous area by epitaxial growth so as to have a thickness in a range of 5 ?m to 200
?m;

forming semiconductor regions including source, drain, body, emitter, base and/or collector regions in a front surface of
the semiconductor layer by ion implantation, wherein the front surface of the semiconductor layer corresponds to a front side
of the semiconductor device;

introducing, after forming the semiconductor regions, hydrogen into the porous area by a thermal treatment, thereby activating
a reallocation of pores and causing cavities to be generated, so that the semiconductor layer with the semiconductor regions
is separated from the semiconductor body along the porous area; and

applying, after separation of the semiconductor layer, rear side processing to the semiconductor layer, wherein a rear side
of the semiconductor layer corresponds to a rear side of the semiconductor device,

wherein the rear side processing comprises ion implantation.

US Pat. No. 9,437,516

CHIP-EMBEDDED PACKAGES WITH BACKSIDE DIE CONNECTION

Infineon Technologies Aus...

20. A semiconductor package, comprising:
a semiconductor die embedded in an insulating material, the die having opposing first and second surfaces and an edge extending
between the first and second surfaces;

a structured metal redistribution layer disposed in the insulating material below the die;
a first metal component embedded in the insulating material above the die and bonded to the second surface of the die, part
of the first metal component extending laterally beyond the edge of the die; and

a second metal component disposed under and connected to the part of the first metal component that extends laterally beyond
the edge of the die, the second metal component vertically extending through the insulating material so that part of the second
metal component is uncovered by the insulating material at a side of the package facing away from the second surface of the
die,

wherein the first and second metal components form at least a thermal pathway from the second surface of the die to the side
of the package facing away from the second surface of the die.

US Pat. No. 9,349,792

SUPER JUNCTION SEMICONDUCTOR DEVICE HAVING COLUMNAR SUPER JUNCTION REGIONS

Infineon Technologies Aus...

1. A super junction semiconductor device, comprising:
a semiconductor portion with a first surface and a second surface parallel to the first surface, and comprising a doped layer
of a first conductivity type formed at least in a cell area; and

columnar first super junction regions of a second, opposite conductivity type extending in a direction perpendicular to the
first surface and separated by columnar second super junction regions of the first conductivity type, the first and second
super junction regions forming a super junction structure between the first surface and the doped layer, wherein a distance
between the first super junction regions and the second surface does not exceed 30 ?m.

US Pat. No. 9,337,279

GROUP III-NITRIDE-BASED ENHANCEMENT MODE TRANSISTOR

Infineon Technologies Aus...

1. A Group III-nitride-based enhancement mode transistor, comprising:
a multi-heterojunction fin structure, wherein a first side face of the multi-heterojunction fin structure is covered by a
p-type Group III-nitride layer;

an insulated gate electrode arranged on a second side face of the multi-heterojunction fin structure; and
a depletion electrode arranged on the p-type Group III-nitride layer.

US Pat. No. 9,306,064

SEMICONDUCTOR DEVICE AND INTEGRATED APPARATUS COMPRISING THE SAME

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a substrate;
a buffer layer on the substrate;
a compensation area which comprises a p-region and a n-region each on and contacting the buffer layer; and
a transistor cell on the compensation area, the transistor cell comprising a source region, a body region, a gate electrode
and a gate dielectric formed at least between the gate electrode and the body region,

wherein the gate dielectric has a thickness in a range of 12 nm to 50 nm.

US Pat. No. 9,166,005

SEMICONDUCTOR DEVICE WITH CHARGE COMPENSATION STRUCTURE

Infineon Technologies Aus...

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor body having a main surface and comprising a compensated silicon semiconductor layer extending to
the main surface, and a substantially intrinsic compound semiconductor region comprising silicon and germanium and extending
at least partially through the compensated silicon semiconductor layer, an integrated concentration of n-type dopants of the
compensated silicon semiconductor layer being substantially equal to an integrated concentration of p-type dopants of the
compensated silicon semiconductor layer; and

diffusing more n-type dopants than p-type dopants from the compensated silicon semiconductor layer into the substantially
intrinsic compound semiconductor region to form a compound semiconductor drift region of the semiconductor device, the compound
semiconductor drift region having a larger integrated concentration of n-type dopants than p-type dopants, in a cross-section
substantially orthogonal to the main surface the compound semiconductor drift region at least substantially filling a vertical
trench extending from the main surface at least partially through the compensated silicon semiconductor layer.

US Pat. No. 9,147,763

CHARGE-COMPENSATION SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A semiconductor device, comprising a semiconductor body comprising a main horizontal surface, an active area, a punch through
area, a source metallization arranged on the main horizontal surface and a drain metallization, in the active area the semiconductor
body further comprising in a vertical cross-section substantially orthogonal to the main horizontal surface:
a first charge-compensation structure comprising a plurality of spaced apart first n-type pillar regions; and
an n-type first field-stop region comprised of a semiconductor material, in Ohmic contact with the drain metallization and
the first n-type pillar regions, and having a doping concentration per area higher than a breakdown charge per area of the
semiconductor material divided by the elementary charge,
in the punch-through area the semiconductor body further comprising:
a p-type semiconductor region in Ohmic contact with the source metallization;
a floating p-type body region extending from the punch-through area into the active area; and
an n-type second field-stop region in Ohmic contact with the first field-stop region, forming a pn-junction with the floating
p-type body region, arranged between the p-type semiconductor region and the floating p-type body region, and having a doping
concentration per area lower than the breakdown charge per area of the semiconductor material divided by the elementary charge.

US Pat. No. 9,123,735

SEMICONDUCTOR DEVICE WITH COMBINED PASSIVE DEVICE ON CHIP BACK SIDE

Infineon Technologies Aus...

1. A semiconductor chip comprising:
a substrate including a first side and a second side, wherein the second side is opposite the first side;
a semiconductor device formed on the first side of the substrate;
an electrically insulating layer formed on at least a portion of the second side of the substrate;
a passive device formed on at least a portion of the electrically insulating layer on the second side of the substrate, wherein
the passive device is electrically insulated from the semiconductor device; and

a chip carrier including a first portion and a second portion, wherein the first portion is electrically isolated from the
second portion, and wherein the chip carrier comprises an electrically conductive material.

US Pat. No. 9,082,813

POWER DEVICE AND A REVERSE CONDUCTING POWER IGBT

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a semiconductor body comprising a base region of a first conductivity type and a main horizontal surface;
a first electrode arranged on the main horizontal surface;
the semiconductor body further comprising, in a vertical cross-section:
a first vertical trench comprising a first gate electrode insulated by a gate dielectric region from the base region;
a second vertical trench comprising a second gate electrode insulated by a gate dielectric region from the base region;
a third vertical trench comprising a third gate electrode insulated by a gate dielectric region from the base region;
a body region of a second conductivity type forming a first pn-junction with the base region and extending between the first
vertical trench and the second vertical trench;

at least one source region of the first conductivity type in ohmic contact with the first electrode and arranged between the
first vertical trench and the second vertical trench;

at least one anti-latch-up region of the second conductivity type arranged between the first vertical trench and the second
vertical trench and in ohmic contact with the first electrode and having a maximum doping concentration which is higher than
a maximum doping concentration of the body region;

an anode region of the second conductivity type forming a rectifying pn-junction with the base region only and adjoining the
third vertical trench, wherein the anode region is in ohmic contact with the first electrode;

a second electrode arranged opposite the first electrode and in ohmic contact with the base region;
a collector region of the second conductivity type in ohmic contact with the second electrode; and
at least two floating semiconductor regions of the second conductivity type arranged between the second vertical trench and
the third vertical trench and at least one fifth vertical trench arranged between two of the at least two floating semiconductor
regions of the second conductivity type, the at least one fifth vertical trench comprising a fifth gate electrode insulated
by a gate dielectric region from the semiconductor body,

wherein the anode region is arranged between the third vertical trench and a fourth vertical trench, the fourth vertical trench
comprising a fourth gate electrode insulated by a gate dielectric region from the anode region.

US Pat. No. 9,443,798

PASSIVE COMPONENT AS THERMAL CAPACITANCE AND HEAT SINK

Infineon Technologies Aus...

1. A system, comprising:
a printed circuit board (PCB) including at least a first layer and a second layer;
a chip die disposed between the first layer and the second layer; and
a passive component strategically located on an outer surface of one of the first layer or the second layer, and arranged
to conduct heat generated by the chip die away from the chip die, the passive component overlapping a portion of the chip
die.

US Pat. No. 9,397,636

SYSTEM AND METHOD FOR DRIVING TRANSISTORS

Infineon Technologies Aus...

1. A circuit comprising:
a first power switch and a second power switch connected in series and configured to be coupled between a high voltage load
and a reference node;

a controller configured to regulate an output voltage of the high voltage load by providing switching signals to the first
power switch; and

a control circuit configured to maintain the second power switch in a conducting state when the first power switch is off
and to divide a blocking voltage across the first power switch and the second power switch by adjusting conduction resistance
of the second power switch when the first power switch is off.

US Pat. No. 9,349,795

SEMICONDUCTOR SWITCHING DEVICE WITH DIFFERENT LOCAL THRESHOLD VOLTAGE

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a semiconductor substrate comprising a plurality of switchable cells defining an active area of the semiconductor device,
an outer rim, and an edge termination region arranged between the switchable cells and the outer rim, each of the switchable
cells comprising a body region, a gate electrode structure and a source region; a source metallization in ohmic contact with
the respective source region of the switchable cells; and a gate metallization in ohmic contact with the respective gate electrode
structure of the switchable cells;

wherein the active area defined by the switchable cells comprises at least a first switchable region and at least a second
switchable region, wherein the switchable cells of the first switchable region have a first threshold voltage, and wherein
the switchable cells of the second switchable region have a second threshold voltage which is higher than the first threshold
voltage, and wherein an area occupied by the first switchable region is larger than an area occupied by the second switchable
region.

US Pat. No. 9,343,588

NORMALLY-OFF SEMICONDUCTOR SWITCHES AND NORMALLY-OFF JFETS

Infineon Technologies Aus...

1. A normally-off JFET, comprising:
a channel region of a first conductivity type;
a floating semiconductor region of a second conductivity type adjoining the channel region;
a contact region of the first conductivity type adjoining the floating semiconductor region; and
wherein the floating semiconductor region is arranged between the contact region and the channel region;
wherein a first pn-junction having a first specific depletion capacitance is formed between the channel region and the floating
semiconductor region; and

wherein a second pn-junction having a second specific depletion capacitance larger than the first depletion capacitance is
formed between the contact region and the floating semiconductor region.

US Pat. No. 9,974,190

SYSTEM AND METHOD OF PROVIDING A SEMICONDUCTOR CARRIER AND REDISTRIBUTION STRUCTURE

Infineon Technologies Aus...

19. A system, comprising:an electronic component comprising a power semiconductor device and a dielectric core layer, the power semiconductor device embedded in the dielectric core layer;
a first carrier comprising at least one contact arranged in a peripheral region which is coupleable to a first major surface of a circuit board;
a second carrier; and
at least one contact on a second major surface of the dielectric core layer which is electrically couplable to the first major surface of the circuit board by way of a redistribution of the first carrier,
wherein the electronic component is arranged on the first carrier and is positionable in a through-hole in a circuit board by way of a connection between the first carrier and the circuit board such that the electronic component is spaced from and not making contact with side faces of the through-hole and embedded in the circuit board and wherein the second carrier is sized and shaped to cover the through-hole and the electronic component when arranged on a second major surface of the circuit board.

US Pat. No. 9,443,787

ELECTRONIC COMPONENT AND METHOD

Infineon Technologies Aus...

1. An electronic component, comprising:
a high-voltage depletion-mode transistor;
a low-voltage enhancement-mode transistor arranged laterally adjacent and spaced apart from the high-voltage depletion-mode
transistor; and

an electrically conductive member electrically coupling a first current electrode of the high-voltage depletion-mode transistor
to a first current electrode of the low-voltage enhancement-mode transistor, the electrically conductive member having a sheet-like
form,

wherein the high-voltage depletion-mode transistor comprises a first side comprising the first current electrode, a second
current electrode and a control electrode,

wherein the low-voltage enhancement-mode transistor comprises a first side comprising a second current electrode and a control
electrode and a second side opposing the first side, the second side comprising the first current electrode of the low-voltage
enhancement-mode transistor,

wherein the electrically conductive member extends between the first current electrode of the high-voltage depletion-node
transistor and the first current electrode of the low-voltage enhancement-mode transistor, and

wherein the second current electrode of the low-voltage enhancement-mode transistor is mounted on a die pad and the control
electrode of the low-voltage enhancement-mode transistor is mounted on a lead spaced at a distance from the die pad.

US Pat. No. 9,425,090

METHOD OF ELECTRODEPOSITING GOLD ON A COPPER SEED LAYER TO FORM A GOLD METALLIZATION STRUCTURE

Infineon Technologies Aus...

1. A method of forming a metallization for electrically connecting one or more semiconductor devices, the method comprising;
forming an electrically conductive barrier layer on a semiconductor substrate such that the barrier layer covers a first terminal
of a device formed in the substrate;

forming a seed layer on the barrier layer, the seed layer extending over the first terminal and comprising a noble metal other
than gold;

masking the substrate with a mask having a first opening that is laterally aligned with the first terminal such that an unmasked
portion of the seed layer is exposed by the first opening and such that a masked portion of the seed layer is covered by the
mask,

electroplating the unmasked portion of the seed layer using a gold electrolyte solution so as to form a first gold metallization
structure arranged in the first mask opening;

removing the mask;
removing the masked portions of the seed layer and the barrier layer; and
diffusing the noble metal from the unmasked portion of the seed layer into the first gold metallization structure,
wherein the first gold metallization structure is electrically connected to the first terminal via the barrier layer, and
wherein diffusing the noble metal comprises diffusing all metallic state noble metal from the unmasked portion of the seed
layer into the first gold metallization structure such that gold from the first gold metallization structure directly contacts
the barrier layer.

US Pat. No. 9,379,691

RUNTIME COMPENSATED OSCILLATOR

INFINEON TECHNOLOGIES AUS...

1. A method of generating a periodic signal comprising:
detecting when a charging state of a storage element crosses a first threshold, detecting comprising using a first circuit
having a first propagation delay;

changing a charging state of a storage element at a first rate until the charging state crosses the first threshold at a first
time based on the detecting;

preserving the charging state of the storage element;
after the preserving the charging state, continuing changing the charging state at the first rate upon receipt of a first
clock edge indicating a beginning of a first time interval;

detecting when a charging state of the storage element crosses a second threshold, detecting comprising using the first circuit
having the first propagation delay; and

ending the first time interval when the charging state crosses the second threshold at a second time based on the detecting.

US Pat. No. 9,245,684

METHOD FOR MANUFACTURING A TRANSFORMER DEVICE ON A GLASS SUBSTRATE

Infineon Technologies Aus...

1. A method for manufacturing a transformer device, comprising:
providing a glass substrate having a first side and a second side arranged opposite the first side;
forming a first recess in the glass substrate at the first side of the glass substrate;
forming a second recess in the glass substrate at the second side of the glass substrate opposite to the first recess;
forming a first coil in the first recess; and
forming a second coil in the second recess.

US Pat. No. 9,225,327

BURST DETECTION FOR LINES TO REMOTE DEVICES

Infineon Technologies Aus...

1. An apparatus, comprising:
an output to be coupled with a remote device via a line in an industrial environment;
a control device coupled with said output and being configured to control said remote device via said line;
a burst detector coupled with said output to detect bursts on said line; and
a switch device to couple said output with a reference potential in response to a burst being detected by said burst detector.

US Pat. No. 9,117,586

TRIMMABLE TRANSFORMER ARRANGEMENT

Infineon Technologies Aus...

1. A method for signal or power transmission through a circuit arrangement that comprises:
input terminals;
output terminals;
a coreless transformer having a first winding and a second winding;
a trimming device that is connected to one of the first and second windings and that includes at least one of a variable capacitive
component and/or a variable inductive component, the variable capacitive component having an adjustable capacitance and the
variable inductive component having an adjustable inductance;

the circuit arrangement having a maximum efficiency frequency (MEF) and a maximum impedance frequency (MIF) that are dependent
on a load connected to the output terminals, and on one of capacitance and inductance;

the method comprising:
applying an input signal that has an input frequency to the input terminals; and
adjusting one of the MEF and MIF of the circuit arrangement to differ from the input frequency by less than a given frequency
difference by adjusting at least one of the adjustable capacitance and the adjustable inductance.

US Pat. No. 9,425,622

POWER CONVERTER CIRCUIT WITH AC OUTPUT AND AT LEAST ONE TRANSFORMER

Infineon Technologies Aus...

1. A power converter circuit, comprising:
a synchronization circuit configured to generate at least one synchronization signal; and
a series circuit comprising a plurality of converter units configured to output an output current;
wherein a first converter unit of the plurality of converter units comprises a transformer and is configured to generate an
output current such that a frequency or a phase of the generated output current is dependent on the synchronization signal.

US Pat. No. 9,379,050

ELECTRONIC DEVICE

Infineon Technologies Aus...

1. An electronic device comprising:
exactly two horizontal transistor devices, the exactly two horizontal transistor devices including a first horizontal transistor
device and a second horizontal transistor device;

the first horizontal transistor device comprising first contact elements arranged on a first active main face, the first contact
elements comprising a first source contact element, a first drain contact element, and a first gate contact element, wherein
the first gate contact element is disposed near a lateral side edge of the first active main face;

the second horizontal transistor device comprising second contact elements arranged on a second active main face, the second
contact elements comprising a second source contact element, a second drain contact element, and a second gate contact element,
wherein the second gate contact element is disposed near a lateral side edge of the second active main face; and

an electrical connection member consisting of exactly five lead elements, each one of the five lead elements comprising a
first main face and a second main face opposite the first main face, the electrical connection member being interposed between
the first horizontal transistor device and the second horizontal transistor device,

wherein the first horizontal transistor device and the second horizontal transistor device are disposed relative to each other
so that the first active main face and the second active main face are facing each other, and that the first horizontal transistor
device and the second horizontal transistor device are laterally displaced from each other so that both of the first active
main face and the second active main face have central regions respectively lying directly opposite to each other and both
of the first active main face and the second active main face have laterally protruding regions respectively,

wherein the first drain contact element is disposed in the central region of the first active main face and directly facing
the second source contact element disposed in the central region of the second active main face,

wherein the first gate contact element is disposed in the laterally protruding region of the first active main face and the
second gate contact element is disposed in the laterally protruding region of the second active main face,

wherein the first source contact element is disposed in the laterally protruding region of the first active main face and
the second drain contact element is disposed in the laterally protruding region of the second active main face,

wherein a first lead element of the five lead elements is directly connected between the first drain contact element and the
second source contact element, the first drain contact element being attached to the first main face of the first lead element
and the second source contact element being attached to the second main face of the first lead element,

wherein a second lead element of the five lead elements is directly connected with the second drain contact element,
wherein a third lead element of the five lead elements is directly connected with the second gate contact element,
wherein a fourth lead element of the five lead elements is directly connected with the first source contact element,
wherein a fifth lead element of the five lead elements is directly connected with the first gate contact element,
wherein the five lead elements are arranged in a row and extend in parallel to each other in one direction and the third lead
element is located at one laterally outermost end of the row of lead elements and the fifth lead element is located at the
other laterally outermost end of the row of lead elements, and

wherein an encapsulation layer forms a lamination package embedding the first horizontal transistor device, the second horizontal
transistor device and respective parts of the five lead elements in such a way that respective end portions of the five lead
elements protrude outside the lamination package.

US Pat. No. 9,362,191

ENCAPSULATED SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a carrier;
a semiconductor chip disposed over the carrier, wherein the semiconductor chip has a first surface and a second surface opposite
to the first surface, and wherein the second surface faces the carrier;

an encapsulant covering at least partially the second surface of the semiconductor chip and at least partially a side wall
surface of the semiconductor chip, wherein the encapsulant comprises a thermal conductivity of equal to or greater than 10
W/(m·K) and a specific heat capacity of equal to or greater than 0.2 J/(g·K); and

an electrically insulating encapsulation material forming an encapsulation body covering at least partially the first surface
of the semiconductor chip and the encapsulant at the side wall surface of the semiconductor chip.

US Pat. No. 9,350,244

SWITCHING REGULATOR WITH INCREASED LIGHT LOAD EFFICIENCY IN PULSE FREQUENCY MODULATION MODE

Infineon Technologies Aus...

1. A switching regulator, comprising:
a multiphase buck converter comprising a plurality of main phases configured to covert a power supply voltage to a lower voltage
for application to an electronic device at different load conditions; and

an auxiliary phase configured to operate in a pulse frequency modulation mode during a light load condition so that power
is supplied to the electronic device by at least the auxiliary phase during the light load condition,

wherein the auxiliary phase and the plurality of main phases of the multiphase buck converter each comprise field effect transistors,
wherein the field effect transistors of the auxiliary phase are lower voltage transistors which occupy smaller physical area
than the field effect transistors of the main phases,

wherein the auxiliary phase and each of the plurality of main phases of the multiphase buck converter has an output coupled
to an inductor,

wherein the inductor coupled to the output of the auxiliary phase occupies less physical area and has a lower saturation current
than the inductors coupled to the outputs of the main phases.

US Pat. No. 9,356,148

FIN-TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a fin at a first side of a semiconductor body;
a body region of a second conductivity type in at least a part of the fin;
a drain extension region of a first conductivity type;
a source region and a drain region of the first conductivity type;
a source contact in contact with the source region; and
a gate structure adjoining opposing walls of the fin,
wherein the body region and the drain extension region are arranged one after another between the source region and the drain
region, the drain extension region having a larger width than the body region, the width being measured perpendicularly with
respect to a direction between the source region and the drain region.

US Pat. No. 9,484,816

CONTROLLABLE ON-TIME REDUCTION FOR SWITCHING VOLTAGE REGULATORS OPERATING IN PULSE FREQUENCY MODULATION MODE

Infineon Technologies Aus...

1. A method of controlling switching voltage regulator that includes a power stage for delivering output current to a load
through an inductor, the method comprising:
setting the power stage in a PFM (pulse frequency modulation) switching mode if the output current decreases below a first
threshold, each period of the PFM switching mode including an on-time during which a high-side transistor of the power stage
is on and a low-side transistor of the power stage is off, an off-time during which the low-side transistor is on and the
high-side transistor is off and a HiZ-time during which the high-side transistor and the low-side transistor are both off;
and

varying the on-time of the PFM switching mode responsive to a change in the output current, by:
increasing the on-time of a PFM pulse from the preceding PFM pulse if the time between the PFM pulses is shorter than a first
expected period: and

decreasing the on-time of the PFM pulse from the preceding PFM pulse if the time between the PFM pulses is longer than a second
expected period.

US Pat. No. 9,450,062

SEMICONDUCTOR DEVICE HAVING POLYSILICON PLUGS WITH SILICIDE CRYSTALLITES

Infineon Technologies Aus...

1. A semiconductor device, comprising:
a field effect transistor structure comprising source zones of a first conductivity type and body zones of a second conductivity
type which is the opposite of the first conductivity type, the source zones adjoining a first surface of a semiconductor die
comprising the source and the body zones;

a dielectric layer adjoining the first surface;
contact plugs extending through openings in the dielectric layer and electrically connected to the source and the body zones,
the contact plugs comprising polysilicon;

an impurity source in contact with the contact plugs and distant to the first surface of the semiconductor die, the impurity
source containing atoms of a metallic recombination element, the contact plugs embedding and separating silicide crystallites
from each other, the silicide crystallites being formed from the atoms of the metallic recombination element and being distributed
over the height of the contact plugs and spaced from a semiconductor material of the semiconductor die; and

a metal silicide formed along an interface between the contact plugs and the semiconductor die.

US Pat. No. 9,117,694

SUPER JUNCTION STRUCTURE SEMICONDUCTOR DEVICE BASED ON A COMPENSATION STRUCTURE INCLUDING COMPENSATION LAYERS AND A FILL STRUCTURE

INFINEON TECHNOLOGIES AUS...

1. A super junction semiconductor device, comprising:
a semiconductor portion comprising strip structures between mesa regions protruding from a base section in a cell area, each
strip structure comprising a compensation structure that comprises a first and a second section inversely provided on opposing
sides of a fill structure, each section comprising a first compensation layer of a first conductivity type and a second compensation
layer of a complementary second conductivity type, wherein

the strip structures are linear stripes extending through the cell area in a first lateral direction and extending into an
edge area surrounding the cell area in lateral directions, each strip structure comprising an end section with a termination
portion in the edge area in which the first compensation layer of the first conductivity type of the first section is connected
with the first compensation layer of the first conductivity type of the second section via a first conductivity layer, and
the second compensation layer of the second conductivity type of the first section is connected with the second compensation
layer of the second conductivity type of the second section via a second conductivity layer.

US Pat. No. 9,112,497

CIRCUIT ARRANGEMENT AND METHOD FOR GENERATING A DRIVE SIGNAL FOR A TRANSISTOR

Infineon Technologies Aus...

1. A method comprising:
receiving, by a driver circuit, from a control circuit, switching information and switching parameter information associated
with a transistor, the switching parameter information including switching speed information, wherein the switching information
and the switching parameter information are received for each switching operation of the transistor and based on a switching
signal received by the control circuit; and

generating, by the driver circuit, based on the switching information and the switching parameter information, a drive signal
associated with the transistor, wherein the drive signal is generated at a voltage or current level that is dependent on the
switching speed information.

US Pat. No. 9,443,973

SEMICONDUCTOR DEVICE WITH CHARGE COMPENSATION REGION UNDERNEATH GATE TRENCH

Infineon Technologies Aus...

7. A power transistor, comprising:
a semiconductor substrate comprising a main surface and a rear surface vertically spaced apart from the main surface, a drift
region, a source region, and a body region, the source region and the body region being formed in the drift region, the source
region extending from the main surface into the substrate, the body region interposed between the source region and the drift
region beneath the main surface;

first and second field plate trenches vertically extending from the main surface to a bottom that is arranged in the drift
region;

first and second field plates arranged in the first and second field plate trenches, respectively, and being dielectrically
insulated from the substrate;

a gate trench laterally arranged between the first and second field plate trenches and vertically extending from the main
surface through the source region and the body region so that the gate trench has a bottom arranged in the drift region;

a gate electrode arranged in the gate trench and being dielectrically insulated from the substrate, the gate electrode being
configured to control an electrically conductive channel in the body region; and

a compensation zone vertically extending from the bottom of the gate trench deeper into the drift region,
a drain region extending from the rear surface into the semiconductor substrate and coupled to the drift region;
a source electrode arranged on the main surface and electrically connected to the source region; and
a drain electrode arranged on the rear surface and electrically connected to the drain region,
third and fourth field plate trenches extending from the main surface to a bottom that is arranged in the drift region; and
third and fourth field plates arranged in the third and fourth field plate trenches, respectively, and being dielectrically
insulated from the substrate,

wherein the compensation zone is laterally aligned with the gate trench along a cross-sectional plane of the device that is
orthogonal to the main surface, and

wherein the compensation zone is adjacent to the field plates along a cross-sectional plane of the device that is parallel
to the main surface,

wherein the gate electrode is laterally arranged between third and fourth field plate trenches,
wherein the compensation zone is arranged underneath a portion of the gate trench that is equidistant to the first, second,
third and fourth field plates,

wherein the drift region, the source region, and the drain region are n-type regions, the drift region being more lightly
doped than the source and drain regions,

wherein the body region and the compensation zone are p-type regions, the compensation zone having a different doping concentration
than the body region, and

wherein the compensation zone is interrupted at regions within the drift zone in which laterally adjacent ones of the first,
second, third and fourth field plate trenches are closest to one another.

US Pat. No. 9,397,645

CIRCUIT FOR COMMON MODE REMOVAL FOR DC-COUPLED FRONT-END CIRCUITS

Infineon Technologies Aus...

1. A method comprising:
receiving a first differential signal including a first voltage signal and a second voltage signal, wherein the first differential
signal includes a first common mode voltage, wherein the first voltage signal is received at a first input pin of a plurality
of input pins and the second voltage signal is received at a second input pin of the plurality of input pins;

receiving a second common mode voltage;
determining, by a circuit that comprises a plurality of switches that are each configured to switch between a plurality of
states, a second differential signal including a third voltage signal and a fourth voltage signal, wherein a difference between
the third voltage signal and the fourth voltage signal is based on a difference between the first voltage signal and the second
voltage signal, wherein the second differential signal includes the second common mode voltage; and

outputting, substantially continuously, the second differential signal, wherein the third voltage signal is output at a first
output pin of a plurality of output pins and the fourth voltage signal is output at a second output pin of the plurality of
output pins, and wherein, during a particular state of the plurality of states, respective current paths are created between
the input pins and the output pins.

US Pat. No. 9,325,242

SWITCHING REGULATOR OUTPUT CAPACITOR CURRENT ESTIMATION

Infineon Technologies Aus...

10. A switching regulator, comprising:
a power stage for coupling to a load through an inductor and a capacitor; and
a controller operable to:
control operation of the power stage via a pulse width modulation (PWM) signal generated based on a difference between a reference
voltage and a load voltage of the load;

sample the load voltage;
sample inductor current of the inductor at a lower rate than the load voltage;
estimate capacitor current of the capacitor based on the sampled load voltage;
generate a first modification term based on the sampled inductor current;
generate a second modification term based on the estimated capacitor current;
combine the first and the second modification terms to form a voltage offset;
adjust the reference voltage by the voltage offset; and
adjust the PWM signal applied to the power stage based on the adjusted reference voltage.

US Pat. No. 9,484,746

POWER CONVERTER CIRCUIT WITH AC OUTPUT

Infineon Technologies Aus...

1. A power converter circuit, comprising:
output terminals configured to receive an external AC voltage;
at least one series circuit with at least two DC/AC converter circuits, each DC/AC converter circuit comprising input terminals
configured to be coupled to a DC power source, and output terminals for providing an AC output current, the at least one series
circuit connected between the output terminals of the power converter circuit; and

a voltage divider circuit connected between the output terminals of the power converter circuit and configured to provide
at least one measurement signal that includes a phase and frequency based on the external AC voltage;

wherein at least one of the DC/AC converter circuits is configured to receive the at least one measurement signal and is configured
to regulate generation of the AC output current dependent on the at least one measurement signal such that a phase difference
between the AC output current and the external AC voltage assumes a set value.

US Pat. No. 9,312,250

CHIP, CHIP ARRANGEMENT AND METHOD FOR PRODUCING A CHIP

INFINEON TECHNOLOGIES AUS...

1. A chip, comprising:
a carrier;
an integrated circuit formed above the carrier; and
an energy storage element having a first electrode and a second electrode for supplying the integrated circuit with electrical
energy;

wherein the carrier, the integrated circuit and the energy storage element are monolithically formed; wherein the carrier
is arranged between the second electrode and the integrated circuit; and

wherein the first electrode is formed within the carrier.

US Pat. No. 9,258,032

SYSTEM AND METHOD FOR RECEIVING DATA ACROSS AN ISOLATION BARRIER

Infineon Technologies Aus...

7. A system for communicating data across an isolation barrier, the system comprising:
a data transmitter coupled to a first portion of the isolation barrier, the transmitter configured to modulate an impedance
coupled to the first portion of the isolation barrier, wherein the impedance is modulated according to the data; and

a receiver coupled to a second portion of the isolation barrier opposite the first portion of the isolation barrier, wherein
the receiver is configured to receive the data by measuring an impedance of a second portion of the isolation barrier opposite
the first portion of the isolation barrier.

US Pat. No. 9,397,684

ANALOG TO DIGITAL CONVERTER CIRCUITS AND METHODS OF OPERATION THEREOF

Infineon Technologies Aus...

1. An analog to digital converter (ADC) circuit comprising:
an input stage to receive an input signal and output a modified input signal;
an input signal selector for supplying the modified input signal to an ADC for conversion to a digital signal;
a control unit of the ADC; and
an operational parameter setting device configured to receive an operational parameter setting signal indicative of an operating
parameter for the input stage from the control unit, wherein the operational parameter setting device is configured to set
an operating parameter for the input stage based on the operational parameter setting signal.