US Pat. No. 9,184,066

CHIP ARRANGEMENTS AND METHODS FOR MANUFACTURING A CHIP ARRANGEMENT

INFINEON TECHNOLOGIES AG,...

1. A chip arrangement comprising:
a carrier having a first carrier side and a second carrier side, wherein the first carrier side is opposite the second carrier
side;

a chip at least partially surrounded by a first encapsulation material, wherein a contact pad of the chip is disposed over
and electrically contacted to the first carrier side of the carrier, wherein the first encapsulation material is formed over
the first carrier side and the second carrier side, wherein the first encapsulation material forms the sidewalls of at least
one cavity on the second carrier side; and

a second encapsulation material formed at least partially over at least one of the first encapsulation material and the carrier,
wherein the second encapsulation material is formed in the cavity over the second carrier side, and wherein the first and
second encapsulation materials comprise different materials.

US Pat. No. 9,293,371

METHOD FOR PROCESSING A SEMICONDUCTOR WORKPIECE WITH METALLIZATION

INFINEON TECHNOLOGIES AG,...

1. A method for processing a semiconductor workpiece, the method comprising:
providing a semiconductor workpiece comprising a substrate region at a back side of the workpiece, a device region at a front
side of the workpiece, and a metallization disposed over a side of the substrate region opposite to the device region; and

patterning the metallization, wherein patterning the metallization comprises etching the metallization,
wherein the semiconductor workpiece comprises a wafer, wherein patterning the metallization comprises exposing a kerf region
of the wafer, and wherein the method further comprises dicing the wafer along the kerf region subsequent to patterning the
metallization.

US Pat. No. 9,093,385

METHOD FOR PROCESSING A SEMICONDUCTOR WORKPIECE WITH METALLIZATION

INFINEON TECHNOLOGIES AG,...

1. A method for processing a semiconductor workpiece, the method comprising:
providing a semiconductor workpiece comprising a metallization layer stack disposed at a side of the semiconductor workpiece,
the metallization layer stack comprising at least a first layer and a second layer disposed over the first layer, wherein
the first layer comprises a first material and the second layer comprises a second material that is different from the first
material;

patterning the metallization layer stack, wherein patterning the metallization layer stack comprises wet etching the first
layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first
material and the second material.

US Pat. No. 9,368,435

ELECTRONIC COMPONENT

Infineon Technologies AG,...

1. An electronic component, comprising:
a dielectric layer;
a semiconductor device embedded in the dielectric layer, wherein the semiconductor device comprises a first surface comprising
a first contact pad and a second surface comprising a second contact pad;

an electrically conductive substrate; and
a redistribution layer comprising a first surface, a second surface providing at least one outer contact and a first electrically
conductive member,

wherein the second contact pad is mounted on the electrically conductive substrate and the first electrically conductive member
comprises at least one stud bump and extends between the electrically conductive substrate and the first surface of the redistribution
layer,

wherein the electronic component further comprises at least one second electrically conductive member comprising a stud bump,
the second electrically conductive member extending between the first contact pad and the first surface of the redistribution
layer.

US Pat. No. 9,201,007

DEVICE FOR DETERMINATION OF GAS CONCENTRATION

Infineon Technologies AG,...

1. A device for establishing gas concentrations in an examination volume, the device comprising:
a radiation source configured to generate an electromagnetic beam;
a beam guiding apparatus arranged downstream of the radiation source, the beam guiding apparatus configured to set a plurality
of variations of beam guidance of the beam entering the beam guiding apparatus in an observation plane in the examination
volume, wherein the beam guiding apparatus comprises:

two first beam deflection devices that are spaced apart from one another by a distance A1 on a first beam axis, and

two second beam deflection devices that are spaced apart from one another by another distance A2 on a second beam axis, wherein the observation plane includes portions of the first beam axis and the second beam axis; and

a spectrometer arranged downstream of the beam guiding apparatus, the spectrometer configured to carry out a spectral analysis
of the beam leaving the beam guiding apparatus;

wherein an output of the spectrometer is configured to be used as a basis to establish in the observation plane a 2D concentration
distribution for one or more gases in the examination volume on the basis of the spectral analysis for different variations
of beam guidance.

US Pat. No. 9,224,633

METHOD FOR MANUFACTURING A COMPOSITE WAFER HAVING A GRAPHITE CORE, AND COMPOSITE WAFER HAVING A GRAPHITE CORE

Infineon Technologies AG,...

1. A method for manufacturing a composite wafer, comprising:
providing a first substrate;
providing a second substrate comprising a graphite layer;
forming a carbon layer comprising at least one of mesophase carbon, pitch and a mixture thereof on at least one of the first
substrate and the graphite layer of the second substrate;

joining the first substrate with the second substrate through the carbon layer; and
subjecting the carbon layer, the first substrate and the second substrate to a thermal treatment to form a stable bond between
the first substrate and the second substrate.

US Pat. No. 9,076,821

ANCHORING STRUCTURE AND INTERMESHING STRUCTURE

Infineon Technologies AG,...

1. An anchoring structure for a metal structure of a semiconductor device, the anchoring structure comprising:
an anchoring recess structure comprising at least one overhanging sidewall, wherein the metal structure is at least partly
arranged within the anchoring recess structure and below an overhang of the overhanging sidewall, wherein the overhanging
sidewall is formed by a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate comprises
mono-crystalline semiconductor in which the anchoring recess structure is formed so that the overhanging sidewall is formed
by the semiconductor.

US Pat. No. 9,146,874

DUAL ACCESS FOR SINGLE PORT CACHE

Infineon Technologies AG,...

1. A system for accessing a multi-way cache formed of single port memory, the system comprising:
an address multiplexer that simultaneously addresses a line of data and a line of program instructions in the multi-way cache;
a first duplicate output way multiplexer configured to select data read from the multi-way cache without selecting program
instructions; and

a second duplicate output way multiplexer configured to select program instructions read from the multi-way cache without
selecting data.

US Pat. No. 9,231,026

MAGNETORESISTIVE SENSOR MODULE WITH A STRUCTURED METAL SHEET FOR ILLUMINATION AND METHOD FOR MANUFACTURING THE SAME

Infineon Technologies AG,...

1. A method of manufacturing a magnetoresistive sensor module, comprising:
providing a semiconductor substrate, wherein a semiconductor circuit arrangement is integrated adjacent to a main surface
of the semiconductor substrate,

forming a metal-insulator arrangement onto the main surface of the semiconductor substrate, the forming of the metal-insulator
arrangement comprising:

applying a structured metal sheet on an insulating layer of the metal-insulator arrangement;
establishing an electrical connection between the structured metal sheet and the semiconductor circuit arrangement; and
applying a topmost layer of insulation material at least partially covering the structured metal sheet;
generating and filling with metal a first via through a first aperture and generating and filling with metal a second via
through a second aperture in a surface of the topmost layer of insulation material, so that the first metal filled via is
electrically connected to a first portion of the structured metal sheet, and the second metal filled via is electrically connected
to a second portion of the structured metal sheet, the second portion being electrically isolated from the first portion;

polishing the surface of the topmost layer of insulation material and an entire surface of the first and second metal filled
vias within the first and second apertures so that an entire polished planar surface of the first and second metal filled
vias is flush with edges of the first and second apertures on a polished planar surface of the topmost layer of insulation
material; and

applying a magnetoresistive sensor structure onto the polished planar surface of the topmost layer of insulation material
and the polished planar surface of the first and second metal filled vias, so that the magnetoresistive sensor structure fully
covers the first and second metal filled vias and is planer and flush with the polished planar surfaces of the first and second
metal filled vias and the polished planar surface of the topmost layer of insulation material, so as to establish an electrical
connection between the magnetoresistive sensor structure and the first and second portions of the structured metal sheet,
so that the magnetoresistive sensor structure is connected to the integrated circuit arrangement.

US Pat. No. 9,099,454

MOLDED SEMICONDUCTOR PACKAGE WITH BACKSIDE DIE METALLIZATION

Infineon Technologies AG,...

1. A semiconductor package, comprising:
a semiconductor die having a first side and a second side opposing the first side;
a terminal at the first side of the die;
a material coupled to the die at the second side of the die;
a molding compound in which the die is embedded, the die being covered by molding compound on all sides except the first side
and the second side, the material at the second side of the die being uncovered by molding compound without the second side
of the die being exposed; and

an electrical connection to the terminal at the first side of the die.

US Pat. No. 9,061,896

METHOD FOR MANUFACTURING A MEMS DEVICE AND MEMS DEVICE

Infineon Technologies AG,...

1. A method for manufacturing a MEMS device, the method comprising:
providing a cavity within a layer adjacent to a sacrificial layer, the cavity extending to the sacrificial layer and comprising
a capillary slot protruding into the layer; and

removing the sacrificial layer by exposing the sacrificial layer to an etching agent that is introduced through the cavity.

US Pat. No. 9,136,213

INTEGRATED SYSTEM AND METHOD OF MAKING THE INTEGRATED SYSTEM

Infineon Technologies AG,...

1. A system comprising:
a first packaged component comprising a first semiconductor component, a first portion of a primary winding, a first portion
of a secondary winding and a first encapsulant;

a second packaged component comprising a second semiconductor component, a second portion of the primary winding, a second
portion of the secondary winding and a second encapsulant, the first packaged component being separate from the second packaged
component;

and
an underfill material disposed between the first packaged component and the second packaged component, wherein the underfill
material comprises a solder ball arrangement, wherein a first set of solder balls connects the first portion of the primary
winding to the second portion of the primary winding, wherein a second set of solder balls connects the first portion of the
secondary winding to the second portion of the secondary winding, and wherein the primary winding and the secondary winding
form a transformer.

US Pat. No. 9,117,786

CHIP MODULE, AN INSULATION MATERIAL AND A METHOD FOR FABRICATING A CHIP MODULE

Infineon Technologies AG,...

1. A chip module, comprising:
a semiconductor chip;
a carrier, wherein the semiconductor chip is arranged on or embedded inside the carrier; and
an insulation layer at least partly covering a face of the carrier, wherein a dielectric constant ?r and a thermal conductivity ? of the insulation layer satisfy the condition ?·?r<1.0 W·m?1·K?1.

US Pat. No. 9,143,123

RF SWITCH, MOBILE COMMUNICATION DEVICE AND METHOD FOR SWITCHING AN RF SIGNAL

Infineon Technologies AG,...

1. An RF switch comprising:
a switchable RF transistor, wherein the switchable RF transistor comprises a stripe of a plurality of adjacent RF transistor
fingers; and

a non-switchable dummy transistor arranged at an end of the stripe of the switchable RF transistor.

US Pat. No. 9,313,897

METHOD FOR ELECTROPHORETICALLY DEPOSITING A FILM ON AN ELECTRONIC ASSEMBLY

Infineon Technologies AG,...

1. A method for manufacturing a packaged component, the method comprising:
placing a component on a component carrier;
connecting a conductive connection element to a component contact of the component and to a component carrier contact of the
component carrier; then,

electrophoretically depositing an insulating film on at least one of the component, the conductive connection element and
the component, carrier, wherein the insulating film is an polyurethane resin or a polar high performance thermoplastic; and

encapsulating the component, the conductive connection element and the component carrier with a molding compound.

US Pat. No. 9,362,216

CONDUCTIVE PADS AND METHODS OF FORMATION THEREOF

Infineon Technologies AG,...

1. A device comprising:
a first conductive pad disposed over a first side of a substrate;
an etch stop layer disposed over a top surface of the first conductive pad; and
a solder layer disposed over the etch stop layer, wherein the solder layer is configured to form a solder with another material;
and

a second conductive pad disposed over the first side of the substrate, wherein the first conductive pad and the second conductive
pad are configured to be coupled to external nodes from the first side of the substrate, wherein the first conductive pad
is configured to be contacted with a first type of contact, and wherein the second conductive pad is configured to be contacted
with a second type of contact that is different from the first type of contact, and wherein the first type of contact and
the second type of contact comprise a type of contact selected from the group consisting of wire bonded contact, soldered
contact, pressure bonded contact, wedge bonded contact, and anodic bonded contact.

US Pat. No. 9,185,762

TIME OF FLIGHT ILLUMINATION CIRCUIT

Infineon Technologies AG,...

1. A driving circuit, comprising:
a current source coupled to an input electrode of a light emitting element and configured to provide a current to the input
electrode to provide a forward bias to the light emitting element; and

a first modulation switch coupled to the input electrode of the light emitting element and configured to enable or disable
the current from the driving circuit to selectively forward bias the light emitting element by switching off the first modulation
switch or by switching on the first modulation switch, respectively,

wherein the light emitting element is reverse biased when the first modulation switch is switched on.

US Pat. No. 9,105,487

SUPER JUNCTION SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A super junction semiconductor device, comprising:
a substrate layer of a first conductivity type; and
an epitaxial layer adjoining the substrate layer and comprising first columns of the first conductivity type and second columns
of a second conductivity type, which is the opposite of the first conductivity type, the first and second columns extending
along a main crystal direction from a first surface opposite to the substrate layer into the epitaxial layer and having vertical
dopant profiles perpendicular to the first surface, wherein

the vertical dopant profile of at least one of the first and second columns includes first portions separated by second portions,
in each of the first portions a dopant concentration is non-constant and varies by at most 30% of a maximum value within the
respective first portion, in the second portions the dopant concentration is lower than in the adjoining first portions, and
a ratio of a total length of the first portions to a total length of the first and second portions is at least 50%.

US Pat. No. 9,370,113

POWER SEMICONDUCTOR MODULE WITH CURRENT SENSOR

Infineon Technologies AG,...

1. A power semiconductor module, comprising:
a power electronics substrate having a first surface, a second surface opposite the first surface, a first longitudinal side
and a second longitudinal side opposite the first longitudinal side;

a module frame, which is arranged in such a way that it encloses the power electronics substrate;
at least one power terminal which is arranged at the first longitudinal side and which extends at least partially through
the module frame;

a further terminal, which is arranged at the second longitudinal side and which extends at least partially through the module
frame;

at least one power semiconductor component which is arranged on the first surface of the power electronics substrate and is
electrically connected to at least one power terminal; and

at least one current sensor which is designed to measure a current in a power terminal, wherein the at least one current sensor
is arranged on the power terminal and has a signal output connected to the further terminal.

US Pat. No. 9,408,266

DRIVER CIRCUIT FOR EFFICIENTLY DRIVING A LARGE NUMBER OF LEDS

Infineon Technologies AG,...

1. A circuit for controlling a plurality of LEDs coupled in series, the circuit comprising:
a switching converter operable as a current source to be coupled to the plurality of LEDs to provide a controlled load current
thereto, the switching converter including an inductor to be continuously connected in series with the plurality of LEDs such
that when the LEDs are coupled the same load current flows through the inductor and the plurality of LEDs;

a plurality of floating driver circuits, each floating driver circuit configured to be coupled in parallel to a respective
individual LED of the plurality of LEDs, and configured to bypass at least a portion of the load current of the respective
individual LED in accordance with a respective modulated input signal; and

a modulator for each floating driver circuit, each modulator configured to be coupled to an I/O interface.

US Pat. No. 9,129,805

DIODE BIASED ESD PROTECTION DEVICE AND METHOD

Infineon Technologies AG,...

1. A method of forming a semiconductor device, the method comprising:
providing a semiconductor body of a first conductivity type;
forming a gate region over a portion of the semiconductor body;
forming highly doped source and drain regions of a second conductivity type opposite to the first conductivity type in the
semiconductor body adjacent to the gate region;

forming a diode on the semiconductor body, the diode comprising a first diode region of the first conductivity type and a
second diode region of the second conductivity type;

forming an external connection pad on the semiconductor body;
electrically coupling the highly doped drain to the external connection pad;
electrically coupling the diode between the gate region and the highly doped source region, wherein the second diode region
of the second conductivity type is directly electrically coupled to the gate region and the first diode region of the first
conductivity type is directly electrically coupled to the doped source region, wherein the second diode region is isolated
from other device regions of the semiconductor device besides the gate region and the first diode region; and

electrically coupling the highly doped source region to a reference potential.

US Pat. No. 9,479,202

SYSTEM AND METHOD FOR BURST MODE AMPLIFIER

Infineon Technologies AG,...

1. A system for amplifying a burst mode RF signal, the system comprising:
a first amplifier, the first amplifier configured to amplify the burst mode RF signal provided at an input of the first amplifier;
a second amplifier having an input coupled to the output of the first amplifier; and
a switchable impedance element coupled to the output of the first amplifier and to an input of the second amplifier, wherein
the switchable impedance element is configured to comprise a first impedance when the burst mode RF signal is active and to
comprise a second impedance when the burst mode RF signal is inactive.

US Pat. No. 9,363,609

METHOD FOR FABRICATING A CAVITY STRUCTURE, FOR FABRICATING A CAVITY STRUCTURE FOR A SEMICONDUCTOR STRUCTURE AND A SEMICONDUCTOR MICROPHONE FABRICATED BY THE SAME

Infineon Technologies AG,...

1. A semiconductor microphone comprising:
a first conductive membrane layer disposed in or over a substrate, the first conductive membrane layer being a moveable membrane
of the microphone;

a second conductive membrane layer disposed over the first conductive membrane layer;
a cavity structure disposed between the first conductive membrane layer and the second conductive membrane layer, wherein
the second conductive membrane layer is separated by the cavity structure from the first conductive membrane layer, wherein
the second conductive membrane layer comprises a circumferential side wall extending in a direction to the first conductive
membrane layer;

an encapsulant layer disposed between the second conductive membrane layer and the first conductive membrane layer, the encapsulant
layer comprising a circumferential side wall disposed on the circumferential side wall of the first conductive membrane layer;
and

a cover layer disposed over a top surface of the cavity structure, the encapsulant layer disposed between the cover layer
and the second conductive membrane layer.

US Pat. No. 9,147,448

CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING A CIRCUIT ARRANGEMENT

INFINEON TECHNOLOGIES AG,...

1. A circuit arrangement, comprising:
a storage circuit configured to provide a first output signal and a second output signal;
an output circuit configured to receive the first output signal and the second output signal and configured to provide an
output signal having one of a first signal level and a second signal level, and to switch from the first signal level to the
second signal level if the difference between the first output signal and the second output signal exceeds a threshold, and

wherein the circuit arrangement is configured to hold the first output signal and the second output signal independent of
a difference between the first output signal and the second output signal after the switching has been carried out.

US Pat. No. 9,484,316

SEMICONDUCTOR DEVICES AND METHODS OF FORMING THEREOF

Infineon Technologies AG,...

1. A method of forming a semiconductor device, the method comprising:
forming a metallization layer over a first major surface of a substrate;
forming a contact layer over a second major surface of the substrate, the second major surface being opposite to the first
major surface, the substrate comprising device regions separated by kerf regions, the contact layer overlapping with the kerf
regions and the device regions, wherein the contact layer substantially covers an entire second major surface;

at the second major surface, forming a structured solder layer over the device regions, wherein a portion of the contact layer
is exposed at the kerf regions after forming the structured solder layer, wherein the structured solder layer overlaps with
at least 80% of the contact layer, and wherein the structured solder layer is thicker than the substrate;

after forming the structured solder layer, forming a conformal liner over the structured solder layer and the exposed contact
layer at the kerf regions, the conformal liner covering sidewalls of the structured solder layer, the conformal liner being
formed in a conformal way as a liner over the structured solder layer; and

dicing through the conformal liner, the contact layer, and the substrate in the kerf regions.

US Pat. No. 9,504,143

ELECTRICAL CIRCUIT

Infineon Technologies AG,...

1. An electrical circuit, comprising:
a first substantially planar electrical circuit part to which a first electrical potential is applicable; and
a second substantially planar electrical circuit part to which a second, different electrical potential is applicable and
which is galvanically isolated from the first substantially planar electrical circuit part by an insulator;

wherein the insulator comprises a conducting portion;
wherein the first and the second substantially planar electrical circuit parts and the insulator form a layer stack, in which
the insulator is arranged between the first and the second substantially planar electrical circuit part, and at least a portion
of the second substantially planar electrical circuit part overlies the first substantially planar electrical circuit part;

wherein the first substantially planar electrical circuit part is a conductor of a high voltage section; and
wherein the second substantially planar electrical circuit part is a circuit element of a low voltage section.

US Pat. No. 9,313,898

LOW VISCOSITY POLYMERIC PRINTING SOLUTIONS AND ELECTRONIC COMPONENTS BEARING POLYIMIDE BASED UPON THE LOW VISCOSITY POLYMERIC PRINTING SOLUTIONS

Infineon Technologies AG,...

1. An electrical component, the electrical component comprising:
a substrate; and
a polymeric layer in working relation with the substrate, the polymeric layer comprising a low molecular mass polyimide having
the chemical structure of formula XXIII, or an isomer thereof:

wherein M is an integer ranging from as low as about 10 to as high as about 100 and:
R1 is a carbonyl group; or

R1 is an alkenyl group of formula CnH2n?2 and n of formula CnH2n?2 is an integer ranging from as low as 2 to as high as 12; or

R1 is an alkenyl group of formula CnH2n?4 and n of formula CnH2n?4 is an integer ranging from as low as 2 to as high as 12; or

R1 is an alkenyl group of formula CnH2n?6 and n of formula CnH2n?6 is an integer ranging from as low as 3 to as high as 12.

US Pat. No. 9,196,535

METHOD AND APPARATUS FOR SEPARATING SEMICONDUCTOR DEVICES FROM A WAFER

INFINEON TECHNOLOGIES AG,...

1. A method for separating semiconductor devices from a wafer, the method comprising:
arranging semiconductor devices on a carrier, the carrier including at least a thermo-release foil, and
removing a plurality or all of the semiconductor devices from the carrier using a gas jet.

US Pat. No. 9,275,324

BOOSTER ANTENNA STRUCTURE FOR A CHIP CARD

INFINEON TECHNOLOGIES AG,...

1. A contactless chip card module arrangement, comprising:
a booster antenna structure for a chip card, wherein the booster antenna structure comprises:
a booster antenna; and
an additional electrically conductive meander structure connected to the booster antenna;
a contactless chip card module which comprises:
a chip; and
a coil which is coupled electrically to the chip;
wherein the booster antenna structure is coupled inductively to the coil of the contactless chip card module by means of at
least one inductive coupling area of the booster antenna; and

wherein the booster antenna structure is power-matched to the contactless chip card module; and
wherein the match is adjustable by means of an ohmic impedance of the additional electrically conductive meander structure.

US Pat. No. 9,203,437

CIRCUITRY AND METHOD FOR CORRECTING 3-BIT ERRORS CONTAINING ADJACENT 2-BIT ERROR

Infineon Technologies AG,...

1. A circuitry for a correction of errors in a possibly erroneous binary word v?=v?1, . . . , v?n relative to a codeword v=v1, . . . , vn, the circuitry comprising:
a syndrome generator for determining an error syndrome s=(s1, s3) according to a modified BCH code with a H-matrix Hmod comprising a first BCH submatrix H1mod and a second BCH submatrix H3mod, and with a code distance d?5,

wherein n? column vectors of the BCH submatrix H1mod are paired as column vector pairs so that a componentwise XOR combination of the two column vectors of each column vector
pair produces an identical column vector K that is different from all column vectors of the first BCH submatrix H1mod and where n? is even and 4?n??n applies,

wherein the second BCH submatrix H3mod comprises a corresponding column vector for each column vector in the first BCH submatrix H1mod so that the corresponding column vector is a third power, according to Galois field arithmetic, of the column vector in the
first BCH submatrix H1mod,

wherein the syndrome generator is configured to determine the error syndrome s by multiplying the H-matrix Hmod with the possibly erroneous binary word v? so that a first error syndrome portion is given by s1=H1mod·v? and a second error syndrome portion is given by s3=H3mod·v?; and

a decoder for generating a correction vector e=(e1, . . . , en) with correction values ej=ej+1=el=1 and et=0 for t?j, j+1, l, if the first error syndrome portion s1 equals the componentwise XOR combination of the identical column vector K and a column vector at a column position l of the
first BCH submatrix H1mod, and if the second error syndrome portion s3 equals the componentwise XOR combination of column vectors at column positions j, j+1, and l of the second BCH submatrix H3mod.

US Pat. No. 9,123,544

SEMICONDUCTOR DEVICE AND METHOD

Infineon Technologies AG,...

1. An electrical device comprising:
a semiconductor chip, the semiconductor chip comprising a horizontal routing line, wherein the routing line comprises a contact
section and a line section electrically coupled to the contact section and extending laterally from the contact section;

an insulating layer arranged over the semiconductor chip;
a solder deposit arranged over the insulating layer; and
a via extending through an opening in the insulating layer to electrically connect the contact section to the solder deposit,
wherein a horizontal front edge line portion of the via laterally facing the line section is substantially straight, has a
concave curvature or has a convex curvature of a diameter greater than a maximum lateral dimension of the via.

US Pat. No. 9,070,067

SMART CARD MODULE AND METHOD FOR PRODUCING A SMART CARD MODULE

Infineon Technologies AG,...

1. A smart card module, comprising:
a microchip;
a cover and a base laminated onto one another to form a sealed and permanent encapsulation of the microchip from all sides,
the base having a first electrical connection to which an active side of the microchip is fitted and for making electrical
contact with the microchip; and

a substrate comprising a mounting surface to which the base of the encapsulation is permanently and fixedly fitted, and a
second electrical connection which electrically connects the microchip to contacts of a contact zone disposed on an opposite
surface of the substrate as the mounting surface, the second electrical connection extending from the mounting surface to
the opposite surface of the substrate.

US Pat. No. 9,355,881

SEMICONDUCTOR DEVICE INCLUDING A DIELECTRIC MATERIAL

Infineon Technologies AG,...

1. A method for manufacturing a semiconductor device, the method comprising:
providing a carrier;
providing a semiconductor wafer having a first side and a second side opposite to the first side;
applying a dielectric material to the carrier or the semiconductor wafer;
bonding the semiconductor wafer to the carrier via the dielectric material;
processing the semiconductor wafer;
removing the carrier from the semiconductor wafer such that the dielectric material remains on the semiconductor wafer to
provide a semiconductor device comprising the dielectric material; and

structuring the dielectric material after removing the carrier from the semiconductor wafer.

US Pat. No. 9,355,909

METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT HAVING FIELD EFFECT TRANSISTORS INCLUDING A PEAK IN A BODY DOPANT CONCENTRATION

Infineon Technologies AG,...

1. A method of forming an integrated circuit, comprising:
forming a first FET and a second FET;
electrically connecting at least one of source, drain, gate of the first FET to the corresponding one of source, drain, gate
of the second FET; and

connecting at least one further of source, drain, gate of the first FET and the corresponding one further of source, drain,
gate of the second FET to a circuit element, respectively; and

wherein the formation of the first and second FET includes forming a body of each of the first and second FETs having a dopant
concentration along a channel of the respective FET that includes a peak at a peak location within the channel, and further
comprising forming the first and second FETs as Trench FETs comprising trenches extending into a semiconductor substrate from
a first surface of the semiconductor substrate, and wherein forming the body of each of the first and second FETs includes:

implanting dopants into the semiconductor substrate such that a peak concentration of the implanted dopants has a greater
distance to the first surface than a pn junction between the source and the body.

US Pat. No. 9,202,800

METHODS FOR PRODUCING A BOND AND A SEMICONDUCTOR MODULE

Infineon Technologies AG,...

1. A method for producing a bond, the method comprising:
providing a holding frame having a receiving region;
providing a pressure chamber having a first housing element and a second housing element; and
for the pressure chamber:
providing a first part, a second part, a connecting means and a sealing means;
loading the pressure chamber with the first part, the second part and the connecting means in such a way that the connecting
means is to be positioned between the first part and the second part, at least the connecting means being arranged in a first
chamber region of the pressure chamber;

placing the loaded pressure chamber into the receiving region;
pressing the first housing element of the pressure chamber against the second housing element of the pressure chamber so that
the pressure chamber placed in the receiving region is clamped with the aid of a working cylinder between the working cylinder
and the holding frame; and

generating in a second chamber region of the pressure chamber a second gas pressure, which is higher than a first gas pressure
in the first chamber region, so that the first part, the second part and the connecting means are pressed against one another
to form a bond.

US Pat. No. 9,373,563

SEMICONDUCTOR ASSEMBLY HAVING A HOUSING

Infineon Technologies AG,...

1. A semiconductor assembly comprising:
a housing comprising an inner housing comprising a cover and a peripheral rim; and
at least one pressure element including a frame arranged adjacent a side-face of the peripheral rim, the inner housing being
arranged within the frame, the pressure element being resiliently coupled to the inner housing by a plurality of resilient
coupling members, and where the pressure element, the inner housing, and the resilient coupling members are provided in the
form of a single plastic part.

US Pat. No. 9,632,173

METHOD, DEVICE AND SYSTEM FOR PROCESSING RADAR SIGNALS

Infineon Technologies AG,...

1. A method for processing radar signals comprising digitized data received by at least two radar antennas, the method comprising:
determining Constant false alarm rejection (CFAR) results on Fast Fourier Transform (FFT) results based on data received by
a first antenna using a processor or hardware logic; and

applying the CFAR results to FFT results based on data received by a second antenna using the processor or hardware logic.

US Pat. No. 9,218,236

ERROR SIGNAL HANDLING UNIT, DEVICE AND METHOD FOR OUTPUTTING AN ERROR CONDITION SIGNAL

Infineon Technologies AG,...

1. An error signal handling unit, comprising:
an error handler comprising at least partially hardware configured to receive an error signal indicating an error condition;
wherein the error handler is further configured to receive a recovery signal indicating a mitigation of the error condition
or indicating that a mitigation of the error condition is possible; and

wherein the error handler is further configured to output an error condition signal based on the error signal in response
to a reception of the error signal if within a given delay time from the reception of the error signal, the error handler
does not receive the recovery signal, and otherwise omit outputting the error condition signal.

US Pat. No. 9,297,669

BIAS FIELD GENERATION FOR A MAGNETO SENSOR

Infineon Technologies AG,...

1. A manufacturing method comprising:
providing a bias field generator to generate a bias magnetic field having a field component in a first direction, wherein
the bias field generator comprises a body of permanent magnetic material or magnetizable material with a cavity such that
the cavity is laterally hounded in a second direction by first and second inclined surface sections of the body and in third
direction by third and fourth inclined surface sections of the body, the second direction being orthogonal to the first direction
and the third direction being orthogonal to the second direction and the first direction; and

arranging a magneto sensor in a part of the cavity wherein the magneto sensor is arranged to be laterally bound by the first
and second inclined surface sections and to be laterally hound by the third and fourth inclined surface sections.

US Pat. No. 9,287,165

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

Infineon Technologies AG,...

1. A power semiconductor device, comprising:
a semiconductor body, having an active zone and a high voltage peripheral zone laterally adjacent to each other, the high
voltage peripheral zone laterally surrounding the active zone;

a metallization layer on a front surface of the semiconductor body and connected to the active zone;
a first barrier layer, comprising a high-melting metal or a high-melting alloy, between the active zone and the metallization
layer; and

a second barrier layer covering at least a part of the peripheral zone, the second barrier layer comprising an amorphous semi-isolating
material,

wherein the first barrier layer and the second barrier layer partially overlap and form an overlap zone, the overlap zone
extending over an entire circumference of the active zone.

US Pat. No. 9,578,789

POWER SEMICONDUCTOR MODULE WITH LIQUID COOLING

Infineon Technologies AG,...

1. A power semiconductor module, comprising:
a baseplate;
a substrate arranged on the baseplate; and
a two-part cooling system arranged under the baseplate and comprising:
an upper piece connected directly to the baseplate and comprising an opening configured so as to form, with the baseplate,
a flow channel for a cooling liquid, the upper piece having a first inflow and an outflow through which the cooling liquid
can be introduced into the flow channel and removed, the upper piece further having at least one second inflow spaced apart
from the first inflow in a longitudinal direction; and

a lower piece attached to the upper piece by adhesive bonding or screws and having an inlet and an outlet, the outlet being
connected to the outflow of the upper piece and the inlet being connected to the first inflow of the upper piece, the lower
piece further having a channel branching off from the inlet, which has at least one bypass channel, which is connected to
the second inflow, so part of the cooling liquid passes through the bypass channel into the flow channel.

US Pat. No. 9,287,238

LEADLESS SEMICONDUCTOR PACKAGE WITH OPTICAL INSPECTION FEATURE

Infineon Technologies AG,...

1. A method of manufacturing molded semiconductor packages, the method comprising:
providing a lead frame comprising a plurality of thicker bond pads interconnected by thinner tie bars at a first side of the
bond pads;

covering the first side of the bond pads with a material resistant to etching of the tie bars;
attaching semiconductor dies and electrical conductors to a second side of the bond pads opposite the first side;
encasing the semiconductor dies and the electrical conductors in a molding compound at the second side of the bonds pads;
etching at least partly through the tie bars between the bond pads at the covered first side of the bond pads;
plating exposed sidewalls of the bonds pads uncovered by the molding compound; and
cutting through the molding compound in different regions where the tie bars were previously etched, to form separate packages,
wherein some of the bond pads are die paddles and other ones of the bond pads are leads,
wherein the molding compound extends to the material covering the first side of the bond pads between adjacent ones of the
die paddles and leads so that the molding compound completely covers facing sidewalls of adjacent ones of the die paddle and
lead bond pads and prevents the plating of the facing sidewalls.

US Pat. No. 9,275,944

SEMICONDUCTOR PACKAGE WITH MULTI-LEVEL DIE BLOCK

Infineon Technologies AG,...

1. A semiconductor package, comprising:
a block having a first side, a second side opposite the first side and a recessed region extending from the second side toward
the first side so that the block has a thinner part in the recessed region and a thicker part outside the recessed region;

a first semiconductor die having opposing first and second sides, the first semiconductor die disposed in the recessed region
of the block and attached to the thinner part of the block at the first side of the first semiconductor die; and

a second semiconductor die attached to the second side of the first semiconductor die at a first side of the second semiconductor
die, wherein a part of the second semiconductor die overhangs the thicker part of the block.

US Pat. No. 9,655,265

ELECTRONIC MODULE

Infineon Technologies AG,...

1. An electronic module, comprising:
an electronic chip arranged in the electronic module and comprising an input terminal and an output terminal;
a first current path electrically connected to the input terminal;
a second current path electrically connected to the output terminal; and
an insulation arranged between the first current path and the second current path,
wherein the first current path and the second current path extend in the same direction and arranged in close proximity to
each other;

wherein the insulator is formed by an insulating layer having a thickness of less than 500 micrometer;
wherein the first current path and the second current path each comprise a first portion which is connected to the electronic
chip, and

wherein the first current path and the second current path each comprise a second portion which is connected to the insulation;
wherein at least one of the first current path and the second current path comprises a step between the first portion and
the second portion; and

wherein a distance between the first portion of the first current path and the first portion of the second current path is
larger than a distance between the second portion of the first current path and the second portion of the second current path.

US Pat. No. 9,299,829

VERTICAL TRANSISTOR COMPONENT

Infineon Technologies AG,...

1. A semiconductor arrangement, comprising:
a semiconductor body having a first surface and a second surface;
a trench extending from the first surface into the semiconductor body;
a dielectric layer and an electrode layer in the trench, the electrode layer being arranged on the dielectric layer such that
the dielectric layer is disposed between the electrode layer and the semiconductor body; and

a contact plug extending through the dielectric layer to the electrode layer and electrically connected to the electrode layer.

US Pat. No. 9,245,984

REVERSE BLOCKING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE WITH LOCAL EMITTER EFFICIENCY MODIFICATION AND METHOD OF MANUFACTURING A REVERSE BLOCKING SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A reverse blocking semiconductor device, comprising:
a collector electrode;
a base region of a first conductivity type and a body region of a second complementary conductivity type, the base and body
regions forming a pn junction; and

an emitter layer arranged between the base region and the collector electrode and comprising emitter zones of the second conductivity
type and a channel of the first conductivity type,

wherein the channel extends through the emitter layer between the base region and the collector electrode and at least a vertical
section of the channel is completely depleted in a reverse blocking state of the reverse blocking semiconductor device.

US Pat. No. 9,274,163

TURRET HANDLERS AND METHODS OF OPERATIONS THEREOF

Infineon Technologies AG,...

1. A method of testing a semiconductor component, the method comprising:
loading a plurality of semiconductor components into a main turret of a turret handler;
transporting the plurality of semiconductor components using the main turret to a test area;
splitting the plurality of semiconductor components into a first set and a second set, wherein splitting the plurality of
semiconductor components into a first set and a second set comprises transporting the first set from the main turret to a
first secondary turret and transporting the second set from the main turret to a second secondary turret;

using a tester, testing a first semiconductor component in the first set at a first test pad while transporting a second semiconductor
component in the second set to a second test pad;

using the tester, testing the second semiconductor component while transporting the first semiconductor component out of the
first test pad; and

merging the first set and the second set into the plurality of semiconductor components and transporting the plurality of
semiconductor components away from the test area using the main turret.

US Pat. No. 9,128,136

APPARATUS AND METHOD FOR DETERMINING THE SENSITIVITY OF A CAPACITIVE SENSING DEVICE

Infineon Technologies AG,...

1. An apparatus for determining a sensitivity of a capacitive sensing device having a sensor capacitor with a variable capacitance,
the apparatus comprising:
a measurement module configured to determine, in response to a first electrical input signal to the sensor capacitor, a first
quantity indicative of a first capacitance of the sensor capacitor and to determine, in response to a second electrical input
signal to the sensor capacitor, a second quantity indicative of a second capacitance of the sensor capacitor; and

a processor configured to determine the sensitivity of the sensing device based on the determined first and second quantity.

US Pat. No. 9,118,351

SYSTEM AND METHOD FOR SIGNATURE-BASED REDUNDANCY COMPARISON

Infineon Technologies AG,...

1. A redundant system, comprising:
a hardware-implemented master part configured to receive an input signal and generate a binary output signal;
a first clock delay configured to receive the input signal and generate a delayed input signal;
a first signature generator coupled to the hardware-implemented master part and configured to receive the binary output signal
and generate a first output signature based thereon;

a second clock delay coupled to the first signature generator and configured to receive the first output signature and generate
a delayed first output signature;

a checker part coupled to the first clock delay and configured to receive the delayed input signal and generate a delayed
binary output signal based thereon;

a second signature generator coupled to the checker part and configured to receive the delayed binary output signal and generate
a delayed second output signature based thereon; and

a comparator coupled to the second clock delay and the second signature generator, the comparator configured to receive the
delayed first output signature and the delayed second output signature and generate an error signal, a state of the error
signal based upon a comparison of the delayed first output signature with the delayed second output signature.

US Pat. No. 9,274,998

DRIVE TRAIN CONTROL

Infineon Technologies AG,...

1. An apparatus, comprising:
a controller to control at least part of a drive train, wherein the controller is configured to:
communicate with at least one submodule of the drive train in a first mode of operation via at least a first communication
channel using a first communication protocol, and

communicate with the at least one submodule of the drive train in a second mode of operation via a second communication channel
using a second communication protocol different from the first communication protocol upon failure of the first communication
channel.

US Pat. No. 9,147,649

MULTI-CHIP MODULE

Infineon Technologies AG,...

1. An electronic module comprising:
a first metal plate having a first major surface and a second major surface and having at least one integral bent-up interconnect
portion extending generally perpendicular from the second major surface of the first metal plate;

a first semiconductor chip including a front side and a back side, the front side including a first contact and a second contact,
the backside electrically connected to and mounted on the second major surface of the first metal plate;

a second semiconductor chip including a front side and a back side, the front side including at least two contacts, the back
side of the second semiconductor chip including a contact arranged over the front side of the first semiconductor chip and
electrically connected to the second contact on the front side of the first semiconductor chip; and

a second metal plate having a first major surface and a second major surface attached over the front side of the second semiconductor
chip with the second major surface facing the second semiconductor chip, the second metal plate being structured to form multiple
external contact elements, wherein at least two of the multiple external contact elements are electrically connected to the
at least two contacts on the front side of the second semiconductor chip, wherein at least one of the multiple external contact
elements includes an integral bent-down interconnect portion that extends perpendicularly from the second major surface of
the second metal plate to the first contact on the front side of the first semiconductor chip and is electrically connected
thereto, wherein the multiple external contact elements are not in direct electrical contact with each other, and wherein
each of the multiple external contact elements separately provides an external electrical terminal, wherein the second metal
plate is physically discontinuous from the at least two contacts on the front side of the second semiconductor chip, and wherein
at least two contacts on the front side of the second semiconductor chip are electrically connected to the multiple external
contact elements of the second metal plate by an electrically conductive adhesion material;

wherein the at least one of the integral bent-up interconnect portion of the first metal plate extends to and is directly
connected to one of the multiple external contact elements of the second metal plate, and the integral bent-up interconnect
portion is uncovered by mold material; and

a molded body embedding the first and second semiconductor chips, wherein the first major surfaces of the first and second
metal plates, including the multiple external contact elements, are exposed by the molded body, and wherein the contact on
the back side of the second semiconductor chip and second contact on the front side of the first semiconductor, and the electrical
connection there between, are embedded within the molded body and are not directly connected to an external contact element.

US Pat. No. 9,281,032

MEMORY TIMING CIRCUIT

Infineon Technologies AG,...

1. A memory circuit, comprising:
a memory cell configured to provide a charge, voltage, or current to an associated bit-line;
a sense amplifier configured to sense the charge, voltage, or current on the bit-line;
a word-line circuit configured to control a word-line of the memory cell;
a bit-line circuit having at least one of (i) a bit-line voltage control circuit and (ii) a mux circuit; anda tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at
an output operative to adaptively control at least one of: (i) the word-line circuit, and (ii) bit-line circuit, wherein the
tracking circuit comprises:
a reference sense amplifier;
a reference bit-line; and
a reference element configured to provide a reference charge, voltage, or current to the reference bit-line, wherein the reference
sense amplifier and the reference bit-line have a configuration substantially similar to the bit-line and sense amplifier.

US Pat. No. 9,257,342

METHODS OF SINGULATING SUBSTRATES TO FORM SEMICONDUCTOR DEVICES USING DUMMY MATERIAL

Infineon Technologies AG,...

1. A method of forming a semiconductor device, the method comprising:
forming a plurality of active elements in a semiconductor substrate having a first side and an opposite second side, the plurality
of active elements being formed adjacent the first side;

forming metallization, at the first side, over the plurality of active elements to form a plurality of devices;
forming openings in the semiconductor substrate, the openings surrounding each of the plurality of devices; and
forming a dummy plug within the openings;
providing a tape over the opposite second side of the semiconductor substrate;
providing a frame and an adhesive covering the first side of the semiconductor substrate,
wherein a portion of the adhesive is disposed within the openings covering the dummy plug; and
singulating the semiconductor substrate
by removing the frame and the adhesive and
followed by removing the dummy plug in the openings from the first side of the semiconductor substrate.

US Pat. No. 9,281,813

HALF BRIDGE FLYBACK AND FORWARD

Infineon Technologies AG,...

1. A circuit, comprising:
a transformer having a first winding and a second winding;
an input connected to a first terminal of the first winding;
a first power transistor having a source, a gate connected to a DC source, and a drain connected to a second terminal of the
first winding; and

a second power transistor having a source connected to ground, a gate connected to a pulsed voltage drive source, and a drain
connected to the source of the first power transistor,

wherein the first power transistor actively turns off independent of load current.

US Pat. No. 9,281,359

SEMICONDUCTOR DEVICE COMPRISING CONTACT TRENCHES

Infineon Technologies AG,...

1. A semiconductor device comprising:
a semiconductor body including a first side and a second side opposite to the first side;
contact trenches extending, from the first and second sides, through a dielectric and into the semiconductor body, the contact
trenches including conductive material electrically coupled to the semiconductor body via sidewalls, wherein the contact trenches
include:

a first contact trench extending through a first dielectric and into the semiconductor body at the first side, wherein the
first contact trench includes a first conductive material electrically coupled to the semiconductor body adjoining the first
contact trench;

a plurality of second contact trenches extending through a second dielectric and into the semiconductor body at the second
side, wherein the second contact trench includes a second conductive material electrically coupled to the semiconductor body
adjoining the second contact trench, the first conductive material and the second conductive material being electrically disconnected,
wherein the plurality of second contact trenches differ by at least one of shape, layout, and depth;

a first contact pattern surrounded by the first dielectric at the first side; and
a second contact pattern surrounded by the second dielectric at the second side, wherein the first conductive material is
electrically coupled to a first semiconductor region of a first conductivity type via a sidewall of the first contact trench;
and the first conductive material is electrically coupled to a second semiconductor region of a second conductivity type via
a bottom side of the first contact trench, the second conductivity type being complementary to the first conductivity type,
and

wherein the second conductive material is electrically coupled to a third semiconductor region of the first conductivity type
via a sidewall of at least one of the second contact trenches; and the second conductive material is electrically coupled
to a fourth semiconductor region of the second conductivity type via a bottom side of at least one of the second contact trenches,

wherein the conductive material covers a surface of the semiconductor body at the second side and at least partly fills the
second trenches; and

wherein an outer surface of the conductive material at the second side is predominantly flat and includes a recess congruent
with the second contact trenches.

US Pat. No. 9,143,043

MULTI-MODE OPERATION AND CONTROL OF A RESONANT CONVERTER

Infineon Technologies AG,...

1. A method of controlling a switched-mode power supply, the method comprising:
generating a feedback signal proportional to an output of the switched-mode power supply;
operating the switched-mode power supply in a normal mode comprising adjusting a pulse modulated signal to regulate a feedback
signal to a first signal level, wherein the pulse modulated signal comprises a high-side switch signal and a low-side switch
signal;

when the feedback signal crosses a first threshold, operating the switched-mode power supply in a second operating mode comprising
periodically asserting the high-side switch signal and the low-side switch signal, wherein assertions of the high-side switch
signal alternate with assertions of the low-side switch signal with a dead-time between each assertion of the high-side switch
signal and each assertion of the low-side switch signal, and

adjusting the dead-time between each assertion of the high-side switch signal and each assertion of the low-side switch signal
to regulate a feedback signal to a second signal level different from the first signal level; and

driving a switch of the switched-mode power supply with the pulse modulated signal.

US Pat. No. 9,310,398

CURRENT SENSOR PACKAGE, ARRANGEMENT AND SYSTEM

Infineon Technologies AG,...

1. A current sensor package configured to sense a primary current flowing in a primary conductor of a substrate, the current
sensor package comprising:
a calibration current provider configured to provide a calibration current for a calibration conductor of the substrate, wherein
the calibration conductor and the primary conductor are arranged in a defined spatial relation to each other on the substrate,
and wherein the primary conductor and the calibration conductor are electrically isolated from each other;

a magnetic field sensor configured to sense a magnetic field of the primary current flowing in the primary conductor to provide
a primary sensor signal, and further configured to sense a magnetic field of the calibration current flowing through the calibration
conductor to provide a calibration sensor signal; and

a controller configured to receive the primary sensor signal and the calibration sensor signal, and configured to calibrate
the primary sensor signal based on the calibration sensor signal and the defined spatial relation between the primary conductor
and the calibration conductor.

US Pat. No. 9,614,045

METHOD OF PROCESSING A SEMICONDUCTOR DEVICE AND CHIP PACKAGE

INFINEON TECHNOLOGIES AG,...

1. A method of processing a semiconductor device, the method comprising:
providing a semiconductor device comprising a contact pad and a polymer layer; and
increasing a surface roughness of the polymer layer by subjecting at least a part of the contact pad and of the polymer layer
to a plasma comprising ammonia.

US Pat. No. 9,281,279

SEMICONDUCTOR DEVICE HAVING AN IDENTIFICATION MARK

Infineon Technologies AG,...

1. A semiconductor device, comprising:
a contact pad arranged over a front side of a chip, and comprising a metallic material, wherein the contact pad comprises
a side wall arranged at a periphery of the contact pad, wherein the side wall surrounds a flat surface of the contact pad
and the side wall protrudes from the flat surface, wherein the side wall comprises a first surface facing the chip, an exposed
second surface facing away from the chip, and an exposed side surface extending from the first surface to the second surface,
wherein the side surface is arranged at the periphery of the contact pad and defines a boundary of the contact pad;

an active area arranged over the front side of the chip and adjacent to the contact pad, wherein the active area comprises
an electronic component;

a conductive structure arranged under the contact pad, wherein the conductive structure forms at least a part of the electronic
component;

a structured dielectric layer arranged under the contact pad, wherein the structured dielectric layer comprises a first section
and a second section separated from the first section, wherein the structured dielectric layer forms at least a part of the
electronic component, wherein a form of the side wall of the contact pad is similar to a form of the first section of the
structured dielectric layer; and

an identification mark arranged over the contact pad and comprising a same metallic material as the contact pad, wherein the
identification mark is separated from the side wall of the contact pad and protrudes from the flat surface of the contact
pad, wherein the identification mark comprises information about a property of the chip, and wherein a form of the identification
mark is similar to a form of the second section of the structured dielectric layer, wherein the contact pad physically contacts
the conductive structure over a substantial area of the contact pad, and wherein the contact pad is separated from the conductive
structure by the structured dielectric layer at the side wall of the contact pad and at the identification mark.

US Pat. No. 9,244,134

XMR-SENSOR AND METHOD FOR MANUFACTURING THE XMR-SENSOR

Infineon Technologies AG,...

1. An XMR-sensor, comprising:
a substrate having a first main surface area and a second, different main surface area;
an XMR-structure comprising at least one section that extends along a first direction perpendicular to the first main surface
area or the second main surface area such that an XMR-plane of the XMR-structure is arranged in the first direction;

a first contact and a second contact arranged to contact the at least one section of the XMR-structure at different locations
of the XMR-structure; and

a current conductor configured to conduct a current therethrough, and generate a magnetic field parallel to the XMR-plane
of the XMR-structure in response to the conducting current,

wherein the substrate comprises at least two substrate layers stacked with respect to one another in the first direction,
wherein the first contact is arranged in or at a first substrate layer of the at least two substrate layers, and wherein the
second contact is arranged in or at a second substrate layer of the at least two substrate layers.

US Pat. No. 9,160,165

SEMICONDUCTOR DEVICE INCLUDING SHORT-CIRCUIT PROTECTION

INFINEON TECHNOLOGIES AG,...

1. A semiconductor device, comprising:
a semiconductor chip including a load current path operable to carry a load current from a supply terminal having a supply
voltage to an output circuit node in accordance with an input signal;

a voltage comparator coupled to the supply terminal and configured to compare the supply voltage with a voltage threshold
and to signal a low supply voltage when the supply voltage reaches or falls below the voltage threshold;

an over-current detector coupled to the load current path and configured to compare a load current signal that represents
the load current with an over-current threshold and to signal an over-current when the load current signal reaches or exceeds
the over-current threshold; and

a control logic unit configured to deactivate the load current flow when an over-current is signalled and further configured
to reduce the over-current threshold from a higher first value to a lower second value as long as the voltage comparator signals
a low supply voltage.

US Pat. No. 9,076,272

WHEEL SPEED SENSOR AND INTERFACE SYSTEMS AND METHODS

Infineon Technologies AG,...

1. A measurement system comprising:
a speed plus sensor comprising a magnetic field sensor configured to detect a magnetic field in response to speed and resonance
characteristics and generate a field sensor output;

a comparator component configured to receive the field sensor output and generate a comparator output by comparing the field
sensor output with a threshold;

a speed measurement component configured to receive the field sensor output and generate a speed measurement signal having
information relating to speed, based on frequency information from the field sensor output;

a summation component configured to add the speed measurement signal to the comparator output and generate a sensor output
signal, amplitude shifted with respect to the speed measurement signal, wherein the sensor output signal comprises speed data
and enhanced resonance data.

US Pat. No. 9,479,099

STATOR FLUX MAGNITUDE AND DIRECTION CONTROL STRATEGIES FOR PERMANENT MAGNET SYNCHRONOUS MOTORS

Infineon Technologies AG,...

1. A motor control system, comprising:
a transform component configured to receive current values associated with a motor being driven by the motor control circuit,
and output polar coordinate values representing a magnitude component and a direction component of a current space vector,
wherein the transform component comprises:

a Clarke transform component configured to receive the current values associated with respective phases of the motor being
drive, and convert the current values into a Cartesian space to obtain Cartesian current values of the current space vector;

a Cartesian to polar transform component configured to receive the Cartesian current values and convert such into the magnitude
component and the direction component of the current space vector; and

a subtraction circuit configured to subtract a position angle from the direction component to transform the direction component
from a stationary coordinate system to a rotating coordinate system; and

a control component configured to receive the magnitude component and the direction component of the current space vector,
and generate motor control signals for driving the motor, wherein the control component further comprises:

a magnitude controller configured to receive the magnitude component of the current space vector and a feedback control value
associated with a speed value and a reference value, and generate a magnitude of a voltage space vector based thereon, wherein
the speed value is calculated from the position angle;

a direction controller configured to control a direction of the voltage space vector to make a stator flux space vector perpendicular
to a rotor magnetic field of the motor being driven; and

an addition circuit to add the position angle to the voltage space vector to transform the voltage space vector from a rotating
coordinate system to a stationary coordinate system;

a polar to Cartesian transform component configured to receive the voltage space vector in the stationary coordinate system
and generate the voltage space vector in Cartesian coordinates in the stationary coordinate system; and

position estimator circuit configured to receive the voltage space vector from the polar to Cartesian transform component
and the current space vector from the Clark transform component, and generate the position angle as an estimate based on the
Cartesian coordinates of the voltage space vector and the Cartesian components of the current space vector.

US Pat. No. 9,387,797

DIRECTION INDICATOR CIRCUIT FOR CONTROLLING A DIRECTION INDICATOR IN A VEHICLE

Infineon Technologies AG,...

1. A direction indicator circuit for controlling a direction indicator in a vehicle, the direction indicator circuit comprising:
a first terminal for connecting to a supply voltage terminal;
a second terminal for connecting to a lighting means of a direction indicator and to a direction indicator switch;
a third terminal for connecting to a capacitor; and
at least one switch selected from the group consisting of a high side switch, a low side switch, and combinations thereof;
wherein a high side switch comprises voltages higher than the supply voltage when in an on state and comprises voltages lower
than the supply voltage when in an off state; wherein a low side switch comprises voltages lower than the supply voltage when
in an on state and comprises voltages higher than the supply voltage when in an off state;

wherein the direction indicator circuit is configured to provide the direction indicator with a current during an on state
and with no current during an off state, wherein the duration of the on state and the duration of the off state are determined
by the size of the capacitor;

wherein the capacitor is discharged essentially constantly during the on state, and wherein the capacitor is charged essentially
constantly during the off state.

US Pat. No. 9,279,856

DIE, CHIP, METHOD FOR DRIVING A DIE OR A CHIP AND METHOD FOR MANUFACTURING A DIE OR A CHIP

INFINEON TECHNOLOGIES AG,...

1. A die, comprising:
a physical unclonable function circuit providing output signals, wherein the output signals are dependent on at least one
physical characteristic specific to the die;

a self-test circuit integrated with the physical unclonable function circuit on the die, wherein the self-test circuit provides
a plurality of test input signals to the physical unclonable function circuit, evaluates the output signals respectively provided
in response to the plurality of test input signals, and determines as to whether the output signals provided in response to
the plurality of test input signals fulfill a predefined criterion, wherein the predefined criterion is that different test
input signals lead to different output signals when using the same physical unclonable function circuit and/or that the same
test input signals lead to different output signals when varying a function of the physical unclonable function circuit; and

an error handling circuit coupled to the self-test circuit, wherein the error handling circuit outputs an alarm signal indicating
that an error has been detected in the physical unclonable function circuit and/or a reset signal to set the die into a predefined
reset state in case the self-test circuit determines that the output signals provided in response to the plurality of test
input signals do not fulfill the predefined criterion.

US Pat. No. 9,202,760

SEMICONDUCTOR DEVICES AND STRUCTURES

Infineon Technologies AG,...

2. A semiconductor structure, comprising:
a first well of a first polarity provided in a substrate of a second polarity different from said first polarity,
a well contact provided in said first well of the first polarity to be coupled with a first supply voltage,
a semiconductor device in said first well,a second well of said second polarity with a higher doping concentration than said substrate arranged around said first well
of the first polarity, said second well of the second polarity being coupled to a resistive element that is distinct from
the substrate, said resistive element to be coupled with a second supply voltage and is located above the substrate;
a third well of said second polarity arranged in said first well of said first polarity and a fourth well of said second polarity
arranged in said first well of the first polarity, and a gate electrode on said substrate between said third well and said
fourth well;

a fifth well of said second polarity having a higher doping concentration than said substrate and being arranged in said substrate,
a distance between said fifth well of said second polarity and said second well of said second polarity being at least a predetermined
distance, the fifth well of said second polarity to be coupled with said second supply voltage via a connection having a resistance
smaller than the resistance of said resistive element.

US Pat. No. 9,281,360

SEMICONDUCTOR DEVICE WITH A SHIELDING STRUCTURE

Infineon Technologies AG,...

1. A semiconductor device, comprising:
a semiconductor body comprising a bottom side, a top side opposite the bottom side, and a surface surrounding the semiconductor
body;

an active semiconductor region formed in the semiconductor body;
an edge region surrounding the active semiconductor region;
a first semiconductor zone formed in the edge region, the first semiconductor zone having a first conduction type;
an edge termination structure formed in the edge region at the top side;
a shielding structure arranged on a side of the edge termination structure facing away from the bottom side, the shielding
structure comprising a number of N1?2 first segments and a number of N2?1 second segments, wherein:

each of the first segments is electrically connected to each of the other first segments and to each of the second segments;
each of the second segments has an electric resistivity higher than an electric resistivity of each of the first segments.

US Pat. No. 9,227,843

METHODS OF MANUFACTURING A MEMS DEVICE HAVING A BACKPLATE WITH ELONGATED PROTRUSIONS

Infineon Technologies AG,...

1. A method of forming a MEMS device, the method comprising:
providing a substrate; and
forming a backplate supported by the substrate, wherein the backplate comprises elongated protrusions, wherein forming the
backplate comprises forming a center region, and forming anchor bridges connected to the substrate, and wherein the elongated
protrusions are disposed on the anchor bridges.

US Pat. No. 9,231,520

WIEN-BRIDGE OSCILLATOR AND CIRCUIT ARRANGEMENT FOR REGULATING A DETUNING

Infineon Technologies AG,...

1. An oscillator circuit comprising:
a Wien-bridge comprising a first branch having a plurality of series connected resistors and a second branch having resistors
and capacitors, wherein a first feedback signal portion of zero detune based on a signal at a first node of the first branch
and a second feedback signal portion exhibiting detune based on a signal at a second node of the first branch are coupled
as feedback signals to the Wien-bridge;

a first differential amplifier for weighted amplification of the first feedback signal portion;
a second differential amplifier for weighted amplification of the second feedback signal portion; and
an amplitude detection block configured to detect an amplitude of an oscillation of the oscillator circuit and to control
a weighting factor.

US Pat. No. 9,190,389

CHIP PACKAGE WITH PASSIVES

Infineon Technologies AG,...

1. A chip package, comprising:
an electrically conducting chip carrier;
at least one semiconductor chip attached to the electrically conducting chip carrier;
an insulating laminate structure embedding the electrically conducting chip carrier and the at least one semiconductor chip;
and

an inductor comprising a first structured electrically conducting layer,
wherein the first structured electrically conducting layer extends in a first plane directly on a surface of the laminate
structure,

wherein the inductor further comprises a second structured electrically conducting layer extending in a second plane,
wherein the first structured electrically conducting layer forms a first coil of the inductor, the second structured electrically
conducting layer forms a second coil of the inductor, and the second coil is electrically coupled to the first coil,

wherein the electrically conducting chip carrier and the at least one semiconductor chip extend between the first plane and
the second plane.

US Pat. No. 9,183,413

METHOD AND SYSTEM FOR CONTROLLING A DEVICE

Infineon Technologies AG,...

1. A method of controlling a secure FPGA system comprising a secure microcontroller and an FPGA, the method comprising:
decrypting data that was encrypted using a first encryption scheme via the secure microcontroller;
re-encrypting the data using a second encryption scheme via the secure microcontroller;
sending the encrypted data to the FPGA coupled to the secure microcontroller; and
decrypting the encrypted data by a decryption engine in the FPGA,
wherein the FPGA has a programmable area and a hardwired area,
wherein the secure microcontroller and the FPGA are implemented on a single die or on multiple die in a package with a first
secure interface between the secure microcontroller and the FPGA programmable area and a second interface between the secure
microcontroller the FPGA hardwired area.

US Pat. No. 9,124,281

ACCURATE AND COST EFFICIENT LINEAR HALL SENSOR WITH DIGITAL OUTPUT

Infineon Technologies AG,...

1. A circuit, comprising:
a chopping generation circuit configured to receive an analog signal and to periodically switch a polarity of the analog signal
to generate a chopped signal having different polarities in temporally adjacent chopping phases;

an analog-to-digital converter (ADC) configured to convert the chopped signal to a digital signal;
a digital signal processing unit comprising a delay removal circuitry configured to generate a first and second digital signal
components from a same chopping phase of the digital signal, and a logic element configured to add or subtract the first and
second digital signal components from the same chopping phase to generate an offset compensated digital output signal;

a first signal path configured to provide the digital signal from the ADC to the logic element as the first digital signal
component; and

a second signal path having one or more delay removal elements configured to operate upon the digital signal to generate the
second digital signal component, which is provided to the logic element.

US Pat. No. 9,281,260

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME

INFINEON TECHNOLOGIES AG,...

1. A method of fabricating a semiconductor package, the method comprising:
forming a die opening in a laminate substrate, the laminate substrate having a front side and a back side;
placing a die within the die opening; and
forming a spacer around the die, the spacer disposed between the laminate substrate and an outer sidewall of the die, the
spacer partially extending over a portion of the die, the forming of the spacer including depositing a spacer material in
a first region around a perimeter of the die, and removing a portion of the spacer material from the first region to form
the spacer.

US Pat. No. 9,280,501

COMPATIBLE NETWORK NODE, IN PARTICULAR, FOR CAN BUS SYSTEMS

Infineon Technologies AG,...

9. A system, comprising:
a first component configured to receive and/or transmit data according to a first protocol or a first version of a first protocol;
a second component configured to receive and/or transmit data according to a second, different protocol or a second, different
version of the first protocol; and

a bus interconnecting the first and the second component;
wherein the first component and the second component each comprise an oscillator, the oscillator of the first component being
more precise than the oscillator of the second component.

US Pat. No. 9,622,341

POWER SEMICONDUCTOR MODULE SYSTEM HAVING A HIGH ISOLATION STRENGTH AND METHOD FOR PRODUCING A POWER SEMICONDUCTOR MODULE ARRANGEMENT HAVING A HIGH ISOLATION STRENGTH

Infineon Technologies AG,...

1. A power semiconductor module system, comprising:
a power semiconductor module comprising:
a module housing having a top side;
a first terminal group having at least one first electrical terminal, or having at least two first electrical terminals which
are permanently electrically conductively connected to one another;

a second terminal group having at least one second electrical terminal, or having at least two second electrical terminals
which are permanently electrically conductively connected to one another;

a circuit board having a first electrode and a second electrode, the circuit board being mountable on the power semiconductor
module in such a way that in the mounted state:

each first terminal is electrically conductively connected to the first electrode; and
each second terminal is electrically conductively connected to the second electrode,
wherein the power semiconductor module system further comprises one or both of the following isolation webs:
a first isolation web fixed to the circuit board even in an unmounted state and arranged between the first terminal group
and the second terminal group in a mounted state; and

a second isolation web fixed to the circuit board even in the unmounted state and arranged between the first terminal group
and the second terminal group in the mounted state on that side of the circuit board which faces away from the power semiconductor
module.

US Pat. No. 9,196,675

CAPACITOR AND METHOD OF FORMING A CAPACITOR

Infineon Technologies AG,...

1. A semiconductor device comprising:
a substrate;
a trench disposed in the substrate;
a first semiconductive electrode supported by trench sidewalls;
a dielectric layer disposed on the first semiconductive electrode;
a second semiconductive electrode disposed on the dielectric layer, wherein the second semiconductive electrode comprises
dielectric islands within the second semiconductive electrode; and

a second dielectric layer within the first semiconductive electrode.

US Pat. No. 9,258,110

PHASE DETECTOR

Infineon Technologies AG,...

1. A device comprising a phase detector, the phase detector comprising:
a frequency information input;
a phase information input;
an adder, the frequency information input being coupled with a first input of the adder and the phase information input being
coupled with a second input of the adder; and

a modulo operation coupled between the frequency information input and the first input of the adder, wherein the modulo operation
is an operation which outputs a rest of a division by N.

US Pat. No. 9,284,184

MEMS DEVICE AND METHOD OF MAKING A MEMS DEVICE

Infineon Technologies AG,...

1. A method of making an electrode of a MEMS device, the method comprising:
forming elongated radial openings in a mask layer, the mask layer disposed over a first sacrificial layer, the elongated radial
openings exposing first surface portions of the first sacrificial layer, the elongated radial openings leading away from a
center point of the first sacrificial layer;

forming first elongated isolation regions at the exposed first surface portions;
forming a second sacrificial layer over the first sacrificial layer;
forming a conductive layer over the second sacrificial layer;
removing a first portion of the first sacrificial layer forming a first spacer; and
removing a second portion of the second sacrificial layer forming a second spacer.

US Pat. No. 9,230,906

FEATURE PATTERNING METHODS AND STRUCTURES THEREOF

Infineon Technologies AG,...

1. A semiconductor device, comprising:
a first material layer and a second material layer disposed over a workpiece, the second material layer being adjacent the
first material layer;

a first portion of a feature being disposed in the first material layer;
a second portion of the feature being disposed in the first material layer proximate the first portion of the feature; and
a third portion of the feature being disposed in the second material layer, wherein the third portion of the feature couples
the first portion of the feature to the second portion of the feature, wherein the third portion of the feature is connected
to a dummy structure.

US Pat. No. 9,279,864

SENSOR DEVICE AND SENSOR ARRANGEMENT

Infineon Technologies AG,...

1. A vertical Hall sensor structure comprising:
a Hall effect region arranged between a first interface and a second interface of the Hall effect region;
a first contact, a second contact, a third contact, and a fourth contact, the first, second, third and fourth contacts being
closer to the first interface than to the second interface and in contact with the Hall effect region, wherein an electrical
resistance between the first and second contacts is substantially equal to an electrical resistance between the third and
second contacts; and

a conductive layer closer to the second interface than to the first interface and in contact with the Hall effect region,
the conductive layer comprising a higher conductivity than the Hall effect region;

wherein a resistance between the fourth contact and the conductive layer is lower than a resistance between the second contact
and the conductive layer.

US Pat. No. 9,252,354

VERTICAL HALL DEVICE WITH HIGHLY CONDUCTIVE OPPOSITE FACE NODE FOR ELECTRICALLY CONNECTING FIRST AND SECOND HALL EFFECT REGIONS

Infineon Technologies AG,...

1. A vertical Hall device comprising:
a first Hall effect region and a second Hall effect region different from the first Hall effect region, both Hall effect regions
in a common semiconductor body, the first Hall effect region and the second Hall effect region having a main face and an opposite
face, respectively;

a highly conductive opposite face node in common ohmic contact to the opposite face of the first Hall effect region and to
the opposite face of the second Hall effect region in the semiconductor body;

a first pair of contacts in or at the main face of the first Hall effect region; and
a second pair of contacts in or at the main face of the second Hall effect region, wherein a convex circumscribing contour
of the second pair of contacts is disjoint from a convex circumscribing contour of the first pair of contacts, in that a straight
line between any two points within the contacts of the first pair of contacts does not contain any point within the contacts
of the second pair of contacts, and a straight line between any two points within the contacts of the second pair of contacts
does not contain any point within the contacts of the first pair of contacts.

US Pat. No. 9,240,225

CURRENT SENSE AMPLIFIER WITH REPLICA BIAS SCHEME

Infineon Technologies AG,...

1. A sense amplifier for sensing a data value from a senseline coupled to a memory cell, the sense amplifier comprising:
first and second current source transistors configured to provide first and second currents, respectively, along first and
second current paths, respectively, wherein the first current path is coupled to the senseline and wherein the second current
path is coupled to a reference senseline;

first and second cascode transistors arranged in series with the first and second current source transistors, respectively,
and arranged on the first and second current paths, respectively;

first and second current mirror transistors arranged in series with the first and second cascode transistors, respectively,
and arranged on the first and second current paths, respectively, wherein the respective cascode transistors are disposed
between the respective current source transistors and the respective current mirror transistors on the first and second current
paths; and

a pre-charge circuit configured to establish a pre-charge condition on the senseline, wherein the pre-charge circuit comprises:
a pre-charge transistor having a gate, a source coupled to a supply voltage node, and a drain coupled to the senseline; and
a third cascode transistor having a source coupled to the senseline and having a drain coupled to the gate of the pre-charge
transistor via a feedback path.

US Pat. No. 9,279,883

METHOD AND DEVICE FOR RADAR APPLICATIONS

Infineon Technologies AG,...

20. A vehicle comprising a radar system for processing radar signals, said system comprising a first device and a second device,
wherein the first device comprises:
a first computing engine;
a first radar acquisition unit connected to the first computing engine;
a first timer unit connected to the first computing engine;
a first cascade input port; and
a first cascade output port,
wherein the first cascade input port is configured to convey an input signal to the first computing engine, and
wherein the first cascade output port is configured to convey an output signal from the first computing engine; and
wherein the second device comprises:
a second computing engine;
a second radar acquisition unit connected to the second computing engine;
a second timer unit connected to the second computing engine;
a second cascade input port; and
a second cascade output port,
wherein the second cascade input port is configured to convey an input signal to the second computing engine, and
wherein the second cascade output port is configured to convey an output signal from the second computing engine, and
wherein the first cascade output port of the first device is connected to the second cascade input port of the second device.

US Pat. No. 9,269,685

INTEGRATED CIRCUIT PACKAGE AND PACKAGING METHODS

INFINEON TECHNOLOGIES AG,...

1. An integrated circuit package comprising:
a package module formed from successive build-up layers which define circuit interconnections, the successive build-up layers
comprising a laminate;

a cavity formed within the package module at a top-side of the package module;
a chip having a front side with at least one forward contact and having a back-side, the chip disposed in the cavity such
that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package
module;

a top layer coupled to the back-side of the chip, the top layer electrically connected to a bottom side of the package module
through one or more integral vias, each of the integral vias substantially vertically extending from the top-side of the package
module through to the bottom side of the package module, the top layer covering at least a part of the chip and the top-side
of the package module; and

a metal foil layer coupled onto the top layer by an adhesive.

US Pat. No. 9,263,552

MOS-TRANSISTOR WITH SEPARATED ELECTRODES ARRANGED IN A TRENCH

Infineon Technologies AG,...

1. A method for producing a trench transistor, the method comprising:
providing a semiconductor body;
forming a first trench in the semiconductor body, the first trench comprising two side walls and a bottom surface;
forming a first isolation layer on inner surfaces of the first trench;
filling the first trench with conductive material to form a first electrode within the first trench;
removing a portion of the first electrode along one of the side walls of the first trench to form a cavity in the first electrode,
the cavity being located within the first trench;

forming a second isolation layer on inner surfaces of the cavity;
at least partially filling the cavity with conductive material to form a second electrode within the cavity;
forming a structured third isolation layer on a top surface of the semiconductor body; and
forming a metallization layer on the structured third isolation layer, wherein the first or the second electrode is electrically
and thermally connected to the metallization layer via openings in the structured third isolation layer.

US Pat. No. 9,373,596

PASSIVATED COPPER CHIP PADS

Infineon Technologies AG,...

1. A method for forming a semiconductor component, the method comprising:
forming a cap layer over a last metal line of an inter level dielectric layer;
forming a passivation layer over the cap layer;
forming a insulating liner over the passivation layer;
forming an opening in the cap layer, the passivation layer, and the insulating liner, wherein the opening exposes a portion
of the last metal line;

forming a conductive liner on surfaces of the opening by
depositing the conductive liner on the opening and over the passivation layer and the insulating liner,
depositing and patterning a photoresist layer, and
using the patterned photo resist as a mask to remove the conductive liner from over the insulating liner by using an etching
process, wherein the conductive liner is removed entirely from over the insulating liner except over sidewalls of the opening,
wherein the sidewalls of the conductive liner remaining after the etching process comprise a vertical section extending above
a top surface of the passivation layer and a slanted section intersecting the vertical section; and

depositing an under bump metallization layer over the conductive liner.

US Pat. No. 9,312,338

SEMICONDUCTOR DEVICE CONTAINING CHALCOGEN ATOMS AND METHOD OF MANUFACTURING

Infineon Technologies AG,...

1. A semiconductor device, comprising:
a single-crystalline semiconductor body with a first surface and a second surface parallel to the first surface, the semiconductor
body containing chalcogen atoms and a background doping of pnictogen atoms, wherein a concentration of the chalcogen atoms
is at least 1E12 cm?3 and a ratio of the chalcogen atoms to the pnictogen atoms of the background doping is in a range from 1:9 to 9:1 and

wherein the semiconductor body comprises a drift zone extending parallel to the first surface and spaced from both the first
and second surface, wherein an effective dopant concentration in the drift zone is defined by the chalcogen atoms and the
background doping of pnictogen atoms in the semiconductor body.

US Pat. No. 9,171,804

METHOD FOR FABRICATING AN ELECTRONIC COMPONENT

Infineon Technologies AG,...

1. An electronic component, comprising:
a carrier;
a semiconductor chip comprising a main face;
a connection layer disposed on the main face of the semiconductor chip, the connection layer comprising a plurality of depressions,
wherein the connection layer is disposed between the semiconductor chip and the carrier, and wherein the depressions or part
of them have a depth so that they do not reach the main face of the semiconductor chip; and

a filler material disposed in the depressions of the connection layer.

US Pat. No. 9,319,779

SYSTEM AND METHOD FOR TRANSDUCER BIASING AND SHOCK PROTECTION

Infineon Technologies AG,...

1. An interface circuit comprising:
an amplifier configured to be coupled to a transducer;
a first bypass circuit coupled to a first voltage reference and the amplifier, wherein the first bypass circuit is configured
to conduct a first current when an input signal amplitude greater than a first threshold is applied to the transducer;

a second bypass circuit coupled to the first voltage reference and the amplifier; and
a control circuit coupled to the second bypass circuit and configured to cause the second bypass circuit to conduct a second
current for a first time period after the first bypass circuit conducts the first current.

US Pat. No. 9,275,878

METAL REDISTRIBUTION LAYER FOR MOLDED SUBSTRATES

Infineon Technologies AG,...

6. A molded semiconductor package, comprising:
a semiconductor die embedded in a molding compound, the semiconductor die having a plurality of terminals at a side uncovered
by the molding compound, the molding compound contacting edge faces of the semiconductor die, the edge faces extending perpendicular
to the side uncovered by the molding compound; and

a metal redistribution layer in direct contact with the terminals of the semiconductor die and extending beyond a lateral
edge of the semiconductor die onto the molding compound, the metal redistribution layer directly contacting the same molding
compound that contacts the edge faces of the semiconductor die, wherein the metal redistribution layer comprises pad structures
in direct contact with the terminals of the semiconductor die and the same molding compound that contacts the edge faces of
the semiconductor die, the pad structures having a larger surface area than the terminals of the semiconductor die.

US Pat. No. 9,525,426

CROSS-COUPLED INPUT VOLTAGE SAMPLING AND DRIVER AMPLIFIER FLICKER NOISE CANCELLATION IN A SWITCHED CAPACITOR ANALOG-TO-DIGITAL CONVERTER

Infineon Technologies AG,...

1. A switched capacitor system comprising:
a switching stage comprising a plurality of switches configured to receive a differential signal at an input of the switching
stage and provide a non-inverted version of the differential signal at an output of the switching stage during a first phase
of operation and an inverted version of the differential signal at the output of the switching stage during a second phase
of operation;

a driver stage comprising a first amplifier, the driver stage located downstream of the switching stage;
a sampling capacitor stage configured to sample an output of the driver stage during the first phase of operation and an output
of the driver stage the second phase of operation;

a switching controller configured to control a cross coupled configuration of the plurality of switches in order to select
the first or second phase of operation; and

an integrator circuit coupled to an output of the sampling capacitor stage, wherein the integrator circuit comprises first
and second feedback paths connected in parallel between a first input and a first output of the integrator circuit, wherein
the first feedback path is configured to sample a portion of a sampling capacitor output signal in the first phase of operation
and the second feedback path is configured to integrate a portion of a further sampling capacitor output signal in the second
phase of operation.

US Pat. No. 9,362,193

CHIP ARRANGEMENT, A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT, INTEGRATED CIRCUITS AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT

Infineon Technologies AG,...

1. An integrated circuit, comprising:
an electrically conductive carrier;
a chip mounted on a top side of the carrier;
encapsulation material at least partially covering the chip and the carrier;
at least one interconnect disposed within the encapsulation material electrically connecting the chip to the carrier;
a layer stack disposed over the carrier on a bottom side of the carrier opposite the top side of the carrier, the layer stack
comprising:

a plurality of discrete polymer layers, wherein at least one of the polymer layers is disposed over the carrier and disposed
on at least a portion of a bottom side of the encapsulation material; and

one or more discrete ceramic layers, wherein at least one of the ceramic layers is disposed between a pair of the plurality
of the polymer layers;

wherein a first layer and a last layer of the layer stack is each a polymer layer; wherein the first layer of the layer stack
is connected to the last layer of the polymer stack so that the first layer and the second layer wrap around the layer stack;

wherein the carrier comprises an extension so that the encapsulation material and the layer stack do not cover any surface
of the carrier extension.

US Pat. No. 9,293,524

SEMICONDUCTOR DEVICE WITH A FIELD RING EDGE TERMINATION STRUCTURE AND A SEPARATION TRENCH ARRANGED BETWEEN DIFFERENT FIELD RINGS

Infineon Technologies AG,...

1. A semiconductor device, comprising:
a semiconductor body comprising a bottom side, a top side opposite the bottom side, and a lateral surface;
an active semiconductor region formed in the semiconductor body;
an edge region surrounding the active semiconductor region;
a first semiconductor zone formed in the edge region, the first semiconductor zone having a first conduction type; and
an edge termination structure formed in the edge region and comprising at least N field limiting structures, each of the field
limiting structures comprising a field ring, and a separation trench formed in the semiconductor body, wherein:

N?2;
each of the field rings has a second conduction type complementary to the first conduction type and forms a pn-junction with
the first semiconductor zone;

each of the field rings surrounds the active semiconductor region; and
for each of the field limiting structures, the separation trench of that field limiting structure is arranged between the
field ring of that field limiting structure and the active semiconductor region, wherein

one of the separation trenches is arranged between a first one of the field rings and a second one of the field rings, wherein
there is no further field ring arranged between the first one of the field rings and the second one of the field rings;

the first field ring surrounds the one of the separation trenches and the one of the separation trenches surrounds the second
field ring; and

a distance between the one of the separation trenches and the first field ring is less than a distance between the one of
the separation trenches and the second field ring.

US Pat. No. 9,281,746

SYSTEM AND METHOD FOR A DIAGNOSTIC CIRCUIT

Infineon Technologies AG,...

17. A diagnostic circuit configured to be coupled to an output terminal of a half-bridge switching circuit and to a sense
terminal of a sense circuit coupled in parallel with the half-bridge switching circuit, the diagnostic circuit comprising:
a sense amplifier comprising a first sense input configured to be coupled to the output terminal and a second sense input
configured to be coupled to the sense terminal;

a gain stage coupled to a first sense output of the sense amplifier and a second sense output of the sense amplifier;
a crossbar switch coupled between the sense amplifier and the gain stage and coupled to a select input, wherein the crossbar
switch is configured to switch the coupling of the sense amplifier and the gain stage based on the select input;

a configurable current source coupled to the sense terminal and the select input, wherein the configurable current source
is configured to be controlled based on the select input; and

a feedback transistor having a conduction terminal coupled to the configurable current source and a control terminal coupled
to an output of the gain stage, wherein the output of the gain stage is proportional to a current flowing in the half-bridge
switching circuit.

US Pat. No. 9,888,601

SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR PRODUCING A SEMICONDUCTOR MODULE ARRANGEMENT

Infineon Technologies AG,...

1. A semiconductor module arrangement, comprising:
a first subassembly having a number N1 of first adjustment openings;
a second subassembly having a number N2 of second adjustment openings; and
a third subassembly having a plurality of adjustment pins which are fixedly connected to one another,
wherein a first set of the plurality of adjustment pins extend beyond a top surface of the third assembly,
wherein a second set of the plurality of adjustment pins extend beyond a bottom surface of the third assembly,
wherein each pin of the first set of the plurality of adjustment pins is vertically aligned with a corresponding pin of the
second set of the plurality of adjustment pins to form a pair of vertically aligned adjustment pins,

wherein each of the first set of the plurality of adjustment pins engages into one of the first adjustment openings,
wherein each of the second set of the plurality of adjustment pins engages into one of the second adjustment openings,
wherein the plurality of adjustment pins constitutes an integral constituent part of the third subassembly prior to the subassemblies
being connected to one another.

US Pat. No. 9,564,423

POWER PACKAGE WITH INTEGRATED MAGNETIC FIELD SENSOR

Infineon Technologies AG,...

1. A power semiconductor package, comprising:
a substrate having a plurality of metal leads;
a power semiconductor die attached to a first one of the leads;
a metal clip included in the power semiconductor package, the metal clip electrically connecting one or more of the leads
to the power semiconductor die or to another one of the leads; and

a magnetic field sensor positioned over or under, and galvanically isolated from, the metal clip, and located in close proximity
to a current pathway of the power semiconductor die, the magnetic field sensor being operable to generate a signal in response
to a magnetic field produced by current flowing in the current pathway, the magnitude of the signal being proportional to
the amount of current flowing in the current pathway.

US Pat. No. 9,313,851

STANDBY POWER FOR LED DRIVERS

Infineon Technologies AG,...

1. A method comprising:
regulating a first parameter of one or more light emitting diodes (LEDs) connected to one or more components; and
switching, in response to an indication from a dimmer interface, from regulating the first parameter of the one or more LEDs
to regulating a second parameter below a light generation threshold of the one or more LEDs, wherein switching from regulating
the first parameter to regulating the second parameter causes the one or more LEDs to enter a non-light generation mode;

wherein the switching from regulating the first parameter to regulating the second parameter is performed by adjusting a winding
ratio between a secondary winding of a transformer and an auxiliary winding of the transformer.

US Pat. No. 9,888,563

ELECTRONICS ASSEMBLY WITH INTERFERENCE-SUPPRESSION CAPACITORS

Infineon Technologies AG,...

1. An electronics assembly, comprising:
a plurality of first semiconductor chips each comprising a first load terminal and a second load terminal;
a conductor structure comprising a first conductor strip, a second conductor strip and a third conductor strip;
a plurality of first interference-suppression capacitors arranged on the conductor structure and each comprising a first capacitor
terminal and a second capacitor terminal; and

a heat sink,
wherein the first load terminal of each first semiconductor chip is electrically connected to the first conductor strip,
wherein the second load terminal of each first semiconductor chip is electrically connected to the third conductor strip,
wherein the first capacitor terminal of each first interference-suppression capacitor is electrically connected to the first
conductor strip,

wherein the second capacitor terminal of each first interference-suppression capacitor is electrically connected to the second
conductor strip,

wherein the heat sink is electrically connected to the second conductor strip.

US Pat. No. 9,312,226

SEMICONDUCTOR DEVICE HAVING AN IDENTIFICATION MARK

Infineon Technologies AG,...

1. A semiconductor device, comprising:
a contact pad arranged over a front side of a chip, and comprising a metallic material, wherein the contact pad comprises
a side wall arranged at a periphery of the contact pad, wherein the side wall surrounds a flat surface of the contact pad
and the side wall protrudes from the flat surface, wherein the side wall comprises a first surface facing the chip, an exposed
second surface facing away from the chip, and an exposed side surface extending from the first surface to the second surface,
wherein the side surface is arranged at the periphery of the contact pad and defines a boundary of the contact pad;

an active area arranged over the front side of the chip and adjacent to the contact pad, wherein the active area comprises
an electronic component;

a conductive structure arranged under the contact pad, wherein the conductive structure forms at least a part of the electronic
component;

a structured dielectric layer arranged under the contact pad, wherein the structured dielectric layer comprises a first section
and a second section separated from the first section, wherein the structured dielectric layer forms at least a part of the
electronic component, wherein a form of the side wall of the contact pad is similar to a form of the first section of the
structured dielectric layer; and

an identification mark arranged over the contact pad and comprising a same metallic material as the contact pad, wherein the
identification mark is separated from the side wall of the contact pad and protrudes from the flat surface of the contact
pad, wherein the identification mark comprises information about a property of the chip, and wherein a form of the identification
mark is similar to a form of the second section of the structured dielectric layer, wherein the contact pad physically contacts
the conductive structure over a substantial area of the contact pad, and wherein the contact pad is separated from the conductive
structure by the structured dielectric layer at the side wall of the contact pad and at the identification mark.

US Pat. No. 9,148,923

DEVICE HAVING A PLURALITY OF DRIVER CIRCUITS TO PROVIDE A CURRENT TO A PLURALITY OF LOADS AND METHOD OF MANUFACTURING THE SAME

Infineon Technologies AG,...

1. A device, comprising:
a substrate having a first side and a second side opposite the first side, the substrate comprising a plurality of driver
circuits at the first side of the substrate, wherein each of the plurality of driver circuits is configured to drive a current
from the first side of the substrate to the second side of the substrate; and

at least one load interface at the second side of the substrate, wherein the at least one load interface is configured to
couple the current from the plurality of the driver circuits to a plurality of loads at the second side of the substrate.

US Pat. No. 9,070,642

ELECTRONIC MODULE

Infineon Technologies AG,...

1. An electronic module comprising:
a passive component having an upper surface of a first area; and
a first semiconductor chip having a lower surface of a second area that is smaller than the first area, wherein the lower
surface of the first semiconductor chip is arranged on the upper surface of the passive component, wherein the first semiconductor
chip is electrically and mechanically attached to the passive component, and wherein the first semiconductor chip comprises
a vertical field-effect transistor.

US Pat. No. 9,368,573

METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A method for manufacturing a semiconductor device, the method comprising:
forming a first source/drain region within a first well region;
forming a second source/drain region within a second well region;
forming an active region electrically coupled between the first source/drain region and the second source/drain region, wherein
the active region comprises a region of lower doping concentration disposed between the first well region and the second well
region, wherein the region of lower doping concentration has a doping concentration lower than a doping concentration of each
of the first well region and the second well region;

forming a trench disposed between the second source/drain region and at least a portion of the active region;
forming a first isolation layer on a bottom and sidewalls of the trench;
forming electrically conductive material in the trench, wherein the electrically conductive material is disposed over the
first isolation layer;

forming a second isolation layer above the active region; and
forming a gate region above the second isolation layer;
wherein the electrically conductive material is coupled to the gate region, and
wherein the first well region is spaced apart from the second well region by the active region.

US Pat. No. 9,175,943

ANGLE MEASUREMENT SYSTEM INCLUDING MAGNET WITH SUBSTANTIALLY SQUARE FACE FOR THROUGH-SHAFT APPLICATIONS

Infineon Technologies AG,...

1. An angle measurement system, comprising:
a shaft extending along a shaft axis and configured to axially rotate thereabout;
a magnet including first and second surfaces, wherein the first and second surfaces include first and second apertures, respectively,
and wherein the first and second apertures define extents of a through-hole in the magnet through which the shaft extends
so opposing ends of the shaft extend entirely through the magnet and past the first and second surfaces, and

an angle sensor configured to measure a time-varying magnetic field produced by the magnet as the shaft rotates, wherein the
angle sensor includes a sensing region that is positioned over the first surface of the magnet and is radially spaced apart
from a sidewall of the shaft;

where the shaft is adapted to rotate through an absolute angle of more than three-hundred and sixty degrees about the shaft
axis.

US Pat. No. 9,450,436

ACTIVE POWER FACTOR CORRECTOR CIRCUIT

Infineon Technologies AG,...

1. A device for charging a battery, the device comprising a power factor converter comprising a controller configured to produce
a first switching frequency for a first load current or voltage and a second switching frequency for a second load current
or load voltage, wherein the first switching frequency and the second switching frequency are determined based on a battery
charging curve.

US Pat. No. 9,248,709

RFID-TAG, A TPMS DEVICE, A TIRE, A RECEIVER DEVICE AND A METHOD FOR PROVIDING INFORMATION RELATED TO IDENTIFICATION OF A TIRE

Infineon Technologies AG,...

1. An RFID-tag for providing information related to a permanent tire identification, comprising:
a memory module configured to store the information related to the permanent tire identification; and
a transmitter module configured to transmit the information related to the permanent tire identification to a receiver device,
the RFID-tag being configured to be coupled to a TPMS device.

US Pat. No. 9,449,902

SEMICONDUCTOR PACKAGES HAVING MULTIPLE LEAD FRAMES AND METHODS OF FORMATION THEREOF

Infineon Technologies AG,...

21. A semiconductor package comprising:
a first lead frame having a first major surface and a second major surface;
a second lead frame, wherein the first lead frame is disposed over the second lead frame; and
a vertical power chip, wherein the first lead frame is disposed between the vertical power chip and the second lead frame,
the vertical power chip comprising a semiconductor body that includes gallium nitride (GaN), a source region disposed in the
semiconductor body and electrically coupled to the first major surface of the first lead frame, a drain region disposed in
the semiconductor body and electrically coupled to the first major surface of the first lead frame, and a gate region electrically
coupled to a gate contact region of a gate lead of the first lead frame, wherein the gate contact region overlaps with and
mechanically supports a major surface of the power chip.

US Pat. No. 9,283,864

CIRCUIT, ELECTRIC POWER TRAIN AND METHOD FOR CHARGING A BATTERY

INFINEON TECHNOLOGIES AG,...

1. A circuit, comprising:
a battery;
an omnipolar switch coupled to the battery and configured to electrically disconnect the battery;
a DC-intermediate circuit coupled to the omnipolar switch via a switching element,
a current supplying device coupled to the DC-intermediate circuit; and
a control unit configured to operate the switching element depending on at least one of the following:
a voltage difference between a voltage of the current supplying device and
a voltage of the battery exceeding a voltage threshold;
a current flowing from the current supplying device to the battery exceeding a current threshold; and
a temperature exceeding a temperature threshold.

US Pat. No. 9,245,760

METHODS OF FORMING EPITAXIAL LAYERS ON A POROUS SEMICONDUCTOR LAYER

Infineon Technologies AG,...

1. A method of forming a semiconductor device, the method comprising:
forming a first porous semiconductor layer over a top surface of a substrate;
forming a first epitaxial layer over the first porous semiconductor layer, wherein forming the first porous semiconductor
layer comprises depositing an epitaxial layer and electrochemically etching at least a portion of the epitaxial layer, wherein
depositing the epitaxial layer comprises forming a first layer having a first doping, and a second layer having a second doping
different from the first layer;

forming stressor structures in the first epitaxial layer;
forming circuitry within and over the first epitaxial layer, wherein the circuitry is formed without completely oxidizing
the first epitaxial layer;

forming a second porous semiconductor layer between the top surface of the substrate and the first porous semiconductor layer;
forming a second epitaxial layer between the first porous semiconductor layer and the second porous semiconductor layer;
thinning the substrate from a back surface to form an intermediate structure; and
dicing the intermediate structure to form singulated chips, wherein the thinning removes the second porous semiconductor layer,
and wherein the thinning is stopped before reaching the first porous semiconductor layer.

US Pat. No. 9,240,800

SYSTEM THAT OBTAINS A SWITCHING POINT WITH THE ENCODER IN A STATIC POSITION

Infineon Technologies AG,...

1. A system comprising:
an encoder having a pole pitch and configured to rotate in a direction of rotation;
multiple sensing elements situated along the direction of rotation and spanning at least half the length of the pole pitch,
the sensing elements providing cyclical signals having maximum and minimum values based on rotation of the encoder; and

control logic configured to receive the signals from the multiple sensing elements, and when the encoder is at a static position,
configured to determine a switching point based on the signals from each of the multiple sensing elements, wherein the switching
point is a midpoint between the maximum and minimum values.

US Pat. No. 9,196,577

SEMICONDUCTOR PACKAGING ARRANGEMENT

Infineon Technologies AG,...

1. A semiconductor packaging arrangement, comprising:
a transistor device comprising a first side, the first side comprising a source electrode and a gate electrode;
a die pad comprising a first surface, and
a lead comprising a first surface,
wherein a first conductive member is arranged between the source electrode and the first surface of the die pad and spaces
the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate
electrode and the first surface of the lead.

US Pat. No. 9,305,798

DEVICE AND METHOD FOR STOPPING ETCHING PROCESS

Infineon Technologies AG,...

1. A method for etching a layer assembly comprising an intermediate layer sandwiched between an etch layer and a stop layer,
the method comprising:
in a region for forming a via contact to a contact portion of the stop layer, etching the etch layer using a first etchant,
the etch layer comprising a first material and the first etchant comprising a first etch selectivity with respect to the etch
layer and the intermediate layer; and

etching the intermediate layer using a second etchant, the second etchant comprising a second etch selectivity with respect
to the intermediate layer and the stop layer, wherein the second etchant is different from the first etchant, wherein the
etch layer has a planar lower surface adjacent the intermediate layer and a non-planar upper surface over the contact portion
of the stop layer, and wherein a thickness of the etch layer overlying the contact portion of the stop layer varies more than
10% around a mean value, wherein the etch layer has a variable thickness in the region to be etched for forming the via contact,
and wherein the thickness is measured from the planar lower surface to the non-planar upper surface.

US Pat. No. 9,245,811

METHOD FOR POSTDOPING A SEMICONDUCTOR WAFER

Infineon Technologies AG,...

1. A method for treating a semiconductor wafer having a basic doping, wherein the method comprises:
determining a doping concentration of the basic doping; and
adapting the basic doping of the semiconductor wafer by postdoping comprising
a proton implantation and a subsequent thermal process for producing hydrogen induced donors,
wherein at least one of the following parameters is dependent on the determined doping concentration of the basic doping:
an implantation dose of the proton implantation, and
a temperature of the thermal process,
wherein the semiconductor wafer has a first side,
wherein the proton implantation is carried out via the first side, and
wherein the proton implantation comprises at least two proton implantation acts in which protons are implanted with different
implantation energies.

US Pat. No. 9,196,562

SEMICONDUCTOR ARRANGEMENT, SEMICONDUCTOR MODULE, AND METHOD FOR CONNECTING A SEMICONDUCTOR CHIP TO A CERAMIC SUBSTRATE

Infineon Technologies AG,...

1. A semiconductor arrangement comprising:
a silicon body having a top surface and a bottom surface;
a thin electrically conductive adhesion layer deposited on the top surface of said silicon body;
a thick metal layer arranged on the thin electrically conductive adhesion layer, said thick metal layer having a bonding surface
facing away from the top surface of said silicon body;

a bonding wire having a diameter of at least 300 micrometers (?m) or a bonding ribbon having a thickness of at least 200 micrometers
(?m) bonded to said thick metal layer at the bonding surface of said thick metal layer; and

wherein the thickness of said thick metal layer is at least 10 micrometers (?m), said thick metal layer comprises copper or
a copper alloy, and said bonding wire or bonding ribbon comprises copper or a copper-based material.

US Pat. No. 9,157,939

SYSTEM AND DEVICE FOR DETERMINING ELECTRIC VOLTAGES

Infineon Technologies AG,...

1. A system for measuring electric voltages in batteries with a plurality of individual battery cells, the system comprising:
a digital analog converter (DAC);
a plurality of comparators;
wherein the DAC and the comparators are coupled together to form a measuring circuit with an analog digital converter (ADC);
wherein the measuring circuit is configured to determine the electric voltages of the individual battery cells; and
wherein the comparators compare a reference voltage generated by the DAC with the electric voltage of the battery cells over
a number of separate measuring channels to the individual battery cells.

US Pat. No. 9,918,367

CURRENT SOURCE REGULATION

Infineon Technologies AG,...

1. A circuit, comprising:
monitor circuitry that is configured to, for at least one LED (Light Emitting Diode) driver of a plurality of LED drivers:
generate a signal to indicate that a voltage drop across the at least one LED driver is outside of a bounded range of voltage
values, wherein the voltage drop is determined based on a drive voltage that is output by the at least one LED driver to source
current to an LED that is coupled thereto and a supply voltage that is output by a power supply to each LED driver of the
plurality of LED drivers, and wherein the signal represents a condition that the voltage drop across the at least one LED
driver is less than or equal to a minimum voltage value of the bounded range of voltage values or a condition that the voltage
drop across the at least one LED driver is greater than or equal to a maximum voltage value of the bounded range of voltage
values; and

controller circuitry that is configured to:
receive the signal from the monitor circuitry; and
based on the signal, increase or decrease magnitude of the supply voltage that is output by the power supply to force the
voltage drop across the at least one LED driver to a voltage value within the bounded range of voltage values.

US Pat. No. 9,310,554

INTEGRATED CIRCUIT INCLUDING NON-PLANAR STRUCTURE AND WAVEGUIDE

Infineon Technologies AG,...

1. An integrated circuit comprising:
a substrate;
an insulation layer positioned over the substrate;
a structure including a fin that extends substantially perpendicular to the insulation layer;
a waveguide that extends over the insulation layer to the fin, and extends over the fin, where the wave guide provides electromagnetic
waves to the structure, and wherein the structure provides a signal in response to at least some of the electromagnetic waves.

US Pat. No. 9,196,510

SEMICONDUCTOR PACKAGE COMPRISING TWO SEMICONDUCTOR MODULES AND LATERALLY EXTENDING CONNECTORS

Infineon Technologies AG,...

1. A semiconductor package, comprising:
a mold body comprising a first main face, a second main face opposite to the first main face and side faces connecting the
first and second main faces;

a first semiconductor module comprising a plurality of first semiconductor chips and a first encapsulation layer disposed
above the first semiconductor chips;

a second semiconductor module disposed above the first semiconductor module, the second semiconductor module comprising at
least one second semiconductor chip and a second encapsulation layer disposed above the at least one second semiconductor
chip; and

a plurality of external connectors extending through one or more of the side faces of the mold body,
wherein the external connectors are mechanically connected to the second semiconductor module.

US Pat. No. 9,171,777

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A power semiconductor device comprising a semiconductor device, the semiconductor device comprising:
a semiconductor substrate comprising a main surface with a polygonal geometry, wherein the semiconductor substrate comprises
a thickness of less than 120 ?m;

a main electric circuit manufactured within a main region on the semiconductor substrate, wherein the main electric circuit
is operable to perform an electric main function,

wherein the main region extends over the main surface of the semiconductor substrate leaving open a corner area at every corner
of the polygonal geometry of the main surface of the semiconductor substrate, wherein each corner area extends at least 500
?m along the edges of the semiconductor substrate beginning at the corners; and

an electric test circuit manufactured within at least one corner area on the semiconductor substrate, wherein the electric
test circuit is operable to enable an electrical test function,

wherein at least one active element of the main electric circuit comprises a breakdown voltage higher than 10V.

US Pat. No. 9,076,540

SYMMETRICAL DIFFERENTIAL SENSING METHOD AND SYSTEM FOR STT MRAM

Infineon Technologies AG,...

1. A system for reading a memory cell, comprising:
a reference source configured to provide a reference current for the memory cell;
a first sampling element selectively coupled to the reference source and configured to sample and hold the reference current;
and

a second sampling element selectively coupled to the memory cell and configured to sample and hold a cell current from the
memory cell;

wherein the reference current and the memory cell current are subsequently switched via a switching circuit such that the
reference current flows through the second sampling element and the cell current flows through the first sampling element.

US Pat. No. 9,373,717

STRESS-INDUCING STRUCTURES, METHODS, AND MATERIALS

Infineon Technologies AG,...

1. An isolation structure comprising:
a trench disposed in a workpiece;
a first insulating material disposed in a lower portion of the trench;
a stress-inducing material disposed over the first insulating material; and
a divot comprising a gutter-shaped depression disposed in the stress-inducing material.

US Pat. No. 9,304,153

SYSTEM AND METHOD FOR POWER SUPPLY TESTING

Infineon Technologies AG,...

1. A method of verifying a component coupled to an output of a switched mode power supply, the method comprising:
measuring a frequency response from a control input of the switched mode power supply to the output of the switched mode power
supply;

comparing the frequency response to a predetermined metric based on the measuring; and
based on the comparing, determining that the component is valid when the frequency response falls within the predetermined
metric.

US Pat. No. 9,281,744

SYSTEM AND METHOD FOR A PROGRAMMABLE VOLTAGE SOURCE

Infineon Technologies AG,...

16. A system comprising:
a programmable voltage source comprising
a digital to analog (D/A) converter;
a plurality of clock generators coupled to an output of the D/A converter, the plurality of clock generators configured to
produce a clock signal having an amplitude proportional to a first signal at the output of the D/A converter;

a multi-stage charge pump coupled to the plurality of clock generators, the multi-stage charge pump producing an output voltage
proportional to the first signal;

a switching network comprising switches, wherein each switch of the switching network comprises a first end coupled to a corresponding
capacitor within the multi-stage charge pump, and a second end coupled to an output node of the programmable voltage source;

a switching network controller configured to activate a switch of the switching network;
a controllable current source coupled to the output node of the programmable voltage source; and
a current control circuit coupled to a control node of the controllable current source, the current control circuit adjusting
the controllable current source based on a voltage at the output of the programmable voltage source and the first signal.

US Pat. No. 9,263,271

METHOD FOR PROCESSING A SEMICONDUCTOR CARRIER, A SEMICONDUCTOR CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

INFINEON TECHNOLOGIES AG,...

1. A method for processing a semiconductor carrier, the method comprising:
providing a semiconductor carrier comprising a doped substrate region and a device region disposed over a first side of the
doped substrate region, the device region comprising at least part of one or more electrical devices; and

thinning the doped substrate region from a second side of the doped substrate region, wherein the second side of the doped
substrate faces a direction opposite to a direction that the first side faces; and

prior to or after thinning the doped substrate, implanting ions into the doped substrate region to form a gettering region
in the doped substrate region of the semiconductor carrier, wherein implanting ions into the doped substrate region comprises
implanting the ions into the doped substrate region from the second side of the doped substrate region.

US Pat. No. 9,171,245

CHIP ARRANGEMENT, ANALYSIS APPARATUS, RECEIVING CONTAINER, AND RECEIVING CONTAINER SYSTEM

INFINEON TECHNOLOGIES AG,...

1. A chip arrangement, comprising:
a first chip having a first antenna which is monolithically integrated in the first chip and is intended to communicate with
at least one of an external reader or an external writer;

a second chip having a second antenna which is monolithically integrated in the second chip and is intended to communicate
with the at least one of the external reader or the external writer;

a booster antenna which is coupled to the first antenna in a first coupling area in order to increase a range of the first
antenna and is coupled to the second antenna in a second coupling area in order to increase a range of the second antenna;

a first detection antenna which is arranged in the first coupling area, is electrically coupled to the booster antenna and
via which the booster antenna is coupled to the first antenna; and

a second detection antenna which is arranged in the second coupling area, is electrically coupled to the booster antenna and
via which the booster antenna is coupled to the second antenna; and

wherein the first coupling area is separate from second coupling area.

US Pat. No. 9,576,935

METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE

Infineon Technologies AG,...

1. A semiconductor package, comprising:
a substrate comprising an aperture;
a semiconductor chip connected to the substrate;
a first insulating material arranged in the aperture; and
a second insulating material laminated onto the semiconductor chip,
wherein the second insulating material comprises reinforcing fibers and wherein the first insulating material is free of any
reinforcing fibers, and

wherein the first insulating material is at least partially exposed.

US Pat. No. 9,543,414

METHOD OF FORMING A SILICON-CARBIDE DEVICE WITH A SHIELDED GATE

Infineon Technologies AG,...

1. A method of forming a semiconductor device, comprising:
forming a silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from
one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third
doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from
the main surface to the first doped regions, the second doped regions having a first conductivity type, the first, third and
fourth doped regions having a second conductivity type;

annealing the substrate so as to activate dopant atoms in the second, third and fourth doped regions;
forming a gate trench that extends through the second and third doped regions and has a bottom that is arranged over a portion
of one of the first doped regions;

applying a high-temperature step in a non-oxide and non-nitride forming atmosphere so as to realign silicon-carbide atoms
along sidewalls of the gate trench and to form rounded corners between the bottom and sidewalls of the gate trench; and

removing a surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate.

US Pat. No. 9,197,061

ELECTROSTATIC DISCHARGE CLAMPING DEVICES WITH TRACING CIRCUITRY

INFINEON TECHNOLOGIES AG,...

1. An electrostatic discharge (ESD) protection circuit arrangement comprising:
at least one MOS buffer transistor configured to receive an input signal from a first functional circuit block at a gate of
the at least one MOS buffer transistor and to provide a first portion of an output signal to a second functional circuit block;

a leakage current prevention circuit comprising:
at least one MOS clamping transistor coupled to the at least one MOS buffer transistor; and
at least one MOS tracing circuitry coupled to the at least one MOS clamping transistor, the at least one MOS tracing circuitry
having at least one MOS tracing transistor configured to control a voltage at a gate of the at least one MOS clamping transistor;

wherein at least one of a source or a drain of the at least one MOS clamping transistor or the at least one MOS tracing transistor
is coupled to a first supply voltage, and

wherein the at least one MOS tracing transistor of a first MOS tracing circuitry comprises a first MOS tracing transistor
and a second MOS tracing transistor coupled to the first MOS tracing transistor, and wherein the first MOS tracing transistor
and the second MOS tracing transistor being transistors of a first MOS type.

US Pat. No. 9,147,637

MODULE INCLUDING A DISCRETE DEVICE MOUNTED ON A DCB SUBSTRATE

Infineon Technologies AG,...

1. A module comprising:
a metal carrier;
a direct copper bonding (DCB) substrate, wherein the DCB substrate is mounted on the metal carrier;
a discrete device mounted on the DCB substrate, wherein the discrete device comprises:
a leadframe;
a semiconductor chip mounted on the leadframe;
an encapsulation material covering the semiconductor chip; and
an electrical terminal protruding out of the encapsulation material and providing an electrical coupling between the semiconductor
chip and the DCB substrate, wherein one end of the electrical terminal is attached to an electrode on a surface of the semiconductor
chip and another end of the electrical terminal is attached to the DCB substrate;

a housing placed on the metal carrier and accommodating the DCB substrate and the discrete device, wherein the discrete device
is completely arranged inside the housing; and

a metal clip, wherein one end of the metal clip is attached to the DCB substrate and another end of the metal clip is arranged
outside the housing.

US Pat. No. 9,099,996

METHODS AND DEVICES FOR PROVIDING CROSS POINT INFORMATION

Infineon Technologies AG,...

1. A method for providing cross point information, the method comprising:
providing an input signal comprising amplitude and phase information;
interpolating between a first point of the input signal and a second point of the input signal to provide cross point information
between the first point and the second point; and

providing a pulse-width modulated signal based on the input signal and the cross point information.

US Pat. No. 9,391,154

METHOD OF MANUFACTURING A DEVICE BY LOCALLY HEATING ONE OR MORE METALIZATION LAYERS AND BY MEANS OF SELECTIVE ETCHING

Infineon Technologies AG,...

1. A device comprising:
a substrate;
a metallization being locally arranged on a selected area, the metallization comprising an alloy of at least two initial metals,
or a compound of one or more initial metals with the substrate, the initial metals or the substrate being such that they exhibit
an etching selectivity toward an etching medium which is different than that of the alloy or the compound,

wherein the metallization comprises a lateral thickness curve which is uniform over a longitudinal expansion of the metallization.

US Pat. No. 9,258,385

METHOD FOR LOADING A PROGRAM MODULE INTO A NETWORK DEVICE AND NETWORK WITH NETWORK DEVICES

Infineon Technologies AG,...

1. A method for loading a program module into one of a plurality of programmable network devices connected to a network comprising:
loading, by a host connected to the network, an ID-generator into at least one of the plurality of network devices, the ID-generator
comprising an ID-generator program module for generating a unique identification code for each of the plurality of network
devices;

generating a unique identification code for the at least one of the plurality of network devices by executing the ID-generator
program module in the at least one of the plurality of network devices, and by counting clock cycles of a clock signal for
a predetermined time period;

assigning a second program module to at least one unique identification code; and
loading the second program module into the at least one of the plurality of network devices having the unique identification
code assigned to the second program module.

US Pat. No. 9,237,624

LED DRIVER WITH COMPENSATION OF THERMALLY INDUCED COLOR DRIFT

Infineon Technologies AG,...

1. A circuit arrangement comprising:
a temperature sensing circuit configured to provide a temperature signal representing temperature(s) of a plurality of light
emitting diodes emitting light of different colors arranged adjacent to each other for additive color mixing to provide a
desired color, wherein the temperature sensing circuit includes a sigma-delta-modulator configured to generate a stream of
bits or digital words whose time average represents the sensed temperature(s), the stream of bits or digital words forming
the temperature signal;

a current source for each light emitting diode of the plurality of light emitting diodes, current sources configured to provide
the light emitting diodes with respective load currents in accordance with corresponding control signals received by the current
sources;

a first modulator unit and a second modulator unit configured to generate the control signals which are modulated such that
a time average value of each control signal corresponds to the value of a corresponding input signal of the respective modulator
unit; and

a calibration circuit configured to provide the input signals dependent on a color signal defining the desired color and dependent
on the temperature signal, wherein the calibration circuit includes a lookup table unit including color calibration data for
different discrete temperature values, the lookup table unit is configured to provide a set of calibration data selected dependent
on the temperature signal, the input signals of the modulator units being responsive to the selected set of calibration data.

US Pat. No. 9,203,451

SYSTEM AND METHOD FOR AN RF RECEIVER

Infineon Technologies AG,...

1. A radio-frequency (RF) front-end for a radio configured to receive an RF signal at a first frequency, the RF front-end
comprising:
an antenna port configured to be coupled to an antenna;
a notch filter having an input coupled to the antenna port, the notch filter configured to reject one or more frequencies,
wherein the first frequency is a harmonic or intermodulation distortion product of the one or more frequencies; and

a piezoelectric filter having an input coupled to an output of the notch filter and an output configured to be coupled to
an RF amplifier, the piezoelectric filter having a pass band comprising the first frequency, wherein

the notch filter comprises a lumped element notch filter having a first parallel LC tank coupled in series between the antenna
port and the input of the piezoelectric filter and a series LC tank coupled between the input of the piezoelectric filter
and a reference voltage,

the first parallel LC tank comprises a first end coupled to the antenna port and a second end coupled to the input of the
piezoelectric filter, and

the series LC tank is coupled between the second end of the first parallel LC tank and the reference voltage.

US Pat. No. 9,450,613

APPARATUS AND METHOD FOR ERROR CORRECTION AND ERROR DETECTION

Infineon Technologies AG,...

1. A syndrome generator for forming an error syndrome of a linear code C of length n with an H-matrix H=(h1, . . . , hn) of n columns h1, . . . , hn of m components each such that the H-matrix is an (m, n)-matrix, wherein a codeword v=v1, . . . , vn of the code C comprises a first subword x1, . . . , xk+m of length k+m and a second subword a1, . . . , al of length l with n=k+m+l,wherein the code C is configured for correcting 1, . . . , t-bit errors in bits of the first subword and to detect 1, . .
. , l bit errors in bits of the second subword so that the columns of the H-matrix H corresponding to the bits of the first
subword are forming a first (m, k+m)-sub-matrix Hx=(h1x, . . . , hk+mx) and so that the columns of the H-matrix H corresponding to the bits of the second subword are forming a second sub-matrix
Ha=(h1a, . . . , hla),wherein all linear combinations of up to t columns of the first submatrix Hx, which do not result in the zero vector, are pairwise different, andwherein all linear combinations of the columns of the second submatrix Ha are different from all linear combinations of up to t columns of the first sub-matrix Hx, which do not result in the zero vector,wherein t?1, k>0, k+m?4, and l>t+1, andwherein the syndrome generator is implemented using digital hardware or a computer or a combination of a computer and digital
hardware.

US Pat. No. 9,346,441

SENSOR SELF-DIAGNOSTICS USING MULTIPLE SIGNAL PATHS

Infineon Technologies AG,...

1. A monolithic integrated circuit comprising:
a first sensor device configured to indicate a physical quantity, the first sensor device having a first signal path for a
first sensor signal on a semiconductor chip; and

a second sensor device configured to indicate the physical quantity, the second sensor device having a second signal path
for a second sensor signal on the semiconductor chip, the second signal path separate and distinct from the first signal path
and, when compared with the first signal path, having at least one characteristic selected from the group consisting of being
slower, being less precise, having more noise and having a different working principle,

wherein a first output signal related to the first signal path and a second output signal related to the second signal path
are communicable from the monolithic integrated circuit to an external control unit.

US Pat. No. 9,316,705

VERTICAL HALL EFFECT-DEVICE

Infineon Technologies AG,...

1. A vertical Hall effect device comprising:
a Hall effect layer comprising at least a first Hall effect region, a second Hall effect region, a third Hall effect region
and a fourth Hall effect region, which are at least partly decoupled from each other;

wherein the Hall effect layer has a first face and a second opposite face;
wherein the vertical Hall effect device has a terminal composition comprising a first terminal, a second terminal, a third
terminal and a fourth terminal;

wherein a low ohmic connecting composition at the first face connects the terminal composition with contacts of the Hall effect
regions in such a way that at each Hall effect region the terminal composition is connected to a same first number of at least
two contacts being connected to the respective Hall effect region at the first face;

wherein the second terminal and the third terminal output an electrical signal responsive to a magnetic field, if an electrical
energy is supplied to the first terminal and to the fourth terminal and wherein the first terminal and the fourth terminal
output the electrical signal responsive to the magnetic field, if an electric energy is supplied to the second terminal and
to the third terminal; and

wherein a low ohmic layer composition having one or more layer portions; is arranged closer to the second face than to the
first face, wherein the low ohmic layer composition connects each of the at least four Hall effect regions to at least one
other of the at least four Hall effect regions.

US Pat. No. 9,306,058

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT

Infineon Technologies AG,...

1. A method of manufacturing a semiconductor device comprising forming a transistor in a semiconductor substrate having a
main surface, wherein forming the transistor comprises:
forming a source region;
forming a drain region;
forming a channel region;
forming a drift zone;
forming a gate electrode adjacent to the channel region, wherein forming the gate electrode comprises forming a gate trench
in the main surface of the semiconductor substrate; and

forming a gate dielectric adjacent to the gate electrode, the gate electrode being disposed adjacent to at least two sides
of the channel region, the channel region and the drift zone being disposed along a first direction parallel to the main surface
between the source region and the drain region, wherein forming the gate dielectric comprises:

filling a dielectric material into the trench;
covering a portion of the dielectric material with a photomask;
removing an uncovered portion of the dielectric material so that a portion of a trench sidewall is uncovered; and
forming a dielectric layer to be disposed adjacent to the trench sidewall, so that the gate dielectric is formed so as to
have a thickness that varies at different positions of the gate electrode, the thickness being horizontally measured between
the gate electrode and an adjacent semiconductor material, and

wherein the thickness of the gate dielectric is formed to be larger at a portion of the gate electrode adjacent to the drift
zone than at a portion adjacent to the channel region, wherein the gate electrode does not extend to a portion of the thicker
gate dielectric.

US Pat. No. 9,188,645

SYSTEM AND METHOD FOR TESTING A CIRCUIT

Infineon Technologies AG,...

5. A system for in-situ testing of at least one circuit element, the system comprising a sensor, the sensor comprising
a first terminal configured to be coupled to a first node of the at least one circuit element;
a second terminal configured to be coupled a second node of the at least one circuit element
a third terminal configured to be coupled to the second node of the at least one circuit element; and
at least one transmitter and at least one receiver configured to provide a measurement of a first transmission factor between
the first terminal and the second terminal, the at least one transmitter and the at least one receiver further configured
to provide a measurement of a second transmission factor between the third terminal and the second terminal, wherein

the sensor determines an operating state of the at least one circuit element based on a ratio of the first transmission factor
to the second transmission factor.

US Pat. No. 9,576,867

DEVICE COMPRISING A DUCTILE LAYER AND METHOD OF MAKING THE SAME

Infineon Technologies AG,...

1. A component comprising:
a substrate;
a first metal line disposed over the substrate;
an insulating layer disposed over the first metal line;
a second metal line disposed over the insulating layer;
a ductile metal layer disposed between the first metal line and the second metal line, wherein the ductile metal layer is
composed of a different metal than the first metal line, and wherein the ductile metal layer comprises tin, indium, or undoped
aluminum and the first metal line comprises copper; and

a metal barrier layer disposed between the first metal line and the second metal line, wherein the metal barrier layer is
disposed directly beneath the second metal line, wherein the ductile metal layer is disposed directly beneath the metal barrier
layer, and wherein the insulating layer is disposed directly beneath the ductile metal layer.

US Pat. No. 9,564,495

SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR BODY CONTAINING HYDROGEN-RELATED DONORS

Infineon Technologies AG,...

1. A semiconductor device, comprising:
a semiconductor body with parallel first and second surfaces and containing hydrogen-related donors, wherein a concentration
profile of the hydrogen-related donors vertical to the first surface includes a maximum value of at least 1E15 cm?3 at a first distance to the first surface and does not fall below 1E14 cm?3 over at least 60% of an interval between the first surface and the first distance.

US Pat. No. 9,439,017

METHOD FOR MANUFACTURING A PLURALITY OF MICROPHONE STRUCTURES, MICROPHONE AND MOBILE DEVICE

INFINEON TECHNOLOGIES AG,...

1. A method for manufacturing a plurality of microphone structures, the method comprising:
providing a substrate having a front side and a backside, the backside facing away from the front side, and having an inner
area and an outer area laterally surrounding the inner area, with the inner area comprising a plurality of microphone areas,
each microphone area being provided for one microphone of the plurality of microphones;

forming a plurality of layers for the plurality of microphones in the microphone areas on the front side of the substrate;
forming a recess from the backside of the substrate with the recess laterally overlapping the entire inner area;
forming a plurality of cavities into a bottom of the recess with each cavity of the plurality of cavities being formed in
one of the microphone areas;

processing the layers to form the plurality of microphone structures, wherein each microphone structure comprises at least
one layer of the plurality of layer and one cavity; and

separating the plurality of microphone structures from each other.

US Pat. No. 9,385,008

SEMICONDUCTOR COMPONENT OF SEMICONDUCTOR CHIP SIZE WITH FLIP-CHIP-LIKE EXTERNAL CONTACTS

Infineon Technologies AG,...

1. A semiconductor component blank comprising:
an auxiliary carrier defining a plurality of component positions arranged in rows and columns on the auxiliary carrier, wherein
the auxiliary carrier includes a first carrier surface and a second carrier surface opposite the first carrier surface; and

a plurality of semiconductor components, wherein each semiconductor component comprises a semiconductor chip including:
an active upper side, a rear side, a first side edge, and a second side edge,
a plurality of solder balls disposed on the active upper side such that the solder balls project from the active upper side
of the semiconductor chip to orient the active upper side in spaced relation from the auxiliary carrier, and

a separate lead-free solder deposit disposed around a portion of each solder ball such that each separate solder deposit is
spaced apart from the active upper side by the corresponding solder ball, each separate solder deposit coupling one of the
solder balls to the first carrier surface of the auxiliary carrier,

wherein the semiconductor chip is encapsulated by a plastic compound on at leak the rear side, the first side edge, and the
second side edge, and wherein the solder balls and the separate solder deposits are embedded in the same plastic compound
as the semiconductor chip such that an exposed external surface of each separate solder deposit is coplanar with a surface
of the plastic compound and each f the solder balls is encased within the plastic compound.

US Pat. No. 9,385,839

NETWORK RETRANSMISSION PROTOCOLS USING A PROXY NODE

Infineon Technologies AG,...

1. A device, comprising:
reception circuitry adapted to receive a data unit from a first node of a network and a confirmation message signal from a
second node of the network, wherein the first and second nodes are different nodes in the network;

analysis circuitry adapted to determine a failure to correctly receive the data unit; and
transmission circuitry adapted to transmit a negative acknowledgement signal to the first node in case the analysis circuitry
determines the data unit has not been correctly received and the confirmation message signal from the second node is received;

wherein the received data unit was transmitted to both the device and the second node by the first node, and wherein the confirmation
message signal indicates that the second node correctly received the data unit.

US Pat. No. 9,275,973

ELECTRONIC DEVICE AND METHOD FOR FABRICATING AN ELECTRONIC DEVICE

Infineon Technologies AG,...

1. An electronic device comprising:
a semiconductor chip comprising a first main face, a second main face, and side faces each connecting the first main face
to the second main face;

an interdiffusion prevention layer directly disposed on the second main face and the side faces, wherein the interdiffusion
prevention layer comprises a single Ti layer or a layer stack comprising two or more layers of Ti and a Ti alloy; and

a metal layer directly disposed on the interdiffusion prevention layer, wherein the metal layer comprises an upper horizontal
portion disposed above the second main face, a vertical portion disposed above the side faces, and a lower horizontal portion
extending in a plane of the first main face, and wherein the lower horizontal portion is shaped in a form of a closed ring
surrounding the semiconductor chip, wherein the metal layer is a porous metal layer.

US Pat. No. 9,202,161

TRANSPONDER INLAY FOR A DOCUMENT FOR PERSONAL IDENTIFICATION AND A METHOD FOR PRODUCING A TRANSPONDER INLAY

Infineon Technologies AG,...

1. A transponder inlay for a document for personal identification, comprising:
a transponder substrate having a thickness and having a first surface extending in first and second lateral directions,
a transponder unit comprising a transponder chip and an antenna mounted on the transponder substrate, wherein at least the
transponder chip is mounted on the first surface of the transponder substrate,

a covering layer,
an adhesive layer, wherein the adhesive layer is arranged between the first surface of the transponder substrate and the covering
layer and secures the covering layer to the transponder substrate,

wherein
the transponder substrate has at least one cutout spaced laterally apart from the transponder chip and antenna along the first
surface and extending through the transponder substrate, and the adhesive layer extends at least partly into the at least
one cutout.

US Pat. No. 9,153,293

OPERATION SCHEME FOR NON-VOLATILE MEMORY

Infineon Technologies AG,...

1. A method of operating an integrated circuit, the method comprising:
determining at least one characteristic a first memory portion; and
conducting an operation for a first memory portion, wherein based on the at least one characteristic determined for the first
memory portion a disturbance for a second memory portion is adjusted;

wherein the disturbance for the second memory portion is adjusted by adjusting a disturb signal for the second memory portion;
adjusting the disturb signal dependent on a number of access cycles already conducted for the first memory portion; and
wherein the first memory portion and the second memory portion are located on a non-volatile memory.

US Pat. No. 9,147,600

PACKAGES FOR MULTIPLE SEMICONDUCTOR CHIPS

Infineon Technologies AG,...

1. A semiconductor device comprising:
a ball grid array ceramic substrate having a first surface and a second surface opposite the first surface, the ball grid
array ceramic substrate comprising electrical circuitry to couple contacts on the first surface to contacts on the second
surface, wherein the ball grid array ceramic substrate has a first hole;

a plurality of leads is disposed over the first surface of the ball grid array ceramic substrate, one or more leads of the
plurality of leads coupled to the contacts on the first surface;

a die paddle is disposed in the first hole;
an encapsulant disposed over the ball grid array ceramic substrate, die paddle and the plurality of leads;
a first chip disposed over the die paddle, wherein the first chip is electrically coupled to a first lead of the plurality
of leads; and

a second chip disposed over the first chip, wherein the second chip is electrically coupled to a second lead of the plurality
of leads.

US Pat. No. 9,111,847

METHOD FOR MANUFACTURING A CHIP PACKAGE, A METHOD FOR MANUFACTURING A WAFER LEVEL PACKAGE, A CHIP PACKAGE AND A WAFER LEVEL PACKAGE

INFINEON TECHNOLOGIES AG,...

1. A method for manufacturing a chip package, the method comprising
forming a layer over a carrier;
forming further carrier material over the layer;
selectively removing one or more portions of the further carrier material thereby releasing one or more portions of the layer
from the further carrier material; and

adhering a chip comprising one or more contact pads to the carrier via the layer;
wherein forming a layer over a carrier and forming further carrier material over the layer comprises
adhering a foil comprising the layer and further carrier material to the carrier.

US Pat. No. 9,425,784

CIRCUIT HAVING A POWER TRANSISTOR AND A DRIVE CIRCUIT

Infineon Technologies AG,...

1. A circuit comprising:
a power transistor with a drive terminal and a load path, the power transistor being integrated in a first semiconductor body;
a first sensor arrangement having a sensor transistor integrated in the first semiconductor body and an evaluation circuit,
the sensor transistor having a load path between a drain terminal and a source terminal, and a gate terminal directly connected
to the drain terminal, the evaluation circuit having only two connections to the sensor transistor, a first connection to
the drain terminal and a second connection to the source terminal of the sensor transistor such that the evaluation circuit
receives a load path voltage across the drain and source terminals of the sensor transistor that corresponds to a threshold
voltage of the sensor transistor and providing a first sensor signal dependent on the load path voltage that corresponds to
the threshold voltage of the sensor transistor; and

a drive circuit to which the first sensor signal is supplied and that is configured to drive the power transistor via its
drive terminal as a function of the first sensor signal.

US Pat. No. 9,404,990

SENSOR OFFSET ERROR COMPENSATION SYSTEMS AND METHODS USING A CORRECTION FACTOR

Infineon Technologies AG,...

1. A sensor configured to sense a physical characteristic comprising:
at least one sensor element having an output, wherein an output signal comprises an offset error in an absence of the physical
characteristic;

an input quantity other than the physical characteristic that affects the offset error, wherein in a first phase of operation
of the sensor a first input quantity produces a first output signal having a first offset error, and wherein in a second phase
of operation of the sensor a second input quantity different from the first input quantity produces a second output signal
having a second offset error; and

offset correction circuitry coupled to the output and configured to:
generate a correction factor based on the first offset error and the second offset error;
generate a corrected second output signal based on the correction factor and the second output signal; and
generate a sensor output signal based on the first output signal and the corrected second output signal to offset a difference
between the first offset error and the second offset error.

US Pat. No. 9,349,696

INTEGRATED ANTENNAS IN WAFER LEVEL PACKAGE

Infineon Technologies AG,...

1. A semiconductor module comprising:
an integrated circuit (IC) device, the IC device embedded in a compound, wherein the compound at least partially extends lateral
to the IC device and has a portion coplanar with at least one surface of the IC device;

interconnect structures to provide an external electrical contact lateral to the IC device;
an antenna structure integrated in the semiconductor module, wherein at least one portion of the antenna structure extends
lateral to the IC device; and

a layer interfacing the IC device and the compound, wherein the layer comprises first and second metal structures, wherein
the first metal structure is provided to electrically connect the IC device to the interconnect structures and the second
metal structure is provided to transmit signals transmitted or received by the antenna structure, wherein the first metal
structure comprises at least one portion coplanar to the at least one portion of the antenna structure and wherein at least
one of the interconnect structures is arranged on the at least one portion of the first metal structure, wherein the layer
further comprises a metal bar provided on a side of the antenna structure for directing a radiation to a specific direction.

US Pat. No. 9,299,816

ESD PROTECTION STRUCTURE, INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE

INFINEON TECHNOLOGIES AG,...

1. An ESD protection structure, comprising:
a plurality of first doped regions of a first conductivity type forming first terminals of a plurality of transistors, wherein
the plurality of first doped regions are formed in a substrate,

a plurality of second doped regions of the first conductivity type forming second terminals of the plurality of transistors,
wherein the plurality of second doped regions are formed in the substrate,

wherein each of the plurality of first doped regions is arranged adjacent to one of the plurality of second doped regions
in an alternating pattern in a first dimension, and each of the plurality of first doped regions is further arranged adjacent
to another one of the plurality of second doped regions in an alternating pattern in a second dimension different than the
first dimension, and

a third doped region of a second conductivity type opposite the first conductivity type formed in the substrate and surrounding
a plurality of doped regions to form a common third terminal of the plurality of transistors, wherein all doped regions surrounded
by the third doped region are the plurality of first doped regions and the plurality of second doped regions,

wherein the plurality of first doped regions are coupled to each other to form a first terminal of the ESD protection structure,
and

wherein the plurality of second doped regions are coupled to each other to form a second terminal of the ESD protection structure.

US Pat. No. 9,287,383

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH STEP-SHAPED EDGE TERMINATION

Infineon Technologies AG,...

1. A method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate comprising a first side, a second side, a plurality of laterally spaced semiconductor
devices integrated into the semiconductor substrate, and a drift region of a first conductivity type;

forming trenches in the semiconductor substrate at the first side of the semiconductor substrate between laterally adjacent
semiconductor devices, each of the trenches comprising two sidewalls and a bottom;

forming first doping zones of a second conductivity type in the semiconductor substrate at least along the sidewalls of the
trenches, wherein the first doping zones form pn-junctions with the drift region;

forming second doping zones of the first conductivity type in the semiconductor substrate at least along a part of the bottom
of the trenches, wherein the second doping zones adjoin the drift region; and

cutting the semiconductor substrate along the second doping zones in the trenches to separate the semiconductor devices.

US Pat. No. 9,224,695

CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT

INFINEON TECHNOLOGIES AG,...

1. A chip arrangement, comprising:
a chip; and
an insulating foil attached directly to one of the front side of the chip and the back side of the chip, wherein the chip
comprises at least one contact pad, and wherein the insulating foil comprises at least one opening to expose the at least
one contact pad, and wherein the insulating foil comprises a metal layer covered with a polymer material.

US Pat. No. 9,123,764

METHOD OF MANUFACTURING A COMPONENT COMPRISING CUTTING A CARRIER

Infineon Technologies AG,...

1. A method of manufacturing a semiconductor device, the method comprising:
placing a wafer on a dicing foil;
separating the wafer into chips, the chips are separated by spaces;
after separating, placing a connection layer on the wafer;
stretching the dicing foil thereby separating the connection layer; and
picking up the chips from the dicing foil.

US Pat. No. 9,378,317

METHOD FOR DETECTING DAMAGE TO A SEMICONDUCTOR CHIP

Infineon Technologies AG,...

1. A method for producing a semiconductor chip, the method comprising:
arranging a plurality of semiconductor components in a semiconductor zone of the semiconductor chip, the plurality of semiconductor
components comprising at least one electrical circuit;

arranging at least one interconnect at a periphery of the semiconductor zone, wherein the at least one interconnect separates
the plurality of semiconductor components from a crack stop located in a first dielectric layer of the semiconductor chip;

arranging at least two transistors at the periphery of the semiconductor zone as at least two temperature sensors;
electrically coupling a current source and the at least two transistors in series to the at least one interconnect; and
creating a detection circuit configured to compare a voltage of the at least one interconnect with a predefined reference
voltage, wherein the detection circuit is configured to detect a change in the voltage of the at least one interconnect, to
identify a temperature, detected by the at least two temperature sensors, corresponding to the voltage of the at least one
interconnect within a particular voltage range below the predefined reference voltage, and to identify a presence of damage
to at least one portion of the semiconductor chip corresponding to the voltage of the at least one interconnect being above
the predefined reference voltage.

US Pat. No. 9,374,081

METHOD FOR DRIVING A LOAD

Infineon Technologies AG,...

11. An electronic circuit, comprising:
an electronic switch comprising a load path configured to be coupled in series with a load and a drive terminal configured
to receive a drive signal, wherein the electronic switch is operable to switch between a first operation state and a second
operation state dependent on the drive signal; and

a drive circuit configured
in a first switching cycle, to switch the electronic switch from the first operation state to the second operation state,
and to evaluate a voltage across the load during the first switching cycle in order to obtain a measured switching profile,

to compare the measured switching profile with a reference profile and to provide a drive profile dependent on the comparison,
to store the drive profile, and
to use the drive profile to drive the electronic switch in a second switching cycle after the first switching cycle, wherein
drive parameters are used at different times in the second switching cycle to drive the electronic switch.

US Pat. No. 9,303,327

ELECTRIC COMPONENT WITH AN ELECTROPHORETICALLY DEPOSITED FILM

Infineon Technologies AG,...

1. A packaged component comprising:
a chip carrier comprising a chip attach area and leads;
a chip disposed on the chip attach area on a first side of the chip carrier; and
an electrically insulating layer disposed on an electrically conductive surface of a second side of the chip carrier, wherein
the insulating layer comprises a polymer and an inorganic material comprising a dielectric strength of equal or greater than
15 ac-kv/mm and a thermal conductivity of equal or greater than 15 W/m*K; and

an encapsulation body at least partially encapsulating the chip carrier and the chip, wherein the leads protrude from the
encapsulation body.

US Pat. No. 9,266,719

METHODS OF MANUFACTURE MEMS DEVICES

Infineon Technologies AG,...

1. A method of forming a micro-electromechanical system (MEMS) device, the method comprising:
forming a buried oxide layer over a substrate;
forming a first semiconductive material over the buried oxide layer;
forming at least one trench in the first semiconductive material and the buried oxide layer, the at least one trench comprising
a first sidewall and a second sidewall opposite the first sidewall;

forming an insulating material layer over at least a portion of the first sidewall of the at least one trench, wherein the
insulating material layer is not an air gap;

forming a second semiconductive material within the at least one trench; and
forming a first gap in an upper portion of the at least one trench, the first gap being formed between the second semiconductive
material and the second sidewall of the at least one trench in the first semiconductive material.

US Pat. No. 9,245,837

RADIO FREQUENCY POWER DEVICE

Infineon Technologies AG,...

1. An electronic RF power device, comprising:
a transistor chip;
a device input terminal;
a device output terminal;
an output impedance transformation circuit;
an output contact clip bonded to the transistor chip and to the output device terminal; and
at least one bond wire bonded to the output impedance transformation circuit and to the transistor chip.

US Pat. No. 9,178,522

ANALOG-TO-DIGITAL CONVERTER AND CONTROL CIRCUIT WITH A LOW QUIESCENT CURRENT AT LOW LOAD

INFINEON TECHNOLOGIES AG,...

1. A circuit, comprising:
a successive approximation register;
an adjustable capacitor having a set input for setting a capacitance value of the adjustable capacitor;
a comparator coupled to an input terminal of the adjustable capacitor, and at least one output coupled to an input of the
successive approximation register; and

an analog input coupled to a terminal of the adjustable capacitor,
wherein the circuit is configured to operate in a first operating mode and a second operating mode, and wherein an output
of the circuit is controlled by the successive approximation register in the first operating mode and the output of the circuit
is not controlled by the successive approximation register in the second operating mode, the output of the circuit being controlled
by an output of the comparator in the second operating mode.

US Pat. No. 9,075,100

METHOD, DEVICE AND CIRCUITRY FOR DETECTING A FAILURE ON A DIFFERENTIAL BUS

INFINEON TECHNOLOGIES AG,...

1. Method for detecting a failure on a differential bus comprising:
detecting a first signal between bus lines of the differential bus,
detecting a second signal between the bus lines,
detecting the failure in case the first signal and the second signal do not show a same absolute value or in case the first
signal and the second signal do not show nearly a same absolute value.

US Pat. No. 9,479,310

METHOD, APPARATUS AND SYSTEM TO COMMUNICATE WITH A DEVICE

Infineon Technologies AG,...

7. An apparatus to communicate with a device, wherein a housing of the apparatus and a housing of the device are remote from
one another,
the apparatus configured to provide a first signal and a second signal,
the apparatus further configured to receive a third signal,
the first signal having a transition between two signal states,
the second signal having a periodicity with a periodic elementary pattern encompassing at least one first cycle pattern,
the periodic elementary pattern of the second signal further comprising a second cycle pattern, wherein the second cycle pattern
differs from the first cycle pattern, and

the apparatus configured to extract information from the third signal based on a timing of the third signal being associated
with a timing of the second signal; and

the apparatus further configured to transmit to the device a control signal having periodic transitions between signal states,
wherein the periodic transitions in the control signal coincide with the second cycle pattern in the second signal.

US Pat. No. 9,479,149

OVERSHOOT COMPENSATION

Infineon Technologies AG,...

1. An overshoot compensation circuit for an input signal, comprising:
a slew rate detection circuit configured to detect a slew rate of the input signal;
a run time circuit configured to initialize a predetermined run time when an absolute value of the slew rate of the input
signal is greater than or equal to a predetermined threshold; and

a low pass filter configured to decrease the slew rate of the input signal only during the predetermined run time.

US Pat. No. 9,379,695

CIRCUIT AND METHOD FOR OPERATING A HALF-BRIDGE

Infineon Technologies AG,...

1. A circuit for operating a half-bridge, comprising:
a first multiplier circuit configured:
to multiply a first signal by a first factor to provide a turn-on signal configured to turn on a first switch of the half-bridge;
and

to multiply the first signal by a second factor to provide a turn-off signal configured to turn off a second switch of the
half-bridge; wherein the first factor and the second factor are chosen so that the second switch is turned off before the
first switch is turned on; and

a first generating unit configured to provide the first signal, wherein the first generating unit comprises a first current
controlled current source controlled by a control current.

US Pat. No. 9,374,042

SYSTEM AND METHOD FOR A LOW NOISE AMPLIFIER

Infineon Technologies AG,...

1. An amplifier system including a low noise amplifier (LNA) bank comprising:
a first LNA comprising:
a first transistor including a control terminal coupled to a first input of the LNA bank, and
a first output network coupled to a conduction path of the first transistor and an output of the LNA bank, wherein the first
output network is configured to have a first type of output impedance in a first frequency band and a second type of output
impedance outside the first frequency band; and

a second LNA comprising:
a second transistor including a control terminal coupled to a second input of the LNA bank, and
a second output network coupled to a conduction path of the second transistor and the output of the LNA bank, wherein the
second output network is configured to have the first type of output impedance in a second frequency band and the second type
of output impedance outside the second frequency band.

US Pat. No. 9,366,700

CURRENT SENSOR

Infineon Technologies AG,...

1. A current sensor, comprising:
a conductive element comprising a first end, a second end, and an intermediate portion arranged between the first end and
the second end, wherein the conductive element is configured to conduct a current to be sensed from the first end through
the intermediate portion to the second end; and

a magnetic field sensor arranged at the intermediate portion of the conductive element and is configured to sense a magnetic
field generated by the current through the conductive element,

wherein the first end is configured to be coupled to a first conductor,
wherein the second end is configured to be coupled to a second conductor; and
wherein:
the first end of the conductive element comprises a connecting element configured to connect to a contact, and the second
end of the conductive element comprises a receptacle configured to receive a cable, or

the first end of the conductive element comprises a first receptacle configured to receive a first cable, and the second end
of the conductive element comprises a second receptacle configured to receive a second cable, or

the first end of the conductive element comprises a first connecting element configured to connect to a first contact, and
the second end of the conductive element comprises a second connecting element configured to connect to a second contact,
or

the first end of the conductive element comprises a connecting element configured to connect to a first contact, and the second
end of the conductive element comprises a terminal element, or

the first end of the conductive element comprises a receptacle configured to receive a cable, and the second end of the conductive
element comprises a terminal element.

US Pat. No. 9,324,845

ESD PROTECTION STRUCTURE, INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE

INFINEON TECHNOLOGIES AG,...

1. An ESD protection structure, comprising:
a plurality of first doped regions of a first conductivity type forming first terminals of a plurality of transistors, wherein
the plurality of first doped regions are formed in a substrate,

a plurality of second doped regions of the first conductivity type forming second terminals of the plurality of transistors,
wherein the plurality of second doped regions are formed in the substrate,

wherein each of the plurality of first doped regions is arranged adjacent to one of the plurality of second doped regions
in an alternating pattern in a first dimension, and each of the plurality of first doped regions is further arranged adjacent
to another one of the plurality of second doped regions in an alternating pattern in a second dimension different than the
first dimension, and

a third doped region of a second conductivity type opposite the first conductivity type formed in the substrate and surrounding
a plurality of doped regions to form a common third terminal of the plurality of transistors, wherein all doped regions surrounded
by the third doped region are the plurality of first doped regions and the plurality of second doped regions,

wherein the plurality of first doped regions are coupled to each other to form a first terminal of the ESD protection structure,
and

wherein the plurality of second doped regions are coupled to each other to form a second terminal of the ESD protection structure.

US Pat. No. 9,274,183

VERTICAL HALL DEVICE COMPRISING FIRST AND SECOND CONTACT INTERCONNECTIONS

Infineon Technologies AG,...

1. A vertical Hall device comprising:
a Hall effect region formed in a substrate;
a sequence of at least six contacts arranged in or at a surface of the Hall effect region between and including a first contact
and a last contact;

a first contact interconnection connecting the first contact with a third-to-the-last contact; and
a second contact interconnection connecting a third contact with the last contact,
wherein the first contact, the third-to-the-last-contact, the third contact, and the last contact are configured to function
as supply contacts during a first clock phase of a spinning current scheme and as sense contacts during a second clock phase
of the spinning current scheme; and

wherein a second contact and a next-to-the-last contact are configured to function as sense contacts during the first clock
phase and as supply contacts during the second clock phase.

US Pat. No. 9,145,292

CAVITY STRUCTURES FOR MEMS DEVICES

Infineon Technologies AG,...

16. A monolithic integrated sensor device comprising:
a microelectromechanical system (MEMS) sensor formed on a first portion of a non-silicon-on-insulator (non-SOI) substrate,
the MEMS sensor comprising:

a monocrystalline sacrificial layer deposited on only the first portion of the non-SOI substrate,
a cavity formed in the monocrystalline sacrificial layer and having an aperture, and
a silicon layer deposited on the monocrystalline sacrificial layer and a second portion of the non-SOI substrate, wherein
the silicon layer seals the aperture; and

a transistor arranged laterally with respect to the MEMS sensor and comprising a portion of the silicon layer formed on the
second portion of the non-SOI substrate.

US Pat. No. 9,083,308

MEMS DEVICE

Infineon Technologies AG,...

1. A microelectromechanical system (MEMS) comprising:
an anchor region;
an electrode connected to the anchor region comprising an outer circumference, a first plurality of openings and a second
plurality of openings;

a first drive or trim electrode surrounding the outer circumference of the electrode; and
a plurality of second drive or trim electrodes located in the first plurality of openings of the electrode.

US Pat. No. 9,076,838

INSULATED GATE BIPOLAR TRANSISTOR WITH MESA SECTIONS BETWEEN CELL TRENCH STRUCTURES AND METHOD OF MANUFACTURING

Infineon Technologies AG,...

1. An insulated gate bipolar transistor, comprising:
a mesa section extending, between two cell trench structures, from a first surface of a semiconductor portion to a layer section
of the semiconductor portion;

a source region formed in the mesa section and electrically connected to an emitter electrode; and
a doped region separated from the source region by a body region of a complementary conductivity type, the doped region comprising
a first portion with a first mean net impurity concentration and a second portion with a second mean net impurity concentration
exceeding at least ten times the first mean net impurity concentration,

wherein the first portion extends from the body region to the layer section,
wherein the first portion is interposed between the second portion and one of the two cell trench structures.

US Pat. No. 9,986,636

PRINTED CIRCUIT BOARDS HAVING A DIELECTRIC LAYER WHICH INCLUDES A POLYMER AND METHODS OF MANUFACTURING SUCH PRINTED CIRCUIT BOARDS

Infineon Technologies AG,...

1. A printed circuit board, comprising:an electrically conductive layer; and
a dielectric layer comprising a polymer, wherein the polymer comprises carbon layer structure,
wherein the carbon layer structure comprises expanded graphite sheets.

US Pat. No. 9,385,075

GLASS CARRIER WITH EMBEDDED SEMICONDUCTOR DEVICE AND METAL LAYERS ON THE TOP SURFACE

Infineon Technologies AG,...

1. A device comprising:
a semiconductor material comprising a first main surface, an opposite surface opposite to the first main surface, a side surface
extending from the first main surface to the opposite surface, and a functional area configured to operate in a radio frequency
range;

a first electrical contact element arranged on the first main surface of the semiconductor material;
a glass material comprising a second main surface, wherein the glass material contacts the side surface of the semiconductor
material and wherein the first main surface of the semiconductor material and the second main surface of the glass material
are arranged in a common plane; and

a redistribution layer comprising at least one metal layer arranged over the first main surface of the semiconductor material
and over the second main surface of the glass material, the redistribution layer electrically coupled to the first electrical
contact element, at least one dielectric layer arranged over the first main surface of the semiconductor material and over
the second main surface of the glass material, and a passive electronic component arranged over the second main surface of
the glass material, wherein when viewed in a direction perpendicular to the common plane an outline of the passive electronic
component is arranged completely outside of an outline of the semiconductor material and completely inside of an outline of
the glass material, and wherein the glass material comprises a Low Temperature Co-Fired Ceramic.

US Pat. No. 9,159,669

NANOTUBE STRUCTURE BASED METAL DAMASCENE PROCESS

INFINEON TECHNOLOGIES AG,...

1. A method for manufacturing a metallization layer on a substrate, the method comprising:
forming an adhesion promoting layer on the substrate;
providing a separate substrate with fully grown nanotubes;
transferring the full grown nanotubes from the separate substrate onto the adhesion promoting layer;
forming a plurality of groups of nanotubes from the nanotubes transferred from the separate substrate over the substrate,
wherein the groups of nanotubes are arranged such that a portion of the substrate is exposed; and

forming metal over the exposed portion of the substrate between the groups of nanotubes.