US Pat. No. 9,443,530

ACOUSTIC ECHO CANCELLATION

Imagination Technologies ...

1. A method of calculating error data in acoustic echo cancellation, the method comprising:
storing received far-end data in a first buffer;
subsequent to the far-end data in the first buffer exceeding a predefined length,
calculating echo-estimate data using the stored far-end data;
storing the echo estimate data in a second buffer;
receiving microphone data; and
subsequent to sufficient echo estimate data being stored in the second buffer, calculating error data by subtracting, from
the microphone data, corresponding echo estimate data stored in the second buffer, thereby substantially avoiding a delay,
caused by processing of the far-end data, in calculating the error data after reception of the microphone data;

wherein the calculated error data is used by an acoustic echo canceller for use in cancelling acoustic echo.

US Pat. No. 9,384,584

DISPLAY LIST CONTROL STREAM GROUPING IN TILE BASED 3D COMPUTER GRAPHICS SYSTEM

Imagination Technologies ...

1. A method for rendering a computer graphics image of a 3-D scene in a computer graphics system configured to use a rendering
space which is divided into a plurality of tiles, wherein the plurality of tiles are grouped into a plurality of tile groups,
the method comprising:
grouping primitives of said 3-D scene into primitive blocks;
for each tile group, generating a control stream data list indicating which primitive blocks contain at least one primitive
that overlaps a tile said tile group, said control stream data lists comprising a plurality of control data block groups each
containing a plurality of control data blocks, wherein a first control data block of a control data block group includes an
array of control pointers pointing to start addresses of subsequent control data blocks in said control data block group and
a start address of a subsequent control data block group in said control stream data list;

for each tile of a tile group for which a primitive block is indicated in the control stream data list for that tile group,
accessing control stream data from the control stream data list for that tile group, determining which control data blocks
in said control stream data list should be used to render that tile, which control data blocks in said control stream data
list should not be used to render that tile, and using said control pointers to selectively access control stream data from
control data blocks to render said tile of the image.

US Pat. No. 9,418,473

RELIGHTABLE TEXTURE FOR USE IN RENDERING AN IMAGE

Imagination Technologies ...

1. A method of determining a relightable texture for use in rendering an image from a rendering viewpoint under arbitrary
lighting conditions, wherein at least one view of a scene from a respective at least one camera viewpoint represents the image,
the method comprising:
separating an initial texture for the image into a lighting estimate and a colour estimate, said initial texture being derived
from the at least one view of the scene from the at least one camera viewpoint;

generating a shadow-detail estimate by filtering the lighting estimate to attenuate low frequency components thereof, wherein
the shadow-detail estimate indicates one or more shadow regions of the relightable texture which are to remain in shadow when
the image is rendered; and

determining the relightable texture for the image using the lighting estimate, the colour estimate and the shadow-detail estimate.

US Pat. No. 9,292,960

RANDOM ACCESSIBLE LOSSLESS PARAMETER DATA COMPRESSION FOR TILE BASED 3D COMPUTER GRAPHICS SYSTEMS

Imagination Technologies ...

1. A method of compressing vertex parameter data in a 3D graphics system, the vertex parameter data comprising data relating
to a plurality of vertices, data for each vertex including multiple bytes relating to at least one parameter, the method comprising:
forming a plurality of byte blocks from the data, comprising grouping together, in the 3-D graphics system, bytes with corresponding
byte positions and pertaining to respective values of a parameter for different vertices; and

compressing, in the 3-D graphics system, at least one of the byte blocks using a first compression algorithm, the first compression
algorithm comprising storing at least one byte in the at least one byte block as a byte origin, and storing each of the remaining
bytes in the byte block encoded as a value derived from a difference between the byte origin and that remaining byte.

US Pat. No. 9,098,933

MEMORY MANAGEMENT FOR SYSTEMS FOR GENERATING 3-DIMENSIONAL COMPUTER IMAGES

Imagination Technologies ...

1. A memory management system for use with systems for generating 3-dimensional computer images, comprising:
a) means for subdividing an image into a plurality of rectangular areas;
b) a memory for storing object data pertaining to objects in the image which fall in each rectangular area, the memory comprising
i) at least one portion allocated to each rectangular area for storing object data pertaining to objects in the respective
rectangular area and ii) at least one portion allocated as a global list for storing object data pertaining to objects falling
in more than one rectangular area;

c) means for storing the object data in the memory;
d) deriving means for deriving image data and shading data for each rectangular area, from the object data;
e) means for supplying object data for each rectangular area from the respective portion of the memory and, if the rectangular
area contains objects also falling in at least one other rectangular area, also from the global list, to the deriving means;
and

f) means for storing the image data and shading data derived by the deriving means, for display.

US Pat. No. 9,622,293

MODULAR RADIO TRANSCEIVER

Imagination Technologies ...

1. A modular radio frequency (RF) transceiver comprising:
a frequency synthesizer module;
at least one transmitter module; and
at least one receiver module,
wherein the frequency synthesizer module is arranged to generate a local oscillator signal, and
wherein each of said modules is arranged adjacently to another of said modules, such that at least one of said at least one
transmitter module and said at least one receiver module is arranged adjacent to the frequency synthesizer module, each of
said at least one transmitter module and said at least one receiver module being arranged to mix at least one respective input
signal with the local oscillator signal, said adjacently arranged modules being electrically connected to each other such
that each of said transmitter and receiver modules receives at least data signals, the local oscillator signal and a power
supply from an adjacent one of said transmitter, receiver, and frequency synthesizer modules.

US Pat. No. 9,390,547

UNTRANSFORMED DISPLAY LISTS IN A TILE BASED RENDERING SYSTEM

Imagination Technologies ...

1. A 3-D rendering system, comprising:
a tiling unit configured to produce a respective object list for each tile of pixels within a frame of pixels to be rendered
that is divided into a plurality of tiles, each object list identifying geometry elements that overlap its tile;

a rasterizer comprising a fetch unit, coupled to a memory for storing untransformed data for geometry elements to be used
in rendering;

a transform unit coupled with the fetch unit, and operable to produce transformed data for a geometry element from received
untransformed data from the fetch unit;

a cache;
a cache controller coupled with the cache, the cache controller operable to receive the transformed data and control storage
of the transformed data in the cache; and

a hidden surface removal unit operable to process an object list for a tile by receiving transformed data from the cache if
present, for a geometry element identified in the object list for the tile,

wherein the system is configured to arrange for the retrieval of untransformed data for a geometry element identified in the
object list for provision to the transform unit to produce said transformed data, said transformed data being provided for
usage by the hidden surface removal unit and cached in the cache for possible subsequent use.

US Pat. No. 9,305,393

BUILDING ACCELERATION STRUCTURES WITH SYNTHETIC ACCELERATION SHAPES FOR USE IN RAY TRACING

Imagination Technologies ...

1. A method of forming an acceleration structure for intersection testing of rays, comprising:
receiving data defining an object located in a 3-D scene, the object composed of primitives;
characterizing aspect ratios of the primitives;
determining an acceleration structure element for inclusion in a hierarchical acceleration structure for use in tracing rays
in the 3-D scene, the acceleration structure element being defined using data that locates a plurality of individual constituent
3-D volumes and specifies a respective extent of each of the constituent 3-D volumes, wherein the determining comprises selecting
how many constituent 3-D volumes will be used, and a location and an extent of each constituent 3-D volume based on respective
aspect ratios of one or more primitives defined in the primitive data which are to be bounded by that acceleration structure
element; and

defining a relationship between the determined acceleration structure element to one or more other elements in the hierarchical
acceleration structure.

US Pat. No. 9,128,700

RESTORING A REGISTER RENAMING MAP

Imagination Technologies ...

1. A method of restoring a register renaming map in an out-of-order processor, comprising:
storing a copy of the register renaming map state in a storage location of a restore table whenever a flow-risk instruction
is inserted into a re-order buffer, until all storage locations are utilised;

determining that a storage location has subsequently become available;
generating a derived register renaming map state for an unrecorded flow-risk instruction inserted into the re-order buffer
whilst all storage locations were utilised, based on a previously stored register renaming map state for an older flow-risk
instruction and values stored in the re-order buffer for intervening instructions inserted between the older flow-risk instruction
and the unrecorded flow-risk instruction;

storing the derived register renaming map state for the unrecorded flow-risk instruction at the available storage location;
and

in the event that execution of one of the flow-risk instructions causes an unexpected change in instruction flow, restoring
the register renaming map using the register renaming map state associated with that flow-risk instruction in the restore
table.

US Pat. No. 9,124,456

EFFICIENT TRACKING OF DECISION-FEEDBACK EQUALISER COEFFICIENTS

Imagination Technologies ...

1. A method of generating updated decision-feedback equaliser (DFE) coefficients for use in an equaliser in a wireless receiver,
the equaliser comprising a feed-forward equaliser (FFE) and a DFE and the method comprising:
updating a channel impulse response estimate;
updating FFE coefficients;
generating updated DFE coefficients based on the updated channel impulse response estimate and the updated FFE coefficients;
extracting a real part of the updated DFE coefficients; and
converting the real part of the updated DFE coefficients to the time domain.

US Pat. No. 9,100,230

EFFICIENT CALCULATION OF INITIAL EQUALISER COEFFICIENTS

Imagination Technologies ...

1. A method of generating initial coefficients for use in an equaliser in a wireless receiver comprising:
generating a channel matched filter using an estimate of channel impulse response; filtering the estimate of channel impulse
response using the channel matched filter;

splitting the filtered estimate of channel impulse response into a first portion and a second portion, the first portion comprising
all pre-echoes; and

calculating initial Feed-Forward Equaliser (FFE) coefficients using an inverted version of the first portion in a frequency
domain.

US Pat. No. 9,100,537

OBJECT TRACKING USING GRAPHICS ENGINE DERIVED VECTORS IN A MOTION ESTIMATION SYSTEM

Imagination Technologies ...

1. A method for motion estimation in a sequence of image data, comprising:
characterizing movement of a camera or viewer, comprising a change in one or more of view direction and position, between
a pair of fields or frames in the sequence of image data;

determining respective sets of candidate motion vectors for positions of objects in one of the fields or frames relative to
positions of the objects in the other of the fields or frames; and

adjusting the sets of candidate motion vectors using the characterized movement of the camera or viewer position, the adjusting
comprising at least one of (1) adjusting criteria for selecting candidate motion vectors, in dependence on the characterized
movement of the camera or viewer position and (2) adjusting one or more of a direction and a magnitude of a candidate motion
vector in dependence on the characterized movement of the camera or viewer position;

wherein the determining respective sets of candidate motion vectors for positions of objects in one of the fields or frames
relative to positions of the objects in the other of the fields or frames comprises defining the candidate motion vectors
as respective sums of a vector derived from the characterized movement of the camera or viewer at a location to which that
candidate motion vector applies and a respective vector representing an estimated true motion of a respective object at the
location to which the candidate motion vector applies, and

further comprising storing the vector representing an estimated true motion of an object and using that stored vector in at
least one of the sets of candidate vectors for object motion, the at least one of the sets pertaining to one or more locations
neighboring the location to which that candidate motion vector applies, in the one of the fields or frames.

US Pat. No. 9,454,810

CORRECTING CHROMINANCE VALUES BASED ONTONE-MAPPED LUMINANCE VALUES

Imagination Technologies ...

1. A method of correcting input chrominance values of pixels to determine corrected chrominance values for the pixels based
on tone-mapped luminance values which have been determined by applying tone mapping to input luminance values of the pixels,
the method comprising:
determining candidate corrected chrominance values for the pixels based on the input chrominance values, the input luminance
values and the tone-mapped luminance values, such that for each of the pixels, a first saturation determined from the input
luminance value and the input chrominance value has a predetermined relationship to a second saturation determined from the
tone-mapped luminance value and the candidate corrected chrominance value;

determining confidence weightings which indicate confidences in the respective candidate corrected chrominance values, wherein
the confidence weightings are determined in dependence on the input luminance values of the respective pixels; and

using the determined confidence weightings to compute, for each of the pixels, a weighted combination of the respective candidate
corrected chrominance value and the respective input chrominance value, thereby determining the corrected chrominance values
for the pixels.

US Pat. No. 9,395,991

SPECULATIVE LOAD ISSUE

Imagination Technologies ...

2. An apparatus with a load and store buffer arranged to issue to a data cache a load instruction in a program, the load and
store buffer comprising:
a store buffer for storing one or more store instructions; and
a load and store logic unit in communication with the store buffer, the load and store logic unit configured to:
determine whether there are any unresolved store instructions in the store buffer that are older than the load instruction,
in response to determining that there is at least one unresolved store instruction in the store buffer older than the load
instruction, determining whether the oldest unresolved store instruction in the store buffer is within a speculation window
for the load instruction, wherein the speculation window for any load instruction in the program covers a predetermined number
of instructions immediately preceding that load instruction or a predetermined number of store instructions immediately preceding
that load instruction, and

in response to determining that the oldest unresolved store instruction is within the speculation window for the load instruction,
speculatively issuing the load instruction to the data cache.

US Pat. No. 9,361,874

VARYING ADAPTIVE FILTER STEP SIZE IN ACOUSTIC ECHO CANCELLATION

Imagination Technologies ...

1. A method of varying a step size of an adaptive filter in an acoustic echo canceller, the method comprising:
calculating echo estimate data using received far-end data;
calculating error data using the echo estimate data and received microphone data;
computing a first average of the microphone data over a predefined number of samples and a second average of the error data
over the predefined number of samples;

estimating an echo leakage using the first average and the second average, wherein the echo leakage indicates an extent to
which the far-end data is present in the error data; and

varying the step size of the adaptive filter based on the estimated echo leakage and a maximum allowed step size;
wherein the adaptive filter is used in acoustic echo cancellation by said acoustic echo canceller.

US Pat. No. 9,342,270

CONVERSION OF A NORMALIZED N-BIT VALUE INTO A NORMALIZED M-BIT VALUE

Imagination Technologies ...

1. A method of processing data in a processor by converting in computing logic a normalized n-bit data value which represents
one of 2n evenly spaced values within a particular range into a normalized m-bit value which represents one of 2m evenly spaced values within the particular range in accordance with a predetermined rounding mode, the method comprising:
receiving the normalized n-bit value at an initial module of the computing logic;
determining, by the initial module, an initial m-bit value, wherein the bits of said initial m-bit value are determined to
be equal to the m most significant bits of a concatenation of one or more copies of a group of one or more bits derived from
the received normalized n-bit value;

based on bits of the normalized n-bit value and in accordance with the predetermined rounding mode, selecting at a selection
module of the computing logic an output state indicating a predefined manner of determining the normalized m-bit value from
the initial m-bit value;

in accordance with the selected output state, determining, at an output module of the computing logic, from the normalized
n-bit value the normalized m-bit value to be equal to one of a plurality of candidate m-bit values, the plurality of candidate
m-bit values consisting of the initial m-bit value and at least one of: (i) the initial m-bit value incremented by one, and
(ii) the initial m-bit value decremented by one; and

outputting, from the output module, the determined normalized m-bit value converted from the normalized n-bit data value,
whereby the data represented by the normalized n-bit data value can be processed in a processor using the normalized m-bit
value.

US Pat. No. 9,112,951

ACOUSTIC ECHO SUPPRESSION

Imagination Technologies ...

1. A controller for an echo suppressor configured to suppress a residual echo of a far-end signal included in a primary error
signal, the controller adapted for operation with a primary adaptive filter configured to form a primary echo estimate of
the far-end signal included in a microphone signal and with an echo canceller configured to cancel that primary echo estimate
from the microphone signal so as to form the primary error signal, the controller comprising:
a secondary adaptive filter configured to form a secondary echo estimate of the far-end signal included in the microphone
signal;

a coherence estimator configured to form a first measure of coherence between the microphone signal and the primary error
signal, and a second measure of coherence between the microphone signal and the primary echo estimate; and

control logic being configured to:
in a first mode selected when the primary adaptive filter is in a non-converged state, combine the microphone signal and the
secondary echo estimate so as to form a transient decision parameter indicative of a state of the microphone signal and, in
dependence on the transient decision parameter, control activation of the echo suppressor; and

in a second mode selected when the primary adaptive filter is in a converged state, combine the first and second measures
of coherence so as to form one or more first steady state decision parameters indicative of a state of the microphone signal
and, in dependence on said one or more first steady state decision parameters, control activation of the echo suppressor.

US Pat. No. 9,430,811

GRAPHICS PROCESSOR WITH NON-BLOCKING CONCURRENT ARCHITECTURE

Imagination Technologies ...

1. A processing system capable of performing concurrent graphics computation, comprising:
a plurality of computation elements, each computation element comprising a local memory, and a plurality of Single Instruction
Multiple Data (SIMD) Arithmetic Logic Units (ALUs);

a scheduler operable to receive inputs defining instances of a first type of computation to be performed on the plurality
of computation elements, each of the instances associated with a respective data element stored in a local memory of one of
the plurality of computation elements, the scheduler operable to sort the instances into packets, and emit a packet comprising
a plurality of instances of computation; and

a distributor operable to receive the packet, and distribute the instances among the computation elements, for execution thereon,
based on where data elements associated with the instances are located among the local memories of the computation elements,
wherein

each of the computation elements is operable to combine instances for concurrent execution by the ALUs thereof, for which
the same type of computation is to be performed and which refer to different data elements stored in the local memory thereof,
and to execute the computation for the combined instances of computation.

US Pat. No. 9,430,820

PIXEL CLUSTERING

Imagination Technologies ...

1. A method of generating a composite image, comprising:
for an output pixel of the composite image, receiving a pixel value from each of a plurality of image sources;
computing distance measures between the received pixel values, such that a distance measure is computed for each combination
of pairs of pixel values;

forming clusters of pixel values according to the computed distance measures;
determining a score for each of the clusters;
selecting one of the clusters according to the scores; and
deriving a value for the output pixel from the selected cluster.

US Pat. No. 9,292,365

PRIORITISING EVENTS TO WHICH A PROCESSOR IS TO RESPOND

Imagination Technologies ...

1. A computer system comprising:
a processor configured to respond to events from a plurality of sources; and
a prioritisation module implemented in hardware and configured to prioritise the events for the processor, the prioritisation
module comprising one or more decision modules, wherein at least one of the one or more decision modules comprises:

a plurality of inputs configured to receive respective event flags relating to events from respective sources, wherein each
of the inputs is associated with a respective priority;

OR logic configured to output a flag corresponding to the result of a logical OR operation on the event flags received at
the plurality of inputs;

identification logic configured to identify which of the inputs to receive an asserted flag has the highest priority; and
an output register configured to store a source identifier of the source for which an asserted event flag is received at the
identified input;

wherein the processor is configured to: (i) respond to receiving an asserted flag outputted by one of said one or more decision
modules, by reading the source identifier stored in the output register of said one of the decision modules, and (ii) use
said source identifier to identify a source of an event to which the processor is to respond.

US Pat. No. 9,275,492

METHOD AND SYSTEM FOR MULTISAMPLE ANTIALIASING

Imagination Technologies ...

1. A method for generating three dimensional computer graphics images using multisample antialiasing by sequentially processing
a plurality of primitives, comprising:
dividing at least a first pixel into a plurality of sample areas;
processing a first primitive, by
determining that all the sample areas of the first pixel are located within said first primitive,
storing a value for the first primitive in a multisample memory for a smaller number of the sample areas of the first pixel
than the total number of the sample areas of the first pixel, and

storing data indicating that all the sample areas of the first pixel are located within the first primitive;
subsequently processing a second primitive, by
reading the stored data for the first pixel to determine that all the sample areas of the first pixel are located within the
first primitive,

determining that only some of the sample areas of the first pixel are located within the second primitive,
determining whether the value for the first primitive is already stored in the multisample memory for each sample area of
the first pixel which is not located within the second primitive,

if it is determined that the value for the first primitive is already stored in the multisample memory for each sample area
of the first pixel which is not located within the second primitive, storing a value for the second primitive in the multisample
memory for each sample area of the first pixel which is located within the second primitive without reading from the multisample
memory the value for the first primitive; and

if it is determined that the value for the first primitive is not already stored in the multisample memory for each sample
area of the first pixel which is not located within the second primitive, reading from the multisample memory the value for
the first primitive, writing to the multisample memory the value for the first primitive for each sample area of the first
pixel which is not located within the second primitive for which the value for the first primitive is not already stored,
and storing a value for the second primitive in the multisample memory for each sample area of the first pixel which is located
within the second primitive.

US Pat. No. 9,098,918

GRAPHICS PROCESSOR WITH NON-BLOCKING CONCURRENT ARCHITECTURE

Imagination Technologies ...

1. A computation apparatus, comprising:
a collection of machine processing elements configurable to perform computations;
one or more non-transitory media storing data defining:
a first class of routines that can be instanced for execution on the collection of machine processing elements,
a second class of routines that can be instanced for execution on the collection of machine processing elements, and
a programming interface by which instances of the second class of routines are defined by a respective parent routine, during
execution, each routine of the second class being associated with a respective scheduling key by its parent routine, wherein
a parent routine is one of a routine of the first class of routines, and a routine of the second class of routines; and

scheduler logic configured to schedule the collection of machine processing elements by providing that, during operation,
each instance of a routine of the second class execute (1) independently of other instances of that routine that were instanced
by the same parent routine, and (2) concurrently with other instances of that routine that share a scheduling key, and causing
the collection of machine processing elements to be configured to perform computations indicated by scheduled instances of
routines that were defined by a respective parent routine.

US Pat. No. 9,304,812

MULTI-PHASED AND MULTI-THREADED PROGRAM EXECUTION BASED ON SIMD RATIO

Imagination Technologies ...

1. A multithreaded single instruction multiple data (SIMD) microprocessor, comprising:
a scheduler circuit operable for scheduling execution of phases of program instructions, from programs, wherein the phases
of program instructions from each program have a predetermined relative order of execution, and a respective first phase of
each program initially is to execute on a respective plurality of data instances, and each subsequent phase of each program
is to process a respective subset of the respective plurality of data instances, the subset determined based on results of
feedback from executing a respective preceding phase of that program, the feedback indicating which data instances are to
be processed by which subsequent phase of the program, and the scheduler circuit is configured to:

create, during scheduling of each subsequent phase of the same program, one or more threads to process data instances from
the respective subset of data instances to be processed by that phase, a number of threads created for each subsequent phase
being determined according to a SIMD ratio for that subsequent phase and the results of executing the respective preceding
phase of the same program,

receive an indication of execution completion of each thread, and
maintain a count of threads remaining to be completed for the phase of a program to which a respective thread of the count
of threads belongs, and responsive to the count of threads indicating that all threads for that phase are completed, allow
a subsequent phase of that program to be scheduled; and

a plurality of resources for executing the one or more threads created for scheduled phases, the plurality of resources comprising
an execution pipeline configurable to process a plurality of data instances by a single thread according to the SIMD ratio
for the phase of the program to which that single thread belongs and to produce the results.

US Pat. No. 9,306,687

METHOD AND SYSTEM FOR OBTAINING MUSIC TRACK INFORMATION

Imagination Technologies ...

1. A method to obtain music track information, the method comprising:
storing music track information received from a music information service in a data storage module;
receiving a request at an intermediary server from an end-user device for music track information for a particular music track
currently playing on a particular radio broadcast signal;

determining at the intermediary server if the data storage module comprises music track information for the particular music
track by checking a flag associated with the particular radio broadcast signal;

in response to determining that the data storage module comprises music track information for the particular music track,
transmitting the music track information for the particular music track from the intermediary server to the end-user device;

in response to determining that the data storage module does not comprise music track information for the particular music
track, transmitting a request to the music information service for music track information for the particular music track;

in response to receiving, at the intermediary server, a reply from the music information service comprising music track information
for the music track identified in the request, storing the music track information in the data storage module and setting
the flag associated with the particular radio broadcast signal at the intermediary server to indicate that the data storage
module comprises music track information for the music track currently playing on the particular radio broadcast signal;

determining whether the particular music track has ended; and
in response to determining that the particular music track has ended, setting the flag associated with the particular radio
broadcast signal to indicate that the data storage module does not comprise music track information for the music track currently
playing on the particular radio broadcast signal.

US Pat. No. 9,424,685

UNIFIED RASTERIZATION AND RAY TRACING RENDERING ENVIRONMENTS

Imagination Technologies ...

1. A machine-implemented method of rendering,images in a computer graphics system, comprising:
identifying one or more visible surfaces, from among surfaces in a 3-D scene, the identified on or more visible surfaces comprising
visible surfaces for a plurality of pixels located in 2-D screen space;

preparing, concurrently with the identifying, to execute shaders associated with respective visible surfaces of pixels of
the one or more visible surfaces that have been identified, the preparing comprising completing a respective normalized set
of inputs to be provided to each shader for use during execution, the normalized set of inputs comprising a specified set
of attributes regardless of whether the one or more identified surfaces were identified by ray intersection testing or scan
conversion;

executing each of the shaders in a computation cluster, wherein each of the executing shaders comprises one or more operations,
wherein at least on of the executing shaders comprises defining one or more rays to be tested for intersection with surfaces
in the 3-D scene;

testing at least some of the rays for intersection concurrently with the identifying and the executing of the shaders; and
shading identified intersections for rays completing intersection testing within the computation cluster.

US Pat. No. 9,349,037

SKIN COLOUR PROBABILITY MAP

Imagination Technologies ...

1. A data processing system for performing face detection on a stream of frames of image data, the data processing system
comprising:
a face detector configured to detect a first face candidate in a first frame by performing face detection within first search
tiles defined for the first frame;

a colour measurement unit configured to calculate a set of colour parameters including an average colour of the first face
candidate expressed according to a predefined colour space, one of the axes of the predefined colour space being substantially
oriented in the direction of maximum variation according to a predetermined distribution of skin colour;

a transformation unit configured to:
transform a second frame into the predefined colour space; and
form a skin colour probability map for the second frame by calculating the probability that a given colour is a skin colour
from a measure of the colour space distance of that colour from the calculated average colour in the predefined colour space;
and

a search tile generator configured to generate a plurality of second search tiles based on the skin colour probability map
for use by the face detector, the second search tiles defining areas of the second frame within which the face detector is
to perform face detection so as to detect one or more second face candidates in the second frame.

US Pat. No. 9,350,679

SEQUENCE NUMBER RETRIEVAL FOR VOICE DATA WITH REDUNDANCY

Imagination Technologies ...

1. A method for determining a sequence number indicating a position of a redundant payload of a voice data packet within a
data stream, the method comprising:
unpacking a primary payload, a sequence number associated with the primary payload, a timestamp associated with the primary
payload, a redundant payload, and a timestamp offset associated with the redundant payload from a voice data packet and storing
the sequence number associated with the primary payload and the timestamp associated with the primary payload in a history
of previously received timestamps associated with previous payloads, and previously received or derived sequence numbers associated
with those previous payloads;

calculating a timestamp parameter for the redundant payload based on the timestamp associated with the primary payload and
the timestamp offset;

calculating a time span of the data stream covered by the voice data packet using the timestamp offset;
selecting a portion of the history based on the time span;
comparing the timestamp parameter to one or more of the timestamps in the selected portion of the history to derive a sequence
number for the redundant payload; and

updating the history to include the timestamp parameter and derived sequence number of the redundant payload.

US Pat. No. 9,292,450

MIGRATION OF DATA TO REGISTER FILE CACHE

Imagination Technologies ...

1. A method of migrating data to a register file cache, the method comprising:
storing in a register renaming table an entry for each of a plurality of physical registers, each entry comprising information
indicating each functional unit of a plurality of functional units that has accessed the physical register;

receiving at a migration unit a register read operation to be executed for a particular functional unit,
the register read operation specifying a particular physical register to be read;
reviewing the entries in the register renaming table at the migration unit to determine whether the particular functional
unit has accessed the particular physical register; and

in response to determining the particular functional unit has not accessed the particular physical register, migrating data
to a register file cache associated with the particular functional unit.

US Pat. No. 9,250,961

TASK EXECUTION IN A SIMD PROCESSING UNIT

Imagination Technologies ...

1. A single instruction multiple data (SIMD) processing unit configured to process a plurality of tasks which each include
up to a predetermined maximum number of work items, wherein the work items of a task are arranged for executing a common sequence
of instructions on respective data items, the data items being arranged into blocks of data items, wherein some of the blocks
include at least one invalid data item, and wherein work items which relate to invalid data items are invalid work items,
the SIMD processing unit comprising:
a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing
cycles; and

a control module configured to assemble the work items into the tasks based on the validity of the work items, such that invalid
work items of the particular task are temporally aligned across the group of processing lanes.

US Pat. No. 9,209,988

HARDWARE-BASED BEACON PROCESSING

Imagination Technologies ...

1. A battery-powered Wireless Local Area Network (WLAN) communication device comprising:
an activity sensor operable to identify a packet available to be received at the WLAN communication device;
a physical layer (PHY) module to be awakened to begin receiving the packet, the PHY module operable to decode a full MAC address
from a media access control portion of a header of the packet;

a MAC address parser coupled to the PHY module to receive the MAC address and to determine whether the packet is to be received
at the WLAN communication device by comparing the full MAC address to a MAC address of the WLAN communication device, the
MAC address parser operable to be awakened for performing the comparing and to be shut down after the comparing, wherein packets
to be received include beacon packets; and

a hardware centric Medium Access Controller (MAC) separate from the MAC address parser and comprising a beacon processor capable
of being awakened from a shutdown state to process a beacon packet, wherein the PHY module, the MAC address parser, and the
beacon processor module are operable to be awakened and shutdown independently of each other and of a microprocessor.

US Pat. No. 9,473,290

SYSTEM AND METHODS FOR GENERATING VARIABLE FREQUENCY CLOCK SIGNALS FROM COMMON CLOCK SIGNAL AND USAGE THEREOF

Imagination Technologies ...

1. A method of clocking modules of a System On Chip (SOC), the modules comprising a first module that outputs data for receipt
by a second module, the method comprising:
producing, for the first module, a clock signal with a repeating pulse pattern, based on a common clock, by deleting pulses
in the common clock that occur at times when the second module would not be able to receive and process a data element outputted
by the first module;

producing, for the second module, a clock signal with a repeating pulse pattern, based on the common clock, for clocking the
second module to process each data element received from the first module wherein the repeating pulse pattern of the clock
signal for the second module has pulses of the same duration as the common clock, but has a lower duty cycle and frequency
than the common clock;

generating a signal, at the first module, indicating that a data element is available to be received by the second module;
generating a signal, at the second module, indicating that the second module is ready to receive a data element; and
indicating to the first module that transfer of a data element can begin, responsive to a coincidence of the generated signals
from the first module and the second module and a co-occurrence of clock pulses in the clock signals produced for the first
module and the second module.

US Pat. No. 9,466,091

ATOMIC MEMORY UPDATE UNIT AND METHODS

Imagination Technologies ...

1. A machine-implemented method of updating a memory, comprising:
receiving, from a computation unit, a request to update a memory, the request including a first value to be used to update
a specified location in the memory and a condition to be satisfied in order for the first value to be used to update the specified
location in the memory, the condition comprising a reference to a second location in the memory, and a criterion to be satisfied
by a value in the second location in the memory;

accessing the second location in the memory; and
determining whether the value in the second location in the memory satisfies the criterion, and if so, then using the first
value to update the specified location in the memory atomically,

wherein atomically comprises that the value in the specified location in the memory is not changed between a time that the
value in the second location in the memory is accessed and a time that the specified location in the memory is updated using
the first value.

US Pat. No. 9,336,623

MULTILEVEL DISPLAY CONTROL LIST IN TILE BASED 3D COMPUTER GRAPHICS SYSTEM

Imagination Technologies ...

1. A method for rendering a computer graphics image from a 3-D scene in a computer graphics system configured to use a rendering
space which is divided into a plurality of tiles, wherein the plurality of tiles are grouped into a plurality of tile blocks,
and the plurality of tile blocks are grouped into a plurality of macrotiles, the method comprising:
grouping primitives of said 3-D scene into primitive blocks;
for each primitive block, determining a macrotile overlapped by that primitive block, and writing a pointer for that primitive
block in a macrotile control list for said macrotile;

for each tile block of a macrotile, generating control stream data indicating whether a primitive block that overlaps said
macrotile is to be processed for that tile block;

for each tile of a tile block for which a primitive block is to be processed, generating a tile indication indicating whether
said primitive block is to be processed or is not to be processed for that tile; and

using said macrotile control list, control stream data and tile indications to render primitive data into said image.

US Pat. No. 9,304,934

REGISTER FILE HAVING A PLURALITY OF SUB-REGISTER FILES

Imagination Technologies ...

1. A register file for use in an out-of-order processor, the register file comprising:
a plurality of sub-register files, each sub-register file comprising at least one physical register; and
a plurality of buffers, each buffer being associated with a sub-register file and arranged to:
receive write operations destined for the associated sub-register file;
store each received write operation in the buffer;
receive a write value for each write operation stored in the buffer;
store each received write value in the buffer;
in response to storing a write value for a particular write operation, identify that particular write operation as a waiting
write operation;

determine, each clock cycle, whether there is at least one waiting write operation in the buffer; and
in response to determining there is at least one waiting write operation in the buffer, select one of the waiting write operations
and issue the selected write operation to the associated sub-register file.

US Pat. No. 9,239,866

METHOD, SYSTEM AND DEVICE FOR CONNECTING SIMILAR USERS

Imagination Technologies ...

1. A method to connect users based on live audio listening information, the method comprising:
storing, using computer storage media, audio listening information for a plurality of users, the information for each user
comprising information identifying audio the user is currently listening to;

automatically generating, at a server, a list of users that are currently listening to the same audio as a particular user
based on the audio listening information stored in the computer storage media;

filtering, at the server, the list of users to include only those users in a same geographic area as the particular user;
and

transmitting contact information for those users in the filtered list of users from the server to an end-user device associated
with the particular user, the contact information enabling the particular user to communicate with at least one of the users
on the filtered list.

US Pat. No. 9,235,921

PROFILING RAY TRACING RENDERERS

Imagination Technologies ...

1. A non-transitory machine readable medium storing machine executable instructions that when executed cause at least one
processor to:
render, using ray tracing, a first frame buffer comprising color information for pixels in a viewport, the first frame buffer
rendered from a 3-D scene description, comprising geometry defining objects in the scene, respective shader code modules defining
how the objects are to interact with light impinging on surfaces of the objects, and one or more sources of light in the scene;
and

generate a second frame buffer with entries corresponding to pixels in the viewport, the second frame buffer comprising color
information for each entry of the second frame buffer, the color information for each entry in the second frame buffer determined
according to a relative computational complexity measured during the rendering of the first frame buffer in determining the
color information for a pixel in the first frame buffer corresponding to that entry in the second frame buffer, including
mapping the relative computational complexity to a shading or coloration,

wherein the relative computational complexity according to which the color information for each entry in the second frame
buffer is determined is:

a number of rays that were used to render the pixel in the first frame buffer corresponding to that entry in the second frame
buffer; or

a number of tests performed in an acceleration structure in order to render the pixel in the first frame buffer corresponding
to that entry in the second frame buffer.

US Pat. No. 9,161,250

TRANSMISSION FREQUENCY SPECTRUM SCANNING

Imagination Technologies ...

1. A method of scanning a transmission spectrum, the method comprising:
analysing received signals over the transmission spectrum to determine an estimate of signal strength of the received signals
as a function of frequency over the transmission spectrum;

using the estimate of the strength of the received signals to identify candidate transmission channel frequencies within the
transmission spectrum by: (i) performing edge detection on the estimate of the strength of the received signals in the frequency
domain, and (ii) using the edge detection to search for a pattern in the estimate of the strength of the received signals
in the frequency domain which is indicative of a candidate transmission channel, said pattern comprising a rising edge, a
frequency interval and a falling edge, wherein the frequency interval between the rising edge and the falling edge is suitable
for a transmission channel; and

performing a targeted scan over the transmission spectrum based on the identified candidate transmission channel frequencies
to thereby identify at least one transmission channel within the transmission spectrum.

US Pat. No. 9,086,721

ALLOCATING RESOURCES TO THREADS BASED ON SPECULATION METRIC

Imagination Technologies ...

1. A method of allocating resources between a plurality of threads in a processor, each thread being associated with a plurality
of instructions, the method comprising:
receiving, at a reservation station, a speculation metric for each thread of the plurality of threads, each speculation metric
representing an extent to which the instructions associated with the thread are speculative;

allocating, at the reservation station, functional unit resources to the plurality of threads based on the speculation metrics,
comprising:

comparing the speculation metrics to identify a thread with less speculative instructions;
determining a difference between the speculation metric for the thread with less speculative instructions and a speculation
metric for another thread; and

in response to determining the difference exceeds a threshold, allocating additional functional unit resources to the thread
with less speculative instructions;

selecting, at the reservation station, instructions associated with the plurality of threads based on the allocation of functional
unit resources; and

issuing, at the reservation station, the selected instructions to the functional unit resources.

US Pat. No. 9,444,567

METHOD AND APPARATUS FOR TIME SYNCHRONISATION IN WIRELESS NETWORKS

Imagination Technologies ...

1. A wireless network, comprising:
a first wireless station comprising a first physical layer clock, a first software clock, and a first clock interface coupled
to the first physical layer clock and to the first software clock;

a second wireless station comprising a second physical layer clock, a second software clock, and a second clock interface
coupled to the second physical layer clock and to the second software clock; and

an access point having a third physical layer clock,
wherein the access point is configured to encode and broadcast a beacon frame over the wireless network, the beacon frame
comprising a timestamp derived from the third physical layer clock,

wherein the first wireless station is configured to receive the beacon frame and decode the timestamp, to control the first
physical layer clock in dependence on the timestamp, and the first clock interface is configured to control the first software
clock in dependence on the first physical layer clock, and

wherein the second wireless station is configured to receive the beacon frame and decode the timestamp, to control the second
physical layer clock in dependence on the timestamp, and the second clock interface is configured to control the second software
clock in dependence on the second physical layer clock, to synchronize the second software clock with the first software clock.

US Pat. No. 9,445,117

ERROR TRACKING AND MITIGATION FOR MOTION COMPENSATION-BASED VIDEO COMPRESSION

Imagination Technologies ...

1. A method of tracing an error in a frame of a video to a subsequent frame of the video, each frame in the video being divided
into a plurality of blocks arranged in a number of rows and columns, each frame of the video being encoded by a technique
that comprises generating motion vectors for blocks of the frame, the method comprising:
(a) receiving an error notification message at an encoder, the error notification message comprising information identifying
an erroneous frame of the video and information identifying portions of the erroneous frame detected as having an error during
decoding;

(b) identifying, at the encoder, the frame immediately following the erroneous frame as a reference frame;
(c) obtaining, at the encoder, minimum and maximum horizontal motion vector components for each column of blocks of the reference
frame;

(d) obtaining, at the encoder, minimum and maximum vertical motion vector components for each row of blocks of the reference
frame; and

(e) identifying, at the encoder, a rectangular region of blocks of the reference frame that the error is likely to have propagated
to from the minimum and maximum horizontal and vertical motion vector components for the reference frame;

wherein identifying the rectangular region of the reference frame comprises:
identifying, at the encoder, rows of the reference frame that the error is likely to have propagated to from the maximum and
minimum vertical motion vector components for the reference frame; and

identifying, at the encoder, columns of the reference frame that the error is likely to have propagated to from the maximum
and minimum horizontal motion vector components for the reference frame; wherein the rectangular region of the reference frame
is defined as the intersection of the identified rows and columns.

US Pat. No. 9,361,242

RETURN STACK BUFFER HAVING MULTIPLE ADDRESS SLOTS PER STACK ENTRY

Imagination Technologies ...

1. A method of operating a processor, comprising:
in response to a function call, storing an address following the function call in one of a plurality of address slots in a
top entry in a return stack buffer, updating a stack pointer and at least one stack pointer bit to point to the entry and
the address slot in which the address was stored and setting a value of two or more pointer bits in the entry, the two or
more pointer bits comprising a first part indicating at least a most recently written address slot in the entry and a second
part indicating, for each of the plurality of address slots in the entry, a most recently written address slot in the previous
entry at the time that the particular one of the plurality of address slots in the entry was written; and

in response to a function return, reading an address from an address slot in an entry in the return stack buffer identified
by the stack pointer and at least one stack pointer bit, updating the stack pointer to point to the previous entry, and updating
the at least one stack pointer bit based on the second part of the pointer bits for the entry and the address slot from which
the address was read.

US Pat. No. 9,194,902

NOISE VARIANCE ESTIMATION AND INTERFERENCE DETECTION

Imagination Technologies ...

1. A method of estimating noise variance within an orthogonal frequency division multiplexing (OFDM) receiver, the method
comprising:
evaluating, by estimating logic associated with said receiver, a noise estimate for each of a plurality of pilots within one
or more received OFDM symbols;

dividing, by dividing logic associated with said receiver, the plurality of pilots into bands;
calculating, by calculating logic associated with said receiver, a noise variance estimate for each band by averaging noise
estimates for pilots within the band;

storing the noise variance estimate for each band in memory;
setting, by an interpolation engine associated with said receiver, a noise variance estimate for a pilot equal to the calculated
noise variance estimate for the band which includes the pilot; and

determining, by said interpolation engine, a noise variance estimate for a data sub-carrier within the one or more received
OFDM symbols by interpolating between the noise variance estimates for each pilot; wherein

the determined noise variance estimate is used by said OFDM receiver in decoding at least one received OFDM symbol.

US Pat. No. 9,189,241

METHOD AND APPARATUS FOR SCHEDULING THE ISSUE OF INSTRUCTIONS IN A MULTITHREADED MICROPROCESSOR

Imagination Technologies ...

1. A method for dynamically determining which instructions from a plurality of available instructions issue in each clock
cycle in a multithreaded processor capable of issuing a plurality of instructions in each clock cycle, the method comprising
the steps of:
determining a highest priority instruction from the plurality of available instructions;
determining a compatibility of the highest priority instruction with each of the available instructions; and
issuing the highest priority instruction together with other instructions compatible with the highest priority instruction
in the same clock cycle,

wherein the highest priority instruction cannot be a speculative instruction, the speculative instruction being defined as
an instruction fetched and/or issued that may not be necessary because an outcome of an earlier program instruction is not
yet known.

US Pat. No. 9,430,864

SYSTEMS AND METHODS FOR 3-D SCENE ACCELERATION STRUCTURE CREATION AND UPDATING

Imagination Technologies ...

1. A machine-implemented method of producing an acceleration structure for use in rendering a computer graphics image from
a three dimensional (3-D) scene, comprising:
mapping, by a processor, a set of primitives to nodes of a working spatial subdivision of the 3-D scene, each node of the
working spatial subdivision enclosing a 3-D volume within the 3-D scene;

representing each of the nodes with a respective temporary data structure stored in a non-transitory machine-readable medium,
the data in that temporary data structure including data identifying one or more of a parent node, a child node and primitives,
of the set of primitives, that were mapped to that node;

defining, by a processor, elements of a hierarchical acceleration structure, from inputs comprising data from a selection
from among the temporary data structures, the defining comprising determining a respective 3-D volume for each of the elements
of the hierarchical acceleration structure from 3-D volumes within the nodes of the working spatial subdivision that correspond
to the selected temporary data structures, and

producing a hierarchical acceleration structure in a non-transitory machine-readable medium, using said determined 3-D volumes.

US Pat. No. 9,424,203

STORING LOOK-UP TABLE INDEXES IN A RETURN STACK BUFFER

Imagination Technologies ...

1. A method of operating a processor, comprising:
in response to a function call, storing an address following the function call in an entry in a look-up table and pushing
an index of the entry into a return stack buffer; and

in response to a function return, removing a most recently written index from the return stack buffer and using the removed
index to access an address stored in the look-up table.

US Pat. No. 9,413,387

DATA COMPRESSION USING ENTROPY ENCODING

Imagination Technologies ...

1. An entropy decoding module configured to perform entropy decoding on a sequence of entropy encoded data values, wherein
the entropy encoded data values have been encoded according to a predetermined variable-length entropy coding scheme such
that each of the entropy encoded data values comprises one or more first bits and zero or more second bits, wherein for each
of the encoded data values the number of first bits is related to the number of second bits according to a predetermined relationship
of the entropy coding scheme, and wherein each of a plurality of bit locations in the sequence of entropy encoded data values
is predetermined by the entropy coding scheme to include either a first bit or a second bit, the entropy decoding module being
configured to:
receive the sequence of entropy encoded data values;
separate the first bits of the received entropy encoded data values from the second bits of the received entropy encoded data
values based on the bit locations of the bits in the sequence of entropy encoded data values in accordance with the entropy
coding scheme;

analyse the separated first bits of the received entropy encoded data values to determine bit-boundaries between the received
entropy encoded data values in accordance with the predetermined relationship between the number of first bits and the number
of second bits for each of the received encoded data values; and

use the second bits and the determined bit-boundaries to decode the entropy encoded data values in accordance with the predetermined
variable-length entropy coding scheme.

US Pat. No. 9,407,578

SYSTEM AND METHOD OF ARBITRATING ACCESS TO INTERCONNECT

Imagination Technologies ...

1. A method of arbitrating for access to an interconnect, comprising:
receiving, over time, one or more data transfer requests, each indicating an input port from n input ports, and an output
port of m output ports in an interconnect, through which the request will be serviced;

buffering each of the requests;
assigning a respective empty arbitration packet to a respective picker assigned to each of the input ports, each arbitration
packet having a location for each of the m output ports;

at each of the pickers, selecting at least one buffered request and placing each selected request in the arbitration packet
at said each picker in the location for the output port indicated by the selected request;

passing the arbitration packets among the pickers until each picker has received each arbitration packet, and while each picker
has each arbitration packet, attempting to place at least one request in any remaining location in that arbitration packet;
and

scheduling fulfillment of the requests using the interconnect according to the placement of the requests in the arbitration
packets.

US Pat. No. 9,367,286

CROSSING PIPELINED DATA BETWEEN CIRCUITRY IN DIFFERENT CLOCK DOMAINS

Imagination Technologies ...

1. A method of crossing pipelined control and data between clock domains in a multi-clock domain integrated circuit, comprising:
storing, by a first circuit clocked by a first clock, an element of control information in a control queue,
storing, by said first circuit, an element of data in a data queue, after a pipeline delay characterized by a pre-set number
of clock events of the first clock;

initializing a counter to an initial value;
updating the counter; and
reading the element of control information from the control queue by a second circuit clocked by a second clock operating
at a different frequency than the first clock, responsive to the counter reaching a pre-determined value, and then reading
the element of data from the data queue after the pre-set number of clock events have occurred for the second clock.

US Pat. No. 9,294,173

LOW COMPLEXITY SOFT OUTPUT MIMO DECODER

Imagination Technologies ...

1. A method of receiving data transmitted in a MIMO system, wherein the data is transmitted from a transmitter over a MIMO
channel as a transmit vector comprising a plurality of values, the method comprising:
receiving the data as a receive vector comprising a plurality of values, the data being received over the MIMO channel at
a receiver in which the MIMO channel is represented as a combination of a unitary matrix and a triangular matrix, wherein
there is a relationship linking: (i) a function of the unitary matrix and the receive vector, and (ii) a multiplication of
the triangular matrix and the transmit vector;

determining a set of candidate vectors for representing the transmit vector by: for each of a plurality of constellation points,
setting a particular value of a corresponding candidate vector to that constellation point and using the relationship and
the particular value which is set to map other values of the candidate vector to constellation points, thereby determining
the set of candidate vectors in which the particular value within the candidate vectors is set to be respective ones of the
constellation points; and using the set of candidate vectors at the receiver to determine soft bits representing the plurality
of values of the transmit vector;

wherein said using the set of candidate vectors to determine the soft bits comprises determining a best matching candidate
vector to the transmit vector by finding the candidate vector which when used to estimate the receive vector using a MIMO
channel matrix which represents the MIMO channel provides a closest estimate to the receive vector.

US Pat. No. 9,282,154

METHOD, SYSTEM AND DEVICE FOR SELECTING A DEVICE TO SATISFY A USER REQUEST

Imagination Technologies ...

1. A method to select an end-user device from a plurality of end-user devices to satisfy a user request, the method comprising:
storing at a portal aggregator data identifying a device group, the data identifying the device group comprising data identifying
at least one user associated with the device group and data identifying a least one capability for each of a plurality of
end-user devices associated with the device group;

receiving a request at the portal aggregator from the user, the request comprising information identifying the user and information
identifying an action;

identifying, at the portal aggregator, the device group associated with the user based on the information identifying the
user;

generating, at the portal aggregator, a list of end-user devices from the identified device group having the capability to
execute the action;

receiving priority information from the user for at least a portion of the end-user devices at the portal aggregator;
performing at least one of filtering and sorting on the list at the portal aggregator based on the priority information;
selecting, at the portal aggregator, an end-user device from the filtered and/or sorted list of end-user devices to execute
the action; and

transmitting a command from the portal aggregator to the selected end-user device to execute the action.

US Pat. No. 9,460,547

SYSTEMS AND METHODS FOR PROGRAM INTERFACES IN MULTIPASS RENDERING

Imagination Technologies ...

1. A machine-implemented method of 3-D rendering, comprising:
establishing a frame buffer having respective locations for storing results of a rendering process that produces pixels of
a frame of pixels;

executing a shader on a processor, the executing comprising storing a value in a location in the frame buffer, and emitting
a definition of a ray to be traced, the definition of the ray comprising identification of a temporary buffer location that
is distinct from the location in the frame buffer where the value was stored;

identifying an intersection between the ray and an element of 3-D geometry;
shading the intersection, the shading comprising determining a value and causing the determined value to be stored in the
temporary buffer location; and

combining contents of the temporary buffer location with the contents of the location in the frame buffer.

US Pat. No. 9,461,702

SYSTEMS AND METHODS OF ECHO AND NOISE CANCELLATION IN VOICE COMMUNICATION

Imagination Technologies ...

1. A machine-implemented method of echo cancellation in a full duplex voice communication system, comprising:
performing acoustic echo cancellation on a near-end signal using a short time domain adaptive filter, to produce a filtered
near-end signal that may have non-linear residual echo and noise;

tracking, in the frequency domain, the non-linear residual echo in the filtered near-end signal to output an error signal;
producing an estimate of a portion of the filtered near-end signal to be removed, as a combination of the non-linear residual
echo, and noise;

imposing a limitation on the estimate based on a moving average of the error signal;
controlling gains associated with a plurality of frequency bins in a Frequency domain Automatic Gain Controller (FAGC), based
on the limited estimate, thereby suppressing the estimated portion of the filtered near-end signal to be removed; and

refining respective gains associated with the plurality of frequency bins of the FAGC.

US Pat. No. 9,391,739

EFFICIENT DEMAPPING OF CONSTELLATIONS

Imagination Technologies ...

1. A method of demapping received symbols in a digital communications receiver, the method comprising:
receiving, at an input, a received symbol;
identifying a closest constellation point to the received symbol using an iterative slicing process and based on calculations
of a sign of a difference between distance metrics, the distance metrics running parallel to one row or one column of constellation
points;

computing a minimum distance metric from the received symbol to the closest constellation point;
calculating soft information for each bit in the received symbol using the computed minimum distance metric from the received
symbol to the closest constellation point; and

outputting the soft information for use by a decoder within the receiver.

US Pat. No. 9,436,470

RESTORING A REGISTER RENAMING MAP

Imagination Technologies ...

1. A method of restoring a register renaming map in an out-of-order processor, comprising:
updating a register commit map whenever an instruction is output from a re-order buffer to a commit stage, wherein the register
commit map is updated using the re-order buffer values for the mapping between a destination architectural register and a
physical register for each instruction output from the re-order buffer;

in response to detecting an unexpected change in instruction flow, marking the instruction in the re-order buffer as requiring
restore;

flushing a front end of the processor, including a fetch stage and a decode and renaming stage;
fetching instructions from a correct address;
waiting until the marked instruction is output to the commit stage; and
restoring the register renaming map using the register commit map.

US Pat. No. 9,348,600

PRIORITISING OF INSTRUCTION FETCHING IN MICROPROCESSOR SYSTEMS

Imagination Technologies ...

1. A method for prioritizing fetching of instructions from at least one source of instructions in a multithreaded processor
system, comprising:
receiving from a plurality of threads executing on said multithreaded processor system requests to fetch instructions from
a source of instructions;

determining a first metric for each thread based on the number of instructions that are currently buffered for that thread;
determining a second metric for each thread respectively based on at least one execution parameter for that thread;
determining a ranked priority order for said plurality of threads by combining the first metrics and the second metrics for
each thread; and

fetching an instruction from the source for the thread with the highest priority in the ranked priority order.

US Pat. No. 9,489,174

ROUNDING FLOATING POINT NUMBERS

Imagination Technologies ...

1. A floating point arithmetic unit comprising:
a rounding module configured to receive an unrounded result, the rounding module further comprising:
a multiplexer configured to select one of:
a first bitstring selected from a first plurality of bitstrings, wherein each bitstring in the first plurality of bitstrings
comprises a corresponding bit sequence of the unrounded result, or

a second bitstring selected from a second plurality of bitstrings, wherein each bitstring in the second plurality of bitstrings
comprises a corresponding bit sequence of an incremented result obtained by incrementing the unrounded result, and

wherein the selection of the first or second bitstring is based on bits in the unrounded result and is not dependent upon
the incremented unrounded result.

US Pat. No. 9,182,899

PAGING WITHIN A SCROLLABLE LIST

Imagination Technologies ...

1. A touch sensitive display system including a processor, the system being configured to display data which is scrollable
in response to swiping of a finger on a touch sensitive display having a display area length, the system being responsive
to a swipe of a predetermined length over the touch sensitive display to scroll a display of said data on said touch sensitive
display such that said data traverses through said display area length from one end thereof to the other end thereof, wherein
said predetermined length is shorter than said display area length, and said system being responsive to a swipe over the touch
sensitive display of a second length longer than said predetermined length, to scroll the display of said data through said
display area length by an amount proportional to said second length.

US Pat. No. 9,300,419

PROXIMITY DETECTION

Imagination Technologies ...

1. A method of estimating the proximity of a first device to a second device in a network of devices comprising at least the
first and second devices, each device in the network being configured to communicate according to a predetermined wireless
communications protocol, the method comprising:
analysing at the first device a first control message which according to the communications protocol instructs the first device
to perform a first channel quality measurement during a first period of time;

broadcasting a second control message over the network which according to the communications protocol instructs devices connected
to the network to not transmit during the first period of time to enable the first channel quality measurement to be performed;

at the second device, disregarding the second control message and transmitting a first signal during at least a portion of
the first period of time;

at the first device, performing the first channel quality measurement in response to the first control message during the
first period of time; and

forming a measure of the proximity of the first device to the second device in dependence on a strength of the first signal
received at the first device during said first channel quality measurement.

US Pat. No. 9,299,187

OPACITY TESTING FOR PROCESSING PRIMITIVES IN A 3D GRAPHICS PROCESSING SYSTEM

Imagination Technologies ...

1. A method of processing a primitive in a 3D graphics processing system to apply depth testing and texturing to the primitive,
wherein the primitive has a non-opaque object type, and wherein the texturing comprises texturing fragments of the primitive
in accordance with the object type associated with the fragments, the method comprising:
receiving fragments of the primitive to be processed, the received fragments of the primitive being associated with said non-opaque
object type;

prior to applying texturing to received fragments of the primitive:
(i) obtaining an opacity state map which provides indications of the opacity of texture elements (texels) of a texture that
is to be applied to the primitive;

(ii) for each of a plurality of blocks of one or more fragments of the primitive, using the opacity state map to determine
a respective opacity state for the fragment block by: (a) determining the position of a block of opacity states within the
opacity state map for the fragment block based on the texture co-ordinates of one or more fragments of the fragment block,
and (b) determining the opacity state for the fragment block based on a predefined combination of the opacity states of the
opacity state block; and

(iii) using the determined opacity states for the fragment blocks to perform one or more of: (a) based on the determined opacity
states, indicating that the fragments of one or more of the fragment blocks are to be associated with a different object type
to said non-opaque object type for subsequent processing of the fragments, (b) discarding one or more of the fragment blocks
based on the determined opacity states, and (c) based on the determined opacity states, setting one or more flags to indicate
that the fragments of one or more of the fragment blocks are not to be transmitted for subsequent texturing;

applying depth testing to fragments of the primitive; and
applying texturing to fragments of the primitive in accordance with their associated object types as adjusted based on said
fragment block opacity states.

US Pat. No. 9,210,422

METHOD AND SYSTEM FOR STAGGERED PARALLELIZED VIDEO DECODING

Imagination Technologies ...

1. A system, comprising:
a frame boundary parser to receive a compressed video stream and to identify even frames and odd frames from the video stream;
a memory to store the even and odd frames;
a first decoder operatively coupled to the memory and structured to process first and second portions of each of the stored
even frames, the first portion corresponding to an L number of lines of an even frame, wherein the L number of lines corresponds
to a height of a reference area of the even frame; and

a second decoder operatively coupled to the memory and structured to process each of the stored odd frames after the first
decoder processes a corresponding first portion of a related even frame from among the stored even frames.

US Pat. No. 9,183,668

RAY TRACING SYSTEM ARCHITECTURES AND METHODS

Imagination Technologies ...

1. A system for 3-D graphics processing using ray tracing, comprising:
a plurality of computation units, collectively capable of performing a sequence of ray tracing operations using a set of data
elements, the ray tracing operations comprising operations to be performed during one or more of acceleration structure traversal
and primitive intersection testing;

an input buffer;
a controller, for the plurality of computation units, coupled to the input buffer, the controller operably configured to determine
a sequence of sets of data elements to be inputted to the plurality of computation units, wherein

each set of input data elements is selected from data elements received at the input buffer,
the input buffer operates asynchronously from the plurality of computation units for receiving groupings of data elements
to be processed by the plurality of computation units,

the groupings potentially having different numbers of data elements, and
the controller is operably configured to aggregate data elements from groupings received at different times respectively into
one of the sets of data elements to be provided to the plurality of computation units, wherein the plurality of computation
units are operable to output results of acceleration structure traversal and to use the results to determine further ray tracing
operations to be performed with the data elements.

US Pat. No. 9,088,336

SYSTEMS AND METHODS OF ECHO AND NOISE CANCELLATION IN VOICE COMMUNICATION

Imagination Technologies ...

1. A system for controlling a Non-Linear Processor (NLP) to activate and deactivate the NLP for complete removal of residual
echo in an echo alone region of a microphone output signal without chopping of a near-end speech signal, the system comprising:
a detector for detecting convergence of an adaptive echo cancellation filter;
a module for updating an NLP energy threshold parameter;
a Single Talk (ST) hangover breaker arranged to break a ST hangover based on said updated NLP energy threshold parameter;
a Double Talk (DT) hangover breaker arranged to break a DT hangover based on a predetermined fall in near-end energy or a
predetermined rise in echo energy;

an estimator configured to produce respective estimates for a plurality of decision parameters including convergence of said
adaptive echo cancellation filter;

a controller to output a NLP decision for a frame of speech, wherein the NLP decision indicates whether the NLP is to be active
or inactive based on estimates from said estimator; and

a module for revising the NLP decision based on revised estimates from said estimator.

US Pat. No. 9,075,724

METHOD AND APPARATUS FOR ENSURING DATA CACHE COHERENCY

Imagination Technologies ...

1. A system capable of concurrently executing a plurality of threads, comprising:
a processor capable of concurrently executing a plurality of threads;
a memory storing data accessible by each of the plurality of threads, through a memory interface; and
an incoherency detection module coupled with the processor and configured to maintain data for each outstanding global write
memory transaction, detect a conflict between any of the outstanding global write memory transactions and a new read memory
transaction, and responsive to detecting a conflict between a specific outstanding global write memory transaction and the
new read memory transaction, to generate barrier data sequenced with respect to the specific global write memory transaction
for which the conflict was detected, the barrier data comprising an identifier of the new read memory transaction, and

wherein the memory interface is operable to prevent the new read memory transaction from being performed until the sequence
of the specific global write memory transaction and the barrier have been processed by the memory interface.

US Pat. No. 9,351,252

METHOD AND SYSTEM FOR WIRELESSLY TRANSMITTING DATA

Imagination Technologies ...

1. A method to wirelessly transmit data, the method comprising:
generating at a first Wi-Fi station data to be transmitted to another Wi-Fi station, the data comprising at least one of status
data and wake-up data;

inserting at the first Wi-Fi station the generated data in a vendor-specific information element of a probe request frame;
and

wirelessly transmitting at the first Wi-Fi station the probe request frame;
wherein the first Wi-Fi station and the other Wi-Fi station are configured to wirelessly communicate via a Wi-Fi network established
by an access point, and the probe request frame is transmitted by the first Wi-Fi station when the first Wi-Fi station does
not have a valid IP address, or the probe request frame is received by the other Wi-Fi station when the other Wi-Fi station
does not have a valid IP address.

US Pat. No. 9,106,788

OBJECT TRACKING USING MOMENTUM AND ACCELERATION VECTORS IN A MOTION ESTIMATION SYSTEM

Imagination Technologies ...

1. A method for motion estimation in a sequence of video images, comprising:
a) subdividing each field or frame of a sequence of video images into a plurality of blocks;
b) assigning to each block in each video field or frame a respective set of candidate motion vectors;
c) determining for each block in a current video field or frame, which of its respective candidate motion vectors produces
a best match to a block in a previous video field or frame;

d) forming a motion vector field for the current video field or frame using the thus determined best match vectors for each
block;

e) forming a further motion vector field by, for each block in a current field or frame, storing a further motion vector derived
from the best match vector for that block at a block location offset by a distance determined based on said further motion
vector; and

f) repeating steps a) to e) for a following video field or frame, wherein the set of candidate motion vectors assigned at
step b) to a respective block in the following video field or frame includes said further motion vector stored at that block
location at step e) during the current video field or frame.

US Pat. No. 9,424,030

TRAILING OR LEADING ZERO COUNTER HAVING PARALLEL AND COMBINATIONAL LOGIC

Imagination Technologies ...

1. A zero counter comprising a plurality of hardware logic blocks each arranged to calculate one bit of an output value, the
output value corresponding to a number of trailing or leading zeros in an input string, wherein a first of the plurality of
hardware logic blocks is arranged to calculate a least significant bit of the output value and comprises:
a low section hardware logic block comprising inputs arranged to receive bits from a first section of the input string including
a least significant bit in the input string and one or more logic gates arranged to combine the received bits and generate
at least one output;

a high section hardware logic block comprising inputs arranged to receive bits from a second section of the input string including
a most significant bit in the input string and one or more logic gates arranged to combine the received bits and generate
at least one output, wherein the first and second sections of the input string are non-overlapping and comprise all the bits
in the input string; and

combining logic arranged to combine the outputs of the low and high section hardware logic blocks to generate the least significant
bit of the output value,

and wherein other hardware logic blocks in the plurality of hardware logic blocks are each arranged to calculate a bit of
index i of the output value where i is an integer, each comprising:

a) i OR reduction stages arranged in series, a first of the i OR reduction stages arranged to receive the input string and
comprising one or more OR gates arranged to combine adjacent bits in the input string to generate an output string and at
least one subsequent stage of the i OR reduction stages arranged to receive the output string from a preceding OR reduction
stage and comprising one or more OR gates arranged to combine adjacent bits in the received string to generate a further output
string;

b) a low section hardware logic block comprising inputs arranged to receive bits from a first section of the string output
by a last OR reduction stage in the series, the first section including a least significant bit in the received string and
one or more logic gates arranged to combine the received bits and generate at least one output;

c) a high section hardware logic block comprising inputs arranged to receive bits from a second section of the string output
by a last OR reduction stage in the series, the second section including a most significant bit in the received string and
one or more logic gates arranged to combine the received bits and generate at least one output, wherein the first and second
sections of the received string are non-overlapping and comprise all the bits in the received string; and

d) combining logic arranged to combine the output of the two section hardware logic blocks and generate a bit of index i of
the output value.

US Pat. No. 9,612,800

IMPLEMENTING A SQUARE ROOT OPERATION IN A COMPUTER SYSTEM

Imagination Technologies ...

1. A method of implementing a square root operation in a computer system to determine a value of ?{square root over (b)}, where b is an input value, comprising:
obtaining an initial approximation of

 denoted as p0; and for iterations in which an iteration index i=0, . . . , c, c being a predetermined number greater than or equal to 0:

(i) performing a first computation using multiplier logic of the computer system to determine a first intermediate parameter
ri based on a multiplication of the input value b with pi;

(ii) performing a second computation using the multiplier logic to determine a second intermediate parameter si based on a multiplication of the first intermediate parameter ri with pi;

(iii) when i denoted as pi+1 using the multiplier logic based on a multiplication of the second intermediate parameter si with pi, incrementing i, and repeating steps (i) and (ii); and
(iv) when i=c, computing with the multiplier logic the value of ?{square root over (b)} based on a multiplication of first intermediate parameter rc with second intermediate parameter sc.

US Pat. No. 9,478,002

VERTEX PARAMETER DATA COMPRESSION

Imagination Technologies ...

1. A method of compressing vertex parameter data in a computer graphics system, wherein the vertex parameter data comprises
a data block comprising data of vertices relating to at least one parameter, the data of each of the vertices includes a plurality
of data segments at respective positions, the method comprising:
analysing the data in the data block to determine a compression grouping scheme for grouping data segments of the vertices
into segment blocks for compression;

grouping together data segments of the vertices according to the determined compression grouping scheme to form a plurality
of segment blocks, the compression grouping scheme being determined such that each of the segment blocks includes a plurality
of segment sets of one or more data segments of a respective plurality of the vertices, the segment sets having corresponding
positions within the data of each of the plurality of the vertices;

compressing at least one of the segment blocks; and
subsequent to said compressing at least one of the segment blocks, using the segment blocks to form a compressed data block.

US Pat. No. 9,519,611

HARDWARE DATA STRUCTURE FOR TRACKING ORDERED TRANSACTIONS

Imagination Technologies ...

1. A hardware data structure configured to track a plurality of ordered transactions in a multi-transactional hardware design,
the hardware data structure comprising:
a counter configured to store a value that tracks a number of in-flight transactions in the hardware design;
a table configured to track an age of each of the in-flight transactions using the counter; and
control logic configured to verify that a transaction response issued by the hardware design has been issued in a predetermined
order based on the tracked ages of the in-flight transactions in the table.

US Pat. No. 9,544,422

ACOUSTIC ECHO SUPPRESSION

Imagination Technologies ...

1. A controller for an echo suppressor configured to suppress a residual echo of a far-end signal included in a primary error
signal, the controller adapted for operation with a primary adaptive filter configured to form a primary echo estimate of
the far-end signal included in a microphone signal and with an echo canceller configured to cancel that primary echo estimate
from the microphone signal so as to form the primary error signal, the controller comprising:
a coherence estimator configured to form a first measure of coherence between the microphone signal and the primary error
signal, and a second measure of coherence between the microphone signal and the primary echo estimate; and

control logic configured to, when the primary adaptive filter is in a converged state, combine the first and second measures
of coherence so as to form one or more first steady state decision parameters indicative of a state of the microphone signal
and, in dependence on said one or more first steady state decision parameters, control activation of the echo suppressor.

US Pat. No. 9,552,666

3-D RENDERING PIPELINE WITH EARLY REGION-BASED OBJECT CULLING

Imagination Technologies ...

1. A region-based deferred 3-D graphics renderer, comprising:
a tiling unit configured to input object data describing positions of objects that may be visible in an image to be rendered,
the image comprising a plurality of pixels, grouped into tiles, and to calculate, for each object, a respective set of tiles
overlapped by that object, and to write identifying data for the object into a display list associated with one or more tiles
of the set of tiles, located in a memory, in association with depth information for the object; and

an Image Synthesis Processor (ISP) fetch unit coupled to the memory and configured to read the identifying data and the depth
information for objects identified in the display list, to receive a depth range produced from depth information for a set
of objects presently rendered by an image synthesis processor for the one or more tiles associated with the display list,
and to determine, based on comparison of said depth range with depth information for objects identified in the display list,
whether parameter data for those objects should be fetched and provided to the image synthesis processor for rendering, wherein
the image synthesis processor is configured to update the depth range as further objects are rendered for the one or more
tiles associated with the display list and to provide the updated depth range to the ISP fetch unit.

US Pat. No. 9,652,240

STACK POINTER VALUE PREDICTION

Imagination Technologies ...

1. A method of predicting stack pointer values for a stack in a processor, the stack having an associated stack pointer, the
method comprising:
in response to detection of an instruction growing the stack, storing a data entry in a data structure different from the
stack using at least one processor, the data entry comprising a size value corresponding to an amount by which the instruction
grows the stack and at least one of:

a register ID of a physical register storing a value of the stack pointer prior to the instruction growing the stack; and
the value of the stack pointer prior to the instruction growing the stack; and
in response to subsequent detection of an instruction shrinking the stack, comparing a size value corresponding to an amount
by which the instruction shrinks the stack to the stored size value in the data structure;

in response to detecting a correspondence between the size value corresponding to an amount by which the instruction shrinks
the stack and the stored size value in the data structure,

updating the stack pointer based on at least one of the register ID and the value of the stack pointer in the data entry comprising
the stored size value used in the comparison and removing from the data structure the data entry comprising the stored size
value used in the comparison; and

in response to failing to detect a correspondence between the size value corresponding to an amount by which the instruction
shrinks the stack and the stored size value, removing the data entry from the data structure.

US Pat. No. 9,603,052

JUST IN TIME PACKET BODY PROVISION FOR WIRELESS TRANSMISSION

Imagination Technologies ...

1. A method of transmitting a payload data unit from a communication device over a wireless network, comprising:
obtaining an allocation of memory storing payload data for said payload data unit at various distributed locations in a system
memory of said communication device, at least some of said locations storing references to other system memory locations in
which other payload data for said payload data unit is stored;

in response to a request to transmit said payload data unit over said wireless network,
retrieving a header of said payload data unit and a reference to a location in the system memory from which to begin retrieving
payload data for said payload data unit;

initiating transmission of a physical layer preamble and retrieved header data for said payload data unit;
outputting one or more requests to retrieve the body of the packet, simultaneously with said initiating transmission, retrieving
payload data from the system memory, using the reference to the memory location, responsive to the determining;

receiving data, in the MAC device, responsive to the one or more requests;
identifying two or more payload data units to be aggregated into one transmission, the identifying comprising identifying
matching destination addresses of the identified two or more payload data units; and

providing the retrieved data to a physical layer for transmission.

US Pat. No. 9,860,561

DATA COMPRESSION USING SPATIAL DECORRELATION

Imagination Technologies ...

1. A method of performing spatial decorrelation on a block of data values at a processing module as part of a data compression
process, the data values in the block being arranged into a two dimensional array, wherein the processing module comprises
a plurality of parallel processing pipelines each comprising a first stage and a second stage, the method comprising, iteratively:
implementing, at the first stages of the processing pipelines, first spatial decorrelation in a first dimension on one or
more data values from a received line of data values from the block, and outputting a first coefficient from the first stage
to the second stage within each of the processing pipelines;

selectively storing the first coefficients for the received line of data values in storage units of the second stages of the
processing pipelines; and

implementing, at the second stages of the processing pipelines, second spatial decorrelation in a second dimension on one
or more first coefficients for the received line of data values, and outputting, from the second stage of each of the processing
pipelines, a second coefficient for a respective one of the data values of the received line, wherein the second coefficients
represent spatially decorrelated data values,

wherein, in each of a plurality of iterations, a respective line of data values is received at the first stages of the processing
pipelines, wherein the lines are received over the plurality of iterations in a particular order such that if the first coefficients
for a particular line will be used for the second spatial decorrelation for another line then the data values of the particular
line are received at the first stages in an earlier iteration to that in which the data values of said another line are received
at the first stages.

US Pat. No. 9,710,954

PROCESSOR WITH RAY TEST INSTRUCTIONS PERFORMED BY SPECIAL PURPOSE UNITS

Imagination Technologies ...

1. A graphics processor, comprising:
a processor programmable by instructions from an instruction set, the instruction set comprising a special purpose intersection
test instruction that provides for a reference to a geometry shape, the geometry shape either being an element of geometry
acceleration data or a primitive, and a reference to one or more rays to test for intersection with the geometry shape;

one or more test cells interfaced to receive an instance of the special purpose intersection test instruction, the instance
of the special purpose intersection test instruction specifying a geometry shape and referencing one or more rays to be tested
for intersection with that specified geometry shape, wherein the one or more test cells are configurable to perform an intersection
test between the specified geometry shape and the one or more rays;

a decode unit configured to receive the instance of the special purpose intersection test instruction, and use the special
purpose intersection test instruction to cause the one or more test cells to be configured to test the specified geometry
shape with the one or more referenced rays for intersection and output a result; and

a fetch unit coupled with the decode unit, and wherein the decode unit is configured to cause the fetch unit to retrieve definition
data for the geometry shape from a memory for use by the one or more test cells.

US Pat. No. 9,529,751

REQUESTS AND DATA HANDLING IN A BUS ARCHITECTURE

Imagination Technologies ...

1. A system on chip, comprising
a plurality of master devices;
a plurality of slave devices;
a plurality of allocators, each allocator configured to allocate requests from master devices of the plurality of master devices
to slave devices, and to generate a hold/go signal indicating that completion of a specific request should be deferred by
the slave device to which it was assigned, wherein the allocator generating the hold/go signal is operable to update status
for the hold/go signal in dependence on activities of the other allocators.

US Pat. No. 9,143,312

USING A SINGLE PHASE ERROR ALGORITHM FOR COARSE AND FINE SIGNAL TIMING SYNCHRONISATION

Imagination Technologies ...

1. A method of adjusting a receiver timing towards a signal timing of a data signal received at a receiver, said signal timing
being a characteristic of said data signal, the method comprising:
receiving the data signal using a receive mode operating in accordance with the receiver timing;
determining, according to particular phase error algorithm, a first set of phase error indications indicating phase errors
between the receiver timing and the signal timing of the received data signal, wherein the first set of phase error indications
forms an error vector;

applying a Fourier transform to the error vector;
analysing the Fourier transform of the error vector to determine a frequency component of the error vector which identifies
a frequency difference between the receiver timing and the signal timing;

adjusting the receiver timing to a first adjusted receiver timing based on the identified frequency difference;
determining an average of a second set of phase error indications indicating phase errors between the first adjusted receiver
timing and the signal timing according to said particular phase error algorithm; and

adjusting the first adjusted receiver timing to a second adjusted receiver timing based on the determined average of the second
set of phase error indications.

US Pat. No. 9,875,083

PERFORMING A COMPARISON COMPUTATION IN A COMPUTER SYSTEM

Imagination Technologies ...

1. A method of performing a comparison computation in a computer system for comparing a result of a multiplication computation
with a predetermined value, wherein the comparison computation is performed in a check procedure implemented by the computer
system for checking a proposed result of a reciprocal square root calculation, wherein the multiplication computation is implemented
by multiplier logic of the computer system and includes a multiplication of three values, each of the three values being allowed
to have a number of digits up to a maximum of k digits, wherein the multiplier logic is configured for performing multiply
operations in which two input values are multiplied together to provide an output value, wherein the size of the multiplier
logic is fixed such that (i) each of the two input values can have up to a maximum of k digits, and (ii) the output value
can have up to a maximum of 2k digits, the method comprising:
performing a reciprocal square root calculation with converging approximation logic on an input value b to generate the proposed
result


performing a first multiply operation with the multiplier logic of the computer system to determine a first intermediate result
by multiplying a first and a second of the three values;

separating digits of the first intermediate result to form: (i) a first portion comprising the most significant digits of
the first intermediate result, and (ii) a second portion comprising less significant digits of the first intermediate result,
wherein each of the first and second portions of the first intermediate result have ?k digits;

per a second multiply operation with the multiplier logic to determine a second intermediate result by multiplying a third
of the three values with said second portion of the first intermediate result;

performing a third multiply operation with the multiplier logic to determine a third result, the third multiply operation
including multiplying the third of the three values with said first portion of the first intermediate result and adding at
least one of the digits of the second intermediate result; and

performing the check procedure for checking the proposed result of the reciprocal square root calculation by using the third
result to determine a comparison of the result of the multiplication computation with the predetermined value,

wherein the three values include b and (r+c), c has a value of 0,
or u, and u is an increment in the least significant digit position of r.

US Pat. No. 9,692,882

AUTO-TUNING OF AN ACOUSTIC ECHO CANCELLER

Imagination Technologies ...

1. A gain control system for dynamically tuning an echo canceller, the echo canceller being configured to estimate an echo
of a far-end signal and subtract that estimate from a microphone signal to output an echo cancelled signal, the system comprising:
an echo measurement unit configured to calculate a ratio of a first microphone signal to a first far-end signal;
an attenuation unit configured to attenuate at least one of the first microphone signal and the first far-end signal to output
a second microphone signal and a second far-end signal to the echo canceller, the ratio of the second microphone signal to
the second far-end signal being different from the calculated ratio; and

an attenuation controller configured to control the attenuation unit, in dependence on the calculated ratio, so as to alter
the ratio of the second microphone signal to the second far-end signal and control the echo-cancelled signal.

US Pat. No. 9,672,039

REGISTER FILE HAVING A PLURALITY OF SUB-REGISTER FILES

Imagination Technologies ...

1. A register file for use in an out-of-order processor, the register file comprising:
a plurality of sub-register files, each sub-register file comprising at least one physical register; and
a plurality of buffers, each buffer being associated with a sub-register file and arranged to:
receive write operations destined for the associated sub-register file,
store the received write operations in the buffer,
receive write values for write operations stored in the buffer,
store the received write values in the buffer,
determine, each scheduling cycle, whether there is at least one stored write operation in the buffer with a stored write value,
and

in response to determining there is at least one stored write operation in the buffer with a stored write value, select one
of the write operations in the buffer with a stored write value and issue the selected write operation to the associated sub-register
file.

US Pat. No. 9,684,592

MEMORY ADDRESS GENERATION FOR DIGITAL SIGNAL PROCESSING

Imagination Technologies ...

1. A processing system, comprising:
a first memory storing a plurality of data items arranged in a first sequence, each data item having an associated memory
address on the first memory;

at least one processor coupled to the first memory and arranged to read and write data directly to the first memory; and
a direct memory access controller coupled to the first memory, and including:
a port to a second memory, and
a configurable address generator arranged to compute a sequence of read addresses according to a selected one of a plurality
of different read modes and to compute a sequence of write addresses according to a selected one of a plurality of different
write modes;

wherein the computed sequence of read addresses and the computed sequence of write addresses are combined such that the direct
memory access controller is configured to transfer the plurality of data items directly from the first memory to the second
memory using the computed sequence of read addresses and the computed sequence of write addresses, such that the data items
written to the second memory during the transfer are arranged in a second sequence that is different from the first sequence,
and

wherein a read mode is a pattern in which data items are read from memory in a single transaction and a write mode is a pattern
in which data items are written to memory in a single transaction.

US Pat. No. 9,606,834

ALLOCATING RESOURCES TO THREADS BASED ON SPECULATION METRIC

Imagination Technologies ...

1. A method of allocating resources between a plurality of threads in a processor, the method comprising:
receiving at a speculation metric calculator a confidence value for each of a plurality of instructions, each instruction
being associated with one of the plurality of threads, each confidence value representing the likelihood that the instruction
has been correctly predicted;

generating at the speculation metric calculator a speculation metric for each thread based on the confidence values, each
speculation metric representing the extent to which the instructions associated with the thread are speculative, comprising:

adding a confidence value for an instruction associated with a thread to the speculation metric for that thread once that
confidence value has been received; and

subtracting that confidence value from the speculation metric for that thread once that instruction has been executed;
providing the speculation metrics from the speculation metric calculator to a reservation station; and
allocating functional unit resources to the plurality of threads at the reservation station based on the speculation metrics.

US Pat. No. 9,607,426

ASYNCHRONOUS AND CONCURRENT RAY TRACING AND RASTERIZATION RENDERING PROCESSES

Imagination Technologies ...

1. A machine-implemented method for rasterizing a stream of geometry for a frame of pixels wherein a value of each pixel is
defined based on one or more samples for that pixel, the method comprising:
processing at least one element of geometry from the stream and determining a first visible element of geometry at a sample
for a pixel in the frame of pixels;

responsive to determining the first visible element of geometry, initiating running of a shader for said first visible element
of geometry, comprising emitting a ray to be traced within a 3-D scene in which elements of the geometry are located, the
ray associated with the sample; and

processing at least one other element of geometry from the stream and determining a second visible element of geometry at
the sample and determining whether the second visible element of geometry is the same element of geometry as the first visible
element of geometry, and if so, then continuing to process the ray, and otherwise terminating the processing of the ray.

US Pat. No. 9,525,869

ENCODING AN IMAGE

Imagination Technologies ...

1. An image processor, comprising:
an image pre-processor configured to:
receive image data which is to be processed to provide an image,
process the received image data to provide the image, said image including at least one image section having a plurality of
pixels,

analyse the pixels in the image section to estimate an indication of the complexity of the image section,
determine metadata based on the estimated indication of the complexity of the image section, and
output the determined metadata; and
an encoder configured to:
receive the metadata determined by the image pre-processor,
use the received metadata to determine a quantization level for use in encoding the image, and
encode the image using the determined quantization level.

US Pat. No. 9,513,963

TASK EXECUTION IN A SIMD PROCESSING UNIT WITH PARALLEL GROUPS OF PROCESSING LANES

Imagination Technologies ...

1. A single instruction multiple data (SIMD) processing unit configured to process a plurality of tasks, which each include
up to a predetermined maximum number of work items, wherein some of the tasks comprise fewer than the predetermined maximum
number of work items, and wherein the work items of a task are arranged for executing a common sequence of instructions on
respective data items, the SIMD processing unit comprising:
a plurality of processing lanes divided into parallel groups, each group being configured to execute instructions of work
items of a respective task over a plurality of processing cycles; and a logic module coupled to the groups of processing lanes
configured to cause a particular group of processing lanes to skip a particular processing cycle, independently of the other
groups of processing lanes, if there are no work items scheduled for execution in any of the processing lanes of the particular
group in the particular processing cycle, wherein a condition resulting in having no work items being scheduled for execution
in any of the processing lanes of the articular group in the particular processing cycle comprises a task including fewer
than said maximum number of work items.

US Pat. No. 9,473,331

EFFICIENT TRACKING OF DECISION-FEEDBACK EQUALISER COEFFICIENTS

Imagination Technologies ...

1. A method of generating updated feed-forward equaliser (FFE) coefficients for use in an equaliser in a wireless receiver,
the equaliser comprising a FFE and a decision-feedback equaliser (DFE) and the method comprising:
updating a channel impulse response estimate;
updating DFE coefficients;
calculating updated FFE coefficients based on the updated channel impulse response estimate and the updated DFE coefficients;
and

using the updated FFE coefficients in a wireless receiver equaliser.

US Pat. No. 9,455,774

LOW COMPLEXITY SOFT OUTPUT MIMO DECODER

Imagination Technologies ...

1. A method of receiving data transmitted in a MIMO system, wherein the data is transmitted from a transmitter over a MIMO
channel as a transmit vector comprising a plurality of values, the method comprising:
receiving the data as a receive vector comprising a plurality of values, the data being received over the MIMO channel at
a receiver in which the MIMO channel is represented as a MIMO channel matrix decomposed into a combination of a unitary matrix
and a triangular matrix, wherein there is a relationship linking: (i) a function of the unitary matrix and the receive vector,
and (ii) a multiplication of the triangular matrix and the transmit vector;

determining a set of candidate vectors for representing the transmit vector by: for each of a plurality of constellation points,
setting a particular value of a corresponding candidate vector to that constellation point and using the relationship and
the particular value which is set to map other values of the candidate vector to constellation points, thereby determining
the set of candidate vectors in which the particular value within the candidate vectors is set to be respective ones of the
constellation points;

determining further sets of candidate vectors by: permuting columns of the MIMO channel matrix which represents the MIMO channel,
decomposing the MIMO channel matrix into a further unitary matrix and a further triangular matrix, and repeating said determining
a set of candidate vectors, this time based on the permuted MIMO channel matrix; and

using the sets of candidate vectors determined from the MIMO channel matrix and the permuted WINO channel matrix at the receiver
to determine soft bits representing the plurality of values of said transmit vector.

US Pat. No. 9,298,467

SWITCH STATEMENT PREDICTION

Imagination Technologies ...

1. A method to predict a target location of a switch statement in a program executed by a processor, the method comprising:
storing, in a register table maintained by a branch predictor, a current value for at least one monitored register, each monitored
register having been identified as storing an input variable to a jump table switch statement, a jump table switch statement
being a switch statement that has been compiled to a jump table;

receiving at the branch predictor an instruction for prediction;
prior to the received instruction being executed, determining, using the branch predictor, whether the received instruction
writes to one of the monitored registers with an update value;

in response to determining that the received instruction writes to one of the monitored registers with an update value, updating
the current value in the register table for the monitored register the received instruction writes to with the update value;
and

predicting, using the branch predictor, the target location of a jump table switch statement instruction using the current
value.

US Pat. No. 9,658,962

CONTROL OF PRE-FETCH TRAFFIC

Imagination Technologies ...

1. A method of controlling traffic generated by a processor, the method comprising:
attaching, at the processor, a pre-fetch identifier to a pre-fetch request to flag the pre-fetch request as a pre-fetch request,
rather than a non-pre-fetch request, the pre-fetch request requesting an item from a memory hierarchy, wherein the item comprises
a piece of data or an instruction;

transmitting the pre-fetch request from the processor to the memory hierarchy; and
in response to receiving, at the processor, an abort response corresponding to the pre-fetch request, removing at least a
portion of data stored locally to the processor relating to the pre-fetch request, wherein the abort response is received
at the processor from the memory hierarchy and the abort response is generated by a node of the memory hierarchy based on
the pre-fetch identifier.

US Pat. No. 9,665,970

VARIABLE-SIZED CONCURRENT GROUPING FOR MULTIPROCESSING

Imagination Technologies ...

1. A non-transitory computer readable storage medium having stored thereon computer-executable instructions that when executed
cause at least one processor to:
prepare a code module of instructions to be ready for instantiation for execution on a target computer system comprising a
plurality of computation units collectively capable of multithreaded execution of instances of code modules, by providing
configuration information comprising an indication of code module operating group size representing an estimate of the number
of instances of the code module that can be collected together in a group, and

cause a packet unit to:
(i) form groups of computation instances to be concurrently dispatched to the target computer system for execution by the
plurality of computation units, each computation instance being an instance of a code module, and

(ii) control the dispatch of groups of computation instances using respective target dispatch quantities of grouped instances
of code modules determined according to a function using the operating group size of at least one of the respective code modules
associated with computation instances of each grouping.

US Pat. No. 9,633,468

COMPACTING RESULTS VECTORS BETWEEN STAGES OF GRAPHICS PROCESSING

Imagination Technologies ...

1. A system for processing rays in 3-D rendering, comprising:
a plurality of ray processing units, each ray processing unit comprising logic for testing a ray for intersection with one
or more shapes comprising one or more elements of an acceleration structure, or one or more elements of geometry, and a memory
configured to store definition data for rays that can be tested for intersection by that ray processing unit; and

a memory hierarchy configured to store data defining elements of the acceleration structure and elements of the geometry,
and wherein the memory hierarchy is configured to store definition data for rays scheduled for ray testing, the definition
data for rays containing both ray origin and ray direction data, wherein

each of the ray processing units is configured to receive data from an interconnect and to process the received data to identify,
within the respective memory of that ray processing unit, one or more rays to be tested for intersection with a shape, and
to output an indication of a result of the testing for intersection of that shape with the one or more identified rays.

US Pat. No. 9,613,431

LOCAL IRRADIANCE ESTIMATION FOR USE IN RENDERING AN IMAGE

Imagination Technologies ...

20. A non-transitory computer readable storage medium having encoded thereon computer readable code that causes a processor
to either:
(i) determine local irradiance estimates for a scene in an image processing system for use in rendering on a display an image
incorporating at least part of the scene from a viewpoint, by:

obtaining initial irradiance estimates for sample positions on one or more surfaces in the scene, the initial irradiance estimates
being based on a global irradiance estimate for the scene;

obtaining visibility indications which indicate the visibility of the sample positions in the scene in dependence on viewing
angle;

calculating an angle-dependent radiance estimate for the scene using the obtained initial irradiance estimates and the obtained
visibility indications; and

determining local irradiance estimates at the sample positions using the radiance estimate and the visibility indications;
wherein said image incorporating at least part of the scene is subsequently rendered from said viewpoint in dependence on
the determined local irradiance estimates; or

(ii) generate a processing block configured to determine local irradiance estimates for a scene in an image processing system
for use in rendering on a display an image incorporating at least part of the scene from a viewpoint, by:

obtaining initial irradiance estimates for sample positions on one or more surfaces in the scene, the initial irradiance estimates
being based on a global irradiance estimate for the scene;

obtaining visibility indications which indicate the visibility of the sample positions in the scene in dependence on viewing
angle;

calculating an angle-dependent radiance estimate for the scene using the obtained initial irradiance estimates and the obtained
visibility indications; and

determining local irradiance estimates at the sample positions using the radiance estimate and the visibility indications;
wherein said image incorporating at least part of the scene is subsequently rendered from said viewpoint in dependence on
the determined local irradiance estimates.

US Pat. No. 9,612,968

MIGRATION OF DATA TO REGISTER FILE CACHE

Imagination Technologies ...

1. A method of migrating data to a register file cache, the method comprising:
receiving at a migration unit a register read operation to be executed by a particular functional unit of a plurality of functional
units, the register read operation specifying a particular physical register of a plurality of physical registers to be read;

querying a register file cache associated with the particular functional unit to determine if the register file cache currently
comprises data for the particular physical register; and

in response to determining the register file cache associated with the particular functional unit does not currently comprise
data for the particular physical register, migrating data to the register file cache associated with the particular functional
unit.

US Pat. No. 9,613,598

MEMORY MANAGEMENT FOR SYSTEMS FOR GENERATING 3-DIMENSIONAL COMPUTER IMAGES

Imagination Technologies ...

1. A method for generating 3-dimensional computer images, the method comprising the steps of:
subdividing an image into a plurality of tiles;
grouping the tiles into a plurality of macrotiles, each macrotile comprising a plurality of the tiles;
defining a threshold level for a display list for the macrotiles which is less than the largest allowable display list;
loading object data for at least one of the macrotiles into the display list until the threshold level is reached;
deriving image data and shading data for each picture element of each of the tiles in at least one of the macrotiles from
the object data, wherein the object data for each of the tiles is processed in dependence on the loaded object data having
reached the threshold level of the display list;

storing the derived image data and shading data in a memory;
releasing for further use areas of the display list containing object data used to derive image data and shading data stored
in the memory;

loading additional object data for at least one of the macrotiles into released areas of the display list;
retrieving image data stored in the memory;
deriving additional image data and shading data for each picture element of the tiles from the additional object data stored
in the display list and the retrieved image data from the memory;

storing the additional derived image data and shading data in the memory; and
providing shading data stored in the memory for display.

US Pat. No. 9,607,429

RELIGHTABLE TEXTURE FOR USE IN RENDERING AN IMAGE

Imagination Technologies ...

1. A method of determining a colour component of a relightable texture and a set of surface normals for use in rendering an
image from a rendering viewpoint under arbitrary lighting conditions, wherein at least one view of a scene from a respective
at least one camera viewpoint represents the image, the method comprising:
analysing the at least one view of the scene to estimate scene geometry and to segment an initial texture into a plurality
of materials, the initial texture being separable into a colour estimate and a corresponding shading estimate;

determining an initial coarse colour estimate for each of the materials;
determining one or more scale factors, for scaling a respective one or more of the initial coarse colour estimates, the scale
factors being determined based on differences between irradiance estimates determined for the materials based on shading estimates
which correspond with scaled versions of the initial coarse colour estimates of the materials;

determining a global irradiance function for the scene using the determined scale factors;
using the global irradiance function and the initial texture to determine a further colour estimate and a corresponding further
shading estimate, wherein the further colour estimate represents the colour component of the relightable texture; and

determining the set of surface normals using the global irradiance function and the further shading estimate.

US Pat. No. 9,602,793

SKIN TONE DETECTION IN A DIGITAL CAMERA

Imagination Technologies ...

1. A method for processing sensor data in an image processor that implements at least one image enhancement process, the method
comprising:
receiving sensor data from an image sensor;
performing a skin tone detection operation to identify skin tone areas in the sensor data in pre-capture processing;
selectively modifying at least one image enhancement process for the identified skin tone areas prior to image capture;
applying the at least one modified image enhancement process to the identified skin tone areas in the sensor data to generate
modified sensor data;

feeding the modified sensor data back to the image sensor, thereby enabling the image sensor to capture an image using the
modified sensor data; wherein each step is performed in the image processor;

dividing the sensor data into blocks of pixels and calculating a percentage of the skin tone area within each block of pixels;
and

determining a weighting scheme, wherein the weighting scheme assigns weights to the at least one image enhancement process
based on the percentage of the skin tone area within each block of pixels, and wherein the at least one image enhancement
process is modified based on the weights assigned.

US Pat. No. 9,105,131

MULTI-CORE GEOMETRY PROCESSING IN A TILE BASED RENDERING SYSTEM

Imagination Technologies ...

1. A 3-D rendering apparatus with deferred rasterization, comprising:
a plurality of geometry processing units, each operable to receive elements of scene geometry, and to produce a tile reference
list for each tile processed by that geometry processing unit, each tile reference list containing a list of entries that
identify (1) a block of scene geometry processed by that geometry processing unit, the block comprising one or more triangles
(2) location(s) in memory storing parameter information for the block of scene geometry (3) an interleave marker, indicating
that processing for the block of geometry, by that geometry processing unit has completed, and (4) an end marker, indicating
that all geometry processed by that geometry processing unit, for the tile to which that tile reference list pertains, has
been listed; and

a rasterization front end, coupled to receive the tile reference lists produced in the plurality of geometry processing units,
wherein the tile reference lists comprise multiple tile reference lists for at least some of the tiles, and to process the
tile references lists by reading entries from one of the tile reference lists until reaching an interleave marker, and then
switching to a different tile reference list pertaining to the same tile, and processing entries from that tile reference
list until reaching an interleave marker or an end marker, and responsive to reaching an end marker, beginning to process
a tile reference list pertaining to another tile.

US Pat. No. 9,077,969

METHOD AND APPARATUS FOR DETERMINING MOTION BETWEEN VIDEO IMAGES

Imagination Technologies ...

1. An apparatus capable of processing an image sequence, comprising:
an input for receiving data for a reference image and another image;
a sub-sampler configured for selecting pixels of the reference image, the selecting comprising applying a plurality of sampling
rates to different regions of the reference image;

a memory coupled to the sub-sampler for storing data for the selected pixels;
an interpolator coupled to the memory for constructing a representation of a pixel of the reference image from two or more
of the selected pixels; and

an element configured for performing an image processing operation on the another image, using the constructed representation
of the pixel of the reference image.

US Pat. No. 9,660,677

IMPULSIVE NOISE REJECTION

Imagination Technologies ...

1. A method of impulsive noise rejection in an OFDM receiver, the method comprising:
measuring a noise value for a single OFDM symbol;
comparing the measured noise value for the single OFDM symbol to a threshold value;
in response to the comparison indicating that the measured noise value exceeds the threshold value, modifying a channel state
information value for the single OFDM symbol to allow for a correct recovery of information represented by the OFDM signal;
and

in response to the comparison indicating that the measured value does not exceed the threshold value, updating the threshold
value, said updating comprising updating a short-term average noise value using the measured value or calculating an expected
noise value using the measured value.

US Pat. No. 9,686,554

ENCODER ADAPTATION

Imagination Technologies ...

1. An adaptive control system for a media encoder configured to encode a media data stream in accordance with a set of one
or more encode parameters, the system comprising:
an input queue configured to receive a sequence of data portions representing the media data stream, each data portion having
an associated timestamp; and

an adaptation controller configured to generate an accumulation parameter indicative of an incidence of accumulation events
at the input queue within an accumulation interval, each accumulation event representing reception of an incoming data portion
into the input queue while a previous data portion in the sequence is in the input queue;

wherein the adaptation controller is further configured to:
on each accumulation event occurring in the input queue within the accumulation interval, calculate the time difference between
the timestamp of the incoming data portion and the timestamp of the previous data portion,

form the accumulation parameter by summing over the time differences calculated in respect of the accumulation events occurring
within the accumulation interval and expressing the sum of the time differences as a proportion of the accumulation interval,
and

control the encode parameters of the media encoder in dependence on the accumulation parameter.

US Pat. No. 9,633,405

TILE BASED COMPUTER GRAPHICS

Imagination Technologies ...

1. A method for generating and shading a computer graphics image in a tile based computer graphics system, comprising:
supplying geometry data;
deriving a plurality of primitives from the geometry data;
deriving one or more modified primitives from at least one of the plurality of primitives;
for each of a plurality of tiles, deriving an object list including data identifying the primitive from which each modified
primitive located at least partially within that tile is derived; and

shading each tile for display using its respective object list.

US Pat. No. 9,633,249

FACE DETECTION IN AN IMAGE DATA STREAM USING SKIN COLOUR PATCH CONSTRUCTS

Imagination Technologies ...

1. A data processing system configured to perform face detection on a stream of frames of image data, the data processing
system comprising:
a skin patch identifier configured to identify one or more patches of skin colour in a first frame and characterize the size
and orientation of each patch of skin colour in the first frame by fitting a respective patch construct of a predefined shape
to the patch of skin colour in the first frame;

a first search tile generator configured to generate one or more first search tiles from the one or more patch constructs;
and

a face detector configured to detect faces in the stream by performing face detection in one or more frames of the stream
within the first search tiles.

US Pat. No. 9,600,240

TRAILING OR LEADING ZERO COUNTER HAVING PARALLEL AND COMBINATIONAL LOGIC

Imagination Technologies ...

1. A zero counter comprising a plurality of hardware logic blocks each arranged to calculate one bit of an output value, the
output value corresponding to a number of trailing or leading zeros in an input string, wherein a first of the plurality of
hardware logic block is arranged to calculate a least significant bit of the output value and comprises:
a low section hardware logic block comprising inputs arranged to receive bits from a first section of the input string including
a least significant bit in the input string and one or more logic gates arranged to combine the received bits and generate
at least one output;

a high section hardware logic block comprising inputs arranged to receive bits from a second section of the input string including
a most significant bit in the input string and one or more logic gates arranged to combine the received bits and generate
at least one output, wherein the first and second sections of the input string are non-overlapping and comprise all the bits
in the input string; and

combining logic arranged to combine the outputs of the two section hardware logic blocks and generate the least significant
bit of the output value, wherein

each other hardware logic block in the plurality of hardware logic blocks is arranged to calculate a bit of index i of the
output value.

US Pat. No. 9,584,719

MULTI-LINE IMAGE PROCESSING WITH PARALLEL PROCESSING UNITS

Imagination Technologies ...

1. An image processing system implemented in a pipeline arrangement, the image processing system comprising:
a first multi-line processing block comprising a plurality of inputs configured to receive, in parallel, pixel values relating
to a respective plurality of pixel lines of an image, the first processing block comprising a plurality of processing units
configured to operate in parallel with each other,

wherein each of the processing units is configured to provide processed pixel values relating to a respective one of said
pixel lines of the image by applying multi-line processing to the pixel values received at at least some of said inputs of
the first processing block; the image processing system further comprising:

a second multi-line processing block comprising a plurality of inputs configured to receive from the first processing block,
in parallel, the processed pixel values provided by the processing units of the first processing block, the second processing
block being configured to apply multi-line processing to the processed pixel values received from the first processing block,
wherein no line store module is implemented between the first and second multi-line processing blocks in the pipeline arrangement
of the image processing system.

US Pat. No. 9,558,001

PRIORITIZING INSTRUCTIONS BASED ON TYPE

Imagination Technologies ...

1. A method of selecting instructions to issue to a functional unit in an out-of-order processor, the method comprising:
receiving a plurality of instructions at a reservation station, each instruction being one of a plurality of types of instructions
and being classified into one of a plurality of categories based on the type of instruction;

storing, at the reservation station, each instruction in one of a plurality of instruction queues, each instruction queue
being associated with one of the plurality of categories, each instruction queue being assigned a priority and a maximum number
of instructions assessed in a clock cycle; and

selecting, at the reservation station, instructions from one or more of the instruction queues to issue to the functional
unit in order of the assigned priorities so that instructions are selected based on a relative priority of the plurality of
types of instructions;

wherein the selecting for a particular instruction queue comprises sequentially assessing, in a clock cycle, each of one or
more instructions in that particular instruction queue up to the maximum number of instructions for that particular queue
to determine if that instruction is ready and has not been previously issued; and

wherein for at least one of the instruction queues, the assigned maximum number of instructions assessed in a clock cycle
is two or more.

US Pat. No. 9,525,870

ENCODING AN IMAGE

Imagination Technologies ...

1. A method of determining a quantization level for use by an encoder in encoding an image in accordance with a target number
of bits, wherein the image comprises one or more image sections which each comprise a plurality of pixels, the method comprising:
for each of the one or more image sections in the image, analysing the pixels in the image section to estimate an indication
of the complexity of the image section;

for each of a plurality of candidate quantization levels, using a relationship and the one or more estimated indications of
the complexity of the one or more image sections to estimate an indication of the number of bits that would be generated by
encoding the one or more image sections in the image with the encoder using the respective candidate quantization level, wherein
said relationship is a function of the quantization level used by the encoder, and wherein said relationship is for use in
relating:(i) an indication of the complexity of an image section, to (ii) an estimate of an indication of the number of bits
that would be generated by encoding that image section with the encoder; and

selecting one of the plurality of candidate quantization levels based on the target number of bits and based on the estimated
indications of the number of bits that would be generated by encoding the one or more image sections in the image with the
encoder using the respective candidate quantization levels, wherein said selected quantization level is for use by the encoder
in encoding the image.

US Pat. No. 9,444,975

IMAGE SENSOR GAMUT MAPPING

Imagination Technologies ...

1. A method of converting a plurality of input component values of a pixel to a corresponding plurality of output component
values of the pixel, wherein the input component values are in a first format which has a first valid component value range
which includes some negative values and wherein the output component values are in a second format which has a second valid
component value range which does not include negative values, wherein the method comprises:
receiving a plurality of input component values of a pixel of an image captured by an image sensor;
for each of the input component values of the pixel: determining whether the input component value of the pixel is negative,
and if it is determined that the input component value is negative applying an initial adjustment to the input component value
such that the adjusted input component value is not negative; and

for each of the input component values of the pixel: if an initial adjustment has been applied to one or more of the other
input component values of the pixel, adjusting the input component value of the pixel based on: (i) the one or more initial
adjustments applied to said one or more of the other input component values, and (ii) one or more parameters which set the
amounts of the respective one or more initial adjustments which are to be transferred from said one or more of the other input
component values to said input component value, to thereby compensate for the initial adjustment applied to said one or more
of the other input component values, wherein respective parameters set the amounts of initial adjustments which are to be
transferred for different transfers from one input component value to another input component value, and

using the adjusted input component values to set output component values;
whereby the output component values of the pixel are based on the adjusted input component values of the pixel.

US Pat. No. 9,805,500

HIDDEN CULLING IN TILE-BASED COMPUTER GENERATED IMAGES

Imagination Technologies ...

1. A method for culling non-visible objects in a tiling unit of a tile-based rendering system configured to use a rendering
space which is subdivided into a plurality of tiles, wherein each of the tiles comprises one or more regions for which depth
comparisons are to be performed, each of the tiles comprising a plurality of pixels, the method comprising, for each of the
tiles of the rendering space:
compiling a display list for the tile, the display list comprising object data for potentially visible objects in the tile,
the compiling of the display list for the tile comprising, for each region of the tile and before rendering of the tile begins:

deriving depth values for an object in the region;
reading a depth threshold for the region from a memory;
performing comparisons between the depth values for the object and the depth threshold for the region;
determining whether the object entirely covers the region; and
when it is determined that the object entirely covers the region and in dependence on the results of at least one of the comparisons,
updating the depth threshold for the region;

in dependence on the result of at least one of the comparisons for each of the one or more regions of the tile, determining
whether to cull the object for the tile, such that the object is not indicated in the display list for the tile; and

subsequently beginning rendering the tile using the display list for the tile.

US Pat. No. 9,749,124

SYMBOL BOUNDARY DETECTION

Imagination Technologies ...

1. A method for detecting a symbol boundary between symbol intervals in a data packet comprising a guard interval preceding
a preamble having a predetermined sequence of symbols, the method comprising:
receiving a signal representing a data packet, the signal comprising a first signal transmitted from one antenna and one or
more other signals transmitted from respective one or more other antennas, said other signals being the same as the first
signal and shifted by predetermined amount of time;

sampling the received signal at a specified sampling rate to obtain a set of samples;
estimating channel impulse responses from the set of samples in dependence on the predetermined sequence of symbols of the
preamble;

determining an energy value for each of a plurality of first windows of channel impulse responses, each of the first windows
corresponding to W number of consecutive samples, W being an integer greater than 1, the energy value for each of the first
windows being indicative of the total energy associated with the channel impulse responses of that window;

determining which of the first windows has the greatest energy value;
identifying the earliest sample nlgi of the consecutive W samples in the determined greatest energy first window;

calculating a sample range in dependence on sample nlgi a peak sample nmax and a Ws number of samples corresponding to the duration of a short guard interval;

determining an energy value for each of a plurality of second windows of channel impulse responses, each second window corresponding
to Ws number of consecutive samples, the plurality of second windows being within the sample range, the energy value for each second
window being indicative of the total energy associated with the channel impulse responses of respective Ws samples;

determining which second window has the greatest estimated energy value; and
identifying the earliest sample of the consecutive Ws samples in said determined second window, the earliest sample being indicative of a symbol boundary in said data packet.

US Pat. No. 9,734,834

COMFORT NOISE GENERATION

Imagination Technologies ...

1. A system, including a processor in communication with a memory, for generating comfort noise for a stream of frames carrying
an audio signal, the system comprising:
frame characterising logic configured to generate a set of filter parameters characterising the frequency content of a frame;
an analysis filter adapted using the filter parameters and configured to filter the frame so as to generate residual samples,
said analysis filter being an inverse LPC filter;

an analysis controller configured to receive an indication that the frame does not comprise speech and, responsive to the
indication, cause the residual samples to be stored in a store; and

a synthesis controller operable to select, from the store, stored residual samples which have been generated by the analysis
filter and cause a synthesis filter, inverse to the analysis filter and adapted using filter parameters generated at the frame
characterising logic for one or more frames not comprising speech, to filter the selected residual samples so as to generate
a frame of comfort noise, said synthesis filter being an LPC filter, and said synthesis controller being configured to select
stored residual samples at random from the store sufficient to generate the frame of comfort noise.

US Pat. No. 9,769,269

METHOD, SYSTEM AND DEVICE FOR SELECTING A DEVICE TO SATISFY A USER REQUEST

Imagination Technologies ...

1. A method to select an end-user device from a plurality of end-user devices to satisfy a user request, the method comprising:
storing at a portal aggregator data identifying a plurality of device groups, the data identifying each device group comprising
data identifying at least one user associated with the device group and data identifying a least one capability for each of
a plurality of end-user devices associated with the device group;

receiving a request at the portal aggregator from the user, the request comprising information identifying the user, information
identifying a first action, information identifying another user, and information identifying a second action;

identifying, at the portal aggregator, a first device group associated with the user based on the information identifying
the user, and a second device group associated with the other user based on the information identifying the other user;

generating, at the portal aggregator, a first list of end-user devices from the first device group having the capability to
execute the first action, and a second list of end-user devices from the second device group having the capability to execute
the second action;

selecting, at the portal aggregator, an end-user device from the first list of end-user devices to execute the first action
and an end-user device from the second list of end-user devices to execute the second action based on a location pattern associated
with the user; and

transmitting a command from the portal aggregator to the selected end-user devices to execute the actions.

US Pat. No. 9,645,945

FILL PARTITIONING OF A SHARED CACHE

Imagination Technologies ...

1. A method of managing memory in a processor, the method comprising:
allowing unrestricted access to any data stored in a shared cache in the processor;
in response to a cache miss event associated with a thread running in the processor, using a fill partitioning policy to select
a location within a defined portion of the shared cache; and storing content of a memory location associated with the cache
miss event in the selected location in the shared cache; and

dynamically switching on and off use of the fill partitioning policy to select a location based on one or more of: thread
ID and cache conditions,

wherein the size of the defined portion of the shared cache allocated to the thread is adjusted dynamically while operations
are in progress.

US Pat. No. 9,544,767

ENCRYPTION KEY UPDATES IN WIRELESS COMMUNICATION SYSTEMS

Imagination Technologies ...

1. A process of receiving encrypted communications in a network, comprising:
maintaining, at a Media Access Control (MAC) layer at a receiving device, a current cipher key for use in decrypting packets
of data received from a transmitting device in an established communication session;

receiving, from the transmitting device, a new cipher key to replace the current cipher key;
in response to determining that (1) a packet was received without detectable error but that (2) data contained in a decrypted
payload from that packet cannot be authenticated using the current cipher key, updating, at the receiving device, the current
cipher key with the new cipher key; and

after updating the current cipher key, waiting for a retransmission of the packet, decrypting and authenticating the payload
of the packet using the updated current cipher key, and only after passing authentication using the updated current cipher
key, acknowledging receipt of the packet and discarding the previous current cipher key.

US Pat. No. 9,478,062

MEMORY ALLOCATION IN DISTRIBUTED MEMORIES FOR MULTIPROCESSING

Imagination Technologies ...

1. A processor for graphics rendering, comprising:
a plurality of processing units, each processing unit capable of executing at least one program instance independently of
the other processing units of the plurality;

a plurality of local memories used by the plurality of processing units;
an allocator shared among the plurality of processing units, the allocator operable to allocate space in the local memories
for data associated with program instances and create a mapping between the program instances and the allocated space in the
local memories;

a collector comprising packet storage configured to store a plurality of packets of program instances, wherein the collector
is configured to collect program instances into packets in the packet storage by, for each of a plurality of program instances,
selecting a packet and adding the program instance to the selected packet, the selected packet being stored in the packet
storage; and

a distributor configured to distribute program instances, obtained from the packets, to be executed on the plurality of processing
units according to the mapping.

US Pat. No. 10,049,489

SYSTEMS AND METHODS FOR SOFT SHADOWING IN 3-D RENDERING

Imagination Technologies ...

1. A machine-implemented method of graphics processing, comprising:identifying visible surfaces of a scene for pixels of a frame of pixels;
determining origins for casting rays from the visible surfaces for a plurality of the pixels towards a light;
determining whether each of the rays is occluded from reaching the light;
for each of the rays that are determined to be occluded from the light, recording a distance along the ray from the surface to its respective occlusion;
for each of the rays that are determined to be not occluded from the light, searching for one or more pixels for which a ray is determined to be occluded from the light, and if at least one pixel is found in the search, determining a distance based on the distances recorded for the found pixels; and
for each of the rays for which a distance is recorded:
determining a blending region for a blending filter based on the recorded distance for the ray;
transforming that blending region into the frame of pixels;
blending shadow information for pixels in the frame of pixels that are within the transformed blending region; and
using the blended shadow information to determine shadowing for one or more pixels corresponding to the ray.

US Pat. No. 9,842,386

IMAGE FILTERING BASED ON IMAGE GRADIENTS

Imagination Technologies ...

1. An image processing method comprising:
determining image gradient indications for at least two images;
determining filter costs for image regions based on the determined image gradient indications for the at least two images;
and

applying a filtering operation to images with filter logic using the determined filter costs for the image regions, so that
the filtering is performed for image regions in dependence upon image gradients of the images.

US Pat. No. 9,736,077

ENHANCED MEDIA QUALITY MANAGEMENT

Imagination Technologies ...

14. A method of transmitting a media stream over a network, the method comprising:
estimating a measure of network quality indicative of available bandwidth over the network;
using the measure of network quality to detect a reduction in available bandwidth and, responsive to detecting said reduction,
determining a first bitrate corresponding to the reduced available bandwidth;

responsive to determining the first bitrate, determining a second bitrate lower than the first bitrate;
transmitting the media stream at a transmission bitrate equal to the second bitrate for a first period of time; and
increasing the transmission bitrate from the second bitrate to the first bitrate over a second period of time subsequent to
said first period of time.

US Pat. No. 9,684,995

SETTING A DISPLAY LIST POINTER FOR PRIMITIVES IN A TILE-BASED GRAPHICS PROCESSING SYSTEM

Imagination Technologies ...

1. A method of assigning primitives to tiles in a graphics processing system which has a rendering space subdivided into a
plurality of tiles, wherein each tile comprises one or more polygonal regions, the method comprising:
in said graphics processing system:
including, in a display list for a tile, indications of primitives which are present within a polygonal region of the tile,
to thereby assign the primitives to the tile,

receiving a set of one or more primitives,
for each of the one or more polygonal regions of a tile:
(i) determining whether the set of one or more primitives entirely covers the polygonal region of the tile, and
(ii) if it is determined that the set of one or more primitives entirely covers the polygonal region of the tile, comparing
a depth threshold for the polygonal region of the tile with a depth value for at least one of the received one or more primitives
of the set which is present within the polygonal region of the tile, to thereby determine whether the set of one or more primitives
entirely obscures previous primitives, which are included in the display list for the tile, in the polygonal region of the
tile, and

if it is determined that the set of one or more primitives entirely obscures previous primitives, which are included in the
display list for the tile, in all of the one or more polygonal regions of the tile, setting a display list start pointer to
indicate that an indication of one of the one or more primitives of the set is a starting point in the display list for the
tile.

US Pat. No. 9,648,158

ECHO PATH CHANGE DETECTOR

Imagination Technologies ...

1. An echo path monitoring system for controlling an adaptive filter configured to estimate an echo of a far-end signal comprised
in a microphone signal, the system comprising:
a comparison generator configured to compare the microphone signal with the estimated echo to obtain a first comparison result
and compare an error signal, which represents a difference between the microphone signal and the estimated echo, with the
estimated echo to obtain a second comparison result; and

a controller configured to combine the results of the first and second comparisons to form a parameter indicative of a state
of the microphone signal and, in dependence on said parameter, control an operating mode of the adaptive filter, wherein the
parameter is indicative of the presence of an echo path change in the microphone signal, and the controller is configured
to form the parameter by dividing the result of the second comparison by the sum of the results of the first and second comparisons.

US Pat. No. 9,626,465

ARBITER VERIFICATION

Imagination Technologies ...

1. A method of verifying operation of an arbiter in a hardware design, the arbiter receiving a plurality of requests over
a plurality of clock cycles, the plurality of requests comprising a watched request, the method comprising, in a processor:
identifying, for each clock cycle, any requests received by the arbiter in that clock cycle;
identifying, for each clock cycle, any requests output from the arbiter in that clock cycle;
tracking a priority of the watched request relative to other pending requests in the arbiter using a counter, the counter
updated based on the requests identified as being received by and output from the arbiter in each clock cycle and a mask identifying
a relative priority of requests received by the arbiter in a same clock cycle; and

verifying operation of the arbiter using an assertion written in an assertion-based language, the assertion establishing a
relationship between the counter and a clock cycle in which the watched request is output from the arbiter.

US Pat. No. 9,619,856

TILE-BASED GRAPHICS

Imagination Technologies ...

1. A method of processing data in a tile-based graphics system having a rendering space sub-divided into a plurality of tiles
with which graphics data items are associated, the method comprising:
fetching, from a graphics data memory into a cache, graphics data items which are to be used in processing one of the tiles;
and

reading the graphics data items from the cache for use in processing said one of the tiles, wherein the method further comprises:
determining indicators for the graphics data items, wherein, for each of the graphics data items, the indicator for that graphics
data item is indicative of the number of tiles with which that graphics data item is associated;

determining which of the graphics data items in the cache to evict based on the determined indicators, such that the graphics
data items to evict from the cache are determined in dependence on the numbers of tiles with which the graphics data items
are associated as indicated by the determined indicators; and

evicting the determined graphics data items from the cache.

US Pat. No. 9,563,727

CLOCK VERIFICATION

Imagination Technologies ...

1. A method of verifying a function of a derived clock signal in an integrated circuit hardware design, the derived clock
signal being derived in the hardware design from a reference clock signal to have a particular duty cycle and period, the
method comprising:
counting, by at least one first state machine, a number of full or half cycles of a first clock signal that occur between
a rising edge and a falling edge of a second clock signal, the second clock signal operating at a lower frequency than the
first clock signal, wherein the faster of the reference clock signal and the derived clock signal is designated as the first
clock signal, and the slower of the reference clock signal and the derived clock signal is designated as the second clock
signal;

counting, by at least one second state machine, a number of full or half cycles of the first clock signal that occur between
a falling edge and a rising edge of the second clock signal;

receiving counts from said at least one first and second state machines;
verifying the duty cycle and the period of the derived clock signal by evaluating one or more assertions written in an assertion-based
language that compare the received counts from said at least one first and second state machines to one or more predetermined
numbers; and

manufacturing an integrated circuit in accordance with the integrated circuit hardware design having the verified function.

US Pat. No. 9,554,153

DATA COMPRESSION USING SPATIAL DECORRELATION

Imagination Technologies ...

1. A spatial decorrelation module configured to perform spatial decorrelation on a block of data values as part of a data
compression system, wherein the data values in the block are arranged into a two dimensional array, and wherein the spatial
decorrelation module comprises a plurality of parallel processing pipelines each comprising a first stage and a second stage,
wherein the first stages of the processing pipelines are configured to implement first spatial decorrelation in a first dimension,
and wherein the second stages of the processing pipelines comprise respective storage units and are configured to implement
spatial decorrelation in a second dimension,
wherein the first stage of each of the processing pipelines is configured to, in each of a plurality of iterations:
(a) receive one or more of the data values from a first line of data values from the block; and
(b) implement first spatial decorrelation in the first dimension on the received data values to thereby output, to corresponding
second stages of the processing pipelines, a first coefficient for a respective one of the data values of the first line;
and

wherein the second stage of each of the processing pipelines is configured to, in each of said plurality of iterations:
(a) selectively store the first coefficients for the first line in the respective storage units; and
(b) implement second spatial decorrelation in the second dimension on first coefficients for a second line for which the first
spatial decorrelation was performed in a previous iteration, to thereby output a second coefficient for a respective one of
the data values of the second line, wherein the second coefficients are spatially decorrelated data values,

wherein the second stages of the processing pipelines are configured to selectively store the first coefficients for the first
line in the respective storage units if the first coefficients for the first line will be used for the second spatial decorrelation
for another line of the block on a subsequent iteration, and

wherein the first stages of the processing pipelines are configured to receive the lines of data values in a particular order
such that if the first coefficients for a particular line will be used for the second spatial decorrelation for another line
then the data values of the particular line are received at the first stages in an earlier iteration to that in which the
data values of said another line are received at the first stages.

US Pat. No. 9,529,747

MEMORY ADDRESS GENERATION FOR DIGITAL SIGNAL PROCESSING

Imagination Technologies ...

1. A digital signal processing system-on-chip, comprising:
a first memory storing a plurality of data items arranged in a first sequence, each data item having an associated memory
address on the first memory;

at least one digital signal processor coupled to the first memory and arranged to read and write data directly to the first
memory; and

a direct memory access controller coupled to the first memory, and including
a port to a paged memory device, and
a configurable address generator arranged to compute a sequence of read addresses according to a selected one of a plurality
of different read modes and to compute a sequence of write addresses according to a selected one of a plurality of different
write modes;

wherein the computed sequence of read addresses and the computed sequence of write addresses are combined such that the direct
memory access controller is configured to transfer the plurality of data items directly from the first memory to the paged
memory device using the computed sequence of read addresses and the computed sequence of write addresses such that the data
items written to the paged memory device during the transfer are arranged in a second sequence that is different from the
first sequence, and

wherein a read mode is a pattern in which data items are read from memory in a single transaction and a write mode is a pattern
in which data items are written to memory in a single transaction.

US Pat. No. 10,142,644

DECODING FRAMES

Imagination Technologies ...

1. A data processing system for decoding a data stream, the data processing system comprising:a first decoder configured to decode the data stream into a first sequence of media frames at a first decode rate so as to generate a first media stream for playback in real-time;
a second decoder operable to decode the data stream into a second sequence of media frames at a second decode rate so as to generate a second media stream; and
a controller configured to detect an error in decoding a particular frame of the first sequence and, responsive to that detection, cause the second decoder to decode the data stream from the particular frame in the sequence of media frames, the second decoder being arranged to decode from the particular frame in dependence on error correction data received over the data stream for the particular frame,
wherein the second decode rate is faster than the first decode rate such that the second sequence of frames of the second media stream catches up with the first sequence of frames of the first media stream,
the controller being further configured to:
determine when the second sequence of frames from the second decoder catches up with the first sequence of frames from the first decoder; and
responsive to that determination: (i) cause the second decoder to operate at the first decode rate so as to generate the second media stream for playback in real-time, and (ii) switch the stream for playback from the first decoder to the second decoder.

US Pat. No. 10,108,768

IDENTIFYING BUGS IN A COUNTER USING FORMAL

Imagination Technologies ...

1. A method of correcting a bug in a counter of a hardware design, the method comprising:(a) receiving, at one or more processors, the hardware design, a test bench counter designed to simulate the counter, and an inductive assertion establishing a relationship between the counter and the test bench counter at two or more points in time;
(b) formally verifying at the one or more processors, using a formal verification tool, the inductive assertion for the counter starting from a non-reset state of an instantiation of the counter; and
(c) in response to the formal verification tool identifying at least one valid state of the instantiation of the counter in which the inductive assertion is not true, outputting from the one or more processors information indicating a location of a bug in the hardware design or the test bench counter;
(d) using the output information to determine whether there is a bug in the hardware design;
(e) in response to determining that there is a bug in the hardware design, modifying the hardware design to correct the bug; and
(f) formally verifying, at the one or more processors, the modified hardware design for implementation in hardware.

US Pat. No. 9,830,734

SYSTEMS AND METHODS FOR DISTRIBUTED SCALABLE RAY PROCESSING

Imagination Technologies ...

1. A machine-implemented method of processing rays, comprising:
at each of a plurality of computation units,
processing rays for intersection with nodes of an acceleration structure, wherein each node of the acceleration structure
is associated with a respective node identifier, and each of the computation units comprises a respective ray definition memory
that stores definition data for rays,

outputting a node identifier and a number, said number being a number of rays that are to be tested in relation to the node
identified by the node identifier as a result of said processing rays for intersection;

at a central collector coupled with each of the plurality of computation units,
receiving the node identifier and the number of rays,
allocating one or more ray packet identifiers based on the number of rays,
returning the allocated one or more ray packet identifiers to the computation unit that outputted the node identifier and
the number of rays,

updating or creating, in a packet memory, a collection of ray packet identifiers indexed by a node identifier determined from
the received node identifier to include the allocated one or more ray packet identifiers, thereby associating the node identified
by the received node identifier with the allocated one or more ray packet identifiers,

receiving, by the respective computation unit that outputted the node identifier and the number of rays, the ray packet identifiers
allocated by the central collector, and storing, in a ray packet index memory local to that computation unit, data associating
an identifier for each ray counted in the number of rays with at least one of the ray packet identifiers.

US Pat. No. 9,818,222

TESSELLATION OF PATCHES OF SURFACES IN A TILE BASED RENDERING SYSTEM

Imagination Technologies ...

1. A method for processing tessellated patches of surfaces in a tile-based three-dimensional graphics rendering system comprising:
deriving, in a tiling unit, a per-tile list of primitive indices for tessellated primitives produced from a higher-order surface
patch;

using the per-tile list of primitive indices for each tile to identify visible tessellated primitives for that tile;
deriving domain points for the tessellated primitives that were identified as being visible;
deriving attributes for the tessellated primitives that were identified as being visible using data defining the higher order
surface patch; and

shading, by a programmable shading unit, the tessellated primitives that were identified as being visible using the derived
attributes for the visible tessellated primitives.

US Pat. No. 9,819,528

EFFICIENT DEMAPPING OF CONSTELLATIONS

Imagination Technologies ...

1. A demapper for use in a digital communications receiver, the demapper comprising:
an input arranged to receive a received symbol;
a decision making network arranged to identify a local minimum constellation point for each bit in the received symbol using
an iterative slicing process and based on calculations of signs of differences between distance metrics running parallel to
a row or column of constellation points;

a distance metric evaluator arranged to compute a minimum distance metric from the received symbol to each local minimum constellation
point; and

a soft information calculating element arranged to calculate soft information for each bit in the received symbol using the
computed minimum distance metric from the received symbol to each local minimum constellation point; and

an output arranged to output the soft information for use by a decoder within the receiver.

US Pat. No. 9,792,123

INDIRECT BRANCH PREDICTION

Imagination Technologies ...

1. A method to predict a target address of an indirect branch instruction in a program executed by a processor, the method
comprising:
storing in an indirect branch predicted target table a plurality of predicted target addresses for indirect branch instructions,
each predicted target address being indexed by a combination of an indirect path history and a taken and not-taken history,
the indirect path history comprising at least a portion of target addresses for a plurality of previous indirect branch instructions,
the taken and not-taken history comprising outcomes for a plurality of previous conditional branch instructions;

receiving at an index generator information identifying an indirect branch instruction, the information identifying the indirect
branch instruction comprising an address of the indirect branch instruction;

obtaining at the index generator a running indirect path history and a running taken and not-taken history, the running indirect
path history comprising at least a portion of predicted target addresses for a plurality of previously predicted indirect
branch instructions, the running taken and not-taken history comprising outcomes for a plurality of previously predicted conditional
branch instructions;

amending one of the running indirect path history and the running taken and not-taken history to comprise at least a portion
of the address of the indirect branch instruction;

subsequent to the amending, combining at the index generator the running indirect path history and the running taken and not-taken
history to generate an index for the identified indirect branch instruction;

identifying a predicted target address in the indirect branch predicted target table using the index for the identified indirect
branch instruction; and

if the identified predicted target address is valid, predicting the target address of the identified indirect branch instruction
to be the identified predicted target address.

US Pat. No. 9,792,720

BUILDING ACCELERATION STRUCTURES WITH SYNTHETIC ACCELERATION SHAPES FOR USE IN RAY TRACING

Imagination Technologies ...

1. A method of forming an acceleration structure for intersection testing of rays, comprising:
receiving data defining a plurality of objects located in a 3-D scene, each of the objects being composed of primitives;
analysing the primitives to determine acceleration structure elements for the objects for inclusion in a hierarchical acceleration
structure for use in intersection testing of rays in the 3-D scene, wherein an acceleration structure element for an object
is defined using data that locates one or more individual constituent 3-D volumes and specifies a respective extent of each
of the constituent 3-D volumes, wherein determining the acceleration structure element for the object comprises selecting
how many constituent 3-D volumes will be used and a location and an extent of each constituent 3-D volume based on a number
of objects which are to be bounded by that acceleration structure element; and

defining relationships between the determined acceleration structure elements in the hierarchical acceleration structure.

US Pat. No. 9,779,470

MULTI-LINE IMAGE PROCESSING WITH PARALLEL PROCESSING UNITS

Imagination Technologies ...

1. An image processing pipeline comprising:
a first multi-line processing block configured to apply multi-line processing to a plurality of pixel values; and
a second multi-line processing block configured to apply multi-line processing to the plurality of pixel values which have
been processed by the first multi-line processing block,

wherein no line store module is implemented between the first and second multi-line processing blocks in the image processing
pipeline.

US Pat. No. 9,779,490

DEFECTIVE PIXEL FIXING

Imagination Technologies ...

1. A method of applying defective pixel fixing to image data, the image data comprising pixel values for a regular array of
pixels in a plurality of colour channels, wherein the method comprises, for a target pixel in a target colour channel of said
regular array of pixels, the target pixel having a given pixel value:
for each of a plurality of directions which intercept the target pixel:
(a) determining a gradient of pixel values in one of said colour channels along said direction; and
(b) determining a candidate value for the target pixel using: (i) the determined gradient, and (ii) a pixel value of a pixel
in the target colour channel which is aligned with the target pixel along said direction;

determining the median of the plurality of candidate values determined for the respective plurality of directions, wherein
the determined median is used as a predicted value for the target pixel;

determining whether the target pixel is characteristic of a defective pixel based on the similarity of the given value of
the target pixel and the predicted value; and

selectively replacing the given value of the target pixel with the predicted value based on the determination as to whether
the target pixel is characteristic of a defective pixel.

US Pat. No. 9,774,873

FRAME PROCESSOR FOR DATA STREAM ENCODER

Imagination Technologies ...

1. A frame processor for preparing a stream of video frames for encoding, the frame processor being arranged to receive a
video frame having a first set of pixel dimensions representing the number of pixels along each dimension of the video frame,
the frame processor comprising:
a hardware processor for receiving said video frames;
a rescaling filter configured to rescale the received video frame to a second set of pixel dimensions such that at least one
of the second set of pixel dimensions are no greater than respective predetermined pixel dimension(s) in the case that said
at least one of the first set of pixel dimensions are greater than the respective predetermined pixel dimension(s) but not
in the case that the first set of pixel dimensions are each equal to or less than the respective predetermined pixel dimension(s),
said rescaled video frame being the received video frame in the case that the received video frame is not rescaled, wherein

the aspect ratio of the received video frame is maintained; and
a frame generator configured to:
embed the rescaled video frame within an output video frame having the predetermined pixel dimensions; and
mark pixels of the output video frame outside the bounds of the rescaled video frame as inactive;
the frame processor being arranged to provide the output video frame to a video encoder.

US Pat. No. 9,760,146

CONDITIONAL ACTIVATION AND DEACTIVATION OF A MICROPROCESSOR

Imagination Technologies ...

14. A method for selectively deactivating a microprocessor, said method comprising:
performing packet processing on received data at a hardware portion of an electronic device;
selectively decoding said received data;
performing data processing on decoded data, wherein said microprocessor is conditionally activated for performing said data
processing, wherein said performing packet processing comprises a medium access control (MAC) device performing real-time
voice communication functions of said electronic device without requiring said microprocessor;

filtering out non-beacon packets from received data by a beacon process module configured to deactivate after processing a
packet and to reactivate in anticipation of receipt of a packet for processing;

conditionally deactivating said microprocessor after performing said data processing if said microprocessor is not executing
an application running on said electronic device; and

at an output portion, outputting said processed data.

US Pat. No. 9,699,470

METHOD AND APPARATUS FOR COMPRESSING AND DECOMPRESSING DATA

Imagination Technologies ...

4. A method for compressing electronic image data comprising two sets of elements which are arranged in an alternating pattern,
the method comprising the steps of:
generating at least two sets of reduced size image data from the electronic image data, each element of each set of reduced
size image data being representative of a plurality of elements of the electronic image data, wherein the sets of reduced
size image data can be combined using modulation values to provide a representation of the electronic image data;

for each of the elements of a first of the two sets of elements of the electronic image data, assigning a modulation value
selected from a plurality of modulation values; and

assigning a respective flag corresponding to each of the elements of a second of the two sets of elements of the electronic
image data, wherein the flag assigned for an element of the second set indicates whether a modulation value for that element
is to be derived by interpolating modulation values assigned to adjacent horizontal elements or adjacent vertical elements.

US Pat. No. 9,697,594

NOISE ENHANCED HISTOGRAMS

Imagination Technologies ...

1. Apparatus provided at an image processing pipeline for binning an input value into one of a plurality of bins which collectively
represent a histogram of input values for use by one or more image processing algorithms in said pipeline, each of the plurality
of bins representing a corresponding range of input values, the apparatus comprising:
an input for receiving an input value;
a noise source configured to generate an error value according to a predetermined noise distribution; and
a binning controller configured to mix the received input value with the error value so as to generate a modified input value
and to allocate the modified input value to the bin corresponding to that modified input value.

US Pat. No. 9,672,584

SYSTEMS AND METHODS OF PARTIAL FRAME BUFFER UPDATING

Imagination Technologies ...

1. A method of representing graphical rendering outputs with stored data, comprising:
providing a pool of memory segments;
maintaining a free segment list of free memory segments of said pool that are available to store pixel data;
providing a plurality of render surfaces, each comprising a plurality of regions of pixel image data; and
for each render surface:
determining which of the plurality of regions have pixel image data values that are different from pixel image data values
in a respective corresponding region of a previous render surface, and which of the plurality of regions have pixel image
data values that are the same as values in a respective corresponding region of the previous render surface, wherein pixel
data for each region of the previous render surface is stored in respective memory segments of said pool;

obtaining from said list free memory segments in which to store pixel data determined to be different from pixel data of said
previous render surface, and storing said different pixel data therein;

storing for said regions of said render surface a mapping comprising references to each memory segment storing said different
pixel data, and references to each memory segment storing pixel data determined to be the same as a corresponding region of
the previous render surface;

updating a respective count for each memory segment storing pixel data for said render surface;
consuming pixel data of said render surface by
reading said mapping to identify each memory segment storing pixel data for the render surface,
reading the pixel data from those memory segments, and
updating the respective count for each memory segments;
wherein maintaining said free segment list comprises determining, based on said counts, which memory segments no longer store
pixel data for any render surface, and returning those memory segments to said free segment list.

US Pat. No. 9,612,844

SCHEDULING EXECUTION OF INSTRUCTIONS ON A PROCESSOR HAVING MULTIPLE HARDWARE THREADS WITH DIFFERENT EXECUTION RESOURCES

Imagination Technologies ...

1. A method for executing instructions on a multi-threaded processor having a plurality of hardware threads that have different
hardware execution resources, comprising:
fetching a respective next instruction for each of a plurality of streams of instructions;
pre-decoding each fetched next instruction at a respective one of a plurality of different instruction pre-decoders each associated
with a respective hardware thread;

detecting, during the pre-decoding, for each fetched next instruction, whether that fetched next instruction requires a resource
for execution that is not available in the associated hardware thread, and responsively generating a flag that such fetched
next instruction should not be run on said associated hardware thread that does not have the resource required for execution;

at an instruction scheduler configured for scheduling instructions on the plurality of hardware threads, preventing each fetched
next instruction for which a flag was generated from running on its associated hardware thread; and

for each fetched next instruction for which a flag was not generated during pre-decoding, executing that instruction in its
associated hardware thread determined to be available to execute that instruction and which has the resource required by that
instruction.

US Pat. No. 9,595,074

MULTISTAGE COLLECTOR FOR OUTPUTS IN MULTIPROCESSOR SYSTEMS

Imagination Technologies ...

1. A method of increasing processing throughput in a multiprocessor system having a plurality of computation units each processing
different computation tasks asynchronously, comprising:
asynchronously receiving outputs from a plurality of said computation units of the multiprocessor system, each of the outputs
comprising an index element and one or more constituent elements associated with that index element, wherein an index element
describes a computation task to be performed for the one or more constituent elements;

grouping at least some constituent elements of said asynchronously received outputs into packets by comparing their respective
index elements and grouping into individual packets those constituent elements associated with matching index elements, said
individual packets being associated with respective matching index elements and having a first predetermined size;

grouping at least some individual packets of constituent elements into larger individual packets until packets of a predetermined
maximum size have been assembled by comparing respective index elements of packets of similar size and grouping packets associated
with matching index elements into said larger individual packets; and

outputting individual packets of said maximum size as output packets, whereby processing throughput of output packets by said
multiprocessor system is increased.

US Pat. No. 9,575,900

DIGITAL SIGNAL PROCESSING DATA TRANSFER

Imagination Technologies ...

1. A digital signal processing system, comprising:
a memory device;
a memory access controller providing a plurality of channels for accessing the memory device;
a plurality of fixed function accelerators, each arranged to only perform a predefined specialised signal processing task
and not being capable of changing the task performed, each connected to the memory access controller and each configured to
read data from the memory device via one of the channels, perform one or more operations on the data, and write data to the
memory device via one of the channels; and

a multi-threaded processor coupled to the memory access controller and configured to execute a plurality of threads, each
thread arranged to control one of the channels, wherein at least one of the threads is configured to detect an occurrence
of an event and, responsive thereto, control provision of data from the memory device to a selected fixed function accelerator
using the thread's associated channel.

US Pat. No. 9,569,860

METHOD AND APPARATUS FOR COMPRESSING AND DECOMPRESSING DATA

Imagination Technologies ...

1. A method for compressing blocks of electronic image data, each block comprising a plurality of elements of the electronic
image data, the method comprising the steps of:
generating a modulation value for each of said plurality of elements of image data;
generating at least two sets of reduced size image data from the electronic image data, each element of each set of reduced
size image data being representative of a plurality of elements of the electronic image data, wherein the sets of reduced
size image data can be combined using the modulation values to provide a representation of the electronic image data;

for each of the blocks:
for each of a plurality of groups of modulation values generated for elements of the image data in the block, assigning a
set of bits of modulation data, wherein the set of bits of modulation data assigned to encode a group of modulation values
comprises:

(i) a plurality of modulation indicators for a respective plurality of modulation values in the group, wherein the modulation
indicator for a respective modulation value in the group indicates which of a set of one or more candidate modulation values
is to be used to represent that modulation value in the group; and

(ii) a plurality of modulation value choice bits indicating the set of one or more candidate modulation values for the group;
and

storing the sets of reduced size image data, and the sets of bits of modulation data for the groups of modulation values for
each of the blocks of elements of the electronic image data.

US Pat. No. 10,096,155

TESSELLATION METHOD USING RECURSIVE SUB-DIVISION OF TRIANGLES

Imagination Technologies ...

1. A method of performing tessellation of surface patches of objects in a 3-D scene in a computer graphics system, the method comprising:for an initial patch comprising a left vertex and a right vertex connected by an edge and defined in domain space:
comparing a vertex tessellation factor of the left vertex and a vertex tessellation factor of the right vertex to a threshold value;
in response to determining that neither of the vertex tessellation factors of the left and right vertices exceed the threshold value, outputting data describing the initial patch; and
in response to determining that either of the vertex tessellation factors of the left and right vertices exceed the threshold value, forming a new vertex sub-dividing the edge into two parts, calculating a vertex tessellation factor for the new vertex, dividing the initial patch to form a first new patch comprising the left vertex and the new vertex and a second new patch comprising the right vertex and the new vertex and reducing the vertex tessellation factor of each vertex in each of the newly formed patches; and
using the newly formed patches in rendering a scene in the computer graphics system.

US Pat. No. 9,892,547

TESSELLATING PATCHES OF SURFACE DATA IN TILE BASED COMPUTER GRAPHICS RENDERING

Imagination Technologies ...

1. A method in a tile based graphics system having a rendering space subdivided into a plurality of tiles, comprising:
reading a patch of surface data;
tessellating the patch of surface data;
determining whether at least a portion of the patch is hidden in a tile, prior to rasterization of the patch;
culling the patch from the tile if said portion of the patch is determined to be hidden in the tile; and
rendering said portion if it is determined not to be hidden in the tile.

US Pat. No. 9,747,660

PRIMITIVE PROCESSING IN A GRAPHICS PROCESSING SYSTEM WITH TAG BUFFER STORAGE OF PRIMITIVE IDENTIFIERS

Imagination Technologies ...

1. A graphics processing system comprising:
a processing module configured to receive primitives to be processed for a tile of a rendering space having one or more tiles,
wherein the processing module is configured to perform hidden surface removal for primitives of the tile to determine primitive
identifiers identifying the primitives which are visible at each of a plurality of sample positions in the tile;

a set of two or more tag buffers configured to store the primitive identifiers determined for each of the sample positions
in the tile, wherein primitive identifiers stored at corresponding sample positions in the tag buffers of the set represent
overlapping layers of primitives;

a tag control module configured to control: (i) selection of a tag buffer for the storage of each of the primitive identifiers
identifying primitives which are determined to be visible by the hidden surface removal, wherein the selection of a tag buffer
is made for a block of one or more sample positions according to the layering of the primitives identified by the primitive
identifiers stored in the tag buffers at the one or more sample positions in the block, and (ii) flushing of primitive identifiers
from one or more of the set of tag buffers; and

a texturing engine configured to receive flushed primitive identifiers and to apply texturing to the primitives identified
by the flushed primitive identifiers.

US Pat. No. 9,740,454

CROSSING PIPELINED DATA BETWEEN CIRCUITRY IN DIFFERENT CLOCK DOMAINS

Imagination Technologies ...

1. An integrated circuit, comprising:
a first circuit clocked by a first clock;
a second circuit clocked by a second clock, wherein the second clock and the first clock are configured to operate at different
frequencies;

a control queue coupled to receive an element of control information outputted from the first circuit, and to be read by the
second circuit;

a data queue coupled to receive an element of data outputted from the first circuit, wherein the element of control information
and element of data are pipelined and offset from each other by a pre-set number of clock events of the first clock; and

a counter operable to be initialized to an initial value and to be updated during subsequent clocking;
wherein the second circuit is configured to read the element of control information from the control queue responsive to the
value of the counter reaching a pre-determined value, and to read the element of data from the data queue after the pre-set
number of clock events have occurred for the second clock after the control information is read.

US Pat. No. 9,769,489

ERROR TRACKING AND MITIGATION FOR MOTION COMPENSATION-BASED VIDEO COMPRESSION

Imagination Technologies ...

1. A computer-implemented method of tracing an error in a frame of a video to a subsequent frame of the video, each frame
in the video being divided into a plurality of blocks arranged in a number of rows and columns, each frame of the video being
encoded by a technique that comprises generating motion vectors for blocks of the frame, the method comprising, by one or
more processors:
(a) receiving an error notification message, the error notification message comprising information identifying an erroneous
frame of the video and information identifying portions of the erroneous frame detected as having an error during decoding;

(b) identifying a frame following the erroneous frame as a reference frame;
(c) obtaining minimum and maximum horizontal motion vector components for each column of blocks of the reference frame;
(d) obtaining minimum and maximum vertical motion vector components for each row of blocks of the reference frame; and
(e) identifying a rectangular region of blocks of the reference frame that the error is likely to have propagated to by tracing
the identified portions of the erroneous frame to a rectangular region of blocks comprising one or more columns of the reference
frame and one or more rows of the reference frame using the minimum and maximum horizontal and vertical motion vector components
for the reference frame.

US Pat. No. 9,767,236

DEADLOCK DETECTION IN HARDWARE DESIGN USING ASSERTION BASED VERIFICATION

Imagination Technologies ...

1. A method to detect deadlock in a hardware design, comprising:
identifying, in a processor, one or more key control signals in the hardware design, each key control signal enabling or blocking
an action from happening;

generating, in a processor, a state machine for each identified key control signal to track the state of that key control
signal;

generating, in a processor, one or more assertions for each identified key control signal to detect whether that key control
signal is in a deadlock state based on data from the state machine for that key control signal, each of the one or more assertions
for each identified key control signal defined in an assertion language; and

determining, in a processor, whether the hardware design can enter a deadlock state by detecting, through formal verification
or simulation based verification of the one or more assertions for each identified key control signal in conjunction with
said state machines, whether any of the identified key control signals can enter a deadlock state further comprising, in response
to determining the hardware design can enter a deadlock state, outputting an indication of the detected deadlock state and
updating the hardware design based on the outputted indication.

US Pat. No. 9,767,798

LOW POWER DETECTION OF A VOICE CONTROL ACTIVATION PHRASE

Imagination Technologies ...

1. A microphone system comprising a microphone and hardware logic configured to compare an audio stream received via the microphone
with a pre-defined phrase and in response to partially detecting the pre-defined phrase in a first portion of the audio stream,
to:
determine if a previous portion of the audio stream comprising a partially detected pre-defined phrase was stored;
in response to determining that the previous portion of the audio stream comprising a partially detected pre-defined phrase
was not stored, to store the first portion of the audio stream;

in response to determining that the previous portion of the audio stream comprising a partially detected pre-defined phrase
was stored, to compare the first portion of the audio stream and the stored previous portion of the audio stream; and

in response to detecting a match between the first portion of the audio stream and the stored previous portion of the audio
stream, to send a trigger signal to activate a module external to the microphone system.

US Pat. No. 9,767,057

HARDWARE DATA STRUCTURE FOR TRACKING PARTIALLY ORDERED AND REORDERED TRANSACTIONS

Imagination Technologies ...

1. A hardware data structure configured to track a plurality of ordered transactions in a multi-transactional hardware design
comprising a slave and a plurality of masters, the slave configured to receive transaction requests from more than one of
the plurality of masters, the hardware data structure comprising:
one or more counters configured to track a number of in-flight transactions in the hardware design;
a table configured to track an age of each of the in-flight transactions for the plurality of masters using the one or more
counters; and

control logic configured to verify that a transaction response issued by the slave for an in-flight transaction for a particular
master has been issued in a predetermined order based on the tracked age of the in-flight transaction for that master in the
table.

US Pat. No. 9,760,997

IMAGE NOISE REDUCTION USING LUCAS KANADE INVERSE ALGORITHM

Imagination Technologies ...

1. A method of transforming a first image to bring it closer to alignment with a second image, the method comprising:
implementing a multiple kernel tracking technique to determine positions of a set of candidate regions of the first image
based on a similarity between a set of target regions of the second image and the set of candidate regions of the first image,
wherein the target regions of the second image are respectively positioned over the positions of a predetermined set of points
of the second image;

using at least some of the determined positions of the set of candidate regions to initialize a Lucas Kanade Inverse algorithm;
using the Lucas Kanade Inverse algorithm to determine a set of points of the first image which correspond to at least some
of the predetermined set of points of the second image;

determining parameters of a transformation to be applied to the first image based on an error metric which is indicative of
an error between a transformation of at least some of the determined set of points of the first image and the corresponding
points of the predetermined set of points of the second image; and

applying the transformation to the first image to bring it closer to alignment with the second image.

US Pat. No. 9,753,693

CONSTANT FRACTION INTEGER MULTIPLICATION

Imagination Technologies ...

1. In an integrated circuit for performing mathematical operations, the improvement comprising a binary logic circuit configured
to determine, for an input value x, a rounded value of
by implementing the operation
where p and q are coprime constant integers with p a and b are predetermined fixed integers, and k is the smallest integer that satisfies either:

wherein the binary logic circuit comprises:
multiplication and addition logic comprising a binary multiplier array having an input to receive x and configured to perform
the multiplication of x by the predetermined fixed integer a and being incapable of performing multiplication of x by a variable
factor, wherein the multiplication and addition logic is further configured to perform the addition of b;

wherein, in dependence on the values of p and q:
if (a) is satisfied by a smaller integer k than (b), then a is predetermined to be an integer given by

 and b is predetermined to be an integer in the range

 and
if (b) is satisfied by a smaller integer k than (a), then a is predetermined to be an integer given by

 and b is predetermined to be an integer in the range

US Pat. No. 9,703,709

METHOD AND APPARATUS FOR ENSURING DATA CACHE COHERENCY

Imagination Technologies ...

1. An incoherency detection module for maintaining data coherency in a memory resource shared by multiple threads running
on a processor, comprising:
a plurality of global write access memories each storing at least a range of memory resource addresses for a plurality of
previous write requests from a respective one of the threads running on said processor;

a comparator unit configured to compare a memory resource address of a read request from a thread running on said processor
with at least said range of memory resource addresses stored in global write access memories of others of said threads running
on said processor;

an outstanding request determination unit configured to determine, if the result of comparison by said comparator unit indicates
that the memory resource address of said read request at least falls within said range of memory resource addresses, whether
any outstanding write requests exist for said others of said threads; and

a request barrier unit configured to issue a request barrier which prevents said read request from accessing said memory resource
if said outstanding request determination unit determines that an outstanding write request exists.

US Pat. No. 9,706,057

AUTO-TUNING OF NON-LINEAR PROCESSOR THRESHOLD

Imagination Technologies ...

1. A threshold control system for controlling a non-linear processor in an echo canceller, the non-linear processor being
configured to remove from a microphone signal after the echo canceller has subtracted an echo estimate from it, any signal
energy below a threshold, the threshold control system comprising:
a convergence unit configured to determine an indication of the stability of an adaptive filter by comparing one or more coefficients
of the adaptive filter with a set of average coefficients, the adaptive filter being configured to continuously model an echo
path so as to generate the echo estimate; and

a threshold tuner configured to adjust the threshold of the non-linear processor in dependence on the indication.

US Pat. No. 9,704,283

RENDERING WITH POINT SAMPLING AND PRE-COMPUTED LIGHT TRANSPORT INFORMATION

Imagination Technologies ...

1. A method for use in rendering a computer graphics image from 3-D scene data, comprising:
tracing, by a processor, a ray in a 3-D scene defined by said 3-D scene data, in a direction and originating from a point
up to a first end of a transition zone, and continuing through the transition zone to a second end of the transition zone;

wherein the first end of the transition zone is separated from the point by a first distance, such that the ray is traced
the first distance before entering the transition zone, and the second end of the transition zone is separated from the point
by a second distance greater than the first distance;

if no intersection was detected for the ray closer than the first end of the transition zone, then
marching a conic section through a 3-D grid of volume elements in the 3-D scene, each volume element associated with data
representative of light energy propagating from that volume element, wherein an area of the conic section is determined based
on a spreading factor and a distance from the point in the 3-D scene, and

collecting light energy data from volume elements intersected by the conic section during the marching; and
producing, by a processor, shading information for the point in the 3-D scene from the collected light energy from the volume
elements, wherein said shading information is used in rendering said computer graphics image.

US Pat. No. 9,703,525

PARTIALLY AND FULLY PARALLEL NORMALISER

Imagination Technologies ...

1. An apparatus comprising hardware logic arranged to normalise an input n-bit binary number, the hardware logic comprising:
a leading zero counter arranged to compute a number of leading zeros in the n-bit number; and
left shifting logic arranged to perform left shifting of the n-bit number,
wherein at least a portion of the left shifting is performed in parallel with the computing of the number of leading zeros
and without input from the leading zero counter.

US Pat. No. 9,524,534

PROCESSING OF PRIMITIVE BLOCKS IN PARALLEL TILING ENGINE PIPES

Imagination Technologies ...

1. A method of processing in a plurality of tiling engine pipes within a graphics processing system configured to use a rendering
space which is subdivided into a plurality of tiles, a sequence of primitive blocks each including at least one primitive,
wherein the tiling engine pipes are arranged to process respective primitive blocks in parallel, and wherein a location of
each of the primitive blocks within the rendering space is indicated by a respective location indicator, and a position of
each of the primitive blocks within the sequence of primitive blocks is indicated by a respective sequence indicator, the
method comprising, for each of a plurality of the respective primitive blocks:
determining a priority for each of a plurality of regions of the respective primitive block, each of the regions comprising
one or more tiles, wherein if location indicators of primitive blocks currently being processed in the parallel tiling engine
pipes indicate that there are overlapping primitive blocks within a particular region of the respective primitive block then
the priority for the particular region is determined based on the sequence indicators of the overlapping primitive blocks
currently being processed in the parallel tiling engine pipes; and

processing primitives of the respective primitive block for tiles of the regions of the respective primitive block in a tile-order
based on the determined priorities for the regions, to thereby determine for each of the tiles of the regions of the respective
primitive block, which, if any, of the primitives of the respective primitive block are present within the tile.

US Pat. No. 9,984,445

TONE MAPPING

Imagination Technologies ...

1. A method of applying tone mapping to a block of a plurality of lines of pixel values, the method comprising, in each of a plurality of iterations:receiving a current line of pixel values of the block;
retrieving stored information relating to pixel values of at least one previous line of the block which have been processed in at least one previous iteration;
using the retrieved information to: (i) determine updated information which is updated in dependence on the pixel values of the current line, and (ii) determine one or more tone mapping relationships for use in mapping the pixel values of the current line to tone-mapped pixel values;
mapping the pixel values of the current line to tone-mapped pixel values using the determined one or more tone mapping relationships; and
storing the updated information for use in processing pixel values of a subsequent line of pixel values of the block in a subsequent iteration.

US Pat. No. 9,830,131

TRAILING OR LEADING ZERO COUNTER HAVING PARALLEL AND COMBINATIONAL LOGIC

Imagination Technologies ...

1. A zero counter comprising a plurality of hardware logic blocks each arranged to calculate one bit of an output value, the
output value corresponding to a number of trailing or leading zeros in an input string, wherein a first of the plurality of
hardware logic block is arranged to calculate a least significant bit of the output value and wherein each other hardware
logic block in the plurality of hardware logic blocks is arranged to calculate a bit of index i of the output value and comprises:
i OR reduction stages arranged in series, a first OR reduction stage arranged to receive the input string and comprising one
or more OR gates arranged to combine adjacent bits in the input string to generate an output string and any subsequent OR
reduction stages arranged to receive the output string from a preceding OR reduction stage and comprising one or more OR gates
arranged to combine adjacent bits in the received string to generate a further output string;

a low section hardware logic block comprising inputs arranged to receive bits from a first section of the string output by
a last OR reduction stage in the series, the first section including a least significant bit in the received string and one
or more logic gates arranged to combine the received bits and generate at least one output;

a high section hardware logic block comprising inputs arranged to receive bits from a second section of the string output
by a last OR reduction stage in the series, the second section including a most significant bit in the received string and
one or more logic gates arranged to combine the received bits and generate at least one output, wherein the first and second
sections of the received string are non-overlapping and comprise all the bits in the received string; and

combining logic arranged to combine the output of the two section hardware logic blocks and generate a bit of index i of the
output value.

US Pat. No. 9,830,738

PRIMITIVE PROCESSING IN A GRAPHICS PROCESSING SYSTEM

Imagination Technologies ...

1. A graphics processing system configured to use a rendering space which is sub-divided into a plurality of tiles, each of
the plurality of tiles containing a plurality of sample positions, the graphics processing system comprising:
a plurality of depth buffers, each of the depth buffers being configured to be dynamically associated with one tile at a time
of the rendering space, and configured to store a depth value for each of the plurality of sample positions within the tile;
and

a processing module configured to receive primitives and tiling data, wherein for each primitive the tiling data indicates
one or more tiles in which that primitive will be processed, and wherein the processing module is configured to perform hidden
surface removal for a primitive of a tile by comparing depth values for that primitive with depth values stored in the depth
buffer associated with the tile while another one of the depth buffers stores depth values for a different partially processed
tile of which not all of the primitives associated with the partially processed tile have finished being processed.

US Pat. No. 9,830,275

TRANSLATION LOOKASIDE BUFFER

Imagination Technologies ...

1. A physical Translation Lookaside Buffer (TLB) comprising:
a physical content addressable memory with variable page size entries, wherein the content addressable memory comprises:
a first set of logically contiguous entry locations, wherein the first set comprises a plurality of subsets and each subset
in the first set comprises logically contiguous entry locations for exclusive use of a corresponding virtual processing element
(VPE) in a plurality of available VPEs, and

a second set of logically contiguous entry locations distinct from the first set, wherein the entry locations in the second
set are shared among the available VPEs; and

a physical set associative memory with fixed page size entries, the set associative memory comprising a third set of logically
contiguous entry locations distinct from the first and second set of entry locations, wherein the third set of entry locations
is shared among the available VPEs.

US Pat. No. 9,799,137

PROCESSING PRIMITIVES WHICH HAVE UNRESOLVED FRAGMENTS IN A GRAPHICS PROCESSING SYSTEM

Imagination Technologies ...

1. A graphics processing system, comprising:
a first depth buffer configured to store depth values for resolved fragments of primitives of a 3D scene to be rendered for
a plurality of sample positions within a rendering space of the graphics processing system;

a second depth buffer configured to store depth values for unresolved fragments of primitives of said 3D scene to be rendered
for the sample positions; and

depth testing logic configured to receive primitive data relating to said primitives and to perform depth tests on fragments
of the primitives using depth values stored in at least one of the depth buffers;

wherein the graphics processing system is configured to: (i) store, in the first depth buffer, the depth value of a fragment
which passes a depth test if the fragment is a resolved fragment, and (ii) store, in the second depth buffer, the depth value
of a fragment which passes a depth test if the fragment is an unresolved fragment; and

wherein the graphics processing system is configured to render said 3D scene in accordance with values stored in said first
and second depth buffers.

US Pat. No. 9,785,406

APPROXIMATING FUNCTIONS

Imagination Technologies ...

1. A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments,
each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic
circuit comprising:
an input for receiving an input variable in the predefined range;
a plurality of logic chains each comprising:
a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h-1 binary adders,
where h is the minimum Hamming weight of:

a binary representation of the fixed gradient;
a trinary representation of the fixed gradient; and
a representation of the fixed gradient as a product of two binary numbers, two trinary numbers, or a binary and a trinary
number;

the h-1 binary adders being logically configured to perform the multiplication using the representation of the fixed gradient
having that minimum Hamming weight h; and

a binary adder adapted to add a base value to one of the input and output of the binary multiplier; and
selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the
received input variable, an approximate value of the mathematical function.

US Pat. No. 9,774,876

METHOD AND SYSTEM FOR STAGGERED PARALLELIZED VIDEO DECODING

IMAGINATION TECHNOLOGIES ...

1. A method for processing video frames, comprising:
receiving a compressed video stream;
identifying even frames and odd frames from the video stream;
storing the even and odd frames in a hardware memory;
processing a first portion of a first even frame from among the stored even frames using a first decoder; and
after the first decoder completes processing the first portion of the first even frame, beginning processing a first odd frame
from among the stored odd frames using a second decoder,

wherein the first portion of the first even frame is associated with a number of lines of a reference area determined using
the search range,

wherein a first portion of the first odd frame is associated with a number of lines of a reference area determined using the
search range, and

wherein the decoding of any video frame is ahead of a next video frame by a processing time that is determined based on at
least the number of lines of the reference area as determined using the search range.

US Pat. No. 9,740,557

PIPELINED ECC-PROTECTED MEMORY ACCESS

Imagination Technologies ...

9. An apparatus for performing Error Correction Code (ECC) memory access, in which a plurality of transactions are overlapped
in time, comprising:
a tag RAM, for an N-way set associative cache, the tag RAM comprising storage for Error Correction Code (ECC) bits calculated
from contents of the tags;

ECC logic for performing an ECC calculation using ECC bits pertaining to a set of tags, obtained from the tag RAM, in response
to indexing the tag RAM with a portion of a memory address, the ECC logic configured for producing a corrected set of tags,
in response to a detected and correctable error in the set of tags;

tag compare circuitry to operate in either a speculative compare mode or an error condition mode,
when in the speculative compare mode, to receive the set of tags from the tag RAM, to compare the set of tags with a portion
of the memory address, and output a matching tag, without using a result of the ECC calculation, and

when in the error condition mode, to receive the corrected set of tags from the ECC logic, to compare the corrected set of
tags with the portion of the memory address and output a matching tag; and

control circuitry configured to maintain the tag compare unit in an error condition mode, in response to the ECC logic detecting
a correctable error in the set of tags, through one or more additional transactions of said plurality of transactions, regardless
whether any error was detected in respective sets of tags obtained from the tag RAM for those one or more additional transactions;

wherein the one or more additional transactions are processed as though an error was detected in the respective sets of tags
obtained from the tag RAM for the one or more additional transactions regardless of whether any error was detected.

US Pat. No. 9,727,380

GLOBAL REGISTER PROTECTION IN A MULTI-THREADED PROCESSOR

Imagination Technologies ...

1. A method for managing global resources within a multi-threaded processor, the multi-threaded processor comprising a plurality
of threads and the method comprising:
receiving an instruction from a thread to write to a global resource;
checking, using hardware logic, one or more registers in the multi-threaded processor to determine whether the thread has
write access to the global resource; and

in response to determining that the thread has write access to the global resource, allowing the instruction to issue, wherein
checking one or more registers in the multi-threaded processor to determine whether the thread has write access to the global
resource comprises:

checking a global control field in a global register in the multi-threaded processor to determine whether the thread has write
access to the global resource, the global control field being associated with the global resource.

US Pat. No. 9,720,695

SYSTEM FOR PROVIDING TRACE DATA IN A DATA PROCESSOR HAVING A PIPELINED ARCHITECTURE

Imagination Technologies ...

1. A method of reporting performance information relating to the execution of a program in a data processor, comprising:
replacing within the program an existing instruction that performs a primary task, with an alternative instruction that is
capable of configuring the data processor to perform the same primary task and which alternative instruction has an additional
function of configuring the data processor to report, to a trace output, performance information relating to one or more of
(1) execution of the alternative instruction and (2) information relating to a result from executing of the alternative instruction;
and

within the data processor, decoding the alternative instruction and executing the alternative instruction, comprising performing
both the primary task and the additional function of reporting performance information.

US Pat. No. 9,710,228

UNIFIED MULTIPLY UNIT

Imagination Technologies ...

1. An arithmetic unit comprising a multi-precision Single Instruction Multiple Data (SIMD) multiply unit, the SIMD multiply
unit comprising:
a carry save adder (CSA) configured to obtain a first partial result and a second partial result based, in part, on a plurality
of partial products of a first multiplier operand and a second modified booth encoded multiplicand operand, said plurality
of partial products being generated by a booth encoder; and

an addition module coupled to the CSA, the addition module comprising:
a full adder to obtain an intermediate sum result and an intermediate carry result by adding the first partial result and
second partial result to a third operand, and

a first carry lookahead adder (CLA) to operate on integer and fixed point operands and coupled to the full adder, the first
CLA to add the intermediate sum result and the intermediate carry result, wherein the first CLA comprises, in addition to
columns for bits in the intermediate sum result and intermediate carry result, one or more additional columns, wherein each
additional column comprises bit values that:

prevent carry propagation across the additional column, or
propagate carries across the additional column,
wherein, a determination to propagate carries, or to prevent carry propagation across each of the one or more additional columns
is based, in part, on a current instruction being executed by the arithmetic unit, a number of concurrent operations specified
in the current instruction, and a precision of the current instruction.

US Pat. No. 10,096,150

ASSIGNING PRIMITIVES TO TILES IN A GRAPHICS PROCESSING SYSTEM

Imagination Technologies ...

1. A method of assigning primitives to tiles in a graphics processing system which has a rendering space subdivided into a plurality of tiles, wherein each tile comprises one or more polygonal regions for which depth comparisons are to be performed, the method comprising:in said graphics processing system:
receiving a plurality of primitives forming a mesh,
identifying external edges of the mesh,
identifying intersection points where the identified external edges of the mesh intersect with lines aligned with the edges of a polygonal region of a tile, and using the identified intersection points to determine whether the mesh entirely covers the polygonal region of the tile,
for each of a plurality of the received primitives which are present within the polygonal region of the tile:
(i) comparing a first depth value for that primitive with a depth threshold for the polygonal region, and
(ii) in dependence on the result of the comparison, selectively including an indication of the primitive in a display list for the tile to thereby assign the primitive to the tile; and
if it is determined that the mesh entirely covers the polygonal region of the tile, updating the depth threshold for the polygonal region in dependence on a comparison of the depth threshold for the polygonal region with a second depth value for at least one of said plurality of the received primitives of the mesh which is present within the polygonal region of the tile.

US Pat. No. 10,089,138

HARDWARE DATA STRUCTURE FOR TRACKING ORDERED TRANSACTIONS

Imagination Technologies ...

1. A hardware data structure to enforce ordering of transactions in a slave, the hardware data structure comprising:a counter configured to store a value that tracks a number of in-flight transactions in the slave;
a table configured to track an age of each of the in-flight transactions using the counter;
control logic configured to determine whether a transaction response issued by the slave has been issued in a predetermined order based on the tracked ages of the in-flight transactions in the table; and
a signal generation module configured, in response to the control logic determining that the transaction response has not been issued in the predetermined order, to output a signal that indicates the slave is not ready to send the transaction response.

US Pat. No. 9,985,660

MEDIA CONTROLLER

Imagination Technologies ...

1. A data processing device comprising:a jitter buffer configured to receive data packets;
a media decoder configured to decode data packets from the jitter buffer so as to form a stream of media frames, each media frame comprising a plurality of samples;
a media consumer having an input buffer for receiving the stream of media frames and being configured to play media frames from the input buffer according to a first frame rate;
a buffer interface configured to monitor the input buffer so as to detect when a number of samples at the input buffer of the media consumer falls below a predetermined level and, in response, generate a play-out request; and
a media controller configured to, in response to the play-out request:
estimate a timestamp of a next data packet to be played out from the jitter buffer based on a preceding data packet played out from the jitter buffer;
search the jitter buffer for a best match data packet having a timestamp in accordance with the estimated timestamp; and
transfer the best match data packet to the media decoder so as to cause the stream of media frames to be delivered into the input buffer at a rate commensurate with the first frame rate.

US Pat. No. 9,836,395

CACHE HASHING

Imagination Technologies ...

1. Cache logic for generating a cache address from a binary input memory address that includes a first binary string of a
first sequence of bits of a first predefined length and a second binary string of a second sequence of bits of a second predefined
length, the cache logic comprising:
a hashing engine configured to generate a third binary string from the first binary string, the third binary string having
the second predefined length, and the hashing engine being further configured to form each bit of the third binary string
by combining a respective subset of bits of the first binary string by means of a first bitwise operation, wherein the subsets
of bits of the first binary string are defined at the hashing engine such that each subset is unique and on average comprises
approximately half of the bits of the first binary string; and

a combination unit arranged to combine the third binary string with the second binary string by a reversible operation so
as to form a binary output string for use as at least part of a cache address in a cache memory.

US Pat. No. 9,831,975

SAMPLING FREQUENCY OFFSET CALCULATION

Imagination Technologies ...

1. A method of decoding a received signal in a digital receiver, the method comprising:
receiving the signal;
for each value of i from a set of predetermined candidate values for i, wherein i is an integer variable, performing a correlation
between a first group of samples in said received signal of said digital receiver and a subsequent group of samples in the
received signal and storing a correlation result, wherein a sample in the subsequent group is spaced from a corresponding
sample in the first group by a spacing of N+i samples, where N is a predefined integer;

determining a sampling frequency offset estimate based on the value of i corresponding to a largest correlation result;
using the sampling frequency offset estimate to decode the received signal; and
outputting the decoded signal.

US Pat. No. 9,824,003

DYNAMICALLY RESIZABLE CIRCULAR BUFFERS

Imagination Technologies ...

1. A circular buffer structure comprising:
a plurality of arrays, wherein each array comprises at least two storage elements configured to store data;
one or more circular buffers; and
buffer control logic configured to:
receive at least one of (a) a request to add data to a particular circular buffer and (b) a request to remove data from a
specific circular buffer;

if a request to add data to a particular circular buffer is received when the particular circular buffer is full, dynamically
allocate an array to the particular circular buffer and add the new data to the dynamically allocated array; and

if a request to remove data from a specific circular buffer is received and removal of the data from the specific circular
buffer creates an empty array, dynamically de-allocate the empty array from the specific circular buffer and disable the de-allocated
array;

wherein the buffer control logic is configured to:
only dynamically allocate an array to the particular circular buffer if a number of arrays already allocated to the particular
circular buffer is not equal to or greater than a maximum threshold,

increase the maximum threshold when the buffer control logic detects a situation in which speed is more important than power
conservation, and

decrease the maximum threshold when the buffer control logic detects a situation in which power conservation is more important
than speed.

US Pat. No. 9,794,058

METHOD AND APPARATUS FOR TIME SYNCHRONISATION IN WIRELESS NETWORKS

Imagination Technologies ...

1. A wireless network, comprising:
an access point comprising a first physical layer counter, wherein the access point is arranged to encode and transmit a timing
synchronization frame over the wireless network, the timing synchronization frame comprising a timestamp derived from the
first physical layer counter; and

a wireless station comprising a second physical layer counter, a higher layer counter, and a clock interface coupled to the
second physical layer counter and the higher layer counter,

wherein the wireless station is arranged to receive the timing synchronization frame and decode the timestamp, control the
second physical layer counter in dependence on the timestamp, and the clock interface is arranged to control the higher layer
counter in dependence on the second physical layer counter.