US Pat. No. 9,287,985

RECOVERING ENERGY FROM AN IRDA/REMOTE CONTROL TRANSMITTER CIRCUIT

IXYS Intl Limited, Cayma...

1. A circuit comprising:
a light emitting diode (LED);
a switch;
an inductor that absorbs energy when an LED drive current is flowing from said inductor through said LED and then through
said switch;

a power supply; and
an energy-transferring circuit that transfers at least a portion of said energy from said inductor and to said power supply.

US Pat. No. 9,288,874

TURNING OFF MULTIPLE FLUORESCENT LAMPS SIMULTANEOUSLY USING RF-ENABLED LAMP STARTER UNITS

IXYS Intl Limited, (KY)

1. A method comprising:
(a) initiating turn off of a first fluorescent lamp of a multi-lamp fluorescent light fixture using a first wireless fluorescent
lamp starter unit; and

(b) initiating turn off of a second fluorescent lamp of the multi-lamp fluorescent light fixture using a second wireless fluorescent
lamp starter unit, wherein the initiating of (a) and the initiating of (b) occur at substantially the same time.

US Pat. No. 9,177,943

POWER DEVICE CASSETTE WITH AUXILIARY EMITTER CONTACT

IXYS Corporation, Milpit...

1. A power semiconductor device module comprising:
a top plate member;
a bottom plate member having a plurality of pedestals;
a plurality of semiconductor device dice, where each of the semiconductor device dice is positioned above a corresponding
one of the plurality of pedestals between the bottom plate member and the top plate member, wherein each of the semiconductor
device dice has: 1) a first power pad disposed on a frontside of the semiconductor device die, 2) a control pad disposed on
the frontside of the semiconductor device die, and 3) a second power pad disposed on a backside of the semiconductor device
die;

a collar having a circular outer periphery;
a first terminal disposed outside the circular outer periphery of the collar, wherein the first terminal is coupled to the
control pad of each of the semiconductor device dice; and

a second terminal disposed outside the circular outer periphery of the collar, wherein the second terminal is coupled to the
first power pad of each of the semiconductor device dice without being electrically connected through either the top plate
member or the bottom plate member.

US Pat. No. 9,155,167

REGISTERING A REPLACEABLE RF-ENABLED FLUORESCENT LAMP STARTER UNIT TO A MASTER UNIT

IXYS Intl Limited, (KY)

1. A method comprising: (a) registering a wireless fluorescent lamp starter unit to a master unit, wherein the registering
involves storing registration information in the starter unit so that the registration information is then usable to distinguish
wireless communications received from the master unit from other wireless communications received onto the master unit.

US Pat. No. 9,082,845

SUPER JUNCTION FIELD EFFECT TRANSISTOR

IXYS Corporation, Milpit...

1. A Super Junction Field Effect Transistor (FET) device, comprising:
a substrate;
a charge compensation region disposed above the substrate and comprising a plurality of columns of P? type semiconductor material
within a region of N? type semiconductor material;

a thin oxide layer disposed on an upper semiconductor surface;
a plurality of edge termination floating rings, wherein each edge termination floating ring extends from the upper semiconductor
surface toward the substrate;

a polysilicon gate structure disposed on an upper surface of the thin oxide layer;
an InterLayer Dielectric (ILD) layer disposed on an upper surface of the thin oxide layer and covering the polysilicon gate
structure;

a gate bus line metal structure disposed on an upper surface of the ILD;
a field plate metal structure disposed at least in part on the upper surface of the ILD layer, wherein a portion of the upper
surface of the ILD extends from the gate bus line metal structure to the field plate metal structure thereby extending over
at least one of the edge termination floating rings, and wherein the entire portion of the upper surface of the ILD layer
is substantially planar; and

a passivation layer that covers the gate bus line metal structure and covers the field plate metal structure of metal and
that covers the portion of the upper surface of the ILD.

US Pat. No. 9,433,067

DIMMING A MULTI-LAMP FLUORESCENT LIGHT FIXTURE BY TURNING OFF AN INDIVIDUAL LAMP USING A WIRELESS FLUORESCENT LAMP STARTER

IXYS Intl Limited, (KY)

1. A method of dimming a multi-lamp fluorescent light fixture comprising:
(a) turning off a first fluorescent lamp using a first wireless fluorescent lamp starter unit, wherein the first fluorescent
lamp is taken from a plurality of illuminated fluorescent lamps of the multi-lamp fluorescent light fixture.

US Pat. No. 9,443,792

BRIDGING DMB STRUCTURE FOR WIRE BONDING IN A POWER SEMICONDUCTOR DEVICE MODULE

IXYS Corporation, Milpit...

1. A power semiconductor device module comprising:
a metal baseplate;
a housing, wherein the housing engages the metal baseplate such that the metal baseplate and the housing together form a tray;
a first direct bonded metal (DMB) structure that is disposed on the metal baseplate in the tray, wherein the first DMB comprises
a ceramic layer, a first direct bonded metal layer disposed on a bottom side of the ceramic layer in thermal contact with
the metal baseplate, a first island of a second direct bonded metal layer disposed on a top side of the ceramic layer, and
a second island of the second direct bonded metal layer disposed on the top side of the ceramic layer;

a discrete semiconductor device that is surface mounted on the first island of the second direct bonded metal layer of the
first DMB structure, wherein the discrete semiconductor device has a bonding pad;

a second DMB structure that is surface mounted on the second island of the second direct bonded metal layer of the first DMB
structure, wherein the second DMB structure comprises a ceramic layer, a first island of a third direct bonded metal layer
disposed on a bottom side of the ceramic layer of the second DMB structure, and a first island of a fourth direct bonded metal
layer disposed on a top side of the ceramic layer of the second DMB structure, wherein the first island of the third direct
bonded metal layer of the second DMB structure is disposed on the second island of the second direct bonded metal layer of
the first DMB structure, and wherein no semiconductor device is mounted on the second DMB structure;

a first external connection terminal electrically coupled to a first wiring pad;
a second external connection terminal electrically coupled to a second wiring pad;
a first bonding wire that extends from the first wiring pad and to a first bonding location on the first island of the fourth
bonded metal layer of the second DMB structure;

a second bonding wire that extends from a second bonding location on the first island of the fourth bonded metal layer of
the second DMB structure and to the bonding pad of the discrete semiconductor device; and

a third bonding wire that extends from the second wiring pad and extends over the first island of the fourth direct bonded
metal layer of second DMB structure without contacting any portion of the first island of the fourth direct bonded metal layer
of the second DMB structure, wherein the third bonding wire extends over a portion of the first island of the fourth direct
bonded metal layer that is disposed between the first bonding location and the second bonding location, and wherein none of
the first, second and third bonding wires crosses over any other one of the first, second and third bonding wires.

US Pat. No. 9,324,072

BIT-FLIPPING MEMORY CONTROLLER TO PREVENT SRAM DATA REMANENCE

IXYS Intl Limited, (KY)

1. An integrated circuit comprising:
a memory having a plurality of memory blocks, wherein each memory block has a set of bits, and wherein each bit has a value;
a secure memory controller that inverts and reverts the value of each bit of each memory block of the memory such that the
amount of time each bit of the memory contains a digital logic one value is substantially equal to the amount of time the
bit contains a digital logic zero value, wherein the secure memory controller uses an inversion flag bit to track whether
a memory block contains bits with inverted values, and wherein the inversion flag bit is a bit of the memory block; and

a tamper detect circuit that causes the memory to be erased if a tamper detect condition is detected.

US Pat. No. 9,099,316

SINTERED BACKSIDE SHIM IN A PRESS PACK CASSETTE

IXYS Corporation, Milpit...

1. A power semiconductor device module, comprising:
a bottom plate member having a plurality of pedestals;
a frame disposed around one of the pedestals;
one or more first metal shims, wherein said one or more first metal shims are stacked onto said one pedestal;
a sintered assembly, wherein the sintered assembly comprises a semiconductor device die that is bonded by a layer of electrically
conductive sintered metal to a second metal shim; and

a top plate member, wherein said one or more first metal shims and the sintered assembly are compressed between the top plate
member and the pedestal of the bottom plate member.

US Pat. No. 9,276,628

PHOTOVOLTAIC CELL AND E-INK DISPLAY ON THE FRONT SIDE OF A CELL PHONE CASE

IXYS Corporation, Milpit...

1. A folding cellular telephone case adapted to fold over and to couple to a connector of a cellular telephone, the folding
cellular telephone case comprising:
a back side panel having an inside surface, a cellular telephone dock connector plug, and a socket, wherein the socket is
disposed adjacent an outside surface of the back side panel, wherein the inside surface has a substantially rectangular and
substantially planar shape that is substantially conformal to a back surface of the cellular telephone, wherein the plug extends
in a direction parallel to the inside surface and extends over a portion of the inside surface such that the plug can engage
a socket of the cellular telephone when the cellular telephone is disposed on the inside surface of the back side panel, wherein
the socket and plug of the back side panel are electrically coupled such that the cellular telephone can be powered by a supply
current that flows in a current path from a source outside the folding telephone case through the socket through the plug
and to the cellular telephone, wherein the back side panel has a peripheral edge that has a substantially rectangular shape;

a front side panel that has a peripheral edge, wherein the peripheral edge of the front side panel has a substantially rectangular
shape that substantially matches the substantially rectangular shape of the peripheral edge of the back side panel, wherein
the front side panel is hinged with respect to the back side panel such that the front side panel can fold over and cover
a front surface of the cellular telephone when the back surface of the cellular telephone is disposed on the inside surface
of the back side panel, wherein the front side panel has an inside surface that covers and faces the front surface of the
cellular telephone when the front side panel is folded over to cover the front surface of the cellular telephone, and wherein
the front side panel has an outside face surface that is opposite to the inside surface of the front side panel, wherein the
front side panel comprises:

a plurality of buttons disposed on the outside face surface;
a rechargeable battery;
an E-ink display disposed on the outside face surface, wherein the E-link display is coupled to and is powered by the rechargeable
battery;

a plurality of photovoltaic devices adapted to charge the rechargeable battery, wherein the photovoltaic devices and the E-ink
display occupy different non-overlapping portions of the outside face surface of the front side panel, wherein the photovoltaic
devices are not coupled to charge any battery of the cellular telephone through the plug of the back side panel; and

electronic circuitry coupled to the plurality of buttons, to the E-ink display, to the rechargeable battery, and to the plug
of the back side panel, wherein the case includes no wireless transceiver, wherein during a first time period the electronic
circuitry receives image information from the cellular telephone via the plug and causes the image information to be displayed
on the E-ink display, wherein during a second time period the electronic circuitry continues to drive the E-ink display such
that the image information remains being displayed on the E-ink display upon and after the cellular telephone becoming decoupled
from the plug, wherein the first and second time periods are contiguous time periods, and wherein the plurality of buttons
are usable during the second period of time to control how the image information is displayed on the E-ink display during
the second time period; and

a hinge portion coupled to the back side panel and to the front side panel, wherein electrical conductors extend from the
plug of the back side panel, through the hinge portion, and to the electronic circuitry of the front side panel, wherein no
charging current flows through the hinge portion to charge any battery of the cellular telephone.

US Pat. No. 9,219,416

BUCK CONVERTER HAVING SELF-DRIVEN BJT SYNCHRONOUS RECTIFIER

IXYS Corporation, Milpit...

1. A switching converter circuit, comprising:
a field effect transistor having a gate, a drain, a primary source, and an auxiliary source;
a first inductor having a first end and a second end, wherein the first end of the first inductor is connected to the primary
source of the field effect transistor;

a second inductor having a first end and a second end, wherein the first end of the second inductor is connected to the auxiliary
source of the field effect transistor, and wherein the second end of the second inductor is connected to the second end of
the first inductor;

a bipolar transistor having a base, an emitter, and a collector, wherein the collector is connected to the first end of the
first inductor, and wherein the base is connected to the first end of the second inductor;

a diode having an anode and a cathode, wherein the anode is connected to the emitter of the bipolar transistor, and wherein
the cathode is connected to the collector of the bipolar transistor; and

an output capacitor having a first plate and a second plate, wherein the first plate is connected to the second end of the
first inductor, and wherein the second plate is connected to the emitter of the bipolar transistor.

US Pat. No. 9,436,466

BLANK BIT AND PROCESSOR INSTRUCTIONS EMPLOYING THE BLANK BIT

IXYS Intl Limited, (KY)

1. A non-transitory computer-readable medium encoded with a processor-executable machine code instruction for:
performing an operation if a bit is storing a first value, otherwise not performing the operation if the bit is storing a
second value, wherein the bit is a bit in a flag register of a processor that executes the machine code instruction, the first
value having been stored in the bit during execution of another machine code instruction by the processor and before an operation
of the other machine code instruction was performed, wherein the other machine code instruction used a first operand, and
wherein the first value was stored in the bit if the first operand used by the other machine code instruction was equal to
zero.

US Pat. No. 9,225,260

HIGH-EFFICIENCY, LOW-POWER POWER SUPPLY CIRCUIT

IXYS Corporation, Milpit...

1. A circuit for charging a capacitor, wherein the capacitor has a first lead coupled to an output voltage VO node, and wherein the capacitor has a second lead coupled to a GND node, the circuit comprising:
a full wave bridge rectifier that supplies a rectified voltage signal (VR) onto a VR node, and that supplies a ground potential GND onto the GND node; and

a charging circuit that: 1) decouples the VO node from the VR node when VR is greater than a first predetermined voltage VP and, 2) supplies a charging current (ICHARGE) from the VR node and onto the VO node when VR is less than VP provided that VO is less than a second predetermined voltage VO(MAX) and provided that VR is greater than VO, wherein the second predetermined voltage VO(MAX) is determined by a Zener voltage of a Zener diode and a source-to-gate voltage of a depletion mode field effect transistor
(dep-FET).

US Pat. No. 9,082,879

SILVER-TO-SILVER BONDED IC PACKAGE HAVING TWO CERAMIC SUBSTRATES EXPOSED ON THE OUTSIDE OF THE PACKAGE

IXYS Corporation, Milpit...

1. A method, comprising:
(a) attaching a sintered silver pad of a first Direct Metal Bonded (DMB) ceramic substrate assembly to a layer of silver that
covers a backside of a semiconductor die such that a silver-to-silver bond is formed between the first DMB ceramic substrate
and the die, wherein the die comprises the layer of silver on the backside of the die, and wherein the die further comprises
a plurality of sintered silver pads on a frontside of the die; and

(b) attaching a plurality of sintered silver pads of a second DMB ceramic substrate assembly to the plurality of sintered
silver pads on the frontside of the semiconductor die such that a plurality of silver-to-silver bonds is formed between the
second DMB ceramic substrate assembly and the die.

US Pat. No. 9,793,352

IGBT ASSEMBLY HAVING SATURABLE INDUCTOR FOR SOFT LANDING A DIODE RECOVERY CURRENT

IXYS Corporation, Milpit...

1. An electronic device comprising:
a Punch Through Insulated Gate Bipolar Transistor (PT IGBT) having a gate, a collector, and an emitter;
a fast recovery diode; and
a saturable inductor, wherein the saturable inductor and the fast recovery diode are coupled together in series between the
emitter and the collector, wherein the saturable inductor has an unsaturated inductance of at least 200 nH, wherein the saturable
inductor has a saturated inductance that is less than the unsaturated inductance, and wherein there is no diode whose anode
is directly connected to the emitter and whose cathode is directly connected to the collector.

US Pat. No. 9,379,203

ULTRA-FAST BREAKOVER DIODE

IXYS Corporation, Milpit...

9. A method comprising:
(a) forming an N type buffer layer of epitaxial semiconductor material on a P type layer of substrate semiconductor material,
wherein a bottom surface of the P type layer is a bottom semiconductor surface, wherein the N type buffer layer has an N type
dopant concentration of at least 1×1015 atoms/cm3 and of no more than 1×1016 atoms/cm3;

(b) forming an N? type base layer of epitaxial semiconductor material such that the N? type base layer is disposed on the
N type buffer layer, wherein the N? type base layer is less than 130 microns thick;

(c) forming a P type base region into the N? type base layer, wherein the P type base region extends down into the N? type
base layer from an upper semiconductor surface;

(d) forming an N+ type annular emitter region that extends down into the P type base region, wherein the N+ type annular emitter
region surrounds a cathode short region that extends up to the upper semiconductor surface, wherein the cathode short region
has a width at the upper semiconductor surface of less than 0.250 millimeters;

(e) forming a cathode metal electrode on the upper semiconductor surface so that the cathode metal electrode contacts the
N+ type annular emitter region and the cathode short region; and

(f) forming an anode metal electrode on the bottom semiconductor surface, wherein (a) through (f) are steps in the manufacture
of a breakover diode

(g) forming a floating metal ring on the upper semiconductor surface, wherein the floating metal ring surrounds the cathode
metal electrode at the upper semiconductor surface.

US Pat. No. 9,337,744

EFFICIENT INRUSH CURRENT CONTROL IN POWER FACTOR CORRECTED AC-TO-DC CONVERTER

IXYS Corporation, Milpit...

11. An AC-to-DC converter circuit comprising:
a full bridge rectifier having a first AC input terminal, a second AC input terminal, a first output terminal, and a second
output terminal;

an inductor;
a storage capacitor;
a switch; and
a microcontroller that controls the switch in a capacitor pre-charge mode of operation of the AC-to-DC converter circuit,
wherein the microcontroller identifies a sequence of switch turn on time values and uses the turn on time values to turn on
and off the switch such that a sequence of pulses of charging current flows in a current path through the storage capacitor
and charges the storage capacitor in multiple charging steps, wherein there is at most one pulse of charging current that
flows for each time that the switch is turned on in the pre-charge operation, wherein the current path extends from the first
output terminal of the full bridge rectifier, then through the inductor, then through the storage capacitor, then through
the switch, and to the second output terminal of the full bridge rectifier, wherein each pulse of charging current of the
sequence of pulses has the same approximate peak current magnitude, wherein the microcontroller is coupled to measure a voltage
on the storage capacitor and measures the voltage in a Power Factor Correction (PFC) mode of operation of the AC-to-DC converter
circuit but wherein the microcontroller does not measure the voltage on the storage capacitor and use information from that
measurement in the pre-charge mode of operation to determine when to turn the switch on at any time between the time of the
first pulse of charging current of the sequence and the time of the last pulse of charging current of the sequence.

US Pat. No. 9,355,580

VIDEO AND CONTENT CONTROLLED BACKLIGHT

IXYS Corporation, Milpit...

1. A display comprising:
a liquid crystal (LC) panel; and
a light emitting diode backlight (LEDBK) panel provided below the LC panel having a plurality of regions each of the same
size, wherein each of the regions has a cluster of light emitting diodes (LEDs) chosen from a plurality of colors of LEDs,
wherein for each of the plurality of regions the cluster of LEDs in that region depends on where that region is located on
the LEDBK panel such that at least some regions of the plurality of regions have different colors of LEDs than other regions
of the plurality of regions, and wherein the color of light emitted from each region of the plurality of regions is controlled
by controlling the current flowing through each LED in the region.

US Pat. No. 9,544,961

MULTI-STAGE LED DRIVER WITH CURRENT PROPORTIONAL TO RECTIFIED INPUT VOLTAGE AND LOW DISTORTION

IXYS Corporation, Milpit...

1. An apparatus comprising:
a plurality of LED groups connected in series to form an LED string that has an first node, a last node, and one or more intermediate
nodes;

a plurality of current cells having inputs coupled to the first, last and intermediate nodes, respectively, and outputs coupled
to an output resistor, and wherein each current cell selectively regulates current flowing between its respective input and
the output resistor based on its respective feedback voltage; and

a feedback circuit that generates a plurality of feedback voltages from a voltage level at the output resistor, and wherein
when a selected current cell is enabled by a selected feedback voltage to regulate a selected current level from its respective
input to the output resistor, upstream current cells are disabled by their respective feedback voltages.

US Pat. No. 9,106,139

LOW FORWARD VOLTAGE RECTIFIER

IXYS Corporation, Milpit...

1. An electronic device comprising:
a current transformer having a first winding and a second winding, the first winding having a first end and a second end,
the second winding having a first end and a second end;

a bipolar transistor having a first terminal, a second terminal, and a third terminal, wherein the first terminal is a collector
terminal, wherein the second terminal is a base terminal, wherein the third terminal is an emitter terminal, wherein the second
end of the first winding of the current transformer is coupled to the second terminal of the bipolar transistor, and wherein
the second end of the second winding of the current transformer is coupled to the first terminal of the bipolar transistor;

a diode having an anode and a cathode, wherein the anode is coupled to the first terminal of the bipolar transistor, and wherein
the cathode is coupled to the third terminal of the bipolar transistor; and

a package having a first package terminal and a second package terminal, wherein the first package terminal is coupled to
the first end of the first winding of the current transformer, wherein the first package terminal is coupled to the first
end of the second winding of the current transformer, wherein the second package terminal is coupled to the third terminal
of the bipolar transistor, and wherein the package encapsulates the current transformer, the bipolar transistor, and the diode.

US Pat. No. 9,263,959

FORWARD CONVERTER WITH SELF-DRIVEN BJT SYNCHRONOUS RECTIFIER

IXYS Corporation, Milpit...

1. A switching converter circuit, comprising:
a transformer having a primary winding and a secondary winding, wherein the secondary winding has a first end and a second
end;

an output capacitor having a first terminal and a second terminal, wherein the first terminal of the output capacitor is coupled
to the first end of the secondary winding;

a first bipolar transistor having an emitter, a collector, and a base, wherein the emitter is coupled to the first end of
the second winding;

a second bipolar transistor having an emitter, a collector, and a base, wherein the collector of the second bipolar transistor
is coupled to the collector of the first bipolar transistor, wherein the base of the second bipolar transistor is coupled
to the base of the first bipolar transistor, and wherein the emitter of the second bipolar transistor is coupled to the second
end of the secondary winding;

a first diode having an anode and cathode, wherein the anode of the first diode is coupled to the collector of the first bipolar
transistor, and wherein the cathode of the first diode is coupled to the emitter of the first bipolar transistor;

a second diode having an anode and cathode, wherein the anode of the second diode is coupled to the collector of the second
bipolar transistor, and wherein the cathode of the second diode is coupled to the emitter of the second bipolar transistor;

a first inductor coupled between the second terminal of the output capacitor and the collectors of the first and second bipolar
transistors; and

a second inductor coupled between the second terminal of the output capacitor and the bases of the first and second bipolar
transistors.

US Pat. No. 9,337,171

FULL BRIDGE RECTIFIER MODULE

IXYS Corporation, Milpit...

1. A packaged semiconductor device, comprising:
a first package terminal;
a second package terminal;
a third package terminal;
a fourth package terminal;
a fifth package terminal;
a sixth package terminal;
a first bipolar transistor BJT1 having an emitter coupled to the first package terminal, having a collector coupled to the third package terminal, and having
a base directly coupled to the fifth package terminal;

a second bipolar transistor BJT2 having an emitter coupled to the second package terminal, having a collector coupled to the third package terminal, and having
a base directly coupled to the fifth package terminal;

a third bipolar transistor BJT3 having an emitter coupled to the first package terminal, having a collector coupled to the fourth package terminal, and having
a base directly coupled to the sixth package terminal;

a fourth bipolar transistor BJT4 having an emitter coupled to the second package terminal, having a collector coupled to the fourth package terminal, and
having a base directly coupled to the sixth package terminal;

a first diode D1 having an anode coupled to the emitter of BJT1 and having a cathode coupled to the collector of BJT1;

a second diode D2 having an anode coupled to the emitter of BJT2 and having a cathode coupled to the collector of BJT2;

a third diode D3 having an anode coupled to the collector of BJT3 and having a cathode coupled to the emitter of BJT3; and

a fourth diode D4 having an anode coupled to the collector of BJT4 and having a cathode coupled to the emitter of BJT4.

US Pat. No. 9,350,254

LOW FORWARD VOLTAGE RECTIFIER

IXYS Corporation, Milpit...

1. A method comprising:
assembling a current transformer, a bipolar transistor and a diode such that a first end of a first winding of the current
transformer is coupled to a first package terminal of a package, such that a first end of a second winding of the current
transformer is coupled to the first package terminal of the package, such that a second end of the first winding of the current
transformer is coupled to a base of the bipolar transistor, such that a second end of the second winding of the current transformer
is coupled to a collector of the bipolar transistor, such that an emitter of the bipolar transistor is coupled to a second
package terminal of the package, such that an anode of the diode is coupled to the collector of the bipolar transistor, such
that a cathode of the diode is coupled to the emitter of the bipolar transistor, and such that the package includes an amount
of molded plastic encapsulant that encapsulates the current transformer, the bipolar transistor and the diode.

US Pat. No. 9,473,074

CHOPPER STABILIZED AMPLIFIER WITH SYNCHRONOUS SWITCHED CAPACITOR NOISE FILTERING

IXYS Corporation, Milpit...

1. An apparatus comprising:
a chopper amplifier having an input that receives an input signal and an output that outputs an amplified signal, the chopper
amplifier includes an input chopping circuit coupled to the input and an output chopping circuit coupled to the output, the
input and output chopping circuits operate in response to a chop clock;

a switched capacitor filter having an input that receives the amplified signal and an output that outputs a filtered signal,
the switched capacitor filter operates in response to at least one filter clock; and

a filter timing adjuster having an input to receive a reference voltage and the chop clock, and an output to output the at
least one filter clock, the filter timing adjuster adjusts a phase of the at least one filter clock with respect to the chop
clock to reduce chopper noise on the reference voltage.

US Pat. No. 9,111,782

SOLDERLESS DIE ATTACH TO A DIRECT BONDED ALUMINUM SUBSTRATE

IXYS Corporation, Milpit...

1. An assembly, comprising:
a Direct-Bonded Aluminum (DBA) substrate, wherein the DBA substrate comprises a ceramic portion, an aluminum layer disposed
on the ceramic portion, and a sintered silver layer disposed over the aluminum portion; and

a semiconductor die having a back side surface and a front side surface, wherein the back side surface is a silver surface,
and wherein the silver surface of the back side surface of the semiconductor die is silver-to-silver bonded directly to the
sintered silver layer of the DBA substrate without any intervening solder, lead, tin, antimony or other metal between the
silver surface and the sintered silver layer.

US Pat. No. 9,054,587

NON-ISOLATED AC-TO-DC CONVERTER HAVING A LOW CHARGING CURRENT INITIAL POWER UP MODE

IXYS Corporation, Milpit...

1. A method comprising:
(a) receiving an AC voltage supply signal from an AC voltage source onto a rectifier and outputting a rectified voltage signal
VR onto a VR node;

(b) storing energy in a capacitor, wherein the capacitor is coupled between an output voltage node VO and a ground node GND;

(c) in a steady state operation mode of a non-isolated AC-to-DC power supply circuit: 1) decoupling the VO node from the VR node when VR is greater than a first predetermined voltage VP and, 2) supplying a charging current (ICHARGE) from the VR node and onto the VO node when VR is less than VP provided that VO is less than a second predetermined voltage VO(MAX) and provided that VR is greater than VO, wherein the charging current ICHARGE has a first maximum limit value IMAX in the steady state operation mode; and

(d) in a power up operation mode of the non-isolated AC-to-DC power supply circuit: limiting current flow from the VR node to the VO node to be less than a second maximum limit value IMAX2, wherein IMAX2 is less than IMAX1, wherein the non-isolated AC-to-DC power supply circuit includes the rectifier and the capacitor and a charging circuit,
and wherein the charging circuit is coupled between the VR node and the VO node.

US Pat. No. 9,129,824

MODULE AND ASSEMBLY WITH DUAL DC-LINKS FOR THREE-LEVEL NPC APPLICATIONS

IXYS Corporation, Milpit...

1. A method of manufacture, comprising:
coupling a collector of a first Insulated Gate Bipolar Transistor (IGBT) to a first power terminal;
coupling an emitter of the first IGBT to a third power terminal;
coupling an anode of a diode to the emitter of the first IGBT;
coupling a cathode of the diode to the collector of the first IGBT;
providing a DC-link between a second power terminal and a fourth power terminal, wherein the DC-link comprises a pair of IGBTs
coupled together in a common collector configuration; and

encapsulating the first IGBT, the diode, and the DC-link in a first power semiconductor module package, wherein the first,
second, third and fourth power terminals are external terminals of the first power semiconductor module package.

US Pat. No. 9,419,118

TRENCH IGBT WITH TUB-SHAPED FLOATING P-WELL AND HOLE DRAINS TO P-BODY REGIONS

IXYS Corporation, Milpit...

1. A trench Insulated Gate Bipolar Transistor (IGBT) die structure comprising:
a P type collector layer;
an N? type drift layer disposed over the P type collector layer;
a trench that extends a first distance toward the N? type drift layer from a substantially planar upper semiconductor surface,
wherein the trench has an inner sidewall and an outer sidewall and a bottom wall, and wherein the N? type drift layer forms
at least a portion of the bottom wall;

a P type body region that has a plurality of deeper portions and a plurality of shallower portions, wherein each deeper portion
extends a second distance into the N? type drift layer from the substantially planar upper semiconductor surface, wherein
each deeper portion forms a part of the outer sidewall of the trench, wherein each shallower portion extends a third distance
into the N? type drift layer from the substantially planar upper semiconductor surface, wherein each shallower portion forms
a part of the outer sidewall of the trench, wherein the second distance is greater than the third distance, and wherein the
second distance is greater than the first distance;

an N+ type emitter region, wherein the N+ type emitter region extends into the P type body region from the substantially planar
upper semiconductor surface, wherein the N+ type emitter region rings the trench and forms a part of the outer sidewall of
the trench;

a floating P type well region that extends into the N? type drift layer from the substantially planar upper semiconductor
surface, wherein the floating P type well region has a peripheral deeper portion that extends the second distance from the
substantially planar upper semiconductor surface toward the N? type drift layer, wherein the floating P type well region has
a central shallower portion that extends the third distance from the substantially planar upper semiconductor surface toward
the N? type drift layer, wherein the peripheral deeper portion of the floating P type well region rings the central shallower
portion of the floating P type well region and extends along the inner sidewall of the trench;

a gate insulating film covering a surface of the trench;
a trench gate electrode disposed on the gate insulating film;
a first metal terminal that is coupled to the P type body region;
a second metal terminal that is coupled to the trench gate electrode; and
a third metal terminal that is coupled to the P type collector layer.

US Pat. No. 9,089,025

1-WIRE COMMUNICATION PROTOCOL AND INTERFACE CIRCUIT FOR HIGH VOLTAGE APPLICATIONS

IXYS Corporation, Milpit...

1. A system for communicating with a host using control signals over a 1-wire interface comprising:
a driver coupled to the host by the 1-wire interface, the driver including a driver controller; and wherein:
control signals are transmitted from the host to the driver by the 1-wire interface for decoding by the driver controller;
the control signals include binary encoded command mode signals and analog encoded command mode signals, each of the binary
encoded command mode signals and the analog encoded command mode signals being signals in a pulse width modulation (PWM) format;

the driver controller interprets the control signals during the binary encoded command mode as binary signals, and interprets
the control signals during the analog encoded command mode as analog signals; and

each binary encoded command mode signal includes a preamble pulse, at least one command pulse, and a post-amble pulse, each
binary encoded command mode signal beginning with the preamble pulse and ending with the post-amble pulse.

US Pat. No. 9,087,809

ULTRA-FAST BREAKOVER DIODE

IXYS Corporation, Milpit...

1. A breakover diode device, comprising:
a first metal electrode;
a second metal electrode; and
means for blocking current flow from the second metal electrode to the first metal electrode for forward blocking voltages
between the second metal electrode and the first metal electrode that are less than a forward breakover voltage, and for breaking
over and conducting a breakover current from the second metal electrode to the first metal electrode for a voltage between
the second metal electrode and the first metal electrode that equals the forward breakover voltage, wherein a turn on time
(TON) of the breakover diode device is 0.3 microseconds or less, wherein the turn on time is a time period between a first time
when said breakover current starts to flow and a second time when a voltage across the means reaches zero volts, and wherein
a voltage of at least four hundred volts is across the means at the first time when said breakover current starts to flow.

US Pat. No. 9,337,616

BIAS CURRENT CONTROL OF LASER DIODE INSTRUMENT TO REDUCE POWER CONSUMPTION OF THE INSTRUMENT

IXYS Corporation, Milpit...

1. A laser diode driver comprising:
a first current source configured to generate one or more bias current pulses;
a second current source configured to generate one or more drive current pulses;
a controller configured to operate the first current source to generate a first bias current pulse and to operate the second
current source to generate a first drive current pulse; and

a summer having inputs to receive the one or more bias current pulses and the one or more drive current pulses, and having
an output terminal configured for connection to a laser diode, the summer configured to drive the output terminal with an
output current that is the sum of the bias current pulses and the drive current pulses, wherein the first drive current pulse
has a rising edge that is delayed in time relative to a rising edge of the first bias current pulse by the time period TDELAY, wherein a current level of the bias current pulses is less than a turn-on current threshold of the laser diode, and wherein
the laser diode turns on in response to the sum of the bias current pulses and the drive current pulses exceeding the turn-on
current threshold.

US Pat. No. 9,780,168

IGBT WITH WAVED FLOATING P-WELL ELECTRON INJECTION

IXYS Corporation, Milpit...

2. An Insulated Gate Bipolar Transistor (IGBT) die structure comprising:
a P type collector layer;
an N? type drift layer disposed over the P type collector layer;
a P type body region that extends into the N? type drift layer;
an N+ type emitter region, wherein the N+ type emitter region extends into the P type body region from a substantially planar
upper semiconductor surface;

a floating P type well region that extends into the N? type drift layer from the substantially planar upper semiconductor
surface and that is laterally separated from the P type body region, wherein the floating P type well region is surrounded
by one or more of the N+ type emitter regions when the IGBT die structure is considered from a top-down perspective, wherein
the floating P type well region substantially surrounds an electron injector portion of the N? type drift layer, wherein the
electron injector portion of the N? type drift layer extends up to the substantially planar upper semiconductor surface, wherein
the floating P type well region forms a waved bottom interface with the underlying N? type drift layer, and wherein the floating
P type well region has at least one thinner portion disposed between two thicker portions;

a floating N+ type well region that extends into the floating P type well region from the substantially planar upper semiconductor
surface, wherein the floating N+ type well region extends over the at least one thinner portion;

a gate that has a first portion and a second portion, wherein the first portion of the gate extends over a first channel,
wherein the first channel extends from the N+ type emitter region, across a part of the P type body region, across a portion
of the N? type drift layer, and across a part of the floating P type well region, to the floating N+ type well region, wherein
a second portion of the gate extends over a second channel, wherein the second channel extends from the floating N+ type well
region, across a portion of the floating P type well region, to the electron injector portion, wherein in an IGBT transistor
on state electrons flow in a current path from the N+ type emitter region, through the first channel to the floating N+ type
well region, through the floating N+ type well region to the second channel, through the second channel, and to the electron
injector portion of the N? type drift layer;

a first metal terminal, wherein the first metal terminal is coupled to the P type body region and to the N+ type emitter region;
a second metal terminal, wherein the second metal terminal is coupled to the gate; and
a third metal terminal that is coupled to the P type collector layer, wherein the floating P type well region has a substantially
octagonal outer periphery when the IGBT die structure is considered from the top-down perspective, wherein the floating P
type well region surrounds a substantially octagonal area of N? type semiconductor material at the substantially planar upper
semiconductor surface, and wherein the electron injector portion is a part of the substantially octagonal area of N? type
semiconductor material.

US Pat. No. 9,590,033

TRENCH SEPARATION DIFFUSION FOR HIGH VOLTAGE DEVICE

IXYS Corporation, Milpit...

12. A reverse blocking thyristor die having a top semiconductor surface, a bottom semiconductor surface, and peripheral side
edges, the die comprising:
a peripheral trench that extends downward into the die from the top semiconductor surface, wherein the peripheral trench has
inner sidewalls, outer sidewalls, and a bottom, wherein an amount of N type semiconductor material laterally rings the trench
such that N type semiconductor material is disposed between the peripheral trench and the peripheral side edges of the die;

a sidewall doped region that extends laterally inwardly from the inner sidewalls of the trench and that also extends laterally
outwardly from the outer sidewalls of the trench, wherein the sidewall doped region is of P type semiconductor material;

a material that fills the trench;
a peripheral aluminum diffused region that extends upward from the bottom semiconductor surface of the die toward the bottom
of the trench, wherein the peripheral aluminum diffused region is of P type semiconductor material and is doped with aluminum,
and wherein the P type semiconductor material of the peripheral aluminum diffused region extends upward and joins to P type
semiconductor material of the sidewall doped region;

a thyristor gate region of P type semiconductor material;
a thyristor cathode region that extends down from the top semiconductor surface of the die into the thyristor gate region,
wherein the thyristor cathode region is of N+ type semiconductor material; and

a thyristor anode region that extends upward from the bottom semiconductor surface of the die, wherein the thyristor anode
region is of P type semiconductor material, wherein the thyristor gate, cathode and anode regions are parts of a thyristor,
and wherein the thyristor has a forward blocking withstand voltage of at least 4000 volts and also has a reverse blocking
withstand voltage of at least 4000 volts.

US Pat. No. 9,589,953

REVERSE BIPOLAR JUNCTION TRANSISTOR INTEGRATED CIRCUIT

IXYS Corporation, Milpit...

1. An integrated circuit comprising:
an emitter/distributed diode electrode layer of a semiconductor material of a first conductivity type;
a base region extending into the emitter/distributed diode electrode layer, wherein the base region is of a second conductivity
type opposite the first conductivity type, wherein the base region has a first depth at its periphery;

a plurality of collector regions extending into the base region, wherein the plurality of collector regions are of the first
conductivity type;

a plurality of distributed diode diffusion regions extending into the emitter/distributed diode electrode layer, wherein the
plurality of distributed diode diffusion regions are of the second conductivity type, wherein the plurality of distributed
diode diffusion regions are disposed in a two-dimensional array across the integrated circuit, wherein each of the distributed
diode diffusion regions is separated from the base region by a respective part of the emitter/distributed diode electrode
layer, and wherein each of the distributed diode diffusion regions has a second depth that is greater than the first depth
of the base region;

a first metal electrode that is coupled to the plurality of collector regions and is coupled to the plurality of distributed
diode diffusion regions, wherein the first metal electrode is not coupled to the base region;

a plurality of insulation features, wherein the first metal electrode is separated from the base region and from the emitter/distributed
diode electrode layer by the plurality of insulation features;

a second metal electrode that is coupled to the base regions; and
a third metal electrode that is electrically coupled to the emitter/distributed diode electrode layer.

US Pat. No. 9,177,888

ELECTRICALLY ISOLATED POWER SEMICONDUCTOR PACKAGE WITH OPTIMIZED LAYOUT

IXYS Corporation, Milpit...

1. A method of manufacturing a packaged power semiconductor device, comprising:
forming an amount of encapsulant over a semiconductor die, a substrate and a portion of each of a plurality of electrically
conductive leads such that the amount of encapsulant does not cover a major surface of the substrate thereby leaving a portion
of the substrate exposed on a lower surface of the packaged power semiconductor device, wherein the amount of encapsulant
that is formed includes an extended region of encapsulant that extends away from the plurality of electrically conductive
leads, wherein the extended region has an upper surface, a lower surface, an end surface opposite the electrically conductive
leads, and a pair of side surfaces, wherein a protrusion of encapsulant extends downward from the lower surface of the extended
region at a location on the lower surface adjacent to the end surface, and wherein the amount of encapsulant defines a hole
that extends from the upper surface of the extended region to the lower surface of the extended region and does not extend
through any part of the substrate.

US Pat. No. 9,542,212

LOADING A MACHINE CODE API ONTO AN 8-BIT VIRTUAL MACHINE TO ENABLE NEW FUNCTIONALITY

IXYS Intl Limited, Cayma...

1. A method involving a chain of a plurality of virtual machine devices that are chained together in serial fashion, and wherein
each of the virtual machine devices comprises a microcontroller that executes a script interpreter, the method comprising:
(a) relaying a first direct script instruction through virtual machine devices from one virtual machine device to the next
down the chain of virtual machine devices such that the first direct script instruction is supplied to a selected one of the
virtual machine devices;

(b) interpreting the first direct script instruction on the selected one of the virtual machine devices thereby putting the
selected virtual machine device into a direct mode;

(c) relaying an amount of code from one virtual machine device to the next down the chain of virtual machine devices such
that the code is received onto the selected virtual machine device;

(d) loading the amount of code into the selected virtual machine device while the selected virtual machine device is operating
in the direct mode;

(e) relaying a second direct script instruction through virtual machine devices from one virtual machine device to the next
down the chain of virtual machine devices such that the second direct script instruction is supplied to the selected one of
the virtual machine devices; and

(f) interpreting the second direct script instruction on the selected one of the virtual machine devices thereby causing the
selected virtual machine device to exit the direct mode.

US Pat. No. 9,627,521

TRENCH IGBT WITH TUB-SHAPED FLOATING P-WELL AND HOLE DRAINS TO P-BODY REGIONS

IXYS Corporation, Milpit...

1. A trench Insulated Gate Bipolar Transistor (IGBT) die comprising:
a collector layer;
a drift layer;
a trench that extends down into the die from an upper semiconductor surface of the die;
a gate insulating film covering a surface of the trench;
a trench gate electrode disposed on the gate insulating film;
a P type body region that extends from the upper semiconductor surface into the drift layer, wherein first parts of an outer
sidewall of the trench are semiconductor material of the P type body region;

an emitter region that extends from the upper semiconductor surface into the P type body region, wherein a second part of
the outer sidewall of the trench is semiconductor material of the emitter region;

a first metal terminal that is coupled to the P type body region;
a second metal terminal that is coupled to the trench gate electrode;
a third metal terminal that is coupled to the collector layer; and
means for retaining holes in a steady on state of the IGBT and for draining holes to the P type body region during a turn
off of the IGBT, wherein the means comprises a central shallower portion and a peripheral deeper portion, wherein the means
is not electrically connected to any one of the first, second and third metal terminals.

US Pat. No. 9,590,092

SUPER JUNCTION FIELD EFFECT TRANSISTOR WITH INTERNAL FLOATING RING

IXYS Corporation, Milpit...

1. A Super Junction Field Effect Transistor (FET) device, comprising:
a substrate;
a charge compensation region disposed above the substrate, wherein the charge compensation region comprises:
a first plurality of columns of P? type semiconductor material within a region of N? type semiconductor material, wherein
each of the first plurality of columns of P? type semiconductor material includes a P? type body portion that extends from
an upper portion of the column towards the substrate;

a floating ring that surrounds the first plurality of columns of P? type semiconductor material, wherein the floating ring
is a ring-shaped column of P? type semiconductor material within the region of N? type semiconductor material; and

a second plurality of columns of P? type semiconductor material within the region of N? type semiconductor material, wherein
each of the second plurality of columns of P? type semiconductor material includes a P? type body portion that extends from
an upper portion of the P? type column towards the substrate, and wherein the second plurality of columns of P? type semiconductor
material surrounds the floating ring;

a layer of oxide disposed above portions of the charge compensation region, wherein the layer of oxide is disposed above an
upper surface of the floating ring; and

a source metal terminal disposed above portions of the charge compensation region, wherein the source metal terminal contacts
each P? type body portion of the first plurality of columns of P? type semiconductor material, wherein the layer of oxide
is disposed between the upper surface of the floating ring and the source metal terminal, and wherein the source metal terminal
contacts each P? type body portion of the second plurality of columns of P? type semiconductor material.

US Pat. No. 9,601,473

POWER DEVICE CASSETTE WITH AUXILIARY EMITTER CONTACT

IXYS Corporation, Milpit...

1. A power semiconductor device module comprising:
a top plate member;
a bottom plate member having a plurality of pedestals;
a plurality of semiconductor device dice, wherein each of the semiconductor device dice is positioned above a corresponding
one of the plurality of pedestals between the bottom plate member and the top plate member, and wherein each of the semiconductor
device dice has an emitter pad and a gate pad;

an auxiliary emitter terminal, wherein the auxiliary emitter terminal is coupled via a branched network to the emitter pads
of the semiconductor device dice; and

a main emitter terminal, wherein the main emitter terminal is coupled through the pedestals to the emitter pads of the semiconductor
device dice, and wherein the branched network does not extend through any of the pedestals.

US Pat. No. 9,641,065

AC LINE FILTER AND AC-TO-DC RECTIFIER MODULE

IXYS Corporation, Milpit...

1. An Alternating Current Line Filter/Rectifier Module (ACLF/RM) comprising:
a first Direct Current (DC) output module terminal;
a second DC output module terminal;
a first NPN bipolar transistor having a base, collector, and emitter;
a first diode having a cathode coupled to the emitter of the first NPN bipolar transistor and having an anode coupled to the
collector of the first NPN bipolar transistor;

a second NPN bipolar transistor having a base, collector and emitter, wherein the emitter of the second NPN bipolar transistor
is coupled to the emitter of the first NPN bipolar transistor;

a second diode having a cathode coupled to the emitter of the second NPN bipolar transistor and having an anode coupled to
the collector of the second NPN bipolar transistor;

a third NPN bipolar transistor having a base, collector, and emitter, wherein the emitter of the third NPN bipolar transistor
is coupled to the collector of the first NPN bipolar transistor;

a third diode having a cathode coupled to the emitter of the third NPN bipolar transistor and having an anode coupled to the
collector of the third NPN bipolar transistor;

a fourth NPN bipolar transistor having a base, collector, and emitter, wherein the collector of the fourth NPN bipolar transistor
is coupled to the collector of the third NPN bipolar transistor, wherein the emitter of the fourth NPN bipolar transistor
is coupled to the collector of the second NPN bipolar transistor;

a fourth diode having a cathode coupled to the emitter of the fourth NPN bipolar transistor and having an anode coupled to
the collector of the fourth NPN bipolar transistor;

a first Alternating Current (AC) input module terminal;
a second AC input module terminal, wherein the first and second AC input module terminals are adapted to receive an AC input
voltage signal onto the ACLF/RM such that a rectified version of the AC input voltage signal is output by the ACLF/RM across
the first and second DC output module terminals.

US Pat. No. 9,571,003

NON-ISOLATED AC-TO-DC CONVERTER WITH FAST DEP-FET TURN ON AND TURN OFF

IXYS Corporation, Milpit...

1. A method comprising:
(a) receiving an alternating current (AC) supply voltage onto a rectifier and outputting a rectified voltage signal VR onto a VR node;

(b) storing energy in a first capacitor so that the first capacitor is charged to a direct current (DC) voltage, wherein the
first capacitor is coupled between an output voltage node VO and a ground node GND;

(c) in a steady state operation mode of a non-isolated AC-to-DC power supply circuit: 1) decoupling the VO node from the VR node when VR is greater than a first predetermined voltage VP by turning off a depletion-mode field effect transistor (dep-FET) and, 2) turning on the dep-FET and thereby supplying a substantially
constant charging current (ICHARGE) from the VR node and through the dep-FET and onto the VO node when VR is less than VP provided that VO is less than a second predetermined voltage VO(MAX) and provided that VR is greater than VO;

(d) removing charge from a gate of the dep-FET when the dep-FET is being turned off in the steady state operation mode such
that a substantial amount of the charge from the gate is transferred into and is stored in a second capacitor; and

(e) moving charge from the second capacitor and back onto the gate of the dep-FET when the dep-FET is being turned on in the
steady state operation mode.

US Pat. No. 9,857,823

PROGRAMMABLE TEMPERATURE COMPENSATED VOLTAGE GENERATOR

IXYS Corporation, Milpit...

1. An apparatus comprising:
a Digital-to-Analog Converter (DAC) that receives a reference voltage and a digital code, wherein the DAC generates a DAC
output voltage;

a temperature compensator that receives a temperature measurement (T) and the DAC digital code to generate a temperature compensation
signal, wherein the temperature compensation signal is represented by a third order polynomial equation; and

a signal combiner that combines the DAC output voltage and the temperature compensation signal to generate an output signal,
wherein the output signal is used to generate a temperature compensated programmable reference voltage.

US Pat. No. 9,595,950

HIGH-VOLTAGE STACKED TRANSISTOR CIRCUIT

IXYS Corporation, Milpit...

1. An apparatus comprising:
a first field effect transistor (FET) having a gate, a source and a drain;
a second FET having a gate, a source and a drain, wherein the source of the second FET is coupled to the drain of the first
FET;

a third FET having a gate, a source and a drain, wherein the source of the third FET is coupled to the drain of the second
FET;

a first bipolar transistor having a base, an emitter, and a collector, wherein the collector of the first bipolar transistor
is coupled to the source of the second FET;

a second bipolar transistor having a base, an emitter, and a collector, wherein the collector of the second bipolar transistor
is coupled to the source of the third FET;

a first diode having an anode an a cathode, wherein the cathode of the first diode is coupled to the emitter of the first
bipolar transistor;

a second diode having an anode an a cathode, wherein the anode of the second diode is coupled to the anode of the first diode,
and wherein the cathode of the second diode is coupled to the emitter of the second bipolar transistor;

a first resistor coupled between the anode of the first diode and the gate of the first FET;
a second resistor;
a third diode, wherein the second resistor and the third diode are coupled in series between the base of the first bipolar
transistor and the source of the first FET;

a third resistor; and
a fourth diode, wherein the third resistor and the fourth diode are coupled in series between the base of the second bipolar
transistor and the source of the second FET.

US Pat. No. 9,813,055

GATE DRIVER THAT DRIVES WITH A SEQUENCE OF GATE RESISTANCES

IXYS Corporation, Milpit...

1. An integrated circuit comprising:
a first power transistor gate driver having an output lead;
a second power transistor gate driver having an output lead;
a third power transistor gate driver having an output lead;
a signal node, wherein a gate driver control signal is present on the signal node, wherein the gate driver control signal
has a rising edge that is followed by a falling edge; and

a driver control circuit that receives the gate driver control signal and in response to the rising edge enables the first,
second and third power transistor gate drivers sequentially in a first predetermined order, wherein each of the three power
transistor gate drivers when enabled in response to the rising edge drives a high voltage onto its output lead, wherein the
driver control circuit in response to the falling edge enables the first, second and third power transistor gate drivers sequentially
in a second predetermined order, and wherein each of the three power transistor gate drivers when enabled in response to the
falling edge drives a low voltage onto its output lead when it is enabled, wherein the driver control circuit comprises:

a first delay line having a plurality of nodes;
a second delay line having a plurality of nodes; and
an amount of digital logic coupled to receive signals from the plurality of nodes of the first delay line and coupled to receive
signals from the plurality of nodes of the second delay line, wherein the amount of digital logic supplies a first enable
signal to the first power transistor gate driver, wherein the amount of digital logic supplies a second enable signal to the
second power transistor gate driver, and wherein the amount of digital logic supplies a third enable signal to the third power
transistor gate driver.

US Pat. No. 9,698,741

CHOPPER STABILIZED AMPLIFIER WITH SYNCHRONOUS SWITCHED CAPACITOR NOISE FILTERING

IXYS Corporation, Milpit...

1. An apparatus comprising:
a chopper amplifier having an input that receives an input signal and an output that outputs an amplified signal, the chopper
amplifier includes an input chopping circuit coupled to the input and an output chopping circuit coupled to the output, the
input and output chopping circuits operate in response to a chop clock;

a switched capacitor filter having an input that receives the amplified signal and an output that outputs a filtered signal,
the switched capacitor filter operates in response to at least one filter clock; and

a filter timing adjuster having an input to receive a reference voltage and the chop clock, and an output to output the at
least one filter clock, the filter timing adjuster adjusts a phase of the at least one filter clock with respect to the chop
clock.

US Pat. No. 9,837,529

POWER MOSFET HAVING IMPROVED MANUFACTURABILITY, LOW ON-RESISTANCE AND HIGH BREAKDOWN VOLTAGE

IXYS Corporation, Milpit...

1. A power field effect transistor die structure comprising:
a substrate semiconductor layer of a first conductivity type;
a first epitaxial semiconductor layer disposed on the substrate;
a second epitaxial semiconductor layer disposed on the first epitaxial semiconductor layer, wherein an upper surface of the
second epitaxial semiconductor layer is an upper semiconductor surface of the die structure, and wherein the first and second
epitaxial semiconductor layers are the only epitaxial semiconductor layers of the power field effect transistor die structure;

a plurality of parallel-extending Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs) of a second conductivity type,
wherein each of the parallel-extending BSSCCRs is disposed partly in the first epitaxial layer and is disposed partly in the
second epitaxial layer but is entirely covered by semiconductor material of the first conductivity type of the second epitaxial
semiconductor layer, wherein each of the parallel-extending BSSCCRs has an end, wherein one of the BSSCCRs extends in a first
straight line;

a transistor structure that is disposed over the plurality of parallel-extending BSSCCRs, wherein the transistor structure
includes a gate region and a source region;

an inner BSSCCR of the second conductivity type, wherein the inner BSSCCR extends for a distance in a second straight line,
wherein the second straight line is perpendicular to the first straight line, wherein the inner BSSCCR is disposed partly
in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered by semiconductor
material of the first conductivity type of the second epitaxial semiconductor layer;

an outer BSSCCR of the second conductivity type, wherein the outer BSSCCR extends parallel to the inner BSSCCR such that the
inner BSSCCR is disposed between the outer BSSCCR and the plurality of parallel-extending BSSCCRs, wherein the outer BSSCCR
is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered
by semiconductor material of the first conductivity type of the second epitaxial semiconductor layer;

a first surface region of the second conductivity type, wherein the first surface region is disposed at the upper semiconductor
surface of the die structure;

a second surface region of the second conductivity type, wherein the second surface region extends parallel to the first surface
region at the upper semiconductor surface of the die structure, and wherein the second surface region is floating and is stripe-shaped;

a third surface region of the second conductivity type, wherein the third surface region extends parallel to the second surface
region at the upper semiconductor surface of the die structure such that the second surface region is disposed between the
first and third surface regions, wherein the third surface region is stripe-shaped; and

a metal bridging member that electrically couples the first and third surface regions together, wherein the metal bridging
member bridges over the second surface region but is not coupled to the second surface region, and wherein the metal bridging
member is disposed at least in part over the inner BSSCCR.

US Pat. No. 9,800,159

BUCK CONVERTER HAVING SELF-DRIVEN BJT SYNCHRONOUS RECTIFIER

IXYS Corporation, Milpit...

1. A buck converter comprising:
an output node;
a ground node;
an output capacitor coupled between the output node and the ground node;
an inductor;
a main switch that in a first portion of a switching cycle of the buck converter conducts a first current in a first current
path, wherein the first current path extends through the main switch, and through the inductor, and to the output node of
the buck converter; and

a self-driven bipolar junction transistor (BJT) synchronous rectifier that conducts a second current in a second portion of
the switching cycle in a second current path, wherein the second current path extends from the ground node of the buck converter,
through the self-driven BJT synchronous rectifier, and through the inductor, and to the output node, wherein the self-driven
BJT synchronous rectifier is off in the first portion of the switching cycle, wherein a collector of a bipolar transistor
of the self-driven BJT synchronous rectifier is connected to a first end of the inductor, and wherein a base of the bipolar
transistor of the self-driven BJT synchronous rectifier is connected to a first end of a second inductor, wherein a second
end of the second inductor is connected to the output node, wherein a first plate of the output capacitor is connected to
the second end of the inductor, and wherein a second plate of the output capacitor is connected to an emitter of the bipolar
transistor of the self-driven BJT synchronous rectifier.

US Pat. No. 9,780,202

TRENCH IGBT WITH WAVED FLOATING P-WELL ELECTRON INJECTION

IXYS Corporation, Milpit...

13. An Insulated Gate Bipolar Transistor (IGBT) die structure comprising:
a P type collector layer;
an N? type drift layer disposed over the P type collector layer;
a P type body region that extends into the N? type drift layer;
an N+ type emitter region, wherein the N+ type emitter region extends into the P type body region from a substantially planar
upper semiconductor surface;

a floating P type well region that extends into the N? type drift layer and that is laterally separated from the P type body
region, wherein the floating P type well region has a thinner portion disposed between two of a plurality of thicker portions,
wherein the thinner portion of the floating P type well region is less than half as thick as the thicker portions of the floating
P type well region, wherein the thinner portion of the floating P type well region extends to a depth DP2THIN measured from the substantially planar upper semiconductor surface, wherein the floating P type well region has a polygonal
outer periphery when the trench IGBT die structure is considered from a top-down perspective, and wherein the floating P type
well region at all locations along its polygonal outer periphery extends to a depth greater than DP2THIN measured from the substantially planar upper semiconductor surface;

a trench gate electrode disposed in a trench, wherein the trench gate electrode is disposed at least in part between the P
type body region on one side of the trench and the floating P type well region on an opposite side of the trench;

a first metal terminal, wherein the first metal terminal is coupled to the P type body region and to the N+ type emitter region;
a second metal terminal, wherein the second metal terminal is coupled to the trench gate electrode; and
a third metal terminal that is coupled to the P type collector layer.

US Pat. No. 9,705,417

LOW FORWARD VOLTAGE RECTIFIER

IXYS Corporation, Milpit...

1. An apparatus comprising:
a first Field Effect Transistor (FET) having a body diode, a source terminal, a drain terminal, and a gate terminal;
a second FET having a body diode, a source terminal, a drain terminal, and a gate terminal, wherein the drain terminal of
the second FET is coupled to the drain terminal of the first FET, and wherein the gate terminal of the second FET is coupled
to the gate terminal of the first FET;

a sense resistor having a first lead and a second lead, wherein the sense resistor is disposed in series with the body diode
of the second FET; and

a comparator having a first input lead, a second input lead, and an output lead, wherein the first input lead of the comparator
is coupled to the first lead of the sense resistor, and wherein the second input lead of the comparator is coupled to the
second lead of the sense resistor, wherein a control signal on the output lead of the comparator is supplied onto the gate
terminals of the first and second FETs.

US Pat. No. 9,640,461

BRIDGING DMB STRUCTURE FOR WIRE BONDING IN A POWER SEMICONDUCTOR MODULE

IXYS Corporation, Milpit...

1. A power semiconductor module comprising:
a metal baseplate;
a first direct bonded metal (DMB) structure that is disposed on the metal baseplate, wherein the first DMB comprises a ceramic
layer, a first direct bonded metal layer disposed on a bottom side of the ceramic layer in thermal contact with the metal
baseplate, a first island of a second direct bonded metal layer disposed on a top side of the ceramic layer, and a second
island of the second direct bonded metal layer disposed on the top side of the ceramic layer;

a semiconductor device that is disposed on the first island of the second direct bonded metal layer of the first DMB structure;
a second DMB structure that is disposed on the second island of the second direct bonded metal layer of the first DMB structure,
wherein the second DMB structure comprises a ceramic layer, a third direct bonded metal layer disposed on a bottom side of
the ceramic layer of the second DMB structure, and a fourth direct bonded metal layer disposed on a top side of the ceramic
layer of the second DMB structure, wherein the third direct bonded metal layer of the second DMB structure is disposed on
the second island of the second direct bonded metal layer of the first DMB structure, and wherein no semiconductor device
is disposed on the second DMB structure;

a first external connection terminal;
a second external connection terminal;
a first bonding wire that connects the first external connection terminal to a first bonding location on the fourth direct
bonded metal layer of the second DMB structure;

a second bonding wire that connects a second bonding location on the fourth direct bonded metal layer of the second DMB structure
to the semiconductor device; and

a third bonding wire that extends from the second external connection terminal over the fourth direct bonded metal layer of
the second DMB structure without contacting any portion of the fourth direct bonded metal layer of the second DMB structure.

US Pat. No. 9,704,832

DIE STACK ASSEMBLY USING AN EDGE SEPARATION STRUCTURE FOR CONNECTIVITY THROUGH A DIE OF THE STACK

IXYS Corporation, Milpit...

1. An assembly comprising:
a first power semiconductor device die having a first substantially planar semiconductor surface and a second substantially
planar semiconductor surface, wherein a peripheral edge separation diffusion region extends from the first substantially planar
semiconductor surface to the second substantially planar semiconductor surface along a side edge of the first power semiconductor
device die, wherein the peripheral edge separation diffusion region of the first power semiconductor device die is a P type
semiconductor region that is doped at least in part with aluminum, and wherein a metal feature covers and makes electrical
contact with the peripheral edge separation diffusion region at the first substantially planar semiconductor surface of the
first power semiconductor device die; and

a second power semiconductor device die having a first substantially planar semiconductor surface and a second substantially
planar semiconductor surface, wherein a peripheral edge separation diffusion region extends from the first substantially planar
semiconductor surface to the second substantially planar semiconductor surface along a side edge of the second power semiconductor
device die, wherein the peripheral edge separation diffusion region of the second power semiconductor device die is a P type
semiconductor region that is doped at least in part with aluminum, wherein the second power semiconductor device die is bonded
to the first power semiconductor device die such that the metal feature is electrically coupled within the assembly through
the peripheral edge separation diffusion region of the first power semiconductor device die to the peripheral edge separation
diffusion region of the second power semiconductor device die.

US Pat. No. 9,842,795

LEAD AND LEAD FRAME FOR POWER PACKAGE

IXYS Corporation, Milpit...

1. A power device comprising:
a substrate;
a power semiconductor chip having an upper surface defining an upper surface plane, and a lower surface, the lower surface
affixed to the substrate;

encapsulating material surrounding the substrate and the power semiconductor chip; and
a lead comprising a main portion, a first raised portion, and an end portion having a connecting portion, a second raised
portion, and a bonded portion, wherein the main portion is separated from the end portion by the first raised portion, wherein
the first raised portion extends from the connecting portion towards the main portion along a first direction, wherein the
second raised portion extends from the connecting portion towards the bonded portion along a second direction, wherein the
first direction and the second direction are nonparallel, wherein the lead is an integrally formed piece of leadframe metal,
wherein the main portion extends from outside the encapsulating material to the power semiconductor chip and having a longitudinal
axis, the longitudinal axis of the main portion being disposed parallel to the upper surface plane of the power semiconductor
chip, wherein part of the end portion is bonded to, and is in electrical contact with, a bonding pad on the upper surface
of the power semiconductor chip, and wherein at least part of the first raised portion is positioned above the semiconductor
chip at a greater height than each of the main portion and the end portion.

US Pat. No. 9,911,838

IGBT DIE STRUCTURE WITH AUXILIARY P WELL TERMINAL

IXYS Corporation, Milpit...

1. An Insulated Gate Bipolar Transistor (IGBT) die structure comprising:
a P type substrate layer;
an N type drift layer disposed over the P type substrate layer;
a P type body region that extends into the N type drift layer;
an N type source region that extends into the P type body region;
an auxiliary P type well region that extends into the N type drift layer and that is separated from the P type body region;
a gate;
a first metal terminal, wherein the first metal terminal is coupled to the P type body region and to the N type source region;
a second metal terminal, wherein the second metal terminal is coupled to the gate;
a third metal terminal, wherein the third metal terminal is coupled to the auxiliary P type well region; and
a fourth metal terminal that is coupled to the P type substrate layer.

US Pat. No. 9,780,648

SYNCHRONOUS SENSING OF INDUCTOR CURRENT IN A BUCK CONVERTER CONTROL CIRCUIT

IXYS Corporation, Milpit...

13. An integrated circuit comprising:
a first input terminal;
a second input terminal;
a first output terminal;
a second output terminal;
a sequential logic element, wherein when the sequential logic element is in a first state then the sequential logic element
asserts an output signal onto the first output terminal, and wherein when the sequential logic element is in a second state
then the sequential logic element deasserts the output signal on the first output terminal;

an analog amplifier that amplifies a voltage signal between the first input terminal and the second input terminal thereby
generating a first analog signal;

an offset detector that detects an offset voltage in the first analog signal, wherein the offset voltage is a voltage of the
first analog signal at a time when the sequential logic element switches from the second state to the first state;

a level shift circuit that level shifts the first analog signal by a voltage that is proportional to the detected offset voltage
thereby generating a second analog signal;

a first detector circuit that determines when the second analog signal exhibits a first characteristic and in response causes
the sequential logic element to be put into the second state;

a second detector circuit that determines when the second analog signal exhibits a second characteristic and in response asserts
a second output signal onto the second output terminal; and

a third input terminal, wherein a trigger signal received onto the third input terminal causes the sequential logic element
to be put into the first state, wherein the integrated circuit comprises no digital processor that fetches and executes any
processor-executable instructions from any memory.

US Pat. No. 9,992,833

MULTI-STAGE LED DRIVER WITH CURRENT PROPORTIONAL TO RECTIFIED INPUT VOLTAGE AND LOW DISTORTION

IXYS, LLC, Milpitas, CA ...

1. A method comprising:receiving a rectified AC input signal at an input node of an LED string formed by a plurality of LED groups having interconnecting nodes and a last node that are connected to a plurality of current cells;
enabling a selected current cell based on the input signal, wherein the selected current cell regulates current flowing from a selected node to an output resistor;
generating feedback voltages based on an output voltage generated by the output resistor; and
disabling current cells that are upstream from the selected current cell.

US Pat. No. 9,935,206

PACKAGED OVERVOLTAGE PROTECTION CIRCUIT FOR TRIGGERING THYRISTORS

IXYS Corporation, Milpit...

1. A packaged overvoltage protection circuit comprising:a first semiconductor die, wherein the first semiconductor die comprises a breakover diode having a reverse breakdown voltage of at least four hundred volts;
a second semiconductor die, wherein the second semiconductor die comprises a breakover diode having a reverse breakdown voltage of at least four hundred volts;
a package housing that encloses the first and second semiconductor dice;
a first package terminal; and
a second package terminal, wherein the first and second semiconductor dice are coupled such that if a positive voltage of adequate magnitude is present between the second package terminal and the first package terminal then breakover of the breakover diodes in the first and second semiconductor dice occurs and a current flows in a current path from the second package terminal, through the breakover diode of the first semiconductor die, through the breakover diode of the second semiconductor die, and to the first package terminal, and such that if a negative voltage of nine hundred volts or less is present between the second package terminal and the first package terminal then neither of the breakover diodes of the first and second semiconductor dice suffers reverse breakdown, and wherein the packaged overvoltage protection circuit has no package terminal other than the first and second package terminals.

US Pat. No. 9,922,864

TRENCH SEPARATION DIFFUSION FOR HIGH VOLTAGE DEVICE

IXYS Corporation, Milpit...

1. A method of manufacture comprising:
forming a peripheral aluminum diffused region of P type semiconductor material that extends upward into a semiconductor wafer
from a bottom semiconductor surface of the wafer, wherein the semiconductor wafer is at least six hundred microns thick and
is of N type bulk semiconductor material;

forming a peripheral trench down into the semiconductor wafer from a top semiconductor surface of the wafer, wherein the peripheral
trench has vertical inner sidewalls, vertical outer sidewalls, and a bottom, and wherein the peripheral aluminum diffused
region and the peripheral trench extend around an active area of the wafer;

forming a sidewall doped region of P type semiconductor material that extends laterally inwardly from the vertical inner sidewalls
toward the active area, wherein the sidewall doped region of P type semiconductor material joins the peripheral aluminum region
of P type semiconductor material so that P type semiconductor material extends contiguously and vertically a distance of at
least six hundred microns from the top semiconductor surface of the wafer to the bottom semiconductor surface of the wafer;

filling the peripheral trench with a solid trench fill material; and
singulating the wafer thereby forming a semiconductor device die having outer edges, wherein the peripheral trench extends
along a periphery of the semiconductor device die, wherein an amount of N type bulk semiconductor material is disposed between
the peripheral trench and outer edges of the die, and wherein the peripheral aluminum diffused region extends upward from
the bottom semiconductor surface a distance of at least one hundred microns into the semiconductor device die.

US Pat. No. 9,912,331

GATE DRIVER THAT DRIVES WITH A SEQUENCE OF GATE RESISTANCES

IXYS Corporation, Milpit...

1. An integrated circuit comprising:
a first power transistor gate driver having an output lead;
a second power transistor gate driver having an output lead;
a third power transistor gate driver having an output lead;
a signal node, wherein a gate driver control signal is present on the signal node, wherein the gate driver control signal
is a digital signal that has a rising edge that is followed by a falling edge; and

a driver control circuit that receives the gate driver control signal and in response to the rising edge enables the first,
second and third power transistor gate drivers sequentially in a first predetermined order, wherein each of the three power
transistor gate drivers when enabled in response to the rising edge drives a high voltage onto its output lead, wherein the
driver control circuit in response to the falling edge enables the first, second and third power transistor gate drivers sequentially
in a second predetermined order, and wherein each of the three power transistor gate drivers when enabled in response to the
falling edge drives a low voltage onto its output lead when it is enabled.

US Pat. No. 9,941,256

INVERSE DIODE STACK

IXYS Corporation, Milpit...

1. An apparatus comprising:a plurality of inverse diode dice, wherein each inverse diode die has a P type anode region that extends into an N? type semiconductor region of the die from a backside semiconductor surface of the die, wherein said each inverse diode die also has an N type cathode region that extends into the N? type semiconductor region of the die from a topside semiconductor surface of the die, and wherein said each inverse diode die also has a P type edge separation diffusion region that extends from the backside semiconductor surface to the topside semiconductor surface so that the P type edge separation diffusion region laterally surrounds the N? type semiconductor region of the die; and
a plurality of Direct Metal Bonded (DMB) substrate structures, wherein each of the DMB substrate structures is bonded to at least one of the inverse diode dice such that the plurality of inverse diode dice are series-connected by the plurality of DMB substrate structures, and wherein the plurality of inverse diode dice and the plurality of DMB substrate structures together form a stack.

US Pat. No. 9,929,066

POWER SEMICONDUCTOR DEVICE MODULE BASEPLATE HAVING PERIPHERAL HEELS

IXYS Corporation, Milpit...

1. A power semiconductor device module baseplate comprising:a substantially rectangular plate portion, wherein the plate portion has a width of at least two centimeters, a length of at least six centimeters, a bottom surface and four sides, wherein the bottom surface has a slightly convex downward shape, wherein a first side of the plate portion is opposite to a second side of the plate portion, wherein there is at least one mounting hole adjacent the first side of the plate portion and there is at least one mounting hole adjacent the second side of the plate portion;
a first downward-extending peripheral heel extension portion, wherein the first downward-extending peripheral heel extension portion extends downward from the bottom surface of the plate portion at the first side of the plate portion for a distance of more than thirty microns and less than five hundred microns; and
a second downward-extending peripheral heel extension portion, wherein the second downward-extending peripheral heel extension portion extends downward from the bottom surface of the plate portion at the second side of the plate portion for a distance of more than thirty microns and less than five hundred microns, wherein the first downward-extending peripheral heel extension portion is one of a first plurality of downward-extending peripheral heel extension portions, wherein the downward-extending peripheral heel extension portions of the first plurality are collinear with respect to one another and are aligned along a first bottom edge of the power semiconductor device module baseplate, wherein the second downward-extending peripheral heel extension portion is one of a second plurality of downward-extending peripheral heel extension portions, wherein the downward-extending peripheral heel extension portions of the second plurality are collinear with respect to one another and are aligned along a second bottom edge of the power semiconductor device module baseplate, wherein each downward-extending peripheral heel extension portion of the first plurality of downward-extending peripheral heel extension portions is a separate and distinct downward-extending peripheral heel extension portion with respect to each of the other downward-extending peripheral heel extension portions of the first plurality of downward-extending peripheral heel extension portions, and wherein each downward-extending peripheral heel extension portion of the second plurality of downward-extending peripheral heel extension portions is a separate and distinct downward-extending peripheral heel extension portion with respect to each of the other downward-extending peripheral heel extension portions of the second plurality of downward-extending peripheral heel extension portions.

US Pat. No. 9,923,324

AC LINE FILTER AND AC-TO-DC RECTIFIER MODULE

IXYS Corporation, Milpit...

1. An AC Line Filter/Rectifier Module (ACLF/RM) comprising:
a plurality of AC input module terminals adapted to receive an AC input voltage signal onto the AC Line Filter/Rectifier module,
wherein the plurality of AC input module terminals are parts of an IEC60320 AC power socket;

a plurality of DC output module terminals adapted to output a full wave rectified version of the AC input voltage signal,
wherein the DC output module terminals include a DC ground terminal;

at least one low forward voltage rectifier, wherein the at least one low forward voltage rectifier comprises:
a bipolar junction transistor having an emitter, a base, and a collector; and
a diode having a cathode and an anode, wherein the cathode is coupled to one of the collector and the emitter of the bipolar
transistor, wherein the anode is coupled to the other of the collector and the emitter of the bipolar transistor; and

a metal housing that houses a first winding and the at least one low forward voltage rectifier, wherein the IEC60320 AC power
socket is secured with respect to the metal housing, and wherein the plurality of DC output module terminals are secured with
respect to the metal housing.

US Pat. No. 9,924,573

MULTI-STAGE LED DRIVER WITH CURRENT PROPORTIONAL TO RECTIFIED INPUT VOLTAGE AND LOW DISTORTION

IXYS Corporation, Milpit...

1. An apparatus comprising:
a plurality of LED groups connected in series to form an LED string that has a first node, a last node, and one or more intermediate
nodes;

a plurality of current cells having inputs coupled to the first, last and intermediate nodes, respectively, and outputs coupled
to an output resistor, and wherein each current cell selectively regulates current flowing between its respective input and
the output resistor based on its respective feedback voltage; and

a feedback circuit that generates a plurality of feedback voltages from a voltage level at the output resistor.

US Pat. No. 9,948,205

AC LINE FILTER AND AC-TO-DC RECTIFIER MODULE

IXYS Corporation, Milpit...

1. A device comprising:a first direct current (DC) output terminal;
a second DC output terminal;
a first bipolar transistor;
a first diode coupled between an emitter and a collector of the first bipolar transistor;
a second bipolar transistor, wherein an emitter of the second bipolar transistor is coupled to the emitter of the first bipolar transistor;
a second diode coupled between the emitter and a collector of the second bipolar transistor;
a third bipolar transistor, wherein an emitter of the third bipolar transistor is coupled to the collector of the first bipolar transistor;
a third diode coupled between the emitter and a collector of the third bipolar transistor;
a fourth bipolar transistor, wherein a collector of the fourth bipolar transistor is coupled to the collector of the third bipolar transistor, wherein an emitter of the fourth bipolar transistor is coupled to the collector of the second bipolar transistor;
a fourth diode coupled between the emitter and the collector of the fourth bipolar transistor;
a first alternating current (AC) input terminal; and
a second AC input terminal, wherein the first and second AC input terminals are adapted to receive an AC input voltage signal onto the device such that a rectified version of the AC input voltage signal is output by the device across the first and second DC output terminals.

US Pat. No. 9,048,949

CONTROLLING TRANSMISSION POWER IN AN IRDA/RC TRANSMITTER CIRCUIT

IXYS CH GmbH, (CH)

1. A handheld infrared remote control (RC) device, the remote control device comprising:
an infrared transmitter circuit that emits an infrared remote control signal that controls an electronic consumer device,
wherein the infrared transmitter circuit transmits the remote control signal to the electronic consumer device at a plurality
of transmission power settings; and

a microcontroller that determines which one of the plurality of transmission power settings will be used.

US Pat. No. 9,210,818

POWER SEMICONDUCTOR MODULE WITH ASYMMETRICAL LEAD SPACING

IXYS Semiconductor GmbH, ...

1. A power semiconductor module comprising:
a first power semiconductor component having power and control terminals, wherein the first power semiconductor component
is disposed on a carrier board;

a second power semiconductor component having power and control terminals, wherein the second power semiconductor component
is also disposed on the carrier board, wherein the power terminals of the first power semiconductor component are commonly
coupled to the power terminals of the second semiconductor component;

a housing that encloses each of the first and second power semiconductor components, wherein the housing at least partly encloses
the carrier board; and

a plurality of electrically conductive leads connected to corresponding ones of the power and control terminals and extending
to outside the housing, wherein the electrically conductive leads connected to the power terminals are arranged in a row along
one side of the housing, wherein the electrically conductive leads connected to the control terminals are arranged in a row
along an opposite side of the housing, and wherein a spacing between adjacent power terminals is greater than or equal to
each spacing between adjacent control terminals.

US Pat. No. 10,050,527

SYNCHRONOUS SENSING OF INDUCTOR CURRENT IN A BUCK CONVERTER CONTROL CIRCUIT

IXYS, LLC, Milpitas, CA ...

1. A method comprising:(a) using an analog amplifier to amplify a voltage signal between a first input terminal and a second input terminal thereby generating a first analog signal, wherein the voltage signal is a voltage signal across a resistor during first and second switching cycles of a buck converter;
(b) using an offset detector to detect an offset voltage in the first analog signal;
(c) using a level shift circuit to level shift the first analog signal by the offset voltage thereby generating a second analog signal, wherein the second analog signal is a level-shifted version of the first analog signal;
(d) detecting when the second analog signal exhibits a first characteristic during the second switching cycle;
(e) in response to the detecting of (d) deasserting a first output signal onto a first output terminal, wherein the deasserting of the first output signal causes a main switch to turn off during the second switching cycle;
(f) detecting when the second analog signal exhibits a second characteristic during the second switching cycle;
(g) in response to the detecting of (f) asserting a second output signal onto a second output terminal;
(h) receiving an input trigger signal onto an input terminal, wherein the input trigger signal is received during the second switching cycle; and
(i) in response to the receiving of (h) asserting the first output signal, wherein the asserting of the first output signal causes the main switch to turn on at the end of the second switching cycle.

US Pat. No. 10,000,423

DIRECT METAL BONDING ON CARBON-COVERED CERAMIC CONTACT PROJECTIONS OF A CERAMIC CARRIER

IXYS, LLC, Milpitas, CA ...

1. A method comprising:placing a ceramic carrier in contact with a unoxidized carbon member such that ceramic contact projections touch unoxidized carbon of the unoxidized carbon member;
moving the ceramic carrier with respect to the unoxidized carbon member such that unoxidized carbon is left disposed on the ceramic projections of the ceramic carrier;
placing a Direct Metal Bonded (DMB) panel stack on the ceramic carrier such that a bottom surface of a second metal plate of the stack rests on the ceramic contact projections of the ceramic carrier, wherein the stack comprises a ceramic sheet member, a first metal plate disposed in contact with a top surface of the ceramic sheet member, and the second metal plate disposed in contact with a bottom surface of the ceramic sheet member, and wherein a separation layer comprising an amount of unoxidized carbon is disposed on each ceramic contact projection so that at least some unoxidized carbon is disposed between the ceramic contact projection and the overlying second metal plate of the stack; and
in a high-temperature direct-bonding step, when the stack is disposed on the ceramic carrier, causing the first metal plate to be direct-bonded to the top surface of the ceramic sheet member at the same time that the second metal plate is direct-bonded to the bottom surface of the ceramic sheet member.

US Pat. No. 10,090,751

GATE DRIVER FOR SWITCHING CONVERTER HAVING BODY DIODE POWER LOSS MINIMIZATION

IXYS, LLC, Milpitas, CA ...

1. A method involving a high-side transistor and a low-side transistor, wherein a source of the high-side transistor is coupled to a drain of the low-side transistor at a node, wherein a diode is disposed in parallel with the high-side transistor, the method comprising:(a) receiving a high-side driver digital control signal, wherein the high-side driver digital control signal has a first digital logic value;
(b) in response to receiving the high-side driver digital control signal of the first digital logic value in (a) driving a high-side (HS) gate signal onto a gate of the high-side transistor such that the high-side transistor is controlled to be off;
(c) determining that a current flow through the diode rises and exceeds a threshold current, wherein the determining of (c) occurs when the high-side driver digital control signal is at the first digital logic value;
(d) in response to the determining of (c) driving the HS gate signal onto the gate of the high-side transistor such that the high-side transistor turns on;
(e) receiving a low-side driver digital control signal, wherein the low-side driver digital control signal has the first digital logic value;
(f) detecting that the low-side driver digital control signal transitions from the first digital logic value to a second digital logic value, wherein the low-side driver digital control signal transitions from the first digital logic value to the second digital logic value in (f) after the determining of (c);
(g) in response to the detecting of (f) driving the HS gate signal onto the gate of the high-side transistor such that the high-side transistor is turned off;
(h) determining that a gate-to-source voltage of the high-side transistor has dropped below a threshold voltage, wherein the gate-to-source voltage of the high-side transistor drops below the threshold voltage in (h) in response to the driving of the HS gate signal in (g);
(i) in response to the determining of (h) driving a low-side (LS) gate signal onto a gate of the low-side transistor such that the low side transistor is controlled to turn on; and
(j) driving the LS gate signal onto the gate of the low-side transistor such that the low side transistor remains on as long as the low-side driver digital control signal remains at the second digital logic value, wherein the high-side driver digital control signal remains at the first digital logic value and does not transition digital values to a second digital logic value at any time during steps (c) through (j).

US Pat. No. 9,790,130

METHOD OF JOINING METAL-CERAMIC SUBSTRATES TO METAL BODIES

IXYS Semiconductor GmbH, ...

1. A method of joining a metal-ceramic substrate to a metal body using a metal alloy, where the metal-ceramic substrate has
metallization on at least one side, the method comprising:
providing the metal body with a thickness of less than 1 mm;
placing a metal alloy which contains aluminum and has a liquidus temperature of greater than 450° C. between the metal-ceramic
substrate and the metal body to form an assembly, wherein the metal-ceramic substrate is adapted to have a semiconductor component
disposed on at least one metalized side of the metal-ceramic substrate, and wherein the metal-ceramic substrate includes a
ceramic substrate and no more than two metal layers; and

heating the assembly to a temperature of greater than 450° C. such that the at least one metalized side of the metal-ceramic
substrate contacts an inert gas atmosphere during heating.

US Pat. No. 10,219,339

CURRENT CORRECTION TECHNIQUES FOR ACCURATE HIGH CURRENT SHORT CHANNEL DRIVER

IXYS, LLC, Milpitas, CA ...

1. An apparatus comprising:an output node;
a ground node;
a bias current node;
a replica node;
a summing node;
a current driver transistor;
a summing node reference current generator circuit, wherein the summing node reference current generator circuit generates a summing node reference current on the summing node;
voltage detector circuit, wherein during an operating mode the voltage detector circuit detects an output voltage on the output node and generates a replica voltage on the replica node;
an Output Model Current Mirror (OMCM) circuit, wherein the OMCM circuit receives the replica voltage generated by the voltage detector circuit and generates an output model current, and wherein the output model current is supplied onto the summing node;
a Corrected Current Mirror (CCM) circuit that generates a scaled corrected current, wherein the CCM circuit generates the scaled corrected current by scaling a corrected current, and wherein the corrected current is a difference between the summing node reference current and the output model current; and
a Corrected Current to Gate Voltage Converter (CCGVC) circuit, wherein the CCGVC circuit converts the scaled corrected current into a gate voltage that is supplied onto the gate of the current driver transistor.

US Pat. No. 10,038,383

LOW FORWARD VOLTAGE RECTIFIER USING CAPACITIVE CURRENT SPLITTING

IXYS, LLC, Milpitas, CA ...

1. A method of manufacture comprising:(a) providing a first capacitor, a second capacitor, a bipolar transistor and a diode, such that the first capacitor is connected between a first node and a base of the bipolar transistor, such that the second capacitor is connected between the first node and a collector of the bipolar transistor, such that an anode of the diode is coupled to the collector of the bipolar transistor, and such that a cathode of the diode is coupled to an emitter of the bipolar transistor at a second node, wherein the first capacitor, the second capacitor, the bipolar transistor, and the diode are parts of a switching power converter circuit.

US Pat. No. 10,062,621

POWER SEMICONDUCTOR DEVICE MODULE HAVING MECHANICAL CORNER PRESS-FIT ANCHORS

IXYS, LLC, Milpitas, CA ...

1. A power semiconductor device module that has a bottom surface and a top surface, herein the power semiconductor device module has a rectangular shape when considered from a top-down perspective, the power semiconductor device module comprising:a metal baseplate, wherein a planar bottom surface of the metal baseplate is the bottom surface of the power semiconductor device module, wherein the planar bottom surface of the metal baseplate is in a plane;
a housing frame of an insulative plastic material, wherein the housing frame fits down onto and engages the metal baseplate such that the metal baseplate and the housing frame together form a shallow tray, wherein the shallow tray has an upper rim;
a cap of an insulative plastic material that fits down onto the upper rim, wherein the cap forms the top surface of the power semiconductor device module, and wherein the cap has a plurality of peripheral holes;
a plurality of electrical press-fit terminals, wherein each electrical press-fit terminal extends through a corresponding one of the peripherals holes such that a press-fit pin portion of the electrical press-fit terminal extends upward and away from the cap in a direction perpendicular to the plane of the planar bottom surface of the metal baseplate; and
four mechanical corner press-fit anchors, wherein each of the four mechanical corner press-fit anchors is disposed outside the upper rim when the power semiconductor device module is considered from the top-down perspective, wherein each of the four mechanical corner press-fit anchors has a press-fit pin portion that extends upward and away from the housing frame in a direction perpendicular to the plane of the planar bottom surface of the metal baseplate.

US Pat. No. 10,038,088

POWER MOSFET HAVING IMPROVED MANUFACTURABILITY, LOW ON-RESISTANCE AND HIGH BREAKDOWN VOLTAGE

IXYS, LLC, Milpitas, CA ...

1. A power field effect transistor die structure comprising:a substrate semiconductor layer of a first conductivity type;
a first epitaxial semiconductor layer disposed on the substrate;
a second epitaxial semiconductor layer disposed on the first epitaxial semiconductor layer, wherein an upper surface of the second epitaxial semiconductor layer is an upper semiconductor surface of the die structure, and wherein the first and second epitaxial semiconductor layers are the only epitaxial semiconductor layers of the power field effect transistor die structure;
a plurality of parallel-extending Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs) of a second conductivity type, wherein each of the parallel-extending BSSCCRs is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered by semiconductor material of the first conductivity type of the second epitaxial semiconductor layer;
a transistor structure that is disposed over the plurality of parallel-extending BSSCCRs, wherein the transistor structure includes a gate region and a source region;
an inner BSSCCR of the second conductivity type, wherein the inner BSSCCR extends adjacent a periphery of the plurality of parallel-extending BSSCCRs, wherein the inner BSSCCR is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered by semiconductor material of the first conductivity type of the second epitaxial semiconductor layer;
an outer BSSCCR of the second conductivity type, wherein the outer BSSCCR extends parallel to the inner BSSCCR such that the inner BSSCCR is disposed between the outer BSSCCR and the plurality of parallel-extending BSSCCRs, wherein the outer BSSCCR is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered by semiconductor material of the first conductivity type of the second epitaxial semiconductor layer;
a first surface region of the second conductivity type, wherein the first surface region is disposed at the upper semiconductor surface of the die structure;
a second surface region of the second conductivity type, wherein the second surface region extends parallel to the first surface region at the upper semiconductor surface of the die structure, and wherein the second surface region is floating and is stripe-shaped;
a third surface region of the second conductivity type, wherein the third surface region extends parallel to the second surface region at the upper semiconductor surface of the die structure such that the second surface region is disposed between the first and third surface regions, wherein the third surface region is stripe-shaped; and
a metal bridging member that electrically couples the first and third surface regions together, wherein the metal bridging member bridges over the second surface region but does not contact the second surface region, and wherein the metal bridging member is disposed at least in part over the inner BSSCCR.

US Pat. No. 10,062,686

REVERSE BIPOLAR JUNCTION TRANSISTOR INTEGRATED CIRCUIT

IXYS, LLC, Milpitas, CA ...

1. An integrated circuit comprising:a first metal electrode;
a second metal electrode;
a third metal electrode;
a bipolar transistor, wherein a base of the bipolar transistor is coupled to the second metal electrode, wherein the base is separated from the first metal electrode by a plurality of insulation features, wherein the bipolar transistor has an emitter-to-base reverse breakdown voltage of at least 156 volts, and wherein the bipolar transistor has an emitter-to-collector reverse breakdown voltage of at least 156 volts; and
a distributed parallel diode, wherein a first electrode of the distributed parallel diode is coupled to a collector of the bipolar transistor and is also coupled to the first metal electrode, wherein a second electrode of the distributed parallel diode is coupled through substrate material to an emitter of the bipolar transistor and is also coupled to the third metal electrode, wherein the collector of the bipolar transistor extends into and is surrounded by the base, and wherein the first electrode of the distributed parallel diode is separated from the base by the insulation features.

US Pat. No. 10,014,852

HIGH-VOLTAGE STACKED TRANSISTOR CIRCUIT

IXYS, LLC, Milpitas, CA ...

1. An apparatus comprising:a first field effect transistor (FET);
a second FET having a source that is coupled to a drain of the first FET;
a third FET having a source that is coupled to a drain of the second FET;
a first bipolar transistor having a collector that is coupled to the drain of the first FET;
a second bipolar transistor having a collector that is coupled to the drain of the second FET;
a first diode having a cathode that is coupled to an emitter of the first bipolar transistor;
a second diode having a cathode that is coupled to an emitter of the second bipolar transistor, wherein an anode of the second diode is coupled to an anode of the first diode;
a first resistor coupled between the anode of the first diode and a gate of the first FET;
a third diode coupled between a base of the first bipolar transistor and a source of the first FET; and
a fourth diode coupled between a base of the second bipolar transistor and the source of the second FET.

US Pat. No. 10,193,000

FAST RECOVERY INVERSE DIODE

IXYS, LLC, Milpitas, CA ...

1. A power semiconductor device die having a top semiconductor surface, a bottom semiconductor surface, and peripheral side edges, the die comprising:a bottomside P type silicon region that extends upward from the bottom semiconductor surface of the die that also extends laterally outwardly to the peripheral side edges of the die, wherein the bottomside P type silicon region has a P type dopant concentration of less than 8×1017 atoms/cm3;
an N? type silicon region disposed over the bottomside P type silicon region;
an N+ type silicon contact region that extends downward from the top semiconductor surface and into the N? type silicon region;
a P type silicon peripheral sidewall region that extends laterally inwardly from the peripheral side edges of the die and laterally rings the N? type silicon region, wherein the P type silicon peripheral sidewall region joins the bottomside P type silicon region thereby forming a P type isolation structure, and wherein each of the N? type silicon region, the N+ type silicon contact region, the P type silicon peripheral sidewall region, and the bottomside P type silicon region is of bulk silicon wafer material;
a topside passivation layer disposed over a part of the top semiconductor surface of the die, wherein the topside passivation layer is disposed over the P type silicon peripheral sidewall region and rings around the N+ type silicon contact region;
a deep layer of hydrogen ions that has a distribution disposed about a hydrogen ion local concentration peak surface, wherein the hydrogen ion local concentration peak surface is a planar surface that extends in a plane parallel to the bottom semiconductor surface, and wherein the hydrogen ion local concentration peak surface extends through the N? type silicon region but does not extend through the bottomside P type silicon region;
a shallow layer of ions that has a distribution disposed about an ion local concentration peak surface, wherein the ion local concentration peak surface is a planar surface that extends in a plane parallel to the bottom semiconductor surface, wherein the ion local concentration peak surface extends through the bottomside P type silicon region but does not extend through the N? type silicon region, and wherein the ions of the shallow layer of ions are ions taken from the group consisting of hydrogen ions and helium ions;
a topside metal electrode disposed on the N+ type silicon contact region; and
a bottomside metal electrode disposed on the bottom semiconductor surface of the die.

US Pat. No. 10,153,716

COMPENSATION FOR ASYMMETRIES IN ELECTRODYNAMICS OF BLDC TYPE MACHINES USING HALL SENSORS

IXYS, LLC, Milpitas, CA ...

1. A method comprising:(a) in response to a change in a Hall sensor state value using a Hall sensor state value to select one of a plurality of reference phase angle values thereby generating a selected reference phase angle value;
(b) supplying the selected reference phase angle value as a Lookup Table (LUT) input value to a Pulse Width Modulation (PWM) sine wave LUT thereby causing the PWM sine wave LUT to output a PWM input value;
(c) supplying the PWM input value to a pulse width modulator circuit thereby causing the pulse width modulator circuit to generate a pulse width modulated switch control signal, wherein the pulse width modulated switch control signal is used to control a transistor, wherein the transistor switches a current that flows through a winding of a motor;
(d) repeating steps (a), (b) and (c) as the motor operates over a first period of time so that one by one each of the reference phase angle values is selected in (a);
(e) detecting a magnitude of a motor current during the first period of time thereby generating a first current value;
(f) repeating steps (a), (b), (c) and (d) as the motor operates over a second period of time, wherein during the second period of time at least one of the reference phase angle values has been adjusted as compared to its value during the first period of time;
(g) detecting a magnitude of the motor current during the second period of time thereby generating a second current value;
(h) based at least in part on the first current value and the second current value determining a plurality of reference phase angle values which when used in the steps (a), (b), (c) results in a motor operation;
(i) switching from a calibration mode to a normal operating mode, wherein steps (a)-(h) occur in the calibration mode; and
(j) during the normal operating mode using the determined plurality of reference phase angle values determined in (h), wherein the determined plurality of reference phase angle values are used in the normal operating mode to generate a pulse width modulation signal that in turn is used to control the transistor so that the transistor switches the current that flows through the winding of the motor.

US Pat. No. 10,069,485

HIGH-SPEED MOSFET AND IGBT GATE DRIVER

IXYS, LLC, Milpitas, CA ...

1. A gate driver integrated circuit comprising:an input terminal that receives a digital input signal, wherein the digital input signal has a digital logic high level during a first period of time and transitions to a digital logic low level so that the digital input signal has a digital logic low level during a second period of time, and wherein the digital input signal does not transition digital logic levels between the second period of time and a third period of time such that the digital input signal maintains the digital logic low level into and throughout the third period of time;
an output terminal;
a positive supply voltage terminal, wherein a positive supply voltage is received onto the positive supply voltage terminal, wherein the positive supply voltage is greater than any voltage of the digital input signal as received onto the input terminal;
a ground terminal;
an active pullup circuit that couples the output terminal to the positive supply voltage terminal during the first period of time;
an active pulldown circuit that drives the output terminal to a negative voltage during the second period of time in response to the digital input signal on the input terminal transitioning from the digital logic high level to the digital logic low level; and
an active grounding circuit that couples the output terminal to the ground terminal during the third period of time while the digital logic low level is still present on the input terminal, wherein the active pulldown circuit comprises a delay circuit, and wherein the delay circuit outputs a signal that determines when the active pulldown circuit stops driving the output terminal to the negative voltage and when the active grounding circuit begins coupling the output terminal to the ground terminal.

US Pat. No. 10,249,716

IGBT ASSEMBLY HAVING SATURABLE INDUCTOR FOR SOFT LANDING A DIODE RECOVERY CURRENT

IXYS, LLC, Milpitas, CA ...

1. A method of manufacture comprising:depositing a volume of a liquid in an immediate vicinity of a conductor, wherein the liquid contains ferromagnetic particles, wherein the conductor is a part of an electronic device assembly;
causing the liquid to solidify so that the conductor and the solidified liquid together form a saturable inductor structure, wherein the saturable inductor structure has an unsaturated inductance of at least 200 nH, wherein the saturable inductor structure has a saturated inductance that is smaller than the unsaturated inductance, and wherein the solidified liquid holds the ferromagnetic particles in place with respect to the conductor; andassembling the saturable inductor structure, a diode and an insulated-gate bipolar transistor (IGBT) such that the diode and the saturable inductor structure are coupled in series between an emitter of the IGBT and a collector of the IGBT.

US Pat. No. 10,217,847

POWER TRANSISTOR WITH INCREASED AVALANCHE CURRENT AND ENERGY RATING

IXYS, LLC, Milpitas, CA ...

1. A method comprising:(a) forming a drift region;
(b) forming a body region which extends down into the drift region from a first upper semiconductor surface, wherein the first upper semiconductor surface extends in a first plane, wherein the body region meets the drift region at a body-to-drift boundary, wherein the body-to-drift boundary has a central portion, wherein the central portion of the body-to-drift boundary is non-planar, and wherein the drift region forms a central ridge that extends upward toward the first upper semiconductor surface; and
(c) forming a source region which extends down into the body region from a second upper semiconductor surface, wherein the second upper semiconductor surface extends in a second plane, wherein a maximum depth of the source region is not greater than a distance between the first plane and the second plane, and wherein the first upper semiconductor surface and the second upper semiconductor surface are not coplanar.

US Pat. No. 10,164,124

FAST RECOVERY INVERSE DIODE

IXYS, LLC, Milpitas, CA ...

1. A power semiconductor device die having a top semiconductor surface, a bottom semiconductor surface, and peripheral side edges, the die comprising:a bottomside P type silicon region that extends upward from the bottom semiconductor surface of the die that also extends laterally outwardly to the peripheral side edges of the die, wherein the bottomside P type silicon region has a P type dopant concentration of less than 8×1017 atoms/cm3;
an N? type silicon region disposed over the bottomside P type silicon region;
an N+ type silicon contact region that extends downward from the top semiconductor surface and into the N? type silicon region;
a P type silicon peripheral sidewall region that extends laterally inwardly from the peripheral side edges of the die and laterally rings the N? type silicon region, wherein the P type silicon peripheral sidewall region joins the bottomside P type silicon region thereby forming a P type isolation structure, and wherein each of the N? type silicon region, the N+ type silicon contact region, the P type silicon peripheral sidewall region, and the bottomside P type silicon region is of bulk silicon wafer material;
a topside passivation layer disposed over a part of the top semiconductor surface of the die, wherein the topside passivation layer is disposed over the P type silicon peripheral sidewall region and rings around the N+ type silicon contact region;
a deep layer of hydrogen ions that has a distribution disposed about a hydrogen ion local concentration peak surface, wherein the hydrogen ion local concentration peak surface is a planar surface that extends in a plane parallel to the bottom semiconductor surface, and wherein the hydrogen ion local concentration peak surface extends through the N? type silicon region but does not extend through the bottomside P type silicon region;
a shallow layer of ions that has a distribution disposed about an ion local concentration peak surface, wherein the ion local concentration peak surface is a planar surface that extends in a plane parallel to the bottom semiconductor surface, wherein the ion local concentration peak surface extends through the bottomside P type silicon region but does not extend through the N? type silicon region, and wherein the ions of the shallow layer of ions are ions taken from the group consisting of hydrogen ions and helium ions;
a topside metal electrode disposed on the N+ type silicon contact region; and
a bottomside metal electrode disposed on the bottom semiconductor surface of the die.

US Pat. No. 10,276,472

HEAT TRANSFER PLATE HAVING SMALL CAVITIES FOR TAKING UP A THERMAL TRANSFER MATERIAL

IXYS, LLC, Milpitas, CA ...

1. A power semiconductor device module comprising:a semiconductor device die; and
a Direct Metal Bonded (DMB) substrate comprising:
an insulative ceramic sheet member;
a top metal plate that is directly bonded to a top surface of the insulative ceramic sheet member, wherein the semiconductor device die is attached to the top metal plate; and
a bottom metal plate that is directly bonded to a bottom surface of the insulative ceramic sheet member; and
a metal baseplate having a substantially planar metal surface, wherein the substantially planar metal surface forms an outside surface of the power semiconductor device module, wherein the metal baseplate has a plurality of cavities each of which extends into the metal baseplate from the substantially planar metal surface, wherein the metal baseplate is in thermal contact with the bottom metal plate, wherein an A by A square area of the metal baseplate includes at least a part of each of B of the cavities, wherein each of the B cavities of the A by A square area has a minimum inside width dimension that is not more than C millimeters across, wherein each of the B cavities has a depth that is less than D millimeters, and wherein the A by A square area of the metal baseplate has an aggregate cavity volume of between E cubic millimeters and F cubic millimeters;
wherein A is 10.0 millimeters, wherein B is ten, wherein C is 1.0 millimeters, wherein D is 0.5 millimeters, wherein E is 0.001 cubic millimeters, and wherein F is 10.0 cubic millimeters.

US Pat. No. 9,473,074

CHOPPER STABILIZED AMPLIFIER WITH SYNCHRONOUS SWITCHED CAPACITOR NOISE FILTERING

IXYS Corporation, Milpit...

1. An apparatus comprising:
a chopper amplifier having an input that receives an input signal and an output that outputs an amplified signal, the chopper
amplifier includes an input chopping circuit coupled to the input and an output chopping circuit coupled to the output, the
input and output chopping circuits operate in response to a chop clock;

a switched capacitor filter having an input that receives the amplified signal and an output that outputs a filtered signal,
the switched capacitor filter operates in response to at least one filter clock; and

a filter timing adjuster having an input to receive a reference voltage and the chop clock, and an output to output the at
least one filter clock, the filter timing adjuster adjusts a phase of the at least one filter clock with respect to the chop
clock to reduce chopper noise on the reference voltage.