US Pat. No. 9,299,563

METHOD FOR FORMING A STRAINED SEMICONDUCTOR STRUCTURE

IMEC VZW, Leuven (BE) Sa...

1. A method for forming a strained semiconductor structure comprising: providing a strain relaxed buffer layer; forming a
sacrificial layer on the strain relaxed buffer layer, wherein the sacrificial layer is a separate layer formed on the strain
relaxed buffer layer; after forming the sacrificial layer, forming a shallow trench isolation structure through the sacrificial
layer; removing at least a portion of an oxide layer on the sacrificial layer; etching through the sacrificial layer such
that a portion of the strain relaxed buffer layer is exposed; and growing the strained semiconductor structure on the exposed
portion of the strain relaxed buffer layer.

US Pat. No. 9,068,891

METHOD AND APPARATUS FOR MEASURING CONCENTRATION OF BIOGENIC SUBSTANCE

PANASONIC CORPORATION, O...

1. A method for measuring a concentration of a biogenic substance, comprising steps of:
(a) preparing an apparatus for biogenic substance concentration measurement,
said apparatus comprising a light source, a polarization controller which controls a polarization of the light from said light
source, a substrate which has periodic metal structures and generates surface enhanced Raman scattering light by being irradiated
with light emitted from said light source, and spectroscopic means which disperses and detects said surface enhanced Raman
scattering light, wherein

said periodic metal structure is arranged with a first distance in a first direction and with a second distance in a second
direction,

said first distance is set to generate surface plasmon by matching a phase of the light emitted by said light source, and
said second distance is smaller than said first distance and the second distance is set between 300 nm and 350 nm;
(b) irradiating the substrate with the light emitted from the light source so as to generate the surface enhanced Raman scattering,
wherein the polarization of said light is controlled along with said first direction by said polarization controller;

(c) detecting said generated surface enhanced Raman scattering with said spectroscopic means;
(d) recording an intensity of said surface enhanced Raman scattering detected in step (c);
(e) irradiating the substrate with the light emitted from the light source so as to generate the surface enhanced Raman scattering,
wherein the polarization of said light is changed by said polarization controller;

(f) detecting said generated surface enhanced Raman scattering at said step (e) with said spectroscopic means;
(g) recording an intensity of said surface enhanced Raman scattering detected in step (f);
(h) determining a larger intensity of surface enhanced Raman scattering and recording said larger intensity by comparing the
recorded intensity of the surface enhanced Raman scattering at said step (g) with the recorded intensity of the surface enhanced
Raman scattering at step (d);

(i) calculating the maximum intensity of surface enhanced Raman scattering by repeating the steps of (e) to (h);
(j) calculating the concentration of the biogenic substance on the basis of said maximum intensity of surface enhanced Raman
scattering calculated in said step (i).

US Pat. No. 9,384,990

TITANIUM NITRIDE ELECTRODE

IMEC VZW, Leuven (BE)

1. A method for decreasing the impedance of a titanium nitride element for use in an electrode component, the method comprising:
obtaining a titanium nitride element; and
hydrothermally treating the titanium nitride element by immersing the titanium nitride element in an acidic aqueous solution
or an alkaline aqueous solution while heating said aqueous solution for a predetermined time,

wherein impedance of the titanium nitride element is decreased by a factor between 5 and 100 following the hydrothermal treatment,
wherein the acidic aqueous solution is selected from a hydrogen chloride aqueous solution and a sulphuric acid aqueous solution,
and

wherein the alkaline aqueous solution is selected from a sodium hydroxide aqueous solution and an ammonium hydroxide aqueous
solution.

US Pat. No. 9,406,777

METHOD FOR MANUFACTURING A TRANSISTOR DEVICE

IMEC VZW, Leuven (BE) Sa...

1. A method for manufacturing a transistor device comprising a channel layer, said method comprising:
providing a substrate;
epitaxially growing a strained layer on said substrate;
epitaxially growing said channel layer on said epitaxially grown strained layer;
providing a first gate structure on said channel layer;
selectively etching into said channel layer and at least partially in said epitaxially grown strained layer, thereby using
said first gate structure as a mask, and thereby creating a protrusion extending from said substrate, said protrusion comprising
a portion of said channel layer and at least an upper portion of said epitaxially grown strained layer, allowing elastic relaxation
in said portions;

epitaxially growing source and drain structures directly adjacent to said protrusion and at opposed sides of the protrusion;
and

after epitaxially growing said source and drain structures directly adjacent to said protrusion, replacing said first gate
structure by a second gate structure.

US Pat. No. 9,391,141

METHOD FOR PRODUCING FIN STRUCTURES OF A SEMICONDUCTOR DEVICE IN A SUBSTRATE

IMEC VZW, Leuven (BE)

1. A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor
substrate, comprising:
providing a semiconductor substrate covered with a shallow trench isolation layer stack on a side thereof;
providing a patterned hard mask layer on the shallow trench isolation layer stack, wherein a pattern of the patterned hard
mask layer corresponds to a fin area on the side of the substrate, wherein the fin structures will be produced in the fin
area;

embedding the hard mask layer in a planarizing filling layer;
providing a DSA layer stack on the planarizing filling layer, and patterning the DSA layer stack into a striped pattern;
patterning the planarizing filling layer and the hard mask layer into a striped pattern using DSA lithographic patterning;
etching the STI layer stack and the substrate in between stripes of the striped pattern of the patterned hard mask layer,
thereby defining the fin structures, wherein the fin structures are separated by trenches;

filling the trenches with a second filling layer; and
performing a surface flattening step on the second filling layer in order to remove excess material of the second filling
layer, thereby exposing the STI layer stack and arriving at a flattened surface.

US Pat. No. 9,324,818

GATE-ALL-AROUND SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

IMEC VZW, Leuven (BE)

1. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate formed of a first crystalline semiconductor material;
forming a plurality of shallow trench isolation (STI) regions in the semiconductor substrate;
forming a plurality of semiconductor fins interposed between a pair of adjacent STI regions and extending in a first lateral
direction, each of the semiconductor fins comprising a second crystalline semiconductor material lattice mismatched to the
first crystalline semiconductor material, each semiconductor fin being separated from an adjacent fin by one of the STI regions;

providing at least one nanostructure formed of a third crystalline semiconductor material on the second crystalline semiconductor
material of each semiconductor fin, the at least one nanostructure extending in the first lateral direction;

providing a sacrificial gate on the at least one nanostructure;
providing on the at least one nanostructure a source region and a drain region separated in the first lateral direction from
the source region by the sacrificial gate;

removing the sacrificial gate and further removing the second crystalline semiconductor material, thereby suspending the at
least one nanostructure being anchored by the source and drain region; and

providing a final gate stack surrounding the at least one nanostructure after removing the second crystalline semiconductor
material.

US Pat. No. 9,174,211

MICROSTRUCTURED MICROPILLAR ARRAYS FOR CONTROLLABLE FILLING OF A CAPILLARY PUMP

IMEC VZW, Leuven (BE)

1. A micro-fluidic device comprising:
a substrate;
a cavity in the substrate; and
a plurality of micro-pillar columns located in the cavity;
wherein the plurality of micro-pillar columns is configured to create a capillary action when a fluid sample is provided in
the cavity,

wherein a micro-fluidic channel is present between two walls of any two adjacent micro-pillars in a same micro-pillar column,
wherein each of the two walls comprises a sharp corner along a direction of a propagation path of the fluid sample in the
micro-fluidic channel thereby forming a first capillary stop valve,

and wherein each micro-pillar column includes a notch located in a sidewall of the cavity, wherein the notch is provided adjacent
to a micro-pillar located at one edge of each micro-pillar column, wherein the notch in conjunction with the micro-pillar
located at that one edge of each micro-pillar column functions as a second capillary stop valve, and wherein each notch of
each adjacent micro-pillar column is located in an opposite sidewall of the cavity.

US Pat. No. 9,068,950

VERNIER PHOTONIC SENSOR DATA-ANALYSIS

UNIVERSITEIT GENT, Ghent...

1. A method for quantifying an effective refractive index change in a photonic sensor the method comprising the steps of:
obtaining spectral data representative for an optical signal being modulated with an optical transfer characteristics of the
photonic sensor, the modulation being obtained by combining modulation of a first electromagnetic wave component in a optical
filter element with a first periodic transfer spectrum having a first free spectral range and modulation of a second electromagnetic
wave component in an optical filter element with a second periodic transfer spectrum having a second free spectral range being
different from the first free spectral range, wherein a relative change is induced in the second periodic transfer spectrum
with respect to the first periodic transfer spectrum as a result of changing environmental conditions or conformational changes
of the photonic sensor, and

quantifying the effective refractive index change of the photonic sensor taking into account said spectral data,
wherein said quantifying comprises determining a wavelength offset of an envelope signal applied to the spectral data, the
envelope signal having a wavelength periodicity substantially larger than a periodicity of the first periodic transfer spectrum
and the second periodic transfer spectrum.

US Pat. No. 9,437,681

DUAL CHANNEL FINFET CMOS DEVICE WITH COMMON STRAIN-RELAXED BUFFER AND METHOD FOR MANUFACTURING THEREOF

IMEC VZW, Leuven (BE) Sa...

1. A CMOS device comprising
a semiconductor substrate,
a patterned strain-relaxed buffer layer of fins comprising silicon germanium (SiGe) on the semiconductor substrate;
on the patterned strain-relaxed buffer layer, an nFinFET having an n-channel region and a pFinFET having a p-channel region,
both channel regions isolated from each other by an isolation region and comprising germanium (Ge) whereby the concentration
of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer;

source/drain regions comprising SiGe for the nFinFET; and
source/drain regions comprising Ge for the pFiNFET.

US Pat. No. 9,224,448

NANO-ELECTRO-MECHANICAL BASED MEMORY

IMEC vzw, Leuven (BE) Ka...

1. A memory arrangement comprising a plurality of cells arranged in an array structure, wherein each cell comprises:
a memory element and a read selector in series, the memory element being a nano-electro-mechanical switch comprising an anchor,
a beam fixed to the anchor, a first control gate, and a second control gate, for controlling the position of the beam, a first
output node against which the beam can be positioned, the read selector comprising a first selector terminal, a second selector
terminal, the first selector terminal connected to the first output node,

wherein first control gates of nano-electro-mechanical switches belonging to a same word are connected together by a first
write word line serving as control gate, and second control gates of nano-electro-mechanical switches belonging to a same
word are connected together by a second write word line serving as control gate.

US Pat. No. 9,369,317

CIRCUITRY AND METHOD FOR MULTI-LEVEL SIGNALS

IMEC VZW, Leuven (BE) Un...

1. Circuitry for converting a multi-level signal into at least one binary signal, the multi-level signal having a period T
and comprising n signal levels, n being equal to or greater than 3, comprising:
comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n?1) different reference
values, and having N sets of (n?1) output terminals for outputting N sets of (n?1) output signals, each set of (n?1) output
signals indicating whether the value of the multi-level signal is below or above the (n?1) reference values, wherein N is
greater than or equal to 2;

N sets of (n?1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period
N*T, each set of the N sets being arranged for sampling-and-holding at moments in time that are shifted in time with respect
to another set of the N sets, wherein each output terminal of a set of the N sets of (n?1) output terminals is connected to
the input of a sample-and-hold circuit of a corresponding set of the N sets of (n?1) sample-and-hold circuits; and

logical circuitry connected to the outputs of the N sets of (n?1) sample-and-hold circuits for generating at least one binary
signal having a period N*T, using the signals on the outputs of the N sets of (n?1) sample-and-hold circuits.

US Pat. No. 9,146,235

INTEGRATED FLUORESCENCE DETECTION

IMEC VZW, Leuven (BE)

13. A method for detecting fluorescent radiation from fluorescent particles, the method comprising:
providing an interaction between a sample comprising fluorescent particles and a sensing layer;
providing an excitation radiation beam for exciting fluorescent particles accommodated on the sensing layer; and
guiding the excitation radiation away from a detection element by diffracting the excitation radiation in a lateral direction
using a photonics crystal, the photonics crystal comprising an absorption material arranged to cause the photonics crystal
to diffract the incident excitation radiation into the lateral direction in which the photonics crystal extends when the incident
excitation radiation has a wavelength within at least 10 nm of a predetermined excitation wavelength.

US Pat. No. 9,087,849

ELECTROSTATIC DISCHARGE PROTECTION DEVICES

IMEC VZW, Leuven (BE)

1. An electrostatic discharge protection device, comprising:
an anode and a cathode;
a first region having a first doped area of a first dopant type, a second doped area of a second dopant type and a first part
of a third doped area of the first dopant type, the first region being a well region of the first dopant type, a first node
of the device being defined by the first and second doped areas;

a second region comprising a fourth doped area of the first dopant type, a fifth doped area of the second dopant type, and
a second part of the third doped area connecting the first part of the third doped area to the fourth doped area, a second
node of the device being defined by the fourth and fifth doped areas,

wherein one of the first and second nodes is configured as one of the anode and the cathode, and wherein the other of the
first and second nodes is configured as the other of the anode and the cathode; and

a grounded-gate metal oxide semiconductor structure having a gate formed over the second part of the third area and an avalanche
zone in the locality of the gate, the first and second nodes being interposed by the gate extending in a first lateral direction,

wherein the grounded-gate metal oxide semiconductor structure comprises a bulk fin-based transistor structure including, in
the second part of the third doped area, a plurality of fin elements isolated from each other in the first lateral direction
by a plurality of shallow trench isolation structures.

US Pat. No. 9,373,519

METHOD TO PATTERN SUBSTRATES

IMEC VZW, Leuven (BE)

1. A method for creating a pattern on a substrate, the method comprising
providing a substrate comprising silicon;
creating a sacrificial layer on the substrate, wherein the sacrificial layer is formed on a first surface area of the substrate
thereby leaving a second surface area exposed;

depositing a first functional layer at least on the second surface area of the substrate;
removing the sacrificial layer;wherein the substrate comprises a biosensing region underlying and in contact with the sacrificial layer and removing the
sacrificial layer is performed by etching the sacrificial layer with an acidic solution that does not adversely affect the
first functional layer and the substrate.

US Pat. No. 9,123,859

MODULE-LEVEL PROCESSING OF SILICON PHOTOVOLTAIC CELLS

IMEC VZW, Leuven (BE)

1. A method for module-level processing of photovoltaic cells, the method comprising:
(a) bonding at least one crystalline silicon photovoltaic substrate to a carrier by means of an adhesive layer, wherein the
adhesive layer is present on a surface of the carrier, wherein part of the adhesive layer remains uncovered after the bonding,
and wherein the at least one crystalline silicon photovoltaic substrate has a front side and a rear side; and

(b) exposing the uncovered part of the adhesive layer and the at least one crystalline silicon photovoltaic substrate to a
plasma; and

(c) removing a surface portion of the at least one crystalline photovoltaic substrate.

US Pat. No. 9,124,251

TWO STAGE SOURCE-FOLLOWER BASED FILTER

IMEC VZW, Leuven (BE) Un...

1. A filter comprising:
two source-follower stages connected in series and in-between an input node and an output node, wherein an inner node connects
the two source-follower stages;

a frequency dependent feedback circuit connected between the input node and the output node;
a first additional frequency dependent feedback circuit connected between the input node and the inner node; and
a second additional frequency dependent feedback circuit connected between the output node and the inner node,
wherein the filter has a transfer function with at least two zeroes and at least two poles, and wherein the first additional
frequency dependent feedback circuit and the second additional frequency dependent feedback circuit define each of the at
least two poles and each of the at least two zeroes independently of one another.

US Pat. No. 9,455,647

ELECTRET ELEMENT AND VIBRATION POWER GENERATING DEVICE USING THE SAME

PANASONIC CORPORATION, O...

1. An electret element comprising a substrate, an electrically-conductive electrode, and an electret layer comprising a first
dielectric layer and a second dielectric layer, wherein:
the electret layer is capable of holding electrical charge;
the electrically-conductive electrode is on a surface of the substrate;
the first dielectric layer is on a surface of the electrically-conductive electrode and has, in a surface opposite to an electrically-conductive
electrode-side surface, at least one concave portion having a bottom face, a side wall and a top face;

the second dielectric layer covers the entirety of the bottom face and at least a part of the side wall; and
a bottom Ec of a conductive band of the second dielectric layer is lower than a bottom Ec of a conductive band of the first
dielectric layer, or a top Ev of a valence band of the second dielectric layer is higher than a top Ev of a valence band of
the first dielectric layer, wherein

a thickness of the first dielectric layer between the bottom face and the surface of the electrically-conductive electrode
is thinner than a thickness of the first dielectric layer between the top face and the surface of the electrically-conductive
electrode.

US Pat. No. 9,406,820

METHOD FOR FABRICATING PHOTOVOLTAIC CELLS WITH PLATED CONTACTS

IMEC vzw, Leuven (BE) Ka...

1. A method of fabricating a photovoltaic cell with a metal contact pattern on a surface of a semiconductor substrate, the
method comprising:
locally smoothening portions of the surface of a bulk semiconductor material of the semiconductor substrate at predetermined
locations by using a first laser to form locally smoothened surfaces;

after locally smoothening, doping the surface of the semiconductor substrate the underlying surface of the semiconductor substrate
to form an emitter region;

after doping the surface, forming a dielectric layer on the surface of the semiconductor substrate;
forming openings through the dielectric layer by using a second laser, thereby locally exposing the locally smoothened surfaces
at the predetermined locations; and

forming the metal contact pattern contacting the locally smoothened surfaces by plating.

US Pat. No. 9,379,798

MODULATION CIRCUIT FOR A RADIO DEVICE AND A METHOD THEREOF

IMEC VZW, Leuven (BE)

1. A circuit comprising:
a first signal path comprising a first mixer, wherein the first mixer is configured to modulate a baseband signal with a local
oscillator signal to provide a first radio-frequency signal, wherein the first mixer is configured to receive (i) the baseband
signal at a non-linear input and (ii) the local oscillator signal at a linear input;

a second signal path comprising a delay circuit and a second mixer, wherein the delay circuit is configured to delay the baseband
signal by a delay time, and wherein the second mixer is configured to modulate the delayed baseband signal with the local
oscillator signal to provide a second radio-frequency signal, wherein the second mixer is further configured to receive (i)
the delayed baseband signal at a non-linear input and (ii) the local oscillator signal at a linear input; and

an adder circuit configured to combine the first radio-frequency signal and the second radio-frequency signal to provide an
output radio-frequency signal.

US Pat. No. 9,432,225

TEST CIRCUITS

IMEC VZW, Leuven (BE) Un...

1. A feed forward equalizer circuit comprising:
an input port for receiving an input signal;
a first line connected to the input port;
an output port for providing an output signal;
a second line connected to the output port;
a first tap element connected between the first line and the second line at respective line nodes;
at least one second tap element connected between the first line and the second line at respective line nodes;
at least one first delay element connected to the first line between the first tap element and the at least one second tap
element;

at least one second delay element connected to the second line between the at least one second tap element and the first tap
element;

a test input port connected to the first line and a test output port connected to the second line, and wherein the test input
port and the test output port are respectively connected to first and second line nodes associated with the at least one second
tap element.

US Pat. No. 9,431,519

METHOD OF PRODUCING A III-V FIN STRUCTURE

IMEC VZW, Leuven (BE) So...

1. A method for producing a III-V fin structure within a gap separating shallow trench isolation (STI) structures and exposing
a semiconductor substrate, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is a Si substrate;
providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor
substrate, wherein the gap is bounded by the at least two identical STI structures, wherein the at least two STI structures
are SiO2;

producing a III-V fin structure within the gap on the exposed semiconductor substrate using a Metal Organic Vapor Phase Epitaxy
(MOVPE) process; and

providing a diffusion barrier at least in contact with each side wall of the at least two identical STI structures and with
side walls of the III-V fin structure, wherein the diffusion barrier is an oxide comprising a metal silicate, and wherein
providing the diffusion barrier further comprises depositing the metal using Molecular Beam Epitaxy (MBE) and subsequently
performing a thermal anneal process, thereby forming the metal silicate.

US Pat. No. 9,246,117

MODULATABLE LIGHT-EMITTING DIODE

Nederlandse Organisatie v...

1. Light-emitting diode comprising (a) an anode electrode layer; (b) a cathode electrode layer; and, in contact with said
electrode layers, (c) a light emitting layer, which separates the electrode layers from each other, comprising (d) an electroluminescent
semiconducting material, wherein the light-emitting layer comprises a blend of the electroluminescent semiconducting material
with (e) a ferro-electric material, and wherein either or both of the electrodes forms a modulatable injection barrier with
the ferroelectric material, the modulation requiring a voltage Vm, and wherein Vm is larger than the voltage Ve required for light emission.

US Pat. No. 9,261,648

PLASMONIC WAVELENGTH SELECTIVE SWITCH

IMEC VZW, Leuven (BE)

1. A plasmonic structure comprising:
a substrate; and
at least one electro conductor provided in or on the substrate, wherein the at least one electro conductor includes a first
part configured to provide a first series of plasmon resonance modes for incident radiation of a first wavelength, and a second
part configured to provide a second series of plasmon resonance modes for incident radiation of a second wavelength, wherein
the first part and second part being functionally connected in a linkage region,

wherein the electro conductor being shaped in the linkage region such as to form a capacitive gap,
wherein the electro conductor is further configured to direct radiation incident on the plasmonic structure of the first wavelength
predominantly toward a first direction and to direct radiation incident on the plasmonic structure of the second wavelength
predominantly toward a second direction, and wherein the first direction and the second direction being separated by an angle
of at least 60°.

US Pat. No. 9,337,380

METHOD FOR FABRICATING HETEROJUNCTION INTERDIGITATED BACK CONTACT PHOTOVOLTAIC CELLS

IMEC VZW, Leuven (BE)

1. A method of forming on a substrate a patterned n+ a-Si:H layer and a patterned p+ a-Si:H layer, the patterned n+ a-Si:H layer and the patterned p+ a-Si:H layer being interdigitated and electrically isolated from each other, the method comprising:
forming a patterned p+ a-Si:H layer on the substrate, the patterned p+ a-Si:H layer covering first regions of the substrate surface and leaving second regions of the substrate surface exposed;

depositing a first intrinsic a-Si:H layer on the substrate;
depositing an n+ a-Si:H layer on the first intrinsic a-Si:H layer;

providing a patterned masking layer covering the n+ a-Si:H layer at least in the second regions; and

selectively removing the n+ a-Si:H layer and the first intrinsic a-Si:H layer in regions not covered by the masking layer and stopping at an underlying
portion of the p+ a-Si:H layer without removing a substantial amount of the underlying portion of the p+ a-Si:H layer,

wherein selectively removing the n+ a-Si:H layer and the first intrinsic a-Si:H layer comprises etching in a solution comprising a diluted tetramethylammonium
hydroxide (TMAH) solution.

US Pat. No. 9,502,415

METHOD FOR PROVIDING AN NMOS DEVICE AND A PMOS DEVICE ON A SILICON SUBSTRATE AND SILICON SUBSTRATE COMPRISING AN NMOS DEVICE AND A PMOS DEVICE

IMEC VZW, Leuven (BE)

1. A method of providing an nMOS device and a pMOS device on a silicon substrate, the method comprising:
providing trenches in a dielectric layer on the silicon substrate, the trenches including at least a first trench defining
an nMOS region and a second trench defining a pMOS region, the trenches extending through the dielectric layer and abutting
a surface of the substrate;

growing a first seed layer in the first trench on the surface;
growing a common strain-relaxed buffer layer in the first trench and in the second trench, the common strain-relaxed buffer
layer comprising silicon germanium (SiGe); and

growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed
buffer layer,

wherein the properties of the first seed layer and the common strained relaxed buffer layer are predetermined such that the
common channel layer is under a tensile strain or is unstrained in the nMOS region and is under a compressive strain in the
pMOS region.

US Pat. No. 9,318,583

TUNNEL FIELD EFFECT TRANSISTOR AND METHOD FOR MAKING THEREOF

IMEC VZW, Leuven (BE)

1. A vertical tunneling field effect transistor, comprising:
a vertical core region extending perpendicularly from a semiconductor substrate, the vertical core region having a top surface,
the vertical core region comprising a doped outer part and a middle part;

a vertical source region of a semiconducting core material comprising the doped outer part of the vertical core region;
a vertical drain region of a semiconducting drain material comprising along its longitudinal direction a first drain part
and a second drain part, the first drain part either directly surrounding the vertical source region or directly sandwiching
the vertical source region between two sub-parts of the first drain part, the second drain part located directly above and
in contact with the first drain part, wherein the vertical drain region comprises a doping type which is opposite to a doping
type of the vertical source region;

a gate dielectric layer directly aside of the first drain part of the vertical drain region;
a gate layer directly aside of the gate dielectric layer, the second drain part extending above the gate layer and gate dielectric
layer;

a drain contact directly connected to a third drain part, the third drain part being an upper part of the second drain part
of the vertical drain region;

a source contact electrically connected to the vertical source region;
a gate contact electrically connected to the gate layer; and
a buffer region in between the drain contact and the vertical source region, wherein the third drain part is located in direct
contact with and on top of the buffer region.

US Pat. No. 9,293,536

BILAYER GRAPHENE TUNNELING FIELD EFFECT TRANSISTOR

IMEC VZW, Leuven (BE)

1. A bilayer graphene tunnelling field effect transistor, comprising:
a bilayer graphene having a bottom surface and a top surface;
a bottom gate electrode capacitively coupled to the bottom surface of the bilayer graphene;
a first top gate electrode capacitively coupled to the top surface of the graphene bilayer; and
a second top gate electrode capacitively coupled to the top surface of the bilayer graphene and spaced apart along the top
surface from the first top gate electrode, whereby the bottom gate electrode fully overlaps the first top gate electrode and
the second top gate electrode, thereby defining a channel region capacitively coupled to the bottom gate electrode and the
first top gate electrode, a source region capacitively coupled to the second top gate electrode and the bottom gate electrode,
a barrier region only capacitively coupled to the bottom gate electrode, and a drain region only capacitively coupled to the
bottom gate electrode.

US Pat. No. 9,472,401

MOLYBDENUM DISULFIDE FILM FORMATION AND TRANSFER TO A SUBSTRATE

IMEC VZW, Leuven (BE)

1. A method for forming an unsupported MoS2 layer in an aqueous medium, comprising:
providing an assembly of a Mo oxide layer on a Si substrate;
annealing the assembly in a presence of H2S at a temperature sufficient to form an annealed MoS2 layer; and

contacting the annealed assembly with an aqueous medium, whereby an unsupported MoS2 layer is obtained.

US Pat. No. 9,520,298

PLASMA METHOD FOR REDUCING POST-LITHOGRAPHY LINE WIDTH ROUGHNESS

IMEC VZW, Leuven (BE)

1. A method for treating a photoresist structure on a substrate, the method comprising:
producing one or more resist structures on a substrate;
introducing the substrate in a plasma reactor; and
subjecting the substrate to a plasma treatment at a temperature of zero degrees Celsius or lower, and for a duration between
60 s and 180 s, to thereby limit reflow of the one or more resist structures and to limit shrinkage of a critical dimension
of the one or more resist structures to between 0% and 10%.

US Pat. No. 9,344,655

ACTIVE PIXEL SENSOR IMAGING SYSTEM

IMEC vzw, Leuven (BE)

1. An active pixel sensor imaging system, comprising:
a plurality of active pixel sensor circuits arranged into an array of rows and columns, at least one of said active pixel
sensor circuits being connected to a supply line and a column line and operable to generate a voltage output through the column
line corresponding to a detected light intensity;

a current sensing circuit, located external to the plurality of active pixel sensor circuits and connected to the supply line,
the current sensing circuit being implemented as a current mirror for sensing a current through an active pixel sensor circuit
readout transistor; and

a feedback circuit, located external to the plurality of active pixel sensor circuits and connected to the column line, to
a current generator and to the current sensing circuit, the feedback circuit being implemented as a classAB current mirror
configured for controlled quiescent current.

US Pat. No. 9,474,155

SUBMOUNT, ASSEMBLY INCLUDING SUBMOUNT, METHOD OF ASSEMBLING AND ASSEMBLING DEVICE

IMEC vzw, Leuven (BE) Ne...

1. A submount for mechanically and electrically coupling an electronic component to a carrier, the submount having a mounting
portion for mounting the submount to the carrier, having attachment portions for holding the electronic component, and having
primary electric contacts for cooperation with respective electrical conductors in the carrier, and secondary electric contacts
for cooperation with respective electric contacts of the electronic component, the secondary electric contacts being electrically
connected to primary electric contacts, wherein the attachment portions are coupled to the mounting portion by respective
extension portions that are laterally stretchable in a plane defined by the mounting portion to allow a displacement of the
attachment portions in a direction away from the mounting portion; wherein said respective attachment portions comprise a
gripping element and wherein said electronic component is attached to said attachment portion by stretching at least one of
said extension portions, arranging the electronic component upon said submount and allowing said at least one of said extension
portions to at least partially relax to therewith have the attachment portions grip into respective attachment portions of
said electronic component.

US Pat. No. 9,117,666

METHOD FOR ACTIVATING A POROUS LAYER SURFACE

IMEC VZW, Leuven (BG)

1. A method for enhancing the reactivity of an exposed surface of a porous dielectric layer, the method comprising:
providing a porous dielectric layer comprising a bulk part and an exposed surface, the bulk part comprising a bulk material
and pores;

filling the pores in a part of the porous dielectric layer with a first liquid, wherein the first liquid is an organic liquid,
and wherein the part of the porous dielectric layer comprises the exposed surface;

removing the first liquid selectively from the exposed surface by drying the surface or by rinsing the surface with a second
liquid, the second liquid being miscible with the first liquid and having a boiling point above 25° C.;

enhancing a reactivity of the exposed surface by contacting the exposed surface with a liquid solution configured to make
the exposed surface more reactive, wherein the liquid solution forms hydrophilic groups on the exposed surface, whereby an
activated exposed surface is formed;

removing the first liquid from the bulk part of the porous dielectric layer; and
depositing a sealing layer on the activated exposed surface of the porous dielectric layer.

US Pat. No. 9,406,503

DECREASING THE CRITICAL DIMENSIONS IN INTEGRATED CIRCUITS

IMEC VZW, Leuven (BE)

1. A method for lithographic patterning of a substrate, comprising:
providing a substrate to be patterned;
applying to the substrate a first thermally shrinkable metal-oxide layer;
etching the first thermally shrinkable metal-oxide layer to form a first metal-oxide pattern;
thermally shrinking the first metal-oxide pattern;
applying to the substrate a second thermally shrinkable metal-oxide layer;
etching the second thermally shrinkable metal-oxide layer to form a second metal-oxide pattern;
thermally shrinking the second metal-oxide pattern, wherein the thermally shrunk first and second metal-oxide patterns form
an overall pattern on the substrate; and

etching exposed areas of the substrate that are not covered by the overall pattern.

US Pat. No. 9,502,264

METHOD FOR SELECTIVE OXIDE REMOVAL

IMEC VZW, Leuven (BE)

1. A method for removing oxide selectively to a material comprising at least silicon and at least nitrogen, the method comprising:
(a) providing in a reactor a structure having a surface comprising a region, wherein said region comprises a material comprising
at least silicon and at least nitrogen;

(b) providing on said structure an oxide layer overlying at least a part of said region; and
(c) removing said oxide layer selective to said material by etching, thereby exposing at least a part of said at least overlaid
part of said region, wherein said etching is performed with an etchant gas comprising boron in the presence of a voltage bias
lower than 30 V that is applied to the structure.

US Pat. No. 9,105,746

METHOD FOR MANUFACTURING A FIELD EFFECT TRANSISTOR OF A NON-PLANAR TYPE

IMEC VZW, Leuven (BE)

1. A method for manufacturing a field effect transistor of a non-planar type, comprising:
providing a substrate having an initially planar front main surface;
providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures
in the substrate between the shallow trench isolation structures, wherein top surfaces of the shallow trench isolation structures
and the fin structures are abutting on a common planar surface, and wherein sidewalls of the fin structures are fully concealed
by the shallow trench isolation structures;

forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface;
forming dielectric spacer structures around the dummy gate structure;
removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures;
removing an upper portion from the fin structures in the gate trench;
epitaxially regrowing the removed upper portion of the fin structures; and
after removing the dummy gate structure and after epitaxially regrowing the removed upper portion of the fin structures, removing
an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the
fin structures within the gate trench, and forming a final gate stack in the gate trench.

US Pat. No. 9,472,474

METHODS FOR CHARACTERIZING SHALLOW SEMICONDUCTOR JUNCTIONS

IMEC VZW, Leuven (BE)

1. A method of characterizing shallow semiconductor PN junctions, the method comprising:
providing a substrate comprising a shallow PN junction formed at a first main surface, the shallow PN junction comprising
a p-type region and an n-type region and being formed substantially parallel to the first main surface;

providing a dielectric layer contacting the first main surface thereby forming a dielectric/semiconductor interface with one
of the p-type region or the n-type region, wherein the shallow PN junction has a depth less than 100 nm from the dielectric/semiconductor
interface;

iterating, at least twice, a combination of processes including:
providing a respective charge on a predetermined area of the dielectric layer via a charge applicator, and
measuring a corresponding junction photovoltage for the predetermined area; and
deriving at least one of an average hole/electron mobility or a dose of active dopants in the substrate corresponding to the
predetermined area, based on the respective charges and the corresponding junction photovoltages.

US Pat. No. 9,465,069

METHOD FOR THE EXTRACTION OF RECOMBINATION CHARACTERISTICS AT METALLIZED SEMICONDUCTOR SURFACES

IMEC VZW, Leuven (BE)

1. A method for determining a recombination characteristic at a semiconductor surface, wherein the method comprises:
providing a test structure, wherein the test structure comprises:
a semiconductor substrate having a first surface and a second surface opposite to the first surface;
a first passivation layer on the first surface;
a second passivation layer on the second surface, the second passivation layer having a plurality of openings at predetermined
locations; and

a plurality of metal features in contact with the second semiconductor surface at the predetermined locations, thus forming
metallized surfaces at the predetermined locations and non-metallized surfaces outside the predetermined locations,

wherein a characteristic size of the metal features is smaller than an effective diffusion length in the underlying semiconductor
at the predetermined locations, and the metal features being provided with a spacing smaller than an effective diffusion length
in the underlying semiconductor outside the predetermined locations, the metal features being grouped in a plurality of zones,
each of the plurality of zones having a different metal coverage, the metal coverage being the ratio between the metallized
surface area and the total area;

performing a photo-conductance decay measurement in each of the plurality of zones, thereby determining effective lifetimes
for different injection levels as a function of metal coverage; and

extracting the recombination characteristic from the determined effective lifetimes.

US Pat. No. 9,257,539

METHOD FOR MANUFACTURING TRANSISTOR AND ASSOCIATED DEVICE

IMEC VZW, Leuven (BE)

1. A method for manufacturing a transistor device, comprising:
providing a plurality of parallel nanowires on a substrate, each nanowire having a first end and a second end, wherein the
first end and the second end of each nanowire are connected to each other by a connection portion, wherein the plurality of
nanowires and the connection portions comprise a same material;

providing a dummy gate structure over a central portion of the parallel nanowires, thereby covering the central portion of
the parallel nanowires;

epitaxially growing extension portions selectively on the parallel nanowires and the connection portions, outside of the central
portion of the parallel nanowires, wherein the extension portions comprise a second material;

providing a filler layer around and on top of the dummy gate structure and the extension portions;
flattening the filler layer, whereby an upper surface of the dummy gate structure is exposed;
removing the dummy gate structure, whereby a gate trench is created and whereby the central portion of the parallel nanowires
is exposed;

providing spacer structures on sidewalls of the gate trench, whereby a final gate trench is defined; thereafter,
thinning the parallel nanowires, whereby free space in between the nanowires and the spacer structures is created, resulting
in an extended exposed portion of the parallel nanowires; and

selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, whereby
a connection between the quantum well layer and respective extension portions is provided.

US Pat. No. 9,413,139

HYBRID WAVEGUIDE LASERS AND METHODS FOR FABRICATING HYBRID WAVEGUIDE LASERS

IMEC VZW, Leuven (BE) Un...

1. A sub-micron III-V waveguide laser comprising:
a local-epitaxy-grown channel waveguide having a width in the range between 50 nm and 800 nm and a height in the range between
500 nm and 1200 nm, wherein the channel waveguide has a first lateral side and a second lateral side;

a lateral cladding layer adjacent to the first lateral side and the second lateral side of the channel waveguide; and
a light confinement element for confining light in the local-epitaxy-grown channel waveguide, wherein the light confinement
element comprises an overlay covering the channel waveguide and containing a high refractive index material having a refractive
index that is higher than a refractive index of the lateral cladding layer.

US Pat. No. 9,287,273

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING TRANSISTORS EACH HAVING A DIFFERENT EFFECTIVE WORK FUNCTION

IMEC VZW, Leuven (BE)

1. A method of manufacturing a semiconductor device comprising transistors each having a different work function arranged
along a main surface of a substrate, the method comprising:
providing at least two channel regions in the substrate;
providing a dielectric layer on the substrate over the at least two channel regions;
providing openings through the dielectric layer to expose portions of each of the at least two channel regions, thereby defining
corresponding gate regions inside the openings and over the at least two channel regions;

providing a gate dielectric layer on the exposed channel regions of each of the gate regions;
providing on the gate dielectric layer of each of the gate regions a barrier layer stack each having a different thickness,
wherein providing the barrier layer stack comprises:
providing a first barrier layer on the gate dielectric layer of each of the gate regions;
selectively removing the first barrier layer from a subset of the gate regions while leaving the first barrier layer in at
least a complementary subset of the gate regions;

repeating at least once the processes of:
providing a subsequent barrier layer in each of the gate regions;
selectively removing the subsequent barrier layer from a respective subset of the channel regions, while leaving the respective
subsequent barrier layer in a respective complementary subset of the channel regions, such that barrier layer stacks having
different thickness along different gate regions are provided; and

providing a gate-filling stack of metal layers on the barrier layer stack in each of the gate regions.

US Pat. No. 9,472,705

INTEGRATED AVALANCHE GERMANIUM PHOTODETECTOR

IMEC VZW, Leuven (BE) Un...

1. An integrated avalanche photodetector comprising:
a germanium (Ge) body adapted to conduct an optical mode, wherein the Ge body comprises:
a first p-doped region for absorption of the optical mode, wherein the first p-doped region extends from a first main surface
to a second main surface of the Ge body;

a first n-doped region aside the first p-doped region, wherein the first n-doped region extends from the first main surface
towards the second main surface of the Ge body, and forms a first avalanche junction with the first p-doped region;

an intrinsic region that occupies undoped parts of the Ge body;
an incidence surface suitable for receiving the optical mode perpendicular to the first avalanche junction; and
a second n-doped Ge region that covers the Ge body and forms a second avalanche junction with the first p-doped region at
the first main surface.

US Pat. No. 9,217,861

MICRO-MIRROR ARRAYS

IMEC VZW, Leuven (BE)

1. A variable focal length lens comprising:
a micro-mirror array having a plurality of micro-mirror elements arranged in at least a first section and a second section,
wherein:

each micro-mirror element has a tilt axis and comprises, on each of two opposing sides of the tilt axis, (i) at least one
actuation electrode, (ii) at least one measurement electrode, and (iii) at least one stopper;

each micro-mirror element in the first section has a first tilt angle range;
each micro-mirror element in the second section has a second tilt angle range; and
the first tilt angle range is less than the second tilt angle range.

US Pat. No. 9,559,320

FERRO-ELECTRIC DEVICE AND MODULATABLE INJECTION BARRIER

NEDERLANDSE ORGANISATIE V...

1. A semiconductor element comprising at least one modulatable injection barrier, said barrier being formed between a first
electrode layer of a first electrode and a semiconductor layer, wherein the semiconductor layer is interposed between the
first electrode and a second electrode,
wherein the semiconductor layer comprises a blend of a semiconductor polymer and a ferro-electric dielectric polymer, the
blend comprising:

a ferro-electric dielectric polymer structure, extending between the first and second electrodes, and the ferro-electric dielectric
polymer being in an amount within the blend sufficient to allow that a polarization charge can be measured, and

a semiconductor polymer path, extending between the first and second electrodes, for travel of charge carriers flowing as
a current through the semiconductor layer between the first and second electrodes,

wherein the semiconductor layer is made up primarily of the ferro-electric dielectric polymer structure, and the semiconductor
polymer path comprises portions of the semiconductor layer wherein holes within the ferro-electric dielectric polymer structure
are filled with semiconductor polymer material providing a continuous semiconductor path between the first electrode and second
electrode.

US Pat. No. 9,391,060

ELECTROSTATIC DISCHARGE PROTECTION

IMEC VZW, Leuven (BE)

1. A bulk fin-based electrostatic discharge device comprising:
a semiconductor substrate;
an isolating layer over the semiconductor substrate;
a first recess formed in the isolating layer, the first recess comprising a first portion of the isolating layer in a first
region and a second portion of the isolating layer in a second region; and

a first fin protruding from the semiconductor substrate through the first recess formed in the isolating layer within the
first and second regions,

wherein one part of the first fin and an upper substrate portion in the first region are homogeneously doped with a first
dopant, and another part of the first fin and an upper substrate portion in the second region are homogeneously doped with
a second dopant.

US Pat. No. 9,326,733

SYSTEM AND METHOD FOR ACQUISITION OF BIOPOTENTIAL SIGNALS WITH MOTION ARTIFACT REDUCTION IN REAL TIME OPERATION

IMEC VZW, Leuven (BE)

1. A biopotential signal acquisition system comprising:
an analogue readout unit configured to receive an analogue biopotential signal and to extract an analogue measured biopotential
signal and an analogue reference signal;

a Sigma-Delta ADC unit configured to provide a digital measured biopotential signal from the analogue measured biopotential
signal and a digital reference signal from the analogue reference signal;

a first digital filter unit connected to an output of the Sigma-Delta ADC, and including a cascaded integrator-comb filter
and a halfband decimation filter connected to the cascaded integrator-comb filter, wherein the first digital filter unit is
configured to provide a first digital filtered version of the digital measured biopotential signal and the digital reference
signal at an output of the cascaded integrator-comb filter, and a second digital filtered version of the digital measured
biopotential signal and the digital reference signal at an output of the first digital filter unit; and

a second digital filter unit connected to the output of the cascaded integrator-comb filter of the first digital filter unit,
and configured to calculate a digital motion artifact estimate based on the first digital filtered version of the digital
measured biopotential signal and the digital reference signal.

US Pat. No. 9,166,608

METHOD AND CIRCUIT FOR BANDWIDTH MISMATCH ESTIMATION IN AN A/D CONVERTER

IMEC VZW, Leuven (BE)

1. A method for estimating bandwidth mismatch in a time-interleaved A/D converter comprising a plurality of channels, each
channel comprising sampling means for sampling a reference analog input voltage signal (Vref), an array of capacitors connected in parallel and a quantizer arranged for converting the sampled input voltage at first
terminals of the capacitors into a digital code, the method comprising:
precharging second terminals of the capacitors of the plurality of channels to a first state and sampling the reference analog
input voltage signal, whereby the reference analog input voltage signal is applied via a first switchable path and the sampled
input voltage signal is received at first terminals of the capacitors,

setting in each channel the second terminals to a second state, thereby generating a further reference voltage signal (Vdiff) at the first terminals,

applying the reference analog input voltage signal to the first terminals of the capacitors via a second switchable path,
the second path having a given impedance being higher than the known impedance of the first path, thereby creating on the
first terminals a non-zero settling error indicative of an incomplete transition from the further reference voltage signal
to the reference analog input voltage signal,

quantizing the non-zero settling error, thereby obtaining an estimate of the non-zero settling error in each channel of the
plurality,

comparing the estimates of the non-zero settling errors of the channels and deriving therefrom an estimation of the bandwidth
mismatch.

US Pat. No. 9,313,428

IMAGING SENSORS

IMEC VZW, Leuven (BE)

1. A method for operating a light detection circuit comprising a first node, a second node, and a photodiode, the method comprising:
accumulating charge carriers via the photodiode;
while the photodiode is accumulating the charge carriers:
(i) connecting a reset voltage to the second node and connecting the second node to the first node;
(ii) isolating the second node from the reset voltage and isolating the first node from the second node, thereby generating
a reference voltage at the first node; and

(iii) sampling the reference voltage;
transferring, from the photodiode, a first portion of the charge carriers to the first node and a second portion of the charge
carriers to the second node;

sampling a first output voltage at the first node represented by the first portion of the charge carriers;
distributing the second portion of the charge carriers between the first node and the second node by connecting the first
node to the second node; and

sampling a second output voltage represented by the first portion of the charge carriers and the second portion of the charge
carriers distributed between the first node and the second node.

US Pat. No. 9,294,048

INSTRUMENTATION AMPLIFIER AND SIGNAL AMPLIFICATION METHOD

IMEC VZW, Leuven (BE)

1. An instrumentation amplifier comprising:
a first amplifier having one input connected to a first input of the instrumentation amplifier;
a second amplifier having one input connected to a second input of the instrumentation amplifier; and
a feedback network comprising an active filter having a first low pass filter characteristic with a first cut-off frequency
in respect of differential mode signals at the first and second inputs of the instrumentation amplifier, and a second low
pass filter characteristic with a second cut-off frequency in respect of common mode signals at the first and second inputs
of the instrumentation amplifier.

US Pat. No. 9,478,611

VERTICAL NANOWIRE SEMICONDUCTOR STRUCTURES

IMEC VZW, Leuven (BE)

1. A semiconductor structure comprising:
a first surface, and
at least one nanowire, the at least one nanowire abutting the first surface and forming an angle therewith,
wherein the first surface has less than 106 threading dislocations per cm2 and is made of a doped semiconductor material having a doping level of more than 1019 at/cm3,

wherein the at least one nanowire is made of an undoped semiconductor material having a doping level of less than 1017 at/cm3 and having a lattice mismatch with the material of the first surface of from 0% to 1%, and

wherein the doped semiconductor material and the undoped semiconductor material each have an electron mobility of at least
2000 cm2/(V·s) or a hole mobility of at least 500 cm2/(V·s).

US Pat. No. 9,482,816

RADIATION COUPLER

IMEC VZW, Leuven (BE)

1. A semiconductor photonics device for coupling radiation to a semiconductor waveguide, the semiconductor photonics device
comprising:
a semiconductor-on-insulator substrate comprising:
a semiconductor substrate,
a buried oxide layer positioned on top of the semiconductor substrate, and
a semiconductor layer positioned on top of the buried oxide layer,
wherein the semiconductor layer comprises a semiconductor waveguide to which radiation is to be coupled; and
a SiN grating coupler positioned above the buried oxide layer and comprising a SiN guiding layer, wherein the SiN guiding
layer is positioned above the semiconductor layer, and wherein the SiN grating coupler is configured for coupling incident
radiation to the semiconductor waveguide,

wherein the semiconductor substrate has a recessed portion at the backside of the semiconductor substrate for receiving incident
radiation to be coupled to the semiconductor waveguide via the backside of the semiconductor substrate and the SiN grating
coupler.

US Pat. No. 9,419,114

TUNNEL FIELD-EFFECT TRANSISTOR

IMEC VZW, Leuven (BE) Ta...

1. A tunnel field-effect transistor device, comprising:
a semiconductor substrate;
a fin structure contacting the semiconductor substrate on a major surface of the semiconductor substrate, wherein the fin
structure is an elevated structure with respect to the semiconductor substrate, wherein the fin structure has a height measured
in a direction orthogonal to the major surface of the semiconductor substrate, wherein the fin structure has a length measured
in a longitudinal direction parallel to the major surface, wherein the fin structure has a width measured in a direction orthogonal
to both the direction of the height and the longitudinal direction, the fin structure comprising a channel region, a drain
region, and a source region, wherein the source region is disposed on the channel region, wherein the source region comprises
a gate interface portion wherein the channel region is disposed on the drain region, and wherein the source region and the
drain region are of opposite conductivity type;

a pocket layer covering the gate interface portion of the source region, the pocket layer contacting at least part of the
channel region, wherein the gate interface portion of the source region comprises at least three mutually non-coplanar surface
segments;

a gate dielectric layer covering the pocket layer, the gate dielectric layer electrically isolating the gate electrode and
the source region: and

a gate electrode covering the gate dielectric layer, wherein the gate electrode is substantially parallel to the at least
three non-coplanar surface segments, wherein the pocket layer comprises an intrinsic semiconductor material or is doped with
a species opposite a conductivity type of the source region, wherein the pocket layer is configured to capture charge carriers
tunneling from the source region in a direction of the gate electrode, and wherein the pocket layer is configured to divert
the charge carriers via the channel region to a portion of the drain region which is in contact with the channel region but
which is electrically insulated from the source region.

US Pat. No. 9,375,182

SYSTEM AND METHOD FOR ACQUISITION OF BIOPOTENTIAL SIGNALS WITH MOTION ARTIFACT REDUCTION

IMEC VZW, Leuven (BE)

1. A biopotential signal acquisition system comprising:
a readout unit configured to receive an analogue biopotential signal and to extract, from that received analogue biopotential
signal, a measured biopotential signal and a first reference signal;

a reference signal processing unit configured to convert the first reference signal into a second reference signal based on
a correlation between the measured biopotential signal and the first reference signal; and

a digital filter unit configured to calculate a digital motion artifact estimate based on a digital version of the measured
biopotential signal and the second reference signal,

wherein the correlation between the measured biopotential signal and the first reference signal is estimated by calculating
a correlation between the digital motion artifact estimate and the first reference signal.

US Pat. No. 9,537,028

PINNED PHOTODIODE (PPD) PIXEL ARCHITECTURE WITH SEPARATE AVALANCHE REGION

IMEC VZW, Leuven (BE)

1. A pinned photodiode pixel architecture comprising:
a first doped region formed over a second doped region, wherein the first doped region is internally biased to a first potential;
and

a third doped region formed over the first doped region, wherein the third doped region is externally biased to a second potential,
wherein at least the second doped region is externally biased to a third potential that is independent of the second potential
to create an avalanche region between the first doped region and the second doped region,

and wherein each of the first doped region, the second doped region, and the third doped region has a different bias.

US Pat. No. 9,520,291

METHOD OF PROVIDING AN IMPLANTED REGION IN A SEMICONDUCTOR STRUCTURE

IMEC VZW, Leuven (BE)

1. A method of providing an implanted region in a semiconductor structure including a first region and a second region, the
method comprising:
providing a first implantation mask covering the first region of the semiconductor structure, the first implantation mask
including a first sacrificial layer, wherein the first sacrificial layer is formed as a spin-on-carbon layer, and a second
sacrificial layer, wherein the second sacrificial layer is formed as a spin-on-glass layer;

subjecting the semiconductor structure to an ion implantation process, wherein an extension of the first implantation mask
is such that ion implantation in the first region is counteracted and ion implantation in the second region is allowed where
the second region is implanted;

forming a third sacrificial layer covering the second region of the semiconductor structure, wherein the third sacrificial
layer includes carbon;

removing the second sacrificial layer at the first region by etching, wherein the third sacrificial layer protects the second
region from being affected by the etching, and

removing the first sacrificial layer at the first region and the third sacrificial layer at the second region by etching.

US Pat. No. 9,478,544

METHOD FOR FORMING A GERMANIUM CHANNEL LAYER FOR AN NMOS TRANSISTOR DEVICE, NMOS TRANSISTOR DEVICE AND CMOS DEVICE

IMEC vzw, Leuven (BE)

1. A method of forming a transistor device, the method comprising:
providing a trench having sidewalls defined by a dielectric material structure and abutting on a silicon substrate's surface;
growing a seed layer in the trench on the surface, the seed layer having a front surface comprising facets having a (111)
orientation;

growing a strain-relaxed buffer (SRB) layer in the trench and on the seed layer, the strain-relaxed buffer layer comprising
silicon germanium (SiGe); and

growing a strain-relaxed germanium channel layer on the strain-relaxed buffer layer.

US Pat. No. 9,529,154

METHOD FOR OPTICAL COUPLING BETWEEN A PHOTONIC INTEGRATED CIRCUIT AND AN EXTERNAL OPTICAL ELEMENT

IMEC VZW, Leuven (BE) Un...

1. A method comprising:
providing a photonic integrated circuit comprising at least one integrated optical waveguide, the photonic integrated circuit
having a cover layer;

providing at least one optical component external to the photonic integrated circuit, the at least one optical component having
an optical coupling facet configured to be optically coupled to the at least one integrated optical waveguide, thereby forming
an assembly;

determining a position of the optical coupling facet of the at least one optical component in the assembly;
determining a position of the at least one integrated optical waveguide;
designing an optical interface pattern between the optical coupling facet of the at least one optical component in the assembly
and the at least one integrated optical waveguide; and

writing the interface pattern in the cover layer of the photonic integrated circuit by means of a femtosecond laser, thereby
forming an optical interface for optically coupling the optical coupling facet and the at least one integrated optical waveguide,

wherein the interface pattern comprises at least one intermediate optical waveguide structure.

US Pat. No. 9,355,889

SEMICONDUCTOR-ON-INSULATOR DEVICE AND METHOD OF FABRICATING THE SAME

IMEC VZW, Leuven (BE)

1. A method of fabricating a semiconductor-on-insulator device, the method comprising:
providing a pre-patterned donor wafer, comprising:
providing a donor substrate comprising a first semiconductor material,
forming shallow trench isolation (STI) regions in the donor substrate,
forming a plurality of fins, each fin formed between adjacent STI regions and separated from an adjacent fin by one of the
STI regions, wherein a top part of each fin comprises a Group III-V or Group IV semiconductor material different from the
first semiconductor material, and

forming a first oxide layer over the STI regions and the fins;
providing a handling wafer;
bonding the pre-patterned donor wafer to the handling wafer by contacting the first oxide layer to the handling wafer;
removing at least part of the first semiconductor material from a backside of the bonded pre-patterned donor wafer; and
sufficiently thinning the STI regions and the fins from the backside of the bonded donor wafer to expose the Group III-V or
Group IV semiconductor material, thereby forming channel regions comprising the Group III-V or Group IV semiconductor material.

US Pat. No. 9,531,371

RESTORING OFF-STATE STRESS DEGRADATION OF THRESHOLD VOLTAGE

IMEC VZW, Leuven (BE)

1. A method for at least partially compensating for a change in threshold voltage level of a field-effect transistor induced
by OFF-state stress degradation, the method comprising:
determining a signal indicative of a change in threshold voltage level of the field-effect transistor with respect to a reference
threshold voltage level; and

applying a restoration signal to the field-effect transistor, wherein applying the restoration signal comprises applying at
least one voltage pulse to the field-effect transistor such that a gate terminal of the field-effect transistor is connected
to a higher voltage level than a drain terminal of the field-effect transistor and to a higher voltage level than a source
terminal of the field-effect transistor, wherein the restoration signal is adapted for shifting the threshold voltage level
of the field-effect transistor in a direction having an opposite sign with respect to the change in threshold voltage level,
and wherein applying the restoration signal includes taking into account the signal indicative of the change in threshold
voltage level.

US Pat. No. 9,580,747

DNA CHIP WITH MICRO-CHANNEL FOR DNA ANALYSIS

PANASONIC CORPORATION, O...

1. A DNA chip with a micro-channel for DNA analysis of DNA included in an analyte according to a PCR method, the DNA chip
comprising:
a first layer made of silicon;
a second layer made of plastic;
a first channel;
a second channel; and
a third channel,
wherein the second layer is formed on a partial area of the first layer, and
the second layer comprises:
a first pump;
a second pump;
a third pump;
a hole configured to inject an analyte;
a hole configured to inject a first reagent;
a hole configured to inject a second reagent; and
a sensor,
the first layer includes a first PCR reactor and a second PCR reactor provided on an area on which the second layer is not
formed, and

the first channel is passed through the hole configured to inject the analyte, the first pump, the first PCR reactor, the
second PCR reactor, and the sensor in sequence, and

the second channel is passed through the hole configured to inject the first reagent and the second pump in sequence, and
the third channel is passed through the hole configured to inject the second reagent and the third pump in sequence, and
the second channel is provided on the first layer and the second channel is connected to the first channel between the first
pump and the first PCR reactor, and

the third channel is provided on the first layer and the third channel is connected to the first channel between the first
PCR reactor and the second PCR reactor.

US Pat. No. 9,532,738

IMPLANTABLE SENSOR

UNIVERSITEIT GENT, Ghent...

1. A sensor configured to sense glucose, urea, or lactate, the sensor being implantable in the body of a living creature or
an object and configured for sensing in tissue or bodily fluids, the sensor comprising:
an integrated radiation source configured for coupling radiation generated by said source into a silicon photonics integrated
circuit for irradiating said tissue or bodily fluids having at least one of glucose, urea, or lactate in said tissue or bodily
fluid,

a silicon photonics integrated circuit configured to spectrally process the radiation interacting with the glucose or urea
or lactate, wherein the silicon photonics integrated circuit comprises at least an integrated optical waveguide, an optical
demultiplexer, and a detection element,

said integrated optical waveguide being configured for receiving radiation from said integrated radiation source and to send
the radiation to the demultiplexer, said waveguide comprising a part configured for evanescent sensing within a measurement
region from which the radiation interacting with the glucose, urea, or lactate is captured by said waveguide and senses the
glucose, urea, or lactate by an evanescent tail of the radiation,

said optical demultiplexer being configured for spectrally processing the radiation to obtain spectrally resolved radiation
said integrated detection element being configured to detect different absorption or reflection bands of the glucose or urea
or lactate from the spectrally resolved radiation to sense the glucose or urea or lactate, wherein the silicon photonics integrated
circuit and the measurement region are configured for sampling free spectral measurements so that sensing can be performed
without the need for extracting a sample or guiding a substrate of interest in a forced manner to the measurement region,
and

wherein the radiation source and the silicon photonics integrated circuit form an integrated spectrometer, and
wherein said sensor is configured to be implantable in the body of a living creature or an object to sense glucose, urea,
or lactate.

US Pat. No. 9,419,110

METHOD FOR REDUCING CONTACT RESISTANCE IN MOS

IMEC VZW, Leuven (BE)

16. A device comprising:
(a) a SinGe1-n substrate having an area doped with a group V element (9),

(b) a nucleation layer of III-V material of from 5 to 15 nm overlaying the SinGe1-n substrate at said area, and

(c) a III-V semiconductor structure on said nucleation layer, said III-V semiconductor structure being a crystal comprising
facets.

US Pat. No. 9,437,488

METALLIZATION METHOD FOR SEMICONDUCTOR STRUCTURES

IMEC VZW, Leuven (BE)

1. A method for fabricating a semiconductor device, comprising:
providing a device with a first sacrificial layer, wherein the first sacrificial layer includes at least one via exposing
a metal surface;

applying a self-assembled monolayer on the exposed metal surface;
growing a metal on the self-assembled monolayer to fill the at least one via, thereby forming at least one metal pillar; and
replacing the first sacrificial layer with a replacement dielectric layer having a dielectric constant of at most 3.9.

US Pat. No. 9,681,844

BIOPOTENTIAL SIGNAL ACQUISITION SYSTEM AND METHOD

IMEC VZW, Leuven (BE) St...

1. A biopotential signal acquisition system, comprising:
a first active electrode including an integrated pre-amplifier and an analogue to digital converter;
a second active electrode including an integrated pre-amplifier and an analogue to digital converter, wherein the second active
electrode has a variable gain;

a test signal generator configured to generate a test signal at a test frequency and to couple the test signal to the first
and/or second active electrodes; and

a digital signal processor configured to process the digital outputs of the first and second active electrodes to derive a
gain control signal based on a difference between the first and second active electrode outputs at the test frequency, and
to apply the gain control signal to the second active electrode.

US Pat. No. 9,601,379

METHODS OF FORMING METAL SOURCE/DRAIN CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES WITH GATE ALL AROUND CHANNEL STRUCTURES

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a nanowire device comprising multiple nanowires, a channel region and a plurality of source/drain regions,
the method comprising:
forming a plurality of stacked substantially un-doped nanowire structures above a semiconductor substrate, said plurality
of stacked substantially un-doped nanowire structures comprising a first plurality of nanowires made of a first semiconductor
material and a second plurality of nanowires made of a second semiconductor material that is different than said first semiconductor
material;

forming a sacrificial structure around said plurality of stacked substantially un-doped nanowire structures at a location
that corresponds to said channel region of said device;

forming a layer of insulating material above and adjacent said plurality of stacked substantially un-doped nanowire structures
and proximate said sacrificial structure;

removing said sacrificial structure to define a cavity that exposes said plurality of stacked substantially un-doped nanowire
structures within said cavity;

performing a selective etching process through said cavity to remove said second plurality of nanowires from said channel
region and said source/drain regions of said device while leaving said first plurality of nanowires in position;

forming a metal conductive source/drain contact structure in each of said source drain regions, wherein each of said metal
conductive source/drain contact structures is positioned all around said first plurality of nanowires positioned in said source/drain
region; and

forming a gate all around gate structure that is positioned all around each of said first plurality of nanowires positioned
in said channel region of said device.

US Pat. No. 9,349,484

SAMPLE-AND-HOLD CIRCUIT FOR AN INTERLEAVED ANALOG-TO-DIGITAL CONVERTER

IMEC VZW, Leuven (BE)

1. A sample-and-hold circuit comprising
a transistor arranged for switching between a sample mode and a hold mode; and
a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal
of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold
mode, the bootstrap circuit comprising a bootstrap capacitance arranged for being precharged to a given charge voltage during
the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample
mode, wherein the bootstrap circuit comprises a programmable switched capacitor charge pump for generating the given charge
voltage to which the bootstrap capacitance is precharged.

US Pat. No. 10,036,625

INTEGRATED SPECTROMETERS WITH SINGLE PIXEL DETECTOR

UNIVERSITEIT GENT, Ghent...

1. An integrated, waveguide based, spectrometer implemented in an integrated photonics circuit, the spectrometer comprising:a sensing region configured for receiving multi-wavelength radiation interacting with a sample in the sensing region,
a wavelength demultiplexing element arranged for capturing said multi-wavelength radiation after interaction with the sample and configured for providing a number of wavelength demultiplexed radiation outputs or a number of different groups of wavelength demultiplexed radiation outputs into different signal carriers,
an integrated modulator configured for differently modulating the different demultiplexed radiation outputs or different groups of demultiplexed radiation outputs in the different signal carriers, the integrated modulator being implemented in the integrated photonics circuit, and
a multiplexer element configured for multiplexing the differently modulated demultiplexed radiation outputs or the differently grouped demultiplexed radiation outputs.

US Pat. No. 9,589,896

ELECTROLESS METAL DEPOSITION ON A MANGANESE OR MANGANESE NITRIDE BARRIER

IMEC VZW, Leuven (BE)

1. An electronic circuit structure, comprising
a substrate;
a dielectric layer on top of the substrate, the dielectric layer comprising a cavity having side-walls;
a manganese or manganese nitride layer covering the side-walls; and
a self-assembled monolayer comprising an organic compound of formula Z-L-A, covering the manganese or manganese nitride layer,
wherein Z is selected from the group consisting of a primary amino group, a carboxylic acid group, a thiol group, a selenol
group, and a heterocyclic group having an unsubstituted tertiary amine in the cycle, wherein L is an organic linker having
from 1 to 12 carbon atoms and from 0 to 3 heteroatoms, and wherein A is a group attaching the linker to the manganese or manganese
nitride layer.

US Pat. No. 9,696,478

INTEGRATED GRATING COUPLER AND POWER SPLITTER

IMEC VZW, Leuven (BE) Un...

1. An optical device for coupling an external optical signal into a plurality of on-chip channel photonic sub-circuits provided
on a substrate, wherein the optical device comprises:
a planar waveguide layer on the substrate;
a diverging grating coupler configured to couple the external optical signal to the planar waveguide layer, thereby creating
a single on-chip diverging optical beam in the planar waveguide layer,

wherein the diverging grating coupler is a curved grating coupler; and
a plurality of channel waveguides formed in the planar waveguide layer, each channel waveguide of the plurality of channel
waveguides comprising a waveguide transition structure having a waveguide aperture oriented towards the diverging grating
coupler,

wherein for each channel waveguide of the plurality of channel waveguides a position and a width of the waveguide aperture
and an angle and a shape of the waveguide transition structure are selected to capture a predetermined portion of the single
on-chip diverging optical beam,

wherein the waveguide transition structure of a center channel waveguide comprises a center rectangular section,
wherein the waveguide transition structure of an outer channel waveguide comprises an outer rectangular section,
wherein the center rectangular section and the outer rectangular sections are configured to match an incident field profile
of the corresponding predetermined portion of the single on-chip diverging optical beam, and

wherein the predetermined portion of the single on-chip diverging optical beam is captured from a slab waveguide region defined
in the planar waveguide layer between the diverging grating coupler and the waveguide aperture.

US Pat. No. 9,866,651

ENTITY CREATION FOR CONSTRAINED DEVICES

KONINKLIJKE KPN N.V., Th...

1. A method for creating a profile for accessing resources across a plurality of nodes in a network, each node associated
with a node identifier, at least one resource, and/or at least one capability, the method comprising:
receiving, from a client at an entity manager, at least one first request to create the profile, said at least one first request
comprising the node identifiers;

generating the profile, said profile comprising a list of node identifiers associated with the plurality of nodes, wherein
the profile is addressable by a profile identifier;
wherein the at least one first request (1) further comprises an operation or (2) is associated with an operation by default
at the entity manager, said method further comprising:
verifying that the nodes are able to support the operation based on the at least one resource and/or the at least one capability
associated with the plurality of nodes;

if the nodes are able to support the operation, associating the profile with the operation.

US Pat. No. 9,792,165

BINDING SMART OBJECTS

KONINKLIJKE KPN N.V., Th...

1. A method comprising:
receiving, at a sensor device, from a binding initiator, a first Representational State Transfer (REST) request for a first
REST resource hosted by the sensor device, the first REST request comprising at least an identification of an action to be
executed on an actuator device and an identification of a condition of a state of the first REST resource for executing the
action on the actuator device;

storing, in a binding table of the sensor device, the identification of the action to be executed on the actuator device and
the identification of the condition for executing the action on the actuator device as information related to the first REST
resource; monitoring, by the sensor device, the state of the first REST resource to determine whether the state satisfies
the condition identified in the first REST request; after determining that the state of the first REST resource satisfies
the condition, providing, from the sensor device to the actuator device, a trigger for the actuator device to execute the
action identified in the first REST request, wherein the trigger is provided in a form of a second REST request;

receiving, at the sensor device, from either the binding initiator or a further device, a third REST request comprising an
indication that the sensor device should no longer provide the trigger to the actuator device to execute the action identified
in the first REST request; and

removing the identification of the action to be executed on the actuator device and the identification of the condition for
executing the action on the actuator device from the binding table.

US Pat. No. 9,343,329

CONTACT FORMATION IN GE-CONTAINING SEMICONDUCTOR DEVICES

IMEC VZW, Leuven (BE)

1. A process for creating a contact on a Ge-containing contact region of a semiconductor structure, said process comprising
the steps of:
(a) providing said semiconductor structure comprising:
(i) a Ge-containing contact region,
(ii) optionally, a SiO2 layer coating said Ge-containing contact region,

(iii) a Si3N4 layer coating said SiO2 layer if present or said Ge-containing contact region,

(c) etching selectively the Si3N4 layer by means of an inductively coupled plasma, thereby exposing the underlying SiO2 layer if present or the Ge-containing contact region,

(d) etching selectively the SiO2 layer if present, thereby exposing the Ge-containing contact region, and

(e) creating said contact on said Ge-containing contact region.

US Pat. No. 9,942,502

IMAGING SENSOR WITH IN-PIXEL AMPLIFICATION

IMEC vzw, Leuven (BE)

1. A pixel architecture comprising:a photodiode element operable for generating a signal;
an in-pixel amplifier configured to amplify the generated signal and having a gain greater than one, the in-pixel amplifier comprising an NMOS amplifier with a depletion-mode NMOS load transistor, wherein the depletion-mode NMOS load transistor functions as a load of the NMOS amplifier;
an output for outputting the amplified signal.

US Pat. No. 9,601,459

METHOD FOR ALIGNING MICRO-ELECTRONIC COMPONENTS

IMEC VZW, Leuven (BE)

1. A method for aligning a first micro-electronic component to a second micro-electronic component, wherein each component
includes a contact area covered by a wetting layer, wherein each component includes a means for containing an alignment liquid
on the respective wetting layer, and wherein each component is further provided with one or more conductor lines running along
a circumference of the respective contact area, the method comprising:
applying an amount of the alignment liquid to the contact area of the second component;
placing the first component with its contact area facing the contact area of the second component so that the alignment liquid
contacts both wetting layers, thereby establishing self-alignment of the contact areas through capillary force;

applying an electric potential such as to charge the conductor lines of at least one of the components in a manner to realize
an electrostatic alignment of the contact areas; and

maintaining the electrostatic alignment while the alignment liquid evaporates.

US Pat. No. 9,601,488

GATE-ALL-AROUND SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

IMEC VZW, Leuven (BE)

1. A semiconductor device comprising:
a semiconductor substrate comprising a crystalline semiconductor material;
at least one suspended nanostructure extending in a first direction and formed at least partially above and between a pair
of adjacent STI regions, the at least one suspended nanostructure being electrically connected to and mechanically supported
by a source region and a drain region formed at opposite ends of the at least one suspended nanostructure in the first direction,
wherein the at least one suspended nanostructure comprises a crystalline semiconductor material that is different from the
crystalline semiconductor material of the semiconductor substrate;

a cavity formed vertically between the at least one suspended nanostructure and the semiconductor substrate and laterally
between sidewalls of the STI regions facing each other; and

a gate stack surrounding the suspended nanostructure, wherein the gate stack extends to cover a top surface and the sidewalls
of the STI regions and an exposed surface of the semiconductor substrate in the cavity.

US Pat. No. 9,595,422

PLASMA ETCHING OF POROUS SUBSTRATES

IMEC VZW, Leuven (BE) Ka...

1. A method of etching a porous material, comprising:
contacting a porous material with an organic gas in an environment having a pressure (P1) and a temperature (T1), wherein the organic gas is such that at the pressure (P1) and the temperature (T1), the organic gas remains in a gas state when outside of the porous material, while the organic gas condenses into an organic
liquid when in contact with the porous material, wherein when in contact with the porous material, the organic liquid fills
pores of the porous material;

subsequent to the contacting, plasma etch-treating the porous material having the pores filled with the organic liquid, thereby
evaporating a fraction of the organic liquid filling the pores of the porous material; and

repeating contacting and plasma etch-treating n times, wherein n?1.

US Pat. No. 9,826,016

FAIR ADAPTIVE STREAMING

KONINKLIJKE KPN N.V., Th...

1. Method for enabling adaptive streaming client devices to share network resources during transmission of content to said
client devices, comprising:
a network node monitoring chunk request messages of client devices, said client devices being configured to select a quality
level of a chunk from a plurality of selectable quality levels and to request a media server for transmission of a chunk of
said selected quality level, said chunk comprising media data representing content for transmission to said client device;

determining for each of said client devices estimated local quality information using the quality level of one or more monitored
chunk request messages of a client device, said local quality information being indicative of a quality level or a Quality
of Experience (QoE) of rendering a plurality of chunks by said client device;

determining global quality information on the basis of said estimated local quality information of said client devices, said
global quality information being indicative of an average quality level or an average QoE of rendering said content by said
client devices; and,

transmitting said global quality information to at least one client device, said global quality information configured for
being used by said at least one client device for selecting a quality level of one or more chunks to be requested by said
client device;

wherein transmitting said global quality information to said at least one client device comprises:
inserting said global quality information in a chunk response message that is transmitted to said client device; and/or,
transmitting said global quality information over a (bi-directional) control channel to said client device;
wherein said client device is configured to:
select said quality level on the basis of said global quality information, preferably said client device using a manifest
file for selecting said quality level, said manifest file defining a plurality of selectable quality levels of said content,
each quality level being associated with a sequence of chunks;

request a chunk of said selected quality level on the basis of location information in said manifest file.

US Pat. No. 9,786,795

SELECTOR FOR RRAM

IMEC VZW, Leuven (BE) Ka...

1. A selector device, comprising:
a first barrier structure comprising a first metal contacting a first semiconductor or a first low bandgap dielectric material;
a second barrier structure comprising a second metal contacting a second semiconductor or a second low bandgap dielectric
material; and

an insulator contacting each of and interposed between the first semiconductor or the first low bandgap dielectric material
and the second semiconductor or the second low bandgap dielectric material,

wherein the first barrier structure, the insulator, and the second barrier structure are stacked to form a metal/semiconductor
or low bandgap dielectric/insulator/semiconductor or low bandgap dielectric/metal structure,

wherein the insulator has a band gap that is between 2 eV and 6 eV, and wherein the insulator has a higher electron barrier
height compared to an electron barrier height of each of the first semiconductor or the first low bandgap dielectric material
and the second semiconductor or the second low bandgap dielectric material.

US Pat. No. 9,673,382

ACTUATOR

Panasonic Corporation, O...

1. An actuator comprising:
a conductive polymer layer;
an ambient temperature molten salt layer; and
an opposite electrode layer; wherein
the ambient temperature molten salt layer is interposed between the conductive polymer layer and the opposite electrode layer,
the ambient temperature molten salt layer comprises an adhesive layer in the inside thereof;
one surface of the adhesive layer adheres to the conductive polymer layer; and
the other surface of the adhesive layer adheres to the opposite electrode layer.

US Pat. No. 9,636,064

SYSTEM AND METHOD FOR MONITORING A SUBJECT'S EYE

IMEC India Private Limite...

1. A camera system comprising:
an image capturing device configured to capture spectral profiles from a frame substantially around a subject's eye; and
an eye monitoring system communicatively connected to the image capturing device, wherein the eye monitoring system is configured
to:

receive the spectral profiles of the frame from the image capturing device;
determine spectral profiles of an eye and skin including an eyelid in the received spectral profiles;
determine a number of the spectral profiles of the eye and a number of the spectral profiles of the skin including the eyelid;
determine a ratio of the number of the spectral profiles of the eye and the number of the spectral profiles of the skin including
the eyelid; and

detect a state of the subject's eye in the frame using the determined ratio.

US Pat. No. 9,614,082

AL-POOR BARRIER FOR INGAAS SEMICONDUCTOR STRUCTURE

IMEC VZW, Leuven (BE)

1. A semiconductor structure comprising:
a) a Si monocrystalline substrate;
b) a III-V structure abutting the Si monocrystalline substrate; and
c) an InaGabAs structure overlaying the III-V structure, wherein a is from 0.40 to 1, b is from 0 to 0.60, and a+b is 1.00,

wherein the III-V structure has a top surface facing away from the Si monocrystalline substrate, the top surface having a
chemical composition GagXxPpSbsZz, wherein X is one or more group III elements other than Ga, wherein Z is one or more group V elements other than P or Sb,
wherein g is from 0.80 to 1.00, x is from 0 to 0.20, z is from 0 to 0.30, p is from 0.10 to 0.55, and s is from 0.50 to 0.80,
g+x is equal to 1.00 and p+s+z is equal to 1.00.

US Pat. No. 10,073,802

INTER-CLUSTER DATA COMMUNICATION NETWORK FOR A DYNAMIC SHARED COMMUNICATION PLATFORM

IMEC VZW, Leuven (BE) St...

1. A data communication network connecting a plurality of computation clusters and arranged for receiving via N data input ports, N>1, input signals from one or more first clusters of the plurality of computation clusters and for outputting output signals to one or more second clusters of the plurality of computation clusters via M data output ports, M>1 the data communication network comprising:a segmented bus network for interconnecting clusters of the plurality of computation clusters;
a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N data input ports, P segmentation switches linking the connected and activated segments,
wherein the N data input ports and the M data output ports are connected via stubs to a subset of the segmentation switches on the P parallel data busses, and
wherein the segmentation switches are implemented, at least partly, in a back-end-of-line (BEOL) fabric of at least one electronic integrated circuit wherein the plurality of computation clusters has been fabricated.

US Pat. No. 9,923,050

SEMICONDUCTOR WAFER AND A METHOD FOR PRODUCING THE SEMICONDUCTOR WAFER

SILTRONIC AG, Munich (DE...

10. A method for producing a semiconductor wafer comprising a silicon single crystal substrate having a top surface and a
stack of layers covering the top surface, the method comprising:
a) providing a silicon single crystal substrate having a top surface, the top surface of the silicon single crystal substrate
having a crystal lattice orientation which is off-oriented with respect to the {111}-plane, a normal to the top surface being
inclined with respect to the <111>-direction toward the [11-2]-direction, the [1-21]-direction, or the [-211]-direction by
an angle ? of not less than 0.3° and not more than 6° , the azimuthal tolerance of the inclination being ±0.1° ;

b) depositing on the top surface of the silicon single crystal substrate an AlN nucleation layer which has a thickness of
not less than 20 nm and not more than 500 nm and covers the top surface of the silicon single crystal substrate; and

c) depositing an AlGaN buffer layer which covers the AIN nucleation layer and comprises one or more AlxGa1?xN layers, wherein 0

US Pat. No. 9,772,447

METHOD FOR REALIZING HETEROGENEOUS III-V SILICON PHOTONIC INTEGRATED CIRCUITS

IMEC VZW, Leuven (BE) Un...

1. A method of producing a photonic integrated circuit, the method comprising:
integrating at least one III-V hybrid device on a source substrate having at least a top silicon waveguide layer; and
transferring, by transfer-printing or by flip-chip bonding, the III-V hybrid device and at least part of the top silicon waveguide
layer of the source substrate to a semiconductor-on-insulator host substrate.

US Pat. No. 9,633,891

METHOD FOR FORMING A TRANSISTOR STRUCTURE COMPRISING A FIN-SHAPED CHANNEL STRUCTURE

IMEC VZW, Leuven (BE)

1. A method for forming a transistor structure comprising a fin-shaped channel structure, the method comprising:
providing a layer stack in a trench defined by adjacent shallow trench isolation (STI) structures;
recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper
portion comprising at least a channel portion;

providing one or more protection layers on the upper portion of the layer stack;
after providing the one or more protection layers, further recessing the STI structures selectively to the protection layers
and the layer stack, to thereby expose a central portion of the layer stack; and

selectively removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the
layer stack being physically separated from each other;

wherein providing the layer stack comprises providing an etch stop layer at a position directly below the channel portion,
such that the freestanding upper part of the layer stack comprises an etch stop layer at its lower surface after selectively
removing the central portion.

US Pat. No. 10,073,226

METHOD FOR COUPLING AN OPTICAL FIBER TO AN OPTICAL OR OPTOELECTRONIC COMPONENT

IMEC VZW, Leuven (BE) Un...

1. A method for optically and mechanically coupling an optical fiber to an optical or optoelectronic component on a substrate, the method comprising:providing an optical fiber comprising a core and a cladding, the core being exposed at an end face of the optical fiber;
forming a light-induced self-written polymer waveguide core on the end face, the light-induced self-written polymer waveguide core extending from the fiber core;
bringing the light-induced self-written polymer waveguide core in proximity of an optical or optoelectronic component;
providing a liquid optical material, the liquid optical material embedding the light-induced self-written polymer waveguide core; and
curing the liquid optical material, thereby forming a polymer cladding layer encapsulating the light-induced self-written polymer waveguide core and mechanically attaching the optical fiber to the optical or optoelectronic component.

US Pat. No. 9,671,335

PHOTONICS INTEGRATED INTERFEROMETRIC SYSTEM AND METHOD

UNIVERSITEIT GENT, Ghent...

1. A photonics integrated system, the photonics integrated system comprising
a substrate,
an integrated interferometer integrated in the substrate and being configured for receiving radiation from an optical radiation
source, and

an integrated spectral filter integrated in the substrate and being configured for receiving radiation from the interferometer,
wherein the integrated interferometer has a period and the integrated spectral filter has a bandwidth such that the period
of the integrated interferometer is smaller than the bandwidth of the integrated spectral filter,

wherein the integrated spectral filter has a periodic transfer characteristic with a period and the system has a bandwidth
such that the period of the periodic transfer characteristic of the integrated spectral filter is larger than the bandwidth
of the system, and

wherein the system furthermore comprises a read-out means for reading out a multiple of channels of the spectrum analyser
in parallel.

US Pat. No. 9,839,123

SMART TEXTILE PRODUCT AND METHOD FOR FABRICATING THE SAME

IMEC VZW, Leuven (BE) Un...

1. A smart textile product comprising: a flexible and/or stretchable textile fabric comprising a plurality of electrically
conductive threads; at least one rigid electronic or optoelectronic component comprising at least one electrically conductive
pad, the at least one electrically conductive pad being configured to be in electrical contact with at least one of the plurality
of electrically conductive threads to provide at least one electrical connection between the at least one rigid electronic
or optoelectronic component and the at least one of the electrically conductive threads of the flexible and/or stretchable
textile fabric; and at least one elastomeric encapsulation layer, wherein the at least one electrical connection is embedded
in the at least one elastomeric encapsulation layer to provide a gradual transition in deformability between the flexible
and/or stretchable textile fabric and the at least one rigid component at a location of the at least one electrical connection,
wherein the at least one elastomeric encapsulation layer comprises a first elastomeric encapsulation layer comprising a first
elastomer and a second elastomeric encapsulation layer comprising a second elastomer different from the first elastomer.

US Pat. No. 9,595,668

SELF-RECTIFYING RRAM ELEMENT

IMEC vzw, Leuven (BE)

1. A memory cell comprising:
a first electrode and a second electrode formed of one of a metallic material or a semiconducting material;
a resistance-switching element formed between the first electrode and the second electrode;
a tunnel rectifier formed between and in physical contact with the resistance-switching element and the first electrode, wherein
the tunnel rectifier comprises a multi-layer tunnel stack comprising at least two dielectric layers each having a dielectric
constant (ki), a conduction band offset (?i), and a thickness, and wherein the resistance-switching element is configured to switch between a low resistance state and
a high resistance state in response to electrons tunneling through the tunnel rectifier,

wherein one of the dielectric layers has a higher dielectric constant, a lower conduction band offset and a higher thickness
compared to any other dielectric layer of the multi-layer tunnel stack, wherein the dielectric constant of one of the dielectric
layers does not exceed 12 and a dielectric constant of another one of the dielectric layers is between about 20 and about
50,

wherein the multi-layer tunnel stack is a stack of three dielectric layers, wherein a dielectric layer is sandwiched between
a first neighboring dielectric layer and a second neighboring dielectric layer and has:

a dielectric constant (k2) that is higher than dielectric constants of the first and second neighboring dielectric layers (k2>k1 and k2>k3);

a conduction band offset (?2) that is lower than conduction band offsets of the first and second neighboring dielectric layers (?2??1 and ?2
a thickness (t2) that is higher than thicknesses of the first and second neighboring dielectric layers (t2>t1 and t2>t3).

US Pat. No. 9,617,149

COMPACT FLUID ANALYSIS DEVICE AND METHOD TO FABRICATE

IMEC VZW, Leuven (BE)

15. A method for fabricating a device for analyzing a fluid sample, the method comprising:
providing a fluidic substrate comprising a micro-fluidic component embedded in the fluidic substrate and configured to propagate
a fluid sample via capillary force through the micro-fluidic component, and a means for providing a fluid sample connected
to the micro-fluidic component;

providing a lid; and
attaching the fluidic substrate to the lid to close the fluidic substrate at least partly,
wherein the fluidic substrate is a silicon fluidic substrate and the lid is CMOS chip,
wherein the CMOS chip includes at least one electrical component, and wherein the at least one electrical component is in
direct contact with the fluid sample when the fluid sample is present in the device,

and wherein the fluidic substrate is attached to the lid using a CMOS compatible bonding process.

US Pat. No. 9,553,586

FILED PROGRAMMABLE GATE ARRAY DEVICE WITH PROGRAMMABLE INTERCONNECT IN BACK END OF LINE PORTION OF THE DEVICE

IMEC VZW, Leuven (BE)

1. A field programmable gate array device, comprising: a front-end-of-line portion comprising a plurality of logic blocks;
a back-end-of-line portion comprising a plurality of metallization layers; and programmable interconnect points configured
to define signal routing between the logic blocks and/or between other portions of the field programmable gate array device,
wherein the interconnect points comprise one or more pass transistors, wherein each pass transistor is equipped with a dynamic
random access memory cell, the dynamic random access memory cell comprising a select transistor connected to a select line
and to a data line, and wherein the select transistor and/or the pass transistor is located in the back-end-of-line portion
of the field programmable gate array device; wherein both the pass transistor and the select transistor are located in the
back-end-of-line portion of the field programmable gate array device.

US Pat. No. 9,599,509

SPECTROSCOPY SYSTEM WITH DISPLACEMENT COMPENSATION AND SPECTROSCOPY METHOD USING THE SPECTROSCOPY SYSTEM

SAMSUNG ELECTRONICS CO., ...

1. A spectroscopy apparatus comprising:
detectors configured to obtain detection spectrums of respective detection areas that are located at different positions of
an object; and

an information processor configured to obtain a target spectrum of a target area by using position information of the detection
areas and the detection spectrums obtained by the detectors,

wherein the information processor is configured to obtain the target spectrum at a specific position of the target area by
applying weights to the detection spectrums of the respective detection areas based on the position information and combining
the weighted detection spectrums.

US Pat. No. 10,200,047

DTC-BASED PLL AND METHOD FOR OPERATING THE DTC-BASED PLL

IMEC VZW, Leuven (BE) St...

1. A phase locked loop for providing phase locking of an output signal to a reference signal, the phase locked loop comprising:a phase detector configured for detecting a phase difference between a signal at a first input and a signal at a second input,
a reference path configured for providing the reference signal to the first input of the phase detector,
a feedback loop configured for providing the output signal of the phase locked loop as a feedback signal to the second input of the phase detector,
a controllable oscillator configured for generating the output signal based at least on the phase difference between the reference signal and the feedback signal detected by the phase detector, the output signal having a period,
a digital-to-time converter, DTC, configured for delaying a signal that is provided at one of the first input and the second input of the phase detector, and
a randomization unit configured for:
generating an output stream of pseudo-random numbers, wherein the output stream of pseudo-random numbers are integers representing an integer number of VCO periods, and
adding the output stream of pseudo-random numbers to a delay calculation path, the delay calculation path being configured for calculating a delay value for the DTC by scaling a sum of an initial delay value and the output stream of pseudo-random numbers with the period of the output signal such that a target output of the phase detector remains substantially unchanged.

US Pat. No. 10,014,178

METHOD FOR DIFFERENTIAL HEATING OF ELONGATE NANO-SCALED STRUCTURES

IMEC VZW, Leuven (BE)

1. A method for manufacturing a semiconductor device, the method comprising:providing a semiconductor substrate;
producing, on the semiconductor substrate, at least one first elongate nanostructure oriented along a first axis and at least one second elongate nanostructure oriented along a second axis, the two axes being differently oriented one to the other;
heating the first and second nanostructures to different temperatures by (i) applying, to the first and second nanostructures at a first time, light having a wavelength and having a plane of polarization such that a difference in absorption of light occurs in the first and second nanostructures, thereby heating the first nanostructure to a first temperature, (ii) rotating the semiconductor substrate relative to the plane of polarization or rotating the plane of polarization relative to the semiconductor substrate, and (iii) after rotating the semiconductor substrate or the plane of polarization, applying the light to the first and second nanostructures at a second time, thereby heating the second nanostructure to a second temperature.

US Pat. No. 9,647,153

METHOD FOR FORMING THIN FILM CHALCOGENIDE LAYERS

IMEC VZW, Leuven (BE) Ki...

1. A method of forming a chalcogenide thin film containing copper and silicon, the method comprising:
depositing a copper layer on a substrate;
depositing a silicon layer on the copper layer, wherein an atomic ratio of the deposited copper to the deposited silicon is
at least 0.7;

after depositing the copper layer and the silicon layer, annealing the deposited layers in an inert atmosphere, thereby forming
a Cu-Si alloy layer; and

after annealing, performing a first selenization of the Cu-Si alloy layer, thereby forming the chalcogenide thin film comprising
a selenide.

US Pat. No. 9,698,262

VERTICAL FIN FIELD-EFFECT SEMICONDUCTOR DEVICE

IMEC VZW, Leuven (BE) Gl...

1. A vertical FinFET semiconductor device, comprising:
a semiconductor substrate that is not formed of silicon on insulator (SOI);
a current-blocking structure formed over the semiconductor substrate an extending in a lateral direction, the current-blocking
structure comprising:

a first layer of a first conductive type,
a layer of a second conductive type over the first layer, and
a second layer of the first conductive type over the layer of the second conductive type; and
at least one semiconductor fin formed on the current-blocking structure and extending in a vertical direction, wherein the
semiconductor fin has a first side and a second side opposing and substantially parallel to each other, and wherein the semiconductor
fin comprises:

a doped bottom portion contacting the second layer of the current-blocking structure,
a doped top portion formed vertically opposite to the doped bottom portion, and
a channel portion vertically interposed between the doped bottom portion and the doped top portion.

US Pat. No. 9,947,860

SPIN TORQUE MAJORITY GATE DEVICE

IMEC vzw, Leuven (BE)

1. A spin torque majority gate device, comprising:a free ferromagnetic layer;
a spin mixing layer formed above the free ferromagnetic layer;
a non-magnetic tunnelling layer formed above the spin mixing layer;
a plurality of input elements formed above the non-magnetic tunnelling layer, each of the input elements comprising a fixed ferromagnetic layer; and
an output element formed above the non-magnetic tunnelling layer and comprising a fixed ferromagnetic layer,
wherein the spin mixing layer is formed of a material having a spin coherence length that is greater than or equal to a maximum lateral distance between any two of the plurality of input elements.

US Pat. No. 9,811,051

APPARATUS AND METHOD FOR PERFORMING IN-LINE LENS-FREE DIGITAL HOLOGRAPHY OF AN OBJECT

IMEC VZW, Leuven (BE)

1. An apparatus for performing in-line lens-free digital holography of an object, comprising:
a point light source adapted for emitting coherent light; and
an image sensing device adapted and arranged for recording interference patterns resulting from interference from light waves
directly originating from the point light source and object light waves,

wherein the object light waves originate from light waves from the point light source that are scattered or reflected by the
object,

wherein the image sensing device comprises a plurality of pixels apportioned between disjoint subsets of pixels,
wherein the point light source comprises a broad wavelength spectrum light source and a pinhole structure, the broad wavelength
spectrum light source being arranged to emit light towards the pinhole structure,

wherein the image sensing device comprises, for each of the disjoint subsets of pixels, a respective narrow band wavelength
filter positioned above each pixel in the disjoint subset of pixels,

wherein a wavelength range of each narrow band wavelength filter falls within a broad wavelength spectrum of the point light
source,

wherein the wavelength ranges of the narrow band wavelength filters are non-overlapping, and
wherein the image sensing device is adapted for receiving and recording, while subjecting the object to light waves emitted
from the point light source, a plurality of interference patterns by a respective plurality of the disjoint subsets of pixels.

US Pat. No. 9,704,992

DRAIN EXTENSION REGION FOR TUNNEL FET

IMEC VZW, Leuven (BE) Ka...

1. A tunnel field-effect transistor, comprising:
a source-channel-drain structure, the source-channel-drain structure comprising:
a source region doped with a dopant element having a first dopant type and a first doping concentration,
a drain region doped with a dopant element having a second dopant type opposite to the first dopant type, and a second doping
concentration, and

a channel region situated between the source region and the drain region and having an intrinsic doping concentration or a
lowly doped concentration lower than the first doping concentration and the second doping concentration;

a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel
region and extending at the source side up to at least an interface between the source region and the channel region; and

an extension region in or on top of the channel region and solely at the side of the drain region, the extension region comprising
a layer with a doping level higher than 1018 at/cm3, wherein a surface of the layer coincides with a surface of the channel region in contact with the gate stack, the extension
region having a thickness less than 5 nm, the extension region extending up to a distance of at least 10 nm from the source
region.

US Pat. No. 9,691,872

III-V SEMICONDUCTOR DEVICE WITH INTERFACIAL LAYER

IMEC VZW, Leuven (BE)

1. A semiconductor structure comprising:
a substrate comprising a III-V material; and
a high-k interfacial layer overlaying the substrate, wherein the interfacial layer comprises a rare earth aluminate, and wherein
the high-k interfacial layer has a top surface facing away from the substrate and a bottom surface facing toward the substrate,
and wherein an aluminium content at the top surface is higher than at the bottom surface.

US Pat. No. 9,842,777

SEMICONDUCTOR DEVICES COMPRISING MULTIPLE CHANNELS AND METHOD OF MAKING SAME

IMEC vzw, Leuven (BE)

1. A method of fabricating a transistor device comprising a plurality of channels arranged in a vertical stack, the method
comprising:
providing a substrate;
forming on the substrate in at least a first channel region a plurality of vertically repeating layer stacks, each of the
layer stacks comprising a first layer, a second layer and a third layer stacked in a predetermined order, wherein each of
the first, second and third layers is formed of silicon, silicon germanium or germanium and has a different germanium concentration
compared to the other two of the first, second and third layers;

selectively removing the first layer with respect to the second and third layers from each of the layer stacks, such that
a gap interposed between the second layer and the third layer is formed in each of the layer stacks; and

selectively removing the second layer with respect to the third layer from each of the layer stacks, wherein removing the
second layer comprises at least partially removing the second layer through the gap, thereby defining the channels comprising
a plurality of vertically arranged third layers.

US Pat. No. 10,012,539

BRAGG GRATING, AND SPECTROSCOPY DEVICE INCLUDING THE BRAGG GRATING

SAMSUNG ELECTRONICS CO., ...

1. A Bragg grating disposed at each of opposite ends of a resonator for reflecting light of a certain wavelength band, the Bragg grating comprising:a core member extending from a waveguide of the resonator in a lengthwise direction of the waveguide;
a plurality of first refractive members protruding from the core member and spaced apart from each other along the lengthwise direction; and
a second refractive member filling spaces between the first refractive members and having a refractive index different from a refractive index of the first refractive members,
wherein the second refractive member comprises a solid material, and
wherein a width of the waveguide is greater than a width of the core member and is less than widths of the plurality of first refractive members.

US Pat. No. 9,818,524

COUPLING ELEMENT FOR DIFFERENTIAL HYBRID COUPLER

IMEC VZW, Leuven (BE)

1. A coupling element arranged in a first layer and a second layer that are separated from each other by an intermediate dielectric
layer, the coupling element comprising:
a first coil arranged such that:
at least one turn of the first coil extends in the first layer, and
another turn of the first coil extends in the second layer;
a second coil arranged such that:
at least one turn of the second coil extends in the first layer and along at least a portion of the first coil arranged in
the first layer, and

another turn of the second coil extends in the second layer and along at least a portion of the first coil arranged in the
second layer;

a third coil arranged such that:
at least one turn of the third coil extends in the first layer and superposes at least a portion of the first coil arranged
in the second layer, and

another turn of the third coil extends in the second layer and superposes at least a portion of the first coil arranged in
the first layer; and

a fourth coil arranged such that:
at least one turn of the fourth coil extends in the first layer and superposes at least a portion of the second coil arranged
in the second layer, and

another turn of the fourth coil extends in the second layer and superposes at least a portion of the second coil arranged
in the first layer.

US Pat. No. 9,799,632

METHOD FOR ALIGNING MICRO-ELECTRONIC COMPONENTS

IMEC VZW, Leuven (BE)

1. An assembly of at least two components, comprising:
a first component and a second component;
wherein each of the first component and the second component comprises a contact area covered by a wetting layer;
wherein each of the first component and the second component comprises means for containing a liquid on the respective wetting
layer;

wherein each of the first component and the second component comprises one or more conductor lines running along a circumference
of the respective contact area, wherein the one or more conductor lines of the first component are arranged to face the one
or more conductor lines of the second component;

and wherein at least one of the first component or the second component is provided with means for applying an electrical
charge to the respective one or more conductor lines.

US Pat. No. 10,115,961

METHOD FOR THE FABRICATION OF A THIN-FILM SOLID-STATE BATTERY WITH NI(OH)2 ELECTRODE, BATTERY CELL, AND BATTERY

IMEC VZW, Leuven (BE) Pa...

1. A method for fabricating a thin-film solid-state battery cell on a substrate comprising a first current collector layer, the method comprising:depositing above the first current collector layer a first electrode layer,
wherein the first electrode layer is a nanoporous composite layer comprising a plurality of pores having pore walls, and
wherein the first electrode layer comprises a mixture of a dielectric material and an active electrode material;
depositing above the first electrode layer a porous dielectric layer; and
depositing directly on the porous dielectric layer a second electrode layer,
wherein depositing the second electrode layer comprises depositing a porous Ni(OH)2 layer using an electrochemical deposition process.

US Pat. No. 9,874,821

METHOD FOR HOTSPOT DETECTION AND RANKING OF A LITHOGRAPHIC MASK

IMEC VZW, Leuven (BE)

1. A method for detecting and ranking hotspots in a lithographic mask for printing a pattern on a substrate, the method comprising:
providing a test substrate comprising a plurality of die areas;
printing the pattern through the mask on the plurality of die areas with a lithographic tool, wherein printing the pattern
includes incrementing a lithographic parameter of the tool from an initial set value of the parameter used when printing the
pattern on one of the die areas to one or more other set values of the parameter used when printing the pattern on others
of the die areas, and wherein incrementing the parameter comprises increasing or decreasing the set value of the parameter
stepwise;

determining a location of one or more repeating defects, wherein the repeating defects occur at a first die area associated
with a first set value of the parameter and at a second die area associated with a second set value of the parameter;

determining for each of the one or more repeating defects an actual parameter value associated with a location of the defect;
and

ranking the defects based on whether each defect is a repeating defect and based on the actual parameter values.

US Pat. No. 9,773,200

MINIATURE INTEGRATED SENSOR CIRCUIT

IMEC VZW, Leuven (BE)

1. A miniature integrated CMOS sensor circuit comprising:
disposed within an area of less than 0.1 mm2, a time-domain ADC module, a digital logic and control module, a data transmitter module, a power circuit module, a voltage
reference module, an identification code tag, and an RF coil,

wherein the RF coil is configured to receive power from and for telemetry communication with an external device unit,
wherein the power circuit module and the voltage reference module are configured to generate a stable reference voltage from
the power received by the RF coil,

and wherein the sensor circuit is configured to derive a periodic clock signal from a signal received from the external device
unit or from the stable reference voltage.

US Pat. No. 9,756,270

IN-PIXEL AMPLIFICATION DEVICE AND METHOD

IMEC vzw, Leuven (BE) Vr...

1. A pixel for converting incident subatomic particles into an output voltage signal, the pixel comprising:
a particle-detector adapted to receive subatomic particles and generate an input voltage signal corresponding to an intensity
of the received subatomic particles; and

a passive amplifier comprising:
a voltage-controlled capacitor adapted to receive and store the input voltage signal at a first terminal, wherein the capacitance
of the voltage-controlled capacitor is variable between a first capacitance and a second capacitance in response to a capacitor
control voltage, wherein the voltage-controlled capacitor comprises:

the first terminal,
a second terminal adapted to receive the capacitor control voltage, and
a third terminal connected to a constant voltage supply, and wherein the capacitor control voltage at the second terminal
controls the capacitance of the voltage-controlled capacitor; and

a first switch, connected to the first terminal of the voltage-controlled capacitor, adapted to selectively provide the input
voltage signal to the voltage-controlled capacitor,

wherein varying the voltage-controlled capacitor from the first capacitance to the second capacitance subjects the input voltage
signal stored at the first terminal to a gain, thereby generating an output voltage signal at the first terminal.

US Pat. No. 9,634,185

OPTICAL SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE DEVICE

IMEC VZW, Leuven (BE)

1. A method for manufacturing an optical semiconductor device, comprising:
providing a substrate comprising a layer of semiconductor material, wherein the semiconductor material has a diamond-cubic
structure;

patterning the layer of semiconductor material having the diamond-cubic structure to form a fin sandwiched between a first
confined space and a second confined space, the first confined space being adjacent to a first major sidewall of the fin and
the second confined space being adjacent to a second major sidewall of the fin, whereby the first confined space and the second
confined space comprise an oxide material in contact with the first major sidewall and the second major sidewall, wherein
the first confined space is smaller than the second confined space; and

annealing the substrate, thereby forming at the base of the fin and across a full width of the fin a slab of semiconductor
material having a diamond-hexagonal structure.

US Pat. No. 9,947,591

METHOD FOR MANUFACTURING A SI-BASED HIGH-MOBILITY CMOS DEVICE WITH STACKED CHANNEL LAYERS, AND RESULTING DEVICES

IMEC VZW, Leuven (BE)

1. A method for manufacturing a Si-based high-mobility CMOS device, wherein a Ge or SixGe1?x channel layer and a III-V semiconductor channel layer are co-integrated on a silicon substrate, the method comprising the steps of:a) providing a silicon substrate having a first insulation layer on top and a trench extending through the insulation layer and into the silicon;
b) manufacturing a III-V semiconductor channel layer above the first insulation layer by means of, in sequence, depositing a first dummy layer of a sacrificial material above the first insulation layer and in the trench, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching the sacrificial material via first holes made in the first oxide layer followed by selective area growth with the III-V semiconductor material;
c) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; and
d) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by means of, in sequence, depositing a second dummy layer of a sacrificial material above the second insulation layer and in the trench, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching the sacrificial material via second holes made in the second oxide layer followed by selective area growth with germanium or silicon-germanium.

US Pat. No. 9,832,051

FRONT-END SYSTEM FOR A RADIO DEVICE

IMEC VZW, Leuven (BE) Vr...

1. A front-end system for a radio device comprising:
a charge generator circuit arranged for receiving a digital baseband signal, and comprising a first converter circuit arranged
for calculating at least one charge value based on the digital baseband signal, wherein the at least one charge value comprises
a digital number, and a second converter circuit arranged for converting the at least one charge value into at least one electrical
charge, and

a modulator circuit arranged for generating a radio frequency signal based on the at least one electrical charge and at least
one local oscillator signal.

US Pat. No. 9,791,621

INTEGRATED SEMICONDUCTOR OPTICAL COUPLER

IMEC VZW, Leuven (BE)

1. A method for fabricating an integrated semiconductor photonics device, the method comprising:
providing a first substrate having on its top surface a monocrystalline semiconductor layer suitable for supporting an optical
mode;

forming a homogeneous and conformal first dielectric layer on a planar upper surface of the monocrystalline semiconductor
layer;

providing a dielectric waveguide core on the first dielectric layer, wherein the dielectric waveguide core is optically coupled
to a first region of the monocrystalline semiconductor layer through the first dielectric layer;

after providing the dielectric waveguide core on the first dielectric layer, depositing a second dielectric layer on the dielectric
waveguide core, thereby covering the dielectric waveguide core, and;

annealing the dielectric waveguide core to drive hydrogen out of the dielectric waveguide core.

US Pat. No. 9,640,411

METHOD FOR MANUFACTURING A TRANSISTOR DEVICE COMPRISING A GERMANIUM CHANNEL MATERIAL ON A SILICON BASED SUBSTRATE, AND ASSOCIATED TRANSISTOR DEVICE

IMEC VZW, Leuven (BE)

1. A method for manufacturing a transistor device comprising a germanium channel material on a silicon substrate, wherein
the silicon substrate is a (100) oriented substrate, the method comprising:
providing an shallow trench isolation (STI) substrate comprising a silicon protrusion embedded in STI dielectric structures;
partially recessing the silicon protrusion in order to provide a trench in between adjacent STI structures, and to provide
a V-shaped groove at an upper surface of the recessed protrusion, wherein the V-shaped groove at an upper surface of the recessed
protrusion is defined by {111} oriented facets;

growing a Si1-xGex strain relaxed buffer (SRB) layer in the trench; and

growing a Germanium based channel layer on the Si1-xGex SRB layer,

wherein the Si1-xGex SRB layer comprises a germanium content x that is within the range of 20% to 99%, and wherein the SRB layer has a thickness
less than 400 nm.

US Pat. No. 10,090,036

NON-VOLATILE MEMORY CELL HAVING PINCH-OFF FERROELECTRIC FIELD EFFECT TRANSISTOR

IMEC vzw, Leuven (BE)

1. A non-volatile memory cell, comprising:a pinch-off ferroelectric field effect transistor (FET) comprising a channel layer electrically connecting a source region and a drain region, wherein each of the channel layer, the source region and the drain region is formed of a semiconductor region doped with a first dopant type; and
at least one select device electrically connected in series to the pinch-off ferroelectric FET.

US Pat. No. 10,033,078

TUNABLE MAGNONIC CRYSTAL DEVICE AND FILTERING METHOD

IMEC VZW, Leuven (BE)

1. A tunable magnonic crystal device, comprising:a spin wave waveguide;
a magnonic crystal structure provided in or on the spin wave waveguide, the magnonic crystal structure being adapted for selectively filtering a spin wave spectral component of a spin wave propagating through the spin wave waveguide so as to provide a filtered spin wave; and
a magneto-electric cell operably connected to the magnonic crystal structure, wherein the magneto-electric cell comprises an electrode for receiving a control voltage, and wherein adjusting the control voltage of the electrode controls a spectral parameter of the filtered spectral component of the spin wave via an interaction, dependent on the control voltage, between the magneto-electric cell and a magnetic property of the magnonic crystal structure.

US Pat. No. 9,847,109

MEMORY CELL

IMEC VZW, Leuven (BE)

1. A memory cell comprising:
a first transistor, wherein the first transistor is a Vt-modifiable n-channel transistor having a control electrode, a first
main electrode, and a second main electrode;

a second transistor, wherein the second transistor is a Vt-modifiable p-channel transistor having a control electrode, a first
main electrode, and a second main electrode; and

a differential sense amplifier,
wherein the control electrodes of the first and second transistors are connected together, wherein the first main electrodes
of the first and second transistors are connected together, wherein the differential sense amplifier is connected to the second
main electrodes of the first and the second transistors, and wherein the differential sense amplifier is adapted for sensing
a current difference between the first transistor and the second transistor.

US Pat. No. 9,632,248

INTEGRATED PHOTONIC COUPLER

IMEC VZW, Leuven (BE) Un...

1. An integrated photonic device comprising:
a substrate;
an integrated waveguide formed on the substrate, the integrated waveguide being configured to conduct light of a predetermined
wavelength;

a sub-wavelength grating integrated in the integrated waveguide, the sub-wavelength grating providing a first periodic variation
of a refractive index in the integrated waveguide in at least one first spatial direction, wherein the first periodic variation
has a first pitch that is less than half of the predetermined wavelength; and

a diffracting grating for at least one of (1) coupling light of the predetermined wavelength into the integrated waveguide
via the sub-wavelength grating or (2) coupling light of the predetermined wavelength out of the integrated waveguide via the
sub-wavelength grating, the diffracting grating (i) providing a second periodic variation of the refractive index in at least
one second spatial direction, wherein the second periodic variation has a second pitch that is at least half of the predetermined
wavelength and (ii) being at least one of:

(a) arranged above the sub-wavelength grating with respect to the substrate; or
(b) partially etched in the sub-wavelength grating,
wherein the sub-wavelength grating is etched into the integrated waveguide to a first depth with respect to the substrate
and the diffracting grating is partially etched into the sub-wavelength grating to a second depth with respect to the substrate,

wherein the second depth is less than the first depth with respect to the substrate.

US Pat. No. 10,241,471

AUTOFOCUS SYSTEM AND METHOD IN DIGITAL HOLOGRAPHY

IMEC TAIWAN CO., Hsinchu...

1. An autofocus method for determining a focal plane for at least one object, the method comprising:reconstructing a holographic image of the at least one object such as to provide a reconstructed image at a plurality of different focal depths,
wherein the reconstructed image comprises a real component and an imaginary component for jointly encoding phase and amplitude information;
performing a first edge detection on the real component for at least two depths of the plurality of different focal depths and a second edge detection on the imaginary component for the at least two depths;
obtaining a first measure of clarity for each of the at least two depths based on a first measure of statistical dispersion with respect to the first edge detection and a second measure of clarity for each of the at least two depths based on a second measure of statistical dispersion with respect to the second edge detection; and
determining the focal plane for the at least one object based on a comparison of a scalar measure of clarity for the at least two depths,
wherein the scalar measure is based on the first measure of clarity and the second measure of clarity.

US Pat. No. 9,870,757

LOW POWER DIGITAL DRIVING OF ACTIVE MATRIX DISPLAYS

IMEC VZW, Leuven (BE)

1. Digital driving circuitry for driving an active matrix display, the display comprising a plurality of pixels logically
organized in a plurality of rows and a plurality of columns, each pixel comprising a light emitting element, wherein the driving
circuitry comprises:
current driver circuitry for each of the plurality of columns and configured to drive a predetermined current through the
corresponding column, the predetermined current being proportional to the number of pixels that are ON in that column,

a first line with a first resistive path and a second line with a second resistive path between which the predetermined current
is configured to be driven through each column, wherein the resistance of the first resistive path is substantially equal
to the resistance of the second resistive path over a length of the first and second lines for all light emitting elements
in each column,

digital select line driving circuitry configured to sequentially select the plurality of rows, and
digital data line driving circuitry configured to write digital image codes to the pixels in a selected row, synchronized
with the digital select line driving; circuitry;

wherein each current driver circuitry contains a counter for storing a natural number equal to the number of light emitting
elements that are ON in the corresponding column at a given moment in time, wherein the counter is synchronized with the select
line driving circuitry and responsive to changes in the digital data line driving circuitry.

US Pat. No. 9,608,094

HETEROSECTION TUNNEL FIELD-EFFECT TRANSISTOR (TFET)

IMEC VZW, Leuven (BE)

1. A tunnel field-effect transistor, comprising:
a doped source region comprising a source semiconductor material having a source doping type;
a doped drain region comprising a drain semiconductor material having a drain doping type opposite to the source doping type;
a channel region comprising a lowly doped channel semiconductor material or an undoped channel semiconductor material, the
channel region situated between the doped source region and the doped drain region;

at least one doped heterosection between the doped source region and the channel region, the at least one doped heterosection
having a heterosection doping type which is identical to the source doping type, the at least one doped heterosection comprising
a semiconductor material which is at least partially different from semiconductor materials of neighboring regions with which
the at least one doped heterosection is in direct physical contact, the at least one doped heterosection having a dielectric
constant lower than 10, and the at least one doped heterosection having a thickness not larger than 10 nm, wherein the neighboring
regions of the at least one doped heterosection comprise at least the doped source region and at least one region selected
from the group consisting of the channel region, a pocket region, and another doped heterosection, and wherein the pocket
region in between the at least one doped heterosection and the channel region comprises a pocket semiconductor material which
is different from the semiconductor material of the at least one doped heterosection and with a pocket doping type which is
opposite to the source doping type.

US Pat. No. 9,972,622

METHOD FOR MANUFACTURING A CMOS DEVICE AND ASSOCIATED DEVICE

IMEC VZW, Leuven (BE)

1. A method for manufacturing a CMOS device, the CMOS comprising a first transistor structure of a first conductivity type in a first region and a second transistor structure of a second conductivity type in a second region, the method comprising:providing a semiconductor base layer having a main upper surface;
epitaxially growing a germanium layer on the main upper surface of the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed;
performing an anneal step;
thinning the germanium layer;
patterning the germanium layer into fin structures having a longitudinal direction parallel to the main upper surface or into vertical wire structures having a main direction perpendicular on the main upper surface;
laterally embedding the fin structures or vertical wire structures in a dielectric layer;
providing a masking layer covering the first region, leaving the second region exposed;
selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench; and
growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench, wherein at least an upper portion of the protrusion is suitable for being used as a channel structure of the transistor structure of a second conductivity type and wherein at least an upper portion of the germanium fin structure or germanium wire structure is suitable for being used as a channel structure of the transistor structure of a first conductivity type,
wherein the anneal step is performed prior to thinning the germanium layer.

US Pat. No. 9,728,813

METHOD FOR FABRICATING SOLID-STATE THIN FILM BATTERIES

IMEC VZW, Leuven (BE)

1. A method for fabricating a thin film solid-state Li-ion battery comprising a first electrode layer, a solid electrolyte
layer, and a second electrode layer, the method comprising:
depositing an initial layer stack on a substrate, wherein the initial layer stack comprises a first Li-free layer comprising
a first electrode material compound, and a second Li-free layer comprising an electrolyte material compound; and

after depositing the initial layer stack, performing a lithiation step, the lithiation step comprising forming a Li-compound
layer on the initial layer stack or between the first and second layers to incorporate Li in the first layer and in the second
layer, thereby forming a stack of a first electrode layer and a solid electrolyte layer.

US Pat. No. 10,014,437

OPTICAL SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE DEVICE

IMEC VZW, Leuven (BE)

1. An optical semiconductor device comprising:a fin on a substrate, wherein the fin comprises a semiconductor material having a diamond-cubic structure, wherein the fin is sandwiched in between a first confined space and a second confined space, wherein a width of the first confined space is smaller than a width of the second confined space; and
a slab of the semiconductor material having a diamond-hexagonal structure, wherein the slab is situated across a full width of the fin at a base of the fin, wherein the slab has a thickness of from 2 nm to 50 nm.

US Pat. No. 9,982,360

METHOD FOR TRANSFERING A GRAPHENE LAYER

IMEC VZW, Leuven (BE)

1. A method for transferring a graphene layer from a metal substrate to a second substrate, comprising:a. providing a graphene layer on a metal substrate;
b. adsorbing hydrogen atoms on the metal substrate by passing protons through the graphene layer by providing a photo acid generator material in contact with the graphene layer, the photo acid generator material being configured to generate protons upon exposure to a certain light, and exposing the photo acid generator material to the certain light, thereby generating the protons;
c. treating the metal substrate having adsorbed hydrogen atoms thereon so as to form hydrogen gas from the adsorbed hydrogen atoms, thereby detaching the graphene layer from the metal substrate; and
d. transferring the graphene layer to a second substrate.

US Pat. No. 9,874,701

ADIABATIC COUPLER

UNIVERSITEIT GENT, Ghent...

1. A system for selectively adiabatically coupling electromagnetic waves from one waveguide to another waveguide, the system
comprising:
a first waveguide portion and a second waveguide portion, the first waveguide portion and the second waveguide portion having
a substantially different surface normal cross-section causing a different interaction of the first and second waveguides
with the environment, and the first waveguide portion and the second waveguide portion being positioned with respect to each
other in a coupling region so that under first predetermined environmental conditions coupling of electromagnetic waves between
the first waveguide portion and the second waveguide portion can occur and under second predetermined environmental conditions
substantially no coupling of electromagnetic waves between the first waveguide portion and the second waveguide portion can
occur; and

a fluid positioning means for selectively positioning at least a first fluid such that it is selectively either simultaneously
overlaying both said first waveguide portion and said second waveguide portion in the coupling region thus inducing first
predetermined environmental conditions or not overlaying both said first waveguide portion and said second waveguide portion
in the coupling region thus inducing second predetermined environmental conditions.

US Pat. No. 9,842,733

METHOD FOR DISSOLVING CHALCOGEN ELEMENTS AND METAL CHALCOGENIDES IN NON-HAZARDOUS SOLVENTS

IMEC VZW, Leuven (BE)

1. A method of preparing a chalcogen-containing solution that is hydrazine free and hydrazinium free, the method comprising:
providing a predetermined amount of a first material consisting of pure elemental chalcogen;
providing a predetermined amount of a second material consisting of pure elemental sulfur;
providing an amine solvent; and
combining the predetermined amount of the first material consisting of the pure elemental chalcogen and the predetermined
amount of the second material consisting of the pure elemental sulfur in the amine solvent at ambient temperature, whereby
the first material consisting of the pure elemental chalcogen and the second material consisting of the pure elemental sulfur
are dissolved in the amine solvent, thereby forming a chalcogen-containing solution that is hydrazine free and hydrazinium
free.

US Pat. No. 9,806,737

CIRCUIT AND METHOD FOR CONVERTING ANALOG SIGNAL TO DIGITAL VALUE REPRESENTATION

IMEC VZW, Leuven (BE)

1. A circuit for converting an analog signal to a digital value representation, comprising:
an incremental sigma-delta analog-to-digital converter (ADC) having an input for receiving the analog signal and an output
for outputting a sequence of digital values corresponding to samples of the received analog signal;

a first input line for providing a primary analog signal representing a sensor measurement to the input of the incremental
sigma-delta ADC;

a second input line for providing a secondary analog signal to the input of the incremental sigma-delta ADC,
wherein the input of the incremental sigma-delta ADC receives the primary analog signal from the first input line during a
first period of analog-to-digital conversion and receives the secondary analog signal from the second input line during a
second period of analog-to-digital conversion; and

a filter configured to receive the sequence of digital values from the incremental sigma-delta ADC, to weight the digital
values in the sequence of digital values and to output a single digital value representing the sensor measurement, wherein
the second period is at least partly overlapping with a third period during which a voltage representing the sensor measurement
settles.

US Pat. No. 10,082,624

SYSTEM FOR COUPLING RADIATION INTO A WAVEGUIDE

UNIVERSITEIT GENT, Ghent...

1. A photonics integrated device for coupling radiation using flood illumination, the device comprising:an integrated waveguide,
a coupler grating at a surface of the device for coupling radiation from said flood illumination towards the integrated waveguide, and
a grating for blocking, reflecting or redirecting radiation away from the coupler grating and away from the integrated waveguide, the grating for blocking, reflecting or redirecting at the surface of the device, wherein the grating for blocking, reflecting or redirecting radiation away from the coupler grating is positioned relative to the coupler grating so as to prevent at least some radiation from said flood illumination, impinging at the grating for blocking, reflecting or redirecting radiation away from the coupler grating and thus impinging at a position of said surface away from the coupling grating, from being reflected within the device towards the coupler grating;wherein the distance between the coupler grating and the grating for blocking, reflecting or redirecting radiation away from the coupler grating is between 0,1 and 1,3 times x, x being determined as (neglecting multipath interference)with i =1. . . n and n corresponding with the number of layers in the photonics integrated device between the top surface and a bottom reflective surface of the photonics integrated device, where radiation is reflected, di being the thickness of the i-th layer, and ?i =arcsin(n0·sin(?0)/ ni) being the direction of propagation in the i-th layer with ni the refractive index of the i-th layer, ?0 being the angle of incidence on the top surface and n0 the refractive index of the medium from which the radiation is impinging,the coupler grating being optimized for an angle of incidence ?0.

US Pat. No. 10,048,212

QUALITY ASSESSMENT OF DIRECTED SELF-ASSEMBLING METHOD

IMEC VZW, Leuven (BE)

1. A method for evaluating the quality of a directed self-assembling method used for generating directed self-assembling patterns, the method comprising:obtaining at least one set of parameter values for a parameterized set of processing steps and material properties characterizing the directed self-assembling method, thus characterizing a specific directed self-assembling method used for generating a directed self-assembled layer;
obtaining, using a scatterometer, a scattered radiation pattern on the directed self-assembled layer, wherein the directed self-assembled layer is obtained by applying the directed self-assembling method characterized by the set of parameter values on a guiding pattern comprising a number of induced, intended defects, thus obtaining scattered radiation pattern results for the directed self-assembled pattern; and
determining, using a computing device and based on the scattered radiation pattern results, a qualification score identifying a robustness of the directed self-assembling method to the induced, intended defects in the guiding pattern and correlating the qualification score with the set of parameter values.

US Pat. No. 10,043,798

BURIED INTERCONNECT FOR SEMICONDUCTOR CIRCUITS

IMEC VZW, Leuven (BE)

1. A semiconductor circuit, comprising:a front-end-of-line comprising a plurality of transistors, each transistor comprising a source region, a drain region, and a gate region, wherein the gate region is situated between the source region and the drain region and comprises a gate electrode, wherein the gate electrode is electrically isolated from its surroundings;
a first buried interconnect situated in the front-end-of-line and electrically connected to the gate region from below through a bottom contact portion of the gate electrode, the first buried interconnect having a length extension in a direction orthogonal to a direction of a length extension of the gate electrode and being laterally arranged between the source/drain regions or the plurality of transistors;
a back-end-of-line comprising a first contact area of a metal layer; and
a middle-end-of-line comprising a first local interconnect configured to electrically connect the first buried interconnect to the first contact area of the metal layer of the back-end-of-line, wherein the first local interconnect is situated distant from a gate electrode of a first transistor of the plurality of transistors and distant from a neighboring gate electrode of a second transistor of the plurality of transistors, and in a region where there are no source or drain regions, and wherein the plurality of transistors is a plurality of fin-based transistors, each fin-based transistor comprising a fin extending between a source region and a drain region of the fin-based transistor.

US Pat. No. 9,983,154

METHOD FOR INSPECTING A PATTERN OF FEATURES ON A SEMICONDUCTOR DIE

IMEC VZW, Leuven (BE)

1. A method for detection of one or more defects in a printed pattern of geometrical features on a semiconductor die, the printed pattern comprising an array of geometrical features having a nominal pitch, the method comprising:determining one or more deviations from the nominal pitch in the printed pattern; and
comparing the printed pattern with a second version of the printed pattern, wherein the second version has the same or similar pitch deviations as the printed pattern.

US Pat. No. 9,948,446

TELECOMMUNICATIONS DEVICE COMPRISING AN ELECTRICAL BALANCE DUPLEXER AND METHOD FOR BALANCING THE ELECTRICAL BALANCE DUPLEXER

IMEC VZW, Leuven (BE) Vr...

1. A telecommunications device comprising:an electrical balance duplexer connected to an output node of a transmission path, an input node of a receive path, an antenna, and a tunable impedance, wherein the electrical balance duplexer is configured to isolate the transmission path from the receive path by tuning the tunable impedance; and
a tuning circuit for tuning the tunable impedance,
wherein the tuning circuit comprises:
amplitude detectors for measuring voltage amplitudes at each of the connections between the electrical balance duplexer and the transmission path, between the electrical balance duplexer and the receive path, and between the electrical balance duplexer and the tunable impedance;
phase detectors for measuring voltage phase differences between each of the connections between the electrical balance duplexer and the transmission path, between the electrical balance duplexer and the receive path, and between the electrical balance duplexer and the tunable impedance;
an impedance sensor for measuring an input impedance of the electrical balance duplexer at the connection between the electrical balance duplexer and the tunable impedance; and
a processing unit operatively connected to the amplitude detectors, the phase detectors, the impedance sensor, and the tunable impedance, wherein the processing unit is configured to:
calculate an optimized impedance value from the voltage amplitudes, the voltage phase differences, and the input impedance of the electrical balance duplexer; and
tune the tunable impedance towards the optimized impedance value.

US Pat. No. 9,941,151

METHOD FOR PRODUCING AN INTEGRATED CIRCUIT INCLUDING A METALLIZATION LAYER COMPRISING LOW K DIELECTRIC MATERIAL

IMEC vzw, Leuven (BE) Ka...

1. A method of manufacturing a metallization layer of an integrated circuit device, the metallization layer comprising a via level and a trench level, the trench level on top of the via level, the via level comprising a first porous dielectric layer with a pattern of one or more metal-filled vias embedded therein, the trench level comprising a second porous dielectric layer with a pattern of one or more metal conductors embedded therein, the method comprising:depositing the first porous dielectric layer;
depositing a layer of a template material directly on the first porous dielectric layer;
annealing and cooling the first porous dielectric layer and the layer of the template material so that the template material diffuses into the pores of the first porous layer, thereby filling the pores over the complete thickness of the porous layer, thus forming a pore-filled dielectric layer, and so that a template layer remains on top of the pore-filled dielectric layer; and
performing a dual damascene process comprising:
forming via openings in the pore-filled dielectric layer according to the via pattern;
forming trenches in the template layer according to the conductor pattern;
filling the via openings and trenches with a barrier layer and a metal, thereby creating metal-filled vias and metal conductors;
removing the remaining template layer on top of the pore-filled dielectric layer;
removing the template material from the pores of the pore-filled dielectric layer;
depositing the second porous dielectric layer directly on top of the first porous layer, thereby embedding the metal conductors in the material of the second porous layer; and
planarizing the second porous dielectric layer and the metal conductors.

US Pat. No. 9,909,992

OPTICAL SPECTROMETER WITH MATCHED éTENDUE

IMEC VZW, Leuven (BE)

1. An optical system configured to characterize a radiation beam, the optical system comprising:
an optical radiation guiding system, comprising:
a collimator configured to collimate the radiation beam into a collimated radiation beam; and
a beam shaper configured to distribute power of the collimated radiation beam over a discrete number of line shaped fields,
wherein a spectrum of the collimated radiation beam entering the beam shaper is delivered to each of the discrete number of
line shaped fields; and

a spectrometer chip, wherein the spectrometer chip is configured to process the spectrum of the collimated radiation beam
in each of the discrete number of line shaped fields coming from the beam shaper.

US Pat. No. 9,911,504

NON-VOLATILE MEMORY ARRAY USING ELECTROMECHANICAL SWITCHES FOR CELL STORAGE

IMEC vzw, Leuven (BE)

1. A data storage cell for storing data, the data storage cell comprising:
a first nano electromechanical switch comprising a first moveable beam fixed to a first anchor, a first control gate and a
second control gate, a first output node against which the first moveable beam can be positioned, wherein the first output
node is physically and electrically isolated from the first control gate and the second control gate;

a second nano electromechanical switch comprising a second moveable beam fixed to a second anchor, a third control gate and
a fourth control gate, wherein the second moveable beam can also be positioned against the first output node, wherein the
first output node is physically and electrically isolated from the third control gate and the fourth control gate, wherein
one or both of the nano electromechanical switches are vertical nano electromechanical switches, wherein the beam is oriented
vertically with respect to an average plane through both control gates of the switch, the first nano electromechanical switch
and the second nano electromechanical switch being configured for selecting a first or a second state of the data storage
cell, the first nano electromechanical switch and the second nano electromechanical switch configured such that the second
moveable beam is not positioned against the first output node when the first moveable beam is positioned against the first
output node, wherein the first and the second anchors are connected with respective word lines for enabling the movement of
the first moveable beam and the second moveable beam, respectively, and wherein the first and second control gate and the
third and the fourth control gate are connected with data lines, respectively, for providing data to be stored to the data
storage cell; and

a first read transistor comprising a single FET, the single FET comprising a transistor gate connected to the first output
node, a transistor drain directly connected to a read bit line that is separate from the first output node, and a transistor
source directly connected to a DC bias or a second data line, wherein a read current is routed from the read bit line through
the single FET to the DC bias or the second data line.

US Pat. No. 9,859,247

METHOD FOR BONDING BARE CHIP DIES

Nederlandse Organisatie v...

14. A bonding method of a micro-electronic component, in particular, a bare die component having one or more electrical connection
pads, on a substrate having on its substrate surface a connection pad structure arranged for interconnecting the micro- electronic
component via a respective one or more connection pads, the method comprising the steps of:
providing a donor film comprising a solder paste and a dynamic release layer;
aligning a laser beam of a laser system and guiding the donor film distanced from the substrate surface;
impinging the laser beam on the dynamic release layer; in such a way that the dynamic release layer is activated to cover
a selected part of the connection pads or the connection pad structure with solder paste transferred from the donor film;
wherein the laser beam is restricted in timing and energy, in such a way that the transferred solder paste includes flux consisting
of more than 10% volume percent of flux;

administering the micro-electronic component with its one or more electrical connection pads to the pad structure, so that
the solder paste on one or both of the pads and the pad structure forms an electrical connection between the pad structure
and a respective pad; and

reflowing the solder paste between the pads and the pad structure to bond the micro-electronic component with a shear strength
of more than 1 Mpa.

US Pat. No. 9,847,262

METHOD AND APPARATUS FOR REAL-TIME MONITORING OF PLASMA ETCH UNIFORMITY

IMEC VZW, Leuven (BE)

1. A method for monitoring an etch uniformity of a plasma etching process for removing a layer of material from a substrate,
wherein the plasma etching process is a capacitively coupled plasma etching process, comprising:
providing a substrate covered by a layer to be etched, wherein the substrate is placed on a powered electrode;
generating a plasma in an area between the layer to be etched and a counter-surface comprising a grounded electrode mounted
opposite the layer and substantially parallel to the layer, whereby material is progressively removed from the layer in a
plasma etching process, the plasma emitting light, wherein no other light source is provided besides the plasma, wherein light
striking a surface of the grounded electrode is partially reflected towards the layer, wherein light striking the layer is
partially reflected from a top surface of the layer and partially refracted through the layer towards the substrate, and wherein
the refracted light reflects from a substrate surface and is refracted once again at the top surface of the layer, where the
refracted light combines with the reflected light to form an interference pattern due to a difference in optical paths of
the reflected light and the refracted light, wherein the interference patterns are primarily due to light beams which have
undergone multiple reflections off the grounded electrode, wherein a size and a material of the counter-surface, a size and
a material of the substrate and the layer, and a distance between the layer and the counter surface are each configured so
that the light interference patterns are primarily due to reflections of light beams taking place in the area between the
layer and the counter-surface, and wherein the light beams are directed according to a Brewster angle of the material of the
counter-surface;

measuring, by an optical emission spectroscopy detector at a lateral location with respect to the area, one or more spectral
components of light emitted from the area wherein the emission spectroscopy detector comprises a lens coupled to an optical
fiber that is coupled to a spectrometer, wherein the lens is arranged to receive light from a totality of the top surface
of the layer from a plurality of directions, wherein the light emitted from the area passes through a polarization filter
before entering the optical detector, wherein the filter is configured to admit only light with a given polarization into
the optical detector, wherein the polarization filter is configured so that only s-polarized light passes the polarization
filter;

arranging the counter-surface relative to the layer so that the optical detector detects oscillations of at least one of the
one or more spectral components as a function of time, the oscillations being caused by detected light interference patterns
which change due to the progressive removal of the material from the layer; and

deriving, from the oscillations, an indication about an etch uniformity of the plasma etching process.

US Pat. No. 9,741,848

MULTI-GATE TUNNEL FIELD-EFFECT TRANSISTOR (TFET)

IMEC VZW, Leuven (BE)

1. A tunnel field-effect transistor, comprising:
a source-channel-drain structure of a semiconducting material comprising:
a source region doped with a dopant element having a source type of doping of N or P,
a drain region doped with a dopant element having a drain type of doping opposite to the source type of doping, and
a channel region situated between the source region and the drain region and forming a source-channel interface with the source
region and a drain-channel interface with the drain region, wherein the channel region is intrinsic or lowly doped;

a reference gate structure comprising a reference gate dielectric layer and a reference gate electrode having a reference
work function and a reference electrostatic potential, wherein the reference electrostatic potential is an electrostatic potential
present at the reference gate electrode, wherein the reference gate dielectric layer is sandwiched in between a semiconducting
material of the channel region and the reference gate electrode; and

a source-side gate structure aside of the reference gate structure, the source-side gate structure comprising a source-side
gate dielectric layer and a source-side gate electrode having a work function and an source-side electrostatic potential,
wherein the source-side electrostatic potential is an electrostatic potential present at the source-side gate electrode, wherein
the source-side gate dielectric layer is sandwiched between the semiconducting material of the channel region and the source-side
gate electrode,

wherein the work function or the electrostatic potential of the source-side gate structure and the reference gate structure
are selected to allow a tunneling mechanism of the tunnel field-effect transistor, in operation, to occur at an interface
or an interface region in the channel region between the source-side gate structure and the reference gate structure.

US Pat. No. 9,691,975

CONDUCTIVE BRIDGING MEMORY DEVICE

IMEC VZW, Leuven (BE)

1. A Conductive Bridge Random Access Memory (CBRAM) device comprising:
an insulating electrolyte element sandwiched between a cation supply metal electrode and a bottom electrode, wherein the conductivity
? of the cation provided by the cation supply electrode in the electrolyte element increases towards the bottom electrode,
wherein the electrolyte element comprises a top layer of a first dielectric material stacked on a bottom layer of a second
dielectric material, wherein the cation conductivity ? in the first dielectric material is lower than the cation conductivity
? the second dielectric material, wherein the cation supply electrode comprises Cu or Ag, wherein the bottom electrode comprises
tungsten, and wherein the second dielectric material is a thermally grown tungsten oxide.

US Pat. No. 9,633,853

METHOD FOR FORMING AN ELECTRICAL CONTACT

IMEC VZW, Leuven (BE)

1. A method for forming an electrical contact to a semiconductor structure, the method comprising:
providing a semiconductor structure;
providing a metal on an area of said semiconductor structure, wherein said area exposes a semiconductor material and is at
least a part of a contact region; and

converting said metal to a Si-comprising or a Ge-comprising alloy, thereby forming said electrical contact on said area,wherein said converting is done by performing a vapor-solid reaction, whereby said semiconductor structure including said
metal is subjected to a silicon-comprising precursor gas or a germanium-comprising precursor gas.

US Pat. No. 10,008,251

MAGNETIC MEMORY HAVING MULTIPLE GATES AND METHOD OF OPERATING SAME

IMEC vzw, Leuven (BE) Ka...

1. A magnetic memory, comprising:a first magnetic stack comprising a first gate dielectric layer formed between a first gate electrode and a first free ferromagnetic layer; and
a second magnetic stack comprising a second gate dielectric layer formed between a second gate electrode and a second free ferromagnetic layer,
wherein the first free ferromagnetic layer and the second free ferromagnetic layer are magnetically coupled, contiguous and are positioned at an oblique angle relative to each other, and
wherein the first gate electrode and the second gate electrode are electrically isolated from each other.

US Pat. No. 9,997,458

METHOD FOR MANUFACTURING GERMAMDE INTERCONNECT STRUCTURES AND CORRESPONDING INTERCONNECT STRUCTURES

IMEC vzw, Leuven (BE)

1. A method for forming an interconnect structure, comprising the steps of:a) forming a recessed structure in a dielectric material on a substrate, the recessed structure having a bottom;
b) at least partially filling, from the bottom up, said recessed structure with a metal, the metal being chosen from the group consisting of copper, nickel and cobalt, or combinations thereof;
c) introducing the substrate in a CVD reactor;
d) bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, wherein the soak treatment is performed to convert substantially all of any copper metal, nickel metal and cobalt metal present in the recessed structure to a germanide such that the recessed structure is completely filled, and substantially no copper metal, nickel metal, or cobalt metal remains in the recessed structure.

US Pat. No. 9,984,874

METHOD OF PRODUCING TRANSITION METAL DICHALCOGENIDE LAYER

IMEC VZW, Leuven (BE)

1. A method of producing at least one transition metal dichalcogenide layer (MX2) on a substrate, the method comprising:obtaining a substrate having a surface;
functionalizing the surface before depositing a transition metal dichalcogenide layer (MX2); and
depositing the transition metal dichalcogenide layer (MX2) on the surface using ALD deposition, starting from a metal halide precursor and a chalcogen source (H2X).

US Pat. No. 9,899,220

METHOD FOR PATTERNING A SUBSTRATE INVOLVING DIRECTED SELF-ASSEMBLY

IMEC VZW, Leuven (BE)

1. A method for patterning a substrate, comprising:
applying a first directed self-assembly (DSA) patterning process defining a first patterned layer on top of the substrate,
wherein a pattern of the first patterned layer is to be transferred into the substrate;

applying a planarizing layer on top of the first patterned layer;
applying a second DSA patterning process defining a second patterned layer on top of the planarizing layer, thereby not patterning
the planarizing layer, wherein a pattern of the second patterned layer is to be transferred into the substrate, and wherein
projections of the pattern of the second patterned layer and the pattern of the first patterned layer on the substrate have
no overlap; and

transferring the patterns defined by the first patterned layer and the second patterned layer into the substrate.

US Pat. No. 9,847,336

METHOD OF FORMING A JUNCTION FIELD EFFECT TRANSISTOR

IMEC vzw, Leuven (BE)

1. A method of fabricating a junction field effect transistor (JFET), the method comprising:
providing a semiconductor substrate;
forming a well of a first dopant type in the substrate, wherein the well is isolated from the semiconductor substrate by an
isolation region of a second dopant type that is the opposite of the first dopant type;

implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET;
implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET, wherein the gate is entirely
formed within the well of the first dopant type;

prior to implanting the dopant of the first type and the dopant of the second type, patterning a pre-metal dielectric (PMD)
layer on the well to form openings in the PMD layer at regions corresponding to the source, the drain and the gate, wherein
the PMD layer permanently remains over a region corresponding to the channel and has a thickness such that the channel is
formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer; and

after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the
gate, and forming metal contacts in the contact openings.

US Pat. No. 9,829,720

ACTIVE MULTIFOCAL LENS

Universiteit Gent, Ghent...

1. An optical lens device having an actively controllable focal length, comprising:
an element with lensing effect comprising a plurality of regions, each region having a corresponding refractive power arranged
for providing a corresponding focal length distinct from the focal length of at least one other region of said plurality of
regions;

at least one addressable optical element integrated in or provided on the element with lensing effect, the at least one addressable
optical element being arranged for changing the transmittance of at least one of said plurality of regions in response to
a control signal; and

a control means programmed for generating said control signal,
wherein said at least one addressable optical element is non-concentric, said at least one addressable optical element comprising
an addressable optical element configured as one or more sectors of the element with lensing effect,

wherein the one or more sectors are pie-slice shaped sectors with their pie-point at the centre of the element with lensing
effect.

US Pat. No. 9,816,935

INTEGRATED WAVEGUIDE STRUCTURE FOR FLUORESCENCE ANALYSIS

IMEC VZW, Leuven (BE)

1. An integrated waveguide structure, comprising:
a substrate;
a waveguide layer arranged on top of the substrate, the waveguide layer comprising:
one or more excitation waveguides configured to transmit excitation radiation to activate a fluorescent particle;
one or more emission waveguides, distinct from the one or more excitation waveguides, configured to transmit radiation emitted
by the fluorescent particle; and

a particle radiation coupler, wherein the particle radiation coupler comprises a resonator element arranged to couple radiation
emitted by the fluorescent particle into at least one of the emission waveguides in response to the activation by the excitation
radiation transmitted via the one or more excitation waveguides; and

one or more sensing sites configured with respect to the one or more excitation waveguides and the one or more emission waveguides
such that a fluorescent particle at one of the sensing sites is activated by the excitation radiation transmitted via the
one or more excitation waveguides and radiation emitted by the fluorescent particle is coupled into at least one of the emission
waveguides by the particle radiation coupler,

wherein the resonator element is positioned between at least one of the emission waveguides and at least one of the excitation
waveguides, and

wherein at least one of the sensing sites is positioned between at least one of the excitation waveguides and the resonator
element.

US Pat. No. 9,685,229

METHOD FOR OPERATING A CONDUCTIVE BRIDGING MEMORY DEVICE

IMEC VZW, Leuven (BE)

1. A method for operating a memory comprising at least one Conductive Bridge Random Access Memory (CBRAM) device, the at least
one CBRAM device comprising an electrolyte element sandwiched between a cation supply top electrode and an inert bottom electrode,
the method comprising:
conditioning the at least one CBRAM device by applying a forming current pulse having a pulse amplitude (If) of 10 uA or less.

US Pat. No. 10,061,209

METHOD FOR VERIFYING A PATTERN OF FEATURES PRINTED BY A LITHOGRAPHY PROCESS

IMEC VZW, Leuven (BE)

1. A method for verifying a printed pattern of features printed through a lithographic mask, the printed pattern approximating a reference pattern, the method comprising:defining sectors of at least a portion of the features in the reference pattern;
producing a lithographic mask according to a mask design suitable for printing an intended pattern;
printing a pattern through the lithographic mask;
determining a contour of the printed pattern;
superimposing the contour of the printed pattern on the reference pattern;
determining surface areas of sectors of the printed pattern that correspond to the sectors of the reference pattern;
calculating one or more parameters as a function of at least one of the surface areas, the parameters being related to a single sector or to multiple sectors, wherein one of the parameters is a ratio of the surface area of a sector of the printed pattern to a surface area of a corresponding sector of the reference pattern; and
evaluating the parameters with respect to a reference value.

US Pat. No. 10,056,253

METHOD FOR FORMING A VERTICAL HETERO-STACK AND A DEVICE INCLUDING A VERTICAL HETERO-STACK

IMEC VZW, Leuven (BE)

1. A method for forming a vertical hetero-stack of a first nanostructure and a second nanostructure arranged on an upper surface of the first nanostructure, wherein the first nanostructure is formed by a first transition metal dichalcogenide, TMDC, material and the second nanostructure is formed by a second TMDC material, the method comprising:providing the first nanostructure on a substrate, wherein the upper surface of the first nanostructure is formed by a basal plane of the first TMDC material;
forming a reactive layer of molecules on the first nanostructure along a periphery of the upper surface; and
forming the second nanostructure by a vapor deposition process, wherein the second TMDC material nucleates on the reactive layer of molecules along the periphery and grows laterally therefrom to form the second nanostructure on the upper surface.

US Pat. No. 9,905,159

DIGITAL DRIVING OF ACTIVE MATRIX DISPLAYS

IMEC VZW, Leuven (BE)

1. A method for digital driving of an active matrix display with a predetermined frame rate, the display comprising a plurality
of pixels logically organized in a plurality of rows and a plurality of columns, the method comprising:
representing each of a plurality of pixels of an image to be displayed within an image frame by an n-bit digital image code;
dividing the image frame into a natural number of sub-frames;
within each sub-frame of a respective image frame, sequentially selecting at least two or more of the plurality of rows twice,
wherein sequentially selecting a row includes a sequential first selection and second selection of the row, wherein upon the
first selection a first digital code is written to the selected row and upon the second selection a second digital code is
written to the selected row, there being a predetermined time delay between the second selection and the first selection,
wherein the first digital code and the second digital code are written respectively by driving the first digital code and
the second digital code using pulse-width modulation, and wherein the first digital code corresponds to a first predetermined
bit of the n-bit digital image code and the second digital code corresponds to a second predetermined bit of the n-bit image
code.

US Pat. No. 9,825,654

DIGITAL FRONTEND SYSTEM FOR A RADIO TRANSMITTER AND A METHOD THEREOF

IMEC VZW, Leuven (BE)

1. A digital frontend system for a radio device comprising:
a digital filter arranged for receiving digital quadrature signals and for filtering the digital quadrature signals and for
outputting filtered quadrature signals; and

a conversion circuit arranged for receiving the filtered quadrature signals and for performing a rectangular to polar conversion
of the filtered quadrature signals and for outputting a plurality of polar signals, wherein the plurality of polar signals
comprises an amplitude signal and quadrature phase signals, wherein the quadrature phase signals are cos(?(t) and sin(?(t),
wherein the conversion circuit comprises a vectoring-mode coordinate rotation digital computer (CORDIC) processor and a rotation-mode
CORDIC processor, wherein each CORDIC processor comprises two computational columns, wherein each computation column of each
CORDIC processor comprises a plurality of computational circuits connected in series via a respective plurality of latch logic
gates, wherein rotation of each of the plurality of computational circuits of the rotation-mode CORDIC processor is based
on output signals of each of the plurality of computational circuits of the vectoring-mode CORDIC processor, and wherein the
output signals comprise information indicative of a direction of rotation.

US Pat. No. 9,709,442

SPECTRAL DETECTOR AND IMAGE SENSOR INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A spectral detector comprising:
a plurality of spectral detection units, each of the spectral detection units comprising:
an optical signal processor configured to deliver an optical signal incident to the spectral detection unit to an outside
of the spectral detection unit; and

a resonator configured to modulate a spectrum of an optical signal incident to the optical signal processor by interacting
with the optical signal processor,

wherein at least some of the resonators of the plurality of spectral detection units have different lengths from each other,
and a number of optical signal processors included in each respective spectral detection unit varies according to a length
of the resonator included in the respective spectral detection unit.

US Pat. No. 10,376,175

SENSOR, SYSTEM, AND HOLDER ARRANGEMENT FOR BIOSIGNAL ACTIVITY MEASUREMENT

IMEC VZW, Leuven (BE) St...

1. A sensor module for brain activity measurement, comprising:a main electrode base; and
a plurality of pins protruding from the main electrode base,
wherein the plurality of pins is arranged such that, when applied on a subject, each pin of the plurality respectively makes contact with skin of the subject or is in close proximity with the skin of the subject,
wherein the main electrode base comprises electronic circuitry for near infrared spectroscopy (NIRS) measurements and electronic circuitry for electroencephalography (EEG) measurements,
wherein the electronic circuitry for NIRS measurements and the electronic circuitry for EEG measurements are connected to the plurality of pins,
wherein the plurality of pins comprises pins that are respectively configured to conduct both light and electricity,
wherein the pins configured to conduct both light and electricity each respectively include (i) an outer, electrically conductive layer and (ii) an inner waveguide core, and
wherein the pins configured to conduct both light and electricity are configurable for NIRS measurements or EEG measurements.

US Pat. No. 10,056,485

SEMICONDUCTOR DEVICES WITH GATE-CONTROLLED ENERGY FILTERING

IMEC VZW, Leuven (BE) UN...

1. A semiconductor device comprising:a first electrode;
a second electrode;
a channel in between the first electrode and the second electrode;
a first interference structure located in the channel such that, when a current is flowing from the second electrode to the first electrode, the current passes through the first interference structure; and
a first gate for controlling a voltage over the first interference structure,
wherein the first interference structure is formed to induce a first local mini-band structure that can be shifted by the voltage controlled by the first gate, such that the first local mini-band structure is:
aligned with a band structure in the semiconductor device to turn the semiconductor device on; and
misaligned with the band structure in the semiconductor device to turn the semiconductor device off.

US Pat. No. 10,019,361

LOW-LAYER MEMORY FOR A COMPUTING PLATFORM

IMEC VZW, Leuven (BE)

1. A memory hierarchy being directly connectable to a processor,wherein the memory hierarchy comprises at least a level 1, referred to as L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB),
wherein the memory hierarchy comprises a first decoding structure (S1) configured to allow data transfer between the non-volatile memory unit and the buffer structure,
wherein the buffer structure comprises a plurality of interconnected wide registers with an asymmetric organization,
wherein a data block size used towards the non-volatile memory unit is wider than a data block size used towards a data path connectable to the processor, and
wherein the buffer structure and the non-volatile memory unit are arranged for being directly connectable to a processor so that data words can be read directly from either of the L1 data memory and the buffer structure (L1-VWB) by the processor.

US Pat. No. 9,927,559

WAVELENGTH-CONTROLLED DIRECTIVITY OF ALL-DIELECTRIC OPTICAL NANO-ANTENNAS

IMEC VZW, Leuven (BE)

1. An optical nanoantenna, for directionally scattering light in a visible or a near-infrared spectral range, comprising:a substrate; and
an antenna structure disposed on the substrate,
wherein the antenna structure comprises a dielectric material having a refractive index that is higher than a refractive index of the substrate and a refractive index of a surrounding medium,
wherein the antenna structure comprises a structure having two distinct end portions,
wherein the antenna structure is asymmetric with respect to at least one mirror reflection in a plane that is orthogonal to a plane of the substrate,
wherein the antenna structure has a reflection symmetry with respect to a plane of symmetry so as to form two connected parts of the antenna structure,
wherein the two connected parts are mirror symmetric with one another,
wherein the plane of symmetry is orthogonal to the plane of the substrate, and
wherein the two connected parts are connected to each other at an acute angle.

US Pat. No. 9,859,161

SELF-ALIGNED INTERCONNECTS

IMEC vzw, Leuven (BE)

1. A method of forming an interconnect structure, comprising the steps of:
providing a first entity comprising:
a first set of one or more line structures having a top surface, comprising:
a first set of one or more conductive lines,
a first set of one or more dielectric lines of width (w) made of a first dielectric material, aligned with and overlaying
the first set of one or more conductive lines, and comprising the top surface,

a second dielectric material of such a nature that the first dielectric material can be etched selectively with respect to
the second dielectric material, the second dielectric material surrounding each line structure and having a top surface coplanar
with the top surface of the one or more line structures;

providing a patterned mask on the first entity, wherein the pattern comprises:
at least one via exposing the whole width (w) of an underlying dielectric line of the first set of one or more dielectric
lines, and/or

at least one trench exposing the whole width (w) of at least one dielectric line of the first set of one or more dielectric
lines;

etching selectively the first dielectric material with respect to the second dielectric material through the patterned mask
so as to form one or more vias in the first dielectric material, thereby exposing a portion of the set of one or more conductive
lines; and

removing the patterned mask, thereby uncovering a perforated surface.

US Pat. No. 9,834,847

NANOWIRE CLUSTER AND TEMPLATE AND METHOD FOR NANOWIRE CLUSTER FORMATION

IMEC VZW, Leuven (BE) Ki...

1. A cluster of spaced nanowires aligned longitudinally along a direction, the cluster comprising:
at least a first region and a second region positioned substantially along the longitudinal direction,
wherein the nanowires of the first region are interconnected with each other in the first region, and the nanowires of the
second region are free of interconnections with each other in the second region.

US Pat. No. 9,826,184

DEVICE FOR IMAGING AND METHOD FOR ACQUIRING A TIME DELAY AND INTEGRATION IMAGE

IMEC vzw, Leuven (BE)

1. A device for imaging, comprising:
an image sensor, arranged to acquire an image, the image sensor comprising:
pixels, arranged in columns and rows forming a plurality of adjacent rows over an area of the image sensor, wherein each pixel
comprises a photo-active region, which is arranged to accumulate an electric charge proportional to intensity of electro-magnetic
radiation incident on the photo-active region, and a transmission region, which is arranged to receive the accumulated electric
charge from the photo-active region;

a first control structure for controlling and timing transfer of accumulated electric charges from the photo-active regions
to the transmission regions in pixels; and

a second control structure for controlling and timing transfer of accumulated electric charge in the transmission region of
each row of pixels to the adjacent row below, wherein the first and second control structures are configured to control the
image sensor to alternately transfer accumulated charges in photo-active regions to the transmission regions of pixels and
transfer the accumulated electric charge in transmission regions from one row to the adjacent row below whereby electric charges
accumulated in photo-active regions in a column of pixels are added to each other, and wherein accumulated charges in a lower-most
row of the image sensor are output to a read-out structure;

wherein the first control structure comprises a plurality of row structures which are arranged to control whether the accumulated
electric charge in the photo-active region of at least one row is to be output to the transmission region of the at least
one row such that the row structures select whether the charge in the photo-active regions of respective rows are added to
the accumulated electric charge in the transmission region, and

wherein each row of pixels is controlled by one of the row structures of the first control structure to control whether the
accumulated electric charge in the photo-active region of the row is to be output to the transmission region of the row.

US Pat. No. 9,800,258

CIRCUIT FOR STABILIZING A DIGITAL-TO-ANALOG CONVERTER REFERENCE VOLTAGE

IMEC VZW, Leuven (BE)

1. A circuit for stabilizing a voltage on a reference node, comprising:
a digital-to-analog converter comprising an array of capacitors and arranged for:
receiving an input voltage (Vin) via an input node;

receiving a voltage (Vref,DAC) via a reference node and a digital-to-analog code (codeDAC) via a controller node, wherein the digital-to-analog code indicates which capacitors of the array of capacitors to which
the voltage (Vref,DAC) is to be applied; and

outputting a digital-to-analog output voltage (Vout);

a capacitive network on the reference node comprising a fixed capacitor (Cref) arranged to be pre-charged to an external reference voltage (Vref) and a variable capacitor (Caux) arranged to be pre-charged to an external auxiliary voltage (Vaux) and afterwards to be connected to the reference node;

a measurement block arranged for measuring the voltage on the reference node; and
a calibration block arranged for receiving the digital-to-analog code and the measured voltage on the reference node and for
determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the
reference node.

US Pat. No. 9,770,196

SENSING OF COMPONENTS IN LIQUIDS

UNIVERSITEIT GENT, Ghent...

1. A sensing system for sensing a component in a liquid, the system comprising:
a microfluidic diffusion channel, the microfluidic diffusion channel comprising an open end and a closed end, the microfluidic
channel providing a diffusion path for the component in the liquid to be sensed,

at least one measurement sensor positioned at the open end, the measurement sensor being arranged for detecting a measurement
signal indicating a characteristic of a portion of the component at the open end of the diffusion channel,

at least one reference sensor positioned in the microfluidic diffusion channel adjacent the closed end, the reference sensor
being arranged for detecting a reference signal of the liquid, the diffusion channel and reference sensor being arranged such
that the reference signal indicates a characteristic of a portion of the component arriving at the reference sensor by diffusion
through the diffusion channel,

the system being configured for combining the measurement signal and the reference signal so as to filter out background influences.

US Pat. No. 9,698,309

METHOD FOR FABRICATING CMOS COMPATIBLE CONTACT LAYERS IN SEMICONDUCTOR DEVICES

IMEC VZW, Leuven (BE)

1. A method for fabricating a contact layer on a p-type gallium nitride (GaN) layer of a GaN based structure, the method comprising:
depositing a nickel (Ni) layer on the p-type GaN layer;
thermally treating the GaN based structure at a temperature range of 350° C. to 500° C., upon depositing the Ni layer;
removing the Ni layer using an etchant, upon thermally treating the GaN based structure; and
depositing the contact layer on the p-type GaN layer, upon removing the Ni layer, wherein the contact layer comprises a multi
layer structure of titanium aluminum titanium (TiAlTi).

US Pat. No. 10,090,852

INPUT CIRCUIT FOR A DYNAMIC COMPARATOR

IMEC VZW, Leuven (BE)

1. Input circuit for a dynamic comparator comprising a positive and a negative branch, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that a source terminal of the transistor in each of the positive and negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch, the first reset voltage and the second reset voltage being independent of each other.

US Pat. No. 9,960,080

METHOD FOR BONDING AND INTERCONNECTING INTEGRATED CIRCUIT DEVICES

IMEC vzw, Leuven (BE)

1. A method for bonding and interconnecting a first IC device arranged on a first substrate to a second IC device arranged on a second substrate, wherein each IC device comprises a dielectric bonding layer at its outer surface, and wherein each IC device further comprises one or more metal contact structures, the method comprising the consecutive steps of:positioning the first substrate with respect to the second substrate, with the bonding layers of the first and second IC device facing each other, by aligning a first metal contact structure in the first IC device to a second metal contact structure in the second IC device;
direct bonding of the substrates, thereby forming a substrate assembly;
optionally thinning the first substrate;
producing by a lithography step and an etching procedure, a first opening in the first substrate, until reaching the first metal contact structure, wherein the first metal contact structure partially covers a cross-section of the first opening;
with the first metal contact structure acting as a mask, etching one or more second openings in the second substrate, stopping on the second metal contact structure, the first and second opening thereby forming an aggregate opening;
producing an isolation layer on the sidewalls and the bottom of at least the first opening;
removing the isolation layer from at least the bottom of the first opening, while maintaining the isolation layer on at least the sidewalls of the first opening, without applying a lithography step; and
producing a metal contact plug in the aggregate opening, the metal plug interconnecting the first and second contact structures,
wherein prior to the step of producing the first opening, the method further comprises bonding the opposite side of the first substrate to an additional substrate or substrate assembly, so that the second substrate is bonded to a stack of substrates, each substrate of the stack comprising a further IC device comprising a metal contact structure, and wherein
the step of producing the first opening comprises consecutive steps of etching openings through consecutive substrates of the stack, consecutively reaching a metal contact structure in the consecutive substrates, until reaching the first metal contact structure,
each of the metal structures in the consecutive substrates serves as a mask for the consecutive etching steps,
the isolation layer is deposited on horizontal areas of the consecutive metal contact structures serving as masks, and
the removing step includes removing the isolation layer from the horizontal areas.

US Pat. No. 9,929,206

INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT

IMEC vzw, Leuven (BE)

1. A method of manufacturing an integrated circuit for an imaging device, comprising:forming a first multi-layer structure on a substrate, on which an array of photo-sensitive areas are arranged, wherein the first multi-layer structure is formed in a first region over a first photo-sensitive area of the array, wherein the first multi-layer structure comprises a bottom reflective structure, a top reflective structure and a spacer layer arranged between the bottom and top reflective structures, the spacer layer having a thickness which is adapted so that the first multi-layer structure selectively transmits a narrow range of wavelengths of electro-magnetic radiation, wherein at least one of the bottom and top reflective structures comprise a stack of alternating layers of a first and a second material for forming a reflective structure; and
forming a second multi-layer structure in a second region over a second photo-sensitive area of the array, wherein the second multi-layer structure comprises a bottom reflective structure, a top reflective structure and a spacer layer arranged between the bottom and top reflective structures, the spacer layer having a thickness which is adapted so that the second multi-layer structure selectively transmits a narrow range of wavelengths of electro-magnetic radiation, wherein at least one of the bottom and top reflective structures comprise a stack of alternating layers of a first and a second material for forming a reflective structure,
wherein thickness and/or material of the alternating layers of the at least one of the bottom and top reflective structures of the first multi-layer structure differ from thickness and/or material of the alternating layers of the at least one of the bottom and top reflective structures of the second multi-layer structure;wherein forming the first and second multi-layer structures comprises:depositing at least the bottom reflective structure of the first multi-layer structure over the first photo-sensitive area;
depositing a cap layer on the at least bottom reflective structure of the first multi-layer structure,
depositing at least the bottom reflective structure of the second multi-layer structure over the second photo-sensitive area and on top of the at least bottom reflective structure of the first multi-layer structure over the first photo-sensitive area; and
selectively removing the at least bottom reflective structure of the second structure from over the first photo-sensitive area.

US Pat. No. 9,905,455

METHOD FOR FORMING CONTACT VIAS

IMEC VZW, Leuven (BE)

1. A method for forming contact vias, comprising:
providing a substrate comprising a plurality of contact structures embedded in a first dielectric layer, wherein the contacts
abut an upper surface of the first dielectric layer;

providing a second dielectric layer on the upper surface of the first dielectric layer;
providing a hardmask layer on top of the second dielectric layer;
patterning the hardmask layer to thereby remove a portion of the hardmask layer at positions where vias in the second dielectric
layer are to be formed and leaving at least an upper portion of the hardmask layer at positions where no vias in the second
dielectric layer are to be formed;

providing a patterned planarizing template layer on top of the patterned hardmask layer, wherein the patterned template layer
includes a set of openings, wherein the set of openings are evenly distributed within the template layer and comprise a limited
number of subsets of openings of identical size, and wherein at least some of the openings correspond to the positions of
the contact structures;

performing a direct self assembly (DSA) process that includes:
providing a predetermined Block Copolymer (BCP) material in all of the openings of the template layer,
inducing polymer separation of the BCP in the openings, and
removing of a first component of the BCP in the openings, wherein the patterned template layer and a second component of the
BCP define a pattern comprising DSA openings, and wherein the DSA openings are located at positions corresponding to the contact
structures; and

etching the contact vias in the second dielectric layer at positions corresponding to the contact structures, using at least
the second component of the BCP as a mask.

US Pat. No. 9,748,951

SWITCHING CIRCUIT

IMEC vzw, Leuven (BE)

1. A conversion circuit, comprising:
a first input terminal for receiving a digital signal;
a second input terminal for receiving a bias voltage signal;
an output terminal for outputting a current;
a first and a second switch transistor connected to the first input terminal for receiving said digital signal;
a first and a second current source transistor connected to the second input terminal for receiving the bias voltage signal;
a first branch, wherein the first switch transistor is connected to the output terminal via the first current source transistor;
and

a second branch wherein the second current source transistor is connected to the output terminal via the second switch transistor.

US Pat. No. 10,141,284

METHOD OF BONDING SEMICONDUCTOR SUBSTRATES

IMEC vzw, Leuven (BE)

1. A method of bonding semiconductor substrates, the method comprising:providing a first semiconductor substrate and a second semiconductor substrate to be bonded;
pre-bond processing each of the first and second semiconductor substrates prior to bonding, pre-bond processing comprising:
depositing a dielectric layer on a major surface of the each of first and second semiconductor substrates,
chemical-mechanical polishing the dielectric layer of the each of the first and second semiconductor substrates to reduce the roughness of the dielectric layer,
depositing a silicon carbon nitride (SiCN) layer on the dielectric layer of the each of the first and second semiconductor substrates,
pre-bond annealing the each of the first and second semiconductor substrates, and
chemical-mechanical polishing the SiCN layer to reduce the roughness of the SiCN layer;
bonding the first and second semiconductor substrates, bonding comprising:
aligning the first and second substrates, and
contacting the SiCN layers of the first and second substrates, thereby forming an assembly of bonded substrates; and
post-bond annealing the assembly of bonded substrates.

US Pat. No. 9,979,402

SPIN TORQUE MAJORITY GATE DEVICE

IMEC vzw, Leuven (BE) Ka...

1. A majority gate device, comprising:a free ferromagnetic layer comprising 3N input zones and an output zone, wherein the output zone has a polygon shape having 3N sides, wherein each of the input zones adjoins the output zone at a corresponding side of the polygon shape and the input zones are positioned around the output zone according to a 3N-fold rotational symmetry, wherein N is a positive integer, and wherein the input zones are spaced apart from one another by the output zone;
a plurality of input controls, wherein each of the input controls is magnetically coupled to a corresponding one of the input zones, and wherein each of the input controls is adapted for controlling the magnetization state of the corresponding one of the input zones; and
an output sensor magnetically coupled to the output zone, the output sensor being adapted for sensing the magnetization state of the output zone.

US Pat. No. 9,967,499

READOUT CIRCUIT FOR IMAGE SENSORS

IMEC vzw, Leuven (BE)

1. A readout circuit of an imaging device, comprising:a pixel signal input configured to receive an analog input signal from at least one imaging pixel element;
a variable gain amplifier configured to provide an amplified analog signal, the amplified analog signal being an amplification of the analog input signal by a gain factor;
a first analog to digital conversion means for quantizing the analog input signal into a first digital signal;
a control means for setting the gain factor of the variable gain amplifier by taking into account the first digital signal;
a second analog to digital conversion means for quantizing the amplified analog signal into a second digital signal; and
a digital output configured to output an output signal, the output signal being determined as function of at least the second digital signal, wherein the first analog to digital conversion means is configured to provide a coarse quantization of the analog input signal and the second analog to digital conversion means is configured to provide a finer quantization of the amplified analog signal than the first analog to digital conversion means.
US Pat. No. 9,885,949

METHOD FOR DESIGNING A LITHOGRAPHIC MASK

IMEC VZW, Leuven (BE)

1. A method for designing a lithographic mask, comprising:
providing an intended pattern comprising a plurality of structural features, wherein the plurality of structural features
is characterized by one or more numerical parameters related to a shape or a position of the structural features;

producing a mask design of a lithographic mask suitable for printing the intended pattern and one or more simulated patterns
printed through the mask design;

producing a lithographic mask according to the mask design;
printing a pattern through the lithographic mask produced according to the mask design; and
performing a verification of the printed pattern, wherein performing the verification of the printed pattern comprises:
determining contours of at least a portion of the structural features in the printed pattern; and
determining, on the contours, values of the one or more numerical parameters and comparing the values of the one or more numerical
parameters on the contours to values of the one or more numerical parameters in the intended pattern or to values of the one
or more numerical parameters in one or more of the simulated patterns.

US Pat. No. 9,685,322

LAYER DEPOSITION ON III-V SEMICONDUCTORS

IMEC VZW, Leuven (BE)

1. A method for depositing a layer on a III-V semiconductor substrate, the method comprising:
(a) providing a passivated III-V semiconductor substrate comprising a III-V semiconductor surface having a surface passivation
layer provided thereon for preventing oxidation of said III-V semiconductor surface, said surface passivation layer comprising
a self-assembled monolayer material produced by a reaction on said III-V semiconductor surface of an organic compound of formula
R-A, wherein A is selected from SH, SeH, TeH and SiX3, wherein X is selected from H, Cl, O—CH3, O—C2H5, and O—C3H7, and wherein R is a hydrocarbyl, fluorocarbyl or hydrofluorocarbyl comprising from 5 to 20 carbon atoms;

(b) thermally annealing said passivated III-V semiconductor substrate in a non-oxidizing environment so as to decompose said
self-assembled monolayer material; and

(c) depositing a layer on said III-V semiconductor surface in said non-oxidizing environment.
US Pat. No. 9,921,163

METHOD AND DEVICE FOR DETECTING ANALYTES

IMEC vzw, Leuven (BE) Pa...

1. A method of determining the concentration of a predefined analyte in a fluid or fluid sample, the method comprising:
a) providing a SERS substrate comprising a plurality of metal nanostructures and predefined receptor molecules capable of
binding predefined competitor molecules, the receptor molecules being bound to the metal nanostructures, each of the competitor
molecules being a molecule capable of reversibly binding to either of an analyte molecule and a receptor molecule, but being
incapable of simultaneously binding both an analyte molecule and a receptor molecule;

b) contacting the SERS substrate with the fluid or fluid sample comprising said analyte in a concentration to be determined
and comprising a predetermined amount of said competitor molecules, such that the amount of competitor molecule bound to the
receptor molecules at the metal nanostructures is an inverse function of the amount of analyte in the fluid or fluid sample,
and such that when a competitor molecule is not bound to a receptor molecule, it is free to diffuse away from the metal nanostructures;

c) radiating the SERS substrate with a monochromatic light source thereby generating a SERS signal having a level indicative
of the amount of competitor molecules bound to the receptor molecules of the SERS substrate;

d) determining the level of the SERS signal while radiating the SERS substrate with the monochromatic light source;
e) determining a concentration of the analyte in the fluid or fluid sample based on the level of the measured SERS signal.

US Pat. No. 9,876,080

STRAINED GROUP IV CHANNELS

IMEC VZW, Leuven (BE)

1. A method for forming a semiconductor structure comprising:
epitaxially growing, on a monocrystalline substrate, a first buffer layer from one of: a III-V buffer layer or a II-VI buffer
layer, wherein the first buffer layer is grown within a space confined by non-crystalline sidewalls, wherein the space has
a width smaller than 10 microns, and wherein the material forming the surface of the first buffer layer facing away from the
monocrystalline substrate has a first relaxed lattice constant;

epitaxially growing on the first buffer layer a first at least one group IV monocrystalline structure comprising a material
having a second relaxed lattice constant different from the first relaxed lattice constant; and

removing the first buffer layer from the first at least one group IV monocrystalline structure by selectively etching away
at least part of the first buffer layer on the first at least one group IV monocrystalline structure.

US Pat. No. 9,842,734

METHOD OF FORMING A FEATURE OF A TARGET MATERIAL ON A SUBSTRATE

IMEC VZW, Leuven (BE)

1. A method of foaming a feature of a target material on a substrate comprising:
forming a feature of a sacrificial material on the substrate; and
forming the feature of the target material by a deposition process during which the feature of the sacrificial material is
removed from the substrate by forming a volatile reaction product with a precursor of the deposition process,

wherein the sacrificial material is replaced by the target material and the target material is selectively deposited on surface
portions of the substrate, which portions were covered by the feature of the sacrificial material, to form the feature of
the target material, and

wherein the deposition process includes exposing the substrate to a first precursor and a second precursor,
the first precursor includes a compound of a first target element, for forming the target material, and a first reaction element,
the sacrificial layer includes a sacrificial element acting as a co-reagent in a reaction with the first precursor and forming
a volatile reaction product with the first reaction element wherein the first target element is deposited on the substrate;
and

the second precursor includes a compound of a second target element, for forming the target material in combination with the
first target element, and a second reaction element wherein the second target element reacts with the first target element
deposited on the substrate to form the target material and the second reaction element forms a volatile reaction product.