US Pat. No. 9,069,923

IP PROTECTION

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1. A method of forming a device comprising:
providing a substrate with a device layer;
providing a MPW mask comprising first and second patterns of first and second chiplets pertaining to first and second IP owners,
the MPW mask is used to form a device for the first IP owner, wherein the first pattern of the first chiplet is according
to that of the first IP owner and the second pattern of the second chiplet is a modified second pattern, the modified second
pattern is different from that according to the second IP owner to protect IP information of the second IP owner from disclosure
to the first IP owner;

providing an exposure source to expose the substrate using the MPW mask without providing a cover on the MPW mask over the
second chiplet;

patterning the device layer in first and second chiplet regions after the exposure, wherein the first pattern of the first
chiplet is transferred to the device layer and the second pattern with IP protection of the second chiplet is transferred
to the device layer;

delivering the device to the first IP owner, the device includes first and second chiplets, wherein the second chiplet includes
IF protection to reduce disclosure of IP information of the second IP owner to the first IP owner; and

continue processing of the device to form the desired function of the device.

US Pat. No. 9,081,919

DESIGN-FOR-MANUFACTURING—DESIGN-ENABLED-MANUFACTURING (DFM-DEM) PROACTIVE INTEGRATED MANUFACTURING FLOW

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:
using a computer for
receiving design data related to layout of an integrated circuit (IC);
extracting information from the design data;
performing analysis on the extracted information;
enabling design-for-manufacturing (DFM) and design-enabled-manufacturing (DEM) aware manufacturing (collectively DFM-DEM)
applications using information stored in a knowledge database, wherein the knowledge database stores information related to
DFM and DEM for facilitating DFM-DEM aware manufacturing; and

updating the knowledge database with new information learned from at least the extracted information and the analysis.

US Pat. No. 9,646,934

INTEGRATED CIRCUITS WITH OVERLAY MARKS AND METHODS OF MANUFACTURING THE SAME

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1. An integrated circuit comprising:
a base dielectric layer;
a first dielectric layer overlying the base dielectric layer;
a second dielectric layer overlying the first dielectric layer;
a first overlay mark pattern positioned within the first dielectric layer;
a second overlay mark pattern positioned within the second dielectric layer, wherein the second overlay mark pattern is offset
from the first overlay mark pattern; and

a first block and a second block positioned within the base dielectric layer, wherein the first overlay mark pattern directly
overlays the first block, wherein the first block comprises a first block geographic center, wherein the second overlay mark
pattern directly overlays the second block, wherein the first block comprises a first block upper surface that is dished with
a trough area and a curved area, wherein the first block geographic center is within the trough area, and wherein the curved
area of the first block upper surface is symmetric with the first overlay mark pattern.

US Pat. No. 9,613,874

METHODS FOR EVALUATING SEMICONDUCTOR DEVICE STRUCTURES

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1. A method for evaluating a semiconductor device structure, the method comprising:
forming a support layer on a first side of a lamellar sample portion of the semiconductor device structure, wherein the lamellar
sample portion has a second side opposite the first side, a target analysis area on or proximate the first side, and a first
thickness defined from the first side to the second side, wherein forming the support layer comprises forming the support
layer using a technique chosen from a physical vapor deposition (PVD) process or an electron beam gas-injection process;

milling the second side to form a reduced thickness lamellar-supported sample portion that has a milled second side opposite
the first side;

removing the support layer from the reduced thickness lamellar-supported sample portion to form a reduced thickness lamellar
sample portion having a second thickness that is defined from the first side to the milled second side and that is less than
the first thickness; and

evaluating the target analysis area of the reduced thickness lamellar sample portion.

US Pat. No. 9,646,666

VOLTAGE CONTROLLED SPIN SWITCHES FOR LOW POWER APPLICATIONS

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1. A switch comprising:
at least three electrodes including source, drain, and gate electrodes;
a source magnet having a magnetization vector M, the source magnet being coupled to the source electrode;
a drain magnet having a magnetization vector m, the drain magnet being coupled to the drain electrode;
a channel disposed between the source magnet and the drain magnet; and
a gate disposed above the drain magnet, the gate being coupled to the gate electrode, wherein an angle formed between the
magnetization vector M and the magnetization vector m is controlled by a voltage source Vg coupled to the gate electrode, wherein the gate comprises a MF/PZ layer formed by one of multiferroic (MF) and a piezoelectric
(PZ) material.

US Pat. No. 9,349,772

METHODS FOR FABRICATINGINTEGRATED CIRCUITS WITH SPIN TORQUE TRANSFER MAGNETIC RANDOMACCESS MEMORY (STT-MRAM) INCLUDING A PASSIVATION LAYER FORMED ALONG LATERAL SIDEWALLS OF A MAGNETIC TUNNEL JUNCTION OF THE STT-MRAM

GLOBALFOUNDRIES SINGAPORE...

1. A method of fabricating an integrated circuit comprising:
forming a trench within a passivation layer, the passivation layer being formed over an interlayer dielectric (ILD) layer
and a metallization layer within the ILD layer, the trench being formed over at least a portion of the metallization layer;

depositing a bottom electrode layer, a magnetic tunnel junction (MTJ) layer, and a top electrode layer over the passivation
layer and within the trench, thereby filling the trench, wherein the trench is filled with portions of the bottom electrode
layer and portions of the MTJ layer, but is not filled with the top electrode layer;

removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode
layer and at least partially within portions of the trench having being reopened by said removing, wherein an entirety of
the bottom electrode layer remains in place during and subsequent to the step of removing portions of the MTJ layer and the
top electrode layer;

forming a further passivation layer over and in physical contact with an upper surface and with lateral sides of the MTJ/top
electrode stack and within the portions of the trench having been reopened, the passivation layer forming and comprising concave
structures adjacent to the lateral sides of the MTJ/top electrode stack, wherein the step of forming the further passivation
layer is performed after the step of removing portions of the MTJ layer and the top electrode layer to form the MTJ/top electrode
stack;

re-forming a top electrode layer over the further passivation layer and over the MTJ/top electrode stack; and
removing portions of the bottom electrode layer, the further passivation layer, and the re-formed top electrode layer to form
a bottom electrode/MTJ/top electrode stack, wherein the step of removing portions of the bottom electrode layer, the further
passivation layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack is performed after
the step of re-forming the top electrode layer, wherein the bottom electrode/MTJ/top electrode stack comprises a spin torque
transfer magnetic random access memory (STT-MRAM) structure.

US Pat. No. 9,111,941

NON-VOLATILE MEMORY DEVICE WITH TSI/TSV APPLICATION

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1. A device comprising:
a semiconductor substrate having an array surface and a non-array surface;
a memory dielectric layer disposed on and contacts the array surface of the substrate;
a memory array having a plurality of memory cells interconnected by first conductors in a first direction and second conductors
in a second direction, the memory array is disposed in the memory dielectric layer which is disposed on and contacts the array
surface of the substrate;

through silicon via (TSV) contacts disposed in the substrate, the TSV contacts extend from the array surface to the non-array
surface, the TSV contacts enable electrical connections to the array surface from the non-array surface; and

a dielectric layer disposed on and contacts the non-array surface of the substrate.

US Pat. No. 9,105,502

INTEGRATED CIRCUIT COMPRISING ON-CHIP RESISTORS WITH PLURALITY OF FIRST AND SECOND TERMINALS COUPLED TO THE RESISTOR BODY

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit (IC), comprising:
a substrate with a resistor region, the resistor region includes an isolation region in the substrate;
a resistor body directly disposed on and contacts the isolation region;
a plurality of first and second contacts/vias formed on the resistor body, wherein a resistor portion of the resistor body
between the first and second contacts/vias forms a resistor;

a terminal ILD layer disposed over the plurality of first and second contacts/vias; and
first and second terminal plates which are non-rectangular terminal plates disposed in the terminal ILD layer, wherein adjacent
sides of the first and second terminal plates are separated by a space and adjacent sides of the first and second terminal
plates are slanted and configured to encompass the same number of contacts/vias.

US Pat. No. 9,178,138

METHOD FOR FORMING A PCRAM WITH LOW RESET CURRENT

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:
a bottom electrode;
a u-shaped heater liner;
an interlayer dielectric (ILD) on the bottom electrode, surrounding the u-shaped heater liner;
an interlayer dielectric structure surrounded by the u-shaped heater liner and including a protrusion extending above the
u-shaped heater liner and a top surface of the ILD;

a phase-change layer on the ILD, surrounding the interlayer dielectric structure;
a dielectric spacer above the ILD and surrounding the protrusion; and
a top electrode covering the ILD, the protrusion, and the dielectric spacer.

US Pat. No. 9,087,988

COMPACT LOCALIZED RRAM CELL STRUCTURE REALIZED BY SPACER TECHNOLOGY

GLOBALFOUNDRIES Singapore...

1. A device comprising:
a substrate;
a well of a first polarity in the substrate;
a shallow trench isolation (STI) region formed in the substrate extending partially into the well;
a channel of a second polarity in the substrate, over the well, at opposite sides of the STI region;
an active area of the first polarity in the substrate over the channel at opposite sides of the STI region;
an RRAM liner on the active area and STI region;
a top electrode on the RRAM liner;
spacers on opposite sides of the RRAM liner and top electrode; and
doped regions of the second polarity in the substrate adjacent the spacers, laterally remote from the RRAM liner.

US Pat. No. 9,054,107

RELIABLE INTERCONNECT FOR SEMICONDUCTOR DEVICE

GLOBALFOUNDRIES SINGAPORE...

1. A semiconductor device comprising:
a substrate;
a lower dielectric layer on the substrate, wherein the lower dielectric layer comprises at least an interconnect region and
a non-interconnect region adjacent to the interconnect region, wherein the interconnect region of the lower dielectric layer
comprises an interconnect disposed therein while the non-interconnect region of the lower dielectric layer is devoid of an
interconnect and comprises an unetched or unpolished top surface having hydrophobic characteristics;

an etch stop layer disposed on and contacting the unetched or unpolished top surface of the non-interconnect region of the
lower dielectric layer, wherein the same etch stop layer is also disposed over and contacts a top surface of the interconnect;
and

an upper dielectric layer disposed on the etch stop layer.

US Pat. No. 9,647,035

NON-VOLATILE RESISTIVE RANDOM ACCESS MEMORY CROSSBAR DEVICES WITH MAXIMIZED MEMORY ELEMENT DENSITY AND METHODS OF FORMING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A non-volatile resistive random access memory crossbar device comprising:
a crossbar array comprising a bitline and a wordline;
a hardmask comprising dielectric material and disposed over the bitline, wherein the hardmask and the bitline comprise a first
sidewall and wherein the hardmask and the bitline further comprise a second sidewall on an opposing side thereof from the
first sidewall; and

a memory element layer and a selector layer disposed in overlying relationship, wherein the memory element layer and the selector
layer in overlying relationship are further disposed in overlying relationship on the first sidewall of the bitline and hardmask,
wherein the memory element layer and the selector layer are further disposed in overlying relationship over the second sidewall
of the bitline and hardmask, and wherein the memory element layer and the selector layer are further disposed between the
bitline and the wordline, to form a first memory element and selector pair.

US Pat. No. 9,240,374

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THEREOF

GLOBALFOUNDRIES Singapore...

1. A method for forming a device comprising:
providing a substrate prepared with intermediate dielectric layer having interconnect levels, wherein the interconnect levels
include M1 to MX metal levels, where 1 is the lowest level and X corresponds to a number of metal level, the metal level MX includes a metal pad having an oxidized portion which is formed by hillock in the metal pad which is exposed to an oxygen
ambient; and

forming an upper level having an upper dielectric layer over the dielectric layer having MX, wherein the upper dielectric layer is processed to form a plurality of via openings over the metal pad and a metal line
trench over the via openings, wherein the metal line trench is formed by

providing a patterned mask layer having a pattern corresponding to the metal line trench,
performing an etch to remove portions of the dielectric layer unprotected by the patterned mask,
performing a removal process to remove the patterned mask layer, wherein the removal process does not remove the oxidized
portion of the metal pad, thereby preventing punch through between MX and its adjacent underlying metal level MX-1.

US Pat. No. 9,287,269

1T SRAM/DRAM

GLOBALFOUNDRIES Singapore...

1. A device comprising:
a substrate having top and bottom surfaces, wherein the substrate comprises a first semiconductor material;
an isolation well disposed below the top substrate surface and an area of the substrate between the isolation well and the
top substrate surface serves as a body region of a transistor, wherein the isolation well isolates the body region from the
substrate;

a floating body having a second semiconductor material different than the first semiconductor material disposed over the isolation
well and within the body region, wherein the second semiconductor material is a band engineered (BE) material such that the
floating body is a BE floating body; and

a transistor disposed over the substrate, the transistor comprises
a gate disposed on the top substrate surface, and
first and second diffusion regions disposed in the body region adjacent to first and second sides of the gate.

US Pat. No. 9,411,919

METHOD AND APPARATUS FOR BITCELL MODELING

GLOBALFOUNDRIES SINGAPORE...

1. An apparatus comprising:
at least one processor; and
at least one memory including computer program code for one or more programs, the at least one memory and the computer program
code configured to, with the at least one processor, cause the apparatus to:

determine a state of a bitcell of an integrated circuit (IC) design;
determine a first threshold voltage for the bitcell based on bias voltages of the bitcell corresponding to the state of the
bitcell, wherein a determination is simultaneously made as to whether the bias voltages satisfy corresponding threshold values;

simulate electrical characteristics of the bitcell according to the first threshold voltage to verify the IC design;
cause the simulation to modify the state of the bitcell after simulation of the electrical characteristics of the bitcell
according to the first threshold voltage;

determine a second threshold voltage for the bitcell based on the modification of the state of the bitcell; and
simulate electrical characteristics of the bitcell according to the second threshold voltage to verify the IC design, wherein:
the bias voltages correspond to pin voltages of the bitcell selected from bitline (BL), wordline (WL), control gate (CG),
array ground (AG), and substrate (SUB),

when WL>15V, CG>14V, AG<0.1V, and SUB<0.1V, then the bitcell is determined to be in an erased state,
when WL>15V, CG<0.1V, BL>11V, and SUB<0.1V, then the bitcell is determined to be in a programmed state, and
when BL>0.1V, CG>0.7V, SUB<0.1V, and WL>2.5V, then the bitcell is determined to be readout by access to cell source-drain
current.

US Pat. No. 9,646,963

INTEGRATED CIRCUITS WITH CAPACITORS AND METHODS FOR PRODUCING THE SAME

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1. An integrated circuit comprising:
a first capacitor having a first capacitance/voltage curve with a first inflection point, wherein the first capacitance/voltage
curve has a first inflection point voltage and a first inflection point capacitance at the first inflection point, wherein
a first capacitance is measured at a first applied voltage greater than the first inflection point voltage, and wherein the
first capacitance is greater than the first inflection point capacitance;

a second capacitor having a second capacitance/voltage curve with a second inflection point, wherein the second capacitance/voltage
curve has a second inflection point voltage and a second inflection point capacitance at the second inflection point, wherein
a second capacitance is measured at a second applied voltage that is greater than the second inflection point voltage, and
wherein the second capacitance is less than the second inflection point capacitance; and

a capacitor interconnect electrically connecting the first capacitor and the second capacitor in parallel to produce a combined
capacitance/voltage curve.

US Pat. No. 9,520,172

MAGNETIC MEMORY CELLS WITH LOW SWITCHING CURRENT DENSITY

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1. A memory cell comprising:
a substrate defined with a memory cell region;
a cell selector unit defined on the substrate, wherein the cell selector unit comprises at least one select transistor;
a storage element which comprises a magnetic tunnel junction (MTJ) element coupled to the selector unit, wherein the MTJ element
comprises a free layer, a fixed layer and a tunnel barrier sandwiched between the fixed and free layers;

a spin-orbit-torque (SOT) layer coupled to the selector unit and is in direct contact with the free layer; and
a strain induced layer coupled to a digital line (DL) and in direct contact with the SOT layer, wherein when the DL is activated,
an electric field applied to the strain induced layer induces a strain on the SOT layer.

US Pat. No. 9,318,378

SLOT DESIGNS IN WIDE METAL LINES

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1. A method of fabricating an interconnection comprising:
providing a substrate prepared with a dielectric layer; and
forming a continuous conductive line in the dielectric layer comprising
patterning the dielectric layer to form a trench in the dielectric layer corresponding to the continuous conductive line,
wherein the patterning forms within the trench with at least one dielectric structure positioned in a portion of the trench
that is proximal to the continuous conductive line having a via plug in communication therewith, and

filling the trench with a conductive material that surrounds the at least one dielectric structure to form the continuous
conductive line having at least one dielectric structure therein, wherein the dielectric structure creates a partial discontinuity
within the continuous conductive line.

US Pat. No. 9,293,388

RELIABLE PASSIVATION LAYERS FOR SEMICONDUCTOR DEVICES

GLOBALFOUNDRIES Singapore...

1. A method for forming a semiconductor device comprising:
providing a substrate, the substrate is prepared with a dielectric layer which includes a top metal level of the device, wherein
the top metal level includes top level conductive lines;

forming a top dielectric layer over the top metal level, the top dielectric layer includes top via openings in communication
with the top level conductive lines;

forming a patterned top conductive layer on the top dielectric layer, the patterned top conductive layer includes a top via
in the top via opening and a top conductive line; and

forming a passivation stack comprising
depositing a first oxide passivation sub-layer to line the patterned conductive layer and exposed top dielectric layer,
performing a plasma surface treatment on a surface of the first oxide passivation sub-layer to form a nitrided layer on the
first oxide passivation sub-layer, and

depositing a second nitride passivation sub-layer in direct contact with the nitrided layer, wherein the nitrided layer is
separate and distinct from the second nitride passivation sub-layer and comprises a different composition than the deposited
second nitride passivation sub-layer and improves the passivation integrity of the passivation stack.

US Pat. No. 9,263,322

RELIABLE CONTACTS

GLOBALFOUNDRIES Singapore...

1. A method of forming a device comprising:
providing a substrate having a device component with a contact region;
forming a contact dielectric layer on the substrate, covering the substrate and the device component, wherein forming the
contact dielectric layer comprises

forming a lower contact dielectric layer,
forming an intermediate contact dielectric etch stop layer on the lower contact dielectric layer,
forming an upper contact dielectric layer on the contact dielectric etch stop layer; and
forming a contact opening through the contact dielectric layer, wherein the contact opening has an upper contact sidewall
profile in the upper contact dielectric layer and a lower tapered contact sidewall profile in the lower contact dielectric
layer, wherein forming the contact opening comprises

forming a hard mask over the upper contact dielectric layer,
patterning the hard mask to form a hard mask opening corresponding to location where the contact opening is to be formed,
performing a first etch to remove exposed portion of the upper contact dielectric layer to form an upper portion of the contact
opening having the upper contact sidewall profile,

performing a second etch to remove exposed portion of the intermediate contact dielectric etch stop layer, and
performing a third etch to remove exposed portion of the lower contact dielectric layer to form a lower portion of the contact
opening having the lower tapered contact sidewall profile, wherein the lower tapered contact sidewall profile prevents shorting
with the device component.

US Pat. No. 9,122,160

METHOD AND APPARATUS FOR PERFORMING OPTICAL PROXIMITY AND PHOTOMASK CORRECTION

GLOBALFOUNDRIES Singapore...

1. A method comprising:
performing optical proximity correction of a photomask of a semiconductor layout to generate a corrected photomask;
generating simulated contour shapes based on simulating a masking process of the corrected photomask;
verifying the simulated contour shapes, by a processor, to determine errors associated with the simulated photomask; and
correcting the errors in the simulated contour shapes of the simulated photomask to generate a final photomask,
wherein the verifying the simulated contour shapes is based on at least one of a process variation band, a mask error enhancement
factor, a depth of focus, and one or more hotspots; and

wherein the simulation of the masking process takes into account at least one of e-beam forward and backward scattering, development,
baking, and etching of the corrected photomask.

US Pat. No. 9,076,962

NONVOLATIVE MEMORY

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a memory cell comprising:
providing a substrate;
forming a lower interlevel dielectric (ILD) layer having top and bottom surfaces over the substrate; and
forming a storage unit in a cell dielectric layer above the top surface of the lower ILD layer comprising
forming at least one cell stack having first and second opposing ends along a wordline direction,
forming a storage layer on the first end of the cell stack, wherein the storage layer lines a sidewall of the first end of
the cell stack and the top surface of the lower ILD layer to form a L-shaped storage layer,

forming a top electrode on the first end of the cell stack, wherein the top electrode is formed over the storage layer, and
forming a bottom electrode on the second end of the cell stack, wherein the bottom electrode lines a sidewall of the second
end of the cell stack and the top surface of the lower ILD layer.

US Pat. No. 9,390,962

METHODS FOR FABRICATING DEVICE SUBSTRATES AND INTEGRATED CIRCUITS

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating a device substrate, the method comprising the steps of:
providing a semiconductor substrate with a substrate surface and having a low voltage (LV) region and a second voltage region
that is either a medium voltage (MV) region or a high voltage (HV) region;

thermally oxidizing a trench-forming area on the substrate surface in the second voltage region to form a silicon oxide layer,
wherein the silicon oxide layer has birds beak edges that extend in opposite directions and form rounded trench shoulders
of the semiconductor substrate in the second voltage region;

forming an LV trench in the semiconductor substrate in the LV region such that the semiconductor substrate has an LV shoulder;
forming a trench in the silicon oxide layer and semiconductor substrate in the second voltage region such that the semiconductor
substrate has a rounded trench shoulder adjacent a birds beak edge;

removing the birds beak edge in the second voltage region; and
forming an oxide layer lining each of the LV trench and LV shoulder in the LV region, wherein the LV shoulder and the oxide
layer thereon form an LV trench corner; and

forming an oxide layer lining each of the trench and rounded trench shoulder in the second voltage region, wherein the rounded
trench shoulder in the second voltage region and oxide layer thereon form a rounded trench corner in the second voltage region
that is more rounded than the LV corner.

US Pat. No. 9,336,345

METHODS FOR CONVERTING PLANAR DESIGNS TO FINFET DESIGNS IN THE DESIGN AND FABRICATION OF INTEGRATED CIRCUITS

GLOBALFOUNDRIES SINGAPORE...

1. A method for converting a planar integrated circuit design to a non-planar integrated circuit design comprising:
identifying, using a computer processor of a computing system, a rectangular silicon active area in the planar integrated
circuit design;

superimposing, using the computer processor, a FinFET design grid comprising a plurality of equidistantly-spaced parallel
grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel
to the grid lines;

generating, using the computer processor, a rectangular active silicon marker area encompassing the silicon active area;
generating, using the computer processor, fin mandrels longitudinally along every other grid line of the plurality of grid
lines and within the active silicon marker area and the silicon active area; and

removing, using the computer processor, a portion of the fin mandrels from the design grid so as to generate the non-planar
integrated circuit design, wherein removing the portion of the fin mandrels from the design grid comprises removing the fin
mandrels from areas of the design grid outside of the active silicon marker area.

US Pat. No. 9,299,798

SEMICONDUCTOR DEVICE AND METHODS FOR FORMING A SEMICONDUCTOR DEVICE

GLOBALFOUNDRIES Singapore...

1. A method of forming a device comprising:
providing a substrate prepared with at least a first transistor and a second transistor, each of the first and second transistors
having a gate disposed on the substrate between first and second heavily doped source/drain (S/D) regions in the substrate,
wherein the heavily doped S/D regions are disposed adjacent to first and second sides of the gate and partially underlaps
the gate;

forming a silicide block layer on the substrate, wherein the silicide block layer covers and in direct contact with the first
and second sides and top surface of the gate and the first and second heavily doped S/D regions;

patterning the silicide block layer to expose portions of the first and second heavily doped S/D regions of the first and
second transistors;

forming silicide contacts in the exposed portions of the first and second heavily doped S/D regions, wherein the patterned
silicide block layer is in direct contact with sides and top surface of the gates when the silicide contacts are formed and
the silicide contacts are displaced from the sides of the gates and sides of the first and second heavily doped S/D regions
of the first and second transistors;

forming a contact dielectric layer covering the at least first and second transistors: and
forming contacts in the contact dielectric layer, wherein the contacts are in communication with the silicide contacts in
the heavily doped S/D regions.

US Pat. No. 9,281,278

INTERCONNECTS WITH IMPROVED TDDB

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device comprising:
providing a substrate prepared with a dielectric layer and a first upper etch stop layer formed thereon, wherein the first
upper etch stop layer also serves as a hard mask layer;

forming an interconnect opening in the dielectric and first upper etch stop layer;
filling the interconnect opening with a conductive material to form an interconnect, the interconnect and first upper etch
stop layer having coplanar top surfaces; and

forming a second upper etch stop layer over the coplanar top surfaces, wherein
the first and second upper etch stop layers comprise identical material which comprises NBLOK, low k NBLOK or a combination
thereof, and

the second upper etch stop layer has sufficient adhesion with the first upper etch stop layer to reduce diffusion of the conductive
material.

US Pat. No. 9,257,554

SPLIT GATE EMBEDDED MEMORY TECHNOLOGY AND METHOD OF MANUFACTURING THEREOF

GLOBALFOUNDRIES Singapore...

1. A method for forming a semiconductor device comprising:
providing a substrate prepared with a memory cell region;
forming a first gate structure on the memory cell region;
forming an isolation layer on the substrate and over the first gate structure;
forming a second gate structure, wherein the second gate structure is adjacent to and separated from the first gate structure
by the isolation layer;

processing the first and second gate structures to form at least one split gate structure with first and second adjacent gates;
and

providing asymmetrical source and drain regions adjacent to first and second sides of the split gate structure, wherein providing
the asymmetrical source and drain regions comprises

forming at least one first lightly doped region in a region of the substrate adjacent to the first side of the split gate
structure, and

forming at least one second lightly doped region in a region of the substrate adjacent to the second side of the split gate
structure, wherein the first and second lightly doped regions are formed at different depths from a top surface of the substrate.

US Pat. No. 9,153,473

WAFER PROCESSING

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a device comprising:
providing a substrate having top and bottom pad stacks, wherein each pad stack comprises at least first and second pad layers,
and the second pad layers of the top and bottom pad stacks comprise an initial thickness TT1 and TB1 respectively;

forming shallow trench isolation (STI) regions in the substrate, wherein forming the STI regions comprises
patterning the top pad stack to form openings corresponding to the STI regions,
etching the substrate to form isolation trenches of the STI regions through the top pad stack openings, wherein etching the
substrate removes exposed portions of the substrate and also reduces the thickness TT1 to a second thickness TT2, and

after etching the substrate, performing a pull-back process to simultaneously reduce the thickness TT2 of the second pad layer of the top pad stack to a third thickness TT3 and the thickness of TB1 of the second pad layer of the bottom pad stack to a second thickness TB2, wherein the pull-back process is a batch wet etch process and TT3 is different than TB2; and

performing a removal process to completely and simultaneously remove the second pad layers of the top and bottom pad stacks
having reduced thickness from the substrate after forming the STI regions.

US Pat. No. 9,343,537

SPLIT GATE EMBEDDED MEMORY TECHNOLOGY AND MANUFACTURING METHOD THEREOF

GLOBALFOUNDRIES Singapore...

1. A method of manufacturing a device, comprising:
providing a semiconductor substrate having at least a non-volatile memory (NVM) device section and a high-voltage (HV) device
section;

forming a deep well region of a first electrical polarity in the substrate;
forming a flash well region of a second electrical polarity over the deep well region in the NVM device section;
forming first and second HV well regions over the deep well region in the HV device section, wherein
the first HV well region is of the first electrical polarity, and
the second HV well region is of the second electrical polarity, the second HV well region is disposed between and spaced apart
from the first HV well region and the flash well region;

depositing a first polysilicon layer over the flash well region, the first HV well region, and the second HV well region;
patterning the first polysilicon layer to form first and second floating gates over the flash well region and first and second
lower HV gates over the first and second HV well regions;

depositing a second polysilicon layer over the first polysilicon layer; and
patterning the second polysilicon layer to form
first and second control gates and first and second select gates over the flash well region, and
first and second upper HV gates over the first and second lower HV gates.

US Pat. No. 9,218,875

RESISTIVE NON-VOLATILE MEMORY

GLOBALFOUNDRIES Singapore...

1. A memory cell comprising:
a storage unit, the storage unit
having a plurality of resistive elements which form a plurality of bits of the memory cell, wherein the plurality of bits
are coupled to respective bitlines of a memory array which form columns of a memory array, and

a secondary selector of the storage unit, the secondary selector is coupled to the plurality of bits of the storage unit of
the memory cell;

a primary selector coupled to the storage unit, the primary selector is coupled to a wordline of the memory cell which is
coupled to a plurality of memory cells to form a row of memory cells of the memory array; and

wherein, when the memory cell is selected for access by activating the wordline of the memory array which the memory cell
is coupled to, the secondary selector of the memory cell selects one bit of the plurality of bits to access based on signals
on the respective bitlines.

US Pat. No. 9,184,215

RRAM STRUCTURE AT STI WITH SI-BASED SELECTOR

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:
a substrate;
a well of a first polarity in the substrate;
a shallow trench isolation (STI) region formed in the substrate extending partially into the well;
bands of a second polarity in the substrate, over the well, at opposite sides of the STI region;
an area of the first polarity at a top surface of the substrate over each band;
an area of the second polarity in the substrate over each band, adjacent each area of the first polarity and remote from the
STI region;

a recess in a top portion of the STI region, wherein a bottom surface of the recess is above a top surface of the band;
a resistive random access memory (RRAM) liner on side and bottom surfaces of the recess; and
a top electrode in the recess.

US Pat. No. 9,147,654

INTEGRATED CIRCUIT SYSTEM EMPLOYING ALTERNATING CONDUCTIVE LAYERS

GLOBALFOUNDRIES Singapore...

11. An integrated circuit system comprising:
a substrate including front-end-of-line circuitry;
a first conductive layer including adjacent first conductive traces over the substrate;
a viabar with a horizontal via length at least twice as long as a horizontal via width separating horizontally the adjacent
first conductive traces in the first conductive layer;

a second conductive layer spaced apart from and not overlapping the first conductive layer, the second conductive layer including
adjacent second conductive traces separated horizontally by another of the viabar; and

a third conductive layer connected to the first conductive layer by one of the viabar separating the adjacent second conductive
traces, the viabar connecting the first conductive layer and the third conductive layer passing through the second conductive
layer without contacting the adjacent second conductive traces as part of a vertical parallel plate capacitor structure.

US Pat. No. 9,129,910

WAFER PROCESSING

GLOBALFOUNDRIES SINGAPORE...

16. A method of forming a device comprising:
providing a wafer substrate having top and bottom pad stacks on top and bottom surfaces of the wafer substrate respectively,
wherein each pad stack comprises at least first and second pad layers, and the second pad layer is provided over the first
pad layer;

forming a protective layer only over a top surface of the top pad stack;
removing the second pad layer of the bottom pad stack by a batch process after forming the protective layer, wherein the entire
protective layer remains and protects the top pad stack during removing of the second pad layer of the bottom pad stack;

removing the entire protective layer from the top surface of the top pad stack after removing the second pad layer of the
bottom pad stack and prior to forming trenches;

forming the trenches in the substrate, wherein forming the trenches comprises
patterning the top pad stack using mask and etch techniques after removing the entire protective layer from the top surface
of the top pad stack, and

patterning the substrate to form the trenches using the patterned top pad stack; and
forming isolation regions in the trenches.

US Pat. No. 9,196,719

ESD PROTECTION CIRCUIT

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:
a substrate defined with a device region, the device region comprises an ESD protection circuit having a transistor, wherein
the transistor is devoid of a drift well, the transistor includes

a gate having first and second sides,
a first diffusion region adjacent to the first side of the gate, and
a second diffusion region displaced away from the second side of the gate,
wherein the first and second diffusion regions comprise dopants of a first polarity type;
a first device well encompasses the device region and a second device well disposed within the first device well, wherein
the second device well encompasses the first diffusion region and at least a part of the gate without encompassing the second
diffusion region;

a third well disposed within the second device well; and
a drain well encompasses the second diffusion region and extends below the gate.

US Pat. No. 9,171,953

FINFET WITH STRESSORS

GLOBALFOUNDRIES Singapore...

1. A device comprising:
a substrate prepared with a dielectric layer on its top surface,
wherein the dielectric layer comprises a non-selectively etched dielectric top surface;
a fin structure
disposed on the substrate in the dielectric layer,
wherein the fin structure includes a bottom portion and a top portion,
the top portion extending above the non-selectively etched dielectric top surface,
wherein
the top portion determines a device height and
the non-selectively etched top surface reduces height variations of fin structures across the wafer;
a gate traversing the fin structure;
S/D regions in the fin structure adjacent to the gate;
a channel between the S/D regions below the gate; and
a first stressor to cause the channel to have a first strain to improve carrier mobility;
wherein the fin structure comprises a first portion and a second portion above the first portion; and
a void
partially beneath the gate and
separating the first and second portions of the fin structure.

US Pat. No. 9,165,610

NON-VOLATILE MEMORY CELL ARRAYS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES

GLOBALFOUNDRIES SINGAPORE...

1. A memory array, comprising:
first, second, third, and fourth memory cells each having a first transistor and a second transistor, each of the first transistors
and second transistors having a source, a drain, and a gate;

a first word-line electrically coupled with the gate of the first transistor of the first memory cell and the gate of the
first transistor of the second memory cell;

a second word-line electrically coupled with the gate of the second transistor of the first memory cell, the gate of the second
transistor of the second memory cell, the gate of the first transistor of the third memory cell, and the gate of the first
transistor of the fourth memory cell; and

a third word-line electrically coupled with the gate of the second transistor of the third memory cell and the gate of the
second transistor of the fourth memory cell.

US Pat. No. 9,159,565

INTEGRATED CIRCUIT SYSTEM WITH BAND TO BAND TUNNELING AND METHOD OF MANUFACTURE THEREOF

GLOBALFOUNDRIES Singapore...

11. An integrated circuit system comprising:
a semiconductor substrate;
a well region, having a first conductivity, implanted on the semiconductor substrate;
a gate oxide layer patterned on the well region;
a source, having a second conductivity, implanted at a first angle;
a dopant pocket, having a third conductivity that is opposite the second conductivity, completely within the source and selectively
implanted with mid-gap dopants at the first angle; and

a drain, having the third conductivity, implanted at a second angle for forming a transistor channel asymmetrically positioned
under the gate oxide layer.

US Pat. No. 9,064,803

SPLIT-GATE FLASH MEMORY EXHIBITING REDUCED INTERFERENCE

GLOBALFOUNDRIES Singapore...

1. A method comprising:
providing a memory gate stack over a substrate; providing a word gate over the substrate;
and providing a dielectric spacer between the word gate and the memory gate stack, the dielectric spacer comprising a low-k
layer and a first high-k layer each layer being formed on the substrate to a same height over the entire length of the low-k
and first high-k layers, the dielectric spacer occupying the entire space between the memory gate stack and the word gate.

US Pat. No. 9,230,990

SILICON-ON-INSULATOR INTEGRATED CIRCUIT DEVICES WITH BODY CONTACT STRUCTURES

GLOBALFOUNDRIES SINGAPORE...

1. A silicon-on-insulator integrated circuit comprising:
a semiconductor substrate layer;
an oxide insulating material layer disposed over the substrate layer;
a semiconductor layer formed over the insulating material layer;
within the semiconductor layer, a plurality of parallel, spaced apart first shallow trench isolation (STI) structures that
extend completely though the semiconductor layer to contact with the oxide insulating material layer;

within the semiconductor layer, a plurality of parallel, spaced apart second STI structures that extend only part-way into
the semiconductor layer, wherein at least two of the plurality of second STI structures are provided such that no first STO
structure is provided therebetween;

a plurality of body contact regions in the semiconductor substrate between at least one of the first and at least one of the
second STI structures;

source/drain regions in the semiconductor substrate between the at least two of the plurality of second STI structures;
a gate structure having a first portion over the plurality of second STI structures and a second portion over the source/drain
regions; and

contact plugs to the body contact regions, to the source/drain regions, and to the gate structure.

US Pat. No. 9,488,975

METHODS AND MEDIA FOR LOT DISPATCH PRIORITY

GLOBALFOUNDRIES SINGAPORE...

12. A method of fabricating a semiconductor device from a substrate, the method comprising:
providing a lot that includes the substrate;
prioritizing dispatch of the lot according to a dispatch method comprising:
calculating a lot level goal for processing time of the lot based on a normal goal in response to a lack of delay in processing
the lot or in response to a recovered delay in processing the lot;

calculating the lot level goal for processing time of the lot based on a vectored goal in response to a delay in processing
the lot, wherein the vectored goal is based at least in part on a predetermined time in which to reduce the normal goal to
recover from a delay in processing the lot; and

prioritizing dispatch of the lot based at least in part on the lot level goal; and
processing the lot based on the dispatch method.
US Pat. No. 9,395,621

PELLICLES AND DEVICES COMPRISING A PHOTOMASK AND THE PELLICLE

GLOBALFOUNDRIES SINGAPORE...

1. A pellicle comprising:
a pellicle frame comprising four pellicle walls that define a trapezoidal area sized and shaped to correspond to a pattern
area of a lithographic photomask; and

a pellicle film extending across the trapezoidal area and affixed to a film-side edge of the pellicle frame;
wherein any one of the four pellicle walls has a vent hole therethrough, the vent hole being located a distance (d) from a
corner of the frame; and

a baffle positioned within the trapezoidal area, wherein the baffle extends across the vent hole without completely blocking
the vent hole.

US Pat. No. 9,362,171

THROUGH VIA CONTACTS WITH INSULATED SUBSTRATE

GLOBALFOUNDRIES Singapore...

1. A method of forming a device comprising:
providing a substrate, wherein the substrate comprises a buried oxide (BOX) layer sandwiched by a base substrate and a bottom
substrate, wherein the BOX layer comprises first and second major surfaces, the first major surface contacts a bottom surface
of the base substrate and the second major surface contacts a top surface of the bottom substrate;

forming a dielectric layer on the base substrate;
forming through via (TV) contacts within the substrate, wherein the TV contacts are formed in through via openings that extend
from a top surface of the dielectric layer to within the BOX layer of the substrate and wherein the through via openings terminate
within the BOX layer and at a distance away from the second major surface of the BOX layer which contacts the top surface
of the bottom substrate;

forming upper interconnect levels on the base substrate over a top surface of the TV contacts, wherein the dielectric layer
separates the upper interconnect levels from the base substrate;

providing a carrier substrate over a top surface of the upper interconnect levels; and
removing the bottom substrate and a portion of the BOX layer, wherein removing the portion of the BOX layer exposes a bottom
surface of the TV contacts, and wherein the remaining BOX layer serves as a first redistribution (RDL) dielectric layer of
a lower RDL of the device.

US Pat. No. 9,099,434

HIGH VOLTAGE DEVICE

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:
a substrate having a device region, wherein the device region comprises a source region, a gate region and a drain region
defined thereon;

a gate disposed on the gate region;
a field structure surrounding the drain region without surrounding the source region;
a source and a drain in the source region and drain region, wherein the drain is separated from the gate on a second side
of the gate and the source is adjacent to a first side of the gate; and

an interconnection to the field structure, the interconnection is coupled to a potential, wherein the potential distributes
the electric field across the substrate between the second side of the gate and the drain.

US Pat. No. 9,087,906

GROUNDING OF SILICON-ON-INSULATOR STRUCTURE

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a device comprising:
providing a substrate having at least a first region and a second region prepared with isolation regions, wherein the first
region is referred to as a chip guarding area and the second region defines a chip region of which at least one transistor
is to be formed, wherein the substrate comprises a top surface layer, a support substrate and an insulator layer isolating
the top surface layer from the support substrate;

forming at least one transistor in the second region of the substrate;
forming at least one substrate contact structure in the first region of the substrate, wherein the substrate contact structure
passes through at least the top surface layer, insulator layer and isolation region and contacts a doped region in the support
substrate in the first region of the substrate, and wherein the substrate contact structure is connected to at least one conductive
line with a desired potential to prevent charging of the support substrate at system level.

US Pat. No. 9,318,399

SEMICONDUCTOR WAFERS EMPLOYING A FIXED-COORDINATE METROLOGY SCHEME AND METHODS FOR FABRICATING INTEGRATED CIRCUITS USING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A semiconductor wafer employing a fixed-coordinate metrology comprising:
an external scribe region in the form of a first rectangular ring, the first rectangular ring defining a first interior space
inward from the external scribe region, wherein the external scribe region comprises a plurality of overlay markings and/or
critical dimension (CD) markings, and wherein the external scribe region comprises, as the first rectangular ring, two horizontal
scribe marking areas defining upper and lower portions of the external scribe region and two MVS target areas disposed along
opposite side regions of the external scribe region, each MVS target area being separated from the two horizontal scribe marking
areas by two vertical scribe marking areas;

an interior scribe region in the form of a second rectangular ring, disposed within the first interior space and immediately
adjacent to the external scribe region at all points along its exterior perimeter, the second rectangular ring defining a
second interior space inward from the interior scribe region, the second interior space being wholly within the first interior
space;

a technology-specific tile region disposed within the second interior space and immediately adjacent to the interior scribe
region;

an electrical testable scribe line measurement (ETSLM) region disposed within the second interior space and immediately adjacent
to both the technology-specific tile region and the interior scribe region; and

a free floorplan area disposed within the second interior space and immediately adjacent to both the ETSLM region and the
interior scribe region.

US Pat. No. 9,196,356

STACKABLE NON-VOLATILE MEMORY

GLOBALFOUNDRIES SINGAPORE...

1. A memory cell of a memory array having a plurality of memory cells interconnected by wordlines and bitlines comprising:
a storage unit having at least first and second resistive elements R1 and R2, wherein a resistive element includes first and second storage terminals,

the first storage terminal of R1 is coupled to a first bitline of the memory array at node N1 of the memory cell, and

the first storage terminal of R2 is coupled to a second bitline of the memory array at node N2 of the memory cell;

a cell selector comprising first and second selector terminals, wherein
the first selector terminal is coupled to a wordline of the memory array, and
the second selector terminal is commonly coupled to the second storage terminals of R1 and R2 of the storage unit at node N3, the cell selector,

when active, selects the memory cell for access; and
when appropriate signals are applied to the memory cell, the cell selector selects an appropriate resistive element from the
first and second resistive elements R1 and R2 of the storage unit.

US Pat. No. 9,128,117

LASER-ENHANCED CHEMICAL ETCHING OF NANOTIPS

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming an integrated circuit (IC) device, comprising:
sharpening a nanotip, the sharpening comprising:
immersing the nanotip in an etchant, the nanotip comprising a base and an apex, the apex having a diameter smaller than a
diameter of the base, and

irradiating the nanotip with laser fluence to establish a temperature gradient in the nanotip along a direction from the apex
to the base of the nanotip such that the apex and base are etched at different rates;

performing wafer metrology on a wafer having a plurality of devices using the sharpened nanotip to measure device performance.

US Pat. No. 9,209,297

INTEGRATION OF TRENCH MOS WITH LOW VOLTAGE INTEGRATED CIRCUITS

GLOBALFOUNDRIES Singapore...

1. A method comprising:
forming a first trench in a substrate, the first trench having a first width;
forming a first oxide layer on side surfaces of the first trench;
forming a second trench in the substrate, below the first trench, the second trench having a second width less than the first
width;

forming a second oxide layer on side and bottom surfaces of the second trench;
forming spacers on sides of the first and second trenches;
removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers;
filling the first and second trenches with a first poly-silicon to form a drain region;
removing an upper portion of the spacers, leaving a lower portion of the spacers and exposing an upper portion of side surfaces
of the first poly-silicon;

forming a third oxide layer on the upper portion of the side surfaces and a top surface of the first poly-silicon; and
filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the
drain region.

US Pat. No. 9,059,582

FALSE-TRIGGERED IMMUNITY AND RELIABILITY-FREE ESD PROTECTION DEVICE

GLOBALFOUNDRIES Singapore...

1. An electrostatic discharge (ESD) protection device for protecting a one-time programmable (OTP) integrated circuit device,
comprising:
a bipolar lateral transistor coupled to a pair of supply terminals;
a control circuit coupled to a control element of the transistor;
a false trigger prevention circuit having an output connected to the control circuit;
a downsize capacitive circuit;
wherein the false trigger prevention circuit and the downsize capacitive circuit are connected in series across the supply
terminals, and

wherein the ESD protection device has a trigger voltage of at least 8.6V.

US Pat. No. 9,397,139

INTEGRATED INDUCTOR AND MAGNETIC RANDOM ACCESS MEMORY DEVICE

GLOBALFOUNDRIES SINGAPORE...

17. A device comprising:
a substrate defined with at least first and second regions;
a first upper dielectric layer disposed over the substrate, wherein the first upper dielectric layer comprises a first upper
interconnect level with a plurality of metal lines in the first and second regions;

a dielectric layer disposed over the first upper dielectric layer, wherein the dielectric layer comprises a second upper interconnect
level with a plurality of metal lines in the first and second regions;

a magnetic random access memory (MRAM) cell, wherein the MRAM cell is disposed between the first and second upper interconnect
levels in the first region; and

an inductor disposed in the second region, wherein the inductor comprises a lower inductor level formed from the metal lines
in the first upper interconnect level and an upper inductor level formed from the metal lines in the second upper interconnect
level, wherein the metal lines in the lower inductor level and upper inductor level are coupled by via contacts to form coils
of the inductor.

US Pat. No. 9,343,413

ESD PROTECTION FOR HIGH VOLTAGE APPLICATIONS

GLOBALFOUNDRIES SINGAPORE...

1. An ESD module comprising:
an ESD circuit coupled between a first source and a second source, wherein the ESD circuit is a silicon controlled rectifier
(SCR) based ESD circuit having a parasitic circuit with first and second junction transistors, the first junction transistor
includes a first collector, a first base and a first emitter, the second junction transistor includes a second collector,
a second base and a second emitter, the SCR based ESD circuit comprises an ESD region having a width and length direction
with

a first ESD well in a device region having first polarity type dopants,
a second ESD well in the device region having second polarity type dopants, wherein the first and second wells abut in the
width direction,

first, second and third first ESD contacts in the first ESD well, wherein the first and third first ESD contacts include first
polarity type dopants and the second first ESD contact includes second polarity type dopants,

first, second and third second ESD contacts in the second ESD well, wherein the first and third second ESD contacts include
second polarity type dopants and the second second ESD contact includes first polarity type dopants, and

wherein the first and second first ESD contacts and the first and second second ESD contacts extend the width of the device
region completely and the third first ESD contact and the third second ESD contact extend the width of the device region partially
from opposite sides of the device region; and

a trigger circuit for activating the ESD circuit to provide a low resistance current path between the first and second sources,
the trigger circuit comprising

a first trigger between the first source and the first collector of the first junction transistor of the parasitic circuit
of the ESD circuit, wherein the first collector is the first ESD well, and

a second trigger between the second source and the second collector of the second junction transistor of the parasitic circuit
of the ESD circuit, wherein the second collector is the second ESD well, and

wherein the trigger circuit provides a low trigger voltage to activate the ESD circuit.

US Pat. No. 9,489,004

BANDGAP REFERENCE VOLTAGE GENERATOR CIRCUITS

GLOBALFOUNDRIES SINGAPORE...

1. A bandgap reference voltage generator circuit, comprising:
an operational amplifier comprising: a first inverting input coupled to a first node and being configured to receive a first
voltage generated at the first node and a second non-inverting input coupled to a second node and being configured to receive
a second voltage generated at the second node, and an output that is configured to generate an output voltage;

a current mirror configured to be coupled to a supply voltage less than or equal to 1.35 volts, wherein the current mirror
comprises: a first P-channel MOSFET configured to generate a third voltage and a first current;

a first branch coupled to the current mirror and configured to receive a second current that is a first portion of the first
current, wherein the first branch comprises: a first PNP bipolar junction transistor; and a first resistor coupled to the
first PNP bipolar junction transistor at the second node that is coupled to the second non-inverting input, wherein the first
resistor has a first resistance value;

a second branch coupled to the first branch and configured to receive a third current that is a second portion of the first
current, wherein the second branch comprises: a voltage divider comprising: a second resistor coupled to a third resistor
and being configured to divide the third voltage to generate the first voltage at the first node that is coupled to the first
inverting input, wherein a second resistance value of the second resistor is the same as a third resistance value of the third
resistor and the same as the first resistance value of the first resistor;

a third branch coupled between the second branch and ground, wherein the third branch comprises: a fourth resistor having
a fourth resistance value and being configured to receive a fourth current that is a third portion of the first current, wherein
the fourth current flows through the fourth resistor to generate a fifth voltage that lowers the third voltage low enough
to cause the first P-channel MOSFET to operate in saturation mode when the supply voltage is less than or equal to 1.35 volts,
wherein a first difference between the supply voltage and the third voltage is greater than a second difference between a
gate-to-source voltage of the first P-channel MOSFET and a threshold voltage of the first P-channel MOSFET, which causes the
first P-channel MOSFET to operate in saturation mode; and

a fourth branch comprising: a fifth resistor coupled to ground and the current mirror, wherein the fifth resistor has a fifth
resistance value that is less than the fourth resistance value, wherein the fifth resistor is configured to receive a fifth
current from the current mirror that is used to generate a bandgap reference voltage that is less than or equal to 0.8 volts,
wherein the fifth resistance value is selected to cause a temperature coefficient of the bandgap reference voltage to be approximately
equal to zero.

US Pat. No. 9,425,127

METHOD FOR FORMING AN AIR GAP AROUND A THROUGH-SILICON VIA

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:
a substrate;
a conductive material extending into the substrate;
an air gap extending into the substrate, between at least part of the conductive material and the substrate;
a cap having a portion over the air gap, and a portion within the air gap, the portion within the air gap extending from a
first portion of the cap at the top of the air gap to a second portion of the cap within the air gap;

a first oxide layer between the air gap and the substrate;
a second oxide layer extending into the substrate between the air gap and the conductive material, the second oxide layer
surrounding side and bottom surfaces of the conductive material; and

a metal liner formed between the second oxide layer and the conductive material, wherein the second oxide layer is in direct
contact with the metal liner.

US Pat. No. 9,341,961

CROSS TECHNOLOGY RETICLE (CTR) OR MULTI-LAYER RETICLE (MLR) CDU, REGISTRATION, AND OVERLAY TECHNIQUES

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:
providing a transmissive or reflective reticle having a frame area and a prime area, the frame area surrounding the prime
area;

determining differences in RT (reticle transmission or reflection for a transmissive or reflective reticle, respectively)
across the prime area; and

providing disposable RT adjustment structures in the prime area in dummy filled regions on the reticle to decrease or increase
the RT differences,

wherein the reticle comprises a multilayer reticle (MLR),
wherein determining RT differences comprises determining RT differences between different layers of the MLR, and
wherein the RT is adjusted subsequent to a determination of an average RT tuning of respective layers of the MLR.

US Pat. No. 9,236,240

WAFER EDGE PROTECTION

GLOBALFOUNDRIES SINGAPORE...

1. A method for forming a device comprising:
providing a wafer substrate having first and second regions, wherein the second region includes an inner region of the substrate
while the first region includes an outer peripheral region from an edge of the substrate towards the inner region;

providing a hard mask stack over the wafer substrate;
providing a soft mask over the hard mask stack, wherein the soft mask having a pattern corresponding to at least one trench
to be formed in the substrate;

providing a protection unit above the substrate, wherein the protection unit includes a region having a total width WT defined by outer and inner rings of the protection unit and wherein WT of the protection unit comprises a first region having a first width W1 and a second region having a second width W2; and

etching the substrate to form the at least one trench in the second region of the substrate, wherein the WT of the protection unit is sufficiently wide to protect the first region of the wafer substrate such that the first region
is devoid of trench.

US Pat. No. 9,230,886

METHOD FOR FORMING THROUGH SILICON VIA WITH WAFER BACKSIDE PROTECTION

GLOBALFOUNDRIES SINGAPORE...

15. A device comprising:
a silicon substrate;
a silicon composite layer covering a bottom surface of the silicon substrate, the silicon composite layer having a bottom
surface;

an oxide layer between the silicon composite layer and both the silicon substrate and the TSV;
an exposed portion of a conductive through silicon via (TSV) protruding 0.5 microns (?m) to 3 ?m out from the bottom surface
of the silicon substrate, the oxide layer and the bottom surface of the silicon composite layer;

a protective film contiguous with the TSV, surrounding the TSV between the TSV and the silicon substrate; and
a passivation layer contiguous with the silicon substrate, surrounding the TSV between the TSV and the silicon substrate,
and extending to a bottom surface of the silicon composite layer,

wherein only the protective film extends down sides of the exposed portion of the TSV below the bottom surface of the silicon
composite layer.

US Pat. No. 9,286,435

SYSTEM AND METHODS FOR OPC MODEL ACCURACY MANAGEMENT AND DISPOSITION

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:
employing a computer for quantifying optical proximity correction (OPC) model accuracy by performing operations comprising
selecting an OPC model at least by performing quad matrix management which comprises
obtaining wafer data from a calibration test pattern,
classifying the same wafer data obtained from the calibration test pattern into four quadrants of a quad matrix, and
utilizing one of the four quadrants to quantify OPC model accuracy;
creating a photomask based at least in part on the selected OPC model after performing the quad matrix management;
performing wafer verification; and
verifying lithography performance.

US Pat. No. 9,087,813

CONTROL GATE

GLOBALFOUNDRIES SINGAPORE...

1. A semiconductor device comprising:
a substrate;
a split gate structure disposed on the substrate, wherein the split gate structure comprises
a second gate disposed on the substrate;
an inter-gate dielectric layer disposed on the substrate and over the second gate;
a first gate, wherein the first gate is adjacent to and separated from the second gate by the inter-gate dielectric layer,
wherein the inter-gate dielectric layer below the first gate and between the first and second gates corresponds to a charge
storage layer, the first and second gates include first and second adjacent sidewalls which are adjacent to the first and
second gates and first and second non-adjacent sidewalls;

a first diffusion region adjacent to the first non-adjacent sidewall of the first gate and a second diffusion region adjacent
to the second non-adjacent sidewall of the second gate; and

an e-field equalizer which at least extends from the first non-adjacent sidewall to belowthe first gate, wherein the e-field equalizer improves uniformity of an e-field across the first gate during operation to
improve charge trapping capabilities of the charge storage layer.

US Pat. No. 9,406,577

WAFER STACK PROTECTION SEAL

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a semiconductor device comprising:
providing first and second wafers with top and bottom surfaces, the wafers include edge and non-edge regions, wherein the
first wafer includes devices formed in the non-edge region;

forming a first protection seal at the edge region of the first wafer, wherein the protection seal is formed by depositing
a polymer material on the top surface of the first wafer to a height about 10-40% greater than a final gap between the first
and second wafers when bonded; and

bonding the first and second wafers to form a device stack, wherein the polymer material on the first wafer contacts the second
wafer and is compressed by the first and second wafers, the polymer material expands laterally to cover at least partially
edges of the wafers and form a bonded wafer protection seal, the bonded wafer protection seal protects the devices in subsequent
processing.

US Pat. No. 9,276,206

SCALABLE AND RELIABLE NON-VOLATILE MEMORY CELL

GLOBALFOUNDRIES Singapore...

1. A method for forming a device comprising:
providing a substrate prepared with a cell region; and
forming first and second memory cells of a memory cell pair in the cell region, wherein forming the memory cell pair comprises
forming first and second storage gates (SGs) of the first and second memory cells, wherein a SG includes a primary gate dielectric
layer, a floating gate (FG) electrode layer, a control gate (CG) dielectric layer and a CG electrode layer,

forming an elevated source line terminal between the SGs of the memory cell pair, the elevated source line having a top surface
extending above a top surface of the substrate and below a top of the FG electrode layer,

forming an erase gate (EG) over the elevated source line, the erase gate is isolated from first sidewalls of the SGs and source
line terminal,

forming first and second access gates (AGs) adjacent to the SGs, and
forming first and second bitline terminals adjacent to the first and second AGs.

US Pat. No. 9,272,899

BONDING METHOD USING POROSIFIED SURFACES FOR MAKING STACKED STRUCTURES

GLOBALFOUNDRIES Singapore...

1. A device comprising:
a first device having a first semiconductor substrate having first and second major surfaces, wherein the first semiconductor
substrate comprises

a first bonding region with a first bonding surface, wherein the first bonding surface comprises a porosified region which
is part of first substrate material of the first semiconductor substrate and extends from the first major surface of the first
semiconductor substrate to a depth shallower than the second major surface of the first semiconductor substrate; and

a second device which comprises a second semiconductor substrate having first and second major surfaces, wherein the second
semiconductor substrate comprises

a second bonding region with a second bonding surface, wherein the second bonding surface includes a conductive contact comprising
a through silicon via (TSV) contact, wherein

the second bonding surface is aligned to be above and facing the porosified region of the first bonding surface, and
the second bonding surface of the conductive contact is bonded to the first bonding surface with the porosified region.

US Pat. No. 9,269,766

GUARD RING FOR MEMORY ARRAY

GLOBALFOUNDRIES SINGAPORE...

1. A method for forming a device comprising:
providing a substrate having an array region in which memory cells are to be formed;
forming storage gates of the memory cells in the array region, wherein each of the storage gates comprises a floating gate
and a control gate formed over the floating gate;

forming a guard ring surrounding the array region;
forming a gate electrode layer on the substrate, wherein the gate electrode layer fills gaps between the storage gates having
the floating and control gates and guard ring as well as covering at least the control gates of the storage gates; and

planarizing the gate electrode layer to produce a planar surface between the gate electrode layer, storage gates and guard
ring, wherein the guard ring maintains thickness of the gate electrode layer in the array region such that thickness of the
storage gates across center and edge regions of the array region is uniform.

US Pat. No. 9,520,299

ETCH BIAS CONTROL

GLOBALFOUNDRIES SINGAPORE...

21. The method of claim 1 wherein the modified dummy structures are tailored to achieve the desired etch bias according to a density equation.

US Pat. No. 9,362,297

INTEGRATED CIRCUITS HAVING IMPROVED SPLIT-GATE NONVOLATILE MEMORY DEVICES AND METHODS FOR FABRICATION OF SAME

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit comprising:
a semiconductor substrate having a lower surface at a first height, an upper surface at a second height greater than the first
height, and a side surface extending vertically from the lower surface to the upper surface;

a source/drain region located at the lower surface of the semiconductor substrate;
a charge storage structure overlying the semiconductor substrate and having a first sidewall overlying the source/drain region,
aligned with the side surface, and directly over the source/drain region;

a control gate overlying the source/drain region; and
a first select gate overlying the upper surface of the semiconductor substrate, wherein a first memory cell is formed by the
control gate and the first select gate.

US Pat. No. 9,361,992

LOW VOLTAGE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATION

GLOBALFOUNDRIES SINGAPORE...

1. A semiconductor device, comprising: a memory cell including a plurality of transistors;
a trimmable sense amplifier electrically connected to said memory cell configured to provide variable current to said memory
cell, wherein said trimmable sense amplifier comprises:

a reference current source;
a first current mirror including a first transistor and a plurality of second transistors, and
a plurality of switches electrically connected to said plurality of second transistors for connecting and disconnecting at
least one of said second transistors.

US Pat. No. 9,213,137

SEMICONDUCTOR DEVICES INCLUDING PHOTODETECTORS INTEGRATED ON WAVEGUIDES AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating a semiconductor device, the method comprising:
etching a waveguide layer in a detector region of a semiconductor substrate to form a recessed waveguide layer section; and
forming a ridge structure germanium (Ge) photodetector overlying a portion of the recessed waveguide layer section, wherein
forming the ridge structure Ge photodetector comprises:

forming a Ge fill overlying the recessed waveguide layer section;
selectively etching the Ge fill to form a first recessed Ge layer section, a second recessed Ge layer section, and a Ge ridge
structure disposed between the first and second recessed Ge layer sections;

P+ doping the first recessed Ge layer section and a first sidewall portion of the Ge ridge structure that are adjacent to
each other to form a P+ electrode; and

N+ doping the second recessed Ge layer section and a second sidewall portion of the Ge ridge structure that are adjacent to
each other to form an N+ electrode.

US Pat. No. 9,184,165

1T SRAM/DRAM

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:
a substrate having top and bottom surfaces, wherein the substrate comprises a device region surrounded by an isolation region;
an isolation buffer layer disposed in the device region and below the top substrate surface, wherein the isolation buffer
layer is an amorphized portion of the substrate, and an area of the substrate between the isolation buffer layer and the top
substrate surface serves as a body region of a transistor, and wherein the isolation region extends from the top substrate
surface and partially into the isolation buffer layer; and

a transistor disposed in the device region over the substrate, the transistor comprises
a gate disposed on the top substrate surface, and
first and second diffusion regions disposed in the body region adjacent to first and second sides of the gate.

US Pat. No. 9,054,209

COMPACT CHARGE TRAP MULTI-TIME PROGRAMMABLE MEMORY

GLOBALFOUNDRIES Singapore...

1. A method comprising:
forming a gate stack on a substrate;
forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed
on the other side of the gate stack;

forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack;
forming a charge-trapping (CT) spacer on each tunnel oxide liner; and
forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the
gate stack,

wherein the source extension region and source are formed on the one side of the gate stack and the drain is formed on the
other side of the gate stack with no drain extension region being formed.

US Pat. No. 9,362,274

SELF-ALIGNED CONTACT FOR REPLACEMENT METAL GATE AND SILICIDE LAST PROCESSES

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:
a substrate;
an STI region in a portion of the substrate;
a first high-k metal gate stack having first spacers, on the substrate between source/drain regions;
a second high-k metal gate stack having second spacers on the STI region;
a substantially entirely planar Al2O3 or HfO2 etch stop layer disposed directly in contact with: an upper surface of the first and second high-k metal gate stacks, an upper
surface of the first spacers, and an upper surface of the second spacers, the etch stop layer having an opening over a portion
of the second high-k metal gate stack;

a pair of third spacers on the etch stop layer over the first high-k metal gate stack;
a pair of fourth spacers on the etch stop layer on the second high-k metal gate stack;
an ILD between the third spacers;
a first contact on the first high-k metal gate stack and over a portion of the first spacers; and
a second contact between and over a portion of the fourth spacers.

US Pat. No. 9,287,197

THROUGH SILICON VIAS

Globalfoundries Singapore...

1. A method of forming a device comprising:
providing a substrate with top and bottom surfaces;
forming a through silicon via (TSV) in the substrate through the top surface;
lining the TSV and the top surface of the substrate with an insulation stack having a first insulation layer, a polish stop
layer and a second insulation layer, wherein the insulation stack lines without filling the TSV, wherein the polish stop layer
lines the first insulation layer and the second insulation layer lines the polish stop layer;

forming a conductive layer on the substrate, the conductive layer filling the TSV over the insulation stack comprising the
first insulation layer, the polish stop layer and the second insulation layer; and

planarizing the substrate to form a top portion of a TSV contact in the TSV, the planarizing removes excess conductive material
of the conductive layer and the second insulation layer over the top surface of the substrate, the planarizing stops on the
polish stop layer of the insulation stack over the top surface of the substrate, the planarizing leaves the polish stop layer
remaining over the top surface of the substrate and a top surface of the conductive material in the TSV is planar with a top
surface of the polish stop layer over the top surface of the substrate, forming the top portion of the TSV contact.

US Pat. No. 9,368,488

EFFICIENT INTEGRATION OF CMOS WITH POLY RESISTOR

GLOBALFOUNDRIES Singapore...

1. A method for forming a device comprising:
providing a substrate, wherein the substrate includes a resistor region defined by a resistor isolation region and a transistor
region surrounded by a transistor isolation region;

forming a gate layer over the substrate;
patterning the gate layer to define a resistor gate on the resistor isolation region and to define a transistor gate on the
transistor region, wherein the resistor and transistor gates are separate gates;

forming a first implant mask with at least first and second openings on the substrate after the resistor and the transistor
gates are defined, wherein the first opening exposes the resistor region and the second opening exposes the transistor region;

implanting resistor well dopants to form a resistor well in the substrate, the resistor well is disposed in the substrate
below the resistor isolation region;

implanting resistor dopants into the resistor gate to define the sheet resistance of the resistor gate;
implanting lightly doped drain (LDD) dopants into the substrate to form LDD regions in the transistor region adjacent to the
transistor gate, wherein implanting the resistor well dopants to form the resistor well, implanting the resistor dopants into
the resistor gate and implanting LDD dopants to form the LDD regions are performed using the first implant mask; and

implanting terminal dopants to form first and second resistor terminals at sides of the resistor gate, wherein a central portion
of the resistor gate sandwiched by the resistor terminals serves as a resistive portion.

US Pat. No. 9,406,687

INTEGRATION OF MEMORY DEVICES WITH DIFFERENT VOLTAGES

GLOBALFOUNDRIES SINGAPORE...

1. A method for forming a device comprising:
providing a substrate prepared with at least a memory cell region having first and second sub-regions and a logic region having
input/output (I/O) region and core region;

forming first voltage memory cell in the first sub-region and forming second voltage memory cell in the second sub-region
of the memory cell region of the same substrate, wherein the first voltage memory cell operates in a first voltage and the
second voltage memory cell operates in a second voltage which is higher than the first voltage, wherein forming each of the
first and second voltage memory cells comprises

forming a split gate having first and second gates, wherein the first gate is a storage gate having a control gate over a
floating gate and the second gate is a wordline; and

forming logic I/O device in the I/O region and logic core device in the core region.

US Pat. No. 9,263,132

DOUBLE GATED FLASH MEMORY

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:
etching to form a fin structure on a substrate;
depositing a hard mask material on the fin structure;
forming an oxide over the substrate;
etching the oxide to expose an upper portion of the fin structure;
removing the hard mask material;
performing an isolation and well implantation to form a well;
providing a memory gate stack and a first tunneling oxide layer along a first side surface of the fin structure; and
providing a select gate and a second tunneling oxide layer along a second side surface of the fin structure,
wherein providing the memory gate stack and the select gate stack includes:
depositing a floating gate material on the first side surface of the fin structure;
depositing a select gate material on the second side surface of the fin structure;
planarizing the floating gate material and the select gate material to be substantially coplanar with an upper surface of
the fin structure; and

depositing a control gate material proximate a side surface of the floating gate material,
wherein an upper surface of the control gate material is substantially coplanar with the upper surface of the fin structure.

US Pat. No. 9,362,374

SIMPLE AND COST-FREE MTP STRUCTURE

GLOBALFOUNDRIES Singapore...

1. A non-volatile (NV) multi-time programmable (MTP) memory cell comprising:
a substrate;
first and second wells disposed in the substrate;
a first transistor having a select gate and a second transistor having a floating gate adjacent one another and disposed over
the second well, wherein the first and second transistors are coupled in series and share a common diffusion region; and

a control gate disposed over the first well, wherein the control gate is coupled to the floating gate and the control and
floating gates comprise the same gate layer extending across the first and the second wells; and

at least one well contact region disposed in the first well and adjacent to the control gate, wherein the well contact region
couples the first well to a control gate line (CGL) and is biased at a bias potential during various operations of the memory
cell.

US Pat. No. 9,257,277

METHODS FOR EXTREME ULTRAVIOLET MASK DEFECT MITIGATION BY MULTI-PATTERNING

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating an integrated circuit comprising:
identifying a position of a defect in a first EUV photolithographic mask, the first EUV photolithographic mask comprising
a desired pattern;

transferring the desired pattern to a photoresist material disposed on a semiconductor substrate, wherein transferring the
desired pattern further transfers an error pattern feature to the photoresist material as a result of the defect in the first
EUV photolithographic mask; and

using a second photolithographic mask, transferring a trim pattern to the photoresist material, wherein the trim pattern removes
the error pattern feature from the photoresist material, wherein transferring the trim pattern further removes a portion of
the desired pattern from the photoresist material, and wherein the method further comprises, using a third photolithographic
mask, transferring a replacement pattern to the photoresist material, wherein the replacement pattern replaces the portion
of the desired pattern removed by the trim pattern.

US Pat. No. 9,698,200

MAGNETISM-CONTROLLABLE DUMMY STRUCTURES IN MEMORY DEVICE

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a device comprising:
providing a substrate defined with first and second functional regions and first and second non-functional regions, wherein
the first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional
region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second
functional region;

forming a magnetic memory element in the first functional region and a logic element in the second functional region; and
forming a plurality of magnetism controllable dummy structures in the proximate memory region and external logic circuit region,
wherein the magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents
electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.

US Pat. No. 9,287,497

INTEGRATED CIRCUITS WITH HALL EFFECT SENSORS AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS

GLOBALFOUNDRIES SINGAPORE...

1. A method of producing an integrated circuit comprising:
forming a buried plate layer within a substrate and overlying a substrate base, wherein the buried plate layer is doped with
an “N” type dopant;

forming a cover insulating layer overlying the buried plate layer; and
forming a plurality of contact points in the substrate, wherein the plurality of contact points are adjacent to the cover
insulating layer, and wherein the plurality of contacts are on four different sides of the cover insulating layer.

US Pat. No. 9,252,270

FLOATING BODY CELL

GLOBALFOUNDRIES Singapore...

1. A method comprising:
forming a silicon on insulator (SOI) layer on a substrate;
forming a band-engineered layer surrounding and/or on the SOI layer, the band-engineered layer formed as a multi-layer stack
with a decreasing concentration of germanium (Ge) from a bottom surface of the multi-layer stack to a top surface of the multi-layer
stack;

forming a silicon layer on the band-engineered layer;
forming a dummy gate on the silicon layer;
forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered
layer; and

forming a gate on the SOI layer, between the source and drain regions, the gate formed by:
removing the dummy gate, the silicon layer and the band-engineered layer below the dummy gate, forming a cavity;
forming a gate oxide layer on sidewalls and a bottom surface of the cavity; and
filling the cavity with a gate material.

US Pat. No. 9,343,472

MEMORY CELL WITH DECOUPLED CHANNELS

GLOBALFOUNDRIES SINGAPORE...

1. A method of fabricating a device comprising:
providing a substrate prepared with a memory cell region; and
forming a memory cell on the memory cell region, wherein forming the memory cell comprises
forming an access transistor and a storage transistor, wherein the access transistor includes first and second access source/drain
(S/D) regions and the storage transistor includes first and second storage S/D regions, wherein the access and storage transistors
are coupled in series and the second S/D regions being a common S/D region,

forming an erase gate over the common S/D region, and
forming a program gate over the first storage S/D region, wherein such an arrangement of the memory cell decouples a program
channel and an erase channel.

US Pat. No. 9,343,662

MAGNETIC MEMORY DEVICE AND METHOD OF FORMING THEREOF

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a device comprising:
providing a substrate;
performing front end of line processing to form circuit components on the substrate; and
performing back end of line processing to form an uppermost inter level dielectric (ILD) layer of the device, the uppermost
ILD layer includes a metal level over a via level, wherein the metal level comprises first and second metal lines having top
surfaces which are coplanar with a top surface of the uppermost ILD layer;

forming a pad level over the uppermost ILD layer, wherein forming the pad level comprises
forming a lower passivation layer and an intermediate dielectric layer over the lower passivation layer, and
patterning the lower passivation and intermediate dielectric layers to form a pad via opening which exposes a portion of the
top surface of the second metal line in the uppermost ILD layer;

providing a storage unit of a memory cell in the pad level, wherein a bottom surface of the storage unit completely contacts
the top surface of the first metal line of the uppermost ILD layer without covering the entire first metal line, and wherein

top surface of the storage unit is coplanar with top surface of the intermediate dielectric layer; and
forming a cell interconnect and a pad interconnect in the pad level, wherein forming the cell interconnect and the pad interconnect
comprises

forming a conductive layer over the intermediate dielectric layer, wherein the conductive layer fills the pad via opening,
and

patterning the conductive layer to simultaneously form the cell interconnect and pad interconnect, wherein the cell interconnect
is a cell contact pad which is formed on top of and in direct contact with the top surfaces of the storage unit and the intermediate
dielectric layer while the pad interconnect includes a pad via contact and a contact pad, wherein the pad via contact extends
beyond a bottom surface of the intermediate dielectric layer to be in direct contact with the exposed portion of the second
metal line and the contact pad is disposed on the intermediate dielectric layer.

US Pat. No. 9,520,371

PLANAR PASSIVATION FOR PADS

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:
a substrate having circuit component and a dielectric layer over the substrate, wherein the dielectric layer comprises a plurality
of inter level dielectric (ILD) layers and the uppermost dielectric layer comprises at least one interconnect;

a pad dielectric layer which comprises a flowable dielectric material disposed over the uppermost ILD layer;
a pad interconnect which is a wire bond pad configured for receiving a wire bond disposed in the pad dielectric layer and
a top surface of the pad interconnect is exposed such that the wire bond is to be attached and in direct contact thereto,
wherein the pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer, wherein a top surface
of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect; and

a passivation layer disposed over and in direct contact with the pad dielectric layer, wherein the passivation layer comprises
a non-planar top surface having a first height closer to the pad interconnect and a second height away from the pad interconnect,
wherein the first height is slightly higher than the second height, and the passivation layer is used for preventing a top
surface of the pad interconnect from oxidation/corrosion and contamination during wire bonding and packaging process.

US Pat. No. 9,511,474

CMP HEAD STRUCTURE WITH RETAINING RING

GLOBALFOUNDRIES SINGAPORE...

1. A CMP apparatus comprising:
a polishing pad on a platen table;
a head assembly, wherein the head assembly includes a retaining ring for holding a wafer in place on the polishing pad;
a ring monitoring equipment configured for sensing and determining a step height between the retaining ring and a membrane
of the retaining ring;

a controller configured for calculating how much the retaining ring should be moved to ensure the step height between the
retaining ring and the membrane remains at a fixed value; and

a mechanism configured to move the retaining ring to ensure the step height remains at the fixed value as the retaining ring
wears out.

US Pat. No. 9,082,846

INTEGRATED CIRCUITS WITH LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR STRUCTURES

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit comprising:
a semiconductor substrate;
a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the
semiconductor substrate, wherein the STI regions electrically isolate devices fabricated in the semiconductor substrate; and

a transistor structure comprising:
a gate dielectric positioned over a portion of a first one of the plurality of STI regions;
a drain region adjacent to the first one of the plurality of STI regions and spaced apart from the gate dielectric;
a first gate electrode that extends over a first portion of the gate dielectric, the first gate electrode having sidewall
spacer structures formed at opposite lateral ends thereof;

a second gate electrode that extends over a second portion of the gate dielectric, the second gate electrode having sidewall
spacer structures formed at opposite lateral ends thereof, and wherein the first gate electrode is separated from the second
gate electrode by the spacer structures of the first gate electrode and the spacer structures of the second gate electrode,
and wherein the spacer structures of the second gate electrode are positioned adjacent to the spacer structures of the first
gate electrode, and wherein an entirety of an upper surface of the first gate electrode is co-planar with an entirety of an
upper surface of the second gate electrode, and wherein the second gate electrode is positioned over the first one of the
plurality of STI regions; and

a source region positioned adjacent to the first portion of the gate dielectric.

US Pat. No. 9,614,027

HIGH VOLTAGE TRANSISTOR WITH REDUCED ISOLATION BREAKDOWN

GLOBALFOUNDRIES SINGAPORE...

1. A high voltage device comprising:
a substrate having a device region, the device region having a planar top surface with a length and a width direction, wherein
first and second opposing width sides of the device region are along a channel width direction and first and second opposing
length sides are along a channel length direction;

an isolation region surrounding the opposing width and length sides of the device region, wherein isolation edges abut the
opposing width and length sides of the device region;

a transistor disposed in the device region, wherein the transistor includes a gate with first and second gate sidewalls, the
gate includes a gate electrode over a gate dielectric, the gate is disposed on the top surface of the device region between
first and second source/drain (S/D) regions, the first S/D region is adjacent to the first gate sidewall and the second S/D
region is adjacent to the second gate sidewall, wherein top surfaces of the first and second S/D regions are co-planar with
the top surface of the device region, the first S/D region is subject to a high voltage; and

a silicide block disposed over a portion of the gate and over at least a portion of the first S/D region, the silicide block
leaves a remaining portion of the gate uncovered while covering at least portions of isolation edges abutting the length sides
of the device region adjacent and proximate to the first gate sidewall, the silicide block prevents formation of silicide
over the silicide block, which includes at least portions of isolation edges abutting the length sides of the device region
adjacent and proximate to the first gate sidewall.

US Pat. No. 9,064,894

STRESS ENHANCED HIGH VOLTAGE DEVICE

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a device comprising:
providing a substrate having a device region surrounded by a device isolation region, wherein the device region comprises
a source region, a gate region and a drain region defined thereon;

forming a gate in the gate region, a source in the source region and a drain in the drain region to form a transistor;
forming an internal isolation region which comprises isolation material, wherein the internal isolation region displaces the
drain from a drain side of the gate and underlaps a portion of the gate on the drain side of the gate;

partially recessing the isolation material of the internal isolation region to form a first secondary trench in the internal
isolation region, wherein a width of the first secondary trench is smaller than a width of the internal isolation region;

forming an etch stop (ES) stressor layer over the substrate, wherein the ES stressor layer lines the transistor and first
secondary trench without filling the first secondary trench to leave a trench gap; and

forming a dielectric layer on the substrate, the dielectric layer covering the transistor and filling the trench gap over
the ES stressor layer.

US Pat. No. 9,847,272

THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES PROVIDING THERMOELECTRIC COOLING AND METHODS FOR COOLING SUCH INTEGRATED CIRCUIT STRUCTURES

GLOBALFOUNDRIES SINGAPORE...

1. A three-dimensional integrated circuit structure comprising:
a plurality of integrated circuit chips stacked one on top of another to form a three-dimensional chip stack, wherein each
integrated circuit chip comprises an active area;

a thermoelectric cooling daisy chain comprising a plurality of vias electrically connected in series with one another formed
surrounding, but not passing through, the active area of each integrated circuit chip of the three-dimensional chip stack,
wherein each individual chain of the daisy chain penetrates through each integrated circuit chip of the three-dimensional
chip stack;

a thermoelectric cooling plate electrically connected in series with the thermoelectric cooling daisy chain; and
a heat sink physically connected with the thermoelectric cooling plate.

US Pat. No. 9,537,092

INTEGRATED CIRCUITS WITH MEMORY CELLS AND METHODS OF MANUFACTURING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit comprising:
a lower electrode overlying a substrate;
an insulating layer overlying the lower electrode;
an upper electrode overlying the insulating layer, such that the lower electrode, the insulating layer, and the upper electrode
comprise a stack having a side surface;

a phase change spacer adjacent to the side surface, wherein the phase change spacer is electrically connected to the lower
electrode and the phase change spacer is directly connected to the upper electrode; and

a heater spacer adjacent to the side surface of the stack, wherein the phase change spacer and the heater spacer are electrically
connected, and wherein the heat spacer is directly connected to the lower electrode.

US Pat. No. 9,082,964

NONVOLATIVE MEMORY WITH FILAMENT

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a memory cell comprising:
providing a substrate;
forming a first electrode;
forming a second electrode; and
forming a resistive stack in between the first and second electrodes, wherein the resistive stack comprises
a storage layer having first and second major surfaces,
a storage dielectric layer having first and second major surfaces which are parallel to the first and second major surfaces
of the storage layer, wherein when subjected to a forming process, one or more filaments are formed in the storage dielectric
layer, and

a dielectric layer which is disposed in between and contacts the second major surface of the storage layer and the first major
surface of the storage dielectric layer, wherein the storage layer, storage dielectric layer and dielectric layer of the resistive
stack comprise about the same surface dimensions.

US Pat. No. 9,130,029

RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS

GLOBALFOUNDRIES Singapore...

1. A device comprising:
a substrate;
an interlayer dielectric (ILD) above the substrate;
a metal gate above the substrate, the metal gate including a first region closer to the substrate, and a second region above
the first region, the second region having a first portion closer to the first region and a second portion above the first
region; and

a gate cap between the ILD and the metal gate and above the metal gate at the second region, wherein:
a first width of the first region is less than the first portion of the second region, and
a second width of the second portion is less than a third width of the first portion.

US Pat. No. 9,064,848

ARC RESIDUE-FREE ETCHING

GLOBALFOUNDRIES Singapore...

10. A device comprising:
a silicon substrate;
a conductive material over the silicon substrate;
a pattern formed in the conductive material using a patterning stack including a hard mask layer having a thickness of 30
Å to 400 Å formed over the conductive material, a sacrificial layer formed over the hard mask layer, an optical dispersive
layer formed over the sacrificial layer, a silicon anti-reflective coating layer formed over the optical dispersive layer,
and a photoresist layer formed over the silicon anti-reflective coating layer in the pattern,

wherein the pattern is formed by etching to transfer the pattern to the hard mask layer, stripping at least the optical dispersive
layer and the sacrificial layer, and etching the conductive material through the patterned hard mask layer;

wherein no or substantially no residue from the silicon anti-reflective coating layer remains after the stripping, wherein
the sacrificial layer comprises an amorphous carbon material and extends over a side portion of the hard mask layer.

US Pat. No. 10,032,766

VDMOS TRANSISTORS, BCD DEVICES INCLUDING VDMOS TRANSISTORS, AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SUCH DEVICES

GLOBALFOUNDRIES SINGAPORE...

1. A bipolar-CMOS-DMOS (BCD) device including a vertical diffused metal oxide semiconductor (VDMOS) transistor, the BCD device comprising:a buried layer over a substrate;
an epitaxial layer over the buried layer and having an upper surface;
deep trench isolation regions extending from the upper surface of the epitaxial layer, through the buried layer, and into the substrate, wherein the deep trench isolation regions isolate a VDMOS region from a device region of the epitaxial layer;
a source region adjacent the upper surface of the epitaxial layer in the VDMOS region;
a vertical gate structure extending into the epitaxial layer in the VDMOS region;
a body region of the epitaxial layer located adjacent the vertical gate structure in the VDMOS region, wherein the body region forms a channel; and
a VDMOS conductive structure extending through the epitaxial layer and into the buried layer in the VDMOS region, wherein the buried layer is a drain for the VDMOS transistor and the VDMOS conductive structure is a drain contact to the buried layer.

US Pat. No. 9,570,138

MAGNETIC MEMORY CELLS WITH FAST READ/WRITE SPEED

GLOBALFOUNDRIES SINGAPORE...

1. A memory cell comprising:
a storage unit, the storage unit comprises
a magnetic storage element with first and second storage terminals;
a bitline coupled to the second storage terminal;
a selector unit, the selector unit comprises
a first selector having a first select transistor having a first drain terminal, a first source terminal and a first control
terminal, wherein

the first drain terminal is coupled to the first storage terminal,
the first source terminal is coupled to a source line,
the first control terminal is coupled to a first control wordline,
a second selector comprises a second select transistor which is a second tunneling select transistor having a second drain
terminal, a second source terminal and a second control terminal, wherein

the second drain terminal is coupled to the first storage terminal,
the second source terminal is coupled to the source line,
the second control terminal is coupled to a second control wordline,
the second tunneling select transistor is configured to have a second unidirectional current flow between the second source
and second drain terminals, wherein the second selector serves at least as a read selector for read operations of the memory
cell and a read current is in the direction of the second unidirectional current flow between the second source and second
drain terminals.

US Pat. No. 9,490,165

RELIABLE INTERCONNECT INTEGRATION SCHEME

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a device comprising:
providing a substrate prepared with a dielectric layer; and
processing the dielectric layer to serve as an intermetal dielectric (IMD) layer, wherein the IMD layer comprises a hybrid
IMD layer comprising a plurality of dielectric materials with different k values, wherein processing the dielectric layer
comprises

providing a second dielectric material having a second k value,
forming interconnects in the second dielectric material,
depositing a passivation layer covering the second dielectric material and surface of the interconnects after forming the
interconnects,

patterning the passivation layer to cover only top surfaces of the interconnects,
providing a patterned soft mask layer covering the patterned passivation layer and in direct contact with a portion of the
second dielectric material adjacent to the passivation layer and interconnects,

removing exposed portions of the second dielectric material not covered by the patterned soft mask layer to form openings,
providing a first dielectric material to fill the openings and between the interconnects, wherein the first dielectric material
comprises a first k value which is lower than the second k value, and wherein the second dielectric material surrounds and
contacts sides and bottom surface of the first dielectric material, and

processing the first and second dielectric materials such that top surfaces of the first dielectric material, the second dielectric
material and the interconnects are coplanar with each other.

US Pat. No. 9,343,587

FIELD EFFECT TRANSISTOR WITH SELF-ADJUSTING THRESHOLD VOLTAGE

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:
forming a gate oxide layer above a channel region in a substrate;
forming a self-adjusting threshold voltage layer above the gate oxide layer;
forming a dummy gate on the self-adjusting threshold voltage layer;
removing the dummy gate, forming a cavity;
depositing a gate material on side surfaces of the cavity, leaving exposed a middle portion of the self-adjusting threshold
voltage layer; and

removing the middle portion of the self-adjusting threshold voltage layer.

US Pat. No. 9,171,858

MULTI-LEVEL MEMORY CELLS AND METHODS FOR FORMING MULTI-LEVEL MEMORY CELLS

GLOBALFOUNDRIES SINGAPORE...

1. A method of producing an integrated circuit with a multi-level memory cell comprising:
forming a gate insulator overlying a substrate;
forming a select gate overlying the gate insulator such that one multi-level memory cell includes one select gate;
forming a thin film storage layer overlying the select gate and the substrate, wherein the thin film storage layer comprises
a plurality of nanocrystals;

forming a left control gate and a right control gate on opposite sides of the select gate and overlying the thin film storage
layer such that the thin film storage layer is between the left control gate and the substrate, and the thin film storage
layer is between the right control gate and the substrate;

forming a select gate hard mask overlying the select gate prior to forming the left control gate and the right control gate;
removing the select gate hard mask after forming the left control gate and the right control gate such that the left control
gate and the right control gate extend above the select gate; and

forming a left implant and a right implant in the substrate such that the select gate, the left control gate, and the right
control gate are positioned between the left implant and the right implant.

US Pat. No. 9,111,992

SEMICONDUCTOR DEVICE INCLUDING AN N-WELL STRUCTURE

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating a device comprising:
providing a substrate without doped regions which serve as buried doped regions, wherein the substrate comprises a planar
top surface;

forming a doped epitaxial layer over and contacts the planar top surface of the substrate, wherein the doped epitaxial layer
includes first polarity type dopants and a planar top epitaxial surface, the doped epitaxial layer includes a device region
which corresponds to a device isolation well for a device in the device region, and a thickness of the doped epitaxial layer
defines a depth of the device isolation well;

selectively counter-doping a portion of the doped epitaxial layer to form a counter-doped region adjacent to the device region
formed by the doped epitaxial layer, wherein the counter doped region extends from the planar top epitaxial surface to at
least the planar top surface of the substrate;

forming a trench isolation region, the trench isolation region isolates the device region; and
forming the device over and contacts the planar top epitaxial surface in the device region.

US Pat. No. 9,242,341

CMP HEAD STRUCTURE

GLOBALFOUNDRIES Singapore...

1. A method for prolonging the use of a retaining ring comprising:
providing a head assembly for use in polishing a wafer, wherein the head assembly includes a retaining ring for holding the
wafer in place on a polishing pad;

determining a step height between the retaining ring and a membrane of the retaining ring;
calculating how much the retaining ring should be moved to ensure the step height between the retaining ring and the membrane
remains at a fixed value; and

moving the retaining ring to ensure the step height remains at the fixed value as the retaining ring wears out.

US Pat. No. 9,054,191

HIGH ION AND LOW SUB-THRESHOLD SWING TUNNELING TRANSISTOR

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:
a substrate; and
a fin-type transistor disposed on the substrate, wherein the transistor comprises
a fin structure protruding from the substrate to serve as a source of the transistor, the fin structure doped with dopants
of a first polarity,

a gate layer disposed over and around a first end of the fin structure to serve as a gate of the transistor, and
a drain layer disposed over the fin structure and adjacent to the gate layer to serve as a drain of the transistor, the drain
layer doped with dopants of a second polarity opposite the first polarity.

US Pat. No. 10,062,698

P-CHANNEL MULTI-TIME PROGRAMMABLE (MTP) MEMORY CELLS

GLOBALFOUNDRIES SINGAPORE...

1. A multi-time programmable (MTP) memory cell comprising:a semiconductor substrate;
an isolation region formed in the semiconductor substrate and extending to a first depth;
an n-well formed in the semiconductor substrate and extending to a second depth greater than the first depth;
a p-channel transistor disposed over the n-well and including a transistor gate;
a p-well formed in the semiconductor substrate and extending to a third depth greater than the first depth, wherein the p-well contacts the isolation region at the first depth and is isolated from the n-well by the isolation region; and
a p-channel capacitor disposed over the p-well and including a capacitor gate, wherein the capacitor gate is coupled to the transistor gate.

US Pat. No. 10,032,905

INTEGRATED CIRCUITS WITH HIGH VOLTAGE TRANSISTORS AND METHODS FOR PRODUCING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit comprising:a substrate;
a gate overlying the substrate;
a drain defined within the substrate, wherein the drain and the gate are separated by a drain distance;
a source defined within the substrate adjacent to the gate, wherein the source is divided into two or more source sections;
a source gap is defined between adjacent source sections, wherein the source gap and the source sections primarily include different types of conductivity determining impurities.

US Pat. No. 9,472,512

INTEGRATED CIRCUITS WITH CONTACTS THROUGH A BURIED OXIDE LAYER AND METHODS OF PRODUCING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit comprising:
a substrate comprising a handle layer, a buried oxide (BOX) layer, and a semiconductor layer, wherein the buried oxide layer
is positioned between the handle layer and the semiconductor layer;

an electronic component overlying the buried oxide layer on a semiconductor layer side of the buried oxide layer;
a gate line electrically connected to the electronic component;
a body line electrically connected to the electronic component;
a first through BOX contact electrically connecting the gate line with the handle layer; and
a second through BOX contact electrically connecting the body line with the handle layer.

US Pat. No. 9,136,179

HIGH GAIN DEVICE

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a device comprising:
providing a substrate having a core device region and a high gain (HG) device region for a HG transistor;
forming a core gate on the substrate in the core device region and a HG gate on the substrate in the HG device region, wherein
the HG gate includes sidewall spacers on its sidewalls, wherein

the core gate and HG gate include gate dielectric and gate electrode layers, and
the gate dielectric layers of the core gate and HG gate comprise the same thickness;
performing a lightly doped drain (LDD) implant, the LDD implant implants first polarity type dopants to form first polarity
type LDD regions adjacent to the core gate, the first polarity type comprises n-type; and

performing a source/drain (S/D) implant, the S/D implant implants first polarity type dopants to form heavily doped first
polarity type core S/D regions adjacent to the core gate and heavily doped first polarity type HG S/D regions adjacent to
the HG gate, the core device region includes core S/D regions with LDD regions while the HG device region includes HG S/D
regions without LDD regions.

US Pat. No. 9,054,135

METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH A HIGH-VOLTAGE MOSFET

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating an integrated circuit comprising:
forming a first silicon material layer over a semiconductor substrate, the semiconductor substrate including a high-voltage
MOSFET region, a logic device region, and a memory array region, the memory array region having formed on the semiconductor
substrate a memory gate stack;

forming a capping layer over the first silicon material layer and over the memory gate stack;
removing the capping layer from over the memory array region and the high-voltage MOSFET region but not from over the logic
device region of the integrated circuit;

forming a second silicon material layer over the capping layer and over the first silicon material layer;
removing the second silicon material layer in an amount such that a thickness of the second silicon material layer over the
first silicon material layer in the high-voltage MOSFET region is substantially equal to a thickness of the capping layer
over the first silicon material layer in the logic device region;

removing the capping layer from over the first silicon material layer in the logic device region;
removing the first and second silicon material layers from the high-voltage MOSFET region except in an area overlying a channel
region of the high-voltage MOSFET region;

masking the memory array region and the logic device region; and
exposing the semiconductor substrate to a dopant ion implantation process.

US Pat. No. 9,806,128

INTERPOSERS FOR INTEGRATED CIRCUITS WITH MULTIPLE-TIME PROGRAMMING AND METHODS FOR MANUFACTURING THE SAME

GLOBALFOUNDRIES SINGAPORE...

20. An interposer for an integrated circuit, said integrated circuit comprising a plurality of transistors, said interposer
defining a first side and a second side, comprising:
a substrate;
a plurality of vias disposed in said substrate;
a plurality of first electrical contacts disposed on said first side of said interposer, wherein at least one of said first
electrical contacts is electrically connected to at least one of said transistors, and wherein said plurality of transistors
are disposed adjacent said plurality of first electrical contacts;

a dielectric layer disposed between said plurality of transistors and said substrate:
a plurality of second electrical contacts comprising solder balls disposed on said second side of said interposer, wherein
each of said second electrical contacts are electrically connected to at least one of said plurality of vias; and

at least one multiple-time programmable (“MTP”) element disposed in said dielectric layer between said plurality of transistors
and said substrate, and electrically connected to at least one of said first electrical contacts and at least one of said
vias;

said at least one MTP element comprising germanium-antimony-tellurium (“GST”).

US Pat. No. 9,685,364

SILICON-ON-INSULATOR INTEGRATED CIRCUIT DEVICES WITH BODY CONTACT STRUCTURES AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating a silicon-on-insulator integrated circuit comprising:
providing a silicon-on-insulator substrate that comprises a semiconductor layer disposed over an insulating layer, which in
turn is disposed over a substrate;

forming a plurality of first shallow isolation trenches completely through the semiconductor layer to expose a portion of
the insulating layer therebelow;

forming a plurality of second shallow isolation trenches only part-way, but not fully, through the semiconductor layer;
subsequent to forming the plurality of second shallow isolation trenches, implanting conductivity-determining ions into the
semiconductor layer beneath the plurality of second shallow isolation trenches;

subsequent to implanting the conductivity-determining ions, filling the plurality of first and second shallow isolation trenches
with an insulating material to form a plurality of first and second shallow trench isolation structures;

forming a gate structure over the semiconductor layer that includes a first portion disposed over and parallel to at least
two of the plurality of second shallow trench isolation structures and a second portion disposed in between the at least two
of the plurality of second shallow trench isolation structures, wherein no first shallow trench isolation structures are formed
in between the at least two of the plurality of second shallow trench isolation structures; and

forming contact plugs to the gate structure and to a body contact region.

US Pat. No. 9,406,667

LATCH-UP IMMUNITY NLDMOS

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:
a substrate;
a dual voltage n-well (DVNW) region in the substrate;
a high voltage p-well (HVPW) region in the DVNW region;
bulk and source regions in the HVPW region;
a drain region in the DVNW region, separate from the HVPW region;
a polysilicon gate over a portion of the HVPW region and the DVNW region;
an n-well (NW) region in the DVNW region in the drain region, the NW region comprising a first N+ region;
second and third N+ regions in the HVPW region; and
a first P+ region separating the second and third N+ regions.

US Pat. No. 9,401,473

COMPACT RRAM STRUCTURE WITH CONTACT-LESS UNIT CELL

GLOBALFOUNDRIES Singapore...

1. A RRAM device, comprising:
a substrate prepared with a diffusion region having first polarity type dopants in the substrate;
a conductive bit line electrode disposed over the substrate;
first and second semiconductor layers disposed over the conductive bit line electrode, wherein the first semiconductor layer
is positioned between the conductive bit line electrode and the second semiconductor layer;

a variable resistance layer positioned between the conductive bit line electrode and the diffusion region, wherein the variable
resistance layer directly contacts a top surface of the diffusion region; and

a single isolation layer disposed on and contacts the substrate, wherein the single isolation layer contacts exposed portions
of the diffusion region and sidewalls of the first and second semiconductor layers, conductive bit line electrode and variable
resistance layer.

US Pat. No. 9,196,830

WRAP AROUND PHASE CHANGE MEMORY

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a device comprising:
providing a bottom electrode;
forming a storage element over the bottom electrode, wherein the storage element comprises
a heat generating element directly disposed on the bottom electrode,
a phase change stack which comprises at least a phase change layer and a dielectric liner, wherein the phase change layer
wraps around an upper portion of the heat generating element and the dielectric liner wraps around the same upper portion
of the heat generating element, wherein the dielectric liner is sandwiched between the phase change layer and the heat generating
element, and wherein the dielectric liner covers the entire uppermost surface of the heat generating element; and

forming a top electrode over the storage element.

US Pat. No. 9,154,122

LATCH UP DETECTION

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:
a first circuit directly coupled to both first and second power rails of the device, the first circuit comprises complementary
metal oxide semiconductor (CMOS) transistors, the first circuit is subject to a latch up event in the presence of a latch
up condition, the latch up event includes a low resistance path created between the first and second power rails;

a latch up sensing (LUS) circuit, wherein the LUS circuit senses a latch up condition in the first circuit and terminates
the latch up event when the latch up condition is sensed, the LUS circuit and the first circuit are distinct circuits, the
LUS circuit is coupled to the first circuit, wherein the LUS circuit is configured to receive a LUS input signal at a LUS
input from the first circuit and generate a LUS output signal at a LUS output to the first circuit, the LUS input signal and
LUS output signal comprise voltage signals, wherein

the LUS circuit includes first and second transistors coupled in between the first and second power rails,
the first transistor is a p-type MOS transistor and includes a first p-transistor terminal, a second p-transistor terminal,
a p-transistor body, and a p-transistor gate terminal, wherein the first p-transistor terminal is coupled to the first power
rail, the second p-transistor terminal is coupled to the LUS output of the LUS circuit, and the p-transistor body is coupled
to the first p-transistor terminal,

the second transistor is a n-type MOS transistor and includes a first n-transistor terminal, a second n-transistor terminal,
a n-transistor body, and a n-transistor gate terminal, wherein the first n-transistor terminal is coupled to the second power
rail, the second n-transistor terminal is coupled to the p-transistor gate terminal, the n-transistor gate terminal is coupled
to the LUS input of the LUS circuit, and the n-transistor body is coupled to the first n-transistor terminal, and

when the input signal is an active latch up signal which indicates the presence of the latch up condition, the LUS circuit
generates an active LUS output signal which creates a break in the low resistance path to terminate the latch up event.

US Pat. No. 9,048,371

SEMICONDUCTOR DEVICES INCLUDING AVALANCHE PHOTODETECTOR DIODES INTEGRATED ON WAVEGUIDES AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating a semiconductor device, the method comprising:
etching a trench into a waveguide layer in a detector region of a semiconductor substrate, wherein etching the trench into
the waveguide layer comprises removing material from the waveguide layer to expose a sidewall and a lower section of the waveguide
layer to form the trench; and

forming an avalanche photodetector diode about the trench comprising:
forming a first multiplication region in the waveguide layer laterally adjacent to the trench, wherein forming the avalanche
photodetector diode comprises P? doping the sidewall and the lower section to form a P? charge layer, and wherein forming
the first multiplication region comprises forming the first multiplication region laterally adjacent to the P? charge layer;
and

forming an absorption region at least partially disposed in the trench, wherein forming the first multiplication region comprises
forming an n-well in the waveguide layer laterally spaced apart from the P? charge layer to form the first multiplication
region disposed between the n-well and the P? charge layer.

US Pat. No. 9,718,672

ELECTRONIC DEVICES INCLUDING SUBSTANTIALLY HERMETICALLY SEALED CAVITIES AND GETTER FILMS WITH KELVIN MEASUREMENT ARRANGEMENT FOR EVALUATING THE GETTER FILMS AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. An electronic device comprising:
an electronic device body structure having a substantially hermetically sealed cavity formed therein;
a getter film in fluid communication with the substantially hermetically sealed cavity;
conductive features accessible from outside the substantially hermetically sealed cavity and operatively coupled to the getter
film for electrical communication with the getter film; and

a Kelvin measurement arrangement in electrical communication with the electronic device for evaluating the getter film.

US Pat. No. 9,613,897

INTEGRATED CIRCUITS INCLUDING MAGNETIC CORE INDUCTORS AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit comprising a magnetic core inductor, the magnetic core inductor comprising:
a bottom magnetic plate comprising a center portion and first, second, third, and fourth extension portions extending from
the center portion;

an interlayer dielectric layer disposed over the bottom magnetic plate;
within the interlayer dielectric layer, first, second, third, and fourth via trenches extending above a respective one of
the first, second, third, and fourth extension portions, and a fifth via trench extending above the center portion, each of
the first through fifth via trenches comprising a magnetic material along sidewalls thereof and being filled with a high dielectric
breakdown material;

a stacked-ring inductor coil comprising a plurality of inductor rings surrounding the fifth via trench; and
a top magnetic plate comprising a center portion and first, second, third, and fourth extension portions extending from the
center portion that lie over respective ones of the center, first, second, third, and fourth extension portions of the bottom
magnetic plate.

US Pat. No. 9,437,550

TSV WITHOUT ZERO ALIGNMENT MARKS

GLOBALFOUNDRIES Singapore...

1. A method of forming a device comprising:
providing a substrate;
forming a dielectric layer disposed on the substrate, the dielectric layer serves as an intermetal dielectric (IMD) layer
which comprises an upper and lower portion, wherein the upper portion of the dielectric layer corresponds to a first metal
level and the lower portion of the dielectric layer corresponds to a premetal dielectric (PMD) level;

patterning the upper portion of the dielectric layer to form at least first and second trench openings and alignment mark
openings, wherein one of the first and second trench openings serve as a through via (TV) trench while another trench opening
serves as an interconnect trench, and wherein the PMD level separates the first and second trench openings and alignment mark
openings in the first metal level from the substrate;

forming a TV opening aligned to the TV trench, wherein the TV opening extends through the PMD level and partially into the
substrate; and

forming a conductive layer over the substrate to fill the trenches and the openings.

US Pat. No. 9,093,551

METHOD AND APPARATUS FOR EMBEDDED NVM UTILIZING AN RMG PROCESS

GLOBALFOUNDRIES Singapore...

1. A method comprising:
forming a first dual polysilicon gate-stack structure and a second dual polysilicon gate-stack structure on an upper surface
of a substrate;

forming spacers on opposite sidewalls of the first dual polysilicon gate-stack structure and the second dual polysilicon gate-stack
structure;

forming an inter-layer dielectric (ILD) adjacent to an exposed sidewall of the spacers;
removing the first dual polysilicon gate-stack structure, forming a first cavity between the spacers; and
forming a high-k/metal gate (HKMG) in the first cavity, wherein the HKMG comprises an access gate.

US Pat. No. 9,076,735

METHODS FOR FABRICATING INTEGRATED CIRCUITS USING CHEMICAL MECHANICAL POLISHING

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating an integrated circuit comprising:
forming a silicon material layer over a semiconductor substrate, the semiconductor substrate including a logic device region
and a memory array region, the memory array region having formed on the semiconductor substrate a memory device;

forming a capping layer over the silicon material layer and over the memory device;
removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing
process while leaving at least a first portion of the capping layer in place over the logic device region; and

removing the first silicon material layer from over the memory device in the memory array region using a second chemical mechanical
polishing process while leaving at least a second portion of the capping layer in place over the logic device region, the
at least a second portion having a thickness that is less than the at least a first portion.

US Pat. No. 9,865,649

INTEGRATED TWO-TERMINAL DEVICE AND LOGIC DEVICE WITH COMPACT INTERCONNECTS HAVING SHALLOW VIA FOR EMBEDDED APPLICATION

GLOBALFOUNDRIES Singapore...

1. A method of forming a device comprising:
providing a substrate defined with at least first and second regions;
providing a plurality of interlevel dielectric (ILD) levels having tight pitch over the first and second regions of the substrate,
comprising

wherein the plurality of ILD levels comprises
an ILD level of which a two-terminal element disposed thereon corresponds to a first ILD level and its metal level corresponds
to Mx,

an immediate ILD level overlying the metal level Mx corresponds to a second ILD level includes a via level Vx and a metal
level Mx+1, and

the next overlying ILD level corresponds to a third ILD level includes a via level Vx+1 and a metal level Mx+2,
forming a first dielectric layer and forming a second upper dielectric layer over the first and second regions covering the
first dielectric layer, and

patterning the second dielectric layer to form a trench opening in the first region;
forming a two-terminal device element in between the metal level Mx and the via level Vx+1 in the first region, wherein the
two-terminal device element comprises a device layer coupled in between the first and second terminals, wherein the first
terminal is in direct contact with a metal line in the metal level Mx of the first region and the second terminal is formed
on a top surface of the device layer, and wherein the device layer is a MTJ stack of a MRAM cell, and wherein a total height
of the MTJ stack with top and bottom electrodes is greater than a height of a via contact in the via level Vx and is shallower
or same as a total height of a metal line in the metal level Mx+1 and the via contact in the via level Vx;

forming a dual damascene interconnect over the second region in the second ILD level, wherein the dual damascene interconnect
comprises a metal line in the metal level Mx+1 and a via contact in the via level Vx in the second region; and

forming dual damascene interconnects in the third ILD level over the first and second regions, wherein a dual damascene interconnect
includes a metal line in the metal level Mx+2 and a via contact in the via level Vx+1, and wherein the dual damascene interconnect
in the first region is coupled to the two-terminal device element and the dual damascene interconnect in the second region
is formed over and is coupled to the dual damascene interconnect in the second ILD level.

US Pat. No. 9,589,616

ENERGY EFFICIENT THREE-TERMINAL VOLTAGE CONTROLLED MEMORY CELL

GLOBALFOUNDRIES SINGAPORE...

1. A memory cell comprising:
at least three terminals including first, second, and third terminals;
a first magnetic tunnel junction (MTJ) structure coupled between the first terminal and the third terminal, wherein a portion
of the first MTJ structure is configured to include a first barrier layer disposed between a first fixed layer and a free
layer, wherein magnetization direction of the free layer is used to store data, the magnetization direction being controlled
by an electric field;

a second MTJ structure coupled between the first terminal and the second terminal, wherein a portion of the second MTJ structure
is configured to include a second barrier layer disposed between a second fixed layer and the free layer, wherein a tunnel
magnetoresistance (TMR) of the second barrier layer is used to read the data, wherein the first terminal comprises a first
conductive plug which covers a first portion of the second barrier layer;

a conductive top lead layer coupled to the second terminal, the conductive top lead layer being disposed to cover the second
fixed layer, wherein the second fixed layer covers a second portion of the second barrier layer; and

a spacer configured to insulate the first conductive plug from the conductive top lead layer and the second fixed layer, wherein
the spacer covers a center portion of the second barrier layer.

US Pat. No. 9,564,243

EQUIVALENT FUSE CIRCUIT FOR A ONE-TIME PROGRAMMABLE READ-ONLY MEMORY ARRAY

GLOBALFOUNDRIES SINGAPORE...

1. A one-time programmable read-only memory array, comprising:
a memory cell, comprising:
a first transistor; and
a fuse equivalent circuit configured to receive a programming current and configured to output the programming current to
the first transistor, the fuse equivalent circuit comprising:

a voltage divider configured to divide a first voltage to generate a second voltage;
an operational amplifier comprising: a first input configured to receive a third voltage, a second input coupled to the voltage
divider and being configured to receive the second voltage, and an output that is configured to generate an output voltage;

a current mirror configured to receive the output voltage and configured to generate a first current; and
a fuse coupled to the first transistor at a node and the voltage divider at the node, the fuse being configured to receive
the first current from the current mirror, wherein the output voltage generated by the operational amplifier controls the
first current to maintain the third voltage at substantially the same value as the second voltage.

US Pat. No. 9,437,547

THROUGH SILICON VIAS

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:
a substrate with top and bottom surfaces;
a through silicon via (TSV) in the substrate, the TSV extends through top and bottom surfaces of the substrate;
an insulation stack disposed in the TSV, the insulation stack lines the sidewalls of the TSV and comprises a first insulation
layer, a polish stop layer and a second insulation layer, wherein the polish stop layer lines the first insulation layer and
the second insulation layer lines the polish stop layer in the TSV, the first insulation layer and the polish stop layer further
extends over the top surface of the substrate and continuously line the top surface, wherein the polish stop layer is disposed
over the first insulation layer; and

a conductive plug disposed in the TSV and fills the TSV having the insulation stack lining the sidewall, wherein a top surface
of the conductive plug in the TSV is coplanar with a top surface of the polish stop layer over the top surface of the substrate,
the polish stop layer serves as a polish stop for a planarizing process.

US Pat. No. 9,368,386

CORNER TRANSISTOR SUPPRESSION

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:
forming a pad oxide layer on an upper surface of a substrate;
forming a pad nitride layer on the pad oxide layer;
forming a trench, having side surfaces and a bottom surface, in the substrate, through the pad oxide and pad nitride layers;
forming an oxide liner on the side surfaces and bottom surface of the trench;
forming a layer of high-K dielectric material on the oxide liner, on side surfaces of the pad oxide and pad nitride layers,
and on an upper surface of the pad nitride layer;

filling the trench with insulating material by a high aspect ratio process forming an overburden over the pad nitride layer
subsequent to forming the layer of high-K dielectric material; and

removing portions of the insulating material and high-K dielectric layer, the pad nitride layer, and the pad oxide layer by
planarizing down to an upper surface of the pad nitride layer followed by etching,

wherein after the etching, high-K dielectric spacers are formed only at upper corners of the trench.

US Pat. No. 9,064,951

DEEP DEPLETED CHANNEL MOSFET WITH MINIMIZED DOPANT FLUCTUATION AND DIFFUSION LEVELS

GLOBALFOUNDRIES Singapore...

1. A device comprising:
a substrate;
a source and a drain in the substrate, separated by a ground plane layer;
a channel layer over the ground plane layer, the channel layer formed in a recess in the substrate above at least part of
the ground plane layer;

a gate electrode over the channel layer; and
a high-k layer on side surfaces of the gate electrode and between the channel layer and the gate electrode.

US Pat. No. 9,653,137

STT-MRAM BITCELL FOR EMBEDDED FLASH APPLICATIONS

GLOBALFOUNDRIES SINGAPORE...

1. A spin transfer torque magnetic random access memory (STT-MRAM) device comprising:
a first bitline having M number of STT-MRAM cells,
a second bitline having M number of STT-MRAM cells, wherein
the first and second bitlines form first and second columns of STT-MRAM cells, and a MRAM cell comprises
a magnetic tunnel junction (MTJ) element having first and second MTJ terminals, and
an access transistor having a gate, source and drain terminals, wherein the drain terminal is coupled the first MTJ terminal,
providing a series coupling between the access transistor with the MTJ element;

a plurality of M number of word lines (WLs) coupled to the gate terminals of the access transistors of the STT-MRAM cells,
wherein a WL is coupled to one STT-MRAM cell in the first and second bitlines to form a row of STT-MRAM cells, the plurality
of M number of WLs form M rows of STT-MRAM cells; and

a source line (SL) coupled to the source terminals of the access transistors of the STT-MRAM cells of the first and second
columns of STT-MRAM cells, wherein the SL is shared by the first and second columns of STT-MRAM cells and configured at a
metal level greater than metal level M1 which is situated above a pre-metal dielectric (PMD) to accommodate an increase in
the width of the SL.

US Pat. No. 9,500,945

PATTERN CLASSIFICATION BASED PROXIMITY CORRECTIONS FOR RETICLE FABRICATION

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:
obtaining a digital layout of a circuit design;
obtaining proximity compensation data generated based on measurements of formed reticle elements, the proximity compensation
data comprising proximity correction values to correct for proximity effects of a reticle-formation process to form a reticle
for use in fabricating a circuit of the circuit design; and

applying, based on a pattern classification of one or more patterns in the digital layout of the circuit design, at least
one proximity correction to the digital layout of the circuit design to facilitate correcting for proximity effects of the
reticle-formation process, the at least one proximity correction being determined based on one or more of the proximity correction
values of the obtained proximity compensation data.

US Pat. No. 9,444,041

BACK-GATED NON-VOLATILE MEMORY CELL

GLOBALFOUNDRIES Singapore...

1. A non-volatile memory device comprising:
a substrate having a non-volatile memory cell region, the substrate includes a buried oxide (BOX) layer between a surface
substrate layer and a base substrate layer;

at least one isolation region in the substrate, wherein the at least one isolation region isolates the non-volatile memory
cell region from other active regions, the isolation region extends from a top surface of the surface substrate layer to a
depth deeper than the BOX layer;

a first polarity type band/well disposed within the base substrate layer, wherein the first polarity type band/well includes
a depth shallower than a bottom of the at least one isolation region; and

a non-volatile memory (NVM) cell disposed on the substrate in the memory cell region, wherein the non-volatile memory cell
comprises a transistor, the transistor includes

a first gate of the memory cell disposed on a surface of the surface substrate layer, the first gate includes a charge storage
layer, the first gate functions as a control gate of the memory cell, and

a second gate of the memory cell disposed in the base substrate layer, wherein the second gate is configured as a select gate
of the NVM cell.

US Pat. No. 9,608,081

SIMPLE AND COST-FREE MTP STRUCTURE

GLOBALFOUNDRIES Singapore...

1. A non-volatile (NV) multi-time programmable (MTP) memory cell comprising:
a substrate;
a first transistor having a select gate and a second transistor having a floating gate adjacent to one another and disposed
over a transistor well, the transistors comprise first and second S/D regions disposed adjacent to the sides of the gates;

a control gate disposed on the substrate and over a control well, wherein the control gate is coupled to the floating gate
and the control and floating gates comprise the same gate layer extending across the control and transistor wells, the control
gate comprises a control capacitor; and

an erase terminal, wherein the erase terminal is decoupled from the control capacitor and transistors.

US Pat. No. 9,553,129

MAGNETIC TUNNEL JUNCTION STACK ALIGNMENT SCHEME

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a device comprising:
providing a substrate defined with a memory cell region;
providing a first upper dielectric layer over the substrate, wherein the first upper dielectric layer comprises a first upper
interconnect level with one or more metal lines in the memory cell region;

providing a second upper dielectric layer over the first upper dielectric layer, wherein the second upper dielectric layer
comprises a via plug coupled to the metal line of the first upper interconnect level;

providing a protective layer over the second upper dielectric layer and covers the via plug;
forming an alignment trench which extends from a top surface of the protective layer to a portion of the second upper dielectric
layer;

forming various layers of a magnetic tunnel junction (MTJ) stack over the second upper dielectric layer, wherein profile of
the alignment trench is transferred to surfaces of the various layers of the MTJ stack to form a topography feature which
serves as an alignment mark; and

patterning the various layers of the MTJ stack to define at least one MTJ element using the topography feature which serves
as the alignment mark visible in top surface of the various layers of the MTJ stack to align the patterned MTJ element to
the underlying via plug and to ensure that the patterned MTJ element is coupled to and in direct contact with the underlying
via plug.

US Pat. No. 9,431,408

METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH A HIGH-VOLTAGE MOSFET

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating an integrated circuit comprising:
forming a first silicon material layer over a semiconductor substrate, the semiconductor substrate including a high-voltage
MOSFET region, a logic device region, and a memory array region, the memory array region having formed on the semiconductor
substrate a memory gate stack;

forming a first capping layer over the first silicon material layer and over the memory gate stack;
removing the first capping layer from over the memory array region but not from over the high-voltage MOSFET region and the
logic device region of the integrated circuit;

forming a second silicon material layer over the first capping layer and over the first silicon material layer;
removing the second silicon material layer in an amount such that the second silicon material layer is completely removed
from over the high-voltage MOSFET region and the logic device region;

removing the first capping layer from over the first silicon material layer in the high-voltage MOSFET region and the logic
device region;

forming a second capping layer over the first silicon material layer in the high-voltage MOSFET region and the logic device
region;

removing the first silicon material layer and the second capping layer from the high-voltage MOSFET region except in an area
overlying a channel region of the high-voltage MOSFET region;

forming a photoresist material layer over the memory array region and the logic device region; and
exposing the semiconductor substrate to a dopant ion implantation process.

US Pat. No. 9,242,338

CMP HEAD STRUCTURE

GLOBALFOUNDRIES Singapore...

1. A method for prolonging the use of a retaining ring comprising:
providing a head assembly for use in a process for polishing a wafer, wherein the head assembly includes a retaining ring
for holding the wafer in place on a polishing pad;

determining a depth of grooves on the retaining ring based on a gap between a membrane of the retaining ring and a side of
the retaining ring which correlates to the depth of the grooves;

calculating an updated pressure to be applied to the retaining ring based on the depth of the grooves; and
applying the updated pressure to the retaining ring during the process.

US Pat. No. 9,214,557

DEVICE WITH ISOLATION BUFFER

GLOBALFOUNDRIES Singapore...

1. A method for forming a device comprising:
providing a substrate prepared with a device region;
forming a fin in the device region, the fin includes top and bottom portions;
forming a gate over the top portion of the fin;
forming source/drain (S/D) regions in the top portion of the fin; and
forming an amorphous isolation buffer at least in the bottom fin portion below the gate, leaving the top fin portion crystalline,
wherein the amorphous isolation buffer reduces S/D junction current leakage.

US Pat. No. 9,171,855

THREE-DIMENSIONAL NON-VOLATILE MEMORY

GLOBALFOUNDRIES SINGAPORE...

1. A memory device, comprising:
a primary fin disposed on a substrate along a first direction;
first and second secondary fins disposed on the substrate along a second direction; and
a first gate of a first memory cell disposed on the substrate in a gate region thereof, wherein the first gate comprises
a program gate disposed on the substrate, wherein the program gate is displaced from the primary fin by a dielectric block
which is disposed on the substrate and adjacent to the primary fin, and wherein the dielectric block has a height which is
less than that of the program gate,

a floating gate disposed over the program gate, wherein the program gate is separated from the floating gate and the primary
fin by an inter-gate dielectric, and wherein the floating gate comprises a floating gate tip disposed adjacent to the program
gate and the dielectric block and between the program gate and the primary fin, and

a control gate disposed adjacent to the floating gate and the program gate, wherein the control gate is separated from the
substrate, the program gate, and the floating gate by the inter-gate dielectric.

US Pat. No. 9,130,010

LATCH-UP ROBUST SCR-BASED DEVICES

GLOBALFOUNDRIES Singapore...

1. A method comprising:
providing a first n-well region in a substrate for a silicon control rectifier (SCR);
providing a first N+ region and a first P+ region in the substrate on a first side of the first n-well region;
providing a second n-well region on a second side of the first n-well region that is opposite the first side;
providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region;
coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an
I/O pad;

providing a holding voltage of the SCR that is greater than a maximum operating voltage of the SCR during a latch-up event
by turning on the power rail;

providing a third P+ region between the second N+ and P+ regions;
providing a resistor having first and second resistor terminals;
providing a capacitor having first and second capacitor terminals; and
coupling the third P+ region to the first resistor and capacitor terminals, the second resistor terminal to the ground rail,
and the second capacitor terminal to the I/O pad.

US Pat. No. 10,032,980

INTEGRATED CIRCUITS WITH MAGNETIC TUNNEL JUNCTIONS AND METHODS FOR PRODUCING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit comprising:a magnetic tunnel junction comprising a fixed layer, a total free structure, and a barrier layer positioned between the fixed layer and the total free structure, wherein the total free structure comprises a first free layer, a second free layer, and a first spacer layer, wherein the first spacer layer is non-magnetic, wherein the first spacer layer is disposed between the first free layer and the second free layer, wherein at least one of the first free layer or the second free layer comprise a primary free layer alloy, wherein the primary free layer alloy comprises an alloy of cobalt, iron, boron, and a free layer additional element, wherein the free layer additional element is present at a concentration of from about 1 atomic percent to about 10 atomic percent, based on a total weight of the primary free layer alloy, and wherein the free layer additional element is selected from one or more of niobium (Nb) and hafnium (Hf).

US Pat. No. 9,941,160

INTEGRATED CIRCUITS HAVING DEVICE CONTACTS AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

10. A method for fabricating an integrated circuit having a device contact, the method comprising:filling a contact opening with conductive material to form a contact, wherein the contact opening is formed in a first ILD layer of dielectric material that overlies a device region, optionally with a liner disposed between the contact and the ILD layer;
planarizing the conductive material to expose a contact seam void formed in the contact;
depositing Ti and/or TiN to form a Ti/TiN layer that partially fills the contact seam void to define a conductive plug and that overlies the contact and the first ILD layer such that the conductive plug fills an upper portion of the contact seam void and leaves a lower-most portion of the seam void unfilled forming an enclosed space between the conductive plug and the lower-most portion of the contact; and depositing a metallization layer overlying the contact;
depositing a second ILD layer of dielectric material overlying the first ILD layer and the contact;
etching the second ILD layer to form a sidewall that defines a metallization trench to expose both the contact and the conductive plug;
forming a liner in the metallization trench overlying the sidewall and the contact, wherein the liner is in direct contact with both the contact and the conductive plug; and
plating a metallization layer in the metallization trench overlying the liner.

US Pat. No. 9,583,167

LOW POWER MEMORY CELL WITH HIGH SENSING MARGIN

GLOBALFOUNDRIES Singapore...

1. A memory cell comprising:
a first magnetic tunnel junction (MTJ) element coupled to a first bit line;
a second MTJ element coupled to a second bit line, wherein the first and second MTJ elements have a common node;
a first selector having a first selector first select transistor with a first gate coupled to a first wordline and first and
second source/drain (S/D) regions, wherein the common node of the first and second MTJ elements is coupled to the first S/D
region of the first selector first select transistor; and

a second selector having a second selector first select transistor with a second gate coupled to a second wordline and first
and second S/D regions, and a second selector second select transistor with a third gate coupled to the second wordline and
first and second S/D regions, wherein the first S/D regions of the second selector first select transistor and second selector
second select transistor are a common first S/D region coupled to the second bitline.

US Pat. No. 9,515,152

SIMPLE AND COST-FREE MTP STRUCTURE

GLOBALFOUNDRIES SINGAPORE...

1. A non-volatile (NV) multi-time programmable (MTP) memory cell comprising:
a substrate;
a floating gate disposed over a transistor well;
a control gate disposed over a control well, wherein the control gate is coupled to the floating gate, the control gate comprises
a control capacitor;

a high voltage (HV) well region disposed within the substrate, wherein the HV well region encompasses the transistor well
and control well; and

a non-self-aligned source/drain (S/D) region disposed within the transistor well, wherein the non-self-aligned S/D region
serves as an erase terminal.

US Pat. No. 9,431,497

TRANSISTOR DEVICES HAVING AN ANTI-FUSE CONFIGURATION AND METHODS OF FORMING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A transistor device having an anti-fuse configuration, the transistor device comprising:
a semiconductor substrate comprising a first fin and a second fin extending parallel to the first fin;
a first insulator layer overlying the semiconductor substrate and having a thickness less than a height of the first fin and
the second fin, with the first fin and the second fin extending through and protruding beyond the first insulator layer to
provide buried fin portions embedded within the first insulator layer and exposed fin portions protruding beyond the first
insulator layer;

a gate electrode structure overlying the exposed fin portions of the first fin and the second fin, wherein the gate electrode
structure wraps around the exposed fin portions on three sides thereof; and

a gate insulating structure disposed between the first fin and the gate electrode structure and between the second fin and
the gate electrode structure, wherein the gate insulating structure comprises a first dielectric layer comprising a breakdown
dielectric material overlying a first surface of the first fin and a first surface of the second fin, and a second dielectric
layer different from the first dielectric layer overlying a second surface of the first fin and a second surface of the second
fin, wherein a first potential breakdown path is defined between the first fin and the gate electrode structure through the
first dielectric layer and a second potential breakdown path is defined between the second fin and the gate electrode structure
through the second dielectric layer, and wherein the gate electrode structure is disposed over the first dielectric layer
and the second dielectric layer, which insulate the first fin and the second fin from the gate electrode structure;

wherein the second dielectric layer of the first fin and the second dielectric layer of the second fin are physically separate
and spaced from each other with the gate electrode structure disposed therebetween.

US Pat. No. 9,362,128

METHODS FOR FABRICATING INTEGRATED CIRCUITS AND COMPONENTS THEREOF

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating a semiconductor device, wherein the method comprises:
providing a partially fabricated semiconductor device, comprising:
a semiconductor substrate;
a first gate formed over the semiconductor substrate; and
a second gate formed over the semiconductor substrate and spaced apart from the first gate;
forming spacers on sidewalls of the first gate and sidewalls of the second gate;
forming a mask between the first gate and the second gate;
implanting a dopant into the semiconductor substrate to form highly doped source-drain regions outside of the first gate and
the second gate and lightly doped source-drain regions underneath the spacers;

removing the mask between the first gate and the second gate;
depositing a protection layer between the first gate and the second gate; and
forming silicide regions outside of the first gate and the second gate;
wherein silicide formation between the first gate and the second gate is inhibited by the protection layer.

US Pat. No. 10,032,765

INTEGRATED CIRCUITS WITH ELECTROSTATIC DISCHARGE PROTECTION AND METHODS FOR PRODUCING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit comprising:a deep well;
a drain well overlying the deep well;
a first source well overlying the deep well, wherein the first source well comprises a first source well concentration of conductivity determining impurities;
a second source well overlying the first source well, wherein the second source well comprises a second source well concentration of conductivity determining impurities that is higher than the first source well concentration;
a drain overlying the drain well;
a source overlying the second source well;
a channel defined between the source and the drain; and
a gate overlying the channel.

US Pat. No. 9,728,721

RESISTIVE MEMORY DEVICE

GLOBALFOUNDRIES SINGAPORE...

1. A method for forming a device comprising:
providing a substrate prepared with a lower cell dielectric layer with gate conductors disposed in a first direction, wherein
the gate conductors are elongated gate conductors formed in the lower cell dielectric layer and separated by the lower cell
dielectric layer;

forming a body unit conductor over a top surface of the lower cell dielectric layer and gate conductors, wherein the body
unit conductor is disposed in and along a second direction orthogonal to the first direction and traverses the gate conductors;

forming memory element conductors on the body unit conductor and lower cell dielectric layer, wherein the memory element conductors
are elongated memory element conductors disposed in and along the same first direction over the gate conductors; and

forming an upper cell dielectric layer on the substrate to cover the lower cell dielectric layer, body unit conductor and
memory element conductors, wherein the upper cell dielectric layer isolates the memory element conductors from each other.

US Pat. No. 9,728,474

SEMICONDUCTOR CHIPS WITH SEAL RINGS AND ELECTRONIC TEST STRUCTURES, SEMICONDUCTOR WAFERS INCLUDING THE SEMICONDUCTOR CHIPS, AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A semiconductor chip comprising:
an active area including a plurality of integrated circuit structures;
a seal ring enclosing the active area;
a corner area of the semiconductor chip that is outside of the seal ring; and
an electronic test structure disposed within the corner area, wherein the electronic test structure comprises a magnetic tunnel
junction (MTJ) in between bottom and top electrode layers connected by vias, and disposed within an insulating dielectric
layer.

US Pat. No. 9,659,943

PROGRAMMABLE INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit comprising:
a semiconductor substrate having a central shallow trench isolation (STI) region; and
a unit cell including:
a first select transistor having a first select gate structure, a first source region, and a first drain region in contact
with a first portion of the central STI region;

a second select transistor having a second select gate structure, a second source region, and a second drain region in contact
with a second portion of the central STI region, wherein the first drain region is opposite of the second drain region relative
to the central STI region; and

a central gate structure overlying the central STI region and including a central gate dielectric layer having:
a medial dielectric region overlying the central STI region between the first drain region and the second drain region;
a first lateral dielectric region overlying the first drain region; and
a second lateral dielectric region overlying the second drain region;
wherein the first lateral dielectric region defines a first programmable element and the second lateral dielectric region
defines a second programmable element.

US Pat. No. 9,673,084

ISOLATION SCHEME FOR HIGH VOLTAGE DEVICE

GLOBALFOUNDRIES SINGAPORE...

1. A method for forming a device comprising:
providing a base substrate with lightly doped first polarity type dopants;
forming a buried layer with heavily doped second polarity type dopants in a top portion of the base substrate;
forming an epitaxial layer over the buried layer;
forming first and second type deep trench isolation (DTI) structures which extend from a top surface of the epitaxial layer
through the buried layer and to a portion of the base substrate to isolate different device regions defined in the base substrate,
wherein the first and second type DTI structures have different width dimensions;

forming shallow trench isolation (STI) regions in the epitaxial layer, the STI regions extend from the top surface of the
epitaxial layer and terminate within the epitaxial layer, wherein the STI regions and DTI structures are discontiguous features,
the STI regions and DTI structures have planar top surfaces which are coplanar with the top surface of the epitaxial layer;
and

forming at least one transistor on the epitaxial layer.

US Pat. No. 9,620,418

METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED ACTIVE REGIONS

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating an integrated circuit, the method comprising:
providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a
low voltage device area and in a high voltage device area, wherein the isolation regions are formed with an upper surface
at a step height over the active regions, and wherein the isolation regions have sidewalls in contact with the active regions;

selectively etching the upper surface of the isolation regions to reduce the step height and selectively etching the sidewalls
of the isolation regions to form voids between the isolation regions and the active regions in the high voltage device area
to expose active side surfaces; and

oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the
high voltage device area.

US Pat. No. 9,520,885

DIGITAL PHASE LOCKED LOOP (PLL) SYSTEM WITH FREQUENCY BAND JUMP IN LOCK MODE

GLOBALFOUNDRIES SINGAPORE...

1. A phase locked loop (PLL) control system, comprising:
a digital controlled oscillator (DCO) comprising:
a delay cell chain comprising a number (B) of delay cells;
a load control cell comprising a number (L) of load cells; and
a module configured to:
dynamically adjust, when the PLL control system is operating in a lock mode, the number (B) of delay cells that are activated
and part of the delay cell chain and the number (L) of load cells that are switched on to control an amount of delay in the
DCO.

US Pat. No. 9,397,146

VERTICAL RANDOM ACCESS MEMORY WITH SELECTORS

GLOBALFOUNDRIES Singapore...

1. A method of manufacturing a device comprising:
providing a substrate;
forming an inter-layer dielectric (ILD) layer over the substrate;
forming, on the ILD layer, a vertical structure having a plurality of memory with one or more selectors, the vertical structure
is made of a plurality of conductive stacks, wherein a conductive stack of the plurality of conductive stacks is formed by

(a) forming first and second first type conductors on first and second sides of the conductive stack,
(b) providing a first memory element adjacent the first first type conductor and a second memory element adjacent the second
first type conductor,

(c) forming first and second electrodes with the first electrode adjacent the first memory element and the second electrode
adjacent the second memory element,

(d) forming a conductor layer of a first polarity type between the first and second first type conductors, and
(e) forming a dielectric layer over the first and second first type conductors, the first and second electrodes, and the conductor
layer of the first polarity type;

forming and stacking a successive conductive stack by repeating steps (a)-(e) over a preceding conductive stack formed by
steps (a)-(e) to form the vertical structure on the ILD layer;

etching an opening through a middle portion of the plurality of conductive stacks which form the vertical structure and the
ILD layer after forming the plurality of conductive stacks; and

filling the opening with a conductor layer.

US Pat. No. 9,349,654

ISOLATION FOR EMBEDDED DEVICES

GLOBALFOUNDRIES Singapore...

1. A method of forming a device comprising:
providing a substrate prepared with isolation regions, wherein the substrate comprises at least first, second and third regions,
the first region comprises a memory region, the second region comprises a high voltage (HV) region and the third region comprises
a logic region;

forming an additional dielectric layer in direct contact with the substrate and the isolation regions;
selectively processing a first select region while protecting first non-select regions, wherein the first select region is
one of the first, second and third regions, and wherein selectively processing the first select region comprises performing
a removal process to remove the additional dielectric layer over the first select region and to reduce a height of the isolation
regions in the first select region; and

forming a first gate dielectric on the select region, wherein top substrate active area and isolation regions of the first
non-select regions are not exposed during processing of the first select region and forming the first gate dielectric.

US Pat. No. 9,269,770

INTEGRATED CIRCUIT SYSTEM WITH DOUBLE DOPED DRAIN TRANSISTOR

GLOBALFOUNDRIES Singapore...

11. An integrated circuit system comprising:
a substrate;
a gate over the substrate;
a first drift region formed in the substrate adjacent to a first side of the gate;
a first counter diffused region formed in the first drift region, to a depth less than a depth of the first drift region,
to form a bipolar-like junction with the first drift region; and

a source diffused region, formed in the first drift region and separated from the first counter diffused region, near a side
of the first counter diffused region located further from the gate.

US Pat. No. 9,236,391

METHOD OF FORMING SPLIT-GATE CELL FOR NON-VOLATIVE MEMORY DEVICES

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising: a first gate on a substrate, the first gate having an upper surface; an interpoly isolation layer
or charge storage layer on side surfaces of the first gate and
extending above the upper surface of the first gate;
a second gate adjacent to the interpoly isolation layer or charge storage layer on a first side of the first gate, the second
gate having a spacer shape and having an uppermost point of the second gate below the upper surface of the first gate;

spacers formed on exposed vertical surfaces of the first and second gates and the interpoly isolation layer;
a salicide formed on exposed non-vertical surfaces of the first and second gates and the substrate; and
wherein the first gate is one of a select gate and a control gate, and the second gate is the other of a select gate and a
control gate, wherein an uppermost point of the interpoly isolation layer or charge storage layer on the first side is higher
than an uppermost point of the second side opposite to the first side and an uppermost point of the first gate is lower than
the uppermost point of the interpoly isolation layer or charge storage layer on the second side.

US Pat. No. 9,165,920

TUNABLE PROTECTION SYSTEM FOR INTEGRATED CIRCUITS

GLOBALFOUNDRIES Singapore...

1. A tunable protection method comprising:
forming a tunable trigger device having a trigger junction body overlapping a trigger active area to provide a trigger overlap,
the tunable trigger device having the trigger overlap adjustable for providing an adjustable protection activation level;

forming a circuit protection device having a protection body overlapping a protection active area to provide a protection
overlap, the circuit protection device having the protection overlap adjustable for providing an adjustable protection level
for integrated circuits; and

connecting electrically the tunable trigger device and the circuit protection device to an input/output pad.

US Pat. No. 9,053,269

SYSTEM AND METHODS FOR OPC MODEL ACCURACY MANAGEMENT AND DISPOSITION

GLOBALFOUNDRIES SINGAPORE...

1. A method for generating a mask used in lithographic processes to form a semiconductor device on a wafer, the method comprising:
employing a computer for performing quad matrix management to quantify optical proximity correction (OPC) model accuracy comprising
obtaining wafer data from a calibration test pattern,
classifying the same wafer data obtained from the calibration test pattern into four quadrants of a quad matrix, and
utilizing one of the four quadrants to quantify OPC model accuracy; and
creating a photomask after performing the quad matrix management.

US Pat. No. 9,640,438

INTEGRATED CIRCUITS WITH INACTIVE GATES AND METHODS OF MANUFACTURING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method of manufacturing an integrated circuit comprising:
forming a first active dummy gate, a second active dummy gate, and an inactive gate overlying a substrate;
replacing the first active dummy gate with a first metal gate, wherein replacing the first active dummy gate comprises planarizing
the first metal gate, the second active dummy gate, and the inactive gate such that a first metal gate top surface is lower
than a top surface of the second active dummy gate; and

replacing the second active dummy gate with a second metal gate after replacing the first active dummy gate, wherein the inactive
gate remains overlying the substrate after replacing the second active dummy gate.

US Pat. No. 9,263,665

TWO-BITS PER CELL STRUCTURE WITH SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method of fabricating an integrated circuit comprising:
forming a bottom electrode within an interlayer dielectric (ILD) layer, wherein the bottom electrode is formed having an upper
surface coplanar with an upper surface of the ILD layer;

forming an anti-ferromagnetic (AF) layer over the bottom electrode;
forming a fixed layer along sidewalls of the AF layer;
forming a tunnel layer along the fixed layer;
forming a free layer along the tunnel layer; and
forming a top electrode along the free layer and over an upper surface of the AF layer.

US Pat. No. 9,202,746

INTEGRATED CIRCUITS WITH IMPROVED GAP FILL DIELECTRIC AND METHODS FOR FABRICATING SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating an integrated circuit, the method comprising:
depositing a gap fill dielectric overlying a semiconductor substrate, wherein the gap fill dielectric is formed with a raised
portion and a base portion and with an upper surface having a height differential between the raised portion and the base
portion;

reducing the height differential of the upper surface of the gap fill dielectric by recessing the raised portion, wherein
the base portion is not recessed, and wherein the upper surface of the gap fill dielectric remains non-planar after reducing
the height differential;

depositing an interlayer dielectric overlying the gap fill dielectric; and
forming an electrical contact to a selected location overlying the semiconductor substrate.

US Pat. No. 9,196,544

INTEGRATED CIRCUITS WITH STRESSED SEMICONDUCTOR-ON-INSULATOR (SOI) BODY CONTACTS AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating an integrated circuit, the method comprising:
forming a channel region in a device area of a semiconductor-on-insulator (SOI) substrate;
forming a body contact in a body contact area of a semiconductor-on-insulator (SOI) substrate, wherein the channel region
and the body contact form a transistor device;

forming a first stress film over the device area and selectively applying a first stress to the channel region in a longitudinal
direction; and

forming a second stress film over the body contact area and selectively applying a second stress to the body contact in a
lateral direction perpendicular to the longitudinal direction.

US Pat. No. 9,064,084

TOPOGRAPHY DRIVEN OPC AND LITHOGRAPHY FLOW

GLOBALFOUNDRIES SINGAPORE...

1. A method for forming a device comprising:
providing a design data file of an integrated circuit (IC);
performing topography analysis on the design data file by using a topography module, wherein the analysis comprises generating
topography maps for mask levels of the IC based on accumulative topography profile for different mask levels separating a
mask level into topography regions based on relative heights, wherein topography maps comprise topography regions;

performing optical proximity correction (OPC), by using an OPC module, on the design data file with topography information
from the topography analysis, wherein the OPC adjusts patterns of the mask levels based on defocus values associated with
topography regions, the OPC produces an adjusted design data file;

generating a mask set from the adjusted design data file; and
processing a wafer to form devices using the mask set.

US Pat. No. 9,048,129

METHOD FOR FORMING FULLY RELAXED SILICON GERMANIUM ON SILICON

GLOBALFOUNDRIES Singapore...

1. A method comprising:
forming a silicon germanium (SiGe) epitaxial layer having a thickness less than 200 nm on a semiconductor substrate;
ion implanting a dopant into the SiGe epitaxial layer; and
annealing the implanted SiGe epitaxial layer at a temperature of 400° C. to 1350° C.,
wherein the annealed SiGe has a threading dislocation density less than 1e6/cm2, and
wherein the annealed SiGe has a degree of strain relaxation greater than 90%.

US Pat. No. 10,062,710

INTEGRATED CIRCUITS WITH DEEP AND ULTRA SHALLOW TRENCH ISOLATIONS AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit comprising:an SOI substrate comprising an active layer, a buried insulator layer, and a handle layer, wherein the active layer overlies the buried insulator layer, and the buried insulator layer overlies the handle layer;
a source defined within the active layer;
a gate well defined within the active layer;
a first ultra shallow trench isolation extending into the active layer, wherein a first portion of the active layer is positioned between the first ultra shallow trench isolation and the buried insulator layer, and wherein the first ultra shallow trench isolation is positioned between the source and the gate well;
a gate insulator directly overlying the first ultra shallow trench isolation, wherein the gate insulator is an electrical insulator; and
a USTI gate directly overlying the gate insulator.

US Pat. No. 9,496,187

SETUP FOR MULTIPLE CROSS-SECTION SAMPLE PREPARATION

GLOBALFOUNDRIES Singapore...

1. A multiple-sample-holder polishing setup for cross-section sample preparation comprising:
a frame, the frame having a hollow center, one or more long rods, one or more short rods and a recess, wherein the one or
more long rods and the one or more short rods are configured to accommodate one or more sample holders and the recess is configured
for accommodating a polishing head;

one or more sample holders, the one or more sample holders to be directly attached to the one or more long rods and the one
or more short rods of the frame;

a paddle affixed to each sample holder; and
a sample attached to the paddle, wherein the sample is coated with a thin epoxy layer prior to polishing thereby allowing
for easy inspection for site of interests as well as quick material removal, and wherein the one or more long rods and the
one or more short rods are configured to allow the one or more sample holders to be placed on different positions on the frame
so that the sample in the sample holders will experience different polishing conditions on the same frame.

US Pat. No. 9,443,761

METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING DEVICE CONTACTS

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating an integrated circuit, the method comprising:
providing a semiconductor device with a metal silicide electrically coupled thereto;
forming a contact opening to the semiconductor device and exposing the metal silicide;
depositing a conductive material within the contact opening to form a contact to the metal silicide while simultaneously forming
a contact seam void within the contact;

depositing a self-aligned conductive material within the contact to form a conductive plug that at least partially fills the
contact seam void; and

depositing a metallization layer overlying the contact.

US Pat. No. 9,343,466

METHODS FOR FABRICATING FLASH MEMORY CELLS AND INTEGRATED CIRCUITS HAVING FLASH MEMORY CELLS EMBEDDED WITH LOGIC

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating a memory cell, the method comprising:
depositing a first tunnel dielectric layer over a semiconductor substrate;
depositing a floating gate material over the first tunnel dielectric layer;
forming two control gate stacks over the floating gate material, wherein a source line area is defined between the two control
gate stacks, and wherein select gate areas are defined adjacent the two control gate stacks;

doping the select gate areas before depositing a second tunnel dielectric layer over the select gate areas of the semiconductor
substrate; and

forming select gates over the second tunnel dielectric layer over the select gate areas of the semiconductor substrate, wherein
the second tunnel dielectric layer forms a gate dielectric layer for each select gate.

US Pat. No. 9,209,275

INTEGRATED CIRCUITS WITH MEMORY CELLS AND METHODS OF MANUFACTURING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method of manufacturing an integrated circuit comprising:
removing a central plug from between a first memory cell and a second memory cell to define a center gap between the first
memory cell and the second memory cell, wherein each of the first memory cell and the second memory cell comprises a control
gate having a control gate height, a cap overlying the control gate, a select gate adjacent to the control gate, and a select
gate dielectric between the control gate and the select gate;

recessing the select gate to a select gate height while the cap overlies the control gate, wherein the select gate height
is less than the control gate height; and

forming a memory spacer overlying the select gate dielectric and adjacent to the control gate.

US Pat. No. 9,054,133

HIGH VOLTAGE TRENCH TRANSISTOR

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a device comprising:
providing a substrate defined with a device region;
forming a gate in the substrate, wherein forming the gate comprises
forming a first trench, wherein the first trench defines an upper trench portion,
forming a first gate dielectric layer on the upper trench portion, wherein the first gate dielectric layer lines the upper
trench portion without filling the trench, and

forming a gate electrode layer on the substrate, wherein the gate electrode layer fills the upper trench portion;
forming a second trench through the gate, wherein the second trench extends below the upper trench portion and forms a lower
trench portion;

forming a second gate dielectric layer in the second trench, wherein the second gate dielectric layer lines the second trench
without filling the trench;

forming a field plate in the second trench, the field plate fills the trench, wherein the field plate is disposed adjacent
to the gate; and

forming first and second diffusion regions,
wherein the gate is displaced from the second diffusion region.

US Pat. No. 9,520,506

3D HIGH VOLTAGE CHARGE PUMP

GLOBALFOUNDRIES SINGAPORE...

1. A non-volatile memory (NVM) charge pump capacitor comprising:
a substrate including a capacitor region in which the capacitor is disposed, the capacitor includes
a first sub-capacitor (C1), the first sub-capacitor comprises a high voltage (HV) metal oxide semiconductor (MOS) capacitor which includes a HV gate
on the substrate, the HV gate includes a HV gate electrode over a HV gate dielectric, wherein

a first C1 plate is served by the HV gate electrode,

a second C1 plate is served by the substrate of the capacitor region, and

a C1 capacitor dielectric is served by the HV gate dielectric,

a second sub-capacitor (C2), the second sub-capacitor comprises a back-end-of-line (BEOL) vertical capacitor disposed in interlevel dielectric (ILD)
layers with metal levels and via levels, wherein a plurality of metal lines are disposed in the metal levels, the metal lines
of a metal level are grouped in alternating first and second groups, the first group serves as first C2 plates and second group serves as second C2 plates and the dielectric layers between the first and second groups serve as C2 capacitor dielectrics, and

a third sub-capacitor (C3), wherein

a first C3 plate is served by the HV gate electrode,

a second C3 plate is served by metal lines of the second group in a first metal level (M1) of the ILD layers, and

a C3 capacitor dielectric is served by a first via level dielectric below M1 and above the HV gate electrode;

a first capacitor terminal coupled to first capacitor plates of C1, C2 and C3; and

a second capacitor terminal coupled to second capacitor plates of C1, C2 and C3.

US Pat. No. 9,490,423

INTEGRATED CIRCUIT STRUCTURES WITH SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY ULTILIZING ALUMINUM METALLIZATION LAYERS AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method of fabricating an integrated circuit, the integrated circuit comprising a memory portion and a logic portion,
the method comprising the steps of:
forming a first interlayer dielectric (ILD) layer in both the memory portion and the logic portion simultaneously;
forming a first metallization layer over the first ILD layer in both the memory portion and the logic portion simultaneously,
wherein the first metallization layer comprises an aluminum material that includes aluminum as its majority constituent;

forming a magnetic tunnel junction (MTJ) structure over the first metallization layer that is in physical and electrical contact
with the first metallization layer in only the memory portion, wherein forming the MTJ structure comprises forming an MTJ
layer in both the memory portion and the logic portion simultaneously, and thereafter etching only a portion of the MTJ layer
in the memory region to form the MTJ structure while simultaneously etching away an entirety of the MTJ layer in the logic
region;

forming an encapsulation layer over the MTJ structure and over the first metallization layer in the memory portion while simultaneously
forming the encapsulation layer of the first metallization layer in the logic portion;

in the memory portion, etching the encapsulation layer and the first metallization layer to form an encapsulation segment
overlying a first memory metal line, wherein both the encapsulation segment and the first memory metal line have dimensions
that are greater than dimensions of the MTJ structure, while simultaneously in the logic portion, etching the encapsulation
layer and the first metallization layer to form an encapsulation segment overlying a first logic metal line;

forming a second ILD layer over the first ILD layer and the encapsulation segments of both the memory and logic portions,
simultaneously;

forming a first contact hole within the second ILD layer and the encapsulation segment in the memory portion to expose a portion
of the MTJ structure, wherein the first contact hole has dimensions that are smaller than the dimensions of the MTJ structure,
and simultaneously forming a second contact hole within the second ILD layer and the encapsulation segment in the logic portion
to expose a portion of the first logic metal line;

forming a first contact plug within the first contact hole in physical and electrical contact with the MTJ structure in the
memory portion, and simultaneously forming a second contact plug within the second contact hole in physical and electrical
contact with the first logic metal line; and

forming a second memory metal line over the second ILD layer and the first contact plug in physical and electrical contact
with the first contact plug and simultaneously forming a second logic metal line over the second ILD layer and the second
contact plug in physical and electrical contact with the second contact plug, wherein the first and second memory metal lines
comprise an aluminum material that includes aluminum as its majority constituent, wherein:

the first and second memory metals lines, and the first and second logic metal lines, respectively, are formed on-axis with
regard to one another, and

the method excludes the use of damascene processes in the formation of the first and second memory metal lines and the first
and second logic metal lines.

US Pat. No. 9,484,530

INTEGRATED CIRCUIT STRUCTURES WITH SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY HAVING INCREASED MEMORY CELL DENSITY AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

11. A method for fabricating an integrated circuit comprising:
forming a word line layer;
forming a bit line layer, wherein the word line layer is formed so as to extend substantially perpendicularly with respect
to the bit line layer;

forming a magnetic random access memory (MRAM) stack in contact with the bit line layer;
forming a spacer structure surrounding the MRAM stack;
forming a first doped silicon layer in contact with the MRAM stack, the first doped silicon layer comprising conductivity-determining
ions of a first type;

forming a trench through the first doped silicon layer to expose an end portion of the first doped silicon layer;
forming a second doped silicon layer in contact with the end portion of the first doped silicon layer and further in contact
with the word line layer, the second doped silicon layer comprising conductivity-determining ions of a second type that is
opposite the first type;

forming a third doped silicon layer in contact with the second doped silicon layer;
forming a source line layer in electrical contact with the third doped silicon layer; and
forming a first interlayer dielectric (ILD) layer below the first doped silicon layer and a second ILD layer above the first
doped silicon layer, wherein forming the trench comprises forming a trench through the first and second ILD layers in addition
to through the first doped silicon layer, wherein forming the second doped silicon layer comprises forming a second doped
silicon layer along the first and second ILD layers within the trench, and wherein the first doped silicon layer and the first
and second ILD layer are formed so as to form a common sidewall that extends vertically above the word line layer, and wherein
the second doped silicon layer is formed along the common sidewall along the first doped silicon layer and the first and second
ILD layers.

US Pat. No. 9,252,142

INTEGRATED CIRCUITS INCLUDING A RESISTANCE ELEMENT AND GATE-LAST TECHNIQUES FOR FORMING THE INTEGRATED CIRCUITS

GLOBALFOUNDRIES SINGAPORE...

1. A gate-last technique for forming an integrated circuit including a resistance element, the technique comprising:
providing a semiconductor substrate including a shallow trench isolation structure disposed therein;
patterning a dummy gate electrode structure overlying semiconductor material of the semiconductor substrate and a resistor
structure overlying the shallow trench isolation structure, wherein the dummy gate electrode structure and the resistor structure
comprise a dummy layer overlying a metal capping layer and a gate dielectric layer underlying the metal capping layer;

forming an interlayer dielectric layer overlying the semiconductor substrate and the shallow trench isolation structure, between
the dummy gate electrode structure and the resistor structure;

concurrently patterning end terminal recesses for the resistance element through the dummy layer of the resistor structure
and removing the dummy layer of the dummy gate electrode structure to form a gate electrode recess, wherein concurrently patterning
the end terminal recesses and removing the dummy layer of the dummy gate electrode structure comprises masking a first region
of the resistor structure with a first mask, wherein entire second regions of the resistor structure on either side of the
first region remain unmasked and wherein portions of the interlayer dielectric layer adjacent to the second regions also remain
unmasked; and

depositing metal gate material in the end terminal recesses and the gate electrode recess to form end terminals for the resistance
element and a gate electrode, respectively.

US Pat. No. 10,134,459

MRAM WITH METAL-INSULATOR-TRANSITION MATERIAL

GLOBALFOUNDRIES SINGAPORE...

1. A memory cell comprising:a first selector having a first gate coupled to a word line (WL) and first selector first and second source/drain (S/D) regions;
a second selector having a second gate coupled to the WL and second selector first and second S/D regions, wherein the first selector and the second selector second S/D regions are coupled to a source line (SL);
a storage element which comprises a magnetic tunnel junction (MTJ) element having first and second MTJ terminals, the first MTJ terminal is coupled to the first selector and the second selector first S/D regions and the second MTJ terminal is coupled to a bit line (BL); and
a voltage control switch, wherein the voltage control switch,
during a write operation, causes the first selector to be on, and
during a read operation, causes the first selector to be off and the second selector to be on.

US Pat. No. 9,865,801

INTEGRATED CIRCUITS WITH MAGNETIC TUNNEL JUNCTIONS AND METHODS FOR PRODUCING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method of producing an integrated circuit comprising:
forming a fixed layer overlying a substrate, wherein the fixed layer comprises a magnetic material;
forming a first tunnel barrier layer overlying the fixed layer, wherein the first tunnel barrier layer is non-magnetic;
forming a total free layer comprising a first free layer overlying the first tunnel barrier layer, wherein the first free
layer comprises one or more of cobalt, iron, and boron, a first spacer layer overlying the first free layer, and a second
free layer overlying the first spacer layer, wherein the first spacer layer is non-magnetic and comprises a first spacer boron
sink material, wherein a boride formation enthalpy of the first spacer boron sink material is lower than the boride formation
enthalpy of cobalt; and

annealing the integrated circuit such that a boron concentration of the first free layer decreases and a boride concentration
of the first spacer layer increases during the anneal.

US Pat. No. 9,653,365

METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH LOW, MEDIUM, AND/OR HIGH VOLTAGE TRANSISTORS ON AN EXTREMELY THIN SILICON-ON-INSULATOR SUBSTRATE

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating an integrated circuit comprising:
providing or obtaining an extremely thin silicon-on-insulator (ETSOI) substrate;
dividing the ETSOI substrate into a low voltage field effect transistor (FET) region and a medium voltage FET region; and
forming a low voltage FET within the low voltage FET region, and forming a medium voltage FET within the medium voltage FET
region,

wherein, channel, source, and drain structures of the low voltage FET are formed in an upper silicon layer of the ETSOI substrate
that is disposed above a buried oxide layer of the ETSOI substrate,

wherein channel, source, and drain structures of the medium voltage FET are formed at least partially below the upper silicon
layer, and wherein:

the ETSOI substrate comprises a silicon base layer, the buried oxide (BOX) insulating layer, which is disposed over and in
contact with the silicon base layer, and the upper silicon layer, which is disposed over and in contact with the BOX insulating
layer, wherein the upper silicon layer has a thickness above the BOX insulating layer of about 3 nm to about 20 nm; and

forming the low and medium voltage FETs comprises:
forming a plurality of first shallow trench isolation (STI) structures in the ETSOI substrate, the first STI structures dividing
the ETSOI substrate into a low voltage field effect transistor (FET) region and a medium voltage FET region;

forming first and second masking layer segments over the ETSOI substrate, the first masking layer segment comprising a segment
formed over an entirety of the low voltage FET region, the second masking layer segment comprising two spaced apart segments
formed over the medium voltage FET region;

removing portions of the upper silicon layer and the BOX insulating layer that are not beneath the first and second masking
layer segments, thereby forming two first stacks comprising segments of the BOX insulating layer and the upper silicon layer
in the medium voltage FET region;

forming a polycrystalline silicon layer within the medium voltage FET region between and adjacent to the two first stacks,
the polycrystalline silicon layer being formed to a height commensurate with the upper silicon layer;

removing the first and second masking layer segments from over the ETSOI substrate;
forming source and drain ion implant regions within the medium voltage FET region, wherein forming the source and drain ion
implant regions in the medium voltage FET region comprises forming the source and drain ion implant regions adjacent to and
underneath the two first stacks;

oxidizing the segments of the upper silicon layer in the two first stacks;
masking the medium FET region while forming a first gate electrode structure over the low voltage FET region, thereby forming
a low voltage FET over the ETSOI; and

un-masking the medium voltage FET region then forming a second gate structure over the medium voltage FET region, thereby
forming a medium voltage FET over the ETSOI.

US Pat. No. 9,543,502

SMALL PITCH AND HIGH DENSITY CONTACT ARRAY

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming high density contact array comprising:
providing a first dielectric layer;
forming a hard mask stack over the first dielectric layer, wherein the hard mask stack comprises first, second and third hard
mask layers having materials with mutual etch selectivity with each other and wherein the third hard mask layer is formed
over the first dielectric layer while the second hard mask layer is formed in between the first and third hard mask layers;

processing the first and second hard mask layers to form high density array of hard mask stack structures by performing a
double patterning process, wherein the hard mask stack structures include patterned first and second hard mask layers having
a first width F1;

reducing the width of the patterned second hard mask layers to a second width F2 to form high density array of hard mask posts;

forming a fourth hard mask layer over the third hard mask layer and surrounding the hard mask posts; and
removing the hard mask posts and portions of the third hard mask layer and first dielectric layer underlying the hard mask
posts to form high density contact hole array.

US Pat. No. 9,343,571

MOS WITH RECESSED LIGHTLY-DOPED DRAIN

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:
a substrate having a surface;
a gate region on the substrate surface;
a recess in the substrate on each side of the gate region;
a source/drain region in the substrate, below each recess;
a spacer on each side of the gate region and extending down into the recess;
a second gate region on the substrate surface; and
a second source/drain region extending downward from the substrate surface, on each side of the second gate region, wherein:
the second source/drain region is positioned higher in the substrate surface than the first source/drain region, and
the gate region has a first uppermost surface and the second gate region has a second uppermost surface, and the first and
second uppermost surfaces are at substantially the same height.

US Pat. No. 9,305,886

INTEGRATED CIRCUITS HAVING CRACK-STOP STRUCTURES AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method for fabricating an integrated circuit, the method comprising:
fabricating a crack-stop structure extending through a plurality of metallization layers above a semiconductor substrate,
wherein the plurality of metallization layers comprises a first metallization layer and a second metallization layer that
overlies the first metallization layer, and wherein fabricating the crack-stop structure comprises:

forming a first via-bar overlying and coupled to a first metal line of the first metallization layer that is disposed in a
first ILD layer of dielectric material, wherein the first via-bar is disposed in a second ILD layer of dielectric material
and has a first width; and

forming a second metal line of the second metallization layer overlying and coupled to the first via-bar, wherein the second
metallization layer is disposed in the second ILD layer, wherein the second metal line has a second width that is from about
1 to about 5 times the first width, and wherein forming the first via-bar comprises forming the first via-bar gouging into
the first metal line a depth of about 50 Å or greater, wherein forming the first via-bar and the second metal line comprises:

forming a liner in a via-bar trench and a metal line trench, wherein forming the liner comprises:
depositing a liner-forming material to form a liner layer in the via-bar trench and the metal line trench; and
etching back portions of the liner layer using an ion bombardment dry etching process so as to drive the liner-forming material
into first metal line; and

depositing a conductive metal fill in the via-bar trench and the metal line trench overlying the liner.

US Pat. No. 9,837,334

PROGRAMMABLE ACTIVE COOLING DEVICE

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit (IC) comprising:
a single silicon-on-insulator (SOI) substrate comprises a top surface layer facing an upward direction, a support substrate
serving as a base of the single SOI substrate and an insulator layer isolating the top surface layer from the support substrate;

at least one device disposed in the top surface layer of the single SOI substrate;
a cooling device comprises a doped layer disposed in a top surface of the support substrate; and
a RDL layer disposed within the support substrate below the doped layer for providing connections to hotspots in the doped
layer to facilitate thermoelectric conduction of heat in the hotspots away from the IC.

US Pat. No. 9,666,640

HIGH THERMAL BUDGET MAGNETIC MEMORY

GLOBALFOUNDRIES SINGAPORE...

18. A storage unit of a magnetic memory cell comprising:
a bottom electrode;
a fixed layer disposed on the bottom electrode, wherein the fixed layer comprises
a composite spacer layer disposed on the bottom electrode, wherein the composite spacer layer comprises
a base layer, and
an amorphous buffer layer disposed over the base layer, and
a reference layer on the composite spacer layer, wherein the amorphous buffer layer serves as a template for the reference
layer to have a desired crystalline structure in a desired orientation;

at least one tunneling barrier layer disposed over the fixed layer;
a storage layer disposed over the tunneling barrier layer; and
a top electrode disposed over the storage layer.

US Pat. No. 9,581,506

METHODS FOR EVALUATING STRAIN OF CRYSTALLINE DEVICES

GLOBALFOUNDRIES SINGAPORE...

1. A method of evaluating a strain of a crystalline structure comprising:
directing an electron beam at the crystalline structure to produce an electron diffraction pattern, wherein the electron diffraction
pattern comprises a reflection point area;

detecting the electron diffraction pattern with a detector comprising a plurality of pixels to produce a raw data set;
filtering the raw data set by applying a mathematical median filter to produce a filtered data set;
enhancing a contrast of the filtered data set to produce an enhanced data set;
determining a center point of the reflection point area with the enhanced data set; and
determining the strain of the crystalline structure based on analysis of the center point.