US Pat. No. 9,059,037

METHODS FOR OVERLAY IMPROVEMENT THROUGH FEED FORWARD CORRECTION

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
obtaining a device after at least one laser annealing process is completed, the device including a substrate surface and at
least one layer over the substrate surface;

performing lithography on the at least one layer;
positioning a first contact-to-gate layer over the at least one layer;
checking alignment of electrical connections between the substrate surface and the first contact-to-gate layer;
determining if an overlay error is present;
adjusting at least one subsequent fabrication process;and
determining a rework threshold for use in adjusting the at least one subsequent fabrication process;
wherein the overlay error and the rework threshold are used to determine an overlay correction.

US Pat. No. 9,396,950

LOW THERMAL BUDGET SCHEMES IN SEMICONDUCTOR DEVICE FABRICATION

GLOBALFOUNDRIES Inc., Gr...

1. A method of fabricating a semiconductor device, comprising:
providing a gate structure over a semiconductor substrate;
performing a pre-amorphization implant process for forming amorphous regions adjacent said gate structure;
performing a first implantation process for forming source/drain extension regions entirely in said amorphous regions;
performing a second implantation process for forming source/drain regions entirely in said amorphous regions; and
performing a rapid thermal anneal process after forming of said source/drain regions, wherein no process step performed between
providing said gate structure and performing said rapid thermal anneal process has a temperature greater than 450° C.

US Pat. No. 9,219,013

TECHNIQUE FOR MANUFACTURING SEMICONDUCTOR DEVICES COMPRISING TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming field effect transistors with different threshold voltages, the method comprising:
forming a first gate electrode structure on a first semiconductor region;
forming a second gate electrode structure on a second semiconductor region;
performing a first implantation sequence comprising at least a source and drain extension implantation and a first halo implantation
in said first and second semiconductor regions;

forming a mask above said first semiconductor region;
performing a second implantation sequence comprising at least a second halo implantation in said second semiconductor region
to increase the threshold voltage of a field effect transistor to be formed in and above said second semiconductor region;
and

removing said mask.

US Pat. No. 9,590,118

WAFER WITH SOI STRUCTURE HAVING A BURIED INSULATING MULTILAYER STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE

GLOBALFOUNDRIES Inc., Gr...

1. A semiconductor device structure, comprising:
an SOI substrate comprising a semiconductor base substrate material, a buried insulating structure formed on said base substrate
material, and a semiconductor film formed on said buried insulating structure, wherein said buried insulating structure comprises
a multilayer stack having a nitride layer interposed between two oxide layers;

a semiconductor device formed in and above an active region of said SOI substrate, comprising:
a gate structure;
raised source/drain regions located at opposing sides of said gate structure; and
a silicide contact region defined in said base substrate material below said semiconductor device;
a nitride material layer disposed above said semiconductor device and at least a portion of said silicide contact region,
a contact dielectric disposed above said nitride material layer, and
a back bias contact at least partially disposed in said contact dielectric and being electrically connected to said silicide
contact region.

US Pat. No. 9,165,840

SEMICONDUCTOR STRUCTURE INCLUDING A SEMICONDUCTOR-ON-INSULATOR REGION AND A BULK REGION, AND METHOD FOR THE FORMATION THEREOF

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
providing a structure comprising a semiconductor substrate, a semiconductor layer provided above said semiconductor substrate
and a dielectric layer provided between said semiconductor substrate and said semiconductor layer;

removing portions of said semiconductor layer and said dielectric layer in a first part of said structure so that said semiconductor
substrate is exposed in said first part of said structure, wherein portions of said dielectric layer and said semiconductor
layer in a second part of said structure remain on said semiconductor substrate;

forming a semiconductor region comprising first, second and third layers of semiconductor material above said exposed semiconductor
substrate in said first part of said structure, said third semiconductor material comprising an upper surface lying in substantially
the same plane as the upper surface of said semiconductor layer;

forming a first transistor in said second part of said structure, said first transistor comprising an active region provided
in said portion of said semiconductor layer in said second part of said structure;

forming a trench isolation region providing electrical isolation between said portion of said semiconductor layer in said
second part of said structure and said first part of said structure; and

wherein said trench isolation region is formed before said portions of said semiconductor layer and said dielectric layer
in said first part of said structure are removed.

US Pat. No. 9,293,461

REPLACEMENT METAL GATE STRUCTURES FOR EFFECTIVE WORK FUNCTION CONTROL

GLOBALFOUNDRIES INC., Gr...

1. A semiconductor structure comprising:
a first field effect transistor and a second field effect transistor that are located on a semiconductor substrate comprising
a semiconductor material, wherein said first field effect transistor comprises:

a first gate dielectric located over a first portion of said semiconductor substrate;
a first barrier metal portion contacting said first gate dielectric;
a first-type work function metal portion comprising a first metal having a first work function and contacting said first barrier
metal portion; and

a first second-type work function metal portion comprising a second metal having a second work function and contacting said
first-type work function metal portion, wherein one of said first and second work functions is closer to a conduction band
of said semiconductor material of said semiconductor substrate than a valence band of said semiconductor material of said
semiconductor substrate, and the other of said first and second work functions is closer to said valence band than to said
conduction band,
and wherein said second field effect transistor comprises:
a second gate dielectric located over a second portion of said semiconductor substrate;
a second barrier metal portion contacting said second gate dielectric; and
a second second-type work function metal portion comprising said second metal and contacting said second barrier metal portion;
a first type stress-generating layer located adjacent to said first field effect transistor;
a second type stress-generating layer located adjacent to said second field effect transistor;
a planarization dielectric layer located above portions of said first and second type stress-generating layers;
first contact via structures extending through portions of said planarization dielectric layer and said first type stress-generating
layer; and

second contact via structures extending through portions of said planarization dielectric layer and said second type stress-generating
layer, wherein said first and said second contact via structures have a topmost surface that is coplanar with topmost surfaces
of said planarization dielectric layer, said first and second type stress-generating layers, said first gate dielectric, said
first barrier metal portion, said first-type work function metal portion, and said first second-type work function metal portion,
said second gate dielectric, said second barrier metal portion, and said second second-type work function metal portion.

US Pat. No. 9,300,555

PEER-TO-PEER AD HOC NETWORK SYSTEM FOR MONITORING A PRESENCE OF MEMBERS OF A GROUP

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:
forming a peer-to-peer ad hoc network comprising one or more groups, each of the one or more groups comprising a plurality
of members;

monitoring, by the plurality of members, a presence of each of the plurality of members in the group, wherein each of the
plurality of members are configured to detect an absence of one of the plurality of members from the group;

based on detecting a missing member of the one or more groups, generating, by a processor of one of the plurality of members,
a notification of the missing member; and

transmitting an alert to a supervisor corresponding to the missing member in response to the notification of the missing member
and wherein the alert comprises a last time that the one of the plurality of members absent from the group communicated with
another member of the group.

US Pat. No. 9,064,890

METHODS OF FORMING ISOLATION MATERIAL ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES

GLOBALFOUNDRIES Inc., Gr...

15. A FinFET device comprised of source/drain regions, comprising:
a substrate comprised of a semiconductor material;
a gate structure positioned above said substrate;
sidewall spacers positioned adjacent said gate structure;
an epi semiconductor material positioned in said source/drain regions of said FinFET device laterally outside of said sidewall
spacers;

a fin that extends laterally under said gate structure and said sidewall spacers in a gate length direction of said FinFET
device, wherein end surfaces of said fin abut and engage said epi semiconductor material, and

an insulating material that is positioned below said fin, above said substrate and laterally between said epi semiconductor
material, wherein a top surface of said insulating material abuts and engages a bottom surface of said fin, a bottom surface
of said insulating material abuts and engages said substrate, and side surfaces of said insulating material abut and engage
at least a portion of said epi semiconductor material.

US Pat. No. 9,224,091

LEARNING ARTIFICIAL NEURAL NETWORK USING TERNARY CONTENT ADDRESSABLE MEMORY (TCAM)

GLOBALFOUNDRIES INC., Gr...

1. A circuit comprising:
one or more ternary content addressable memory (TCAM) arrays comprising one or more matchlines configured to model a neural
network, wherein each of the one or more TCAM arrays models a connected group of neurons such that input search data into
the one or more matchlines is modeled as neuron dendrite information, and output from the one or more matchlines is modeled
as neuron axon information;

one or more additional bits included within each of the one or more matchlines that are configured to model connectivity strength
between each neuron dendrite and axon; and

a real-time learning block included within each of the one or more TCAM arrays configured to modify the connectivity strength
between each neuron dendrite and axon using wild-cards written and stored in the one or more additional bits.

US Pat. No. 9,147,748

METHODS OF FORMING REPLACEMENT SPACER STRUCTURES ON SEMICONDUCTOR DEVICES

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a transistor device, comprising:
forming a structure above a semiconductor substrate, said structure comprising a sacrificial gate structure, a first gate
cap layer positioned above said sacrificial gate structure and first sidewall spacers positioned adjacent said sacrificial
gate structure;

performing at least one etching process to remove said first sidewall spacers and said first gate cap layer so as to thereby
expose an upper surface and sidewalls of said sacrificial gate structure;

forming an etch stop layer above source/drain regions of said device and on said sidewalls and said upper surface of said
sacrificial gate structure;

forming a first layer of insulating material above said etch stop layer;
removing said sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of
said etch stop layer;

forming a replacement gate structure in said replacement gate cavity;
forming a second gate cap layer above said replacement gate structure;
forming a first contact opening that extends through at least said first layer of insulating material so as to thereby expose
at least a portion of said etch stop layer positioned on the sidewall of said replacement gate structure;

performing an isotropic etching process to clear said sidewall of said replacement gate structure of said etch stop layer;
after performing said isotropic etching process, forming a spacer in said first contact opening; and
forming a first conductive contact in said first contact opening.

US Pat. No. 9,184,095

CONTACT BARS WITH REDUCED FRINGING CAPACITANCE IN A SEMICONDUCTOR DEVICE

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
forming a metal-containing electrode material layer so as to line sidewall and bottom surfaces of a gate opening formed in
a gate electrode structure of a transistor of a semiconductor device;

after forming said metal-containing electrode material layer, forming a contact opening so as to expose a contact area of
at least one of a drain region and a source region of said transistor and a sidewall surface of a sidewall spacer positioned
adjacent to said gate electrode structure, wherein forming said contact opening comprises selectively removing a portion of
a first interlayer dielectric material with respect to at least said sidewall surface of said sidewall spacer, said contact
opening being self-aligned with respect to at least said sidewall surface of said sidewall spacer;

completely filling said contact opening and said gate opening with a contact metal during a same material deposition step,
wherein said contact metal completely filling said contact opening and said gate opening is deposited on and in direct contact
with said exposed contact area and said exposed sidewall surface of said sidewall spacer;

removing excess material of said conductive material so as to form at least one contact bar, wherein said contact bar is self-aligned
with respect to said sidewall spacer element; and

forming a second interlayer dielectric material above said first interlayer dielectric material and said contact bar.

US Pat. No. 9,293,520

METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE

GLOBALFOUNDRIES INC., Gr...

1. A semiconductor structure comprising:
a material stack comprising an n-type semiconductor layer on a base semiconductor layer, a dielectric layer on the n-type
semiconductor layer, and an upper semiconductor layer present on the dielectric layer;

a capacitor present in a capacitor trench and extending from the upper semiconductor layer through the dielectric layer into
contact with the n-type semiconductor layer, wherein the capacitor comprises a node dielectric present on the sidewalls of
the capacitor trench and an upper electrode filling at least a portion of the capacitor trench;

a substrate contact present in a contact trench and extending from the upper semiconductor layer through the dielectric layer
and the n-type semiconductor layer to a p-type doped region of the base semiconductor layer; and

an isolation trench extending from the upper semiconductor layer through the dielectric layer and the n-type semiconductor
layer and into, and in direct contact with, the base semiconductor layer, wherein the isolation trench is located between
the capacitor trench and the contact trench, wherein the isolation trench includes a dielectric material on opposing sidewalls
of the isolation trench and on a base portion of the isolation trench, and wherein a bottom surface of the isolation trench
is lower than a bottom surface of the contact trench and a bottom surface of the capacitor trench.

US Pat. No. 9,202,758

METHOD FOR MANUFACTURING A CONTACT FOR A SEMICONDUCTOR COMPONENT AND RELATED STRUCTURE

GLOBALFOUNDRIES Inc., Gr...

1. A method for manufacturing a semiconductor component, comprising:
providing a semiconductor material;
forming a layer of silicon nitride directly on the semiconductor material;
forming a layer of dielectric material directly on the layer of silicon nitride using Sub-Atmospheric Chemical Vapor Deposition
(SACVD), the layer of dielectric material comprising doped silicate glass;

forming a contact hole in the layer of dielectric material, the contact hole having sidewalls and exposing a portion of the
semiconductor material; and

forming a layer of tungsten nitride in the contact hole and on the exposed portion;
wherein all processing temperatures for manufacturing the semiconductor component are less than about 450 degrees Celsius;
wherein forming the layer of dielectric material includes using ozone as a carrier gas.

US Pat. No. 9,136,266

GATE OXIDE QUALITY FOR COMPLEX MOSFET DEVICES

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a semiconductor device, comprising:
forming a silicon germanium layer on a surface of a semiconductor substrate, the silicon germanium layer having an upper surface;
forming at least one insulating material layer on an entire upper surface of said silicon germanium layer;
thereafter performing an annealing process;
removing said at least one insulating material layer for exposing the entire upper surface of said silicon germanium layer;
and

forming a gate dielectric material layer on said exposed the entire upper surface of said silicon germanium layer.

US Pat. No. 9,214,360

METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
forming a layer of material above a semiconductor substrate;
forming a masking layer comprising a first plurality of features and a second plurality of features above said layer of material,
wherein forming said masking layer comprises:

forming a plurality of first mandrels above a first region of said semiconductor substrate and a plurality of second mandrels
above a second region of said semiconductor substrate;

forming a first spacer on opposing sidewalls of each of said pluralities of first and second mandrels, wherein said first
spacers formed above said first region comprise said first plurality of features;

removing each of said pluralities of first and second mandrels from above said respective first and second regions selectively
to said first spacers; and

after removing said pluralities of first and second mandrels, selectively forming a plurality of combined spacers above said
second region by forming a second spacer on opposing sidewalls of each of said first spacers formed above said second region,
said plurality of combined spacers comprising said second plurality of features, wherein said first plurality of features
and said second plurality of features have a same pitch spacing and wherein said first plurality of features and second plurality
of features have different widths; and

performing at least one etching process on said layer of material through said masking layer.

US Pat. No. 9,218,976

FULLY SILICIDED GATE FORMED ACCORDING TO THE GATE-FIRST HKMG APPROACH

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a transistor, the method comprising:
forming a gate structure above an active region formed in a semiconductor layer, wherein said gate structure comprises a gate
insulating layer comprising a high-k material, a gate metal layer comprising a work function metal species formed on and in
contact with an upper surface of said gate insulating layer, a gate material formed on and in contact with an upper surface
of said gate metal layer, and an insulating cap layer formed above said gate material;

after forming said gate structure, forming source and drain regions of said transistor in said active region;
forming a first metal silicide layer having an interface with said source and drain regions;
after forming said first metal silicide layer, removing said insulating cap layer from said gate structure so as to expose
said gate material; and

after exposing said gate material, forming a second metal silicide layer in said gate structure, said second metal silicide
being formed so as to completely replace said gate material and to form an interface with said gate metal layer.

US Pat. No. 9,147,618

METHOD FOR DETECTING DEFECTS IN A DIFFUSION BARRIER LAYER

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:
providing a semiconductor structure comprising a diffusion barrier layer formed above a dielectric material and a seed layer
provided on said diffusion barrier layer, said seed layer comprising an alloy of copper and a metal other than copper;

depositing an electrically conductive material comprising copper on said seed layer;
performing an annealing process after depositing said electrically conductive layer, wherein at least a first portion of said
metal other than copper diffuses away from a vicinity of said diffusion barrier layer through said electrically conductive
material, and wherein, in case of a defect in said diffusion barrier layer, a second portion of said metal other than copper
indicative of said defect is present in said dielectric material in a vicinity of said defect in said diffusion barrier layer
at a higher concentration relative to other portions of said dielectric material in the vicinity of said diffusion barrier
without said defect;

measuring a distribution of said metal other than copper in at least a portion of said semiconductor structure; and
determining, from said measured distribution of said metal other than copper, if said second portion of said metal other than
copper is present in said dielectric material at said higher concentration in a vicinity of said diffusion barrier layer to
identify said defect.

US Pat. No. 9,281,397

SEMICONDUCTOR DEVICE INCLUDING AN ASYMMETRIC FEATURE

GLOBALFOUNDRIES INC., Gr...

1. A semiconductor device having an asymmetric feature, the device comprising:
a first gate formed on a substrate;
first and second diffusion regions formed in the substrate on a side of the first gate;
first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric
with respect to the second contact;

a first FET comprising the first and second diffusion regions, first gate and first and second contacts;
a second FET formed on the substrate adjacent to the first FET and including a second gate formed on the substrate third and
fourth diffusion regions formed in the substrate on a side of the second gate, and third and fourth contacts which contact
the third and fourth diffusion regions, respectively; and

a third FET formed on the substrate adjacent to the second FET, the third FET including a third ate formed on the substrate
fifth and sixth diffusion regions formed in the substrate on a side of the third gate, and fifth and sixth contacts which
contact the fifth and sixth diffusion regions, respectively,

wherein a pitch between the first and second gates comprises a first pitch and a pitch between the second and third gates
comprises a second pitch which is different from the first pitch.

US Pat. No. 9,223,510

OPTIMIZING STORAGE UTILIZATION BY MODIFYING A LOGICAL VOLUME OFFSET

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:
arranging, by a host processor, a first multiple of storage slices having multiple physical regions to store a second multiple
of logical volumes;

assigning a respective offset to each of the logical volumes;
configuring each the logical volumes to start storing data at a first of the storage slices indicated by the assigned respective
offset;

subsequent to configuring each of the logical volumes, identifying, by the host processor, one the storage slices having a
highest storage utilization; and

reconfiguring one of the logical volumes having a highest number of the physical regions in the identified one of the storage
slices to start storing the data at a second of the storage slices.

US Pat. No. 9,218,994

TWO-DIMENSIONAL TRANSFER STATION USED AS INTERFACE BETWEEN A PROCESS TOOL AND A TRANSPORT SYSTEM AND A METHOD OF OPERATING THE SAME

GLOBALFOUNDRIES Inc., Gr...

1. A method of exchanging transport carriers between an automated transport system and a process tool of a manufacturing environment,
the method comprising:
supplying a first substrate carrier to a first transfer place of a two-dimensional array of transfer places, each of said
transfer places being accessible by a vehicle of said automated transport system, wherein said automated transport system
comprises first and second rails configured to convey the vehicle to different subsets of the transfer places of said two-dimensional
array;

transferring said first substrate carrier to a first one of a plurality of load ports of said process tool, wherein the number
of said plurality of buffer places is higher than the number of said plurality of load ports;

transferring a second substrate carrier from a second one of said plurality of load ports to said first transfer place of
said two-dimensional array; and

picking up said second transport carrier from said first transfer place by a vehicle of said automated transport system.

US Pat. No. 9,281,200

ENHANCED PATTERNING UNIFORMITY OF GATE ELECTRODES OF A SEMICONDUCTOR DEVICE BY LATE GATE DOPING

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a semiconductor device, the method comprising:
forming a gate layer stack above a first active region and a second active region, said gate layer stack comprising a semiconductor
electrode material having a uniform material composition;

forming a first gate electrode structure above said first active region and a second gate electrode structure above said second
active region from said gate layer stack;

forming a mask material laterally adjacent to said first and second gate electrode structures so as to cover said first and
second active regions;

forming a patterned implantation mask above said mask material, said patterned implantation mask covering said second gate
electrode structure and exposing said first gate electrode structure;

implanting a dopant species selectively into said semiconductor electrode material of said first gate electrode structure
through said patterned implantation mask and in the presence of said mask material;

removing said patterned implantation mask and said mask material from above said first and second active regions during a
same material removal process; and performing an anneal process so as to distribute said dopant species.

US Pat. No. 9,275,868

UNIFORM ROUGHNESS ON BACKSIDE OF A WAFER

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:
forming a material on a backside of a wafer, wherein the backside is adapted to be part of a base of a semiconductor and an
upper surface of the wafer is adapted to be in contact with semiconductor layers;

patterning the material to expose portions of the backside of the wafer; and
roughening the backside of the wafer through the patterned material to form a uniform roughness comprising a repeating array
of structures of recesses or indentations in the backside of the wafer thus forming a controlled topography.

US Pat. No. 9,491,875

FOOT PAD STRUCTURE FOR AN APPARATUS

GLOBALFOUNDRIES INC., Gr...

1. A foot pad structure, adapted for a device housing, comprising:
a supporting pad; and
an engaging shell for containing the supporting pad, wherein at least one engaging component is disposed on an outer surface
of the engaging shell and is adapted for engaging with the device housing to fix the engaging shell to the device housing,

wherein the engaging shell comprises a plate and a flange extending from a periphery of the plate to define a supporting pad
containing region,

wherein a plurality of slots are provided to a lower part of the flange, said lower part of the flange being distal of the
plate, and

wherein the lower part of the flange deforms and retracts by the plurality of slots when forces are exerted on the lower part
of the flange, to facilitate engagement of the engaging shell to the device housing and disengagement of the engaging shell
from the device housing.

US Pat. No. 9,398,730

FLUID-COOLED ELECTRONIC CIRCUIT DEVICE WITH COOLING FLUID CONDUITS HAVING OPTICAL TRANSMISSION MEDIUM

GLOBALFOUNDRIES INC., Gr...

1. An electronic circuit device, comprising a combined optical transmission and cooling fluid conduit network, wherein the
network comprises at least one cooling conduit that comprises an optical transmission medium, wherein the network is configured
to convey:
a cooling fluid via the at least one cooling conduit, the network being in thermal communication with a first set of components
of the electronic circuit device; and

an electromagnetic signal via the optical transmission medium, the network being in thermal communication and signal communication
with a second set of one or more components of the electronic circuit device, wherein the first set and second set of components
at least partly overlap.

US Pat. No. 9,263,537

METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE

GLOBALFOUNDRIES Inc., Gr...

1. A transistor device, comprising:
a gate structure positioned above a semiconductor substrate;
a spacer structure positioned adjacent said gate structure;
a layer of insulating material positioned above said substrate and around said spacer structure;
a first gate cap protection layer positioned on said gate structure, said spacer structure and portions of said layer of insulating
material;

a gate cap layer positioned on said first gate cap protection layer, wherein sidewalls and a bottom surface of said gate cap
layer each contact said first gate cap protection layer; and

a second gate cap protection layer positioned on an upper surface of said gate cap layer, wherein said first and second gate
cap protection layers encapsulate said gate cap layer.

US Pat. No. 9,236,440

SANDWICH SILICIDATION FOR FULLY SILICIDED GATE FORMATION

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a transistor, the method comprising:
forming an active region in a semiconductor layer; and
forming a gate structure on said active region, wherein forming said gate structure comprises:
forming an insulating layer on said active region;
forming a gate metal layer on said insulating layer, wherein said gate metal layer does not comprise silicon-based or metal
silicide materials;

forming a first metal layer on said gate metal layer, wherein said first metal layer does not comprise silicon-based or metal
silicide materials;

forming a gate material layer on said first metal layer; and
performing a salicidation process to form a first metal silicide layer above said gate metal layer and to form a second metal
silicide layer above said first metal silicide layer, said salicidation process comprising:

depositing a refractory metal layer above said transistor after forming said gate structure; and
applying a heat treatment to form said second metal silicide layer from at least a portion of said refractory metal layer
and at least a portion of said gate material layer.

US Pat. No. 9,230,564

METHODS FOR FABRICATING MAGNETIC TRANSDUCERS USING POST-DEPOSITION TILTING

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:
forming a thin film magnetic transducer structure on a substantially planar portion of a substrate such that a plane of deposition
of the thin film magnetic transducer structure is substantially parallel to a plane of the substrate; and

causing the thin film transducer structure to tilt at an angle relative to the plane of the substrate, wherein the thin film
magnetic transducer structure is fixed at the angle after being tilted, wherein the angle is in a range from greater than
0 degrees to less than or equal to 90 degrees; and

removing a sacrificial portion of the substrate for causing the thin film magnetic transducer structure to pivot.

US Pat. No. 9,105,507

METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE WITH UNDOPED FINS

GLOBALFOUNDRIES Inc., Gr...

1. A FinFET device, comprising:
a plurality of fin structures positioned in and above a semiconducting substrate, each of said plurality of fin structures
comprising:

a first portion of said semiconducting substrate;
an undoped layer of semiconducting material positioned above said first portion of said semiconducting substrate; and
a dopant-containing layer of semiconducting material positioned between said first portion of said semiconducting substrate
and said undoped layer of semiconducting material, wherein said dopant-containing layer of semiconducting material is adapted
to retard diffusion of one of boron and phosphorous; and

a gate electrode positioned around at least said undoped layer of semiconducting material comprising each of said plurality
of fin structures, wherein a height level of a bottom surface of said gate electrode is positioned approximately level with
or lower than a height level of a bottom of said undoped layer of semiconducting material comprising each of said plurality
of fin structures.

US Pat. No. 9,245,824

THROUGH-VIAS FOR WIRING LAYERS OF SEMICONDUCTOR DEVICES

GLOBALFOUNDRIES INC., Gr...

1. A method for forming a through-via in a semiconductor device comprising:
performing a first etching through at least a first dielectric material of a wiring layer of the semiconductor device to expose
a semiconductor material of a semiconductor layer below said wiring layer, said first etching forming a first hole outlining
a collar structure for the through-via;

depositing a porous stress-abating dielectric material in the first hole such that the stress-abating dielectric material
forms the collar structure and extends between the semiconductor layer to a top surface of the wiring layer;

performing a second etching through at least the semiconductor layer, said second etching forming a via hole in the semiconductor
material; and

filling at least a portion of said via hole with conductive material to form the through-via such that said stress-abating
dielectric material, at least in said wiring layer, provides a buffer between said conductive material and said first dielectric
material.

US Pat. No. 9,472,670

FIELD EFFECT TRANSISTOR DEVICE SPACERS

INTERNATIONAL BUSINESS MA...

1. A method for forming field effect transistors, the method comprising:
forming a first fin and a second fin on an insulator layer of a substrate;
forming a first dummy gate stack over the first fin;
forming a second dummy gate stack over the second fin;
forming a first layer of spacer material over the first fin, the second fin, the first dummy gate stack, and the second dummy
gate stack;

patterning a first masking layer over the first layer of spacer material over the first fin and the first dummy gate stack;
removing exposed portions of the first layer of spacer material to form spacers adjacent to sidewalls of the second dummy
gate stack;

removing the first masking layer;
performing an epitaxial growth process to form a first epitaxially grown semiconductor material on exposed portions of the
second fin;

depositing an oxide layer over the first layer of spacer material, the first dummy gate stack, and the first epitaxially grown
semiconductor material;

forming a second layer of spacer material over the oxide layer;
patterning a second masking layer over the oxide layer over the second dummy gate stack and the first epitaxially grown semiconductor
material;

removing exposed portions of the second layer of spacer material;
removing exposed portions of the oxide layer;
removing exposed portions of the first layer of spacer material to form spacers adjacent to sidewalls of the first dummy gate
stack;

removing the second masking layer;
performing an epitaxial growth process to form a second epitaxially grown semiconductor material on exposed portions of the
first fin;

patterning a third masking layer over the second epitaxially grown semiconductor material and the first dummy gate stack;
removing exposed portions of the second layer of spacer material;
removing the third masking layer;
depositing a layer of insulator material over the first epitaxially grown semiconductor material, the second epitaxially grown
semiconductor material, the first dummy gate stack, and the second dummy gate stack;

removing a portion of the layer of insulator material to expose a portion of the first dummy gate stack and a portion of the
second dummy gate stack;

removing the first dummy gate stack and the second dummy gate stack to expose a channel region of the first fin and a channel
region of the second fin; and

forming a first gate stack over the channel region of the first fin and over the channel region of the second fin.

US Pat. No. 9,281,249

DECOUPLING MEASUREMENT OF LAYER THICKNESSES OF A PLURALITY OF LAYERS OF A CIRCUIT STRUCTURE

GLOBALFOUNDRIES Inc., Gr...

1. A method comprising:
obtaining a measurement of thickness of a plurality of layers of a circuit structure, the thickness of the plurality of layers
measured using an optical critical dimension (OCD) measurement technique, and the plurality of layers comprising a high-k
layer and an interfacial layer;

separately obtaining a measurement of thickness of the high-k layer, the thickness of the high-k layer measured using a separate
measurement technique from the OCD measurement technique and providing greater decoupling, as compared to the OCD measurement
technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer; and

ascertaining, by a hardware processor, a thickness of the interfacial layer using, in part, the separately obtained thickness
measurement of the high-k layer,

wherein the circuit structure comprises a fin field-effect transistor (FinFET) or a nanostructure, and wherein measurement
of the thickness of the plurality of layers using the OCD measurement technique and measurement of the thickness of the high-k
layer using the separate measurement technique are performed concurrently during fabrication of the FinFET or nanostructure.

US Pat. No. 9,400,863

COLOR-INSENSITIVE RULES FOR ROUTING STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:
designating each of a plurality of first routes extending horizontally in an integrated circuit (IC) design positions as one
of a plurality of colors, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical
positions of the IC design, wherein each of the first routes is generated according to a first design rule indicating a first
separation distance between routes designated as different colors and a second separation distance between routes designated
as same colors;

designating a second route as color insensitive based on whether the second route overlaps one of the vertical positions of
the plurality of equally spaced vertical positions;

generating the second route according to a second design rule indicating a third separation distance between the second route
and each route of the plurality of first routes without regard to a color designation; and

fabricating a semiconductor device comprising an integrated circuit containing the generated first and second routes.

US Pat. No. 9,392,731

COOLING APPARATUS WITH DYNAMIC LOAD ADJUSTMENT

GLOBALFOUNDRIES INC., Gr...

1. A method for cooling heat producing units, comprising:
using a device that includes:
a first thermal interface material (TIM) layer having a top surface and a bottom surface;
a first heat producing unit having a top surface in thermal contact with the bottom surface of a first portion of the first
TIM layer to facilitate heat transfer away from the first heat producing unit;

a second heat producing unit having a top surface in thermal contact with the bottom surface of a second portion the first
TIM layer to facilitate heat transfer away from the second heat producing unit;

a first heat sink column having a top surface and a bottom surface, the bottom surface of the first heat sink column in thermal
contact with the top surface of the first portion the first TIM layer;

a second heat sink column having a top surface and a bottom surface, the bottom surface of the second heat sink column in
thermal contact with the top surface of the second portion of the first TIM layer; and

a load plate having a bottom surface in thermal contact with the top surface of the first heat sink column and the top surface
of the second heat sink column, by:

exerting a compressive force on each heat sink column, by moving the load plate into a latched position;
conducting heat away from the first portion of the first TIM layer with the first heat sink column and away from the second
portion of the first TIM layer with the second heat sink column;

adjusting, using a thermal expansion of the first heat sink column in response to a first level of heat produced by the first
heat producing unit, a compression of the first portion the first TIM layer by a first amount; and

adjusting, using the thermal expansion of the second heat sink column in response to a second level of heat produced by the
second heat producing unit, the compression of the second portion of the first TIM layer by a second amount that is different
than the first amount.

US Pat. No. 9,281,236

EMBEDDED ON-CHIP SECURITY

GLOBALFOUNDRIES INC., Gr...

1. An integrated circuit comprising:
a reset input and a clock input;
a circular shift logic, for use in producing circularly shifting test patterns, wherein the
circular shift logic comprises the reset and clock input and one or more outputs and complement outputs, wherein the one or
more outputs are operatively connected with the reset input and the clock input, and wherein each output corresponds to a
complement output;

a plurality of n-channel metal-oxide-semiconductor field-effect transistors (nMOSFET),
wherein a nMOSFET comprises a gate, a source, and a drain, wherein the source is operatively connected with zero voltage,
the gate is operatively connected with an output of the circular shift logic, and the drain is operatively connected with
a conductive element of the randomly patterned interconnect structure; and

a plurality of p-channel metal-oxide-semiconductor field-effect transistors (pMOSFET),
wherein each pMOSFET corresponds to a nMOSFET, and wherein the pMOSFET is operatively connected with a conductive element
of the randomly patterned interconnect structure adjacent to the conductive element operatively connected with the corresponding
nMOSFET, and wherein a pMOSFET comprises a gate, a source, and a drain, wherein the source is operatively connected with a
voltage source, the gate is operatively connected with a complement output of the circular shift logic, and the drain is operatively
connected with a conductive element of the randomly patterned interconnect structure.

US Pat. No. 9,281,247

STRAINED SILICON AND STRAINED SILICON GERMANIUM ON INSULATOR FIELD-EFFECT TRANSISTOR

GLOBALFOUNDRIES INC., Gr...

1. A non-transitory computer readable medium for fabricating an integrated circuit structure, the computer readable medium
having program instructions embodied therewith, the program instructions readable by at least one information processing system
to cause the at least one information processing system to:
pattern a strained silicon layer formed on a dielectric layer of a substrate into at least one N-type field-effect transistor
(NFET) region comprising at least a first portion of the strained silicon layer;

pattern the strained silicon layer into at least one P-type field-effect transistor (PFET) region comprising at least a second
portion of the strained silicon layer;

form a masking layer over the first portion of the strained silicon layer;
transform, after forming the masking layer and while maintaining at least a top portion of the second portion of the strained
silicon layer exposed, the second portion of the strained silicon layer into a relaxed silicon layer;

epitaxially grow, after the second portion of the strained silicon layer has been transformed into the relaxed silicon layer,
a silicon germanium layer on the relaxed silicon layer; and

transform, while maintaining at least a top surface of the silicon germanium layer exposed, the relaxed silicon layer and
the silicon germanium layer into a strained silicon germanium layer.

US Pat. No. 9,280,463

SEMICONDUCTOR MEMORY GARBAGE COLLECTION

GLOBALFOUNDRIES INC., Gr...

1. An apparatus comprising:
an identification module that identifies a garbage collection time window for at least one block of a flash memory array and
determines a garbage collection level for the at least one block, wherein the garbage collection level is determined from
at least one of a free pages number and a partial pages number for each block;

a garbage collection module garbage that collects a first block of the flash memory array with a highest garbage collection
level and an open garbage collection time window; and

wherein at least a portion of the identification module and the garbage collection module comprise one or more of hardware
and program code, the program code stored on one or more computer readable storage media.

US Pat. No. 9,286,459

AUTHORIZED REMOTE ACCESS TO AN OPERATING SYSTEM HOSTED BY A VIRTUAL MACHINE

GLOBALFOUNDRIES INC., Gr...

1. A method for providing authorized remote access to an operating system hosted by a virtual machine (VM), the method comprising:
defining, at a client system, a first profile and a first key for a first user and a second profile and a second key for a
second user, the first profile and first key for the first user and the second profile and the second key for the second user
also being defined on a server system;

receiving, at the client system from the first user, a request for an initial program load (IPL) of an operating system hosted
by the VM, the VM being provided by a server system;

generating, at the client system, a first authentication token for the second user and a shut-down instruction for shutting
down the operating system, the first authentication token being generated based on the second key of the second user the second
user currently having access to the operation system;

communicating, by the client system, the first authentication token and the shut-down instruction to the server system, the
first authentication token being verifiable by the server system using the second key prior to execution of the shut-down
instruction on the server system to shut-down the operating system;

confirming, at the client system, the shut-down of the operating system;
in response to the confirming, generating, at the client system, a second authentication token for the first user and an IPL
instruction for restarting the operating system, the second authentication token being generated based on the first key of
the first user; and

communicating, by the client system, the second authentication token and the IPL instruction to the server system, the second
authentication token being verifiable by the server system using the first key prior to execution of the IPL instruction on
the server system to re-start the operating system.

US Pat. No. 9,295,166

DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:
obtaining a structure comprising:
a substrate including a plurality of recesses;
a plurality of electrically conductive contact pads within the recesses; and
a plurality of solder bumps, each solder bump including a first solder bump structure comprised of a first solder having a
first melting point, the first solder bump structure adjoining one of the contact pads and extending above a top surface of
the substrate, and a layer of second solder completely covering the first solder bump structure, the second solder having
a lower melting point than the first solder;

contacting electrically conductive elements of an integrated circuit chip with the solder bumps;
causing reflow of the layers of second solder, the first solder bump structures remaining solid during reflow of the layers
of second solder; and

causing the second solder to solidify such that the structure is attached to the integrated circuit chip;
further including filling a space between the integrated circuit chip and the substrate with underfill material.

US Pat. No. 9,288,211

PROVIDING ACCESS CONTROL FOR PUBLIC AND PRIVATE DOCUMENT FIELDS

GLOBALFOUNDRIES INC., Gr...

1. A method to control access to information, the method comprising:
a computer hardware generating a modified list of search terms by adding first additional search terms to a list of search
terms, wherein the first additional terms include synonyms of the search terms and terms that are related to the search terms;
the computer hardware removing frequently used words from the modified list of search terms; and

responsive to a determination that a user has authorization to view a first type of field of a first document, the computer
hardware adding to the modified list of search terms an encrypted version of a search term included in a list of search terms
such that execution of a search using the modified list of search terms returns a result that identifies the first document
as a search result when either the unencrypted or the encrypted version of the search term is found in a list of index terms
associated with the first document;

the computer hardware determining that a second type of field of a second document has restricted access, based on a second
degree of authorization of the user; the computer hardware generating a modified list of index terms by encrypting one or
more tokens occurring in the second type of field using a second set of encryption settings; and

the computer hardware executing an indexing step using the modified list of index terms.

US Pat. No. 9,252,238

SEMICONDUCTOR STRUCTURES WITH COPLANAR RECESSED GATE LAYERS AND FABRICATION METHODS

LAM RESEARCH CORPORATION,...

1. A method comprising:
fabricating a semiconductor structure, the fabricating comprising:
providing a gate structure over a semiconductor substrate, the gate structure comprising multiple conformal gate layers and
a gate material disposed within the multiple conformal gate layers;

recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, wherein upper surfaces
of the recessed, multiple conformal gate layers are coplanar; and

removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar
with an upper surface of the recessed, multiple conformal gate layers.

US Pat. No. 9,275,861

METHODS OF FORMING GROUP III-V SEMICONDUCTOR MATERIALS ON GROUP IV SUBSTRATES AND THE RESULTING SUBSTRATE STRUCTURES

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
forming a layer of insulating material above a surface of a semiconductor substrate;
performing a first etching process on said layer of insulating material to define a patterned layer of insulating material
that is comprised of isolation regions and a trench defined between said isolation regions with a plurality of isolated features
formed within said trench, wherein portions of said surface of said substrate within said trench are exposed;

performing at least one second etching process through said patterned layer of insulating material to define a plurality of
intersecting ridges that define a ridged surface in said substrate within said trench;

after forming said ridged surface in said substrate, performing a third etching process to remove said plurality of isolated
features within said trench; and

after removing said plurality of isolated features, forming a Group III-V material on said ridged surface of said substrate
within said trench between said isolation regions.

US Pat. No. 9,293,414

ELECTRONIC FUSE HAVING A SUBSTANTIALLY UNIFORM THERMAL PROFILE

GLOBALFOUNDRIES Inc., Gr...

1. An electronic fuse, comprising:
a body having a width and a length, and, along its width, a first end region, a second end region, and a central region disposed
between said first and second end regions;

an anode coupled to said body; and
a cathode coupled to said body and positioned parallel to and spaced apart from said anode in a length direction of said body,
wherein each of said anode and said cathode comprises:

a first line contacting said body, wherein said first line is discontinuous along its length and includes a first portion
and a second portion with a space therebetween, said first portion contacts said first end region and said central region,
and said second portion contacts said second end region and said central region;

a second line disposed above said first line; and
a plurality of vias coupling said first and second lines, wherein said first portion of said first line is coupled to a first
subset of said plurality of vias and said second portion of said first line is coupled to a second subset of said plurality
of vias not including vias in said first subset.

US Pat. No. 9,280,296

RECOVERY FROM FAILURE OF PRIMARY STORAGE VOLUMES BY USING MIRRORED DATA MAINTAINED WITH HOST TIMESTAMPS

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:
receiving, in a primary storage controller, an input/output (I/O) command from a host, wherein a host timestamp is associated
with the I/O command;

communicating, by the primary storage controller during a mirroring of storage volumes to a secondary storage controller,
the host timestamp associated with the I/O command to the secondary storage controller, wherein the mirrored copies of the
storage volumes are timestamped with a time that is calculated by adding the host timestamp on a last host I/O operation to
time elapsed in primary storage controller since the last host I/O operation and subtracting a drift of a clock of the primary
storage controller, wherein the drift comprises an error in the time elapsed in the in the primary storage controller; and

recovering, from a failure of one or more of the storage volumes in the primary storage controller, by using the timestamped
mirrored copies of the storage volumes.

US Pat. No. 9,275,951

CURVILINEAR WIRING STRUCTURE TO REDUCE AREAS OF HIGH FIELD DENSITY IN AN INTEGRATED CIRCUIT

GLOBALFOUNDRIES INC., Gr...

1. A method for reducing areas of high field density in an integrated circuit, the method comprising:
forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit, wherein forming the first
curvilinear wiring structure comprises forming a first set of concentric conductive annular structures having a first electrode
and a second electrode;

forming a second curvilinear wiring structure in a second interconnect layer of the integrated circuit, wherein the second
curvilinear wiring structure is substantially vertically aligned with the first curvilinear wiring structure; and

electrically connecting the first curvilinear wiring structure to the second curvilinear wiring structure, wherein electrically
connecting the first curvilinear wiring structure to the second curvilinear wiring structure comprises:

forming a curvilinear conductive via to electrically connect the first curvilinear wiring structure to the second curvilinear
wiring structure; and

extending the curvilinear conductive via between the first curvilinear wiring structure and the second curvilinear wiring
structure.

US Pat. No. 9,324,790

SELF-ALIGNED DUAL-HEIGHT ISOLATION FOR BULK FINFET

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor structure, the method comprising:
forming a first isolation region between fins of a first group of fins and between fins of a second group of fins, the first
and second group of fins being formed in a bulk semiconductor substrate, wherein said forming said first isolation region
comprises:

conformally depositing a first dielectric layer above the bulk semiconductor substrate and between the first and second group
of fins,

forming a dummy material on a portion of said first dielectric layer that is located between said first and second group of
fins, said dummy material having a topmost surface that is coplanar with a topmost surface of the first dielectric layer that
is located atop the first and second group of fins, and

recessing exposed portions of said first dielectric layer selective to said first and second group of fins and said dummy
material; and

forming a second isolation region between the first group of fins and the second group of fins, the second isolation region
extending through a portion of the first isolation region such that the first and second isolation regions are in direct contact
and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk
semiconductor substrate of the first isolation region, wherein said forming said second isolation region comprises removing
said dummy material and etching entirely through a remaining portion of said first dielectric layer and partially into said
bulk semiconductor substrate.

US Pat. No. 9,276,118

FINFET DEVICE HAVING A MERGE SOURCE DRAIN REGION UNDER CONTACT AREAS AND UNMERGED FINS BETWEEN CONTACT AREAS, AND A METHOD OF MANUFACTURING SAME

GLOBALFOUNDRIES INC., Gr...

1. A fin field-effect transistor (FinFET) device, comprising:
a substrate;
a plurality of fins on the substrate;
a plurality of gate regions on portions of the fins, wherein the gate regions are spaced apart from each other;
spacers on each respective gate region;
one or more contact area trenches respectively formed at one or more portions between adjacent gate regions;
an epitaxy region on each of the fins in the one or more contact area trenches, wherein the epitaxy regions on adjacent fins
in the one or more contact area trenches are merged with each other to form merged epitaxy regions; and

an unmerged epitaxy region on portions of each of the fins between the one or more contact area trenches;
wherein the unmerged epitaxy regions are doped differently than the merged epitaxy regions.

US Pat. No. 9,338,528

OPTIMAL POSITIONING OF REFLECTING OPTICAL DEVICES

GLOBALFOUNDRIES INC., Gr...

11. A computer program product for optimal positioning of reflecting optical devices by an all optical switch in an optically-connected
system of a computing environment by at least one processor device, the computer program product comprising a non-transitory
computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program
code portions comprising:
a first executable portion that uses optical power readings taken from an optimal monitoring module that are transmitted to
the all optical switch for optimal positioning of a reflecting optical device in order to produce maximum optical output power;
and a second executable portion that transmits the optical power readings to an optical switch controller using an optical
control loop function; wherein the reflecting optical device is a microelectromechanical (MEMS) mirror and the optically-connected
system is one of an optically-connected circuit network system and an electrical circuit system and the optimal monitoring
module is included in each one of a plurality of optical transceivers and optical receivers; and a third executable portion
for aggregating the optical power readings of each of a plurality of optical transceivers and optical receivers prior to transmitting
the optical power readings to the all optical switch, wherein each of the optical power readings taken by each of the plurality
of optical transceivers and optical receivers are periodically performed.

US Pat. No. 9,299,781

SEMICONDUCTOR DEVICES WITH CONTACT STRUCTURES AND A GATE STRUCTURE POSITIONED IN TRENCHES FORMED IN A LAYER OF MATERIAL

GLOBALFOUNDRIES Inc., Gr...

1. A device, comprising:
an active region defined in a semiconductor substrate;
a layer of material positioned above said substrate;
a plurality of laterally spaced-apart source/drain trenches formed in said layer of material above said active region;
a conductive source/drain contact structure formed within each of said source/drain trenches;
a gate trench formed partially in said layer of material between said spaced-apart source/drain trenches formed in said layer
of material and partially within another layer of material surrounding an outer perimeter of said layer of material, wherein
portions of said layer of material remain positioned between said source/drain trenches and said gate trench;

a gate structure positioned within said gate trench; and
a gate cap layer positioned above said gate structure, wherein an entirety of sidewalls of said gate cap layer directly contacts
sidewalls of said gate trench.

US Pat. No. 9,287,136

FINFET FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING

GLOBALFOUNDRIES INC., Gr...

1. A multigate field-effect transistor device comprising:
a gate structure that envelops a plurality of surfaces of at least one fin that are above a substrate; and
the at least one fin, wherein the at least one fin provides a channel between a source and the gate structure and between
a drain and the gate structure, the at least one fin having a maximum dimension of 30 nm,

wherein the at least one fin is composed of a semiconducting material and at least one monolayer of dopant atoms that conformally
overlays the semiconducting material in three-dimensions so a conformal thickness of 5 nm or less of said at least one monolayer
of dopant atoms is present on an upper surface and sidewall surfaces of the at least one fin, wherein a lattice structure
of the at least one monolayer of dopant atoms substantially match a lattice structure of the semiconductor material; and

wherein the at least one monolayer of dopant atoms includes at least 4×1020 active dopant atoms per cm3 that are bonded with atoms on a surface of the semiconducting material such that bonding between the active dopant atoms and
the atoms on the surface of the semiconducting material increases the conductivity of the surface of the semiconducting material.

US Pat. No. 9,286,133

VERIFICATION OF DYNAMIC LOGICAL PARTITIONING

GLOBALFOUNDRIES INC., Gr...

1. A method for verifying transitions between logical partition configurations, the method comprising:
dividing physical resources of a processing core into a number of logical partitions, wherein each logical partition has an
associated context comprising at least one processing subcore;

assigning a test case to each processing subcore, wherein the assigned test case contains instructions for verifying the associated
context of the respective logical partition to which the processing subcore belongs, and executing the assigned test cases;

reassigning at least some of the test cases to different processing subcores prior to reconfiguring the physical resources
of the processing core into a different number of logical partitions;

reconfiguring the physical resources into the different number of logical partitions; and
executing the test cases as assigned within the different number of logical partitions.

US Pat. No. 9,281,390

STRUCTURE AND METHOD FOR FORMING PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A semiconductor structure comprising:
a programmable memory device located on a first portion of a semiconductor substrate, wherein said programmable memory device
comprises a gate structure and spacers abutting the gate structure, the gate structure comprising a first metal gate electrode
atop a high-k gate dielectric, wherein a portion of the high-k gate dielectric is present beneath the spacers abutting the
gate structure, and wherein the portion of the high-k gate dielectric located beneath the spacer provides an electron injection
barrier that facilitates electron and hole trapping in a memory function of the programmable memory device; and

a semiconductor device located on a second portion of the semiconductor substrate, wherein the programmable memory device
is separated from the semiconductor device by an isolation region located in the semiconductor substrate in between the first
and second portions, wherein the semiconductor device includes a semiconductor gate structure and a semiconductor spacer adjacent
to the semiconductor gate structure, and wherein the semiconductor gate structure includes a second metal gate electrode located
atop of a semiconductor gate dielectric, wherein an edge of the semiconductor gate dielectric is aligned to a sidewall of
the second metal gate electrode, and wherein the semiconductor gate dielectric is not located underneath the semiconductor
spacer.

US Pat. No. 9,286,425

METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS

GLOBALFOUNDRIES INC., Gr...

1. A process for manufacturing an integrated circuit, the process comprising:
translating inputs into a design structure embodied in a machine readable storage medium in a data format used for the exchange
of layout data of integrated circuits and/or symbolic data format; and fabricating the integrated circuit defined by the design
structure having manufacturing data, wherein the integrated circuit includes:

a high-leakage dielectric on each of sides of a segmented field effect transistor (FET) comprised of active silicon islands
and gate electrodes thereon; and

a low-leakage dielectric on and in contact with a top surface of the active silicon islands, adjacent the high-leakage dielectric,
a top surface of the high-leakage dielectric being at a coplanar level as the top surface of the active silicon islands; and

a gate electrode material is within a divot of a shallow trench isolation material and is in direct contact with and between
a portion of the shallow trench isolation material and the high-leakage dielectric, wherein the high-leakage dielectric is
within the divot and on a side surface of the active silicon islands, wherein:

the high-leakage dielectric, the low-leakage dielectric, the gate electrode material, and the shallow trench isolation material
are completely above a buried oxide (BOX) layer;

the gate electrodes are directly in contact with the shallow trench isolation material; and
top surfaces of the gate electrode material and the shallow trench isolation material are formed at the coplanar level as
the top surfaces of the high-leakage dielectric and the active silicon islands.

US Pat. No. 9,268,491

THICK AND THIN DATA VOLUME MANAGEMENT

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:
configuring, by a processor, one or more storage devices as a plurality of physical storage units;
configuring multiple storage pools, each of the multiple storage pools having one or more respective pool attributes;
defining a grouped pool comprising the multiple storage pools; and
upon receiving a request to create a data volume having one or more volume attributes and comprising a requested number of
the physical storage units:

identifying a given storage pool in response to a comparison between the one or more pool attributes thereof and the one or
more volume attributes thereof;

detecting an available number of the physical storage units in the given storage pool; and
upon determining that the requested number of the physical storage units is greater than the available number of the physical
storage units:

computing a number comprising the available number of the physical storage units subtracted from the requested number of the
physical storage units.

US Pat. No. 9,276,115

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:
forming at least one gate structure over a plurality of fin structures;
removing dielectric material adjacent to the at least one gate structure using a maskless process, thereby exposing an underlying
epitaxial layer formed adjacent to the at least one gate structure;

depositing metal material on the exposed underlying epitaxial layer to form contact metal in electrical contact with source
and drain regions, adjacent to the at least one gate structure;

forming active areas and device isolation after the formation of the contact metal, comprising the at least one gate structure,
wherein the active areas and the contact metal are self-aligned with each other in a direction parallel to the at least one
gate structure.

US Pat. No. 9,269,407

SYSTEM AND METHOD FOR MANAGING CIRCUIT PERFORMANCE AND POWER CONSUMPTION BY SELECTIVELY ADJUSTING SUPPLY VOLTAGE OVER TIME

GLOBALFOUNDRIES INC., Gr...

1. A system comprising:
an adjustable voltage regulator; and,
an integrated circuit chip,
said adjustable voltage regulator and said integrated circuit chip each being incorporated into a product,
said integrated circuit chip comprising:
a power rail;
a power supply pin electrically connecting said power rail and said adjustable voltage regulator;
a memory storing an age/voltage table that associates different ages of said integrated circuit chip with different supply
voltages for said power rail;

an age monitor automatically measuring an age of said integrated circuit chip;
a voltage selector in communication with said age monitor, said memory and said adjustable voltage regulator, said voltage
selector accessing said age/voltage table, using said age/voltage table to automatically make a selection of a specific supply
voltage for said power rail based on said age and outputting said selection, as a voltage selection signal, to said adjustable
voltage regulator, and

said adjustable voltage regulator applying said specific supply voltage to said power rail in response to said voltage selection
signal.

US Pat. No. 9,286,969

LOW POWER SENSE AMPLIFIER FOR STATIC RANDOM ACCESS MEMORY

GLOBALFOUNDRIES INC., Gr...

1. A circuit, comprising:
a first pass gate transistor driven by a signal derived from a bit line true associated with a static random access memory
(SRAM) cell;

a second pass gate transistor driven by a signal derived from a bit line complement associated with the SRAM cell;
a first pull down transistor driven by the signal derived from the bit line complement and coupled to the first pass gate
transistor;

a second pull down transistor driven by the signal derived from the bit line true and coupled to the second pass gate transistor;
a data line true coupled to a node coupling the first pass gate transistor with the first pull down transistor, wherein the
data line true is isolated from the bit line true by the first pass gate transistor;

a data line complement coupled to a node coupling the second pass gate transistor with the second pull down transistor, wherein
the data line complement is isolated from the bit line complement by the second pass gate transistor; and

a current cut-off device that cuts off parasitic current from flowing through one of a first path formed from the first pass
gate transistor and the first pull down transistor and a second path formed from the second pass gate transistor and the second
pull down transistor.

US Pat. No. 9,286,201

METHOD AND SYSTEM FOR AUTOMATIC SPACE ORGANIZATION IN TIER2 SOLID STATE DRIVE (SSD) CACHE IN DATABASES FOR MULTI PAGE SUPPORT

GLOBALFOUNDRIES INC., Gr...

1. A method of adjusting space allocated for different page sizes on a non-transitory recording medium, the method comprising:
dividing the recording medium into multiple blocks such that a block size of the multiple blocks supports a largest page size
of the different page sizes, and such that each of the multiple blocks is used for a single page size;

assigning an incoming page to a block based on a temperature of the incoming page;
creating temperature heaps for each page size; and
if all of the blocks are assigned;
checking for a highest rejected temperature for each page size to determine a coldest block; and
converting the coldest block to another page size if a difference in the highest rejected temperature and a temperature of
the coldest block is greater than a temperature threshold for admission.

US Pat. No. 9,280,465

TECHNIQUES FOR MOVING CHECKPOINT-BASED HIGH-AVAILABILITY LOG AND DATA DIRECTLY FROM A PRODUCER CACHE TO A CONSUMER CACHE

GLOBALFOUNDRIES INC., Gr...

1. A data processing system, comprising:
a producer core;
a producer cache coupled to the producer core;
a consumer core; and
a consumer cache coupled to the consumer core;
wherein the producer cache is configured to log addresses for cache lines modified by the producer core in a data array of
the producer cache to create a high-availability (HA) log for the producer core, write the HA log directly into the consumer
cache of the consumer core, and write HA data associated with the addresses of the HA log directly into the consumer cache,
and wherein the HA log corresponds to a cache line that includes multiple of the addresses and the consumer core is configured
to process the HA log and the HA data for the data processing system;

wherein the addresses for the modified cache lines are logged in an intermediate buffer of the producer cache; and
wherein the HA log is transferred from the intermediate buffer to a circular buffer of the consumer cache in response to the
intermediate buffer being full and is written into the consumer cache by injecting the HA log stored in the circular buffer
into the consumer cache.

US Pat. No. 9,276,079

SEMICONDUCTOR DEVICE EXHIBITING REDUCED PARASITICS AND METHOD FOR MAKING SAME

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a semiconductor device, the method comprising:
providing a substrate;
forming a gate stack at each device location on said substrate, the gate stack including a metal gate conductor on a gate
dielectric layer disposed on a device channel;

forming a gate spacer extending from the substrate about the sides of the gate stack, the thickness of said gate spacer being
as thick as said gate stack;

forming source/drain regions adjacent said gate spacer at each end of said gate stack;
forming silicide regions on each of said source/drain regions;
depositing a stress liner comprising a nitride layer on said substrate overlying the metal gate and extending from said substrate
between the gate spacers, said stress liner separating each silicide region at said substrate from a respective said gate
spacer;

forming a dielectric layer over said stress liner, the combined thickness of said dielectric layer and said stress liner over
said gate stack and said silicide regions being at least 3 times as tall as said gate stack; and

forming contacts through said combined thickness to said metal gate and the silicide regions, each gate contact being above
said device channel and narrower than said gate stack.

US Pat. No. 9,257,324

FORMING STRUCTURES ON RESISTIVE SUBSTRATES

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a substrate, the method comprising:
forming an intrinsic region;
forming a first region having a first resistivity, for accommodating a field effect transistor;
forming a second region having a second resistivity, for accommodating an npn subcollector of a bipolar transistor device
and triple well;

forming a third region having a third resistivity, for accommodating a passive device; and
forming a fourth region, substantially without implantation, to provide low perimeter capacitance for devices, the fourth
region comprising a portion of the intrinsic region;

wherein the resistivity of the first region is between 1 ohm-cm and 100 ohm-cm and includes dopant materials to lower its
resistivity with respect to the intrinsic region, the resistivity of the second region is between 0.001 and 0.1 ohm-cm, the
resistivity of the third region is between 500 and 5000 ohm-cm and includes dopant materials to increase its resistivity with
respect to the intrinsic region, and the resistivity of the fourth region and the intrinsic region is about 1000 ohm-cm.

US Pat. No. 9,257,531

SELF-ALIGNED CONTACT STRUCTURE FOR REPLACEMENT METAL GATE

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a semiconductor structure comprising:
forming a replacement gate structure embedded within a planarization dielectric layer on a semiconductor substrate;
removing said planarization dielectric layer to physically expose a semiconductor surface;
forming a raised semiconductor structure by depositing a faceted semiconductor material on said physically exposed semiconductor
surface to a height above a topmost surface of said replacement gate structure;

depositing a first dielectric material over said replacement gate structure and said raised semiconductor structure;
recessing a top surface of said raised semiconductor structure;
depositing a second dielectric material over said deposited first dielectric material, wherein a portion of said second dielectric
material is deposited directly over said recessed top surface of said raised semiconductor structure and below a planar interface
between said second dielectric material and said first dielectric material; and

forming a cavity by etching another portion of said second dielectric material overlying said portion of said second dielectric
material and subsequently etching said portion of said second dielectric material selective to said first dielectric material.

US Pat. No. 9,224,863

PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL ON THE BASIS OF A SEED LAYER

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a transistor in a semiconductor device, the method comprising:
performing an epitaxial growth process to deposit a layer of a threshold voltage adjusting semiconductor material on a semiconductor
base material formed in an active region of said semiconductor device, wherein said threshold voltage adjusting semiconductor
material has a greater natural lattice constant than said semiconductor base material;

forming a cavity in said active region laterally adjacent to a gate electrode structure, said cavity extending through said
threshold voltage adjusting semiconductor material and into said semiconductor base material;

forming a liner of a first semiconductor material on at least a portion of exposed surface areas of said cavity, wherein at
least a portion of said liner covers upper sidewall surface portions of said cavity including sidewall surfaces of said threshold
voltage adjusting semiconductor material, said first semiconductor material having a first material composition;

forming a second semiconductor material in said cavity, said second semiconductor material comprising a strain-inducing atomic
species and having a second material composition that differs from said first material composition, wherein said second semiconductor
material partially fills said cavity and exposes said at least said portion of said liner covering said upper sidewall surface
portions of said cavity;

forming a third semiconductor material on said second semiconductor material so as to fill a remaining portion of said cavity
and to cover said at least said portion of said liner covering said upper sidewall surface portions of said cavity, said third
semiconductor material comprising said strain-inducing atomic species and having a third material composition that differs
from said first material composition; and

forming drain and source regions at least in a portion of said second semiconductor material.

US Pat. No. 9,287,264

EPITAXIALLY GROWN SILICON GERMANIUM CHANNEL FINFET WITH SILICON UNDERLAYER

GLOBALFOUNDRIES Inc., Gr...

1. A method for epitaxially growing a FinFET, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate includes at least an insulator and an underlayer;
forming a channel layer on the semiconductor substrate using epitaxial growth;
etching a recess into the channel layer;
regrowing a portion of the channel layer using epitaxial growth;
etching one or more recesses into the channel layer and the underlayer to form a plurality of fins;
forming a gate structure and a set of spacers, wherein the set of spacers are formed on sidewalls of the gate structure;
etching a source drain region into the channel layer; and
forming a source drain material in the source drain region using epitaxial growth.

US Pat. No. 9,293,467

RECONFIGURABLE TUNNEL FIELD-EFFECT TRANSISTORS

GLOBALFOUNDRIES INC., Gr...

1. A tunnel field-effect transistor (TFET) device, comprising:
first and second semiconductor contact regions separated by a semiconductor channel region;
a channel gate overlying the channel region; and
first and second doping gates overlying the first and second contact regions respectively; and
further comprising first and second contact electrodes connected to the first and second contact regions respectively, wherein
at least one of the first and second doping gates is shorted to the corresponding contact electrode, and

wherein application of a positive voltage level at the first doping gate and a negative voltage level at the second doping
gate produces an n-type first contact region and a p-type second contact region, and reversing the voltage levels at the doping
gates produces a p-type first contact region and an n-type second contact region.

US Pat. No. 9,275,989

CAPACITORS POSITIONED AT THE DEVICE LEVEL IN AN INTEGRATED CIRCUIT PRODUCT AND METHODS OF MAKING SUCH CAPACITORS

GLOBALFOUNDRIES Inc., Gr...

1. An integrated circuit product, comprising:
a transistor formed in and above a semiconducting substrate, said transistor comprising a gate electrode and a plurality source/drain
regions;

a plurality of source/drain interconnects, each of which is conductively coupled to one of said source drain regions;
a plurality of source/drain contacts, each of which is conductively coupled to one of said source/drain interconnects;
a gate contact that is conductively coupled to said gate electrode;
a capacitor comprised of two outer conductive plates and an inner conductive plate positioned between said outer conductive
plates, wherein said inner conductive plate is comprised of a first conductive portion that is comprised of the same material
as said gate contact and wherein each of said outer conductive plates comprise:

a first conductive portion that is comprised of the same material as said source/drain interconnects; and
a second conductive portion that is comprised of the same material as said source/drain contacts;
at least one region of insulating material positioned between said plurality of conductive plates; and
a metal-1 metallization layer positioned above said capacitor and said transistor.

US Pat. No. 9,538,689

DATA CENTER COOLING WITH CRITICAL DEVICE PRIORITIZATION

GLOBALFOUNDRIES Inc., Gr...

1. A computer program product for automatically adjusting room temperature in a data center room, the computer program product
comprising a computer readable storage medium having program code embodied therewith, the program code readable and executable
by one or more processors to perform a method comprising:
receiving, by a processor in a heating, ventilation and air conditioning (HVAC) system, a throttle threshold temperature for
each of multiple computing devices, wherein the multiple computing devices are physically located within a data center room
that is climate-controlled by the HVAC system, wherein the throttle threshold temperature is a temperature that, if exceeded,
causes operations of one or more components of a computing device to be reduced, and wherein the throttle threshold temperature
is provided by a hardware management module (MM) associated with at least one of the multiple computing devices;

monitoring, by the processor in the HVAC system, a real-time temperature of at least one of the multiple computing devices,
wherein the real-time temperature is provided by the hardware MM associated with said at least one of the multiple computing
devices;

in response to the real-time temperature of said at least one of the multiple computing devices exceeding the throttle threshold
temperature for said at least one of the multiple computing devices, decreasing an ambient air temperature in the data center
room by adjusting a hardware thermostat in the HVAC system;

identifying, by the processor in the HVAC system, a critical computing device from the multiple computing devices, wherein
the critical computing device has been predetermined to be critical to a mission;

identifying, by the processor in the HVAC system, a non-critical computing device from the multiple computing devices, wherein
the non-critical computing device has been predetermined to be non-critical to the mission; and

prioritizing, for the mission, cooling of the critical computing device over the non-critical computing device, the prioritizing
including controlling the ambient air temperature in the data center room based on the throttle threshold temperature for
the critical computing device, or a throttling history of the critical computing device.

US Pat. No. 9,269,603

TEMPORARY LIQUID THERMAL INTERFACE MATERIAL FOR SURFACE TENSION ADHESION AND THERMAL CONTROL

GLOBALFOUNDRIES INC., Gr...

1. A method of testing a three-dimensional device, comprising:
temporarily adhering a wafer to a glass substrate with an adhesive;
thinning the wafer to form a thinned wafer; and
temporarily attaching the thinned wafer to a carrier wafer by applying a non-adhesive material therebetween and pressing the
thinned wafer and the carrier wafer together,

wherein the non-adhesive material is applied after the adhesive material,
wherein the thinned wafer is detached from the glass substrate prior to temporarily attaching the thinned wafer to the carrier
wafer, and

wherein the carrier wafer is an unprocessed silicon wafer,
wherein the thinning the wafer to form the thinned wafer forms a through silicon via (TSV) in the thinned wafer, and further
comprising:

testing the thinned wafer by contacting the TSV while the thinned wafer is attached to the carrier wafer;
dicing the thinned wafer while the thinned wafer is attached to the carrier wafer and without dicing the carrier wafer, wherein
the dicing forms diced dies;

releasing the diced dies from the carrier wafer using a bake procedure that evaporates the non-adhesive material;
picking the diced dies from the carrier wafer; and
removing the adhesive material the diced dies.

US Pat. No. 9,332,673

SURFACE MODIFICATION OF HOSES TO REDUCE DEPLETION OF CORROSION INHIBITOR

GLOBALFOUNDRIES INC., Gr...

1. A cooling apparatus for transferring heat from at least one electronic component mounted on a circuit board, comprising:
a plurality of liquid-coolant cooling system components in fluid communication with each other, wherein the plurality of liquid-coolant
cooling system components comprise a first liquid-cooled cold plate and one or more other liquid-coolant cooling system components
selected from a group consisting of an additional liquid-cooled cold plate, a coolant supply header, a coolant return header,
a coolant supply manifold, a coolant return manifold, a coolant pump, a coolant reservoir, a heat exchanger, and combinations
thereof, wherein each liquid-cooled cold plate is positioned over and in thermal contact with at least one electronic component
mounted on a circuit board and has a thermal dissipation channel extending through a portion thereof;

a liquid coolant;
a corrosion inhibitor dissolved in the liquid coolant;
at least one hose interconnecting at least two of the plurality of liquid-coolant cooling system components, wherein the hose
comprises a modified surface that is pre-treated with a passivating agent to reduce depletion of the corrosion inhibitor dissolved
in the liquid coolant.

US Pat. No. 9,293,382

VOLTAGE CONTRAST INSPECTION OF DEEP TRENCH ISOLATION

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:
providing a semiconductor-on-insulator (SOI) substrate having a buried dielectric layer located above a buried plate;
forming a deep trench isolation structure in the SOI substrate having a first node dielectric and a first inner electrode,
wherein the deep trench isolation structure electrically isolates an inner buried plate located on one side of the deep trench
isolation structure from an outer buried plate located on an opposite side of the deep trench isolation structure;

forming a deep trench capacitor in the SOI substrate having a second node dielectric and a second inner electrode;
forming a first test structure and a second test structure in the SOI substrate and on opposite sides of the deep trench isolation
structure, the first and second test structures having a third node dielectric and a third inner electrode, wherein the first
test structure and the second test structure are similar in size and shape, and have a different width than the deep trench
capacitor;

etching the third node dielectric and the third inner electrode of the first and second test structures to a first depth below
the buried dielectric layer;

etching the second node dielectric and the second inner electrode of the deep trench capacitor to a second depth above the
buried plate and within the buried dielectric layer; and

etching the first node dielectric and the first inner electrode to a third depth above the buried plate and within the buried
dielectric layer, wherein the first depth is deeper than the second depth.

US Pat. No. 9,287,109

METHODS OF FORMING A PROTECTION LAYER TO PROTECT A METAL HARD MASK LAYER DURING LITHOGRAPHY REWORKING PROCESSES

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
forming a layer of insulating material above a semiconductor substrate;
forming a hard mask layer above said layer of insulating material;
forming a blanket protection layer on said hard mask layer;
forming a masking layer above said blanket protection layer;
performing at least one etching process on said masking layer to form a patterned masking layer having an opening that stops
on and exposes an upper surface portion of said blanket protection layer without exposing said underlying hard mask layer;

while said blanket protection layer is covering said hard mask layer, confirming that said patterned masking layer is properly
positioned relative to at least one underlying structure or layer;

after confirming that said patterned masking layer is properly positioned, performing at least one etching process through
said patterned masking layer to pattern said blanket protection layer and said underlying hard mask layer, said patterned
hard mask layer exposing an upper surface portion of said layer of insulating material;

removing said patterned blanket protection layer, and
after removing said patterned blanket protection layer, forming one of a trench and an opening in said layer of insulating
material through said patterned hard mask layer.

US Pat. No. 9,408,304

THROUGH PRINTED CIRCUIT BOARD (PCB) VIAS

GLOBALFOUNDRIES INC., Gr...

1. A structure, comprising:
a multiple layered body;
an opening in the multiple layered body;
at least one signal via extending through the opening;
ground vias extending through the opening and on opposing sides of the at least one signal via;
a ground plate above and below the opening and electrically connected to the ground vias at respective ends; and
a microstrip signal line above and below the opening and electrically connected to the at least one signal via.

US Pat. No. 9,252,203

METAL-INSULATOR-METAL BACK END OF LINE CAPACITOR STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A semiconductor structure comprising:
a first metallization layer;
an interlevel dielectric layer disposed on the first metallization layer;
a metal sublayer disposed within the interlevel dielectric layer;
a second metallization layer disposed on the interlevel dielectric layer;
a metal-insulator-metal (MIM) capacitor disposed on the metal sublayer, the MIM capacitor having a first plate, a capacitor
dielectric layer, and a second plate, wherein the capacitor dielectric layer is disposed between the first plate and the second
plate, and wherein a portion of the metal sublayer extends beyond the MIM capacitor, and wherein the second plate is in contact
with the metal sublayer;

a via from the first plate to the second metallization layer; and
a via from the metal sublayer to the second metallization layer.

US Pat. No. 9,245,794

FORMATION OF ALLOY LINER BY REACTION OF DIFFUSION BARRIER AND SEED LAYER FOR INTERCONNECT APPLICATION

GLOBALFOUNDRIES INC., Gr...

1. An interconnect structure comprising:
a dielectric material including at least one opening therein;
an alloy metal A deficient diffusion barrier located within said at least one opening;
an alloy liner located directly on said alloy metal A deficient diffusion barrier, said alloy liner consists of a thermal
reaction product of alloy metal A and alloy metal B;

an alloy metal B deficient Cu alloy seed layer located directly on said alloy liner; and
an interconnect conductive material located within the at least one opening atop said alloy metal B deficient Cu alloy seed
layer, wherein alloy metal A is a transition metal selected from Group IVB, VB, VIB, VIIB or VIII of the Periodic Table of
Elements, and alloy metal B is a transition metal from Group IVB, VB, VIB, VIIB or VIII of the Periodic Table of Elements
or a metal from Group IIIA of the Periodic Table of Elements, with the proviso that alloy metal B is different from alloy
metal A.

US Pat. No. 9,306,001

UNIFORMLY DOPED LEAKAGE CURRENT STOPPER TO COUNTER UNDER CHANNEL LEAKAGE CURRENTS IN BULK FINFET DEVICES

INTERNATIONAL BUSINESS MA...

12. A fin-type field effect transistor (FinFET) comprising:
at least one fin having an active region and a non-active region;
a channel region in the active region of the at least one fin;
a leakage current stopper region in the non-active region;
the leakage current stopper region formed by:
exposing a surface of the non-active region of the at least one fin, the exposed surface leading to a portion of the non-active
region that is substantially underneath the channel region; and

implanting dopants through the exposed surface of the non-active region of the at least one fin to form the leakage current
stopper region.

US Pat. No. 9,578,794

APPARATUS AND METHOD FOR DETACHING A COMPONENT FROM A MOUNTING SURFACE

GLOBALFOUNDRIES Inc., Gr...

1. An apparatus for detaching a component from a mounting surface to which the component is attached by an adhesive, the apparatus
comprising:
a right-angled hook disposed on one side of the component, the right-angled hook protruding into a first space between the
component and the mounting surface, wherein the right-angled hook defines a first width and is oriented at an angle relative
to the mounting surface to project inwardly to said mounting surface towards said component;

a curved hook that is non-right angled and is disposed on another side of the component, the curved hook protruding into a
second space between the component and the mounting surface, wherein between said curved hook and said mounting surface, an
angle of curvature is defined relative to said mounting surface, wherein the curved hook defines a second width, and the first
width of the right-angled hook is less than the second width of the curved hook;

a connecting body connecting the right-angled hook and the curved hook; and
an adjusting member coupled to one of the curved hook and the right-angled hook, the adjusting member structured to adjust
a distance between the right-angled hook and the curved hook, and if the right-angled hook protrudes precisely into the first
space and the curved hook protrudes precisely into the second space then the apparatus clamps the component such that further
adjustment of the adjusting member to tighten clamping of the component will compress the curved hook, wherein the curved
hook is shaped to generate a shear force sufficient to detach the component from the mounting surface if compressed by the
further adjustment of the adjusting member.

US Pat. No. 9,064,702

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

IMEC, Leuven (BE) GLOBAL...

1. A method for reducing defects in an active device area of a semiconductor device during fabrication, comprising:
providing a substantially planar surface comprising an active device area adjacent an isolation structure;
forming a stress-inducing layer over the substantially planar surface and patterning to remove a portion of the stress-inducing
layer from the active device area while leaving the stress-inducing layer over the isolation region, the patterned stress-inducing
layer being configured to induce a stress field in the active device area, the induced stress field resulting in a shear stress
being applied on defects present in the active device area;

forming at least one screening layer between the patterned stress-inducing layer and the substantially planar surface, the
screening layer being configured to screen part of the stress field induced by the patterned stress-inducing layer;

performing an anneal process after forming the patterned stress-inducing layer over the substantially planar surface, so as
to induce a movement of the defects towards a contact interface between the active device area and the isolation structure,
wherein the stress field in the active device area has a sign and a magnitude that are conducive to movement of the defects
in the active device area towards the contact interface during the anneal process; and

removing the patterned stress-inducing layer from the substantially planar surface.

US Pat. No. 9,578,775

LGA SOCKET TERMINAL DAMAGE PREVENTION

GLOBALFOUNDRIES INC., Gr...

1. A land grid array (LGA) socket apparatus for preventing LGA socket terminal damage, comprising:
an LGA socket, with two guide rails provided respectively on inner sides of two opposite side walls of the LGA socket, a height
of a top surface of each guide rail from a bottom of the LGA socket being greater than a height of LGA socket terminals from
a bottom of the LGA socket, and a length of each guide rail being smaller than a length of an inner side of the side wall,

wherein the guide rails are configured to support at least two protrusions provided respectively at corners at opposite sides
of an integrated circuit chip assembly when the integrated circuit chip assembly is slid into the LGA socket from a side,
and

wherein the guide rails are configured to, when the integrated circuit chip assembly is slid to an end of the guide rail,
enable the at least two protrusions to fall into gaps between an end of the guide rails and an end wall of the respective
LGA socket, so that the integrated circuit chip assembly is installed in the LGA socket.

US Pat. No. 9,538,690

DATA CENTER COOLING METHOD WITH CRITICAL DEVICE PRIORITIZATION

GLOBALFOUNDRIES Inc., Gr...

1. A method of automatically adjusting room temperature in a data center room, the method comprising:
receiving, by a processor in a heating, ventilation and air conditioning (HVAC) system, a throttle threshold temperature for
each of multiple computing devices, wherein the multiple computing devices are physically located within a data center room
that is climate-controlled by the HVAC system, wherein the throttle threshold temperature is a temperature that, if exceeded,
causes operations of one or more components of a computing device to be reduced, and wherein the throttle threshold temperature
is provided by a hardware management module (MM) associated with at least one of the multiple computing devices;

monitoring, by the processor in the HVAC system, a real-time temperature of at least one of the multiple computing devices,
wherein the real-time temperature is provided by the hardware MM associated with said at least one of the multiple computing
devices;

in response to the real-time temperature of said at least one of the multiple computing devices exceeding the throttle threshold
temperature for said at least one of the multiple computing devices, decreasing an ambient air temperature in the data center
room by adjusting a hardware thermostat in the HVAC system;

identifying, by the processor in the HVAC system, a critical computing device from the multiple computing devices, wherein
the critical computing device has been predetermined to be critical to a mission;

identifying, by the processor in the HVAC system, a non-critical computing device from the multiple computing devices, wherein
the non-critical computing device has been predetermined to be non-critical to the mission; and

prioritizing, for the mission, cooling of the critical computing device over the non-critical computing device, the prioritizing
including controlling the ambient air temperature in the data center room based on the throttle threshold temperature for
the critical computing device, or a throttling history of the critical computing device.

US Pat. No. 9,292,079

ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE

GLOBALFOUNDRIES INC., Gr...

1. A method for an integrated circuit with power gating, the method comprising:
providing a power header switch to connect and disconnect any one of a plurality of circuits to a common voltage source, wherein
a powered off circuit is disconnected from the common voltage source;

configuring a power-up sequencer to comprise an initial stages power-up component and a final stages power-up component, wherein
the final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit;
and

configuring the initial stages power-up component to execute initial stages of the power-up process for the powered off circuit,
the initial stages power-up component being activated in response to a predictive power-up request.

US Pat. No. 9,269,634

SELF-ALIGNED METAL GATE CMOS WITH METAL BASE LAYER AND DUMMY GATE STRUCTURE

GLOBALFOUNDRIES INC., Gr...

1. A method for forming a semiconductor device, comprising:
forming an N-field effect transistor (NFET) gate region and a P-field effect transistor (PFET) gate region, wherein each gate
region comprises a metal base layer and a dummy gate structure formed on the metal base layer, wherein the dummy gate structure
of the NFET gate region comprises an N-type polysilicon (N-poly) material, wherein the dummy gate structure of the PFET gate
region comprises a P-type polysilicon (P-poly) material, and wherein sidewall spacers are formed on sidewalls of the dummy
gate structures of the NFET gate region and the PFET gate region;

depositing a silicon nitride (SiN) liner over the NFET and PFET gate regions;
depositing a dielectric layer over the SiN liner;
etching the dielectric layer and the SiN liner to expose the dummy gate structure of the NFET region and the dummy gate structure
of the PFET region;

removing the dummy gate structure of the NFET gate region selective to the dummy gate structure of the PFET gate region, thereby
forming an NFET gate hole which exposes the metal base layer of the NFET gate region; and

filling the NFET gate hole with SiN material.

US Pat. No. 9,251,890

BIAS TEMPERATURE INSTABILITY STATE DETECTION AND CORRECTION

GLOBALFOUNDRIES INC., Gr...

1. A memory device comprising:
a set of memory circuits configured to store data by selectively being operated in one of the two following states: idle state
and active state;

a timing control module configured to selectively control the operational state of the set of memory circuits, with the timing
control module including a root combinational logic location; and

an age-detect-and-correct (ADAC) circuit, connected across the root combinational logic location and including a first set
of transistor(s) and a second set of transistor(s), the ADAC circuit being configured to control the timing control module
to arbitrate between the idle state and the active state based upon a difference in bias temperature instability fatigue as
between the first set of transistor(s) and the second set of transistor(s).

US Pat. No. 9,293,587

FORMING EMBEDDED SOURCE AND DRAIN REGIONS TO PREVENT BOTTOM LEAKAGE IN A DIELECTRICALLY ISOLATED FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A device comprising:
a gate structure formed over a finned substrate;
an embedded source and a drain (S/D) adjacent the gate structure and adjacent a fin of the finned substrate; and
an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D.

US Pat. No. 9,613,817

METHOD OF ENHANCING SURFACE DOPING CONCENTRATION OF SOURCE/DRAIN REGIONS

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:
providing a substrate for an integrated circuit;
forming an n-type and a p-type S/D region for a semiconductor device on a surface of the substrate;
exposing a top surface of solely one type of the n-type and p-type S/D regions;
depositing a diffusion layer over the top surface of the one type of S/D regions, the diffusion layer having a predetermined
concentration of a first diffusion species;

heating the diffusion layer to diffuse the first diffusion species into the one type of S/D regions to enhance a concentration
of the first diffusion species proximate the top surface of the one type of S/D regions;

removing the diffusion layer from the top surface of the one type of S/D regions;
depositing a metal layer over the top surface of the one type of S/D regions immediately after removing the diffusion layer;
forming electrical contacts over the top surface of the one type of S/D regions from the metal layer;
depositing a dielectric screen layer over the one type of S/D regions;
exposing a top surface of solely the other type of the n-type and p-type S/D regions;
depositing a second diffusion layer over the top surface of the other type of S/D regions, the second diffusion layer having
a predetermined concentration of second diffusion species; and

heating the second diffusion layer to diffuse the second diffusion species into the other type of S/D regions to enhance a
concentration of the second diffusion species proximate the top surface of the other type of S/D regions.

US Pat. No. 9,786,545

METHOD OF FORMING ANA REGIONS IN AN INTEGRATED CIRCUIT

GLOBALFOUNDRIES Inc., Gr...

12. A method comprising:
providing a structure having a first hardmask layer, interposer layer, second hardmask layer and mandrel layer disposed respectively
over a dielectric stack;

patterning an array of mandrels into the mandrel layer with a mandrel mask;
patterning a beta trench and an ANA trench into the mandrel layer with a first cut mask;
patterning a gamma trench and the ANA trench into the interposer layer with a second cut mask;
disposing an organic planarization layer (OPL) over the structure;
etching the OPL to dispose the OPL only in the ANA trench;
etching the structure to form a pattern in the dielectric stack; and
forming an array of metal lines from the pattern in the dielectric stack, a portion of the pattern formed by the ANA trench
forming an ANA region within the dielectric stack.

US Pat. No. 9,231,821

VLAG PIM LINK FAILOVER USING PIM HELLO MESSAGE

GlobalFoundries Inc., Gr...

1. A system for Protocol Independent Multicast (PIM) virtual link aggregation group (vLAG) fast link failover recovery, the
system comprising:
a network comprising a first vLAG switch connected to a second vLAG switch by an inter-switch link (ISL), the first vLAG switch
connected to an upstream network device by a failed link and the second vLAG switch connected to the upstream network device
by a functional link;

wherein to recover from the failed link, the first vLAG switch transmits a ROUTEUPDATE message to the second vLAG switch upon
the ISL that instructs the second vLAG switch to receive data traffic from the upstream network device and forward the data
traffic to the first vLAG switch upon the ISL;

wherein the second vLAG switch is instructed by the upstream network device that it is implemented in a next best route from
the upstream network device to the first vLAG switch and transmits a NEWSOURCE message to the first vLAG switch upon the ISL,
and;

wherein receipt of the NEWSOURCE message causes the first vLAG switch to transmit the ROUTEUPDATE message to the second vLAG
switch upon the ISL.

US Pat. No. 9,269,621

DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a metal interconnect structure comprising:
forming a first line trench extending through a first dielectric material layer on a substrate;
forming a stack, from bottom to top, of a first metal line and a dielectric cap material portion within said first line trench,
said dielectric cap material portion having a top surface coplanar with a top surface of said first dielectric material layer;

forming a second dielectric material layer over said first dielectric material layer and said stack;
forming a second line trench extending through said second dielectric material layer;
forming a via cavity extending to a top surface of said first metal line underneath said second line trench by removing a
portion of said dielectric cap material portion, wherein said via cavity is laterally surrounded by said first dielectric
material layer; and

forming a dual damascene line and via structure including a second metal line located within said second line trench and a
via structure located within said via cavity.

US Pat. No. 9,263,512

MEMORY CELL WITH INTEGRATED III-V DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:
forming an oxide layer on a top surface of a substrate;
forming a deep trench through the oxide layer and into the substrate;
forming a buried plate of a deep trench capacitor by doping sidewalls of the substrate exposed within the deep trench using
an ion implantation technique, the oxide layer remains and protects a top surface of the substrate from being doped by the
ion implantation;

forming a node dielectric along sidewalls and a bottom of the deep trench;
forming an inner electrode on top of the node dielectric within the deep trench;
forming an opening by recessing the node dielectric and the inner electrode; and
forming a dielectric cap by filling the opening with a dielectric material such that a top surface of the dielectric cap is
substantially flush with the top surface of the oxide layer, and

bonding a III-V compound semiconductor to a top surface of the oxide layer, wherein the dielectric cap is in direct contact
with the III-V compound semiconductor.

US Pat. No. 9,281,023

SINGLE ENDED SENSING CIRCUITS FOR SIGNAL LINES

GLOBALFOUNDRIES INC., Gr...

1. A sensing circuit comprising:
a first node;
a second node electrically connected to a signal line;
an isolation field effect transistor comprising a source electrically connected to said second node, a drain electrically
connected to said first node, and a gate;

a variable reference voltage generator electrically connected to said gate;
a pre-charge device electrically connected to said first node; and
a sense amplifier comprising:
an input receiving an input signal from said first node; and
an output outputting an output signal,
said variable reference voltage generator applying a first reference voltage to said gate and said pre-charge device turning
on, during a pre-charging mode, such that said first node is pre-charged to a first pre-charge voltage, said second node is
pre-charged to a second pre-charge voltage that is lower than said first pre-charge voltage, said input signal becomes a HIGH
input signal and said output signal becomes a LOW output signal, and

said variable reference voltage generator applying a second reference voltage that is less than said first reference voltage
to said gate, during a sensing mode, such that, upon sensing a voltage decrease at said first node, said sense amplifier switches
said LOW output signal to a HIGH output signal.

US Pat. No. 9,196,523

SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. An interconnect structure comprising:
at least one patterned dielectric layer located on a substrate, wherein said at least one patterned dielectric layer includes
differently sized conductive features embedded therein, said differently sized conductive features are laterally adjacent
to each other and are located at a same interconnect level, wherein said at least one patterned dielectric layer is a dielectric
coating composition containing a functionalized polymer, copolymer, or a blend including at least two of any combination of
polymers and/or copolymers having one or more acid-sensitive reactive groups that has been crosslinked with a residual acid
derived from a photoacid generator present in a sacrificial chemically amplified photoresist material.

US Pat. No. 9,269,786

SILICON NITRIDE LAYER DEPOSITED AT LOW TEMPERATURE TO PREVENT GATE DIELECTRIC REGROWTH HIGH-K METAL GATE FIELD EFFECT TRANSISTORS

GLOBALFOUNDRIES Inc., Gr...

1. An integrated semiconductor structure comprising:
a field effect transistor (FET) having a metal gate adjacent to an interlayer dielectric (ILD) on top of a source and drain,
the metal gate surrounded by a gate work function metal, the gate work function metal surrounded by a gate dielectric and
the gate dielectric abutting to a sidewall spacer,

an oxygen blocking layer above a planarized top surface of the metal gate and spanning across the gate dielectric, the ILD,
the entire source and the entire drain, wherein the work function metal and the metal gate each have a top and wherein the
gate dielectric further comprising a recess to a level below the top of the work function metal and below the top of the metal
gate, the oxygen blocking layer fills the entire recess, and wherein the gate dielectric and the oxygen blocking layer comprise
different materials, and

a dielectric layer directly over the oxygen blocking layer, the gate dielectric and the ILD, the dielectric layer only in
direct contact with the oxygen blocking layer.

US Pat. No. 9,263,541

ALTERNATIVE GATE DIELECTRIC FILMS FOR SILICON GERMANIUM AND GERMANIUM CHANNEL MATERIALS

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a semiconductor structure, the method comprising:
performing a surface oxidation of a semiconductor substrate to form an interfacial oxide layer;
depositing a first dielectric layer on the interfacial oxide layer;
performing a densifying process to densify the surface oxidation of said first dielectric layer; and
depositing a second dielectric layer on the first dielectric layer.

US Pat. No. 9,865,608

METHOD OF FORMING A DEVICE INCLUDING A FLOATING GATE ELECTRODE AND A LAYER OF FERROELECTRIC MATERIAL

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
providing a semiconductor structure, said semiconductor structure comprising a semiconductor substrate and a gate stack, said
gate stack comprising a gate insulation material over said substrate, a floating gate electrode material over said gate insulation
material, a ferroelectric transistor dielectric over said floating gate electrode material and a top electrode material over
said ferroelectric transistor dielectric;

performing a first patterning process, said first patterning process removing portions of said top electrode material and
said ferroelectric transistor dielectric, portions of said top electrode material and said ferroelectric transistor dielectric
that are not removed in said first patterning process forming an upper portion of a gate structure, portions of said floating
gate electrode material and said gate insulation material that are not covered by said upper portion of said gate structure
remaining in said semiconductor structure;

forming a liner layer above said gate stack after performing said first patterning process;
forming a mask layer above a portion of said liner layer above said upper portion of said gate structure; and
performing a second patterning process after said first patterning process using said liner layer and said mask layer, said
second patterning process removing portions of said first liner layer, said floating gate electrode material, and said gate
insulation material not covered by said mask layer, portions of said floating gate electrode material and said gate insulation
material that are not removed in said second patterning process forming a lower portion of said gate structure;

wherein a projected area of said upper portion of said gate structure onto a plane that is perpendicular to a thickness direction
of said substrate is smaller than a projected area of said lower portion of said gate structure onto said plane.

US Pat. No. 9,245,960

LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED AIRGAP FIELD PLATES

GLOBALFOUNDRIES Inc., Gr...

1. A field effect transistor comprising:
an insulator layer;
a semiconductor body on said insulator layer, said semiconductor body being essentially rectangular in shape and having a
bottom surface immediately adjacent to said insulator layer, a top surface opposite said bottom surface, opposing sidewalls,
a first end and a second end opposite said first end, and said semiconductor body comprising:

a source region within said semiconductor body at said first end;
a drain region within said semiconductor body at said second end;
a channel region within said semiconductor body positioned laterally adjacent to said source region; and
a drain drift region within said semiconductor body extending laterally from said channel region to said drain region;
dielectric field plates on said insulator layer positioned laterally immediately adjacent to said opposing sidewalls, respectively,
such that said drain drift region is positioned between and immediately adjacent to said dielectric field plates;

conductive field plates on said insulator layer positioned laterally immediately adjacent to said dielectric field plates
such that each dielectric field plate is between said drain drift region and a conductive field plate,

said dielectric field plate having a width that increases along a length of said drain drift region from said channel region
to said drain region such that a distance between said drain drift region and said conductive field plate increases along
said length of said drain drift region,

said dielectric field plate comprising a cavity filled with any one of air and gas,
said cavity having an essentially triangular shaped cross-section through a plane that is parallel to said top surface of
said semiconductor body, and

said conductive field plate being longer than said cavity and extending laterally beyond said cavity toward said drain region;
and,

a dielectric cap layer above and immediately adjacent to top surfaces of said conductive field plates and said semiconductor
body, said dielectric cap layer further extending laterally over and covering said cavity.

US Pat. No. 9,122,830

WIDE PIN FOR IMPROVED CIRCUIT ROUTING

GLOBALFOUNDRIES Inc., Gr...

1. An integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal
layer (M2) wire at a via, wherein the M1 pin has a width at least equal to a width at a first horizontal side of the via and
at least equal to a second width at a second horizontal side of the via sufficient to satisfy an enclosure rule for the via,
wherein the M1 pin and the M2 pin each entirely enclose the via, and wherein the M1 pin extends vertically past the via towards
an adjacent power rail a distance substantially equal to zero.

US Pat. No. 9,286,980

CONVERTING AN XY TCAM TO A VALUE TCAM

GLOBALFOUNDRIES INC., Gr...

1. An integrated circuit ternary content addressable memory (TCAM) system, comprising:
an array of XY TCAM cells;
respective translation circuits connected to respective pairs of the XY TCAM cells; and
a memory controller structured to provide control signals to the respective translation circuits, wherein the memory controller
and respective translation circuits are structured to control the array of XY TCAM cells to perform single cycle update and
single cycle search operations,

wherein each of the respective translation circuits is configured to:
receive an external data in signal and an external bit enable signal from the memory controller;
provide a first data in signal and a first bit enable signal to a first cell of one of the respective pairs of the XY TCAM
cells; and

provide a second data in signal and a second bit enable signal to a second cell of the one of the respective pairs of the
XY TCAM cells.

US Pat. No. 9,251,825

BACKWARD COMPATIBLE HEAD FOR QUASI-STATIC TILTED READING AND/OR RECORDING

GLOBALFOUNDRIES INC., Gr...

1. An apparatus, comprising:
a first module having a first array of N+1 transducers; and
a second module having a second array of N+1 transducers,
wherein an axis of each array is defined between opposite ends thereof,
wherein the axes of the arrays are oriented about parallel to each other,
wherein no more than N of the N+1 transducers of the first array of the first module are about aligned with N of the N+1 transducers
of the second array of the second module when the axes of the arrays are positioned towards a first position, the first position
being characterized by the axes of the arrays each being oriented at a first angle greater than about 0.1° relative to a line
oriented perpendicular to an intended direction of tape travel thereacross.

US Pat. No. 9,478,662

GATE AND SOURCE/DRAIN CONTACT STRUCTURES FOR A SEMICONDUCTOR DEVICE

GLOBALFOUNDRIES Inc., Gr...

1. A semiconductor device, comprising:
a substrate;
a source/drain region defined in said substrate;
a conductive gate structure;
a dielectric layer disposed above said source/drain region and said conductive gate structure;
a first conductive contact positioned in said dielectric layer that conductively contacts said conductive gate structure,
wherein a first dielectric spacer is disposed on all sidewalls of said first conductive contact; and

a second conductive contact positioned in said dielectric layer that conductively contacts said source/drain region, wherein
said first dielectric spacer at least partially defines a spacing between said first conductive contact and said second conductive
contact.

US Pat. No. 9,099,353

METHOD AND SYSTEM FOR DETERMINING OVERLAP PROCESS WINDOWS IN SEMICONDUCTORS BY INSPECTION TECHNIQUES

GLOBALFOUNDRIES Inc., Gr...

12. A method, comprising:
forming a first combined pattern from a first layout layer and a second layout layer of a semiconductor device in a material
layer formed in a first test region of a substrate, said first and second layout patterns defining an overlap area;

forming a second combined pattern from said first layout layer and said second layout layer in said material layer formed
in a second test region of said substrate, said second combined pattern including a geometric modulation relative to said
first combined pattern, wherein each of said first and second combined patterns is formed by sequentially using a first lithography/etch
sequence and a second lithography/etch sequence;

performing an inspection process at least for said overlap area in said first and second test regions; and
determining a validity of at least one of a process flow and a layout design of said overlap area by using a result of said
inspection process.

US Pat. No. 9,466,723

LINER AND CAP LAYER FOR PLACEHOLDER SOURCE/DRAIN CONTACT STRUCTURE PLANARIZATION AND REPLACEMENT

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
forming a placeholder source/drain contact structure above a semiconductor material;
performing a conformal deposition process to form a liner layer above said placeholder source/drain contact structure;
forming a dielectric layer above said liner layer;
performing a first planarization process to remove material of said dielectric layer and expose a first top surface of said
liner layer above said placeholder source/drain contact structure;

forming a first cap layer above said dielectric layer and said first top surface;
performing a second planarization process to remove material of said first cap layer and said liner layer to expose a second
top surface of said placeholder source/drain contact structure;

removing said placeholder source/drain contact structure to define a source/drain contact recess in said dielectric layer,
wherein sidewalls of said dielectric layer in said source/drain contact recess are covered by said liner layer; and

forming a conductive material in said source/drain contact recess.

US Pat. No. 9,293,439

ELECTRONIC MODULE ASSEMBLY WITH PATTERNED ADHESIVE ARRAY

GLOBALFOUNDRIES Inc., Gr...

1. A method for fabricating an electronic module assembly, comprising:
placing a chip on a laminate;
forming a seal band on the laminate;
depositing a patterned array of stabilizing lid ties to the laminate, wherein depositing a patterned array of lid ties to
the laminate comprises depositing an outer ring of lid ties and an inner ring of lid ties comprised of silicone adhesive,
and wherein the outer ring and inner ring each form a perimeter around the chip;

applying a lid on to the seal band; and
curing the electronic module assembly.

US Pat. No. 9,291,665

EVALUATING TRANSISTORS WITH E-BEAM INSPECTION

GLOBALFOUNDRIES INC., Gr...

1. A test structure of a semiconductor wafer, the test structure comprising:
a series of electrical units connected electrically in series output-to-input in an open loop configuration, the series of
electrical units configured to have alternating output voltages, such that each electrical unit is configured to output a
voltage opposite an output voltage of a preceding electrical unit, and such that each electrical unit is configured to have
an output voltage that alternates when an input voltage applied to a first electrical unit in the series of electrical units
alternates,

wherein the series of electrical units is a series of latches, and
wherein each latch of the series of latches comprises two pairs of cross-coupled FETs, wherein a gate of a first pair of the
FETs is connected to a drain-to-drain connection of the second pair of the FETs, and a gate of the second pair of the FETs
is connected to a drain-to-drain connection of the first pair of the FETs.

US Pat. No. 9,293,551

INTEGRATED MULTIPLE GATE LENGTH SEMICONDUCTOR DEVICE INCLUDING SELF-ALIGNED CONTACTS

GLOBALFOUNDRIES INC., Gr...

1. A method of fabricating a multi-gate semiconductor device, the method comprising:
forming a first gate void in a semiconductor substrate and a second gate void in the semiconductor substrate, the first gate
void having a first length and the second gate void a second length greater than the first length;

forming a gate dielectric layer in the first and second gate voids;
forming a first plurality of work function metal layers on the gate dielectric layer of the first gate void and forming a
second plurality of work function metal layers on the gate dielectric layer of the second gate void, the second plurality
of work function metal layers including a portion of the first plurality of work function metal layers such that the second
plurality of work function metal layers has a greater number of layers than the first plurality of work function metal layers;

etching the first plurality of work function metal layers to form a first gate cavity and etching the second plurality of
work function metal layers to form a second gate cavity;

forming a barrier layer in the first and second gate cavities; and
forming metal gate stacks in the first and second cavities and on an exposed surface of the barrier layer,
wherein the forming the second plurality of work function metal layers on the gate dielectric layer of the second gate void
comprises:

forming a first work function metal layer directly on the gate dielectric layer;
forming a second work function metal layer on the first work function metal layer;
forming a third work function metal layer on the second work function metal layer; and
forming a fourth work function metal layer on the third work function metal layer.

US Pat. No. 9,196,548

METHODS OF USING A TRENCH SALICIDE ROUTING LAYER

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:
providing on a substrate at least one gate structure;
providing first and second fin structures in a vertical direction intersecting with the at least one gate structure;
providing first, second, and third sets of segments of a salicide layer, each of the first, second, and third sets having
different vertical positions, separated from each other by a gate structure of the at least one gate structure, wherein the
second set separates the first and third sets, and each of the sets of segments comprises segments having a length extending
along a horizontal direction perpendicular to the vertical direction;

providing a first segment in the first set of segments of the salicide layer, the first segment being connected with the second
fin structure and separated from the first fin structure; and

providing a second segment in the second set of segments of the salicide layer, the second segment selectively connecting
with the first fin structure and separating from the second fin structure,

wherein positions of the segments of the salicide layer determine selection between a 1-1-2 type of static random access memory
(SRAM) configuration and a 1-2-2 type of SRAM configuration.

US Pat. No. 9,601,379

METHODS OF FORMING METAL SOURCE/DRAIN CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES WITH GATE ALL AROUND CHANNEL STRUCTURES

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a nanowire device comprising multiple nanowires, a channel region and a plurality of source/drain regions,
the method comprising:
forming a plurality of stacked substantially un-doped nanowire structures above a semiconductor substrate, said plurality
of stacked substantially un-doped nanowire structures comprising a first plurality of nanowires made of a first semiconductor
material and a second plurality of nanowires made of a second semiconductor material that is different than said first semiconductor
material;

forming a sacrificial structure around said plurality of stacked substantially un-doped nanowire structures at a location
that corresponds to said channel region of said device;

forming a layer of insulating material above and adjacent said plurality of stacked substantially un-doped nanowire structures
and proximate said sacrificial structure;

removing said sacrificial structure to define a cavity that exposes said plurality of stacked substantially un-doped nanowire
structures within said cavity;

performing a selective etching process through said cavity to remove said second plurality of nanowires from said channel
region and said source/drain regions of said device while leaving said first plurality of nanowires in position;

forming a metal conductive source/drain contact structure in each of said source drain regions, wherein each of said metal
conductive source/drain contact structures is positioned all around said first plurality of nanowires positioned in said source/drain
region; and

forming a gate all around gate structure that is positioned all around each of said first plurality of nanowires positioned
in said channel region of said device.

US Pat. No. 9,735,063

METHODS FOR FORMING FIN STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A method for forming an intermediate semiconductor structure, the method comprising:
providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed
thereon;

removing upper portions of the first at least one dielectric material to expose upper portions of the first and the second
plurality of fins comprising:

depositing a first blocking material over the first and second plurality of fins having the first at least one dielectric
material disposed thereon;

removing an upper portion of the first blocking material so that upper portions of the first and second plurality of fins
with the first least one dielectric material extends above the remaining first blocking material;

removing upper portions of the first at least one dielectric material disposed above the remaining first blocking material
to expose upper portions of the first and second plurality of fins; and

removing the remaining first blocking material;
removing the first at least one dielectric material from the lower portions of the second plurality of fins to expose lower
portions of the second plurality of fins;

depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality
of fins and on the upper exposed portions of first plurality of fins;

removing the second at least one dielectric material to expose upper portions of the first and the second plurality of fins;
and

wherein the first at least one dielectric material is different from the second at least one dielectric material.

US Pat. No. 9,472,651

SPACERLESS FIN DEVICE WITH REDUCED PARASITIC RESISTANCE AND CAPACITANCE AND METHOD TO FABRICATE SAME

GLOBALFOUNDRIES INC., Gr...

1. A method to fabricate a device, comprising:
providing a substrate comprised of an insulator layer having a plurality of elongated semiconductor fin structures disposed
on a surface of the insulator layer, the fin structures being disposed substantially parallel to one another;

forming on the surface of the insulator layer a plurality of elongated sacrificial gate structures each comprised of silicon
nitride, the sacrificial gate structures being disposed substantially parallel to one another and orthogonal to the fin structures,
where a portion of each of a plurality of adjacent fin structures is embedded within one of the sacrificial gate structures
leaving other portions exposed between the sacrificial gate structures;

epitaxially depositing a plurality of semiconductor source/drain (S/D) structures over exposed portions of the fin structures
between the sacrificial gate structures, the S/D structures having a faceted shape with bottom edges adjacent to the sacrificial
gate structures and angled sidewalls extending upwards away from the sacrificial gate structures such that the angled sidewalls
of the S/D structures are physically separated from the sacrificial gate structures by spaces;

forming a layer of oxide over the S/D structures, wherein portions of the layer of oxide completely fill each space that extends
laterally between an angled sidewall of a S/D structure and an adjacent sacrificial gate structure;

removing the sacrificial gate structures and replacing the removed sacrificial gate structures with gate structures each comprised
of a layer of gate dielectric and gate metal;

forming trenches parallel to and between the gate structures, the trenches extending through the layer of oxide and through
an underlying portion of the S/D structures and fin structures to the surface of the insulator layer thereby separating an
underlying portion of a given one of the S/D structure and fin structure and forming an opening in the S/D structure and fin
structure between two opposing ends of the separated S/D structure and fin structure; and

forming S/D contacts in the trenches so as to contact, for the given one of the S/D contacts, the two opposing ends of the
separated S/D structure and fin structure, wherein additional portions of the layer of oxide are disposed between and in contact
with the S/D contacts and the gate structures.

US Pat. No. 9,208,451

AUTOMATIC IDENTIFICATION OF INFORMATION USEFUL FOR GENERATION-BASED FUNCTIONAL VERIFICATION

GlobalFoundries Inc., Gr...

1. A computer-implemented method, the method performed by a computerized device, the method comprising:
performing repeatedly:
operating an instruction generator associated with a Design Under Test (DUT) to determine a generated instruction, the generated
instruction having one or more instruction attributes; and

simulating execution of the generated instruction by the DUT;
collecting, based on said simulating, information relating to one or more output architectural properties of the generated
instruction;

based on the generated instruction and the collected information, utilizing a classification technique to classify the information
based on the instruction attributes; and

based on the classified information, determining prediction rules that predict under which instruction attributes the generated
instruction is expected to hold a target output architectural property.

US Pat. No. 9,913,405

GLASS INTERPOSER WITH EMBEDDED THERMOELECTRIC DEVICES

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a Peltier device, comprising:
forming vias including a first via, a second via and a third via in a glass interposer by etching the glass interposer to
form openings that extend only through an upper portion of the glass interposer, such that the vias have a bottom that is
separated from a bottom surface of the glass interposer by a lower portion of the glass interposer;

forming a top seed layer on the glass interposer and in the vias;
depositing an n-type semiconductor material in the first via;
depositing a p-type semiconductor material in the second via; and
depositing an electrically conductive material in the third via and over the first and second vias, wherein the electrically
conductive material is in direct contact with an upper surface of the n-type semiconductor material in the first via and in
direct contact with an upper surface of the p-type semiconductor material in the second via.

US Pat. No. 9,312,387

METHODS OF FORMING FINFET DEVICES WITH ALTERNATIVE CHANNEL MATERIALS

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a FinFET device in and above a substrate comprised of silicon, comprising:
forming a doped fin for said device, said doped fin comprising a doped region that extends at least throughout a vertical
height and a lateral width of said doped fin and at least into a portion of said substrate positioned vertically under said
doped fin;

forming a layer of germanium, silicon/germanium (SixGe1-x) or a III-V semiconductor material around at least a portion of said doped fin; and

forming a gate structure around at least a portion of said layer of germanium, silicon/germanium or III-V semiconductor material
above said portion of said doped fin to define a channel region of said FinFET device in said portion of said layer of germanium,
silicon/germanium or III-V semiconductor material, wherein said gate structure includes a gate insulation layer formed above
said layer of germanium, silicon/germanium or III-V semiconductor material and a gate electrode formed above said gate insulation
layer.

US Pat. No. 9,159,816

PNP BIPOLAR JUNCTION TRANSISTOR FABRICATION USING SELECTIVE EPITAXY

GLOBALFOUNDRIES INC., Gr...

1. A lateral PNP bipolar junction transistor formed using a device region having a top surface, the lateral PNP bipolar junction
transistor comprising:
a base comprised of n-type semiconductor material;
a first base contact positioned at a location on the top surface of the device region that is in vertical alignment with the
base;

a second base contact in the device region, the second base contact aligned vertically with the first base contact, and the
second base contact comprised of an n-type semiconductor material;

an emitter comprised of p-type semiconductor material having the epitaxial relationship with the device region; and
a collector comprised of the p-type semiconductor material having the epitaxial relationship with the device region,
wherein the emitter and the collector are each in contact with the top surface of the device region, and the first base contact
and the base are laterally positioned between the emitter and the collector.

US Pat. No. 9,478,663

FINFET DEVICE INCLUDING A UNIFORM SILICON ALLOY FIN

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
forming a fin on a semiconductor substrate;
forming recesses on sidewalls of said fin;
epitaxially growing a silicon alloy in said recesses; and
performing a thermal process to define a silicon alloy fin portion from said silicon alloy material and said fin, wherein
an alloy component in said silicon alloy component mixes with a material of said fin to provide a uniform diffusion of said
alloy component in said silicon alloy fin portion.

US Pat. No. 9,384,006

APPARATUS AND METHODS FOR AUTOMATICALLY REFLECTING CHANGES TO A COMPUTING SOLUTION INTO AN IMAGE FOR THE COMPUTING SOLUTION

GLOBALFOUNDRIES INC., Gr...

1. A computer-implemented method executed by at least one processor for providing a computing solution, the method comprising:
providing a boot device that comprises a computer readable non-transitory storage that includes a bootable image that comprises:
boot code executed by the at least one processor that initializes an apparatus;
requirements for the computing solution that include at least one software application and business logic;
a system verification and integration mechanism; and
a building and integration mechanism;
booting a computer system from the bootable image on the boot device;
the system verification and integration mechanism comparing available hardware and software with the requirements for the
computing solution and determining computing resources from the available hardware and software that meet the requirements
for the computing solution; and

the building and integration mechanism automatically provisioning the computing resources with the at least one software application
and the business logic without intervention of a human user to provide the computing solution, detecting changes made to the
computing solution after the building and integration mechanism automatically provisions the computing resources, and reflecting
the changes made to the computing solution in the bootable image.

US Pat. No. 9,252,807

EFFICIENT ONE-PASS CACHE-AWARE COMPRESSION

GLOBALFOUNDRIES INC., Gr...

1. A method for efficient one-pass cache-aware compression by a processor device in a computing storage environment, the method
comprising:
linking an output of a fast compressor to Huffman encoding for achieving the one-pass cache-aware compression by using a predetermined
Huffman-tree upon determining by the fast compressor a final representation of each data byte; and

retaining relevant data in an L1 cache during the Huffman encoding process without extracting data from an L2 cache during
the Huffman encoding.

US Pat. No. 9,251,610

LOCATION INFO-GRAPHICS VISUALIZATIONS

GLOBALFOUNDRIES INC., Gr...

1. A computerized visualization method for illustrating multi-dimensional data, comprising:
receiving a plurality of location data points, each location data point having a plurality of measured features;
choosing at least one location dimension from received said plurality of measured features;
grouping said plurality of location data points into a plurality of location groups according to chosen said at least one
location dimension;

plotting, by a processor, said plurality of location groups as a plurality of flower charts, each said plurality of flower
charts, having a plurality of pie sectors, illustrates remaining said plurality of measured features subsequent to said choosing
at least one location dimension;

positioning each said plurality of flower charts, in a visual representation, according to chosen said plurality of location
dimensions;

wherein each said plurality of pie sectors has at least one segment and any two pixels of same at least one segment have an
identical color value; and

wherein a plurality of segments of said plurality of pie sectors is organized according to opacity having a series of graduated
tones ranging from black to white.

US Pat. No. 9,178,019

FIN ISOLATION IN MULTI-GATE FIELD EFFECT TRANSISTORS

GLOBALFOUNDRIES INC., Gr...

1. A field effect transistor (FET) device, comprising:
a first plurality of semiconductor fins on a substrate;
a second plurality of fins on the substrate;
an isolation fin that includes a dielectric material on the substrate, the isolation fin disposed between the first plurality
of semiconductor fins and the second plurality of semiconductor fins;

distal ends disposed at individual pairs of the first and second plurality of semiconductor fins, the distal ends comprising
the dielectric material of the isolation fin so as to physically connect the individual pairs of semiconductor fins, while
maintaining electrical isolation of the individual pairs of semiconductor fins; and

a gate stack over the first and second plurality of semiconductor fins and the isolation fin.

US Pat. No. 9,093,467

METHODS OF FORMING GATE STRUCTURES FOR SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND THE RESULTING DEVICES

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a replacement gate structure above a substrate, comprising:
forming a sacrificial gate structure above a surface of said substrate, said sacrificial gate structure comprising a sacrificial
gate electrode;

forming a sidewall spacer adjacent opposite sides of said sacrificial gate electrode;
forming a layer of insulating material adjacent said sidewall spacers;
performing at least one first etching process to remove a portion, but not all, of said sacrificial gate electrode so as to
thereby define a recessed sacrificial gate electrode having a recessed upper surface;

performing at least one second etching process to recess said sidewall spacers so as to define recessed sidewall spacers positioned
adjacent said recessed sacrificial gate electrode, wherein said recessed sidewall spacers have a recessed upper surface that
is positioned above said surface of said substrate and wherein said recessed upper surface of said recessed sidewall spacers,
said recessed upper surface of said recessed sacrificial gate electrode and said layer of insulating material define a gate
opening;

forming a plurality of sidewall spacers above said recessed upper surface of said sidewall spacers within said gate opening,
said plurality of sidewall spacers comprising one low-k spacer comprised of an insulating material having a dielectric constant
equal to or less than 3.9 that is positioned laterally between two other spacers of said plurality of sidewall spacers;

after forming said plurality of sidewall spacers, removing at least said recessed sacrificial gate electrode so as to define,
at least in part, a replacement gate cavity;

forming a replacement gate structure within said replacement gate cavity; and
forming a gate cap layer within said replacement gate cavity above said replacement gate structure.

US Pat. No. 9,076,645

METHOD OF FABRICATING AN INTERLAYER STRUCTURE OF INCREASED ELASTICITY MODULUS

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:
fabricating a circuit structure, the fabricating comprising:
providing an interlayer structure above a substrate, the interlayer structure comprising porogens dispersed within a dielectric
material; and

pulse laser annealing the interlayer structure to form a treated interlayer structure, the pulse laser annealing polymerizing
the dielectric material of the interlayer structure to form a polymeric dielectric material, wherein the polymeric dielectric
material comprises pores disposed therein, and the pulse laser annealing facilitates increasing elasticity modulus of the
treated interlayer structure by, in part, maintaining structural integrity of the treated interlayer structure, notwithstanding
the pores disposed therein.

US Pat. No. 9,432,754

MAINTAINING A FABRIC NAME ACROSS A DISTRIBUTED SWITCH

GLOBALFOUNDRIES INC., Gr...

1. A method for managing a distributed Fibre Channel over Ethernet (FCoE) fabric in which Fibre Channel frames are encapsulated
in Ethernet frames, the method comprising:
transmitting from a first FCoE data-plane forwarder (FDF) to a controlling FCoE forwarder (cFCF) of the distributed Fibre
Channel fabric a discovery advertisement message containing a fabric name field comprising a zero value;

receiving a unicast discovery solicitation message from the cFCF;
instantiating a switch link between the cFCF of the distributed Fibre Channel fabric and the first FDF responsive to accepting
a request to establish the switch link comprising VA_port to VA_port link, wherein the distributed Fibre Channel fabric further
comprises a set of FDFs, and wherein a VA_port is an instance of an FC-2V sublevel of the Fibre Channel;

receiving, from the cFCF, a distributed switch membership distribution (DFMD) message, wherein the DFMD message contains a
fabric name identifying the distributed Fibre Channel fabric; and

modifying the first FDF to join the distributed Fibre Channel fabric based on the fabric name contained in the DFMD message.

US Pat. No. 9,424,992

COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF MANUFACTURE

GLOBALFOUNDRIES INC., Gr...

1. A method of forming complimentary metal-insulator-metal (MIM) capacitors comprising forming a high density capacitor and
a low density capacitor on a same level both having a bottom plate, a top plate and a high-k dielectric, the method further
comprising:
depositing a low-k dielectric on the bottom plate;
etching the low-k dielectric to remove it from an area of the bottom plate where the high density capacitor will be formed,
such that the high density capacitor will be devoid of the low-k dielectric; and

depositing a high-k dielectric, with a dielectric constant higher than the low-k dielectric, on the area of the bottom plate
and on the low-k dielectric, such that the high-k dielectric is deposited for both the high density capacitor and the low
density capacitor at a same time.

US Pat. No. 9,318,345

ENHANCING TRANSISTOR PERFORMANCE BY REDUCING EXPOSURE TO OXYGEN PLASMA IN A DUAL STRESS LINER APPROACH

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
forming a first strain-inducing dielectric layer above a first transistor and a second transistor of a semiconductor device;
selectively removing a portion of said first strain-inducing layer from above said second transistor by covering said first
transistor with a resist mask and performing a first plasma assisted etch process in a first processing chamber using a first
process environment;

moving said semiconductor device from said first processing chamber to a second processing chamber;
removing said resist mask by performing a second plasma assisted process in said second processing chamber using a second
process environment that is different from said first process environment;

forming a second strain-inducing dielectric layer above said first transistor and said second transistor;
selectively removing said second strain-inducing dielectric layer from above said first transistor in a third process environment
by using a resist mask formed above said second transistor; and

removing said resist mask in a fourth process environment that is different from said first and third process environments.

US Pat. No. 9,312,371

BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATION

GLOBALFOUNDRIES Inc., Gr...

1. A structure comprising:
a bipolar junction transistor comprising:
a substrate comprising a plurality of fins extending above the substrate;
a plurality of base regions having a first conductivity type, the plurality of base regions comprising center portions of
the plurality of fins;

a plurality of emitter regions having a second conductivity type, the plurality of emitter regions comprising first upper
portions of the plurality of fins;

a plurality of collector regions having the second conductivity type, the plurality of collector regions comprising second
upper portions of the plurality of fins; and,

a base region overlie structure disposed over, in part, the plurality of base regions, the base region overlie structure separating
the plurality of emitter regions from the plurality of collector regions and aligning to the plurality of base regions.

US Pat. No. 9,250,890

OPTIMIZING PERFORMANCE OF A COMPUTER SYSTEM IN RESPONSE TO A SOFTWARE CHANGE

GLOBALFOUNDRIES INC., Gr...

1. A method for optimizing a performance of a computer system running a computer program after the program has undergone a
change, the method comprising:
the computer system selecting, from a set of components of the computer program, a set of first-generation candidate components
that have a likelihood of being affected by a varying of a characteristic of a variable comprised by the computer program;

the computer system confirming that each component of a subset of the set of first-generation candidate components would actually
be affected by the varying; and

the computer system further selecting from the set of components of the computer program a set of next-generation candidate
components, wherein a second-generation component of the set of next-generation candidate components is identified as having
a likelihood of being affected by a change to any first-generation component of the subset of the set of first-generation
candidate components.

US Pat. No. 9,076,815

SPACER STRESS RELAXATION

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a transistor structure comprising:
forming a gate structure above an active region of a semiconductor layer,
forming a first spacer element on the sidewalls of said gate structure, said first spacer element having an internal stress;
forming an intermediate spacer layer on said first spacer element;
forming a second spacer element on said intermediate spacer element, said second spacer element having an internal stress;
forming a metal silicide layer that has an interface with said semiconductor layer;
removing a portion of said second spacer element after forming said metal silicide layer, wherein said second spacer element
is only partially removed so as to leave a residual portion of said second spacer element; and

performing an ion implantation in order to relax the internal stress in said residual portion of said second spacer element
and said first spacer element.

US Pat. No. 9,298,253

ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE

GLOBALFOUNDRIES INC., Gr...

1. An integrated circuit with power gating, the integrated circuit comprising:
a power header switch configured to connect and disconnect any one of a plurality of circuits to a common voltage source,
wherein a powered off circuit is disconnected from the common voltage source; and

a power-up sequencer comprising an initial stages power-up component and a final stages power-up component, wherein the final
stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and wherein
the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off
circuit, the initial stages power-up component being activated in response to receiving a predictive power-up request.

US Pat. No. 9,284,414

FLAME RETARDANT POLYMERS CONTAINING RENEWABLE CONTENT

GLOBALFOUNDRIES INC., Gr...

1. A method of making a flame retardant polymer, comprising the steps of:
providing a biobased diol and a phosphorus-containing monomer, wherein at least 50% of the mass of the biobased diol is obtained
directly from a biological product, and wherein the phosphorus-containing monomer is selected from a group consisting of phosphonic
dichlorides, dichlorophosphates, and combinations thereof;

preparing a polycondensation reaction product of the biobased diol and the phosphorus-containing monomer.

US Pat. No. 9,099,380

METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR AND RESULTING DEVICE

GLOBALFOUNDRIES Inc., Gr...

1. A device comprising:
a doped silicon substrate;
shallow trench isolation (STI) regions in the silicon substrate; and
carbon-doped silicon (Si:C) formed in a recess formed between STI regions.

US Pat. No. 9,466,692

METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE

INTERNATIONAL BUSINESS MA...

1. A method of fabricating a gate stack for a FinFET device, said method comprising steps of:
after removal of a dummy gate, providing a replacement gate structure by performing steps of:
growing a high-k dielectric layer over an area vacated by the dummy gate;
depositing a thin metal layer over the high-k dielectric layer;
depositing a sacrificial layer over the thin metal layer;
annealing the replacement gate structure comprising the high-k dielectric layer, thin metal layer, and sacrificial layer at
a high temperature of not less than 800° C.;

performing a millisecond anneal;
removing the sacrificial layer; and
depositing a metal layer of low resistivity metal.

US Pat. No. 9,461,169

DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER

GLOBALFOUNDRIES INC., Gr...

1. A method for inducing stress in a semiconductor layer, comprising:
forming a substrate structure, the substrate structure comprising a semiconductor base layer, a buried dielectric layer formed
on the semiconductor base layer, and a semiconductor channel layer formed on the buried dielectric layer;

ion implanting a dopant through an uppermost surface of the semiconductor channel layer and the buried dielectric layer into
the semiconductor base layer to form an amorphized material region only in a portion of the semiconductor base layer that
is in direct contact with the buried dielectric layer;

depositing a stress layer after the amorphized region is formed, wherein the stress layer is directly on a surface of the
semiconductor channel layer that is opposite a surface of the semiconductor channel layer that is in direct contact with the
buried dielectric layer;

annealing the substrate structure to memorize stress in a portion of the semiconductor base layer that is in direct contact
with the buried dielectric layer by recrystallizing the amorphized material, wherein the memorized stress of the semiconductor
base layer induces stress in the semiconductor channel layer;

removing the stress layer; and
forming a gate structure after removing the stress layer, wherein the gate structure is formed on the surface of the semiconductor
channel layer that is opposite the surface of the semiconductor channel layer that is in direct contact with the buried dielectric
layer, and wherein the gate structure includes an electrode layer and a gate dielectric layer that are separate layers from
the substrate structure.

US Pat. No. 9,337,274

FORMATION OF LARGE SCALE SINGLE CRYSTALLINE GRAPHENE

GLOBALFOUNDRIES INC., Gr...

10. A method for transfer of graphene, comprising:
forming a spreading layer of graphene on a silicon carbide (SiC) substrate, the spreading layer having at least one monolayer
of graphene;

depositing a stressor layer on the spreading layer, the stressor layer being configured to apply stress to at least a closest
monolayer of the spreading layer;

bonding a handle substrate to the stressor layer;
splitting the spreading layer by exfoliating the closest monolayer from the spreading layer, leaving remnants of the two-dimensional
material from the at least one monolayer, on the closest monolayer, wherein the closest monolayer remains on the stressor
layer;

depositing a metal over remnants and the closest monolayer;
applying a tape to the metal;
stripping the metal and the tape to remove the remnants from the closest monolayer to provide a single monolayer on the stressor
layer; and

transferring the single monolayer to a third substrate.

US Pat. No. 9,299,841

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:
a plurality of Si fins on a buried oxide layer;
a plurality of replacement metal gate structures extending over the plurality of Si fins and buried oxide, positioned orthogonal
to the plurality of Si fins, the plurality of replacement metal gate structures comprising a gate dielectric, a metal gate
and a nitride capping material, with nitride sidewall spacers;

a doped Si epitaxial material adjacent to the nitride sidewall spacers and on the plurality of Si fins;
a metal material adjacent to the plurality of replacement metal gate structures and on the doped epitaxial material, the metal
material being planar with the capping material;

insulator material on the metal material and the capping material; and
contact studs in the insulator material and extending to the metal material to be in electrical contact with source and drain
regions of the plurality of replacement metal gate structures,

wherein an upper surface of the nitride capping material and an upper surface of the metal material are planar with one another.

US Pat. No. 9,293,556

SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR AND METHOD FOR THE FORMATION THEREOF

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
providing a semiconductor structure comprising a logic transistor region, a ferroelectric transistor region and an input/output
transistor region;

forming an input/output transistor dielectric over at least said input/output transistor region and said logic transistor
region;

removing said input/output transistor dielectric from at least said logic transistor region;
after removing said input/output transistor dielectric from at least said logic transistor region, depositing a logic transistor
dielectric over said semiconductor structure and depositing a first metal over said logic transistor dielectric;

removing said logic transistor dielectric and said first metal from said ferroelectric transistor region; and
forming a ferroelectric transistor dielectric over said ferroelectric transistor region.

US Pat. No. 9,188,578

NANOGAP DEVICE WITH CAPPED NANOWIRE STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A method for forming a nanogap device, said method comprising:
providing a dielectric membrane directly on top of a front-side surface of a semiconductor substrate;
forming a nanowire directly on top of a surface of said dielectric membrane;
forming a first metal pad and a second metal pad directly on top of said nanowire;
depositing an anti-retraction capping material on an upper surface of said nanowire as well as directly on top of the first
metal pad and the second metal pad;

cutting said anti-retraction capping material and said nanowire to provide a first capped nanowire structure and a second
capped nanowire structure, wherein said first capped nanowire structure and said second capped nanowire structure are separated
by a nanogap of less than 3 nanometers

forming an opening in a back-side surface of said semiconductor substrate after said providing said dielectric membrane and
prior to said forming said nanowire;

wherein said opening is formed of a first tapered sidewall and a second tapered sidewall of said semiconductor substrate,
said first tapered sidewall stopping at a first point directly contacting said dielectric membrane and said second tapered
sidewall stopping at a second point directly contacting said dielectric membrane;

wherein said first point is between said first metal pad and said nanogap, such that said first point is closer to said nanogap
than said first metal pad is to said nanogap; and

wherein said second point is between said second metal pad and said nanogap, such that said second point is closer to said
nanogap than said second metal pad is to said nanogap.

US Pat. No. 9,168,571

APPARATUS AND METHOD FOR CONTROLLED ACCESS TO PRESSURIZED FLUID LINES AND TO EXHAUSTED LINES

GLOBALFOUNDRIES INC., Gr...

1. An apparatus, comprising:
a venting and purging system comprising:
a manifold having an isolation valve, a pressure gauge, a purge gas valve and a helium valve; and
a purge gas tank connected to said purge valve and a helium tank connected to said helium valve;
an access device comprising:
a rod body having a longitudinal bore;
a packing fitting attached to a first end of said rod body and a valve attached to an opposite second end of said rod body;
a transverse arm between said first and second ends of said rod body, said transverse arm having a longitudinal bore communicating
with said longitudinal bore of said rod body, said traverse arm connected to said manifold;

an additional transverse arm between said first and second ends of said rod body, said additional transverse arm having an
additional longitudinal bore communicating with said longitudinal bore of said rod body; and

a slideable rod in said longitudinal bore of said rod body, said rod having a first end and an opposite second end, in a first
position of said rod said first end extends through said packing fitting to outside of said rod body and said second end is
completely within said rod body, in a second position of said rod said first end extends through said packing fitting to outside
of said rod body and said second end of said rod extends through and past said valve.

US Pat. No. 9,460,975

DFT STRUCTURE FOR TSVS IN 3D ICS WHILE MAINTAINING FUNCTIONAL PURPOSE

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:
providing a wafer of a three-dimensional (3D) integrated circuit (IC) stack, the wafer having thin and thick metal layers;
forming first and second through-silicon-vias (TSVs) on the wafer, the first and second TSVs laterally separated;
forming an electronic fuse (eFuse) cell between and separated from the first and second TSVs;
forming a flip-flop (FF) adjacent to the second TSV and on an opposite side of the second TSV from the eFuse cell;
connecting the first TSV, the eFuse cell, the second TSV, and the FF in series in an electric circuit; and
testing the first and second TSVs prior to bonding the wafer to a subsequent wafer in the 3D IC stack.

US Pat. No. 9,298,630

OPTIMIZING MEMORY BANDWIDTH CONSUMPTION USING DATA SPLITTING WITH SOFTWARE CACHING

GLOBALFOUNDRIES INC., Gr...

1. A method for data splitting of an array using a software cache, the method run by a processor device of a computer system,
the method comprising:
collecting information for a dominant data access loop and reference code patterns based on data reference pattern analysis,
and for pointer aliasing and data shape based on pointer escape analysis;

selecting a candidate array for data splitting based on the reference code patterns, the pointer aliasing, and the data shape
information, wherein the candidate array is referenced by a dominant data access loop;

determining a data splitting mode by which to split the data of the candidate array, based on the reference code patterns,
the pointer aliasing, and the data shape information;

splitting the data of the candidate array into two or more split arrays, based on the reference code pattern; and
creating a software cache wherein the software cache includes a portion of the data of the two or more split arrays in a transposed
format; and

storing the portion of the data of the two or more split arrays in the transposed format within the software cache and consulting
the software cache during an access of the two or more split arrays.

US Pat. No. 9,275,907

3D TRANSISTOR CHANNEL MOBILITY ENHANCEMENT

GLOBALFOUNDRIES INC., Gr...

1. A semiconductor structure comprising:
multiple fins above a semiconductor substrate,
each of the fins comprising a first semiconductor material and having a center portion and an end portion adjacent to the
center portion,

the center portion comprising a channel region, and
the end portion having a different crystal lattice than the center portion;
a gate adjacent to the center portion of each of the fins;
a gate sidewall spacer adjacent to the gate, the end portion of each of the fins extending laterally beyond the gate and the
gate sidewall spacer;

an epitaxial doped layer covering the end portion of each of the fins and filling any space between adjacent end portions
of adjacent fins, the epitaxial doped layer comprising a second semiconductor material that is different from the first semiconductor
material; and

a nitride layer immediately adjacent to a top surface and sidewalls of the epitaxial doped layer and further abutting the
gate sidewall spacer, the nitride layer being physically separated from the gate by the gate sidewall spacer and not extending
over the gate sidewall spacer and the gate,

the end portion of each of the fins having the different crystal lattice, the epitaxial doped layer, and the nitride layer
comprising a strained source and drain region that induces stress in the channel region, the stress enhancing carrier mobility
within the channel region.

US Pat. No. 10,091,909

METHOD AND DEVICE FOR COOLING A HEAT GENERATING COMPONENT

GLOBALFOUNDRIES INC., Gr...

1. A cooling arrangement, comprising:a heat spreader comprising a first surface, a second surface, at least one heat absorption chamber and at least one heat dissipation chamber, the at least one heat absorption chamber being in thermal contact with the first surface and the at least one heat dissipation chamber being in thermal contact with the second surface and hydraulically coupled to the at least one heat absorption chamber;
at least one heat generating component arranged in thermal contact with the first surface of the heat spreader;
a cooling fluid, filling at least part of the heat absorption chamber and the heat dissipation chamber;
at least one actuator for driving the cooling fluid; and
a controller for generating at least one control signal for the at least one actuator, such that the cooling fluid can be driven through the at least one heat absorption chamber using a plurality of flow patterns;
wherein the heat spreader comprises a plurality of regions and associated temperature sensors, the plurality of temperature sensors are coupled to the controller, and the controller programmed to identify at least one cold region of the heat spreader, the at least one cold region being characterized in that it has a temperature below an average temperature of the plurality of regions, and the controller is further programmed to generate at least one control signal based on the at least one identified cold region, such that the flow of cooling fluid is sourced from the at least one cold region in at least one flow pattern.

US Pat. No. 9,391,180

HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a semiconductor structure, said method comprising:
forming an interfacial intrinsic non-crystalline semiconductor material layer on a surface of a crystalline semiconductor
material;

forming a doped non-crystalline semiconductor material layer on an exposed surface of said interfacial intrinsic non-crystalline
semiconductor material layer; and

forming at least one electrode material portion on an exposed surface of said doped non-crystalline semiconductor material
layer, wherein said interfacial intrinsic non-crystalline semiconductor material layer is hydrogenated, and said doped non-crystalline
semiconductor material layer is non-hydrogenated.

US Pat. No. 9,299,847

PRINTED TRANSISTOR AND FABRICATION METHOD

GLOBALFOUNDRIES INC., Gr...

1. A thin film transistor, comprising:
source, drain and channel regions printed on a passivated transparent substrate;
a gate dielectric formed over the channel region;
a gate conductor formed over the gate dielectric;
a permanent antireflective coating formed over the source region, drain region and gate electrode;
an interlevel dielectric layer formed over the permanent antireflective coating, the permanent antireflective coating and
the interlevel dielectric layer being configured to provide holes for contacting the source region, drain region and gate
electrode; and

contacts formed through the interlevel dielectric layer and the permanent antireflective coating to electrically connect to
the source region, drain region and gate electrode.

US Pat. No. 9,275,898

METHOD TO IMPROVE SELECTIVITY COBALT CAP PROCESS

GLOBALFOUNDRIES INC., Gr...

16. A method comprising:
providing a copper (Cu) filled via in an ultra low-k (ULK) oxide interlayer dielectric (ILD); and
forming a cobalt (Co) cap on the Cu filled via with a selectivity greater than 200 with respect to the ULK oxide ILD by:
depositing cyclopentadienylcobalt dicarbonyl (Co(C5H5)(Co)2) and hydrogen (H2) over the Cu-filled via and the ULK oxide ILD, forming a Co cap;

depositing ultraviolet (UV) cured trimethylsilane (TMS) or tetramethylsilane (4MS) over the Co cap and the ULK oxide ILD;
performing an ammonia (NH3) plasma treatment after depositing the UV cured TMS or 4MS; and

repeating the depositing Co(C5H5)(Co)2 through performing an NH3 plasma treatment steps two (2) times.

US Pat. No. 9,268,886

SETTING SWITCH SIZE AND TRANSITION PATTERN IN A RESONANT CLOCK DISTRIBUTION SYSTEM

GLOBALFOUNDRIES INC., Gr...

1. A method for providing a resonant clocking circuit for reducing power consumed by a clock distribution system in an integrated
circuit, the method comprising:
creating a clock grid including a plurality of resonant structures distributed in the clock grid;
providing a plurality of programmable switches that switch a respective one of the plurality of resonant structures between
a non-resonant mode and a resonant mode, each of the plurality of programmable switches being controllable to progressively
energize the respective one of the plurality of resonant structures;

determining a transition pattern for controlling the plurality of programmable switches to progressively energize the plurality
of resonant structures, and

fabricating an integrated circuit chip comprising the clock grid;
wherein the creating, the providing, and the determining are performed by a design module of a computing device.

US Pat. No. 9,230,940

THREE-DIMENSIONAL CHIP STACK FOR SELF-POWERED INTEGRATED CIRCUIT

GLOBALFOUNDRIES INC., Gr...

1. A stacked three-dimensional integrated circuit, comprising:
a power generation die including a power source;
a power storage and control die including a power controller and one or more storage devices that store power received from
the power source; and

a functional system die including one or more functional components that are powered by power generated by the power source,
wherein the power generation die and the functional system die are stacked in a three-dimensional structure.

US Pat. No. 9,335,368

METHOD AND APPARATUS FOR QUANTIFYING DEFECTS DUE TO THROUGH SILICON VIAS IN INTEGRATED CIRCUITS

GLOBALFOUNDRIES INC., Gr...

1. A device comprising:
a silicon layer having an upper surface, and on a plastic carrier;
a plurality of devices in the silicon layer and electrically coupled through the upper surface to a test control system;
a through silicon via (TSV) extending into the silicon layer; and
a plurality of parallel heating structures, each one of the plurality of heating structures individually controlled and adjacent
to one of the plurality of devices electrically coupled to the test control system.

US Pat. No. 9,299,769

SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING

GLOBALFOUNDRIES INC., Gr...

1. A semiconductor-on-oxide wafer comprising:
a substrate;
a first dielectric layer over the substrate;
a first conductive layer over the first dielectric layer;
a second dielectric layer over the first dielectric layer;
a second conductive layer over a portion of the second dielectric layer, the second conductive layer including a separation,
wherein the second conductive layer includes an additional separation, and the first conductive layer includes a separation
aligned with the additional separation in the second conductive layer;

a third dielectric layer over the second conductive layer; and
a contact extending through the third dielectric layer and the separation in the second conductive layer contacting the first
conductive layer.

US Pat. No. 9,299,777

GATE-ALL-AROUND NANOWIRE MOSFET AND METHOD OF FORMATION

GLOBALFOUNDRIES INC., Gr...

1. A gate-all-around structure for a semiconductor device, comprising:
a substrate;
an insulator layer comprising silicon dioxide disposed on the substrate;
a nanowire substantially laterally disposed on the insulator layer;
a source region disposed in communication with a first end of the nanowire;
a drain region disposed in communication with a second end of the nanowire;
a gate positioned substantially transverse to the nanowire, a bottom portion of the gate surrounds a portion of the nanowire
between the source region and the drain region, and wherein the width of the bottom portion of the gate is less than the width
of a top portion of the gate; and

a layer of high-k dielectric material disposed on the nanowire between the gate and the nanowire.

US Pat. No. 9,236,437

METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a semiconductor structure, comprising:
forming a plurality of gates in a dielectric layer;
recessing the plurality of gates;
depositing a capping layer over the plurality of gates;
forming a first mask layer having a patterned opening therein;
performing a selective dielectric etch within the patterned opening to form a plurality of source/drain (S/D) cavities;
depositing a source/drain contact metal in the S/D cavities to form a plurality of contact strips;
forming a second mask layer comprising a plurality of regions disposed over a portion of the capping layer and a portion of
an adjacent contact strip of the plurality of contact strips;

performing an etch of the adjacent contact strip to form a source/drain contact.

US Pat. No. 9,231,074

BIPOLAR JUNCTION TRANSISTORS WITH AN AIR GAP IN THE SHALLOW TRENCH ISOLATION

GLOBALFOUNDRIES INC., Gr...

1. A method of fabricating a bipolar junction transistor, the method comprising:
forming a trench isolation region in a substrate and coextensive with a collector in the substrate;
forming a base layer on the collector and on a first portion of the trench isolation region;
forming an emitter on the base layer;
forming a first dielectric layer on the base layer and on a second portion of the trench isolation region peripheral to the
base layer; and

after the first dielectric layer, the base layer, and the emitter are formed, at least partially removing the first portion
and the second portion of the trench isolation region to define an air gap beneath the first dielectric layer and the base
layer.

US Pat. No. 9,157,956

ADAPTIVE POWER CONTROL USING TIMING CANONICALS

GLOBALFOUNDRIES INC., Gr...

1. A method of optimizing power usage in an integrated circuit design, said method comprising:
manufacturing integrated circuit devices according to an integrated circuit design using manufacturing equipment, said integrated
circuit design producing integrated circuit devices that are identically designed and perform at different operating speeds
caused by manufacturing process variations;

determining an operating speed of each of said integrated circuit devices based on delay parameters applied to a canonical
equation that evaluates different threshold voltage portions of each of said integrated circuit devices differently, each
of said different threshold voltage portions of said integrated circuit devices operating at different threshold voltages;

sorting said integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast
integrated circuit devices based on said operating speed of each of said integrated circuit devices to classify said integrated
circuit devices into different voltage bins, said relatively fast integrated circuit devices consuming more power than said
relatively slow integrated circuit devices; and

embedding voltage bin information in said integrated circuit devices based on which of said different voltage bins each of
said integrated circuit devices has been classified, said voltage bin information controlling an operating voltage at which
each of said integrated circuit devices are to be operated.

US Pat. No. 9,159,567

REPLACEMENT LOW-K SPACER

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:
providing a gate structure having a dummy gate, and a first spacer along a side of the dummy gate;
removing the dummy gate and the first spacer to expose a gate dielectric;
depositing a second spacer on at least one side of a gate structure cavity and a top of the gate dielectric;
removing a bottom portion of the second spacer to expose the gate dielectric;
wet cleaning the gate structure; and
exerting stress on the gate structure after the depositing the second spacer and before the removing the bottom portion of
the second spacer.

US Pat. No. 9,362,180

INTEGRATED CIRCUIT HAVING MULTIPLE THRESHOLD VOLTAGES

GLOBALFOUNDRIES INC., Gr...

1. An integrated circuit comprising:
a substrate structure;
a first plurality of field effect transistors formed in the substrate structure, a second plurality of field effect transistors
formed in the substrate structure, a third plurality of field effect transistors formed in the substrate structure, and a
fourth plurality of field effect transistors formed in the substrate structure;

wherein field effect transistors of the first plurality of field effect transistors each have a first channel polarity and
a first gate stack comprising a dielectric layer, a first conductive cap layer overlying the dielectric layer, a second conductive
cap layer overlying the first cap layer, a first work function layer overlying the second conductive cap layer, and a metal
layer overlying the first work function layer;

wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack that comprises
the layers of the first gate stack and the first channel polarity, the first conductive cap layer including a first thickness
at the first gate stack and a second thickness at the second gate stack, wherein the second thickness is different from the
first thickness;

wherein field effect transistors of the third plurality of field effect transistors each have a third gate stack and a channel
polarity opposite the first channel polarity, the third gate stack comprising the layers of the first and second gate stacks
and a second work function layer positioned between the second conductive cap layer and the first work function layer;

wherein field effect transistors of the fourth plurality of field effect transistors each have a fourth gate stack that comprises
the layers of the third gate stack and a channel polarity opposite the first channel polarity, the first conductive cap layer
including the first thickness at the fourth gate stack and the second thickness at the third gate stack;

wherein the second gate stack has a gate material sequence in common with the first gate stack, wherein the fourth gate stack
has a gate material sequence in common with the third gate stack, and wherein the third gate stack has a gate material sequence
that is different from a gate material sequence of the first gate stack;

wherein field effect transistors of the first plurality of field effect transistors each have a first Vt, and wherein field
effect transistors of the second plurality of field effect transistors each have a second Vt, the second Vt being different
from the first Vt.

US Pat. No. 9,318,148

COMBINED SOFT DETECTION/SOFT DECODING IN TAPE DRIVE STORAGE CHANNELS

GLOBALFOUNDRIES INC., Gr...

1. A tape drive system, comprising:
a soft detector, comprising logic configured to:
execute a first forward loop of a detection algorithm on a first block of signal samples during a first time interval;
execute a first reverse loop of the detection algorithm on the first block of signal samples during a second time interval;
execute a second reverse loop of the detection algorithm on the first block of signal samples during a fifth time interval;
and

execute a second forward loop of the detection algorithm on the first block of signal samples during a fourth time interval
using second soft information.

US Pat. No. 9,299,608

T-SHAPED CONTACTS FOR SEMICONDUCTOR DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:
providing a starting semiconductor structure, the structure comprising a semiconductor substrate, an active layer with one
or more active regions, at least one gate over a portion of the active layer, and a layer of filler material on both sides
of the at least one gate;

creating a multi-layer etching stack over the starting structure, the multi-layer etching stack comprising a dielectric layer
between top and bottom hard mask layers, wherein only the dielectric layer and bottom hard mask layers are used as etch stops;
and

creating T-shaped contacts thru the multi-layer etching stack to the one or more active regions and the at least one gate,
wherein each T-shaped contact uses a single fill of bulk conductive material.

US Pat. No. 9,298,625

READ AND WRITE REQUESTS TO PARTIALLY CACHED FILES

GLOBALFOUNDRIES INC., Gr...

1. A method for partial file caching in a clustered file system comprising:
a processor in communication with a cache file system populating data on demand, including populating data as it is being
access from a separate file system and maintaining modifications to cached data and the populated data with the separate file
system;

the processor storing the data on a file system block boundary;
for a read request, the processor aligning the request on the block boundary; and
for a write request, the processor aligning a partial block request to the block boundary.

US Pat. No. 9,269,435

DRIFT MITIGATION FOR MULTI-BITS PHASE CHANGE MEMORY

GLOBALFOUNDRIES INC., Gr...

10. A computer program product for operating a memory cell, a memory cell state being represented by a configuration of amorphous
material in the memory cell, a resistance of the memory cell drifting over a period of time, the computer program product
comprising a computer readable storage device, the computer readable storage device readable by a processing circuit and storing
instructions run by the processing circuit for performing a method to:
apply, by a signal generator, at least one input signal to the memory cell;
measure at least one response signal of the memory cell;
calculate a parameter which is based on the at least one response signal of the said memory cell resulting from the configuration
of the amorphous material in the said memory cell, the parameter being sensitive to the resistance drift characteristic of
the memory cell; and,

determine a memory state and predict a drift behavior of the memory cell based on the calculated parameter.

US Pat. No. 9,490,174

FABRICATING RAISED FINS USING ANCILLARY FIN STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:
fabricating a raised fin structure, the raised fin structure comprising a raised contact structure, comprising:
providing a base fin structure;
providing at least one ancillary fin structure, the at least one ancillary fin structure contacting from the base fin structure
at a side of the base fin structure;

growing a material over the base fin structure to form the raised fin structure;
growing the material over the at least one ancillary fin structure, wherein the at least one ancillary fin structure contacting
the base fin structure increases a volume of material grown over the base fin structure near the contact between the base
fin structure and the at least one ancillary fin structure to form the raised contact structure; and

wherein providing the conductive contact comprises a silicidation process, wherein the silicidation process comprises at least
providing an oxide material over the raised fin structure and etching to remove a portion of the oxide material from over
at least the raised contact structure, wherein a convex shape of the raised contact structure facilitates preventing incomplete
removal of the portion of the oxide material.

US Pat. No. 9,478,600

METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a semiconductor device comprising:
providing an upper semiconductor layer on a dielectric layer, wherein said dielectric layer is present on a base semiconductor
layer;

forming an etch mask on a surface of said upper semiconductor layer, wherein said etch mask comprises a contact opening having
a first width and a capacitor opening having a second width, wherein said first width is of a dimension that is greater than
2 times said value of said second width;

etching a contact trench and a capacitor trench into contact with said base semiconductor layer;
forming a conformal dielectric layer on said contact trench and said capacitor trench;
recessing said conformal dielectric layer within said contact trench and said capacitor trench with an anisotropic etch, wherein
a first remaining portion of said conformal dielectric layer that is present in said contact trench is below said upper surface
of base semiconductor layer to expose a sidewall portion of said base semiconductor layer within said contact trench, and
a second remaining portion of said conformal dielectric layer that is present in said capacitor trench is present on an entirety
of said sidewalls and base portions of said capacitor trench that is present in said base semiconductor layer; and

filling said contact trench and said capacitor trench with a conductive material.

US Pat. No. 9,318,217

PROGRAMMING AN ELECTRICAL FUSE WITH A SILICON-CONTROLLED RECTIFIER

GLOBALFOUNDRIES INC., Gr...

1. A method for programming an electrical fuse using a silicon-controlled rectifier that has a terminal coupled with the electrical
fuse, the method comprising:
directing a programming current for the electrical fuse through the electrical fuse and the silicon-controlled rectifier;
and

switching the silicon-controlled rectifier from a low-impedance state to a high-impedance state that interrupts the programming
current upon reaching a first programmed resistance value for the electrical fuse,

wherein the electrical fuse is a closed electrical circuit after the first programmed resistance value is reached and the
programming current is interrupted.

US Pat. No. 9,287,345

SEMICONDUCTOR STRUCTURE WITH THIN FILM RESISTOR AND TERMINAL BOND PAD

GLOBALFOUNDRIES INC., Gr...

19. A semiconductor structure, comprising:
a last wiring level including a terminal wire, two related wires. and another wire formed in a dielectric material layer;
at least one of a diffusion barrier layer and an isolation layer formed on the dielectric material layer;
a terminal bond pad formed on the terminal wire;
a thin film resistor formed on and conductively linking the two related wires;
a cap formed on the other wire;
a passivation layer formed over the terminal bond pad, the thin film resistor, and the cap; and
an opening formed in the passivation layer over the terminal bond pad,
wherein the terminal bond pad, the thin film resistor, and the cap are composed of portions of a common layer of refractory
metal, and

the passivation layer is a different material than the at least one of the diffusion barrier layer and the isolation layer.


US Pat. No. 9,263,338

SEMICONDUCTOR DEVICE INCLUDING VERTICALLY SPACED SEMICONDUCTOR CHANNEL STRUCTURES AND RELATED METHODS

STMICROELECTRONICS, INC.,...

1. A method for making a semiconductor device comprising:
forming, on a substrate, at least one stack of alternating first and second semiconductor layers, the first semiconductor
layer comprising a first semiconductor material and the second semiconductor layer comprising a second semiconductor material,
the first semiconductor material being selectively etchable with respect to the second semiconductor material;

removing portions of the at least one stack and substrate to define exposed sidewalls thereof;
forming respective spacers on the exposed sidewalls;
etching a plurality of recesses through the at least one stack and substrate to define a plurality of spaced apart pillars;
selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures
supported at opposing ends by respective spacers; and

forming raised source and drain regions overlying opposing ends of the second semiconductor material structures, and forming
at least one gate overlying the second semiconductor material structures between the raised source and drain regions, wherein
portions of the substrate beneath the second semiconductor material structures extend vertically upward into the raised source
and drain regions and the at least one gate.

US Pat. No. 9,224,604

DEVICE AND METHOD FOR FORMING SHARP EXTENSION REGION WITH CONTROLLABLE JUNCTION DEPTH AND LATERAL OVERLAP

GLOBALFOUNDRIES INC., Gr...

1. A method for forming a semiconductor device, comprising:
forming a gate stack on a monocrystalline substrate;
amorphorizing a surface of the substrate adjacent to the gate stack and below a portion of the gate stack;
etching the surface to selectively remove a thickness of amorphorized portions to form undercuts underneath the gate stack,
such that the undercuts are angled, where lower portions of the undercuts extend horizontally farther underneath the gate
electrode than upper portions of the undercuts; and

epitaxially growing a layer in the thickness and the undercuts to form an extension region for the semiconductor device.

US Pat. No. 9,218,956

CAPPING COATING FOR 3D INTEGRATION APPLICATIONS

GLOBALFOUNDRIES INC., Gr...

1. A method of constructing a structure for interconnecting semiconductor components, comprising:
forming a bi-layer capping coating on a layer to be transferred located on a substrate, the bi-layer capping coating comprising
a nitride-containing layer on the layer to be transferred and an amino silane layer on the nitride-containing layer, each
layer of said bi-layer capping coating providing protection and adhesion, wherein said amino silane layer is composed of an
amino silane compound represented by the formula:


wherein:
each of R1 R2, R3 is independently hydrogen, C1-C6 alkyl, C1-C6 acyl, C2-C6 allyl, C2-C6 alkenyl, or C2-C6 alkynyl,

R4 is C1-C6 alkyl, phenyl, or benzyl, and

each of R5 and R6 is independently C1-C6 alkyl, C1-C6 acyl, C2-C6 allyl, C2-C6 alkenyl, or C2-C6 alkenyl;

forming a carrier assembly on the bi-layer capping coating;
removing the substrate such that the layer to be transferred is attached to said carrier assembly to provide a transferred
layer;

joining an exposed surface of the transferred layer to a receiver substrate; and
removing the carrier assembly by an oxygen-based plasma removal process,
wherein said nitride-containing layer protects a metallic element in said transferred layer from said oxygen-based plasma
removal process.

US Pat. No. 9,136,234

SEMICONDUCTOR DEVICE WITH IMPROVED METAL PILLAR CONFIGURATION

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
forming a contact pad above a substrate comprising circuit elements;
forming a conductive protection layer protecting said contact pad;
depositing a passivation layer embedding said contact pad and covering said conductive protection layer;
forming an opening in said passivation layer;
depositing a metal layer system;
forming a metal pillar on said metal layer system in said opening; and
removing exposed portions of said metal layer system to expose a portion of said conductive protection layer.

US Pat. No. 9,484,359

MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE

GLOBALFOUNDRIES INC., Gr...

1. A semiconductor on insulator (SOI) substrate comprising:
a SOI layer;
a first buried insulator (BOX) under the SOI layer;
a metal backgate having a first region and a second region located entirely under the first BOX;
a bulk layer under the metal backgate, wherein the second region of the metal backgate is doped; and
a first gate stack wherein the first region is asymmetrically aligned under the first gate stack.

US Pat. No. 9,466,505

METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
forming a layer of material above a semiconductor substrate;
performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers
above said layer of material, wherein said first plurality of spacers are positioned above a first region of said semiconductor
substrate and said second plurality of spacers are positioned above a second region of said semiconductor substrate, said
first and second pluralities of spacers having a same initial width and a same pitch spacing;

forming a masking layer above said layer of material, said masking layer covering said first plurality of spacers and exposing
said second plurality of spacers; and

performing a first etching process through said masking layer on said exposed second plurality of spacers so as to form a
plurality of reduced-width spacers having a width that is less than said initial width, wherein said first plurality of spacers
and said plurality of reduced-width spacers define an etch mask.

US Pat. No. 9,429,619

RELIABILITY TEST SCREEN OPTIMIZATION

GLOBALFOUNDRIES INC., Gr...

1. A method of optimizing power usage in an integrated circuit design, said method comprising:
manufacturing integrated circuit devices according to an integrated circuit design using manufacturing equipment, said integrated
circuit design producing integrated circuit devices that are identically designed and perform at different operating speeds
caused by manufacturing process variations;

sorting said integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast
integrated circuit devices to classify said integrated circuit devices into different voltage bins, said relatively fast integrated
circuit devices having a smaller delay and consuming more power than said relatively slow integrated circuit devices,

establishing a bin-specific reliability testing processes comprising enhanced voltage screening and dynamic voltage screening
for each of said voltage bins;

performing reliability testing using said bin-specific reliability testing processes for each of said voltage bins on said
integrated circuit devices using a tester;

identifying as defective ones of said integrated circuit devices that fail said bin-specific reliability testing processes
of a corresponding voltage bin into which each of said integrated circuit devices has been classified;

removing said defective ones of said integrated circuit devices to allow only non-defective integrated circuit devices to
remain; and

supplying said non-defective integrated circuit devices to a customer.

US Pat. No. 9,418,902

FORMING ISOLATED FINS FROM A SUBSTRATE

Globalfoundries Inc., Gr...

1. A method of isolating a semiconductor fin from a substrate, the method comprising:
forming a hard mask layer on a top surface of the fin;
forming a masking layer around a base portion of the fin and the substrate;
forming spacers on a top portion of the fin above the masking layer;
removing the masking layer to expose the base portion of the fin and the substrate; and
forming an isolation region from the base portion of the fin, the isolation region electrically insulating the top portion
of the fin from the substrate, wherein forming an isolation region from the base portion of the fin comprises oxidizing or
nitriding the base portion of the fin, and wherein the oxidizing or nitriding comprises performing an ion implantation of
the isolation region with a species selected from the group consisting of oxygen and nitrogen.

US Pat. No. 9,390,979

OPPOSITE POLARITY BORDERLESS REPLACEMENT METAL CONTACT SCHEME

GLOBALFOUNDRIES INC., Gr...

9. A method of forming a semiconductor device comprising:
forming a set of source-drain (s/d) regions and a set of replacement metal gates on a substrate;
forming a set of gate capping regions over the set of replacement metal gates;
forming an oxide layer over the semiconductor device;
forming a set of masks over a portion of the semiconductor device, wherein each mask in the set of masks covers at least one
source/drain (s/d) contact location;

removing the oxide layer from remainder portions of the semiconductor device that are not covered by the set of masks;
removing the set of masks from the entire semiconductor structure;
forming a silicon oxycarbide dielectric layer in the remainder portions of the semiconductor device;
removing the oxide layer from the portion of the semiconductor device previously covered by the set of masks; and
depositing a metal contact layer that forms a contact to the at least one s/d contact location in the portion of the semiconductor
device previously covered by the set of masks.

US Pat. No. 9,297,062

DIRECTED SURFACE FUNCTIONALIZATION ON SELECTED SURFACE AREAS OF TOPOGRAPHICAL FEATURES WITH NANOMETER RESOLUTION

GLOBALFOUNDRIES INC., Gr...

1. A method for making a single molecule receptor in a nanopore structure, the method comprising:
depositing a material by a physical vapor deposition (PVD) technique onto a selected interior surface of a nanochannel, the
material forming a raised patch having a diameter of about 1 to about 100 nanometers (nm) and extending from the selected
area of the interior surface to the nanochannel's opening; and

functionalizing a surface of the material with a chemical compound having at least two functional groups to form the single
molecule receptor;

wherein the single molecule receptor is a binding site with nanometer dimensions that binds to only a single molecule of an
analyte in a complex sample.

US Pat. No. 9,257,336

BOTTOM-UP PLATING OF THROUGH-SUBSTRATE VIAS

GLOBALFOUNDRIES Inc., Gr...

1. A method of plating a through-substrate via (TSV) hole in a substrate, the TSV hole comprising an open end terminating
at a conductive pad, a stack of wiring levels superimposed to one another positioned on top of the conductive pad, and a plurality
of chip interconnects configured on a top surface of an upper wiring level, the method comprising:
attaching a conductive handler to a plurality of temporary solder contacts that are connected to the plurality of chip interconnects
such that an air gap is formed between the handler and the substrate;

exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution;
and applying an electrical potential along an electrical path from the conductive handler to the conductive pad causing conductive
material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including
the conductive handler, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.

US Pat. No. 9,478,538

METHODS FOR FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING DEVICES

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:
forming first and second gate cavities so as to expose first and second portions, respectively, of a semiconductor material;
forming a gate insulation layer in said first and second gate cavities;
forming a first work function material layer in said first gate cavity and a second work function material layer in said second
gate cavity;

selectively forming a first barrier layer above said first work function material layer and said gate insulation layer in
said first gate cavity;

forming a second barrier above said first barrier layer in said first gate cavity and above said second work function material
layer and said gate insulation layer in said second gate cavity; and

forming a conductive material above said second barrier layer in said first and second gate cavities in the presence of a
treatment species to define first and second gate electrode structures, respectively.

US Pat. No. 9,431,540

METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH SIDEWALL SPACERS FOR CONFINING EPITAXIAL GROWTH

STMICROELECTRONICS, INC.,...

1. A method for making a semiconductor device comprising:
forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins;
forming at least one dielectric layer directly contacting the substrate and adjacent an end portion of the plurality of semiconductor
fins and within the space between adjacent semiconductor fins;

forming a pair of sidewall spacers adjacent outermost semiconductor fins at the end portion of the plurality of semiconductor
fins;

removing the at least one dielectric layer and end portion of the plurality of semiconductor fins between the pair of sidewall
spacers; and

forming source/drain regions between the pair of sidewall spacers.

US Pat. No. 9,190,486

INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED PARASITIC CAPACITANCE

GLOBALFOUNDRIES INC., Gr...

1. A method for fabricating an integrated circuit, comprising:
forming a sacrificial gate structure over a semiconductor substrate,
wherein a top surface of the sacrificial gate structure is located a first distance from the semiconductor substrate;
forming a spacer around the sacrificial gate structure;
depositing a dielectric material over the spacer and the semiconductor substrate;
selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material, wherein
the trench is bounded by a trench surface, wherein a top end of the trench surface is located a second distance from the semiconductor
substrate, and wherein the second distance is greater than the first distance; and

depositing a replacement spacer material along the trench surface and merging an upper region of the replacement spacer material
to form a merged upper region of the replacement spacer material, to enclose a void within the replacement spacer material
and to partially enclose a pocket within the replacement spacer material, wherein the void is formed around at least one sidewall
of the sacrificial gate structure, the pocket is formed directly over and overlaps the sacrificial gate structure, and the
pocket does not overlap the void.

US Pat. No. 9,472,241

IDENTIFYING AND RERECORDING ONLY THE INCOMPLETE UNITS OF A PROGRAM BROADCAST RECORDING

GLOBALFOUNDRIES INC., Gr...

1. A system for managing program recordings, comprising:
a computer, comprising at least one processor, configured to check each data integrity value, from among a plurality of data
integrity values each associated with a separate unit of a program comprising a plurality of units, against a separate recorded
portion of a recording of the program corresponding to one of the plurality of units, wherein the recording of the program
is recorded from a broadcast of the program;

the computer, responsive to a particular data integrity value from among the plurality of data integrity values not matching
when checked against a particular separate recorded portion of the program corresponding to a particular unit from among the
plurality of units, configured to select to correct the recording by replacing only the particular separate recorded portion
of the program from a second recording of only the particular unit from a subsequent broadcast of the program; and

the computer configured to receive a communication comprising the plurality of data integrity values from a provider of the
program.

US Pat. No. 9,298,501

CONCURRENT MANAGEMENT CONSOLE OPERATIONS

GLOBALFOUNDRIES INC., Gr...

1. A method for concurrent management console operations comprising:
organizing, by use of a processor, a single software image for a management command, the single software image comprising
parameters that specify a logical unit size for each device of a plurality of devices;

creating a plurality of processes independently executing the management command and employing the single software image on
each of the plurality of devices from a management console, wherein the management console comprises a process recording field;

creating a management command Dynamic Host Configuration Protocol (DHCP) configuration file for the management command;
directing DHCP configuration file accesses to the management command DHCP configuration file;
stopping use of an original DHCP configuration file;
failing a first process of the plurality of processes on a first device of the plurality of devices in response to the first
process writing a status message indicating that the first process is failed to the process recording field;

repairing and resuming the first process in response to failing the first process;
determining that each process of the plurality of processes has completed on each of the plurality of devices in response
to each process writing a status message indicating that the process is complete to the process recording field;

ending the management command after each process has completed; and
replacing the management command DHCP configuration file with the original DHCP configuration file.

US Pat. No. 9,291,702

APPARATUS FOR INDICATING THE LOCATION OF A SIGNAL EMITTING TAG

GLOBALFOUNDRIES INC., Gr...

1. A method for indicating the location of a signal emitting tag, the apparatus comprising:
providing a plurality of signal detectors;
emitting a signal from a signal emitting tag carried by an individual that is collocated with a point of origin of said signal:
receiving said signal at one or more of said plurality of signal detectors;
transmitting the received signal data from the one or more plurality of signal detectors to a control logic;
determining, by said control logic, a location of said signal based on known locations of said one or more plurality of signal
detectors;

activating, by said control logic, at least one visible light producing device in response to the data received from the plurality
of signal detectors and the identified location of said signal;

illuminating, by the control logic, said location of said signal using the at least one visible light producing device to
identify said point of origin of said signal emitting tag based on said signal collocated with the individual; and

monitoring said point of origin of said signal emitting tag, based, at least in part, on the data from the plurality of signal
detectors, for readjusting orientation of the visible light producing device to continuously illuminate the point of origin
of the signal.