US Pat. No. 9,781,834

MAGNETICALLY-COUPLED INDUCTORS ON INTEGRATED PASSIVE DEVICES AND ASSEMBLIES INCLUDING SAME

Ferric Inc., New York, N...

1. An assembly comprising:
a processor chip having opposing first and second sides, the processor chip comprising:
a first multilevel wiring structure; and
a first inductor integrated into said first multilevel wiring network and disposed proximal to the first side of the processor
chip, said first inductor comprising:

a first planar magnetic core; and
a first conductive winding comprising at least a portion of said first multilevel wiring network, said first conductive winding
turning around in a generally spiral manner around said first planar magnetic core;

an integrated passive device (IPD) having opposing first and second sides, the first side of the IPD mounted on the first
side of the processor chip, the IPD comprising:

a second multilevel wiring structure; and
a plurality of passive devices electrically connected to the second multilevel wiring structure, the plurality of passive
devices including a second inductor disposed proximal to the first side of the IPD, the second inductor comprising:

a second magnetic core; and
a second conductive winding comprising at least a portion of said second multilevel wiring structure, said second conductive
winding turning around in a generally spiral manner around said second planar magnetic core,

wherein the first and second inductors are magnetically coupled.

US Pat. No. 9,357,650

METHOD OF MAKING MAGNETIC CORE INDUCTOR INTEGRATED WITH MULTILEVEL WIRING NETWORK

Ferric Inc., New York, N...

1. A method, comprising:
depositing by high-vacuum (HV) sputtering a layer of a magnetic material on a first insulating layer, said first insulating
layer disposed on a first wiring plane of a multilevel wiring network, said magnetic material having a thickness between about
10 nm and 1000 nm;

disposing a second insulating layer over said layer of said magnetic material;
repeating in alternate fashion said depositing step and said disposing step up to about 100 times each, resulting in a magnetic
member with a laminated configuration;

masking and patterning for said magnetic member in such manner that after said patterning a remaining portion of said magnetic
member comprises a planar magnetic core; and

wherein said method is characterized as fabricating a planar inductor suitable for integrating into said multilevel wiring
network that is arranged into wiring planes, wherein said inductor comprises said planar magnetic core.

US Pat. No. 9,357,651

MAGNETIC CORE INDUCTOR INTEGRATED WITH MULTILEVEL WIRING NETWORK

Ferric Inc., New York, N...

1. A processor, comprising:
a semiconductor integrated circuit, wherein said semiconductor integrated circuit comprises a multilevel wiring network, wherein
said semiconductor integrated circuit operates with a plurality of DC supply voltages; and

a DC to DC voltage converter which delivers at least one of said DC supply voltages for said semiconductor integrated circuit,
wherein said DC to DC voltage converter comprises an inductor, and wherein said inductor is integrated thereinto said multilevel
wiring network, wherein said inductor comprises a planar magnetic core and a conductive winding, wherein said conductive winding
turns around in generally spiral manner on the outside of said planar magnetic core, said planar magnetic core having a laminated
configuration comprising at least one layer of a magnetic material and at least one current rectifying layer;

wherein the current rectifying layer comprises a p-type semiconductor, the p-type semiconductor having a first work function
less than a second work function of the magnetic material; and

wherein the laminated configuration further comprises an interface metal layer disposed on said p-type semiconductor, the
interface layer having a work function less than said first work function of said p-type semiconductor.

US Pat. No. 9,906,131

ZERO-VOLTAGE SWITCH-MODE POWER CONVERTER

Ferric Inc., New York, N...

1. A switch-mode power converter comprising:
a bridge node having a bridge voltage;
a first switch having a first input and a first output, the first input having a power converter input voltage, the first
output electrically connected to the bridge node, the first switch having a closed state in which the first input is electrically
connected to the first output and an open state in which the first input is not electrically connected to the first output;

a second switch having a second input and a second output, the second input electrically connected to the bridge node, the
second output electrically connected to a second voltage, the second voltage lower than the power converter input voltage,
the second switch having a closed state in which the second input is electrically connected to the second output and an open
state in which the second input is not electrically connected to the second output;

a logic circuit in electrical communication with the first and second switches, the logic circuit controlling a respective
state of the first and second switches such that the first switch is in the open state when the second switch is in the closed
state and the second switch is in the open state when the first switch is in the closed state;

an LC circuit in electrical communication with the bridge node and a power converter load, the power converter load receiving
an output current at a power converter output voltage, the power converter output voltage lower than the power converter input
voltage;

a PWM and frequency control circuit configured to control (a) a ratio of times that the first and second switches are in respective
closed states to control the power converter output voltage and (b) a switching frequency of the first and second switches;

a first delay feedback circuit configured to control a low-to-high delay time between an open time of said second switch and
a close time of said first switch; and

a second delay feedback circuit configured to control a high-to-low delay time between an open time of said first switch and
a close time of said second switch;

wherein the first and second delay feedback circuits each include a sample and hold circuit and a variable delay circuit;
and

wherein the sample and hold circuit of the first delay feedback circuit (a) samples a first switch voltage across the first
switch at the close time of the first switch and (b) determines an error between the sampled first switch voltage and the
power converter input voltage.

US Pat. No. 9,647,053

SYSTEMS AND METHODS FOR INTEGRATED MULTI-LAYER MAGNETIC FILMS

Ferric Inc., New York, N...

1. A structure comprising:
a semiconductor integrated circuit comprising a multilevel wiring network; and
an inductor integrated into said multilevel wiring network, wherein said inductor comprises a planar laminated magnetic core
and a conductive winding that turns around in a generally spiral manner on the outside of said planar laminated magnetic core,
said planar laminated magnetic core comprising an electrical insulator layer and a first interface layer, wherein the electrical
insulator layer and the first interface layer are disposed between a first magnetic layer and a second magnetic layer, and
wherein said first interface layer comprises at least one of tantalum, titanium, tungsten, chromium, or platinum.

US Pat. No. 10,244,633

INTEGRATED SWITCHED INDUCTOR POWER CONVERTER

Ferric Inc., New York, N...

1. A switched inductor DC-DC power converter, comprising:a CMOS power switch;
an LC filter electrically coupled to an output of the CMOS power switch, the LC filter comprising:
a thin-film inductor electrically coupled to the output of the CMOS power switch; and
an output capacitor electrically coupled to an output of the thin-film inductor;
regulation circuitry electrically coupled to an input of the CMOS power switch;
feedback control circuitry that regulates a switching frequency of the CMOS power switch; and
interface circuitry electrically coupled to an input of the control circuitry,
wherein the switched inductor DC-DC power converter is integrated on a common substrate; and
wherein the common substrate comprises a multilevel wiring network and the inductor is integrated on top of the multilevel wiring network.

US Pat. No. 10,347,709

METHODS OF MANUFACTURING INTEGRATED MAGNETIC CORE INDUCTORS WITH VERTICAL LAMINATIONS

Ferric Inc., New York, N...

1. A method of manufacturing an inductor comprising a laminated ferromagnetic core, comprising:depositing a conductive seed layer on a planar surface, the planar surface disposed above a substrate;
depositing a masking insulator layer on the conductive seed layer and defining a pattern in the masking insulator layer, via photolithography or a subtractive wet or dry etch, to form exposed portions of the conductive seed layer between adjacent patterned portions of the masking insulator layer;
depositing a plurality of ferromagnetic layers on the exposed portions of the conductive seed layer, each ferromagnetic layer disposed on one of said exposed portions of the conductive seed layer and having a height extending from the conductive seed layer along a first axis, said first axis orthogonal to the planar surface;
forming said laminated ferromagnetic core wherein the ferromagnetic layers and the patterned portions of the masking insulator layer comprise alternating layers; and
forming a conductive winding around the laminated ferromagnetic core.

US Pat. No. 10,326,366

ZERO-VOLTAGE SWITCH-MODE POWER CONVERTER

Ferric Inc., New York, N...

13. A method of operating a switch-mode power converter, the method comprising:controlling a duty cycle of first and second switches electrically connected to a bridge node to convert a power converter input voltage to a power converter output voltage, wherein:
the first switch has a first input and a first output, the first input having a power converter input voltage, the first output electrically connected to a bridge node, the first switch having a closed state in which the first input is electrically connected to the first output and an open state in which the first input is not electrically connected to the first output,
the second switch has a second input and a second output, the second input electrically connected to the bridge node, the second output electrically connected to a second voltage, the second voltage lower than the power converter input voltage, the second switch having a closed state in which the second input is electrically connected to the second output and an open state in which the second input is not electrically connected to the second output, and
first switch is in the open state when the second switch is in the closed state and the second switch is in the open state when the first switch is in the closed state;
discharging the bridge node voltage during a high-to-low-delay time between an open time of the first switch and a close time of the second switch so that the bridge node voltage equals the second voltage at an end of the high-to-low-delay time;
adjusting the high-to-low-delay time if the bridge node voltage does not equal the second voltage at the end of the high-to-low-delay time;
charging the bridge node voltage during a low-to-high-delay time between an open time of the second switch and a close time of the first switch so that the bridge node voltage equals the power converter input voltage at an end of the low-to-high-delay time;
adjusting the low-to-high-delay time if the bridge node voltage does not equal the power converter input voltage at the end of the low-to-high-delay time; and
adjusting a switching frequency of the first and second switches so that an inductor current of an LC circuit in electrical communication with the bridge node raises the bridge voltage to the power converter input voltage during the low-to-high-delay time;
wherein said switching frequency defines a power conversion cycle of said switch-mode power converter, said first switch is in its closed state during a portion of the power conversion cycle, and said second switch is in its closed state during another portion of the same power conversion cycle.

US Pat. No. 10,367,415

PROCESSOR MODULE WITH INTEGRATED PACKAGED POWER CONVERTER

Ferric Inc., New York, N...

1. An assembly comprising:a processor module comprising:
a processor package substrate having opposing first and second sides;
a processor chip mounted on the first side of the processor package substrate; and
an array of electrical terminations disposed on the second side of the processor package substrate; and
a power management module disposed on the second side of the processor package substrate, the power management module comprising:
a power management package substrate; and
a power converter chip mounted on the power management package substrate, the power converter chip disposed between the power management package substrate and the first or second side of the processor package substrate,
wherein a height of the power management module is less than or equal to a height of the electrical terminations on the second side of the processor package substrate, the height measured with respect to an axis that is orthogonal to a plane defined by the second side of the processor package substrate.

US Pat. No. 10,431,371

MANUFACTURING METHODS FOR MAGNETIC CORE INDUCTORS WITH BIASED PERMEABILITY

Ferric Inc., New York, N...

1. A method of forming an inductor assembly, comprising:depositing a magnetic core on a planar substrate, the magnetic core lying in a core plane;
forming an inductor coil that winds around the magnetic core, the inductor coil configured to generate an inductor magnetic field that passes through the magnetic core in a closed loop parallel to the core plane; and
annealing the magnetic core while applying an external magnetic field that passes through the magnetic core in a radial direction to permanently fix an easy axis of magnetization of the magnetic core parallel to the radial direction, the radial direction orthogonal to the closed loop,
wherein permanently fixing the easy axis of magnetization parallel to the radial direction causes a hard axis of magnetization of the magnetic core to be permanently oriented in a generally circular closed path parallel to the closed loop.

US Pat. No. 10,354,950

SYSTEMS AND METHODS FOR MICROELECTRONICS FABRICATION AND PACKAGING USING A MAGNETIC POLYMER

Ferric Inc., New York, N...

1. A structure comprising:a semiconductor integrated circuit or an integrated passive device comprising a multilevel wiring network fabricated on a semiconductor die, wherein said semiconductor die includes a semiconductor; and
an inductor integrated into said multilevel wiring network, wherein said inductor comprises:
a planar magnetic core disposed parallel to a wiring plane;
a conductive winding that turns around in a spiral manner on the outside of said magnetic core, said conductive winding including at least one level from said multilevel wiring network; and
an insulation layer disposed between the magnetic core and the conductive winding, the insulation layer including a magnetically-anisotropic magnetic polymer, the magnetic polymer comprising:
a polymer matrix; and
a plurality of ferromagnetic particles disposed in the polymer matrix,
wherein said magnetic polymer surrounds said magnetic core and said magnetic polymer increases an inductance of said inductor, and
said magnetic polymer has a magnetic anisotropy in which the hard axis of magnetization of the magnetic polymer is aligned parallel to the wiring plane.

US Pat. No. 10,658,331

PROCESSOR MODULE WITH INTEGRATED PACKAGED POWER CONVERTER

Ferric Inc., New York, N...

1. An assembly comprising:a processor module comprising:
a processor package substrate having opposing first and second sides;
a processor chip mounted on the first side of the processor package substrate;
an array of electrical terminations disposed on the second side of the processor package substrate; and
conductive interconnects extending across the first and second sides of the processor package substrate; and
a power converter chip embedded in the processor package substrate, the power converter chip configured to down convert an input voltage to a supply voltage, the supply voltage lower than the input voltage,
wherein the conductive interconnects are electrically coupled to the power converter chip and the processor chip to provide the supply voltage to the processor chip.

US Pat. No. 10,629,357

APPARATUS AND METHODS FOR MAGNETIC CORE INDUCTORS WITH BIASED PERMEABILITY

Ferric Inc., New York, N...

1. A method of fabricating an inductor assembly, comprising:fabricating a magnetic core and an inductor coil that winds around the magnetic core on a first substrate, the magnetic core lying in a core plane, the inductor coil configured to generate an inductor magnetic field that passes through the magnetic core in a first direction parallel to the core plane;
providing relative movement between the first substrate and a second substrate having a bias coil disposed thereon such that the bias coil on the second substrate and the magnetic core on the first substrate are within range of one another; and
applying current in the bias coil to: (i) generate a bias magnetic field that passes through the magnetic core in a second direction that is orthogonal to the first direction and (ii) generate heat to heat the magnetic core, to induce a permanent or semi-permanent orientation of anisotropy for the magnetic core.

US Pat. No. 10,593,470

COMPACT TRANSCEIVER ON A MULTI-LEVEL INTEGRATED CIRCUIT

Ferric Inc., New York, N...

1. A system for transmitting power or data through variable magnetic fields, comprising:a first transceiver apparatus comprising a first transceiver coil that generates first variable magnetic fields;
a semiconductor integrated circuit comprising a multilevel wiring network fabricated on a semiconductor die; and
an inductor integrated into the multilevel wiring network, wherein the inductor comprises:
a magnetic core; and
a second transceiver coil that is wound in a generally spiral manner on the outside of the magnetic core, the second transceiver coil including at least one level from the multilevel wiring network,whereinthe second transceiver coil is electrically coupled to active circuit elements on the semiconductor die, and
the first and second transceiver coils are inductively coupled to each other.

US Pat. No. 10,893,609

INTEGRATED CIRCUIT WITH LAMINATED MAGNETIC CORE INDUCTOR INCLUDING A FERROMAGNETIC ALLOY

Ferric Inc., New York, N...

1. A microelectronic device comprising:a semiconductor integrated circuit, wherein said semiconductor integrated circuit comprises a multilevel wiring network, wherein said semiconductor integrated circuit operates with a plurality of DC supply voltages; and
a DC to DC voltage converter which delivers at least one of said DC supply voltages for said semiconductor integrated circuit, said DC to DC voltage converter comprising an inductor, and wherein said inductor is integrated thereinto said multilevel wiring network, wherein said inductor comprises a planar magnetic core and a conductive winding, wherein said conductive winding turns around in generally spiral manner on the outside of said planar magnetic core, said planar magnetic core having a laminated configuration comprising at least one magnetic layer and at least one current rectifying layer, wherein the at least one magnetic layer comprises a ferromagnetic alloy having an iron composition of about 10 atomic percent to about 90 atomic percent,
wherein:
the at least one current rectifying layer comprises a p-type semiconductor, the p-type semiconductor having a first work function less than a second work function of the ferromagnetic alloy, and
the laminated configuration further comprises an interface metal layer disposed on said p-type semiconductor, the interface layer having a work function less than said first work function of said p-type semiconductor.

US Pat. No. 10,878,996

COMPACT TRANSCEIVER ON A MULTI-LEVEL INTEGRATED CIRCUIT

Ferric Inc., New York, N...

1. A method for transmitting power or data through magnetic fields, comprising:passing a first variable electrical current through a first transceiver coil in a first transceiver apparatus;
generating a variable magnetic flux that passes through an interior of the first transceiver coil, the variable magnetic flux extending along a first flux axis to a semiconductor integrated circuit chip, the semiconductor integrated circuit chip including a second transceiver coil disposed about an outside of a magnetic core;
generating a second variable current in the second transceiver coil, the second variable current based on the variable magnetic flux; and
modulating an impedance of the second transceiver coil to transmit data to the first transceiver apparatus.