US Pat. No. 9,260,278

REMOTE HANDLING APPARATUS FOR LOAD OBJECT AND AUXILIARY APPARATUS THEREOF

FUJI ELECTRIC CO., LTD., ...

13. A remote handling apparatus for a load object, comprising:
a joystick device including an input coordinate sensor that detects an input coordinate value of one input axis of a stick
that accepts manual operation from an operator, and a counterforce generator that is connected to the stick to generate counterforce
to allow the operator to recognize the counterforce via a stick according to a value indicated by a received counterforce
command signal;

a lifting controller that receives an input coordinate signal indicating the input coordinate value from the input coordinate
sensor and that outputs a velocity command signal indicating a velocity command value corresponding to the input coordinate
value;

a load lifting device that is installed away from the joystick device, receives the velocity command signal, and allows a
load object to ascend, stop or descend according to the velocity command value;

a load sensor installed to detect a dynamic load value of the load object; and
a pulsed counterforce controller that receives a dynamic load signal indicating the dynamic load value from the load sensor,
calculates a time rate of change of either the deviation amount, which is a difference of the dynamic load value from a static
load value of the load object, or the dynamic load value, and outputs a counterforce command signal indicating a counterforce
command value for generating a pulsed counterforce to the counterforce generator according to the presence of the time rate
of change.

US Pat. No. 9,252,266

WIDE BAND GAP SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

FUJI ELECTRIC CO., LTD., ...

1. A wide band gap semiconductor device comprising:
a silicon carbide semiconductor substrate;
a second conductivity type silicon carbide semiconductor layer having a high impurity concentration and disposed on one principal
surface of the semiconductor substrate;

a second conductivity type silicon carbide drift layer having a low impurity concentration and disposed on the second conductivity
type silicon carbide semiconductor layer;

a first conductivity type silicon carbide base layer disposed on the drift layer;
a second conductivity type silicon carbide source region selectively disposed on a principal surface of the base layer;
a first trench having a depth extending from a principal surface of the source region to reach the drift layer;
a gate insulating film lining the first trench;
a control electrode which is filled in the first trench, inside the gate insulating film, so as to be located in a position
facing the source region, the base layer and the drift layer;

a second trench provided near the first trench and having a depth extending from the principal surface of the base layer to
reach the drift layer so as to be deeper than the first trench;

a first main electrode which is disposed in the second trench to form a Schottky junction between the first main electrode
and a surface of the drift layer located in the second trench so that the first main electrode covers the principal surface
of the source region and the principal surface of the base layer in common;

third trenches each of which has a depth extending from the other principal surface of the silicon carbide semiconductor substrate
to reach the second conductivity type silicon carbide semiconductor layer having the high impurity concentration; and

a second main electrode which is electrically connected to inner surfaces of the third trenches and the other principal surface
of the silicon carbide semiconductor substrate.

US Pat. No. 9,240,727

SWITCHING POWER SUPPLY DEVICE CONTROL CIRCUIT HAVING AN OVERCURRENT PROTECTION CONTROL CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A switching power supply device control circuit, being a control circuit of a flyback type switching power supply device
that converts a voltage of an AC input into a predetermined direct current voltage by turning a switching element on and off
and that supplies a voltage to a load, comprising:
a current detecting circuit, connected to the switching element, that converts a current of the switching element into a voltage
signal;

an overcurrent protection circuit that detects an overcurrent with respect to the load based on the voltage signal converted
by the current detecting circuit;

a voltage correction circuit that corrects a reference voltage signal to the overcurrent protection circuit in response to
a change in the voltage of the AC input;

an oscillator circuit having a frequency modulating function whereby a switching frequency with respect to the switching element
can be modulated; and

a slope compensation circuit that generates a slope compensation signal increasing monotonically in proportion to an on-state
period of the switching frequency including a frequency modulation period set by the oscillator circuit, wherein the voltage
correction circuit corrects the reference voltage signal in accordance with the slope compensation signal.

US Pat. No. 9,257,830

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a semiconductor switching element;
an overvoltage protection circuit to protect the switching element from overvoltage;
a resistance circuit to transmit a control signal for turning the switching element ON and OFF to a control terminal of the
switching element;

a first switching means for receiving, through the overvoltage protection circuit, a signal corresponding to a voltage appearing
at an output terminal of the switching element on turning OFF of the switching element;

a second switching means for operating according to a voltage of a first capacitor connected to an output side of the first
switching means to increase a resistance value of the resistance circuit; and

a timing control means for controlling timing of operating the second switching means in accordance with the voltage of the
first capacitor, the first capacitor being charged or discharged responsive to a level of the control signal,

wherein the timing control means turns off the second switching means by discharging the first capacitor with the control
signal before the elapse of an ON time of the control signal causes an excessive current to flow in the switching element,
and slows a turn-off speed of the switching element by increasing the resistance value.

US Pat. No. 9,240,451

SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A silicon carbide semiconductor device, comprising:
a silicon carbide semiconductor substrate including:
a first region that has a structure in which a first-conductivity-type region is provided or a structure in which the first-conductivity-type
region and a second-conductivity-type region are periodically provided;

a second region which surrounds the first region and in which a second-conductivity-type region is provided;
a third region which surrounds the second region and in which a second-conductivity-type region having a different impurity
concentration from the second-conductivity-type region of the second region is provided; and

an interlayer insulating film which is formed on the second region and the third region;
a first metal layer that covers at least the first region and that is a film including at least one of a titanium film, a
titanium alloy film, a nickel film, a nickel alloy film, or a nickel-titanium alloy film; and

a second metal layer that is formed on the first metal layer and that is an aluminum film or an aluminum alloy film, wherein
the first and second metal layers are formed on the silicon carbide semiconductor substrate, and

wherein dry etching is performed on a portion of the second metal layer and the second metal layer covers the entire first
metal layer.

US Pat. No. 9,178,448

POWER CONVERSION DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A power conversion device for driving a load, comprising:
a power conversion device main body configured to receive an input of a power supply voltage, and to drive the load; and
a brake circuit configured to protect the power conversion device main body from overvoltage applied thereto, the brake circuit
including

a semiconductor switch circuit that, when conductive, forms a bypass current path with respect to the power conversion device
main body, thus consuming excess power, and

a Zener diode that is connected between a positive electrode line, via which the power supply voltage is applied to the power
conversion device main body, and a control terminal of the semiconductor switch circuit, the Zener diode becoming conductive
when the voltage applied to the power conversion device main body exceeds a predetermined value, to thereby suppress the voltage.

US Pat. No. 9,240,456

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method for manufacturing a semiconductor device comprising:
forming on a first main surface of a semiconductor wafer of a first conduction type, each of
a first electrode,
a MOS gate structure which is a gate electrode of a semiconductor element,
an edge termination region for forming a breakdown voltage of the semiconductor element, and
a first semiconductor region, that is a second conduction type, surrounding the semiconductor element and the edge termination
region;

forming a groove that reaches the first semiconductor region from a second main surface of the semiconductor wafer, the groove
being formed so that a portion of the semiconductor wafer, which has a predetermined width greater than zero and forms an
entire outer periphery of the semiconductor wafer including an outer circumferential end of the semiconductor wafer, remains
and the groove is formed inside the portion of the semiconductor wafer that forms the entire outer periphery of the semiconductor
wafer so that the groove is formed further towards a center of the semiconductor wafer than the outer circumferential end;

forming a second semiconductor region, that is the second conduction type, in direct contact with the second main surface
of the semiconductor wafer;

forming a third semiconductor region, that is the second conduction type, in direct contact with a side wall of the groove
so as to be electrically connected to both of the first semiconductor region and the second semiconductor region; and

forming a second electrode that is electrically connected to the second semiconductor region,
wherein in the forming the groove, the groove is formed such that a corner of the groove, which is closest to the outer circumferential
end of the semiconductor wafer than any other corner of the groove, has an arc shape in a plan view of the device.

US Pat. No. 9,178,049

MOS TYPE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A MOS type semiconductor device, comprising:
a stripe-shaped plan-view pattern of protruding semiconductor region on one principal surface of a first conductivity type
semiconductor substrate, the protruding semiconductor region having

a second conductivity type region sandwiched between an upper side first conductivity type first region and a lower side first
conductivity type second region,

a top flat portion including a depression region with a depth reaching the second conductivity type region from a surface
of the upper side first conductivity type first region, and

an inclined portion between the top flat portion and a bottom flat portion around the protruding semiconductor region; and
a gate electrode covering a surface of the inclined portion of the second conductivity type region across a gate insulator,
the gate electrode having

a first end portion on a surface within the inclined portion, and
a second end portion on a surface of the lower side first conductivity type second region on the side of and in the vicinity
of the second conductivity type region,

the gate electrode terminating on the inclined portion without extending onto the top flat portion.

US Pat. No. 9,184,743

CONTROL APPARATUS FOR SWITCHING DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A control apparatus which controls conduction and shutoff of a switching device having an overcurrent threshold, the control
apparatus comprising:
a current sensor which detects a current flowing in the switching device and generates a detected current signal representative
of the current;

a first comparison circuit which compares the detected current signal with a predetermined first reference value, and when
the detected current signal is equal to or greater than the first reference value, outputs a surge suppression signal; and

a first shutoff circuit which grounds a control terminal of the switching device in response to output of the surge suppression
signal from the first comparison circuit,

wherein the first reference value is smaller than a predetermined second reference value, the second reference value representing
a value of the detected current signal corresponding to the overcurrent threshold, and

wherein the first reference value is set to represent a value of the detected current signal between a rated current value
of the switching device and the overcurrent threshold.

US Pat. No. 9,281,194

FABRICATION METHOD OF SILICON CARBIDE SEMICONDUCTOR APPARATUS

FUJI ELECTRIC CO., LTD., ...

7. A silicon carbide semiconductor apparatus fabrication method comprising:
forming an ohmic metal film on a silicon carbide substrate by sputtering a target including a mixture or an alloy having therein
nickel, and a metal(s) reducing magnetic permeability of nickel and producing a carbide, compositional ratios of the mixture
or the alloy being adjusted to predetermined compositional ratios; and

executing heat treatment for the ohmic metal film to calcinate the ohmic metal film, wherein
the metal(s) reducing the magnetic permeability of the nickel and producing the carbide is/are one, or two or more metal(s)
selected from among molybdenum, tungsten, tantalum, vanadium, zirconium, titanium, chromium, and aluminum, and

a ratio of said one, or two or more selected metal(s) in the target is 8 at % or greater and 50 at % or less.

US Pat. No. 9,252,209

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a first semiconductor layer of a first-conductivity-type;
a second semiconductor layer of second-conductivity-type that is provided on a first main surface of the first semiconductor
layer and has an impurity concentration more than that of the first semiconductor layer;

a third semiconductor layer of the first-conductivity-type that is provided on a second main surface of the first semiconductor
layer and has an impurity concentration more than that of the first semiconductor layer; and

a plurality of broad buffer layers of the first conductivity-type that are provided in the first semiconductor layer and each
of the broad buffer layers has an impurity concentration more than that of the first semiconductor layer, and has a mountain-shaped
impurity concentration distribution in which a local maximum value is less than the impurity concentration of the third semiconductor
layer, the mountain-shaped impurity concentration distribution having a peak at the local maximum value and differences of
elevation in a depth direction, wherein a resistivity ?0 (?cm) of the first semiconductor layer satisfies 0.12V0??0 with respect to a rated voltage V0 (V).

US Pat. No. 9,252,086

CONNECTOR AND RESIN-SEALED SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A connector for electrically connecting a chip electrode, arranged on one main surface of a semiconductor element, to a
lead constituting an external leading terminal of the chip electrode, comprising:
a plate shape portion including a first main surface and a second main surface;
a first interface arranged on the first main surface joined to the chip electrode;
a second interface arranged on the first main surface joined to a base end part of the lead; and
a first step formed between the first interface and an entire surface of the first main surface except for the first interface
and extending in a direction perpendicular to a direction from the first interface toward the second interface such that the
entire surface of the first main surface except for the first interface is arranged away from a surface of the chip electrode,

wherein a height between the surface of the chip electrode and the first main surface except for the first interface is equal
to or less than a half of a thickness of the connector.

US Pat. No. 9,252,693

STEPPING MOTOR DRIVE DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A stepping motor drive device, comprising:
a plurality of insulated gate semiconductor elements provided in parallel that apply drive voltage in a complementary way
to paired coils of a stepping motor, thus driving the stepping motor; and

a fall delay circuit that delays a timing of a fall of input pulse signals applied in a complementary way to the gate of each
insulated gate semiconductor element by a time Td, wherein

Td>Trise?Tfall,

in accordance with a rise time Trise when turning on, and a fall time Tfall when turning off, the insulated gate semiconductor
element.

US Pat. No. 9,184,268

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a drift region that is a semiconductor substrate of a first conductivity type;
a base region of a second conductivity type that is selectively provided in a surface layer of a first main surface of the
semiconductor substrate;

an emitter region of the first conductivity type that is selectively provided in the base region;
a trench that extends from the first main surface of the semiconductor substrate to the drift region through the emitter region
and the base region;

an insulating film that is provided along an inner wall of the trench;
a gate electrode that is embedded in the trench through the insulating film;
an emitter electrode that comes into contact with the emitter region and the base region;
a shell region of the first conductivity type that is provided in the drift region so as to come into contact with a surface
of the base region close to the drift region; and

a collector region of the second conductivity type that is provided in a surface layer of a second main surface of the semiconductor
substrate, wherein:

the shell region has a higher impurity concentration than the drift region,
an effective dose of a first-conductivity-type impurity in the shell region is equal to or less than 5.0×1012 cm?2, and

the drift region has a resistivity to prevent a depletion layer, which is spread from the collector region when a reverse
rated voltage with the emitter electrode as a positive electrode is applied, from reaching either the shell region or the
bottom of the trench, whichever is closer to the collector region than the other.

US Pat. No. 9,142,664

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
an active region which is disposed on a first main surface side of a substrate to apply a current actively or passively;
a first conductivity-type low-resistivity layer which is disposed on a second main surface side of the substrate;
a vertical drift portion which is disposed between the active region and the low-resistivity layer so that a drift current
flows into the vertical drift portion vertically in the ON state while the vertical drift portion is depleted in the OFF state,
and which forms a first parallel pn structure in which a first vertical first conductivity-type region oriented in a thickness
direction of the substrate and a first vertical second conductivity-type region oriented in the thickness direction of the
substrate alternate repeatedly;

an edge termination region which is provided around the vertical drift portion and disposed between the first main surface
and the low-resistivity layer, so that the edge termination region substantially serves as a region in which current does
not flow in the ON state while the edge termination region is depleted in the OFF state;

a first conductivity-type layer which is provided between the first parallel pn structure and the low-resistivity layer so
as to extend from the active region to the edge termination region and which has higher resistivity than the low-resistivity
layer; and

a second conductivity-type layer which is provided selectively inside the first conductivity-type layer in the edge termination
region.

US Pat. No. 9,099,925

SWITCHING POWER SUPPLY WITH CIRCUIT TO CONTROL TURN ON TIMING OF SWITCHING ELEMENT

FUJI ELECTRIC CO., LTD., ...

1. A switching power supply comprising:
an inductor connected to a rectifier circuit that rectifies an input AC voltage;
a switching element forming a current path from the rectifier circuit through the inductor in an ON state of the switching
element;

a diode forming a current path from the inductor to an output capacitor in an OFF state of the switching element to obtain
a specified output DC voltage on the output capacitor; and

a control circuit that controls current through the inductor by ON/OFF controlling the switching element, the control circuit
comprising

an ON width controlling component that controls an ON width of the switching element corresponding to a voltage difference
between a reference voltage and the output DC voltage,

a zero current detecting component that detects zero current flowing through the switching element and a controlling circuitry
that turns ON the switching element at a timing of the detected zero current,

a load condition detecting component that detects a load condition;
a frequency reducing component that delays a turn ON timing of the switching element upon detection of a light load condition
by the load condition detecting component to reduce a switching frequency of the switching element, and

an AC period detecting component that detects a period of the input voltage and a circuitry to hold the load condition detected
by the load condition detecting component over every period detected by the AC period detecting.

US Pat. No. 9,276,482

FORWARD TYPE DC-DC CONVERTER

FUJI ELECTRIC CO., LTD., ...

1. A forward type DC-DC converter that converts a voltage of a DC input power supply to a specified DC output voltage insulated
from the voltage of the DC input power supply, the DC-DC converter comprising:
a series circuit of a primary side semiconductor switch and a primary winding of a transformer, the series circuit being connected
in parallel to the DC input power supply;

a rectifying diode that rectifies a voltage across a secondary winding of the transformer;
a smoothing filter comprising a DC reactor and a smoothing capacitor, the smoothing filter that smoothes an output voltage
of the rectifying diode;

a freewheeling diode that freewheels a current in the DC reactor;
a first MOSFET connected in inverse parallel to the rectifying diode; and
a second MOSFET connected in inverse parallel to the freewheeling diode,
a voltage across the smoothing capacitor being served as a DC output voltage,
the DC output voltage being controlled by turning-on and -off operations of the first MOSFET and the second MOSFET based on
periodical turning-on and -off operations of the primary side semiconductor switch, and

an arithmetic circuit in which
a turning-on time width of the first MOSFET is calculated by use of a time width within which a current flows in the DC reactor
on a secondary side within a turning-off time width of the primary side semiconductor switch in a previous period, the DC
output voltage and the voltage across the secondary winding of the transformer, and

a turning-on time width of the second MOSFET is calculated by use of a turning-on time width of the primary side semiconductor
switch immediately before a turning-on of the second MOSFET, the DC output voltage, and the voltage across the secondary winding
of the transformer.

US Pat. No. 9,184,230

SILICON CARBIDE VERTICAL FIELD EFFECT TRANSISTOR

FUJI ELECTRIC CO., LTD., ...

1. A silicon carbide vertical field effect transistor comprising:
a first-conductive-type silicon carbide substrate;
a low-concentration first-conductive-type silicon carbide layer formed on a surface of the first-conductive-type silicon carbide
substrate;

second-conductive-type regions selectively formed on a surface of the low-concentration first-conductive-type silicon carbide
layer;

first-conductive-type source regions formed in the second-conductive-type regions;
a high-concentration second-conductive-type region formed between the first-conductive-type source regions on the second-conductive-type
region;

a source electrode electrically connected directly to the high-concentration second-conductive-type region and a first-conductive-type
source region among the first-conductive-type source regions;

a gate insulating film formed from a first first-conductive-type source region to an adjacent second first-conductive-type
source region of the first-conductive-type source regions and over a respective first second-conductive-type region and a
respective second second-conductive-type region of the second-conductive-type regions and over the first-conductive-type silicon
carbide layer;

a gate electrode formed on the gate insulating film;
a drain electrode on a back side of the first-conductive-type silicon carbide substrate, wherein
a second high-concentration second-conductive-type region is disposed between the first-conductive-type silicon carbide layer
and each of the second-conductive-type regions;

a width of the second high-concentration second-conductive-type region is smaller than that of the second-conductive-type
regions; and,

the second high-concentration second-conductive-type region overlaps the high-concentration second-conductive-type region.

US Pat. No. 9,229,461

INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. An integrated circuit, comprising a voltage divider circuit, having:
a resistive voltage divider element for dividing a voltage between ground and a high-voltage line which supplies a voltage
obtained by rectifying an alternating-current voltage or a direct-current voltage;

a switch which is connected in series to the resistive voltage divider element and which cuts off a current path formed between
the high-voltage line and ground via the resistive voltage divider element; and

switching means for opening and closing the switch according to the state of a semiconductor device which is a supply destination
of the voltage obtained by division by the resistive voltage divider element,

the voltage divider circuit being formed on the same semiconductor substrate as the semiconductor device
wherein the switch is a MOSFET, and at least one resistor constituting the resistive voltage divider element is formed so
as to be completely surrounded by the MOSFET, and one end of the resistor is connected to a drain terminal of the MOSFET.

US Pat. No. 9,106,155

THREE-LEVEL POWER CONVERSION CIRCUIT SYSTEM

FUJI ELECTRIC CO., LTD., ...

1. A three-level power conversion circuit system for outputting potential at levels selected from among three absolute values
during conversion of power from two series-connected DC power supplies to alternating current, comprising:
a plurality of one-phase switch circuits that receive power from the two DC power supplies, each of the one-phase switch circuits
including

a semiconductor switch series circuit in which first and second semiconductor switches are connected in series and the series
is connected in parallel to the DC power supplies,

diodes that are connected in anti-parallel to the first and second semiconductor switches;
a bidirectional semiconductor switch circuit in a circuit path between a series connection point of the semiconductor switch
series circuit and a series connection point of the DC power supplies, and

opening means in the circuit path for opening the circuit path if the bidirectional semiconductor switch circuit fails,
wherein the bidirectional switch circuits in all of the one-phase switch circuits are placed in a constant off-state, if the
bidirectional semiconductor switch circuit in any of the one-phase switch circuits fails, and

wherein after any of the bidirectional switch circuits fails, operation of the power conversion circuit system is continued
as a two-level output inverter system using the semiconductor switch series circuits of the one-phase switch circuits.

US Pat. No. 9,093,904

RESONANT SWITCHING POWER SUPPLY DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A resonant switching power supply device, comprising:
a first switch and a second switch connected in series to terminals into which a direct current voltage is input;
a series circuit of a resonant capacitor, at least one of a resonant inductor and transformer leakage inductor, and a first
winding on a primary side of a transformer, connected to the first switch or the second switch;

a resonant current detector unit that detects a resonant current flowing through the series circuit;
a winding voltage detector unit that detects a winding voltage, which is a voltage across a first winding of the transformer;
and

a control and drive unit that drives the first switch and second switch to be turned on and off alternately, wherein
the control and drive unit has a protection function whereby, in the event that, after detection occurs that a polarity of
the winding voltage detected by the winding voltage detector unit has been inverted, either the first switch or the second
switch is not in an off-state, when detection occurs that the resonant current detected by the resonant current detector unit
has exceeded a threshold value with respect to another resonant current immediately before the inversion of the polarity of
the winding voltage, the first switch or second switch that is not in an off-state is turned off.

US Pat. No. 9,257,911

SWITCHING POWER SOURCE DEVICE WITH TIMING CONTROL OF SYNCHRONOUS RECTIFIER

FUJI ELECTRIC CO., LTD., ...

1. A switching power source device that converts direct current voltage applied to input terminals and outputs direct current
voltage from output terminals, wherein
a main switching element connected in series to a primary winding of a transformer is connected between the input terminals,
and

a synchronous rectifier switching element connected in series to a secondary winding of the transformer is connected between
the output terminals,

the switching power source device comprising:
a rectifier element connected in parallel to the synchronous rectifier switching element;
a drive control unit that drives the main switching element and synchronous rectifier switching element;
an element voltage detection unit that detects a value of a voltage across the synchronous rectifier switching element;
an output voltage detection unit that detects a value of an output voltage between the output terminals;
a variable pulse generator unit that generates a clock pulse of a frequency in accordance with a difference between the value
of the voltage across the synchronous rectifier switching element and the output voltage value detected by the element voltage
detection unit and the output voltage detection unit;

a counter unit that increases or reduces a count value in accordance with the clock pulse; and
an on/off control unit that maintains the synchronous rectifier switching element in an on-state until the main switching
element is turned off and the count value reaches a predetermined value.

US Pat. No. 9,206,708

DIRECT CONTACT CONDENSER FOR A STEAM TURBINE AND HAVING A FIRST COOLING WATER SPRAYING MECHANISM SPRAYING COOLING WATER DOWNSTREAM AND A SECOND COOLING WATER SPRAYING MECHANISM SPRAYING COOLING WATER IN MULTIPLE DIRECTIONS

Fuji Electric Co., Ltd., ...

1. A direct contact condenser for a steam turbine, the direct contact condenser comprising:
an exhaust gas inlet part configured to introduce a turbine exhaust gas containing steam and a non-condensable gas of the
steam turbine in a horizontal direction;

a steam cooling chamber configured to spray cooling water at the turbine exhaust gas introduced through the exhaust gas inlet
part to cool the turbine exhaust gas; and

a water storage which is disposed at a bottom of the steam cooling chamber and which stores condensed water generated by cooling
the steam and the cooling water,

the steam cooling chamber comprising:
a first cooling water spraying mechanism which is disposed adjacent the exhaust gas inlet part and which sprays the cooling
water within a range restricted to a downstream direction of the turbine exhaust gas; and

a second cooling water spraying mechanism which sprays the cooling water to the turbine exhaust gas cooled by the first cooling
water spraying mechanism in all directions.

US Pat. No. 9,257,909

SWITCHING POWER SUPPLY WITH SWITCHING FREQUENCY CONTROLLED TO PREVENT HARMONIC INTERFERENCE WITH RECEIVED RADIO BROADCAST

FUJI ELECTRIC CO., LTD., ...

1. A switching power supply comprising:
a main body of the switching power supply that performs switching operation of a DC power using a semiconductor switching
element ON/OFF-driven at a power supply frequency fs and rectifying and smoothing operation of the switched power to supply
a DC voltage to electronic devices including an AM radio receiver;

a receiving frequency detecting means that detects a receiving frequency fc of an AM radio broadcast;
a power supply frequency detecting means that detects power supply frequency fs of ON/OFF-driving the semiconductor switching
element;

a higher harmonic detecting means that determines an order n, n a natural number, of a higher harmonic component near the
receiving frequency fc of the AM radio broadcast, the higher harmonic being a power supply higher harmonic generated with
switching operation of the semiconductor switching element, based on a fundamental power supply frequency fso of ON/OFF-driving
the semiconductor switching element;

a frequency judging means that judges whether the higher harmonic component of the order n that is determined by the higher
harmonic detecting means is higher or lower than the receiving frequency fc of the AM radio broadcast and output a frequency
judgment result;

a power supply frequency width determining means that determines, according to the frequency judgment result, an upper limit
value fs-max and a lower limit value fs-min for a power supply frequency fs that does not interfere with the receiving frequency
fc of the AM radio broadcast from values of the fundamental power supply frequency fso of the switching operation, the order
n of the higher harmonic component, the receiving frequency fc of the AM radio broadcast, and a bandwidth BW thereof; and

a power supply frequency control means that compares the power supply frequency fs with the upper limit value fs-max and with
the lower limit value fs-min for the power supply frequency fs and sets the power supply frequency fs at a value within a
range specified by the upper limit value fs-max and the lower limit value fs-min.

US Pat. No. 9,070,696

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:
an insulating circuit substrate mounted with at least one semiconductor element;
a resin case provided with a plurality of terminals having leg portions; and
protrusion marks formed in vicinities of the leg portions of the plurality of terminals of the resin case,
wherein the plurality of terminals and the resin case are integrally molded using a molding die, and the protrusion marks
are marks where protrusions for fixing the plurality of terminals in predetermined positions in the molding die are placed.

US Pat. No. 9,252,218

SILICON CARBIDE SEMICONDUCTOR ELEMENT AND FABRICATION METHOD THEREOF

FUJI ELECTRIC CO., LTD., ...

1. A silicon carbide semiconductor element comprising:
a structure in which a thin film of Ni2Si and TiC formed by sintering after deposition of a thin layer including Ni and a thin layer of Ti is disposed on a silicon
carbide substrate and has a layer including TiC formed by TiC precipitation on a surface, wherein

the silicon carbide semiconductor element is further structured such that a multilayer thin film is formed on a surface of
the layer including TiC, the multilayer thin film including a Ti layer as a first thin film and an Ni layer as a second thin
film, and

a composition ratio of C derived from the layer including TiC is 15% or more at an interface between the layer including TiC
and the Ti layer of the multilayer thin film.

US Pat. No. 9,187,354

METHOD FOR INHIBITING SCALE AND GEOTHERMAL POWER GENERATING DEVICE

FUJI ELECTRIC CO., LTD., ...

11. A geothermal power generation device comprising:
piping that channels geothermal water collected from a production well;
a chelating agent feed unit for feeding a chelating agent to the geothermal water flowing through the piping;
an alkaline agent feed unit for feeding an alkaline agent to the geothermal water flowing through the piping;
a chemical-mixing part provided, on the piping route, downstream from the chelating agent feed unit and the alkaline agent
feed unit;

a first detector for measuring the pressure at an inlet of the chemical-mixing part; and
a second detector for measuring the pressure at an outlet of the chemical-mixing part;
the chelating agent feed unit being controlled so that when the difference between a detection value by the first detector
and a detection value by the second detector exceeds a preset upper threshold, the amount of the chelating agent fed is increased,
and the chelating agent is fed at an increased feed amount until the difference between the detection values falls below a
preset lower threshold.

US Pat. No. 9,081,319

ELECTROPHOTOGRAPHIC PHOTOCONDUCTOR, MANUFACTURING METHOD THEREOF, AND ELECTROPHOTOGRAPHIC DEVICE

FUJI ELECTRIC CO., LTD., ...

1. An electrophotographic photoconductor, comprising:
a conductive substrate;
an undercoat layer provided on the conductive substrate and consisting of:
from 5 to 80 parts by weight, based on 100 parts by weight of a solids fraction in the undercoat layer, of a resin that has
an acid value and a base value that are each no greater than 10 KOH mg/g and that is obtained by polymerizing starting materials
consisting of from 0.1 to 10 mol % of one type of aromatic dicarboxylic acid, at least one type of aliphatic dicarboxylic
acid having 8 or more carbon atoms, and at least one type of diamine having a cycloalkane structure; and

from 95 to 20 parts by weight, based on 100 parts by weight of a solids fraction in the undercoat layer, of at least one metal
oxide that has an acid value and a base value that are each no greater than 20.0 KOH mg/g so that the at least one metal oxide
is effectively dispersed in said resin; and

a photosensitive layer provided on the undercoat layer so that a sequential stack is obtained.

US Pat. No. 9,245,821

COOLING DEVICE FOR SEMICONDUCTOR MODULE, AND SEMICONDUCTOR MODULE

FUJI ELECTRIC CO., LTD., ...

9. A semiconductor module, comprising:
a water jacket for forming a cooling device, to which a coolant is adapted to be supplied from outside for cooling a semiconductor
element disposed outside the water jacket;

a heat dissipating device thermally connected to the semiconductor element;
a first flow channel device disposed inside the water jacket and extending from a coolant introducing port, the first flow
channel device including a guide device having an inclined surface for guiding the coolant toward one side surface of the
heat dissipating device;

a second flow channel device disposed inside the water jacket parallel to the first flow channel device at a distance therefrom
and extending toward a coolant discharge port, the second flow channel device being formed with a sidewall parallel to the
other side surface of the heat dissipating device;

a flow velocity adjusting device extending from a bottom surface of the heat dissipating device, disposed in the second flow
channel device and formed parallel to the other side surface of the heat dissipating device with a predetermined space between
the flow velocity adjusting device and the other side surface of the heat dissipating device; and

a third flow channel device formed at a position communicating the first flow channel device and the second flow channel device
inside the water jacket,

wherein the coolant introducing port and the coolant discharge port are formed in a same wall surface of the water jacket,
and the heat dissipating device is disposed in the third flow channel device.

US Pat. No. 9,237,676

SEMICONDUCTOR MODULE COOLER AND SEMICONDUCTOR MODULE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor module cooler for supplying a coolant to a water jacket from outside and cooling a semiconductor device
arranged on an outer surface of the cooler, the semiconductor module cooler comprising:
a heat sink thermally connected to the semiconductor device;
a first flow channel arranged inside the water jacket with a guide section extending from a coolant inlet and having an inclined
surface for guiding the coolant toward one side surface of the heat sink;

a second flow channel arranged inside the water jacket in parallel to the first flow channel and extending to a coolant outlet,
the second flow channel being formed with a sidewall in parallel to another side surface of the heat sink; and

a third flow channel formed inside the water jacket at a position connecting the first flow channel and the second flow channel,
wherein the coolant inlet and the coolant outlet are formed on a same wall surface of the water jacket, and the heat sink
is arranged in the third flow channel,

a cross-sectional area of the first flow channel at an end section on a coolant inlet side is smaller than a cross-sectional
area of the second flow channel at an end section on a coolant outlet side, and

the guide section is configured to reduce the cross-sectional area of the first flow channel from the coolant inlet to one
side surface of the heat sink contacting the guide section.

US Pat. No. 9,124,254

DC-DC CONVERTER CONTROL METHOD AND DC-DC CONVERTER CONTROL CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A method of controlling a DC-DC converter including an error amplifier that amplifies and outputs a difference in voltage
between a feedback voltage output from an output stage and a reference voltage, a phase compensation capacitor connected to
an output of the error amplifier, and a PWM (pulse width modulation) signal generating circuit that outputs an output signal
driving a switching element of the output stage, the output signal having a pulse width that changes in accordance with an
output voltage of the error amplifier, the method comprising:
setting a non-zero minimum value for the pulse width of the output signal of the PWM signal generating circuit; and
supplying a current to the phase compensation capacitor, in response to detecting that the pulse width of the output signal
has become less than the non-zero minimum value.

US Pat. No. 9,245,832

SEMICONDUCTOR MODULE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor module, comprising:
a metal block that has a first surface and a second surface;
an insulation layer for heat radiation formed by directly depositing a ceramic material on at least the first surface of the
metal block;

an insulation layer for a relay electrode, formed by directly depositing a ceramic material on a part of the second surface
of the metal block;

a relay electrode formed by depositing a metal material on an upper surface of the insulation layer for the relay electrode;
a circuit element bonded with the second surface of the metal block; and
an external lead terminal, wherein
a bonding wire or a lead frame from the circuit element is bonded with the relay electrode, and
the relay electrode and the external lead terminal are connected.

US Pat. No. 9,129,840

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a semiconductor chip; and
a conductive connector comprising a distal end fixed to a bonding target material, the distal end comprising a concave portion,
wherein the conductive connector is bonded to the bonding target material at the concave portion using metal nanoparticles.

US Pat. No. 9,230,799

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE

TOHOKU UNIVERSITY, Senda...

1. A method for fabricating a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer, the
method comprising:
forming a first nitride layer on a substrate;
forming a second nitride layer on the first nitride layer;
forming a field oxide layer on the second nitride layer;
forming a gate insulating film in which an Al2O3 film is formed to penetrate the field oxide layer, the first nitride layer, and the second nitride layer, the Al2O3 film is subject to radical oxidation, and

then a SiO2 film is formed by using microwave plasma, the SiO2 film penetrating the field oxide layer and the second nitride layer only, and the SiO2 film located between the Al2O3 film and a gate electrode, wherein

the gate electrode is at least partially located in an opening of the SiO2 film of the gate insulating film, and

in the forming the gate insulating film, the microwave plasma is generated by using microwaves at a frequency of 2.45 GHz
by using a radial line slot antenna.

US Pat. No. 9,246,474

DRIVE CIRCUIT FOR INSULATED GATE SWITCHING ELEMENT

FUJI ELECTRIC CO., LTD., ...

1. A drive circuit for an insulated gate switching element, comprising:
a constant current source that generates a constant current;
a switching circuit that connects a gate of the insulated gate switching element to a power supply potential side via the
constant current source when turning the insulated gate switching element ON and connects the gate of the insulated gate switching
element to a reference potential side via a discharge circuit when turning the insulated gate switching element OFF, based
on a drive signal;

a gate voltage detection circuit that detects a gate voltage of the insulated gate switching element; and
a current mode selection circuit that switches a mode of the constant current source from a normal current mode to a low current
consumption mode when detecting, based on the gate voltage detected by the gate voltage detection circuit becoming equal to
or greater than a predetermined value, that the insulated gate switching element is turned ON, and switches the mode of the
constant current source from the low current consumption mode to the normal current mode when the gate voltage detected by
the gate voltage detection circuit becomes less than the predetermined value;

wherein the current mode selection circuit has a partial resistor having a power supply-side resistor and first and second
ground-side resistors, connected between a positive power supply and a ground, and a switching element connected directly
to, and in parallel with, the second ground-side resistor, sets a ground-side partial resistance value at a normal value when
the gate voltage detected by the gate voltage detection circuit is less than the predetermined value, and sets the ground-side
partial resistance value at a low consumption mode resistance value lower than the normal value when the gate voltage detected
by the gate voltage detection circuit is equal to or greater than the predetermined value.

US Pat. No. 9,220,182

SEMICONDUCTOR MODULE COOLER AND SEMICONDUCTOR MODULE

HONDA MOTOR CO., LTD., T...

1. A semiconductor module cooler for supplying a coolant from an outside to a water jacket and cooling a semiconductor element
arranged over an outer surface of the cooler, the cooler comprising:
a heat sink which is thermally connected to the semiconductor element;
a first flow path which is placed in the water jacket, which extends from a coolant introduction inlet, and in which a guide
portion having an incline for leading the coolant toward one side of the heat sink is placed;

a second flow path which is placed in the water jacket parallel with and apart from the first flow path, which extends toward
a coolant discharge outlet, and which has a sidewall parallel to another side of the heat sink;

a flow speed adjusting plate which is placed in the second flow path and which is formed apart from and parallel with said
another side of the heat sink;

a third flow path formed in a position in the water jacket in which the first flow path connects with the second flow path;
and

one or more convex ribs which are formed on a bottom of the water jacket having the third flow path and which fit into one
or more notches at one or more positions,

wherein:
the heat sink is placed in the third flow path; and
the one or more notches are put in an edge in a longitudinal direction of the heat sink at one or more positions.

US Pat. No. 9,263,543

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method for manufacturing a semiconductor device having an improved recognition rate by an automatic wire bonding apparatus,
comprising:
(a) providing a silicon carbide semiconductor substrate; and
(b) forming an electrode structure on the silicon carbide semiconductor substrate by:
(i) forming a Schottky layer including a metal selected from the group consisting of titanium, tungsten, molybdenum, and chrome
on a front surface of the silicon carbide semiconductor substrate;

(ii) heating the Schottky layer to form a Schottky electrode which has a Schottky contact with the silicon carbide semiconductor
substrate; and

(iii) forming a surface electrode comprised of aluminum or aluminum including silicon on a surface of the Schottky electrode,
while heating at a temperature range effective for the surface electrode to closely cover any uneven portion of the Schottky
electrode and provide a surface electrode having a predetermined reflectance that is equal to or less than 80% so that said
improved recognition rate is obtained.

US Pat. No. 9,257,544

SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type and formed of a silicon carbide semiconductor;
a second semiconductor layer of the first conductivity type and formed of the silicon carbide semiconductor having an impurity
concentration higher than that of the first semiconductor layer, the second semiconductor layer being disposed on one face
of the first semiconductor layer;

a third semiconductor layer of the first conductivity type and formed of the silicon carbide semiconductor having an impurity
concentration higher than that of the second semiconductor layer, the third semiconductor layer being disposed on a face that
with respect to a first semiconductor layer side of the second semiconductor layer, is on an opposite aspect of the second
semiconductor layer;

a fourth semiconductor layer of the second conductivity type and formed of the silicon carbide semiconductor, the fourth semiconductor
layer being disposed on a face that with respect to a first semiconductor layer side of the third semiconductor layer, is
on an opposite aspect of the third semiconductor layer;

a first semiconductor region of the first conductivity type and selectively disposed inside the fourth semiconductor layer;
a plurality of trenches that respectively penetrate the fourth semiconductor layer and the first semiconductor region in a
depth direction orthogonal to the one face of the first semiconductor layer, the plurality of trenches being disposed at predetermined
intervals in a first direction parallel to the one face of the first semiconductor layer, the plurality of trenches extending
in a second direction orthogonal to the first direction and parallel to the one face of the first semiconductor layer to form
stripes;

a gate electrode that is disposed inside each trench through a gate insulation film;
a second semiconductor region of the second conductivity type, having an impurity concentration higher than that of the fourth
semiconductor layer, and selectively disposed inside the fourth semiconductor layer, the second semiconductor region having
a depth deeper than that of the fourth semiconductor layer and shallower than that of the plurality of trenches;

a third semiconductor region of the second conductivity type that is disposed to cover a bottom portion of the plurality of
trenches;

a fifth semiconductor layer of the second conductivity type and disposed on the other face of the first semiconductor layer;
an emitter electrode that is in contact with the first semiconductor region and the second semiconductor region; and
a collector electrode that is in contact with the fifth semiconductor layer.

US Pat. No. 9,245,851

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device in which an alignment marker is disposed on a semiconductor substrate, wherein the alignment marker
includes:
a wiring layer that is disposed on a surface of the semiconductor substrate;
an interlayer insulating film that is disposed on the surface of the semiconductor substrate so as to cover the wiring layer;
a plurality of first opening portions that are disposed in the interlayer insulating film to a depth which reaches the wiring
layer;

a first metal film for position detection that is disposed on a surface of the interlayer insulating film along an inner wall
of the first opening portions so as to be brought into contact with the wiring layer, which has a shape in which concavities
and convexities are continuously formed;

a second metal film that is disposed on a surface of the first metal film such that recessed portions of the concavities and
convexities of the first metal film are exposed, which is formed of a material which prevents reflection of incident light;
and

a passivation film that is disposed on the surfaces of the interlayer insulating film and the second metal film, which is
formed of a material which allows incident light to be transmitted.

US Pat. No. 9,179,578

SEMICONDUCTOR MODULE AND HEAT RADIATION MEMBER

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor module comprising:
a heat radiation member including:
a first member which contains aluminum; and
a second member which contains copper, which is embedded in the first member, and sides of the second member being enclosed
by the first member; and

a semiconductor element which is thermally connected to the heat radiation member, wherein:
the first member has a cavity,
the second member has a proximal surface in the cavity,
the second member has an exposed distal surface, opposite the proximal surface, which is exposed in the cavity of the first
member,

four sides of the second member are enclosed by the first member,
the second member has four edge surfaces in the cavity, and
the first member covers four edge portions of the distal surface of the second member.

US Pat. No. 9,196,585

POLYSILICON FUSE, SEMICONDUCTOR DEVICE HAVING OVERLAPPING POLYSILICON FUSE SECTIONS AND METHOD OF SEVERING POLYSILICON FUSE

FUJI ELECTRIC CO., LTD., ...

1. A polysilicon fuse comprising:
a first polysilicon fuse section for forming a cavity, the first polysilicon fuse section having a first narrowed portion
with a narrow width and, on each side of the first narrowed portion, having a first electrode portion with a wide width which
is connected to the first narrowed portion; and

a second polysilicon fuse section for adjusting circuit characteristics, the second polysilicon fuse section having a second
narrowed portion with a narrow width and, on each side of the second narrowed portion, having a second electrode portion with
a wide width which is connected to the second narrowed portion,

the first narrowed portion and the second narrowed portion being arranged overlaid with each other, with the first narrowed
portion being arranged beneath the second narrowed portion, and with a dialectric layer disposed in between the first narrowed
portion and the second narrowed portion.

US Pat. No. 9,197,135

BI-DIRECTIONAL DC/DC CONVERTER WITH FREQUENCY CONTROL CHANGE-OVER

FUJI ELECTRIC CO., LTD., ...

1. A bi-directional DC/DC converter capable of bi-directional power supply between a first DC voltage source and a second
DC voltage source through an isolation transformer, the bi-directional DC/DC converter comprising:
a first bridge circuit composed of a plurality of semiconductor switching elements connected to the first DC voltage source;
a second bridge circuit composed of a plurality of semiconductor switching elements connected to the second DC voltage source;
the isolation transformer connected between an AC side of the first bridge circuit and an AC side of the second bridge circuit;
an LC resonance circuit composed of at least one set of a reactor and a capacitor connected between the AC side of the first
bridge circuit and the isolation transformer or a reactor and a capacitor connected between the AC side of the second bridge
circuit and the isolation transformer;

a first detection circuit for detecting a voltage and a current of the first DC voltage source;
a second detection circuit for detecting a voltage and a current of the second DC voltage source;
a first control circuit for controlling the semiconductor switching elements of the first bridge circuit; and
a second control circuit for controlling the semiconductor switching elements of the second bridge circuit; wherein
the first control circuit has a control means for performing fixed frequency control of the semiconductor switching elements
of the first bridge circuit at around a resonance frequency of the LC resonance circuit, and a control means for performing
frequency modulation control of the semiconductor switching elements of the first bridge circuit at a frequency lower than
the resonance frequency;

the second control circuit has a control means for performing fixed frequency control of the semiconductor switching elements
of the second bridge circuit at around the resonance frequency of the LC resonance circuit, and a control means for performing
frequency modulation control of the semiconductor switching elements of the second bridge circuit at a frequency lower than
the resonance frequency;

the first control circuit also has a first change-over means for performing change-over of the first bridge circuit between
the fixed frequency control and the frequency modulation control based on a magnitude of a control variable determined according
to detected values by the second detection circuit in a mode of supplying electric power from the first DC voltage source
to the second DC voltage source;

the second control circuit also has a second change-over means for performing change-over of the second bridge circuit between
the fixed frequency control and the frequency modulation control based on a magnitude of a control variable determined according
to detected values by the first detection circuit in a mode of supplying electric power from the second DC voltage source
to the first DC voltage source.

US Pat. No. 9,202,652

ELECTROMAGNETIC CONTACTOR

FUJI ELECTRIC CO., LTD., ...

1. An electromagnetic contactor, comprising:
a pair of fixed contacts disposed to maintain a predetermined interval and a movable contact disposed to be capable of connecting
to and separating from the pair of fixed contacts; and

an electromagnet unit that drives the movable contact, including:
a plunger drive portion;
a magnetic yoke enclosing the plunger drive portion;
an upper magnetic yoke covering an upper portion of the magnetic yoke;
a movable plunger having a leading end protruding through an aperture formed in the upper magnetic yoke, a peripheral flange
portion formed on a side of the protruding end, and a lower portion, the movable plunger being urged by a return spring;

an annular permanent magnet fixed onto the upper magnetic yoke to enclose the peripheral flange portion of the movable plunger,
and magnetized in a moving direction of the movable plunger; and

a cylindrical auxiliary yoke disposed to partly overlap the lower portion of the movable plunger so that a magnetic circuit
passing through the upper magnetic yoke, magnetic yoke, auxiliary yoke and movable plunger is formed,

wherein relationships among a gap g1 between a lower surface of the peripheral flange portion of the movable plunger and an
upper surface of the upper magnetic yoke, a gap g2 between an outer peripheral surface of the movable plunger and the aperture
of the upper magnetic yoke, a gap g3 between the outer peripheral surface of the movable plunger and the cylindrical auxiliary
yoke, and a gap g4 between a lower surface of the movable plunger and an upper surface of a bottom plate portion of the magnetic
yoke are set as g1

US Pat. No. 9,276,066

SEMICONDUCTOR MULTI-LAYER SUBSTRATE AND SEMICONDUCTOR ELEMENT

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor multi-layer substrate comprising:
a substrate;
a buffer layer formed on the substrate and made of a nitride semiconductor;
an electric-field control layer formed on the buffer layer and made of a nitride semiconductor, the electric-field control
layer having conductivity in the substrate's lateral direction;

an electric-field relaxation layer formed on the electric-field control layer and made of a nitride semiconductor; and
an active layer formed on the electric-field relaxation layer and made of an nitride semiconductor,
wherein a resistance in the substrate's lateral direction of the electric-field control layer is equal to or smaller than
10 times a resistance of the electric-field relaxation layer,

a ratio of an electric field share between the electric-field relaxation layer and the buffer layer is controlled by a ratio
between a thickness of the electric-field relaxation layer and a thickness of the buffer layer, and

a ratio of a distance between an upper surface of the electric-field relaxation layer and an upper surface of the electric-field
control layer relative to a sum of the thicknesses of the buffer layer, the electric-field control layer, and the electric-field
relaxation layer is within a range of 0.3 to 0.8.

US Pat. No. 9,240,713

SWITCHING POWER SUPPLY DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A switching power supply device, comprising:
a switching power supply device main body for generating a predetermined output DC voltage from an output AC voltage, the
switching power supply device main body including a switching element and;

a switching control unit for controlling a switching frequency of the switching element in accordance with a feedback voltage
that indicates the difference between an output set voltage and the output DC voltage, the switching control unit including:

a jitter control unit for applying jitter to the switching frequency to reduce noise accompanying a switching operation of
the switching element, and

a jitter amplitude control unit for changing the jitter amplitude caused by the jitter control unit in accordance with the
feedback voltage, thereby maintaining a noise reduction effect.

US Pat. No. 9,196,281

PERPENDICULAR MAGNETIC RECORDING MEDIUM HAVING TAILORED GRANULAR LAYERS

FUJI ELECTRIC CO., LTD., ...

1. A perpendicular magnetic recording medium, comprising:
a nonmagnetic substrate;
a first layer having granular structure in which a first material is surrounded by a second material, the first material being
a magnetic crystalline material, and the second material being a non-magnetic amorphous material; and

a second layer positioned immediately below the first layer and having a granular structure in which a third material is surrounded
by a fourth material, the third material being a non-magnetic crystalline material, and the fourth material being a non-magnetic
amorphous material,

wherein, when the first material is a material denoted by “1,” the second material is a material denoted by “2,” the third
material is a material denoted by “3,” and the fourth material is a material denoted by “4,” an interface energy, Ei(a//b),
exists when two different materials including a material denoted by “a” and a material denoted by “b” are in contact, a surface
energy, Es(a), is determined when the material denoted by “a” exists independently, a surface energy, Es(b), is determined
when the material denoted by “b” exists independently, and an energy, G(a//b), is determined by subtracting a sum of the respective
surface energies (?Es) from the interface energy (Ei(a//b)), so that materials “a” and “b” are suitable for the perpendicular
magnetic recording medium when a condition is satisfied as follows:

G(2//4) is the minimum among G(1//3), G(1//4), G(2//3) and G(2//4).

US Pat. No. 9,231,494

POWER SUPPLY DEVICE WITH A RESONANT BRIDGE CIRCUIT CONTROL UNIT

CENTRAL JAPAN RAILWAY COM...

1. A power supply device comprising:
a power receiving coil configured to exchange power by an external magnetic coupling;
a bridge circuit in which one end of the power receiving coil is connected to one alternating-current (AC) terminal through
a resonance capacitor forming a resonance circuit with the power receiving coil, and another end of the power receiving coil
is connected to another AC terminal;

a smoothing capacitor configured to be connected between direct-current (DC) terminals of the bridge circuit, and to be connected
to both ends of a load;

a current detection unit configured to detect an input current that flows through the power receiving coil;
a voltage detection unit configured to detect a voltage between the DC terminals of the bridge circuit; and
a control unit configured to switch a semiconductor switch in the bridge circuit, the bridge circuit including a plurality
of switching arms each of which comprises an inverse-parallel connection of the semiconductor switch and a diode,

wherein the control unit switches the semiconductor switch such that a voltage between the AC terminals of the bridge circuit
becomes a positive-negative voltage whose peak value is the voltage between the DC terminals only during prescribed equal
time periods before and after a point that has deviated from each zero crossing point in one cycle of the input current by
a prescribed compensation period and such that the voltage between the AC terminals becomes a zero voltage during time periods
other than said prescribed equal time periods, and sets the compensation period such that a time period during which the voltage
between the AC terminals becomes a zero voltage is minimized to maximize an input power factor.

US Pat. No. 9,603,291

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
an outer case including a protruding member protruding upwardly therefrom;
a semiconductor element accommodated in the outer case;
a control circuit board fixed to the outer case at a position away from the semiconductor element;
a shield plate having a through-hole and provided between the semiconductor element and the control circuit board;
a support separately formed from the protruding member, and having a base portion accommodated in the outer case and a convex
portion protruding from the base portion to the control circuit board through the through-hole, the base portion having a
diameter larger than that of the convex portion and supporting the shield plate thereon, and the convex portion supporting
a rear surface of the control circuit board at an upper portion thereof;

a first fixing member engaging the convex portion to fix the shield plate on the base portion; and
a second fixing member engaging the protruding member or the convex portion to fix the control circuit board to the outer
case,

wherein the convex portion is longer than a thickness of the shield plate.

US Pat. No. 9,411,346

INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE

Fuji Electric Co., Ltd., ...

1. An integrated circuit, comprising a voltage divider circuit, having:
a resistive voltage divider element for dividing a voltage between ground and a high-voltage line which supplies a voltage
obtained by rectifying an alternating-current voltage or a direct-current voltage;

a switch which is connected in series to the resistive voltage divider element and which cuts off a current path formed between
the high-voltage line and ground via the resistive voltage divider element; and

switching means for opening and closing the switch according to the state of a semiconductor device which is a supply destination
of the voltage obtained by division by the resistive voltage divider element,

the voltage divider circuit being formed on the same semiconductor substrate as the semiconductor device
wherein the switch is a MOSFET, and at least one resistor constituting the resistive voltage divider element is formed so
as to be completely surrounded by the MOSFET, and one end of the resistor is connected to a drain terminal of the MOSFET.

US Pat. No. 9,269,579

METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method for manufacturing a silicon carbide semiconductor device in which an electrode structure is formed on a silicon
carbide substrate, the method comprising:
forming a metal film comprised of a first metal on a surface of the silicon carbide substrate;
annealing the silicon carbide substrate on which the metal film has been formed to change the metal film into a metal silicide
film, a graphite layer being formed on the metal silicide film as a result of the forming the metal silicide film;

forming a metal layer comprised of a second metal on the graphite layer; and
performing a further annealing to the silicon carbide substrate on which the metal layer has been formed to thereby change
the graphite layer into a carbide layer, and to thereby eliminate the graphite layer.

US Pat. No. 9,301,403

METHOD OF SOLDERING ELECTRONIC PART

FUJI ELECTRIC CO., LTD., ...

1. A method of soldering an electronic part by two steps of high- and low-temperature soldering in a reflow process employing
at least two kinds of solders having different reflow temperatures, characterized in that;
high-temperature soldering as the former step is carried out by employing a solder cream obtained by kneading an Sn—Ag—Cu
alloy with a flux, wherein the Sn—Ag—Cu alloy comprises a mixture of a first powder alloy for a high melting point and a second
powder alloy for a low melting point,

the first powder alloy comprises 10 to 30% by weight of Ag and 2 to 20% by weight of Cu with a balance consisting of Sn and
unavoidable impurities,

the second powder alloy comprises smaller compositions (% by weight) of Ag and Cu than the first powder alloy and having a
melting point lower than that of the first powder alloy and,

the mixture contains a total of not more than 35% by weight of Ag and Cu,
and further, the total amount of Ag component in the alloy composition of the mixture after melting is more than 10% by weight,
and

whereafter low-temperature soldering as the latter step is carried out by employing a solder cream obtained by kneading the
second powder alloy with a flux.

US Pat. No. 9,596,791

COOLING DEVICE AND POWER CONVERTER HAVING COOLING DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A cooling device, comprising:
a rectangular parallelepiped housing having a longitudinal axis and in which a plurality of electronic components, including
a heat generating electronic component, is housed, the plurality of electronic components being arranged along a longitudinal
direction of the housing to have a first end of the electronic components arranged opposite a second end of the electronic
components along the longitudinal direction;

a plurality of heat-radiating side wall fins formed on an outer surface of a first side wall of the housing so as to each
have a side longitudinal axis that extends in parallel with the longitudinal axis of the housing, at least one of the side
wall fins extending along the side longitudinal axis thereof from the first end of the electronic components to the second
end of the electronic components;

a plurality of heat-radiating bottom fins formed on a bottom surface of a bottom portion of the housing so as to each have
a bottom longitudinal axis that extends in parallel with the longitudinal axis of the housing, at least one of the bottom
fins extending along the bottom longitudinal axis thereof from the first end to the second end;

a cover member covering the plurality of heat-radiating side wall fins and the plurality of heat-radiating bottom fins from
an outer side, the cover member forming a side wall cooling channel between the plurality of heat-radiating side wall fins,
and further forming a bottom cooling channel between the bottom fins;

a fluid introduction chamber attached to a second side wall of the housing, the fluid introduction chamber facing in a direction
crossing the first side wall, and in a direction to face the second side wall so that the side wall cooling channel and the
bottom cooling channel communicate with the fluid introduction chamber; and

a coolant supply device externally attached to the chamber and supplying a coolant to the side wall and bottom cooling channels
via the fluid introduction chamber,

wherein the side wall fins and the bottom fins are formed in predetermined shapes, whereby an amount of the coolant supplied
from the coolant supply device to the side wall cooling channel is adjusted and an amount of the coolant supplied from the
coolant supply device to the bottom cooling channel is adjusted.

US Pat. No. 9,287,698

POWER CONVERSION APPARATUS

FUJI ELECTRIC CO., LTD., ...

1. A power conversion apparatus for driving an AC motor by using an inverter having a DC side to which a parallel circuit
having a DC power supply and a capacitor is connected, wherein a controller for controlling semiconductor switching devices
of the inverter includes:
a current detecting unit which detects an output current of the inverter;
an overcurrent level determining unit which determines an overcurrent level for stopping operation of the inverter in accordance
with a value corresponding to a number of revolutions of the motor;

a current comparing unit which compares a detected output current value of the inverter outputted from the current detecting
unit with the overcurrent level determined by the overcurrent level determining unit; and

a drive signal generating unit which generates a signal for turning off all the semiconductor switching devices of the inverter
when the current comparing unit makes a determination that the detected output current value has reached the overcurrent level;

wherein:
the overcurrent level determined by the overcurrent level determining unit becomes lower in terms of value as the value corresponding
to the number of revolutions becomes larger in a constant output region of the motor.

US Pat. No. 9,263,075

MAGNETIC RECORDING MEDIUM FOR HEAT-ASSISTED RECORDING DEVICE AND MANUFACTURING METHOD THEREOF

Fuji Electric Co., Ltd., ...

1. A magnetic recording medium for a heat-assisted recording device, comprising, in the order recited:
a non-magnetic substrate;
a magnetic recording layer;
a protective layer; and
a liquid lubricating layer,
wherein the magnetic recording layer has a granular structure formed by magnetic portions and non-magnetic portions that surround
the magnetic portions in which the non-magnetic portions between adjacent magnetic portions are recessed with respect to the
magnetic portions, the non-magnetic portions having a volume percentage based on total volume of the granular structure ranging
from 15 vol % to 30 vol % and including a carbon-based material, and

wherein the magnetic recording medium has a surface having an arithmetic mean roughness Ra and an average length of roughness
curve elements RSm such that Ra/RSm ranges from 0.05 to 0.15.

US Pat. No. 9,285,298

METHOD OF ANALYZING MICROPARTICLE COMPOSITION AND MICROPARTICLE COMPOSITION ANALYZING DEVICE

THE UNIVERSITY OF TOKYO, ...

1. A method of obtaining a component of a microparticle composition to be analyzed, using a particle trap having a mesh-shaped
structure for capturing microparticles of the microparticle composition, the method comprising:
converging microparticles in a gas sample to form a particle beam, wherein an excess gas phase component in the gas sample
is removed from the particle beam;

capturing the microparticles in the particle beam with the particle trap having the mesh-shaped structure by irradiating a
narrow region of the particle trap with the particle beam; and

vaporizing, sublimating, or reacting the microparticles captured by the particle trap by performing concentrated irradiation
of the narrow region of the particle trap in which the microparticles are captured with an energy beam to yield a desorbed
component for analysis;

wherein the mesh-shaped structure of the particle trap comprises (i) a first mesh-shaped structure having a predetermined
porosity and which is disposed on a front side of the particle trap, which front side is to be irradiated with the particle
beam, and (ii) a second mesh-shaped structure having a porosity smaller than that of the first mesh-shaped structure, which
is disposed on a back side of the particle trap which is a side opposite to the front side, the second mesh-shaped structure
being connected to the first mesh-shaped structure.

US Pat. No. 9,269,644

METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method for producing a semiconductor device comprising:
solder-connecting a semiconductor chip, onto an insulating substrate comprising a ceramic board and having conductor layers
on two surfaces thereof, with a lead-free solder,

warping a radiating base such that a surface of the radiating base on a side opposite to the insulating substrate is convex,
and

solder-connecting the insulating substrate onto the warped radiating base with the lead-free solder so as to provide a substantially
flat solder-connected radiating base,

wherein the conductive layer on one surface of the insulating substrate solder-connecting to the radiating base has a thickness
greater than that of the conductive layer on the other surface of the insulating substrate.

US Pat. No. 9,263,367

SEMICONDUCTOR DEVICE

HONDA MOTOR CO., LTD., T...

1. A semiconductor device comprising:
an insulation circuit substrate:
a semiconductor element mounted on the insulation circuit substrate; and
a cooler which cools the semiconductor element connected to the insulation circuit substrate,
wherein the cooler comprises:
a heat dissipation substrate joined to the insulation circuit substrate;
a fin provided on a surface opposite to the joining surface with the insulation circuit substrate on the heat dissipation
substrate;

a case which houses the fin and is connected to the heat dissipation substrate;
an inlet and an outlet for a coolant which are provided on side walls of the case, the side walls being opposed to each other,
and are provided at diagonal positions of the case;

an introduction path which is connected to the inlet and is formed along the inner surface of a first side wall on which the
inlet of the case is provided;

a discharge path Which is connected to the outlet and is formed along the inner surface of a second side wall on which the
outlet of the case is provided; and

a cooling flow channel which is formed at a position where the fin is housed between the introduction path and the discharge
path,

wherein the height of the opening of the inlet is larger than the height of the introduction path, and, at a connecting portion
between the inlet and the introduction path, an inclined surface which is inclined in the longitudinal direction of the introduction
path from the bottom surface of the connecting portion is provided.

US Pat. No. 9,293,564

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device including:
an active region through which a current flows when in an on-state;
a termination structure portion surrounding the active region, which secures a predetermined breakdown voltage;
a first parallel pn layer provided from the active region over to the termination structure portion, in which first-conductivity-type
semiconductor regions and second-conductivity-type semiconductor regions are alternately disposed; and

a second parallel pn layer disposed on the top of the first parallel pn layer, the method comprising:
(a) forming the first parallel pn layer in a first formation step;
(b) depositing a first-conductivity-type first semiconductor layer on a surface of the first parallel pn layer in a second
formation step that further includes forming the second parallel pn layer by selectively introducing second-conductivity-type
impurities into the first semiconductor layer; and forming first second-conductivity-type impurity regions in positions opposed
in a depth direction to regions of the first parallel pn layer in which the second-conductivity-type semiconductor regions
are formed;

(c) forming a local insulating film on a surface of the first semiconductor layer in the termination structure portion so
that an end portion of the local insulating film is positioned on the first second-conductivity-type impurity region, by heating
in a first heat treatment at a low temperature effective to suppress diffusion of the first second-conductivity-type impurity
regions; and

(d) diffusing the first second conductivity type impurity regions by heating in a second heat treatment.

US Pat. No. 9,294,093

LEVEL SHIFT CIRCUIT UTILIZING RESISTANCE IN SEMICONDUCTOR SUBSTRATE

FUJI ELECTRIC CO., LTD., ...

1. An apparatus, comprising:
a first signal output device configured to output a first level shifting signal and including a first resistance;
a second signal output device configured to output a second level shifting signal and including a second resistance;
wherein the first level shifting signal and the second level shifting signal are to control an output switching element of
a high potential side of an output device comprising a power source and a load;

a first detector device configured to compare the first level shifting signal to a reference signal and output a first comparison
result signal to a first switching element coupled to the first resistance; and

a second detector device configured to compare the second level shifting signal to the reference signal and output a second
comparison result signal to a second switching element coupled to the second resistance;

wherein
the first comparison result signal and second comparison result signals are configured to at least partly control switching
of the first switching element and the second switching element, and

each of the resistance and the second resistance is a parasitic resistance in a semiconductor substrate included in the apparatus.

US Pat. No. 9,293,525

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a well region of a second conductivity type that is selectively formed in a surface layer of a front surface of a semiconductor
substrate of a first conductivity type;

a first region of the first conductivity type which is formed in the well region and has an annular shape in a plan view;
a second region of the second conductivity type that is formed inside the first region of the well region and has an annular
shape in a plan view;

a RESURF region of the first conductivity type that is formed between the first region and the second region in the well region;
and

a high voltage isolation structure that has a double RESURF structure in which the well region is interposed between the semiconductor
substrate and the RESURF region,

wherein the high voltage isolation structure has a planar shape that includes a straight portion and a corner portion which
is connected to the straight portion and has a constant curvature,

the RESURF region in the corner portion includes a high concentration region and a low concentration region which has a smaller
diffusion depth and a lower impurity concentration than the high concentration region,

both a first total net amount of impurities per unit area in the straight portion of the RESURF region and a second total
net amount of impurities per unit area in the corner portion of the RESURF region are equal to or less than 1.4×1012[/cm2],

a third total net amount of impurities of the well region is equal to or less than 2.8×1012[/cm2],

both a value obtained by subtracting the first total net amount of impurities from the third total net amount of impurities
and a value obtained by subtracting the second total net amount of impurities from the third total net amount of impurities
are equal to or less than 1.4×1012[/cm2],

the second total net amount of impurities is less than the first total net amount of impurities, and
a maximum breakdown voltage of the straight portion is higher than a maximum breakdown voltage of the corner portion.

US Pat. No. 9,165,871

SEMICONDUCTOR UNIT AND SEMICONDUCTOR DEVICE USING THE SAME

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor unit comprising:
a plurality of semiconductor chips connected in parallel, each of the semiconductor chips being an SiC switching device having
one principal surface and an other principal surface, wherein a first main electrode is formed on the one principal surface
while a second main electrode and a gate electrode are formed on the other principal surface;

a first common conductive plate having a first principal surface and a second principal surface, wherein the first main electrodes
are joined to the first principal surface of the first common conductive plate;

a conductive block joined to the second main electrode;
a second common conductive plate having a first principal surface and a second principal surface, wherein the first principal
surface of the second common conductive plate are connected to the conductive block;

an insulating resin packed in between the first principal surface of the first common conductive plate and the first principal
surface of the second common conductive plate, with the second principal surface of the first common conductive plate and
the second principal surface of the second common conductive plate being exposed; and

a third conductive plate electrically insulated from the second common conductive plate and passing through the second principal
surface of the second common conductive plate, wherein the gate electrodes are connected to the third conductive plate.

US Pat. No. 9,300,204

SWITCHING POWER SUPPLY

FUJI ELECTRIC CO., LTD., ...

1. A switching power supply comprising:
a main body of the switching power supply that performs switching operation of input voltage through switching a switching
element to obtain a specified output voltage;

a control circuit that ON/OFF drives the switching element at a predetermined frequency;
a noise detecting circuit that detects GND bounce noise developed on a ground line of the control circuit accompanying the
switching of the switching element; and

a canceling signal generating circuit that generates a canceling signal corresponding to the GND bounce noise and in a reversed
phase with respect to the GND bounce noise and adds the canceling signal onto the ground line of the control circuit when
the noise detecting circuit detects the GND bounce noise;

wherein the noise detecting circuit detects the GND bounce noise based on an output voltage of a current transformer linked
with the ground line exceeding a threshold level for noise detection a predetermined number of successive times.

US Pat. No. 9,356,100

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a first conductivity type silicon carbide substrate;
a first conductivity type silicon carbide layer formed on a surface of the first conductivity type silicon carbide substrate,
and having an impurity concentration that is lower than that of the first conductivity type silicon carbide substrate;

a second conductivity type region selectively formed inside the first conductivity type silicon carbide layer;
a second conductivity type silicon carbide layer formed on surfaces of the first conductivity type silicon carbide layer and
the second conductivity type region, and having an impurity concentration that is lower than that of the second conductivity
type region;

a first conductivity type region selectively formed inside the second conductivity type silicon carbide layer, penetrating
the second conductivity type silicon carbide layer in a depth direction, and in contact with the first conductivity type silicon
carbide layer;

a first conductivity type source region formed inside the second conductivity type silicon carbide layer;
a second conductivity type high-concentration region formed inside the second conductivity type silicon carbide layer and
disposed on a side opposite to that of the first conductivity type region of the first conductivity type source region;

a source electrode electrically connected to the second conductivity type high-concentration region and the first conductivity
type source region;

a gate electrode formed through a gate insulating film on a surface of a portion between the first conductivity type source
region and the first conductivity type region in the second conductivity type silicon carbide layer, spanning from the first
conductivity type source region to the first conductivity type region;

a drain electrode formed on a back face of the first conductivity type silicon carbide substrate, wherein
an impurity concentration of the first conductivity type region is greater than 1.0×1016 cm?3 and less than or equal to 5.0×1016 cm?3,

a width of the first conductivity type region is within a range from 0.8 ?m to 3.0 ?m;
the second conductivity type silicon carbide layer directly underlies the first conductivity type source region; and
the second conductivity type silicon carbide layer extends to the same length as the second conductivity type region adjacent
to the first conductivity type region.

US Pat. No. 9,222,970

FAULT POSITION ANALYSIS METHOD AND FAULT POSITION ANALYSIS DEVICE FOR SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A fault position analysis method for a semiconductor device, the method comprising:
scanning and irradiating a device and a circuit located on a front surface of a substrate with a laser beam to heat the device
and the circuit from a rear surface side of the substrate of the semiconductor device;

causing a current to flow to the device and circuit while being heated;
detecting a change in a resistance value caused by a change in a current; and
identifying a fault position,
wherein the semiconductor device is a semiconductor device with an N-doped SiC substrate and wherein the laser beam has a
wavelengths of 650 to 810 nm.

US Pat. No. 9,123,696

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

7. An apparatus, comprising:
a plurality of semiconductor modules; and
a cooling device configured to distribute a coolant in a flow direction;
wherein
the plurality of semiconductor modules are arrayed transversely to the flow direction, and include at least an upstream module
and a downstream module, the downstream module being located downstream of the upstream module with respect to the flow direction,

the upstream module includes an upstream resistor and an upstream gate input terminal,
the downstream module includes a downstream resistor and a downstream gate input terminal, and
a gate signal is coupled via the downstream resistor to the upstream gate signal input terminal, and is coupled via the upstream
resistor to the downstream gate signal input terminal.

US Pat. No. 9,443,942

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:
a first conductivity type semiconductor substrate;
a second conductivity type first semiconductor region that is disposed in a front surface layer of the first conductivity
type semiconductor substrate;

a second conductivity type guard ring region that is a breakdown voltage structure disposed surrounding the first semiconductor
region, the guard ring region including a plurality of guard rings;

an insulating film that extends from an end portion of the first semiconductor region and formed to continuously extend over
the plurality of guard rings;

a conductive film that is disposed on the semiconductor substrate so as to be sandwiched between the end portion of the first
semiconductor region and an end portion of the guard ring region, and on the guard ring region via the insulating film; and

a main electrode, disposed on the first semiconductor region, which is spaced away from the conductive film,
wherein the insulating film is formed between the second conductivity type guard ring region and the conductive film without
a trench in the insulating film reaching the second conductivity type guard ring region,

wherein the guard rings are disposed relative to each other and the first semiconductor region so that
an on-time voltage, which is applied to the conductive film at an on-time, forms inversion layers in the front surface layer
of the semiconductor substrate, the inversion layers connecting the guard rings to the first semiconductor region, and further
connecting the guard rings to each other, and

an off-time voltage, which is applied to the conductive film at an off-time, extinguishes the inversion layers.

US Pat. No. 9,433,122

AIR CONDITIONING SYSTEM

FUJITSU LIMITED, Kawasak...

1. An air conditioning system, comprising:
at least one first air conditioner provided in a first space and configured to
suck air exhausted from a high-heat-generation type information technology (IT) rack which generates higher heat than heat
generated by other IT racks, the high-heat generation type IT rack and other IT racks respectively arranged in the first space
and housing at least one information processor,

cool down the sucked air, and
exhaust the cooled air to the high-heat-generation type IT rack; and
a second air conditioner provided in a second space, the second space being divided from and communicated with the first space
via a first opening allowing continuous air ventilation and a second opening allowing continuous air ventilation, and configured
to cool down the at least one information processor housed in the high-heat generation type IT rack and the other IT racks
arranged in the first space by cooling down air exhausted from the first space via the first opening and exhausting the cooled
air back to the first space via the second opening while operating at a reserved cooling capacity,

wherein the first air conditioner includes:
a suction unit that sucks air exhausted from an information processor housed in the high-heat-generation type IT rack;
a cooling unit that cools down the air sucked by the suction unit;
an exhaust unit that exhausts the air cooled down by the cooling unit; and
at least one controller that
acquires a cooling state of the cooling unit,
determines, based on the acquired cooling state, whether a thermal load of the cooling unit exceeds a cooling capacity of
the cooling unit, and

reduces a volume of air exhausted by the exhaust unit by a volume corresponding to the reserved cooling capacity of the second
air conditioner in response to the thermal load of the cooling unit exceeding the cooling capacity of the cooling unit, and

wherein the second air conditioner cools down the sucked air by the first air conditioner using the reserved cooling capacity
of the second air conditioner when the at least one controller of the first air conditioner reduces the volume of the air
exhausted by the exhaust unit of the first air conditioner.

US Pat. No. 9,293,391

SEMICONDUCTOR MODULE COOLER AND SEMICONDUCTOR MODULE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor module cooler, comprising:
a water jacket to which a refrigerant is adapted to be supplied from outside for cooling a semiconductor device disposed outside
the water jacket;

a heat sink thermally connected to the semiconductor device and having a plurality of fins;
a first flow path disposed inside the water jacket and extending from a refrigerant inlet, the first flow path including a
guide portion having an inclined surface for guiding the refrigerant toward one side surface of the heat sink;

a second flow path disposed inside the water jacket parallel to the first flow path at a distance therefrom and extending
toward a refrigerant outlet, the second flow path being formed with a sidewall parallel to the other side surface of the heat
sink;

a flow velocity adjustment plate disposed in the second flow path and formed parallel to the other side surface of the heat
sink at a distance therefrom; and

a third flow path formed at a position communicating the first flow path and the second flow path inside the water jacket,
wherein the plurality of fins is disposed in the third flow path such that a clearance exists between leading ends of the
plurality of fins and a bottom wall of the water jacket, and

the flow velocity adjustment plate protrudes upwardly from the bottom wall of the water jacket and is arranged at a boundary
between the second flow path and the third flow path with a space relative to the plurality of fins to intersect therewith.

US Pat. No. 9,571,001

POWER CONVERSION DEVICE, INCLUDING SERIAL SWITCHING ELEMENT, THAT COMPENSATES FOR VOLTAGE FLUCTUATIONS

FUJI ELECTRIC CO., LTD., ...

1. A power conversion device, comprising:
a first circuit wherein a first inductor and a first bidirectional switching element are directly connected;
a second circuit, connected in parallel to the first bidirectional switching element, wherein a second bidirectional switching
element and a capacitor are connected;

a serial switching element wherein 2N (N being a positive integer) switching elements, in each of which a diode is connected
in anti-parallel, are connected in series;

a serial storage element including first and second storage elements connected in series, the serial storage element being
connected in parallel to the serial switching element;

a first serial rectifier element, connected in parallel to the serial storage element, wherein first and second rectifier
elements are connected in series; and

a second inductor directly connected from an intermediate point of the 2N switching elements to a connection point of the
second bidirectional switching element and the capacitor, wherein

a connection point of the first and second storage elements is directly connected to a connection point of the first bidirectional
switching element and the capacitor,

a connection point of the first and second rectifier elements is directly connected to a connection point of the first bidirectional
switching element and second bidirectional switching element, and

alternating current applied to the first circuit is converted, and output from both ends of the capacitor.

US Pat. No. 9,554,464

METAL-BASE PRINTED CIRCUIT BOARD

Waseda University, (JP) ...

1. A metal-base printed circuit board comprising:
a metal base plate having an insulating resin layer and a copper foil layer stacked thereon, in this order, wherein:
the insulating resin layer comprises a resin, a first inorganic filler made of inorganic particles having an average particle
diameter (D50) of 1 nm to 300 nm, and a second inorganic filler made of inorganic particles having an average particle diameter (D50) of 500 nm to 20 ?m, and

the first inorganic filler and the second inorganic filler are uniformly dispersed in the insulating resin layer, wherein
the content of the first inorganic filler in the insulating resin layer is 1% by mass to 7% by mass, and

the second inorganic filler is inorganic particles made of any one of, or any combination of, BN, AlN, and SiO2.

US Pat. No. 9,276,494

SWITCHING POWER SUPPLY DEVICE, INCLUDING A ZERO CURRENT DETECTING

FUJI ELECTRIC CO., LTD., ...

1. A switching power supply device that includes:
an inductor connected to a rectifier circuit for rectifying AC power,
a switching element forming a current path from the rectifier circuit through the inductor in an ON state of the switching
element;

a diode forming a current path from the inductor to an output capacitor in an OFF state of the switching element; and
a control circuit controlling electric current flowing through the inductor by ON/OFF driving the switching element;
the control circuit comprising:
a zero current detecting circuit that detects a gradient of current flowing through the inductor in an OFF state of the switching
element and detects a timing of zero current flowing through the inductor corresponding to the detected gradient to turn ON
the switching element, and

an ON width generating circuit that compares a comparison reference voltage generated based on an output voltage obtained
at the output capacitor with a ramp voltage generated upon turning ON of the switching element to determine an ON width of
the switching element, and turns OFF the switching element;

wherein the zero current detecting circuit
receives a signal for controlling ON/OFF driving of the switching element,
receives a voltage signal proportional to the current flowing through the inductor in an OFF state of the switching element,
compares the voltage signal sequentially with a first comparison reference voltage and a second comparison reference voltage,
detects a gradient of the current flowing through the inductor, and
detects the timing of zero current flowing through the inductor corresponding to the detected gradient of current; and
wherein the zero current detecting circuit comprises a capacitor that is charged by a first constant current source and discharged
by a second constant current source,

charges the capacitor by the first constant current source after the voltage signal exceeds the first comparison reference
voltage until the voltage signal reaches the second comparison reference voltage,

then discharges a charged voltage of the capacitor by the second constant current source, and
detects a timing at which the charged voltage of the capacitor reaches a third comparison reference voltage through the discharge
as the timing of zero current flowing in the inductor.

US Pat. No. 9,176,454

ELECTROPHOTOGRAPHIC PHOTORECEPTOR

FUJI ELECTRIC CO., LTD., ...

1. An electrophotographic photoreceptor, which is used by being detachably mounted onto an apparatus main body of an electrophotographic
application apparatus while being incorporated in a process cartridge, the apparatus main body including a drive-side power
transmission portion, the electrophotographic photoreceptor comprising:
a photosensitive drum including
a cylindrical conductive substrate having an outer circumferential surface, and
a photosensitive layer containing a photoconductive material on the outer circumferential surface; and
a flange that is fitted to an edge of the photosensitive drum, the flange configured to transmit a rotational driving force
from the drive-side power transmission portion to the photosensitive drum, the flange including

a driving force receiving portion, and
a driven-side power transmission portion configured to transmit the rotational driving force from the drive-side power transmission
portion to the driving force receiving portion, the driven-side power transmission portion including

a cylindrical body, a core of the cylindrical body being a central shaft of the photosensitive drum, the cylindrical body
protruding from the driving force receiving portion, and

a plurality of hemispherical engaging projections that are disposed at each trisection point of an outer circumference of
the cylindrical body in such a manner so as to protrude in a radially outward direction from the outer circumference, away
from the driving force receiving portion, and to be configured to come into engagement with the drive-side power transmission
portion, circumferences of the hemispherical engaging projections being disposed in direct contact with the cylindrical body.

US Pat. No. 9,293,982

SWITCHING POWER SUPPLY

FUJI ELECTRIC CO., LTD., ...

1. A switching power supply comprising:
a switching power supply main body configured to switch an input voltage through a switching element at a specified frequency
to apply the switched voltage to a primary winding of a transformer, and rectify and smooth an AC voltage developed across
a secondary winding of the transformer to obtain a specified output voltage;

a control circuit configured to conduct feedback control of a pulse width of a driving signal for switching the switching
element according to the output voltage of the switching power supply main body and settle the output voltage to a specified
voltage level;

a frequency reducing circuit that is disposed in the control circuit and is configured to reduce a frequency of the driving
signal for switching the switching element upon detection of an overload state of the switching power supply main body and
limit an output current of the switching power supply; and

an initial state setting circuit that is configured to set the control circuit to an overload detecting state for a predetermined
period of time in a startup period of the control circuit,

wherein
the control circuit is further configured to compare an output signal of an oscillator, an oscillation frequency of which
varies corresponding to a feedback voltage generated by detecting the DC output voltage of the switching power supply main
body, with the feedback voltage, and compare the output signal of the oscillator with a control voltage for soft starting
generated at the startup period of the control circuit, to generate a driving signal for switching the switching element;
and

the initial state setting circuit is composed of a switch circuit that is configured to pull down the control voltage for
soft starting to a ground potential for a predetermined period of time in the startup period of the control circuit to inhibit
generation of the driving signal, and to pull up the feedback voltage to a voltage exhibiting an overload state.

US Pat. No. 9,622,351

SEMICONDUCTOR MODULE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor module comprising:
a laminate substrate including an insulative plate, a circuit board provided on a first surface of the insulative plate and
a metal plate provided on a second surface that is opposite to the first surface; and

an interconnecting substrate that opposes the laminate substrate, the interconnecting substrate including a metal layer, wherein
the insulative plate extends more outside than an outer edge portion of the circuit board, and
the metal layer has a region overlapping the outer edge portion of the circuit board and extends more outside than the outer
edge portion of the circuit board.

US Pat. No. 9,504,154

SEMICONDUCTOR DEVICE

Fuji Electric Co., Ltd., ...

1. A semiconductor device comprising:
a plurality of semiconductor modules, each having one or more semiconductor chips mounted on an insulated circuit board and
contained in a casing, with externally connecting terminals connected to the semiconductor chips or the insulated circuit
board protruding from the casing;

bus bars electrically connecting specific externally connecting terminals of the plurality of semiconductor modules arranged
in parallel; and

a semiconductor module case having through-holes for protruding external terminals that are portions of the bus bars, and
covering and fastening the plurality of semiconductor modules that are connected by the bus bars;

wherein the bus bars and the externally connecting terminals of the semiconductor modules are connected by means of laser
welding.

US Pat. No. 9,204,559

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND MOUNTING JIG

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device, comprising:
a process of joining a plurality of tubular contact elements onto a circuit pattern on an insulated circuit board, said process
comprising the steps of:

preparing a mounting jig having an insulated circuit board positioning jig for holding the insulated circuit board at a predetermined
position for positioning, a tubular contact element positioning jig having a plurality of positioning holes disposed at predetermined
positions to insert the plurality of tubular contact elements, and a tubular contact element press-down jig for pressing down
the plurality of tubular contact elements inserted into the respective positioning holes in the tubular contact element positioning
jig;

positioning the insulated circuit board by housing the insulated circuit board in a predetermined position on the insulated
circuit board positioning jig;

positioning the plurality of tubular contact elements on a circuit pattern on the insulated circuit board by laying the tubular
contact element positioning jig on the insulated circuit board positioning jig and inserting the plurality of tubular contact
elements into the respective positioning holes in the tubular contact element positioning jig; and

placing the tubular contact element press-down jig on the tubular contact element positioning jig and heating while pressing
down the plurality of tubular contact elements inserted in the plurality of positioning holes of the tubular contact element
positioning jig toward the insulated circuit board, to solder the plurality of tubular contact elements positioned on the
circuit pattern on the insulated circuit board to the circuit pattern on the insulated circuit board positioned in the insulated
circuit board positioning jig.

US Pat. No. 9,661,783

MAGNETIC COMPONENT COOLING STRUCTURE AND POWER CONVERTER HAVING THE SAME

FUJI ELECTRIC CO., LTD., ...

1. A magnetic component cooling structure for cooling a magnetic component, the magnetic component cooling structure comprising:
a housing that the magnetic component is disposed within;
an inner fan disposed inside the housing to generate cool air that flows in the housing so that a cool air flow space, in
which the cool air generated by the inner fan flows in the housing, is formed;

an attachment member mounting the magnetic component on a bottom portion of the housing so that the magnetic component is
fixed to a position within the cool air flow space such that the cool air is blown from the inner fan to the magnetic component,
the attachment member including:

a top plate that makes contact with an upper surface of the magnetic component;
a pair of legs that extends downward from the top plate and that is fixed to the bottom portion; and
a guiding plate that guides the cool air blown from the inner fan into the magnetic component.

US Pat. No. 9,225,233

POWER CONVERSION DEVICE CONTROL DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A power conversion device control device, comprising:
a semiconductor element drive circuit that drives one of a plurality of semiconductor elements configuring a power conversion
device based on a drive signal input from a control circuit;

a plurality of protection circuits that detect information necessary in order to carry out a protection operation of the semiconductor
element; and

an alarm signal formation circuit, in which there is set a pulse signal having as one cycle a period in which are combined
a determination period, of which a different period is set for each of the plurality of protection circuits, and a constant
period whose condition varies with respect to the determination period, in which a protection circuit among the plurality
of protection circuits for which it is first detected that a protection operation is necessary is taken as a first-come first-served
protection circuit, and in which the pulse signal corresponding to the protection circuit is output as an alarm signal to
an alarm signal terminal, wherein

the alarm signal formation circuit is such that a resetting condition of the alarm signal is a condition that a protection
operation stopped condition, wherein it is detected that no protection operation is necessary in at least the first-come first-served
protection circuit, is met, and a determination of the resetting condition is carried out during the constant period of the
pulse signal.

US Pat. No. 9,047,905

RECORDING MEDIUM

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a recording medium, comprising:
forming a magnetic layer on a substrate;
forming an underlayer on the magnetic layer, the underlayer comprising a material selected from the group consisting of silicon,
silicon carbide and germanium, a thickness of the underlayer being 0.3 nm or greater and 1.8 nm or less, and

forming a carbon layer comprising amorphous carbon containing hydrogen on the underlayer, an amount of hydrogen included in
the carbon layer being 24.7 at % or higher and 46.8 at % or lower, and a thickness of the carbon layer being 0.2 nm or greater
and 1.7 nm or less

wherein the carbon layer is formed by ECWR with an output power of 190 W to 1050 W and a pressure of 0.09 Pa to 0.35 Pa
wherein either an ECWR plasma source was used with an output power of 1050 W and a pressure of 0.09 Pa applied to deposit
an carbon layer with a targeted hydrogen content of 30 at % or an ECWR plasma source was used with an output power of 190
W and a pressure of 0.35 Pa applied to deposit a carbon layer with a targeted hydrogen content of 45 at %.

US Pat. No. 9,051,644

THIN-FILM MANUFACTURING METHOD AND APPARATUS

Fuji Electric Co., Ltd., ...

1. A DLC thin-film manufacturing method, comprising the steps of:
generating a plasma from source gas comprising hydro-carbon series gas;
extracting carbon ions from the plasma; and
depositing a DLC thin film on at least one side of a substrate to be deposited with the carbon ions, wherein
the method is performed in an apparatus having: a plasma chamber generating the plasma; a film deposition chamber accommodating
the substrate to be deposited; an ion transfer path for transferring the carbon ions from the plasma chamber to the film deposition
chamber; a branch pipe branching from the ion transfer path; and an exhaust pump connected to the branch pipe and extending
in the direction of the carbon ions being extracted from the plasma, and wherein

the DLC thin film is formed while the source gas except the carbon ions is being exhausted from the branch pipe to the exhaust
pump linearly in the same direction as the direction of extracting the carbon ions from the plasma chamber.

US Pat. No. 9,408,322

CASE UNIT

FUJI ELECTRIC CO., LTD., ...

1. A case unit that accommodates an electric apparatus body into a case of a predetermined size and is detachably mounted
on a rack body from a front side of the rack body so as to operate the electric apparatus body, the case unit comprising:
a pair of case attachment members that are provided at both ends of a front side of the case while being projected in the
horizontal direction so as to fix the case to the rack body;

a screw insertion hole that is provided at each of the case attachment members and is used to insert a fixing screw of the
case into the rack body;

a sliding member that is provided in a front panel of the case so as to be movable in the vertical direction and is placed
at a down position due to the weight of the sliding member;

a window portion that is provided in the sliding member and is used to cover and hide the screw insertion hole when the sliding
member is located at the down position and to expose the screw insertion hole when the sliding member is lifted to an up position
against gravity; and

an interlocking switch that is provided in the case and is used to control the operation of the electric apparatus body in
a manner such that the interlocking switch is pressed by the sliding member and turned on when the sliding member is placed
to the up position, and is released from the pressure of the sliding member and turned off when the sliding member is placed
at the down position.

US Pat. No. 9,129,819

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

10. A device, comprising:
an active element portion on a semiconductor substrate; and
an edge structure bordering the active element portion, and including straight portions and curved corner portions;
wherein the edge structure further includes
guard rings in the straight portions and curved corner portions,
bridge structures at intervals along a periphery of the edge structure, and
connective structures for electrically connecting the guard rings to the bridge structures,
the guard rings including
a first guard ring in a first curved corner portion and a first straight portion of the straight portions and curved corner
portions, and

a second guard ring, adjacent to the first guard ring, in a second curved corner portion and a second straight portion of
the straight portions and curved corner portions; and

wherein a connective structure of the connective structures is present in both the first curved corner portion and in second
curved corner portion, and

in the second guard ring, a connective structure of the connective structures is present in the second curved corner portion
but absent in at least part of the second straight portion.

US Pat. No. 9,111,759

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device manufacturing method, comprising:
a first step of forming a first alignment mark in one portion of a semiconductor substrate doped with 1.0×1019/cm3 or more of arsenic; and

a second step of forming a second alignment mark by an epitaxial layer being grown on a main surface of the semiconductor
substrate, and a portion of the epitaxial layer above the first alignment mark being transformed in accordance with the first
alignment mark,

wherein the epitaxial layer is grown in the second step at atmospheric pressure using trichlorosilane as a raw material gas,
with an epitaxial growth temperature of 1,150° C. to 1,180° C., and an epitaxial growth rate of 2.2 ?m per minute to 2.6 ?m
per minute.

US Pat. No. 9,062,647

SEMICONDUCTOR DEVICE INCLUDING CURRENT CONTROL FUNCTION AND SELF-INTERRUPT FUNCTION

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:
a first series circuit wherein a first semiconductor switching element and a sense resistor are connected in series:
a second semiconductor switching element connected in parallel to the first series circuit;
a drive signal control circuit, into which a drive signal is input, that outputs a drive control signal controlling the first
and second semiconductor switching elements; and

a self-interrupting circuit connected to the drive signal control circuit, wherein
the self-interrupting circuit
outputs a predetermined voltage to the drive signal control circuit at a time of normal operation, and
outputs a voltage whose amplitude temporally changes in stages to the drive signal control circuit at a time of abnormal operation,
and the drive signal control circuit
controls so that the amplitude of the drive control signal decreases when the voltage across the sense resistor is higher
than the output voltage of the self-interrupting circuit, and

controls so that the amplitude of the drive control signal increases when the voltage across the sense resistor is lower than
the output voltage of the self-interrupting circuit.

US Pat. No. 9,310,295

LASER-TYPE GAS ANALYZER

FUJI ELECTRIC CO., LTD., ...

1. A laser-type gas analyzer, comprising:
a mid-infrared laser light-emitting unit that emits laser light of a wavelength band of a mid-infrared region that includes
an optical absorption spectrum of a first gas to be measured;

a mid-infrared laser driving unit that drives the mid-infrared laser light-emitting unit;
a mid-infrared laser optical unit that collimates the laser light emitted by the mid-infrared laser light-emitting unit, and
irradiates the light into a space to be measured in which the first gas to be measured is present;

a mid-infrared light-receiving unit that receives the laser light irradiated by the mid-infrared laser optical unit, and outputs
the received laser light as an electrical mid-infrared light reception signal;

a mid-infrared light reception signal processing and computing unit that extracts, from the mid-infrared light reception signal,
a signal component affected by optical absorption by the first gas to be measured, and calculates a gas concentration of the
first gas to be measured on the basis of an amount of change of this signal component;

a near-infrared laser light-emitting unit that emits, at respective times, first laser light of a wavelength band of a near-infrared
region that includes an optical absorption spectrum of a second gas to be measured, second laser light of a wavelength band
of a near-infrared region that includes an optical absorption spectrum of water, and third laser light of a wavelength band
of a near-infrared region in which the optical absorption spectra of water, the first gas to be measured and the second gas
to be measured are equal to or smaller than a predetermined amount;

a near-infrared laser driving unit that drives the near-infrared laser light-emitting unit;
a near-infrared laser optical unit that collimates, at respective times, the first, second and third laser light emitted by
the near-infrared laser light-emitting unit, and irradiates the collimated light to the space to be measured;

a near-infrared light-receiving unit that receives, at respective times, the first, second and third laser light irradiated
by the near-infrared laser optical unit, and outputs the received light as respective electrical near-infrared light reception
signals;

a near-infrared light reception signal processing and computing unit that performs, at respective times, processes of extracting,
from the near-infrared light reception signal of the first laser light, a signal component affected by optical absorption
by the second gas to be measured, and computing a gas concentration of the second gas to be measured on the basis of an amount
of change of this signal component, computing a water concentration in the space on the basis of the near-infrared light reception
signal of the second laser light, and computing a light amount decrement due to dust on the basis of the near-infrared light
reception signal of the third laser light; and

a gas concentration correcting unit that corrects the gas concentration of the first gas to be measured, as worked out by
the mid-infrared light reception signal processing and computing unit and the gas concentration of the second gas to be measured,
as worked out by the near-infrared light reception signal processing and computing unit, in use of the water concentration
and light amount decrement as worked out by the near-infrared light reception signal processing and computing unit.

US Pat. No. 9,299,633

SEMICONDUCTOR DEVICE, HEAT RADIATION MEMBER, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a substrate having a front surface, and a rear surface including a fin forming region and a first peripheral region surrounding
the fin forming region;

an insulating substrate disposed on the front surface;
a semiconductor chip disposed on the insulating substrate;
a first bonding member bonded to the rear surface of the substrate;
a plurality of fins formed in the fin forming region and bonded to the rear surface of the substrate through only the first
bonding member; and

a first reinforcing member formed on the rear surface of the substrate separately from the plurality of fins and bonded to
the rear surface of the substrate through only the first bonding member separately from the plurality of fins, so as to overlap
the first peripheral region.

US Pat. No. 9,299,637

SEMICONDUCTOR MODULE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor module comprising:
a semiconductor element;
a pin electrically and thermally connected to an upper surface of the semiconductor element;
a pin wiring substrate including a pin wiring insulating substrate, a first metal film provided on a lower surface of the
pin wiring insulating substrate, and a second metal film provided on an upper surface of the pin wiring insulating substrate,
the first metal film and the second metal film being electrically bonded to the pin;

solder bonding the pin and the semiconductor element;
a DCB substrate including a ceramic insulating substrate, a third metal film bonded to a lower surface of the semiconductor
element and provided on an upper surface of the ceramic insulating substrate, and a fourth metal film provided on a lower
surface of the ceramic insulating substrate; and

a first cooler thermally connected to the fourth metal film,
wherein a ratio H/T of a height H of the solder to a distance T from the semiconductor element to the first metal film of
the pin wiring insulating substrate is equal to or greater than 0.2 and equal to or less than 0.7.

US Pat. No. 9,178,431

SWITCHING POWER SUPPLY INCLUDING THRESHOLD BASED PERMISSIONS

FUJI ELECTRIC CO., LTD., ...

1. A switching power supply comprising:
a power factor correction converter that conducts switching of an input AC voltage to obtain a DC voltage;
a DC-DC converter that conducts switching of an output voltage of the power factor correction converter to obtain a specified
DC output voltage; and

a load condition detecting circuit that delivers an operation permission signal to the power factor correction converter corresponding
to a load condition of the DC-DC converter and permits or stops operation of the power factor correction converter;

wherein the load condition detecting circuit
sets a second threshold voltage and a third threshold voltage for determining a magnitude of the load on the DC-DC converter
based on the maximum value of the output voltage of the power factor correction converter in a suspended state of operation
of the power factor correction converter;

delivers the operation permission signal when a signal indicating the magnitude of the load on the DC-DC converter changes
from being below the second threshold voltage to exceeding the second threshold voltage for a specified period of time in
a suspended state of operation of the power factor correction converter; and

delivers the operation permission signal when the signal indicating the magnitude of the load on the DC-DC converter changes
from being below the third threshold voltage to exceeding the third threshold voltage in a suspended state of operation of
the power factor correction converter.

US Pat. No. 9,112,503

ELECTROMAGNETIC COIL DRIVE DEVICE

FUJI ELECTRIC CO., LTD., ...

1. An electromagnetic coil drive device, comprising:
a semiconductor switch connected in series with an electromagnetic coil for controlling a current supplied to the coil;
a capacitor;
a comparator for comparing a voltage to charge and discharge the capacitor with two different voltages, for generating a signal
to operate on-off of the semiconductor switch in accordance with a result of a comparison;

a first charging circuit to charge the capacitor based on a voltage applied to the coil; and
a discharging circuit to discharge the capacitor;
wherein the first charging circuit has a first resistor and at least one compensating circuit connected in parallel with the
first resistor, and

the compensating circuit includes:
a first compensating circuit in which a second resistor and a first Zener diode are connected in series, and
a second compensating circuit in which a third resistor and a second Zener diode are connected in series; and
the first Zener diode and the second Zener diode have different Zener voltages.

US Pat. No. 9,397,015

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE CASING

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
an insulating substrate;
a semiconductor element which is mounted on the insulating substrate;
a hollow casing which surrounds a peripheral edge of the insulating substrate to contain the semiconductor element therein;
and

a sealing material which is charged into the casing to seal the inside of the casing; wherein:
the casing has a plurality of protrusion portions separate from each other and protruding partially from an upper surface
of the casing.

US Pat. No. 9,368,613

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method for manufacturing the semiconductor device, comprising:
forming a polysilicon layer on an insulating film;
implanting phosphorus ions into the polysilicon layer and performing a first heat treatment to form a first-conductivity-type
semiconductor layer; and

selectively implanting boron ions and arsenic ions into regions of the first-conductivity-type semiconductor layer so as to
form separated, different implanted regions and performing a second heat treatment of the separated, different implanted regions
to form a plurality of third semiconductor regions and a plurality of first semiconductor regions, which reach the insulating
film through the first-conductivity-type semiconductor layer in a depth direction and have a higher impurity concentration
than the first-conductivity-type semiconductor layer, the plurality of third semiconductor regions and the plurality of first
semiconductor regions being separated from each other by regions of the first-conductivity-type semiconductor layer that are
not implanted with the boron ions and the arsenic ions,

wherein an end of the polysilicon layer comprises a first semiconductor region among the plurality of first semiconductor
regions.

US Pat. No. 9,355,858

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device, comprising:
forming a first semiconductor region of a second conduction type on a side of a wafer of a first conduction type;
forming a front surface element structure on a first main surface of the wafer;
forming a concave portion extending from a second main surface of the wafer to the first semiconductor region;
forming a second semiconductor region of the second conduction type so as to be electrically connected to the first semiconductor
region, the second main surface of the wafer being disposed on the second semiconductor region; and

removing a portion of the first semiconductor region and cutting the wafer into chips, the removing being performed so that
the first semiconductor region is removed such that a cut plane of the first semiconductor region is inclined with respect
to the first main surface of the wafer, an angle between the cut plane and a bottom wall of the concave portion being an acute
angle.

US Pat. No. 9,356,115

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate having a first semiconductor element provided in a first region on one side of the semiconductor
substrate, and a second semiconductor element provided in a second region on another side of the semiconductor substrate to
be side-by-side with the first semiconductor element, the semiconductor substrate being a semiconductor substrate of a first
conduction type that is provided with an insulated gate structure as a top surface element structure of the first semiconductor
element, the insulated gate structure including a base region of a second conduction type, an emitter region of the first
conduction type and a gate electrode, that is provided with an anode region of the second conduction type as a top surface
element structure of the second semiconductor element, that is provided with a collector region of the second conduction type
as a bottom surface element structure of the first semiconductor element, and that is provided with a cathode region of the
first conduction type as a bottom surface element structure of the second semiconductor element;

preparing a light ion source and a mask;
shielding the first region by providing a mask on a top surface of the semiconductor substrate on said one side of the semiconductor
substrate;

irradiating the top surface of the semiconductor substrate with light ions by operating a light ion source to introduce lattice
defects at a specified depth within the second region through the top surface of the semiconductor substrate; and

irradiating a bottom surface of the semiconductor substrate with light ions by operating the light ion source to introduce
lattice defects at a specified depth on the entire bottom surface within the semiconductor substrate;

wherein the first semiconductor element has a minimum carrier lifetime value that is longer than that of the second semiconductor
element;

wherein the anode region of the second semiconductor element has a carrier lifetime that is made shorter during irradiating
the top surface of the semiconductor substrate (a) than that of the emitter region of the first semiconductor element which
is protected by the mask during irradiating, and (b) than that of the cathode region of the second semiconductor element;

wherein the collector region has a carrier lifetime that is made shorter during irradiating the entire bottom surface of the
semiconductor substrate than that of the cathode region, and

wherein the first semiconductor element includes an IGBT region, the second semiconductor element includes an FWD region,
and the semiconductor substrate has a drift region in which is defined a depth region formed at a predetermined depth, D,
that includes at least a portion of the IGBT region and at least a portion of the FWD region, the depth region having a carrier
lifetime that is shortened in both the IGBT region and the FWD region to provide respective short carrier lifetime regions,
provided that the short carrier lifetime region of the IGBT region has a rear surface having a depth that is greater than
that of the short carrier lifetime region of the FWD region.

US Pat. No. 9,299,642

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME

FUJI ELECTRIC CO., LTD., ...

1. A method for producing a semiconductor device comprising:
a step of preparing a frame including a first step portion provided in a ring shape in an inner circumference of one main
surface of the frame, a terminal fixed to the first step portion, a second step portion provided in a ring shape in an inner
circumference of another main surface of the frame, and an inner wall provided between the first step portion and the second
step portion;

a step of preparing a circuit board;
a step of applying a first adhesive resin onto the second step portion while the one main surface of the frame is facing downward;
a step of fitting the circuit board to the second step portion; and
a step of applying a second adhesive resin onto the inner wall and the terminal while the one main surface of the frame is
facing upward.

US Pat. No. 9,276,071

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a first-conduction-type semiconductor substrate including a first-conduction-type drift layer;
a first second-conduction-type semiconductor layer that is provided in one main surface of the semiconductor substrate and
is adjacent to the drift layer;

a second first-conduction-type or second-conduction-type semiconductor layer that is provided in the other main surface of
the semiconductor substrate;

one or more first-conduction-type high-concentration layer that are provided between the drift layer and the second semiconductor
layer and have a higher impurity concentration than the drift layer;

a first crystal defect region including the drift layer; and
a second crystal defect region that includes the high-concentration layer, is provided adjacent to the first crystal defect
region, and has a lower defect concentration than the first crystal defect region.

US Pat. No. 9,076,479

MAGNETIC RECORDING MEDIUM

FUJI ELECTRIC CO., LTD., ...

1. A magnetic recording medium, comprising:
a substrate having sequentially formed thereon, in the order recited,
a magnetic layer;
a protective layer having a thickness ranging from 1.0 nm to 2.5 nm and being comprised of:
an amorphous metal layer formed on the magnetic layer and having a thickness of at least 0.3 nm, the amorphous metal layer
being comprised of a metal selected from the group consisting of Si (silicon), Al (aluminum), Ge (germanium), Ti (titanium),
Zr (zirconium), Hf (hafnium), V (vanadium), Nb (niobium), Ta (tantalum), Cr (chromium), Mo (molybdenum) and W (tungsten) that
is in an amorphous state; and

a carbon layer formed on the amorphous metal layer and having a thickness of at least 0.3 nm, the carbon layer comprising
amorphous carbon; and

a lubricating layer,
wherein the carbon layer and the amorphous metal layer have respective surfaces that contact the lubricating layer, and
wherein the carbon layer includes nitrogen atoms in a surface thereof in which a ratio of number of nitrogen atoms to total
number of carbon atoms, nitrogen atoms, and oxygen atoms is 14 atomic % or less.

US Pat. No. 9,078,355

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:
a control terminal attached to a patterned insulating substrate;
a first projection formed on the control terminal;
a second projection formed on the control terminal away from the first projection;
a valley formed between the first projection and the second projection;
a resin case disposed to cover the patterned insulating substrate, and having an opening for passing the control terminal
therethrough;

a first concave portion formed on a sidewall of the opening of the resin case;
a beam portion disposed at a bottom portion of the opening of the resin case;
a second concave portion formed in the beam portion;
a resin block inserted into the opening of the resin case and sandwiching the control terminal together with the sidewall
of the opening of the resin case to fix the control terminal to the resin case;

a convex step portion formed in the resin block to fit into the valley of the control terminal;
a third projection formed on a side surface of the resin block to fit into the first concave portion; and
a fourth projection formed on a bottom surface of the resin block to fit into the second concave portion.

US Pat. No. 9,418,916

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:
a semiconductor chip;
a first electrode pad and second electrode pad included on the semiconductor chip;
a first conductive post connected to the first electrode pad by a joining material;
a plurality of second conductive posts connected to the second electrode pad by a joining material; and
a printed substrate including an electrical circuit to which the first conductive post and second conductive posts are connected,
wherein

the first electrode pad is disposed opposing an intermediate portion of an edge of the second electrode pad, and
the plurality of second conductive posts are arrayed outside a short-circuit prevention region positioned between two of the
second conductive posts arrayed on a side of the second electrode pad near the first conductive post, the short-circuit prevention
region including a point of intersection of a first imaginary line bisecting the two of the second conductive posts and a
second imaginary line, the second imaginary line being perpendicular to the first imagery line and bisecting the first conductive
post, and the short-circuit prevention region being free of any second conductive posts.

US Pat. No. 9,369,061

RECTIFIER CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A rectifier circuit which converts an AC input voltage that is received at first and second AC input terminals to DC voltage,
comprising:
a diode bridge that includes a first series of diodes and a second series of diodes connected in parallel to the first series
of diodes, the diode bridge including a first AC input node, a second AC input node, a first rectifier output node, and a
second rectifier output node, the second AC input node being connected to the second AC input terminal;

an inductor connected between the first AC input terminal and the first AC input node of the diode bridge;
a capacitor series circuit in which a plurality of capacitors are connected in series between the first and second output
nodes of the diode bridge, the capacitor series circuit having an intermediate connection node between two of the capacitors;

a first bi-directional switch capable of passing and shutting off current in a forward direction and in a reverse direction,
the first bi-directional switch being connected between the first AC input node of the diode bridge and the intermediate connection
node; and

a second bi-directional switch capable of passing and shutting off current in a forward direction and in a reverse direction,
the second bi-directional switch being connected between the second AC input terminal and the intermediate connection node,

wherein the diodes in the first series of diodes are fast recovery diodes and the diodes in the second series of diodes are
not fast recovery diodes, the diodes in the first series of diodes having shorter reverse recover time than the diodes in
the second series of diodes, the diodes in the second series of diodes having smaller forward voltage drop than the fast recovery
diodes, and

wherein the first bi-directional switch is driven at a first frequency that is higher than a second frequency at which the
second bi-directional switch is driven.

US Pat. No. 9,362,392

VERTICAL HIGH-VOLTAGE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

FUJI ELECTRIC CO., LTD., ...

1. A vertical high-voltage semiconductor device comprising:
a first-conductivity-type semiconductor substrate;
a first-conductivity-type semiconductor layer formed on the semiconductor substrate and having a concentration lower than
the semiconductor substrate;

a high-concentration second-conductivity-type semiconductor layer selectively formed in a surface of the semiconductor layer;
a second-conductivity-type relatively low concentration semiconductor base layer formed on the first-conductivity-type semiconductor
layer and the second-conductivity-type semiconductor layer;

a first-conductivity-type source region selectively formed in a surface layer of the second-conductivity-type base layer;
a first-conductivity-type well region formed to penetrate the second-conductivity-type base layer from a surface to the first-conductivity-type
semiconductor layer;

a gate electrode layer disposed via a gate insulating film on at least a portion of a surface exposed portion of the second-conductivity-type
base layer interposed between the first-conductivity-type source region and the first-conductivity-type well region;

a source electrode connected via the first-conductivity-type source region and a contact auxiliary layer to the second-conductivity-type
base layer; and

a drain electrode disposed on a back surface of the first-conductivity-type semiconductor substrate, wherein
portions of the high concentration second-conductivity-type layer and the second-conductivity-type base layer are joined outside
of the well region so as to include a point that is farthest and equidistant from centers of all the source regions facing
each other and that is closest and equidistant from end portions farthest from the centers of the source regions in a planar
view.

US Pat. No. 9,231,479

POWER SUPPLY DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A power supply device, comprising:
a rectifier circuit that rectifies an alternating current power supply voltage;
a first semiconductor switching device for controlling an input current waveform of the rectifier circuit to a sinusoidal
wave;

a smoothing capacitor to which an output voltage of the rectifier circuit is applied;
a step-up chopper that steps up a voltage across the smoothing capacitor; and
an inverter that converts a direct current output voltage of the step-up chopper into an alternating current output voltage
and supplies the alternating current output voltage to a load,

the step-up chopper including an inductor and a diode mutually connected in series to a positive side direct current bus between
the smoothing capacitor and inverter and a second semiconductor switching device connected between a connection point of the
inductor and diode and a negative side direct current bus,

and the power supply device further comprising an instantaneous voltage drop compensation function whereby an energy of the
smoothing capacitor is supplied by an operation of the step-up chopper to the inverter when there is an instantaneous voltage
drop in the alternating current power supply voltage and an output voltage of the inverter is maintained at a constant value,
wherein

a plurality of MOSFETs with a breakdown voltage lower than a breakdown voltage of the first semiconductor switching device
are connected in series between a connection point of the smoothing capacitor and inductor and a connection point of the diode
and inverter;

wherein
the plurality of MOSFETs are turned on in a condition wherein a potential difference across the plurality of MOSFETs is practically
zero;

the plurality of MOSFETs are driven by a same gate drive circuit; and
a diode is connected between a gate electrode of at least one of the plurality of MOSFETs and the gate drive circuit.

US Pat. No. 9,219,141

SUPER JUNCTION MOSFET, METHOD OF MANUFACTURING THE SAME, AND COMPLEX SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A super junction MOSFET comprising: a plurality of mutually parallel pn junctions extending in a vertical direction on
a first principal surface of a first conductivity type drain layer; a parallel pn layer in which first conductivity type drift
regions and second conductivity type partition regions, each sandwiched between adjacent pn junctions, are disposed alternately
in contact with each other; and an MOS gate structure on the first principal surface side of the parallel pn layer; wherein
a first conductivity type first buffer layer and a second buffer layer are provided, in that order from a second principal
surface side of the parallel pn layer, between the second principal surface of the parallel pn layer and the drain layer;
wherein the impurity concentration of the first buffer layer is a low concentration that is equal to or less than the same
level as that of the impurity concentration of the drift region; wherein the impurity concentration of the second buffer layer
is higher than that of the drift region; and wherein the parallel pn layer is shorter in carrier lifetime than the second
buffer layer.

US Pat. No. 9,136,695

PROTECTION CONTROL SYSTEM FOR A MULTILEVEL POWER CONVERSION CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A protection control system for a multilevel power conversion circuit of a flying capacitor type for converting a DC power
into an AC power or converting an AC power into a DC power, one phase portion of the power conversion circuit comprising:
six semiconductor switches of first through sixth semiconductor switches sequentially connected in series from a positive
terminal to a negative terminal of a DC power supply circuit, each semiconductor switch having an antiparallel-connected diode;

a gate driving circuit with an arm short-circuit protection circuit connected to a gate terminal of each semiconductor switch;
a first capacitor connected between a connection point of the second and third semiconductor switches and a connection point
of the fourth and fifth semiconductor switch;

a second capacitor connected between a connection point of the first and second semiconductor switches and a connection point
of the fifth and sixth semiconductor switches; and

an AC terminal at a connection point of the third and fourth semiconductor switches; wherein the protection control system
turns ON the second semiconductor switch or maintains the second semiconductor switch in an ON state, in a case of short-circuit
fault of the third semiconductor switch.

US Pat. No. 9,087,893

SUPERJUNCTION SEMICONDUCTOR DEVICE WITH REDUCED SWITCHING LOSS

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, characterized by comprising:
an active portion provided on a first main surface side;
a low resistance layer provided on a second main surface side;
a parallel p-n layer, provided between the active portion and low resistance layer, wherein a first conductivity type region
and second conductivity type region are disposed alternately;

a second conductivity type base region, provided on the first main surface side of the second conductivity type region, that
has an impurity concentration higher than that of the second conductivity type region; and

a first conductivity type high concentration region, provided on the first main surface side of the first conductivity type
region, that is positioned farther to the second main surface side than an end portion on the second main surface side of
the second conductivity type base region, and has an impurity concentration higher than an impurity concentration on the second
main surface side of the first conductivity type region

wherein the first conductivity type high concentration region has one-eighth or more and one-fourth or less the thickness
of the first conductivity type region positioned at a depth from the end portion on the second main surface side of the second
conductivity type base region to the end portion on the second main surface side of the second conductivity type region.

US Pat. No. 9,484,343

INSULATED GATE BIPOLAR TRANSISTOR WITH A FREE WHEELING DIODE

FUJI ELECTRIC CO., LTD., ...

1. A reverse-conducting semiconductor device comprising:
an insulated-gate bipolar transistor portion comprising:
a drift layer of a first conductivity type,
a base layer of a second conductivity type selectively formed on the front surface of the drift layer (1),

an emitter region of the first conductivity type selectively formed on the surface of the base layer,
a trench formed from the surface of the base layer into the drift layer,
a gate oxide formed on the inner sidewall of the trench,
a gate electrode formed to face the base layer and the emitter region sandwiched between the gate oxide,
a field stop layer of the first conductivity type formed on the rear side surface of the drift layer,
a collector layer of the second conductivity type formed on the rear side surface of the field stop layer,
a free-wheeling diode portion adjacent to the insulated-gate bipolar transistor portion, wherein the drift layer and the field
stop layer extends from the insulated-gate bipolar transistor portion,

an anode layer of a second conductivity type selectively formed on the front surface of the drift layer, and
a cathode layer of the first conductivity type formed on the rear side surface of the field stop layer,
wherein Rp1, ?Rp1, Rp2, and ?Rp2 are defined as the position of the peak concentration of the cathode layer, the standard deviation of the concentration
of the cathode layer, the position of the peak concentration of the collector layer, and the standard deviation of the concentration
of the collector layer, respectively, and

wherein the following equation 1 is satisfied as:
Rp2+3?Rp2?Rp1+3?Rp1  (1)

US Pat. No. 9,450,110

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a semiconductor substrate of a first conductive type;
an active region that is formed on a first primary surface of the semiconductor substrate and allows a primary electric current
to flow therethrough;

an edge termination structure surrounding the active region;
a first semiconductor region of a second conductive type, the first semiconductor region being formed in the active region;
a plurality of second semiconductor regions of the second conductive type, the second semiconductor regions constituting the
edge termination structure;

a first primary electrode above the first primary surface, electrically connected to the first semiconductor region, having
a lower surface in contact with a semiconductor surface on an upper surface of the semiconductor substrate, and having a contact
edge at a circumferential edge of the lower surface;

a third semiconductor region of the second conductive type, the third semiconductor region being a resistance region separated
from the first primary electrode in a depth direction by an insulating film interposed between the third semiconductor region
and the first primary electrode, and the third semiconductor region being between the first semiconductor region and the second
semiconductor regions; and

two or more diffusion regions of the second conductive type having different resistances and being respectively disposed in
an upper surface of the semiconductor substrate along a direction outward from the first semiconductor region.

US Pat. No. 9,412,732

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

12. A semiconductor device, comprising:
a semiconductor layer of a first conductor type,
a first semiconductor region of a second conductor type connected to a first potential, and disposed on the semiconductor
layer;

a second semiconductor region of the second conductor type connected to one of a second potential and a floating potential,
and disposed on the semiconductor layer;

a third semiconductor region of the first conductor type connected to the second potential, and disposed inside the second
semiconductor region;

a circuit including a gate drive circuit that drives a first transistor of an external circuit in which the first transistor
on a high-potential side and a second transistor on a low-potential side are connected, the circuit that includes the gate
drive circuit being disposed in the first semiconductor region and the third semiconductor region; and

an isolation region electrically isolating the first semiconductor region from the second semiconductor region.

US Pat. No. 9,305,910

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:
a first conductive pattern equipped insulating substrate, having a first conductive pattern on a first insulating substrate;
a first semiconductor element having one surface fixed to the first conductive pattern;
a metal pin equipped printed circuit board, having a conductive layer on a second insulating substrate and a plurality of
metal pins fixed to the conductive layer; and

a third insulating substrate;
wherein a portion of the plurality of meal pins constituting the plurality of metal pins is fixed to other surface of the
first semiconductor element, and

the metal pin equipped printed circuit board is sandwiched between the first conductive pattern equipped insulating substrate
and the third insulating substrate.

US Pat. No. 9,196,566

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a plurality of insulating substrates comprising conductive patterns disposed thereon;
a case accommodating the plurality of insulating substrates such a first side of each of the plurality of insulating substrates
is exposed outside the case;

a cooler disposed facing the first side of each of the plurality of insulating substrates;
a beam portion disposed in the case so as to face a second side of each of the plurality of insulating substrates; and
a fastener disposed at a center of the beam portion, and having a leading end disposed in an attachment hole of the cooler
such that the beam portion is distorted.

US Pat. No. 9,143,054

MULTILEVEL CONVERSION CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A multilevel conversion circuit that generates multi-levels of voltage from a DC power supply provided with three terminals,
composed of two single power supplies, and having three different voltage levels including zero, and selects and delivers
the multi-levels of voltage, the multilevel conversion circuit comprising:
first and second switch groups, each switch group comprising series-connected n semiconductor switches, n being an integer
of three or larger, having an antiparallel-connected diode;

third and fourth switch groups, each switch group comprising series-connected (n?1) semiconductor switches; and
an AC switch composed of a combination of reverse-blocking semiconductor switches; wherein
a series circuit of the first switch group and the second switch group is connected between a first DC terminal that is one
of the three terminals of the DC power supply at the highest potential and a third DC terminal that is one of the three terminals
of the DC power supply at the lowest potential, the first switch group being connected to the first DC terminal;

a series circuit of the third switch group and the fourth switch group is connected between a negative terminal of a first
semiconductor switch composing the first switch group and a positive terminal of an n-th semiconductor switch composing the
second switch group, the third switch group being connected to the negative terminal of the first semiconductor switch of
the first switch group;

the AC switch is connected between a connection point of the third switch group and the fourth switch group and a second DC
terminal that is one of the three terminals of the DC power supply at a middle potential;

a j-th capacitor, j being an integer from 1 to (n?2), is connected between a positive terminal of an (n?m)-th semiconductor
switch composing the first switch group, m being an integer from 0 to (n?3), and a negative terminal of a k-th semiconductor
switch composing the second switch group, k being an integer from 1 to (n?2);

an (n?1)-th capacitor is connected between a positive side terminal of the third switch group and a negative side terminal
of the fourth switch group;

an i-th capacitor, i being an integer from n to (2n?3), is connected between a positive terminal of (n?m?1)-th semiconductor
switch composing the third switch group and a negative terminal of k-th semiconductor switch composing the fourth switch group;

a connection point between the first switch group and the second switch group is an AC terminal; and
a linking means connects a terminal of the j-th capacitor and a terminal of the i-th capacitor.

US Pat. No. 9,093,493

WIDE BANDGAP INSULATED GATE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A wide bandgap insulated gate semiconductor device, comprising:
a semiconductor substrate made of semiconductor having a bandgap wider than silicon;
a first conductivity type drift layer over the semiconductor substrate, said drift layer having a low impurity concentration;
a plurality of second conductivity type channel regions selectively disposed over the drift layer;
first conductivity type semiconductor regions selectively disposed in respective surfaces in said channel regions, said first
conductivity type semiconductor regions having a high impurity concentration;

a plurality of second conductivity type base regions in contact with bottoms of the respective channel regions, said base
regions having a high impurity concentration;

a protruding drift layer portion that is a first conductivity type region interposed between said plurality of channel regions
and said plurality of second conductivity type base regions thereunder;

a gate electrode formed, through a gate insulating film, on the protruding drift layer portion and on respective surfaces
of the channel regions;

a first common electrode in contact with the first conductivity type semiconductor regions in said channel regions; and
a second conductivity type floating region inside the protruding drift layer portion, having side faces respectively facing
side faces of the second conductivity type base regions, the second conductivity type floating region having a high impurity
concentration,

wherein respective gaps between said second conductivity type base regions and said second conductivity type floating region
defined by the respective side faces have a wide portion and a narrow portion.

US Pat. No. 9,460,871

METHOD FOR ASSEMBLING ARC-EXTINGUISHING CHAMBER OF ELECTROMAGNETIC CONTACTOR

FUJI ELECTRIC CO., LTD., ...

1. A method for assembling an arc-extinguishing chamber of an electromagnetic contactor, comprising:
a step of fixing a pair of fixed contacts each including a support conductor and a C-shaped part, to the arc-extinguishing
chamber having a tub-shape with one end being open, the C-shaped part being disposed inside of the arc-extinguishing chamber;

a step of installing an insulation cover covering a part other than a contact point part of each C-shaped part of the pair
of fixed contacts; and

a step of disposing a movable contact to be capable of contacting with and separating from the contact point parts of the
fixed contacts,

wherein the arc-extinguishing chamber comprises:
a flat fixed contact point supporting insulating substrate supporting the pair of fixed contacts;
a metallic angular cylindrical body brazed to the fixed contact point supporting insulating substrate; and
an insulating cylindrical body disposed on an inner circumferential surface of the metallic angular cylindrical body.

US Pat. No. 9,460,927

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device manufacturing method for manufacturing a semiconductor device having a gate and a collector on opposite
sides of the semiconductor device, a p-n junction, and a low-lifetime region that has a carrier lifetime shorter than that
in other regions at the interface of the p-n junction, the method comprising:
providing a first semiconductor region of a first conductivity type;
forming the p-n junction and the low-lifetime region, by a process including
a first implanting of impurities of a second conductivity type into a surface of a rear side of the first semiconductor region
with a first acceleration energy, and

after the first implanting, a second implanting of impurities of the second conductivity type, with a second acceleration
energy differing from the first acceleration energy, into the surface of the rear side of the first semiconductor region;
and

forming the collector on the rear side of the first semiconductor region.

US Pat. No. 9,412,694

POLYSILICON FUSE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE INCLUDING POLYSILICON FUSE

FUJI ELECTRIC CO., LTD., ...

1. A polysilicon fuse comprising:
a lower part electrode;
an interlayer insulating film that is arranged on the lower part electrode;
an opening portion in the interlayer insulating film that reaches the lower part electrode;
a polysilicon portion, which serves as a melting portion, that is arranged inside the opening portion and includes a cavity;
and

an upper part electrode that is arranged on the interlayer insulating film so as to contact with the polysilicon portion.

US Pat. No. 9,399,268

LASER WELDING METHOD, LASER WELDING JIG, AND SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a ceramic insulated substrate;
a front surface conductor pattern fixed on a front surface of the ceramic insulated substrate;
a semiconductor chip electrically connected to the front surface conductor pattern;
a first member electrically connected to the semiconductor chip; and
a second member laser-welded to the first member at at least one portion to electrically connect thereto;
wherein a gap between the first member and the second member at the portion of laser-welding is at most 300 ?m.

US Pat. No. 9,385,615

ISOLATED SWITCHING POWER SUPPLY

FUJI ELECTRIC CO., LTD., ...

1. An isolated switching power supply comprising:
a switching element that is connected to an input power supply through a primary winding of an isolation transformer;
a control circuit that ON/OFF-drives the switching element and generates an AC power in a secondary winding and in an auxiliary
winding of the transformer;

an output circuit that rectifies the AC power generated in the secondary winding of the isolation transformer and outputs
the rectified power;

an internal power supply circuit that generates a driving power supply voltage for the control circuit from the AC power generated
in the auxiliary winding of the transformer;

an output voltage detecting circuit that feeds back an output monitoring voltage derived from the driving power supply voltage
generated by the internal power supply circuit to the control circuit to control the ON/OFF driving of the switching element
by the control circuit; and

an output voltage controller that changes a level of the output monitoring voltage obtained from the driving power supply
voltage corresponding to a change of a condition for the ON/OFF driving of the switching element in the control circuit,

wherein a change of a condition signal is received at the output voltage controller directly from the control circuit.

US Pat. No. 9,331,194

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device having an insulated gate structure, the device comprising:
a first conductivity-type semiconductor substrate constituting a first conductivity-type drift layer;
a second conductivity-type well region that is provided selectively on a surface layer of one of main surfaces of the first
conductivity-type semiconductor substrate;

a first conductivity-type source region that is provided selectively near the main surface inside the second conductivity-type
well region;

a second conductivity-type low-concentration region that is provided selectively near the main surface inside the second conductivity-type
well region and has a net doping concentration lower than a concentration of a second conductivity-type impurity contained
in the second conductivity-type well region, and the second conductivity-type low-concentration region is surrounded by the
second conductivity-type well region; and

a gate insulator that is provided on surfaces of the main surface, and a gate electrode that is provided on surfaces of the
gate insulator, and the gate electrode is provided over the first conductivity-type source region, the second conductivity-type
low-concentration region, the second conductivity-type well region, and the first conductivity-type drift layer.

US Pat. No. 9,318,433

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising a trimming circuit including:
a constant current circuit;
a fuse resistor, one end of which is connected to the constant current circuit;
a trimming pad connected to a connection point connecting the constant current circuit and the one end of the fuse resistor;
a protection resistor of which one end is connected to the connection point;
a protection diode, a cathode of which is connected to the other end of the protection resistor:
a MOS transistor, a gate of which is connected to the other end of the protection resistor; and
a ground to which are connected the other end of the fuse resistor and an anode of the protection diode, wherein
the fuse resistor, protection resistor, and protection diode are formed of a polysilicon layer disposed across a first dielectric
on a semiconductor substrate,

wherein a first layer polysilicon layer in which the fuse resistor is formed is disposed on the first dielectric, a second
layer polysilicon layer in which the protection resistor and protection diode are formed is disposed across a second dielectric
on the first layer polysilicon layer, and a third dielectric is disposed on the second layer polysilicon layer.

US Pat. No. 9,236,814

PARALLEL INVERTER DEVICE AND METHOD FOR CONTROL THEREOF

FUJI ELECTRIC CO., LTD., ...

1. A parallel inverter device, comprising a plurality of inverters connected in parallel that supply an alternating current
voltage to a single load and a transmission means, wherein
each of the plurality of inverters includes
a power converter that converts direct current to alternating current and supplies the alternating current voltage to the
single load, and

a power converter control unit;
one of the inverters is a master inverter, the power converter control unit thereof computing a voltage command value for
the power converter in the master inverter, and another of the inverters is a slave inverter, the power converter of the slave
inverter being driven in accordance with said voltage command value;

the transmission means transmits the voltage command value computed by the power converter control unit of the master inverter
to the slave inverter, delayed by a transmission delay time inherent to the transmission means; and

the power converter control unit included in the master inverter further includes a discrete delay device that delays the
voltage command value by a time duration equal to the transmission delay time, and provides the voltage command value delayed
by the delay device to the power converter included in the master inverter.

US Pat. No. 9,214,878

MULTILEVEL POWER CONVERTER CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A multilevel power converter circuit that converts from direct current to alternating current comprising:
a direct current power supply series circuit including first and second direct current power supplies connected in series,
the direct current power supply series circuit having a positive terminal, a negative terminal and an intermediate potential
point, the intermediate potential point being at a junction of the first and second direct current power supplies;

a first semiconductor switch series circuit connected between the positive terminal and negative terminal of the direct current
power supply series circuit, and a second semiconductor switch series circuit connected between an emitter of a 1st first semiconductor switch of the first semiconductor switch series circuit and a collector of a 2nth first semiconductor switch of the first semiconductor switch series circuit, n being an integer of 3 or higher;

the first semiconductor switch series circuit including 2n first semiconductor switches connected in series with each other,
and first diodes connected in anti-parallel with each of said first semiconductor switches;

n?1 first capacitors, one first capacitor connected between a collector of the nth first semiconductor switch of the first semiconductor switch series circuit and an emitter of the (n+1)th first semiconductor switch of the first semiconductor switch series circuit, and another first capacitor connected between
a collector of the (n?m)th first semiconductor switch of the first semiconductor switch series circuit and an emitter of the (n+m+1)th first semiconductor switch of the first semiconductor switch series circuit, wherein m is an integer of from 1 to n?2;

the second semiconductor switch series circuit including 2n?2 second semiconductor switches connected in series with each
other and second diodes connected in anti-parallel with each of said second semiconductor switches;

n?2 second capacitors, one second capacitor connected between a collector of the (n?1)th second semiconductor switch of the second semiconductor switch series circuit and an emitter of the nth second semiconductor switch of the second semiconductor switch series circuit and, when n is 4 or higher, another second capacitor
connected between a collector of the (n?m)th second semiconductor switch of the second semiconductor switch series circuit and an emitter of the (n+m?1)th second semiconductor switch of the second semiconductor switch series circuit; and

a bidirectional switch connected between an emitter of the nth first semiconductor switch of the first semiconductor switch series circuit and the intermediate potential point of the direct
current power supply series circuit.

US Pat. No. 9,203,217

INVERTER APPARATUS

FUJI ELECTRIC CO., LTD., ...

1. An inverter apparatus comprising:
an inverter stack having casters at a bottom; and
a switchboard for entering the inverter stack from a front side to store,
wherein the switchboard has an output relay terminal, at a storage bottom portion to store the inverter stack, extending along
an entering direction of the inverter stack, and

the output relay terminal is attached with an output electric wire connected to a load at a rear end portion, is connected
to an output terminal of the inverter stack at a front end portion, and is fastened to an output relay bar protruding downward
from the bottom of the inverter stack through a fastening member.

US Pat. No. 9,147,579

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device that has a cavity with a shape of a flat plate inside a semiconductor
substrate, the method comprising:
a trench forming step of forming two or more trenches in a surface region of a semiconductor substrate with a predetermined
distance between the adjacent trenches, each trench having a sectional shape which outwardly expands at least at one part
in the trench, such that at least one region in the depth direction of the trench is wider than regions above and below it
in the depth direction; and

an annealing step for closing openings of the trenches and expanding the outwardly expanding part of the trench to join all
the trenches to form a single cavity inside the semiconductor substrate,

wherein a trench interval x3 is smaller than a trench opening width x1.

US Pat. No. 9,136,770

ADAPTER POWER SUPPLY HAVING THERMOELECTRIC CONVERSION ELEMENT

FUJI ELECTRIC CO., LTD., ...

1. An adapter power supply comprising:
a switching element that performs switching of an input voltage obtained by rectifying an input AC voltage to deliver switched
voltage to a primary winding of an isolating transformer;

a diode that rectifies a voltage obtained across a secondary winding of the isolating transformer to obtain a DC output voltage;
and

a thermoelectric conversion element that performs thermoelectric conversion to variably set the DC output voltage corresponding
to a temperature difference between a heated temperature of the switching element or the diode and an atmospheric temperature.

US Pat. No. 9,136,326

SEMICONDUCTOR DEVICE WITH INCREASED ESD RESISTANCE AND MANUFACTURING METHOD THEREOF

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:
a second conductivity type well layer disposed on or in a surface layer of a first conductivity type semiconductor substrate;
a first conductivity type second well layer selectively disposed in a surface layer of the second conductivity type well layer;
a second conductivity type first offset layer and second conductivity type second offset layer spaced apart in a surface layer
of the first conductivity type second well layer;

a second conductivity type high concentration layer, with an impurity concentration higher than that of the second offset
layer, disposed in a surface layer of the second offset layer; and

a LOCOS oxide film disposed so as to enclose the high concentration layer, wherein
the diffusion depth of the second well layer below the high concentration layer is less than the diffusion depth of the second
well layer below the LOCOS oxide film.

US Pat. No. 9,129,939

SIC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

FUJI ELECTRIC CO., LTD., ...

1. A method for manufacturing an SiC semiconductor device in which an electrode structure is formed in an SiC semiconductor,
the method comprising:
producing a nickel silicide layer containing titanium carbide by heating after a layer containing nickel and titanium is formed
on the SiC semiconductor;

removing a carbon layer produced in a surface of the nickel silicide layer by reverse sputtering; and
forming a metal layer by laminating a titanium layer, a nickel layer and a gold layer sequentially on the nickel silicide
layer containing titanium carbide.

US Pat. No. 9,117,681

SILICON CARBIDE SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING THE SAME, AND SILICON CARBIDE DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A silicon carbide semiconductor element comprising:
an n-type silicon carbide substrate or a silicon carbide substrate having an n-type silicon carbide region in a surface region
thereof;

a nickel silicide film formed directly on a surface of the n-type silicon carbide substrate or directly on a surface of the
n-type silicon carbide region of a silicon carbide substrate;

a nickel aluminum film having a thickness in a range of 5 nm to 20 nm formed on the nickel silicide film and having a composition
of 50% nickel and 50% aluminum in order to enhance adhesiveness between the nickel silicide film and the aluminum film and
to prevent the resistance of the nickel aluminum film from rising; and

an aluminum film having a thickness in a range of 2 ?m to 4 ?m formed on a surface of the nickel aluminum film
the nickel silicide film being formed by heat treatment of a nickel film on the n-type silicon carbide substrate or the silicon
carbide substrate having an n-type silicon carbide region, the nickel silicide film having a thickness in a range of 0.05
?m to 4 ?m.

US Pat. No. 9,390,843

INPUT CIRCUIT INCLUDES A CONSTANT CURRENT CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. An input circuit comprising:
an input voltage detecting circuit that is connected to an input terminal, detects and input voltage, and delivers a detected
voltage; and

a constant current circuit that is connected to the input terminal and generates electric current flow corresponding to the
detected voltage, wherein the generated electric current flow is proportional to the input voltage over a predetermined temperature
range,

wherein the input voltage detecting circuit is a dividing resistor, and
wherein the constant current circuit comprises:
a MOSFET,
a current detecting resistor connected between a source of the MOSFET and a base potential,
an operational amplifier, a non-inverting input terminal of the operational amplifier being connected to a divided output
of the dividing resistor, an inverting input terminal of the operational amplifier being connected to a source of the MOSFET,
and an output terminal of the operational amplifier being connected to a gate of the MOSFET; and

a drain of the MOSFET is connected to the input terminal.

US Pat. No. 9,368,419

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a frame body having an opening region;
an insulating substrate disposed in the opening region of the frame body and including a semiconductor chip;
a lead portion including an inclined portion that is at least partially exposed to the opening region of the frame body and
that extends so as to be inclined with respect to an end surface forming the opening region, and a terminal portion that extends
outside of the frame body; and

an ultrasonic-bonded wire connecting the lead portion and the semiconductor chip, the inclined portion of the lead portion
being a pad for the ultrasonic-bonded wire, and the inclined portion of the lead portion having a width that exceeds a width
of the terminal portion of the lead portion.

US Pat. No. 9,362,393

VERTICAL SEMICONDUCTOR DEVICE INCLUDING ELEMENT ACTIVE PORTION AND VOLTAGE WITHSTANDING STRUCTURE PORTION, AND METHOD OF MANUFACTURING THE VERTICAL SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

25. A vertical semiconductor device comprising an element active portion and a voltage withstanding structure portion,
the element active portion including:
a first conductivity type first semiconductor layer;
a drift layer disposed on a first main surface of the first semiconductor layer;
a second conductivity type well region disposed in a surface layer of the drift layer;
a first conductivity type source region disposed in a surface layer of the well region;
a second conductivity type contact region disposed in a surface layer of the well region;
a trench disposed in a surface layer of the well region;
a gate electrode disposed across a gate insulating film in the trench;
an interlayer dielectric disposed on the upper surface of the gate electrode;
a first main electrode electrically connected to the source region and contact region on the upper surface of the interlayer
dielectric; and

a gate pad electrode, to which the gate electrode is electrically connected, disposed separated from the first main electrode
on the upper surface of the interlayer dielectric, wherein

the drift layer below the first main electrode includes first parallel pn layers wherein a first first conductivity type semiconductor
region and first second conductivity type semiconductor region are repeatedly alternately disposed in a direction parallel
to the first main surface and the first second conductivity type semiconductor region is in contact with the well region,

the drift layer below the gate pad electrode includes second parallel pn layers wherein a second first conductivity type semiconductor
region and second second conductivity type semiconductor region are repeatedly alternately disposed in a direction parallel
to the first main surface and the second second conductivity type semiconductor region is disposed so as to oppose the well
region,

the planar form of the gate electrode is a stripe form,
the source region immediately below a first position between an end portion of the first main electrode disposed in a direction
parallel to the longitudinal direction of the stripe form gate electrode and an end portion of the gate pad electrode, and
immediately below the first main electrode and the gate pad electrode adjacent to the first position, is separated from the
gate electrode by a space,

a gate runner connecting the gate electrode and gate pad electrode is disposed on the first main surface of the first main
electrode, the source region disposed immediately below a second position between an end portion of the first main electrode
disposed in a direction perpendicular to the longitudinal direction of the stripe form gate electrode and an end portion of
the gate runner, and immediately below the first main electrode and the gate runner adjacent to the second position, is separated
from the gate electrode by a space,

a first conductivity type isolation region is included between the second parallel pn layers and the well region, and
the trench reaches the first first conductivity type semiconductor region and the first conductivity type isolation region.

US Pat. No. 9,234,507

STEAM CHARACTERISTICS AUTOMATIC MEASURING DEVICE AND GEOTHERMAL POWER-GENERATING DEVICE

Fuji Electric Co., Ltd., ...

1. A steam characteristics automatic measuring device comprising:
a silica monitor for measuring a concentration of silica included in a condensate obtained by cooling steam taken out from
under the ground, wherein the steam is divided into non-condensable gas and the condensate by the cooling;

an electrical conductivity meter for automatically measuring an electrical conductivity of the condensate;
an automatic non-condensable gas flowmeter for automatically and continuously measuring a flow rate of the non-condensable
gas comprising a thermometer for measuring a temperature of the condensate;

a level detector for detecting a liquid level of the condensate and for outputting a lowest level-detecting signal when the
liquid level falls to a lowest level and outputting a highest level-detecting signal when the liquid level rises to a highest
level;

a processor for calculating a flow rate of saturated dissolved gas in the condensate based on the temperature, wherein the
processor calculates a total flow rate of the non-condensable gas and the dissolved gas by adding the flow rate of non-condensable
gas to the flow rate of saturated dissolved gas; and

a data processing transmitter for automatically transmitting data measured by each of the silica monitor, the electrical conductivity
meter and data corresponding to the total flow rate calculated by the processor.

US Pat. No. 9,209,296

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a main drain region which is a first conduction type and is formed on a first main surface of a semiconductor substrate of
the first conduction type;

a vertical trench MOS gate-type semiconductor element portion including a base region that is a second conduction type and
is selectively formed on a second main surface of the semiconductor substrate, a main source region that is the first conduction
type and is selectively formed on a surface of the base region, a trench that extends from a surface of the base region to
the semiconductor substrate through the base region and the main source region, and a trench MOS gate that includes a gate
electrode provided in the trench with a first insulating film, which is an insulating film, interposed therebetween;

a semiconductor element portion for control that is adjacent to the vertical trench MOS gate-type semiconductor element portion,
with an element isolation region including a second insulating film which is formed on the second main surface of the semiconductor
substrate and is thicker than the first insulating film interposed therebetween, includes a well diffusion region which is
the second conduction type and forms a pn junction with the semiconductor substrate on the second main surface of the semiconductor
substrate, a gate electrode for control which is formed on a surface of the well diffusion region with a third insulating
film which is thinner than the second insulating film interposed therebetween, and a control drain region of the first conduction
type and a control source region of the first conduction type which are provided on the surface of the well diffusion region
with the control gate electrode interposed between, and controls the vertical trench MOS gate-type semiconductor element portion;
and

a junction edge termination region that includes the second insulating film provided on the second main surface of the semiconductor
substrate and surrounds the vertical trench MOS gate-type semiconductor element portion or both the vertical trench MOS gate-type
semiconductor element portion and the semiconductor element portion for control,

wherein the junction edge termination region includes the second insulating film, a sustain region which is the second conduction
type and comes into contact with the trench at an outer circumferential end of the vertical trench MOS gate-type semiconductor
element portion, and a first region which is the second conduction type and is provided so as to come into contact with an
outside of the sustain region,

the first region has a junction depth greater than that of the base region and has low impurity concentration,
the sustain region has a junction depth less than that of the first region and has high impurity concentration,
the well diffusion region has a junction depth greater than those of the base region and the sustain region and has low impurity
concentration, and

an avalanche breakdown voltage of the junction edge termination region and the well diffusion region is higher than that of
the vertical trench MOS gate-type semiconductor element portion.

US Pat. No. 9,196,282

MAGNETIC RECORDING MEDIUM

FUJI ELECTRIC CO., LTD., ...

1. A magnetic recording medium comprising:
a substrate,
a magnetic layer on the substrate, and
a carbon-based protective layer on the magnetic layer,
wherein a thickness of the carbon-based protective layer is 2 nm or less, and a contact angle of water on a surface of the
carbon-based protective layer is 25.5° or greater and less than 60°, and the carbon-based protective layer is formed by a
plasma CVD method.

US Pat. No. 9,146,460

IMPRINTING METHOD AND APPARATUS THEREFOR

FUJI ELECTRIC CO., LTD., ...

1. An imprinting apparatus for carrying out an imprinting method for forming a predetermined pattern in a resist surface of
a substrate coated with a thermal imprint resist by using a mold having a pattern of projections and recesses formed in a
transfer surface, the imprinting apparatus comprising:
a plurality of units which perform one or more steps in the imprinting method and which are selected from independent units
in each of which one step is executed, composite units each of which a plurality of steps are executed, and combinations of
independent units and composite units; and

conveying devices which convey the mold and the substrate paired with each other between the plurality of units;
wherein the plurality of units include a loader unit, an alignment unit, a heating unit, a press unit, a cooling unit, a release
unit, and an unloader unit;

wherein the heating unit is divided into dual- or multi-stage sub-units which are different in maximum achievable temperature;
wherein, in a first heating sub-unit, a first heating is performed by contacting a thermal block to the mold and blowing hot
air to the substrate;

wherein, in a second heating sub-unit, a second heating is performed by hot air; and
wherein, the mold and substrate are heated together and the entire substrate is heated during the first heating and the second
heating.

US Pat. No. 9,136,775

CONTROL METHOD FOR MULTILEVEL POWER CONVERSION CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A control method for controlling a multilevel power conversion circuit for converting DC power to AC power or AC power
to DC power, one phase portion of the power conversion circuit including:
a first semiconductor switch series circuit that is connected between a positive terminal and a negative terminal of a DC
power supply system having the positive terminal, the negative terminal, and a middle terminal, and composed of at least series-connected
six semiconductor switches each having an anti-parallel-connected diode;

a first capacitor that is connected in parallel to a series circuit of two semiconductor switches connected to a middle point
of the first semiconductor switch series circuit;

a second capacitor that is connected in parallel to a series circuit of four semiconductor switches, two of which are in a
one side of a middle point of the first semiconductor switch series circuit and two of which are in the other side of the
middle point of the first semiconductor switch series circuit;

a second semiconductor switch series circuit that is connected in parallel to the second capacitor and composed of at least
series-connected four semiconductor switches each having an anti-parallel connected diode;

a third capacitor that is connected in parallel to a series circuit of two semiconductor switches each connected to a middle
point of the second semiconductor switch series circuit; and

a bidirectional switch that is connected between the middle point of the second semiconductor switch series circuit and the
middle terminal of the DC power supply system and is capable of bidirectional switching, the method comprising:

delivering a predetermined switching pattern of semiconductor switches when a potential at the middle point of the first semiconductor
switch series circuit, the middle point being an AC terminal, changes from a positive side potential through a middle point
potential to a negative side potential of the DC power supply system, or from the negative side potential through the middle
point potential to the positive side potential,

wherein a period of time for delivering the predetermined switching pattern is shorter than one carrier period of pulse width
modulation control.

US Pat. No. 9,130,480

DEVICE FOR APPLYING HIGH VOLTAGE USING PULSE VOLTAGE, AND METHOD OF APPLYING HIGH VOLTAGE

Sawafuji Electric Co., Lt...

1. A device for applying a high voltage using a pulse voltage that applies a high voltage having a steep leading edge to a
capacitive load, comprising:
a pulse transformer;
a switching circuit that supplies a pulse wave having a steep leading edge to the capacitive load via the pulse transformer,
the switching circuit having a plurality of switching elements that are turned ON/OFF by gate control;
an oscillator circuit configured to generate a signal having a predetermined duty ratio of ?%, a duty ratio of 0%, and at
least an intermediate duty ratio of ?(?>?>0) % that is between said duty ratio of ?% and a duty ratio of 0%; and

a short pulse generation circuit that generates a short pulse corresponding to an ON voltage only during a predetermined period
corresponding to a leading edge of a rectangular pulse output from said oscillator circuit, wherein

the switching elements are gate controlled based on said short pulse,
an output from the switching circuit applies a voltage to the capacitive load via the pulse transformer, and
a secondary side leakage inductance L1 of the pulse transformer has a value such that half a cycle of oscillating voltage generated by the secondary side leakage
inductance of the pulse transformer and the capacitance of a capacitive corresponds to a pulse width ?0 of an ON period when at least one of the switching elements is turned ON/OFF; wherein

the value of the secondary side leakage inductance L1 of the pulse transformer and a value of the pulse width ?0 of the pulse wave are given so as to satisfy the following equation

L1=(?0/?)2×(1/C1)
wherein C1: capacitance of the capacitive load.

US Pat. No. 9,115,722

FEED WATER PUMP CONTROL DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A water feed pump control device that carries out an estimated constant end pressure control by controlling the operating
speed of a feed water pump installed in a feed water pipe with an inverter device, the feed water pump control device comprising:
a first storage device that stores linearized characteristics showing the relationship between the output frequency of the
inverter device and a discharge side pressure;

a pressure sensor that detects the discharge side pressure of the feed water pump;
a power consumption calculation device that calculates the power consumption of the inverter device;
a second storage device that stores F-P characteristics showing the relationship between the output frequency of the inverter
device and the power consumption;

a determination device that determines the presence or absence of a boost pressure of the feed water pump based on the inverter
device output frequency, power consumption, and F-P characteristics; and

a correction device that corrects the linearized characteristics when it is determined by the determination device that there
is boost pressure.

US Pat. No. 9,117,797

HIGH-VOLTAGE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A high-voltage semiconductor device comprising:
a second conductivity type well region which is formed on a first conductivity type semiconductor substrate and includes a
logic circuit formation region and a withstand voltage region surrounding the logic circuit formation region;

a first conductivity type well region which is formed on the semiconductor substrate so as to surround the withstand voltage
region;

a transistor which includes a second conductivity type drain region selectively formed in a surface layer of the second conductivity
type well region between the withstand voltage region and the logic circuit formation region and having a higher concentration
of impurities than the withstand voltage region, and a second conductivity type source region selectively formed in the surface
layer of the second conductivity type well region, and which uses the withstand voltage region between the drain region and
the source region as a drift region and uses the first conductivity type well region as a base region;

an opening region which is provided locally in the second conductivity type well region between the drain region and the logic
circuit formation region so as to prevent the second conductivity type well region from lying all over the opening region
in a depth direction; and

a conductive path which electrically connects the drain region with a logic circuit in the logic circuit formation region;
the high-voltage semiconductor device further comprising:

a shield layer which is formed on a first insulating layer formed on a surface of the opening region and which is connected
to a negative electrode side of a power supply connected to the logic circuit in the logic circuit formation region.

US Pat. No. 9,093,099

PERPENDICULAR MAGNETIC RECORDING MEDIUM AND METHOD FOR MANUFACTURING THE SAME

FUJI ELECTRIC CO., LTD., ...

1. A perpendicular magnetic recording medium comprising:
a nonmagnetic seed layer, a nonmagnetic underlayer, and a magnetic layer formed in this order on a nonmagnetic substrate,
wherein the nonmagnetic seed layer includes a MgO layer in direct contact with a metal layer thereon having a body-centered
cubic (bcc) structure,

the nonmagnetic underlayer has a NaCl type structure of one selected from the group consisting of MgO, NiO, TiO, CrN, Ti carbides,
and Ti nitrides, the nonmagnetic underlayer being disposed directly on the nonmagnetic seed layer, and

the magnetic layer includes an alloy selected from the group consisting of FePt, FePd, and CoPt having an L10 type ordered structure.

US Pat. No. 9,064,818

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:
an insulating circuit substrate mounted with at least one semiconductor element;
a resin case having a bottom surface portion attached with the insulating circuit substrate and a side surface portion enclosing
a periphery of the bottom surface portion;

a plurality of leads molded integrally with the resin case and provided parallel around a periphery of the insulating circuit
substrate, the plurality of leads being positioned in the bottom surface portion inside the resin case so that an upper surface
of the lead and a surface of the bottom surface portion are coplanar, and penetrating the side surface portion of the resin
case to extend from inside the resin case to outside the resin case; and

a sealing resin filled inside the resin case,
wherein the resin case includes depressed portions formed in the bottom surface portion on each of two sides of each of the
plurality of leads along a border between the bottom surface portion and the side surface portion to fill with the sealing
resin.

US Pat. No. 9,048,051

ELECTROMAGNETIC CONTACTOR

FUJI ELECTRIC CO., LTD., ...

1. An electromagnetic contactor, comprising:
a pair of fixed contacts disposed with a predetermined interval maintained therebetween;
a movable contact disposed to contact to and separate from the pair of fixed contacts;
an electromagnet unit to drive the movable contact; and
a drive circuit driving the electromagnet unit,
wherein the electromagnet unit includes at least:
a magnetic yoke having a bottom plate portion,
an upper portion magnetic yoke disposed over the magnetic yoke opposite to the bottom plate portion, and having a through
hole,

a cylindrical auxiliary yoke protruding from the bottom plate portion toward the upper portion magnetic yoke,
a movable plunger connected to the movable contact and having a peripheral flange portion disposed above the upper portion
magnetic yoke, and an end portion disposed inside the cylindrical auxiliary yoke,

a return spring disposed on the bottom plate portion to urge the end portion of the movable plunger toward the upper portion
magnetic yoke,

a coil disposed between the upper portion magnetic yoke and the bottom plate portion of the magnetic yoke to move the movable
plunger, and

a ring-form permanent magnet disposed on the upper portion magnetic yoke to enclose the peripheral flange portion of the movable
plunger and magnetized in a moving direction of the movable plunger,

the drive circuit includes:
a power source to supply power to the coil;
a pulse drive circuit to output and supply to the coil an engage pulse causing the movable plunger to perform an attracting
operation and a hold pulse maintaining the attracting operation when the movable plunger is subject to the attracting operation
by the engage pulse, and

a flywheel circuit having a semiconductor switching element connected in parallel to the coil, and
the movable plunger is arranged to have a first gap between a lower surface of the peripheral flange portion of the movable
plunger and an upper surface of the upper portion magnetic yoke, and a second gap between an outer peripheral surface of the
movable plunger and a side surface of the upper portion magnetic yoke in the through hole, the first gap being less than the
second gap so that a magnetic flux density between the first gap is greater than the second gap to form a magnetic circuit
in which a magnetic field passes through the peripheral flange of the movable plunger, the upper portion magnetic yoke, the
magnetic yoke, the cylindrical auxiliary yoke, and the end portion of the movable plunger.

US Pat. No. 9,413,255

SWITCHING POWER SUPPLY DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A switching power supply device, comprising:
an isolation transformer having a primary winding, an auxiliary winding, a tertiary winding and a plurality of secondary windings,
the primary winding being connected to a direct current voltage source via a capacitor, leakage inductance of the isolation
transformer and the capacitor forming a series resonant circuit;

a first switching element connected in series to the primary winding of the isolation transformer, the first switching element
being configured to be driven by a drive control circuit that performs a separately excited oscillation operation, to thereby
apply a direct current input voltage from the direct current voltage source to the series resonant circuit;

a second switching element connected in parallel to the series resonant circuit, the second switching element being configured
to be driven by a voltage generated in the auxiliary winding of the isolation transformer upon turning-off of the first switching
element, to thereby form a current path of the series resonant circuit;

an output circuit configured to rectify, smooth, and output power generated on the secondary windings of the isolation transformer;
and

the drive control circuit, including
an output control circuit configured to generate an output control signal with a pulse width corresponding to an output voltage
of the output circuit;

a winding detection circuit configured to compare a voltage generated in the tertiary winding of the isolation transformer
with a winding threshold voltage, and to output a winding detection signal;

a drive circuit configured to generate, in accordance with the winding detection signal and the output control signal, a pulse-width
controlled drive signal for driving the first switching element; and

a threshold setting circuit configured to change the winding threshold voltage in the winding detection circuit in accordance
with the direct current input voltage applied to the series resonant circuit, to thereby adjust the timing of turning on the
first switching element.

US Pat. No. 9,406,576

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a frame body having an opening region;
an insulating substrate disposed in the opening region of the frame body and including a semiconductor chip;
a lead portion including an inclined portion that is at least partially exposed to the opening region of the frame body and
that extends so as to be inclined with respect to an end surface forming the opening region, and a terminal portion that extends
outside of the frame body; and

an ultrasonic-bonded wire connecting the lead portion and the semiconductor chip, the inclined portion of the lead portion
being a pad for the ultrasonic-bonded wire, and the inclined portion of the lead portion having a width that exceeds a width
of the terminal portion of the lead portion.

US Pat. No. 9,385,125

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor integrated circuit device, comprising:
a second conductivity type region, provided in a surface layer of a first conductivity type semiconductor substrate, in which
a circuit portion is formed and to which is applied a first potential, which is a high voltage potential of a power supply
of the circuit portion;

a first conductivity type well region, provided in the interior of the second conductivity type region and configuring the
circuit portion, to which is applied a second potential, which is a low voltage potential of the power supply;

a first conductivity type low potential region, provided in a surface layer of the first conductivity type semiconductor substrate
on the outer side of the second conductivity type region, to which is applied a third potential lower than the second potential;

a cavity selectively provided between the circuit portion and first conductivity type low potential region and between the
first conductivity type semiconductor substrate and second conductivity type region; and

a first conductivity type region penetrating the second conductivity type region and reaching the cavity.

US Pat. No. 9,356,580

INSULATED GATE SEMICONDUCTOR ELEMENT DRIVE DEVICE

FUJI ELECTRIC CO., LTD., ...

1. An insulated gate semiconductor element drive device, including a plurality of drive circuits which drive a plurality of
respective insulated gate semiconductor elements connected in parallel, which drives each of the drive circuits in accordance
with a control signal and drives the plurality of insulated gate semiconductor elements in parallel, each of the drives circuits
comprising:
a constant current circuit which supplies a constant current to the gate of the insulated gate semiconductor element and on-operates
the insulated gate semiconductor element;

a discharge circuit which grounds the gate of the insulated gate semiconductor element and off-operates the insulated gate
semiconductor element;

a switch circuit which operates one of the constant current circuit or discharge circuit in accordance with a control signal
and turns on or off the insulated gate semiconductor element;

a current detection circuit which detects a current flowing through the insulated gate semiconductor element when the insulated
gate semiconductor element is turned on; and

a current regulation circuit which feeds the current detected by the current detection circuit back to the constant current
circuit and controls an output current of the constant current circuit.

US Pat. No. 9,312,845

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device that performs, from among a high-potential-side switching element and a low-potential-side switching
element, which are connected in series and which are interposed between a high-potential main power supply potential and a
low-potential main power supply potential, drive control of the high-potential-side switching element, the semiconductor device
comprising:
only one level shift circuit that receives a single line input signal of a low-side region operating in a low-voltage potential
system, and outputs a single line output as a signal of a high-side region operating in a high-voltage potential system, upon
raising a signal level;

a pulse modulation circuit that operates in a low-side region, generates a data symbol constituted by 2 or more bits and representing
a set signal or a reset signal, and outputs the generated data symbol as the single line input signal of the level shift circuit;

a pulse demodulation circuit that operates in a high-side region, demodulates the data symbol outputted from the level shift
circuit, and generates a level-shifted set signal or reset signal; and

a control circuit that controls conduction/non-conduction of the high-potential-side switching element on the basis of the
level-shifted set signal or reset signal outputted from the pulse demodulation circuit.

US Pat. No. 9,287,767

DC VOLTAGE CONVERSION CIRCUIT HAVING OUTPUT VOLTAGE WITH A PREDETERMINED MAGNITUDE

FUJI ELECTRIC CO., LTD., ...

1. A DC voltage conversion circuit comprising:
a first DC power supply;
a first semiconductor switching device which is connected to two ends of the first DC power supply through an inductor;
a series circuit which is connected in parallel with the switching device and which includes a rectifier device, a parasitic
inductor and a load, so that an input voltage supplied from the DC power supply can be converted into an output voltage with
a predetermined magnitude by a switching operation of the switching device and supplied to the load;

a series circuit which is connected to two ends of the rectifier device and which includes a first snubber capacitor and a
first snubber diode; and
a charging circuit which charges the first snubber capacitor to a voltage lower than the input voltage or the output voltage
in a period of time when the switching device is ON,
wherein the charging circuit includes a series circuit of a second DC power supply and a diode,
wherein a current does not flow into the first snubber diode and the first snubber capacitor until a sum of a voltage of the
first semiconductor switching device and a voltage of the first snubber capacitor exceeds a voltage across the load; and

when a sum of the voltage of the first semiconductor switching device and the voltage of the first snubber capacitor exceeds
the voltage across the load, a surge voltage occurs in the parasitic inductor.

US Pat. No. 9,236,248

FABRICATION METHOD OF SILICON CARBIDE SEMICONDUCTOR ELEMENT

FUJI ELECTRIC CO., LTD., ...

1. A fabrication method of a silicon carbide semiconductor element, the fabrication method comprising:
defining a plane of a silicon carbide substrate having a <0001> c-axis tilted by ? from a normal line direction of a principal
plane of the silicon carbide substrate in a <11-20> direction as the principal plane and removing a principal surface layer
of the silicon carbide substrate such that a periphery of a region in which an alignment mark is provided is surrounded so
as to leave a convex-shaped alignment mark; and

growing an epitaxial layer on the principal surface layer of the silicon carbide substrate to cover the alignment mark, wherein
a width X of the alignment mark parallel to the principal surface of the silicon carbide substrate satisfies Y?X·tan ? in
terms of a relationship with a film thickness Y of the epitaxial layer.

US Pat. No. 9,200,974

SEMICONDUCTOR PRESSURE SENSOR DEVICE AND METHOD OF MANUFACTURING THE SAME

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor pressure sensor device disposed in an exhaust system of an internal combustion engine, comprising:
a diaphragm, disposed on a semiconductor substrate, which is strained in accordance with a pressure;
strain gauges connected to and disposed on the diaphragm;
a metal wiring layer connected to the strain gauges and disposed on the semiconductor substrate via an interlayer insulating
film;

a passivation film having an opening portion from which the metal wiring layer is exposed;
an adhesion securing and diffusion preventing layer, disposed on the passivation film, which coats the exposed top, and the
edge portion, of the metal wiring layer; and

a conductive layer configuring a pad electrode stacked on the adhesion securing and diffusion preventing layer, wherein
the edge face of a stacked metal layer configured of the adhesion securing and diffusion preventing layer and conductive layer
is of a normal tapered shape or stepped shape which expands toward the semiconductor substrate side.

US Pat. No. 9,129,892

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device having a first region in which a vertical semiconductor element is disposed
and a second region in which a lateral semiconductor element electrically isolated from the vertical semiconductor element
by an isolating structure is disposed, the semiconductor device manufacturing method comprising:
a first step of forming by epitaxial growth on a first semiconductor layer a first conductivity type first epitaxial layer
with an impurity concentration lower than that of the first semiconductor layer;

a second step of carrying out a first ion implantation of a first conductivity type impurity throughout the whole of a first
region of the first epitaxial layer;

a third step of selectively carrying out a second ion implantation of a second conductivity type impurity into the first region
of the first epitaxial layer into which the first ion implantation has been carried out;

a fourth step, after the third step, of forming by epitaxial growth on the first epitaxial layer a first conductivity type
second epitaxial layer having an impurity concentration the same as that of the first epitaxial layer;

a fifth step of carrying out a third ion implantation of a first conductivity type impurity into a region of the second epitaxial
layer directly above a place of the first ion implantation and into a second region distanced from the region directly above
the place of the first ion implantation;

a sixth step, after the fifth step, of selectively carrying out a fourth ion implantation of a second conductivity type impurity
into a region of the second epitaxial layer directly above a place of the second ion implantation;

a seventh step, after the sixth step, of forming by epitaxial growth on the second epitaxial layer a first conductivity type
third epitaxial layer having an impurity concentration the same as that of the second epitaxial layer; and

an eighth step of diffusing by heat treatment the first conductivity type impurity and second conductivity type impurity ion
implanted into the first epitaxial layer and second epitaxial layer, thereby forming a parallel pn-layer formed by the first
conductivity type third semiconductor layer and second conductivity type fourth semiconductor layer connected from the first
epitaxial layer to the third epitaxial layer being alternately disposed, and forming a fifth semiconductor layer connected
across the second region of the second epitaxial layer and third epitaxial layer, thereby configuring an isolating structure.

US Pat. No. 9,124,187

CONTROL DEVICE FOR SWITCHING POWER SOURCE

FUJI ELECTRIC CO., LTD., ...

1. A control device for a switching power source, comprising:
an error amplifier that amplifies a differential between a voltage outputted from a switching power source and a reference
voltage;

an analog/digital converter that converts the differential amplified by the error amplifier to a digital signal;
an analog/digital output stabilization circuit that outputs an updated digital signal equal to a current digital signal outputted
from the analog/digital converter if the digital signal from the analog/digital converter changes more than a prescribed threshold;

a digital dither circuit that splits a K bit digital signal outputted from the analog/digital output stabilization circuit
to an upper digit N bit digital signal and a lower digit M bit digital signal, generates a 1 bit digital signal representing
a dither sum on the basis of the lower digit M bit digital signal and switching frequency data, adds the upper digit N bit
digital signal to the 1 bit digital signal, and outputs a digital signal obtained by said adding; and

a digital pulse width modulation circuit that generates a control pulse signal for driving the switching power source on the
basis of the digital signal outputted from the digital dither circuit.

US Pat. No. 9,106,074

MULTILEVEL POWER CONVERTER

FUJI ELECTRIC CO., LTD., ...

1. A multilevel power converter, for converting DC power to AC power or AC power to DC power, comprising:
a DC power supply assembly having a positive terminal, a negative terminal, and a middle point terminal at a middle electric
potential between the positive terminal and the negative terminal; and

a circuit for one phase including:
a series-connected semiconductor switch circuit of at least four semiconductor switches each having an antiparallel-connected
diode, the series-connected semiconductor switch circuit being connected between the positive terminal and the negative terminal
of the DC power supply assembly,

a bidirectional switch capable of bidirectional switching connected between the middle point terminal of the power supply
assembly and an intermediate connection point of the series-connected semiconductor switch circuit, and

a circuit including a one or more semiconductor switches connected between each of two output terminals outputting a potential
of each connection point of the semiconductor switches in the series-connected semiconductor switch circuit and a terminal
of the bidirectional switch, the terminal being at a side unconnected to the DC power supply assembly, and

a capacitor connected between the two output terminals;
wherein the multilevel power converter responds to a request for a total phase interruption for forced shut down in a procedure
of interrupting the semiconductor switches according to a predetermined sequential operation and finally interrupting the
bidirectional switch.

US Pat. No. 9,099,383

SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE

FURUKAWA ELECTRIC CO., LT...

1. A semiconductor substrate, comprising:
a silicon substrate; and
a nitride semiconductor layer that is epitaxially grown on a Si (150) surface of the silicon substrate.

US Pat. No. 9,076,782

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

FUJI ELECTRIC CO., LTD., ...

10. A method of manufacturing a semiconductor device in which a plurality of semiconductor chips mounted on an insulating
substrate formed with a conductive pattern is electrically connected to each other or to the conductive pattern by a lead
frame, the method comprising:
a first joining step for joining the semiconductor chips to the conductive pattern on the insulating substrate by joining
materials;

a wire bonding step for bonding positioning wires having a predetermined diameter and a predetermined length to positions
on main surfaces of the semiconductor chips or a main surface of the conductive pattern to which the lead frame is joined;

a positioning step for preparing the lead frame having opening portions each having a size capable of inserting the positioning
wires therethrough, and then positioning the lead frame with the positioning wires when connecting the plurality of semiconductor
chips to each other or to the conductive pattern on the insulating substrate; and

a second joining step for joining joints of the lead frame to the semiconductor chips or the conductive pattern at predetermined
positions therein through solder layers.

US Pat. No. 9,059,009

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:
an insulating substrate with conductive patterns, having at least a first conductive pattern, a second conductive pattern,
and a third conductive pattern, on a first insulating substrate;

a positive-electrode external lead terminal fixed to the first conductive pattern;
a negative-electrode external lead terminal fixed to the second conductive pattern;
an external lead terminal of intermediate potential fixed to the third conductive pattern;
a first semiconductor element having one surface fixed to the first conductive pattern;
a second semiconductor element having one surface fixed to the third conductive pattern; and
an insulating substrate with conductive pins, having conductive layers on front and rear surfaces of a second insulating substrate
respectively, a plurality of first conductive pins fixed to the conductive layer on the rear surface of the second insulating
substrate, and a plurality of second conductive pins fixed to the conductive layer on the front surface of the second insulating
substrate,

wherein the positive-electrode external lead terminal and the negative-electrode external lead terminal are disposed adjacent
to each other in parallel,

a portion of the pins constituting the plurality of first conductive pins is fixed to the other surface of the first semiconductor
element, and another portion of pins constituting the plurality of first conductive pins are fixed to the third conductive
pattern,

a portion of the pins constituting the plurality of second conductive pins is fixed to the other surface of the second semiconductor
element, and another portion of the pins constituting the plurality of second conductive pins are fixed to the second conductive
pattern,

the insulating substrate with conductive pins is disposed on the other surface of the first semiconductor element and the
other surface of the second semiconductor element, and

an area in which the first semiconductor element and the second semiconductor element are disposed has a size substantially
equivalent to a face of the insulating substrate with conductive pins.

US Pat. No. 9,431,391

GALLIUM NITRIDE HEMT DEVICE WITH A MOSFET IN SERIES COUPLED TO DIODES FOR PROTECTION OF HIGH-VOLTAGE

Furukawa Electric Co., Lt...

1. A semiconductor device, comprising:
a first element which is a normally-on type transistor made of nitride-based compound semiconductor, the first element being
a gallium nitride-high electron mobility transistor (GaN-HEMT) or a junction field effect transistor (FET);

a second element connected to the first element in series and being a transistor having withstand voltage between a source
and a drain which is lower than withstand voltage of the first element;

a first diode connected between a gate of the first element or a gate of the second element and a drain of the first element
so that a cathode of the first diode is connected at the drain's side, an anode of the first diode is directly connected to
the gate of the first element, and the first diode having predetermined avalanche withstand voltage;

a first resistance connected to the gate to which the first diode is connected, wherein the avalanche withstand voltage of
the first diode is lower than breakdown voltage of the first element, the first diode is connected to the gate of the first
element, and the first resistance is connected to the gate of the first element and the source of the second element; and

a protection diode, a cathode of the protection diode being connected to a source of the first element and the drain of the
second element, and an anode of the protection diode being connected to the first resistance and directly connected to the
anode of the first diode.

US Pat. No. 9,431,270

METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method for producing a semiconductor device comprising:
a diffusion step of forming a diffusion layer with a high-temperature and long-term thermal diffusion process which is performed
for 100 hours or more on a silicon semiconductor substrate produced by a floating zone method, at a thermal diffusion temperature
of at least about 1290° C. to a melting temperature of a silicon crystal; and

a giving step of giving a diffusion source for a silicon atom, which becomes an interstitial atom in the silicon semiconductor
substrate in the diffusion step, to surface layers of two main surfaces of the silicon semiconductor substrate before the
diffusion step
wherein the semiconductor substrate is cut from a silicon crystal, which is produced by the floating zone method using crystal
silicon produced by a Czochralski method as a raw material and wherein the giving step is a step of implanting the silicon
atoms into surface layers of the two main surfaces of the silicon semiconductor substrate.

US Pat. No. 9,418,502

COMMODITY STORAGE DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A commodity storage device that has commodity storage columns defining respective commodity storage passages in each of
which commodities are stored upright in a line, the commodity storage device comprising:
first gate members, each of which is provided turnably in such a manner as to enter and retreat from the corresponding commodity
storage passage, restricts extraction of a most downstream commodity on a most downstream side when held in a state of entering
the commodity storage passage during a normal state, but retreats from the commodity storage passage to allow the most downstream
commodity to be extracted in response to an extraction operation on the most downstream commodity when the state of entering
the commodity storage passage is cancelled;

second gate members, each of which is provided so as to be able to turn in conjunction with the corresponding first gate member
in such a manner as to enter and retreat from the corresponding commodity storage passage, retreats from the commodity storage
passage when the first gate member is restricted to the state of entering the commodity storage passage, but enters the commodity
storage passage and comes into abutment with an upper portion of a second commodity adjacent to an upstream-side part of the
most downstream commodity, to restrict the second commodity from moving to a downstream side when the first gate member retreats
from the commodity storage passage; and

flapper members, each of which is provided turnably on a side wall forming the corresponding commodity storage passage in
such a manner as to enter and retreat from the commodity storage passage, retreats from the commodity storage passage when
the first gate member is restricted to the state of entering the commodity storage passage, but enters the commodity storage
passage and comes into abutment with a lower portion of the second commodity to restrict the second commodity from moving
to the downstream side when the state of the first gate member of entering the commodity storage passage is cancelled.

US Pat. No. 9,406,603

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a semiconductor mounting board in which a plurality of semiconductor elements are mounted on an insulating wiring board, the
semiconductor mounting board having a circuit pattern;

an implant board in which via holes for electrical connection are provided in an insulating substrate having a printed wiring,
and

implant pins, first ends of which are press-fitted into the via holes and second ends of which are bonded to the semiconductor
element and/or the circuit pattern of the semiconductor mounting board such that there is an electrical connection to the
semiconductor element of the semiconductor mounting board,

wherein distance between (i) the implant board and (ii) the semiconductor elements and/or the circuit pattern of the semiconductor
mounting board varies, and

wherein the implant pins are bonded to the semiconductor element and/or the circuit pattern of the semiconductor mounting
board through cylindrical terminals press-fitted onto the second ends of the implant pins, and in the semiconductor device
a depth with which each of the implant pins is press-fitted into corresponding ones of the cylindrical terminals varies so
that total length of the implant pin and the cylindrical terminal which are press-fitted to each other match up with a distance
between the semiconductor element and/or the circuit pattern on the semiconductor mounting board and the implant board.

US Pat. No. 9,407,153

SWITCHING POWER SUPPLY SYSTEM

FUJI ELECTRIC CO., LTD., ...

1. A switching power supply system comprising:
a switching power supply system main body switching a switching device connected in series to a primary winding of a transformer
applied with an input voltage, and rectifying a voltage generated in a secondary winding of the transformer to obtain a predetermined
output voltage; and

a control circuit receiving an internal power supply voltage generated from the voltage generated in an auxiliary winding
of the transformer after applying specified voltage and controlling the switching of the switching device,

wherein the control circuit comprises:
an under voltage lock out circuit stopping the operation of the control circuit while the voltage supplied from the auxiliary
winding is lower than a predetermined power supply lower limit voltage;

a feedback voltage decision circuit stopping the driving of the switching device when a feedback voltage, which indicates
an error between a predetermined value of the output voltage and the value of the output voltage, is lower than a predetermined
threshold value;

a flip-flop set by an output of the feedback voltage decision circuit, and reset when the voltage supplied from the auxiliary
winding exceeds the voltage ensuring a normal operation of the control circuit; and

a switching circuit to set the power supply lower limit voltage in the under voltage lock out circuit, lower than that of
the normal operation when the flip-flop is set.

US Pat. No. 9,373,555

POWER SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING THE SAME, AND POWER CONVERTER

FUJI ELECTRIC CO., LTD., ...

1. A power semiconductor module comprising:
a metal plate having a through hole with an eaves;
an insulated metal block including a metal block having an element mounting region on an upper surface, and an insulating
layer made of a ceramic material directly formed on surfaces other than the upper surface of the metal block and a portion
other than the element mounting region on the upper surface, the insulated metal block being fitted into the through hole
with the eaves in the metal plate so that an upper portion of the insulated metal block contacts the eaves of the through
hole to electrically insulate between the metal block and the metal plate by the insulating layer;

a circuit pattern disposed over the metal plate with the insulating material interposed therebetween;
a power semiconductor element fixed to the element mounting region of the upper surface of the metal block; and
a connection conductor connecting the power semiconductor element and the circuit pattern.

US Pat. No. 9,299,771

SEMICONDUCTOR DEVICE WITH AN ELECTRIC FIELD REDUCTION MECHANISM IN AN EDGE TERMINATION REGION SURROUNDING THE ACTIVE REGION

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
an active region provided in one main surface of a semiconductor substrate;
an edge termination region surrounding the active region;
an electric field reduction mechanism provided in the edge termination region, the electric field reduction mechanism including
a plurality of guard rings provided in a surface layer of the one main surface of the semiconductor substrate and field plates
provided on the guard rings, the field plates having the same potential as the guard rings and including

first field plates provided on surfaces of the guard rings, and
second field plates provided on the first field plates and having a thickness greater than that of the first field plates,
wherein a gap between the second field plates is greater than a gap between the first field plates;

an interlayer insulating film interposed between the first field plates and the second field plates; and
barrier metal films provided between the second field plate and the interlayer insulating film so as to be in conductive contact
with the second field plates, wherein a gap between the barrier metal films is substantially equal to the gap between the
first field plates.

US Pat. No. 9,252,144

FIELD EFFECT TRANSISTOR AND A DEVICE ELEMENT FORMED ON THE SAME SUBSTRATE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a first field effect transistor of a first conductivity type and including:
a first semiconductor region of a second conductivity type disposed on a semiconductor substrate of a first conductivity type
or formed on a surface layer of the semiconductor substrate of the first conductivity type,

a second semiconductor region of a first conductivity type selectively formed on a surface layer of the first semiconductor
region;

a third semiconductor region of the first conductivity type selectively formed on the surface layer of the first semiconductor
region and spaced apart from the second semiconductor region;

a first gate electrode formed on a surface of a portion of the first semiconductor region disposed between the second semiconductor
region and the third semiconductor region with an intercalated first gate insulating film;

a fourth semiconductor region of the first conductivity type selectively formed in the second semiconductor region;
a first electrode connected to the third semiconductor region; and
a second electrode connected to the fourth semiconductor region; and
a device element including a fifth semiconductor region of the first conductivity type formed on the surface layer of the
first semiconductor region, spaced apart from the second semiconductor region and the third semiconductor region, the device
element being isolated from the first field effect transistor by a part of the first semiconductor region disposed between
the second semiconductor region and the fifth semiconductor region,

wherein an impurity concentration of the first semiconductor region disposed between the second semiconductor region and the
semiconductor substrate is in the range of 1.3×1012/cm2 to 2.8×1012/cm2, and an impurity concentration of the second semiconductor region is in the range of 1.1×1012/cm2 to 1.4×1012/cm2.

US Pat. No. 9,209,099

POWER SEMICONDUCTOR MODULE

FUJI ELECTRIC CO., LTD., ...

1. A power semiconductor module, comprising:
a frame made of an insulator and having a bottom opening and a top opening;
a first electrode plate made of a metal and fixed in the bottom opening in said frame;
a semiconductor element having a front surface electrode and a reverse surface electrode, said reverse surface electrode being
electrically and physically connected to a principal surface of said first electrode plate;

a multilayer substrate comprising a circuit plate, an insulating plate, and a metal plate stacked together, said metal plate
being fixed to the principal surface of said first electrode plate;

a wiring member that electrically connects the front surface electrode of said semiconductor element to the circuit plate
of said multilayer substrate;

a second electrode plate made of a metal and fixed in the top opening in said frame; and
a metal block that has a first surface having a protrusion and a second surface opposite thereto and that tapers from said
first surface to said second surface, said protrusion being electrically and physically connected to the circuit plate of
said multilayer substrate, and said second surface of the metal block being electrically and physically connected to said
second electrode plate.

US Pat. No. 9,190,092

MAGNETIC RECORDING MEDIUM AND METHOD FOR PRODUCING THE SAME

FUJI ELECTRIC CO., LTD., ...

1. A patterned magnetic recording medium, including a plurality of magnetic dots, each corresponding to a recording bit, formed
on a non-magnetic material, the patterned magnetic recording medium comprising:
an aluminum layer on a substrate made of the non-magnetic material; and
a plurality of polygonal cavity portions in the aluminum layer,
wherein each of the plurality of polygonal cavity portions extends across a width of more than one said recording bit in a
track direction of the recording medium, and

wherein the plurality of magnetic dots are formed only in corners of the plurality of polygonal cavity portions.

US Pat. No. 9,171,768

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
an insulating substrate joined with a semiconductor chip;
a case covering a surface of the insulating substrate where the semiconductor chip is joined, and having a lid disposed above
a surface of the insulating substrate where the semiconductor chip is joined; and

a control terminal having one end portion electrically connected to the semiconductor chip, and another end portion passing
through the lid and exposed to outside of the case,

wherein the control terminal includes a through section exposed to the outside of the case and extending perpendicular to
the insulating substrate, the through section having a cut-out section where a part of the exposed portion is cut out, and
a blocking section surrounded by the cut-out section and bent laterally outwardly at one end thereof, the blocking section
contacting the lid and blocking a movement of the control terminal;

a connection section extending parallel to the through section, and having one end portion connected to the insulating substrate;
and

a linking section connecting the through section and the connection section on a side where the blocking section is not disposed,
the linking section having a flat surface orthogonal to the through section to absorb a compressive load applied to the through
section, and

wherein the lid includes a through hole, through which the through section passes, the through hole having a width in a lateral
direction corresponding to a thickness of the through section;

a step provided at a side section of the through hole and extending from an upper surface of the lid exposed to the outside
of the case, the step contacting the blocking section; and

a protrusion provided on a side opposite to the step relative to the through hole and contacting the flat surface of the linking
section, the protrusion having a size such that when the protrusion contacts the flat surface of the linking section, a free
end of the blocking section is exposed inside the step.

US Pat. No. 9,166,497

SWITCHING POWER SOURCE DEVICE WITH DISCHARGE CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A switching power source device comprising:
a switching power supply main body that switches an input voltage via a switching element to obtain a predetermined DC output
voltage;

a control circuit that performs on/off-driving of the switching element; and
a capacitor that is connected to the control circuit to be charged by an external power supply via an activation switch circuit
during activation and that is charged by a voltage generated in the switching power supply main body after completion of activation
to supply a control power voltage to the control circuit, the control circuit comprising:

a latch circuit that is set according to a latch signal emitted when an abnormality is detected, to stop the driving of the
switching element;

a discharge circuit that receives the latch signal to be turned on and discharges charges accumulated in the capacitor; and
a comparator that resets the latch circuit when the control power voltage decreases to an operation stop voltage.

US Pat. No. 9,082,812

SEMICONDUCTOR DEVICE INCLUDING A COUNTER LAYER, FOR POWER CONVERSION AND METHOD OF MANUFACTURING THE SAME

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:
a drift layer which includes a first conductivity type semiconductor substrate;
a second conductivity type base layer which is selectively formed on a surface of a first principal plane of the semiconductor
substrate;

a first conductivity type source layer which is selectively formed on a surface of the base layer;
a second conductivity type contact layer which is formed to be in contact with the source layer on the first principal plane
side of the base layer and which has a concentration higher than that of the base layer;

a gate electrode which is formed so as to face the drift layer, the base layer, and the source layer through an insulating
film;

an emitter electrode which is formed on the first principal plane so as to be electrically connected to the source layer;
and

an interlayer insulating film which is formed on the first principal plane of the semiconductor substrate to be interposed
between the gate electrode and the emitter electrode so as to insulate the gate electrode and the emitter electrode,

wherein the semiconductor device further includes a second conductivity type counter layer which is formed to be in contact
with the source layer and to overlap the contact layer and which is formed to be shallower than the base layer and to have
a high concentration,

wherein a total doping amount per unit area of the counter layer is larger than 10% of a total doping amount per unit area
of the contact layer,

wherein the depth of the counter layer is shallower than the depth of the contact layer;
wherein the depth of the counter layer is deeper than the depth of the source layer, and
wherein a sum of the total doping amount per unit area of the counter layer and the total doping amount per unit area of the
contact layer is larger than that of the source layer.

US Pat. No. 9,071,166

POWER CONVERTER WITH SURGE VOLTAGE SUPPRESSION

FUJI ELECTRIC CO., LTD., ...

2. A power converter for converting power received from a power source, and supplying the converted power to a load, comprising:
a semiconductor switching element;
a control circuit that controls turning on and off of the semiconductor switching element; and
an LC circuit formed of an inductor and a capacitor, the inductor being connected between the semiconductor switching element
and the load, the capacitor being connected between a load side terminal of the inductor and one end of the power source;

the control circuit providing a control signal for turning the semiconductor switching element into an on-state,
wherein
the control signal is configured of a first on-signal and second on-signal,
an off-state period is provided between the first on-signal and the second on-signal of the control signal, the off-state
period being a time practically equivalent to a period of the first on-signal, and

the period of the first on-signal the off-state period are set to a time practically one-sixth of a resonance cycle of the
LC circuit provided between the semiconductor switching element and the load.

US Pat. No. 9,362,373

SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME

FUJI ELECTRIC CO., LTD., ...

9. The method according to claim 8, the method further comprising the steps of:
forming a second electrode on the interlayer insulator film; and
connecting the second electrode to the semiconductor region of second conductivity type through the first opening and the
second opening.

US Pat. No. 9,287,187

POWER SEMICONDUCTOR MODULE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor power module molded structure, comprising:
a case; and
a plurality of power semiconductor modules in the case, each of the power semiconductor modules comprising:
one insulating layer,
a copper base substrate having a first copper block and a second copper block, either the first or second copper block being
fixed on one side of the one insulating layer and the other being fixed on the other side of the one insulating layer;

a plurality of power semiconductor elements having silicon carbide and formed on the copper base substrate, each having one
side fixed onto the first copper block with a first conductive bond layer;

a plurality of implant pins fixed to the other side of each of the plurality of power semiconductor elements with a second
conductive bond layer;

a printed circuit board fixed to the plurality of implant pins and disposed to face the plurality of power semiconductor elements;
a first sealing material containing no flame retardant, and disposed only at a portion where the plurality of power semiconductor
elements is enclosed, the first sealing material covering an upper portion and side portions of each of the plurality of power
semiconductor elements between the copper base substrate and the printed circuit board;

a second sealing material containing a flame retardant, and disposed to cover the first sealing material; and
an external connection terminal extending upwardly from the copper base substrate to cross the printed circuit board,
wherein said plurality of power semiconductor elements is disposed on the one insulating layer with a space therebetween,
only the first sealing material being disposed in the space and around said plurality of power semiconductor elements,

the second sealing material encloses an outer circumferential part of the first sealing material surrounding said plurality
of power semiconductor elements to directly cover side portions of the first sealing material and indirectly cover an upper
portion of the first sealing material through the printed circuit board,

the first sealing material contains no flame retardant to enhance a thermal resistant performance, and the second sealing
material contains the flame retardant to resist oxidation degradation, and

the first sealing material encloses the external connection terminal between the copper base substrate and the printed circuit
board,

wherein said plurality of power semiconductor modules is arranged side by side in the case,
the printed circuit boards of the plurality of power semiconductors are integrally connected to each other, and
the second sealing material is arranged in the case between the plurality of power semiconductor modules, and
wherein a heat distortion temperature of each of the first sealing materials is 175° C. to 225° C., a thermal expansion coefficient
of each of the first sealing materials is 1.5×10?5/° C. to 1.8×10?5/° C., and a bonding strength of each of the first sealing materials to each of the copper base substrates is 10 MPa to 30
MPa; a heat distortion temperature of each of the second sealing materials is 100° C. to 175° C., a thermal expansion coefficient
of each of the second sealing materials is 1.5×10?5/° C. to 1.8×10?5/° C., and a bonding strength of each of the second sealing materials to each of the copper base substrates is 10 MPa to 30
MPa; and liquid epoxy resin is used in the first sealing materials and the second sealing materials.

US Pat. No. 9,225,326

VOLTAGE CONTROLLED SWITCHING ELEMENT GATE DRIVE CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A voltage controlled switching element gate drive circuit that supplies a gate signal to a gate of a voltage controlled
switching element to drive the voltage controlled switching element, the gate drive circuit comprising:
a high potential side switching element and low potential side switching element connected in series;
a variable resistor interposed between at least the high potential side switching element and a high potential power supply
or the low potential side switching element and a low potential power supply; and

a control circuit that adjusts a resistance value of the variable resistor;
wherein the variable resistor includes a first constant-value resistor coupled to a variable-current source; and
wherein the variable current source includes a series circuit of a first insulated gate transistor and a second constant-value
resistor interposed between the first constant-value resistor and a ground potential.

US Pat. No. 9,184,663

SWITCHING POWER SUPPLY DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A switching power supply device comprising:
a power factor correction converter which obtains a DC voltage by switching an input AC voltage;
a DC-DC converter which obtains a predetermined DC output voltage by switching an output voltage of the power factor correction
converter; and

a load state detecting circuit which outputs an operation-enable signal for the power factor correction converter in accordance
with a load state of the DC-DC converter to thereby enable or stop operation of the power factor correction converter; wherein:

the load state detecting circuit is configured so that a threshold for determining the size of the load of the DC-DC converter
is set in the load state detecting circuit based on a predetermined maximum value of the output voltage of the power factor
correction converter in an operation-stopped state of the power factor correction converter, so that the load state detecting
circuit outputs the operation-enable signal when a signal indicating the size of the load of the DC-DC converter exceeds the
threshold,

the threshold is set as a threshold voltage to be compared with a feedback voltage used for controlling the DC output voltage
in the DC-DC converter; and

the load state detecting circuit includes:
a flip-flop which outputs the operation-enable signal at a reset time;
a light load detecting circuit which sets the flip-flop when the feedback voltage is lower than a preset first threshold voltage;
and

a normal load detecting circuit which resets the flip-flop when a fixed time has passed after the feedback voltage exceeds
a second threshold voltage which is higher than the first threshold voltage and which is set based on the maximum value of
the output voltage of the power factor correction converter.

US Pat. No. 9,166,018

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device, comprising:
a first ion implantation step of implanting a p-type impurity into a surface of a semiconductor wafer to form a p-type impurity
region in a surface layer of said semiconductor wafer;

a coating step of coating a resist on the surface of the semiconductor wafer where the p-type impurity region is formed;
an exposing step of patterning the resist to selectively expose the semiconductor wafer;
a second ion implantation step of implanting an n-type impurity into the semiconductor wafer using the resist that remains
as a mask to selectively form an n-type impurity region, said n-type impurity region being deeper than the p-type impurity
region from the surface of the semiconductor wafer and being adjacent to the p-type impurity region; and

a removal step of removing a portion of the semiconductor wafer above the n-type impurity region to expose the n-type impurity
region, the removed portion of the semiconductor wafer being a region where the p-type impurity has been implanted in the
first ion implantation step.

US Pat. No. 9,447,767

SINGLE CHIP IGNITER AND INTERNAL COMBUSTION ENGINE IGNITION DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A single chip igniter, comprising:
a MOS transistor;
a gate terminal electrically connected to the gate of the MOS transistor; and
a control circuit that limits the gate voltage of the MOS transistor,
all disposed on the same semiconductor substrate, wherein
an input voltage into the gate terminal of the single chip igniter is the power supply voltage of the control circuit and
a control signal of the MOS transistor, the minimum value of the input voltage is less than 3.5V, and wherein

the effective gate threshold voltage of the MOS transistor configuring the single chip igniter is 1V or less, and
when the channel length of the MOS transistor configuring the single chip igniter is L (cm) and the impurity concentration
per unit volume of the channel region of the MOS transistor is N (cm?3), L?4×10?4×(10?17)1/3×N1/3.

US Pat. No. 9,230,958

WIDE BAND GAP SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF

FUJI ELECTRIC CO., LTD., ...

1. A wide band gap semiconductor apparatus comprising:
a semiconductor substrate formed by a high concentration, wide band gap semiconductor of a first conductivity type;
a deposited semiconductor film formed on a surface of the semiconductor substrate and formed by a wide band gap semiconductor
of the first conductivity type and having a concentration lower than that of the semiconductor substrate;

a deposited metal film formed on the deposited semiconductor film; and
a second conductivity type region formed in a vicinity of the deposited metal film in the deposited semiconductor film, wherein
a plurality of second conductivity type regions are disposed at predetermined intervals along a width direction in the deposited
semiconductor film, at least at a position in a lower portion in a depth direction of the deposited metal film, and

the deposited semiconductor film has an internal width in the depth direction different from a width thereof at a position
in an upper portion in the depth direction, wherein

an interval of the deposited semiconductor film is set to have a substantially rhombic shape with which the interval narrows
from the position in the upper portion in the depth direction to the lower portion as a depth thereof becomes deeper and thereafter,
widens.