US Pat. No. 9,240,228

STATIC MEMORY APPARATUS AND DATA READING METHOD THEREOF

Faraday Technology Corp.,...

1. A static memory apparatus, comprising:
a plurality of memory cells arranged to form a memory array coupled to a plurality of bit lines;
a plurality of dummy memory cells coupled to a dummy bit line and respectively comprising a plurality of discharge ends to
discharge charges on the dummy bit line;

a sense amplifier coupled to the bit lines and the dummy bit line and performing a sensing and amplifying operation on signals
on the bit lines according to a signal on the dummy bit line to generate readout data; and

a discharge current adjuster coupled to at least one controlled discharge end of the discharge ends and adjusting a discharge
current on the at least one controlled discharge end according to an operating voltage received by the memory cells.

US Pat. No. 9,095,808

ELECTROLYTIC SYSTEM AND METHOD FOR FILTERING AN AQUEOUS PARTICULATE SUSPENSION

Physical Sciences, Inc., ...

1. A method for the filtration of suspended particles in a solution comprising:
a. adding a solution with suspended particles to an electrolytic cell containing a filter and at least an anode and a cathode,
wherein said suspended particles are algae particles;

b. establishing a predetermined gap between said anode and said cathode;
c. connecting said anode and said cathode to a power supply; and
d. delivering an electric field from said power supply to said anode and said cathode; wherein said suspended particles move
away from said filter, creating a zone of depleted suspended particles near the filter.

US Pat. No. 9,276,596

ANALOG TO DIGITAL CONVERTING APPARATUS AND INITIAL METHOD THEREOF

FARADAY TECHNOLOGY CORPOR...

1. An analog to digital converting apparatus, comprising:
a first switching capacitor unit, having a plurality of first capacitors and a plurality of first switches respectively corresponding
to the first capacitors, wherein the first switching capacitor unit couples each of the first capacitors to a first logic
voltage, a second logic voltage, or a first input voltage to generate a first voltage through one of the corresponding first
switches according to a first control signal;

a second switching capacitor unit, having a plurality of second capacitors and a plurality of second switches respectively
corresponding to the second capacitors, wherein the second switching capacitor unit couples each of the second capacitors
to the first logic voltage, the second logic voltage, or a second input voltage to generate a second voltage through one of
the corresponding second switches according to the first control signal;

a circuit unit, generating the first control signal by comparing the first voltage and the second voltage;
a first and second initialization switches, respectively serially connected between the first voltage and a common-mode endpoint
and between the common-mode endpoint and the second voltage, and being turned on or off according to a second control signal;

a third capacitor and a fourth capacitor, respectively receiving the first and second voltages and commonly coupled to the
common-mode endpoint; and

a logic buffer, choosing to output the first logic voltage or the second logic voltage to the common-mode endpoint according
to the second control signal,

wherein the second control signal indicates whether the analog to digital converting apparatus is in a sampling period or
not.

US Pat. No. 9,053,621

IMAGE SURVEILLANCE SYSTEM AND IMAGE SURVEILLANCE METHOD

Faraday Technology Corp.,...

1. An image surveillance method suitable for an image surveillance system, the image surveillance method comprising:
capturing an image;
defining at least one reference target in the captured image;
identifying a monitored object in the image;
individually calculating a distance between the monitored object and each of the at least one reference target; and
determining whether to announce at least one warning according to a relationship between at least one threshold and the distance,
wherein the step of determining whether to announce the at least one warning according to the relationship between the at
least one threshold and the distance comprises:

calculating a function; and
determining whether to announce the at least one warning according to a relationship between the at least one threshold and
the function, wherein the function is

Di is a distance from the monitored object to an ith reference target of the at least one reference target, ai and bi are real numbers, k is a real number larger than
and n is a quantity of the at least one reference target.

US Pat. No. 9,366,722

METHOD AND APPARATUS FOR PERFORMING DE-SKEW CONTROL

Faraday Technology Corp.,...

1. A method for performing de-skew control, the method applied to an electronic device, the method comprising:
performing a symbol detection at a plurality of lanes of the electronic device, respectively, to determine locations of a
specific symbol at the plurality of lanes, respectively;

selectively rearranging decoded data in the plurality of lanes to generate a plurality of sets of de-skewed data respectively
corresponding to the plurality of lanes according to the locations of the specific symbol at the plurality of lanes; and

buffering the plurality of sets of de-skewed data to selectively delay output time of the plurality of sets of de-skewed data,
to control beginning of the plurality of sets of de-skewed data to be simultaneously outputted;

wherein the step of buffering the plurality of sets of de-skewed data to selectively delay the output time of the plurality
of sets of de-skewed data, to control the beginning of the plurality of sets of de-skewed data to be simultaneously outputted
further comprises:

utilizing a plurality of D flip flops corresponding to the plurality of lanes, respectively, to buffer the plurality of de-skewed
data, so as to selectively delay the output time of the plurality of de-skewed data.

US Pat. No. 9,431,024

METHOD AND APPARATUS FOR DETECTING NOISE OF AUDIO SIGNALS

Faraday Technology Corp.,...

1. A method for detecting noise of audio signals, comprising:
converting an audio signal into a plurality of audio frames, wherein the audio frames are arranged in a chronological order
while taking a target frame as a center;

calculating a plurality of magnitudes respectively corresponding to a plurality of spectral components of each of the audio
frames;

calculating differences between the adjacent magnitudes in a time-frequency domain to obtain a plurality of difference values
in at least two directions orthogonal to each other in the time-frequency domain, wherein the time-frequency domain is defined
by the audio frames;

determining a maximum degree of difference of the magnitudes in the time-frequency domain according to the difference values;
and

determining whether a part of the audio signal corresponding to the target frame is a noise according to the maximum degree
of difference.

US Pat. No. 9,323,264

VOLTAGE REGULATOR APPARATUS WITH SENSING MODULES AND RELATED OPERATING METHOD THEREOF

Faraday Technology Corp.,...

1. A voltage regulator apparatus, comprising:
a bandgap reference circuit, arranged for generating a bandgap reference voltage;
a voltage regulator module, coupled to the bandgap reference circuit, the voltage regulator module arranged for regulating
an input voltage according to the bandgap reference voltage to generate an output voltage;

a first sensing module, coupled to the voltage regulator module, the first sensing module arranged for sensing a variation
of the output voltage to selectively control the output voltage, wherein when the output voltage abruptly decreases, the first
sensing module reduces a decrement of the output voltage based on a variation amount of the output voltage;

a second sensing module, coupled to the voltage regulator module, the second sensing module arranged for sensing the variation
of the output voltage, converting the variation of the output voltage into a current signal, and applying the current signal
to a control terminal within the voltage regulator module, to indirectly control the output voltage; and

a third sensing module, coupled to the voltage regulator module, the third sensing module arranged for sensing a variation
of the output voltage to selectively control the output voltage, wherein when the output voltage abruptly increases, the third
sensing module reduces an increment of the output voltage based on another variation amount of the output voltage.

US Pat. No. 9,275,726

STATIC MEMORY CELL

Faraday Technology Corp.,...

1. A static memory cell comprising:
a data latch circuit configured to store a bit data, the data latch circuit comprising a first inverter and a second inverter
coupled to each other, the first inverter and the second inverter respectively receiving a first voltage and a second voltage
as power voltages; and

a voltage provider coupled to the data latch circuit to provide the first voltage and the second voltage to the data latch
circuit,

wherein when the bit data is written into the data latch circuit, the voltage provider adjusts a voltage value of the first
voltage or a voltage value of the second voltage according to the bit data,

wherein the voltage provider comprises:
a first tri-state inverter, an output end of the first tri-state inverter being coupled to an input end of the first tri-state
inverter, such that the output end of the first tri-state inverter being coupled to a first output end, and the first output
end providing the first voltage to the first inverter; and

a second tri-state inverter, an output end of the second tri-state inverter being coupled to an input end of the second tri-state
inverter, such that the output end of the second tri-state inverter being coupled to a second output end, and the second output
end providing the second voltage to the second inverter,

wherein when the bit data is written into the data latch circuit, one of the first tri-state inverter and the second tri-state
inverter is enabled according to the bit data.

US Pat. No. 10,090,853

ANALOG-TO-DIGITAL CONVERSION DEVICE

Faraday Technology Corp.,...

1. An analog-to-digital conversion device, converting an input signal pair to generate an output signal, the analog-to-digital conversion device comprising:a plurality of switch groups receiving the input signal pair and a plurality of reference voltages and selecting to output one of the input signal pair and the reference voltages according to a control signal to respectively generate a plurality of selection voltages;
a plurality of capacitors respectively receiving the selection voltages and generating a first comparison voltage and a second comparison voltage;
a comparator coupled to the capacitors and comparing the first comparison voltage and the second comparison voltage to generate a comparison result signal; and
a controller coupled to the comparator and the switch groups and setting a plurality of conversion times for converting a plurality of bits of the output signal according to the comparison result signal,
wherein at least two of the conversion times are different,
wherein the conversion time for converting a more significant bit of the output signal is not shorter than the conversion time for converting a less significant bit of the output signal.

US Pat. No. 9,442,502

VOLTAGE REGULATOR WITH SOFT-START CIRCUIT

Faraday Technology Corp.,...

1. A voltage regulator, comprising:
an operational amplifier, wherein a first input terminal of the operational amplifier receives a control voltage, a second
input terminal of the operational amplifier receives a feedback voltage, and an output terminal of the operational amplifier
generates an error signal;

a transistor, wherein a gate terminal of the transistor is connected to the output terminal of the operational amplifier and
receives the error signal, a first terminal of the transistor receives a power supply voltage, and a second terminal of the
transistor is connected to an output terminal of the voltage regulator, wherein the output terminal of the voltage regulator
generates an output voltage;

a first resistor, wherein a first terminal of the first resistor is connected to the output terminal of the voltage regulator,
and a second terminal of the first resistor is connected to the second input terminal of the operational amplifier;

a second resistor, wherein a first terminal of the second resistor is connected to the second terminal of the first resistor
and generates the feedback voltage, and a second terminal of the second resistor is connected to a ground voltage;

an output voltage delaying circuit connected to the output terminal of the voltage regulator, wherein the output voltage delaying
circuit receives the output voltage and generates a delayed output voltage; and

a selecting circuit, wherein a first input terminal of the selecting circuit receives a reference voltage, a second input
terminal of the selecting circuit receives the delayed output voltage, and an output terminal of the selecting circuit generates
the control voltage to the first input terminal of the operational amplifier,

wherein if the reference voltage is larger than the delayed output voltage, the selecting circuit selects the delayed output
voltage as the control voltage, wherein if the reference voltage is smaller than the delayed output voltage, the selecting
circuit selects the reference voltage as the control voltage.

US Pat. No. 9,641,159

FLIP-FLOP CIRCUIT

Faraday Technology Corp.,...

1. A flip-flop circuit, comprising:
a first logic circuit, receiving a selecting signal and a clock signal, and operating a logic operation on the selecting signal
and the clock signal to generate a first control signal;

a first master latch, coupled to the first logic circuit and receiving the first control signal, and receiving the clock signal
and a data signal, wherein the first master latch receives the data signal according to the first control signal, and latches
the data signal according to the clock signal and the selecting signal;

a second master latch, receiving the selecting signal, the clock signal and a scan data signal, and latching the scan data
signal according to the selecting signal and the clock signal, wherein an output terminal of the second master latch is directly
connected to an output terminal of the first master latch; and

a slave latch, coupled to the output terminals of the first master latch and the second master latch, and latching a signal
on the output terminals of the first and second master latches according to the clock signal and the selecting signal for
generating an output signal.

US Pat. No. 9,484,085

STATIC MEMORY APPARATUS AND STATIC MEMORY CELL THEREOF

FARADAY TECHNOLOGY CORPOR...

1. A static memory cell, comprising:
a data latch circuit, comprising a first tristate output inverting circuit and a second tristate output inverting circuit,
an input terminal of the first tristate output inverting circuit being coupled to an output terminal of the second tristate
output inverting circuit, an output terminal of the first tristate output inverting circuit being coupled to an input terminal
of the second tristate output inverting circuit;

a data write-in circuit, coupled to the data latch circuit, providing a first reference voltage to a power receiving terminal
of a selected tristate output inverting circuit which is one of the first tristate output inverting circuit and the second
tristate output inverting circuit, and providing a second reference voltage to an input terminal of the selected tristate
output inverting circuit during a data write-in time period; and

a data read-out circuit, coupled to the output terminal of the second tristate output inverting circuit, generating read-out
data according to a voltage at the output terminal of the second tristate output inverting circuit and the second reference
voltage during a data read-out time period.

US Pat. No. 9,332,185

METHOD AND APPARATUS FOR REDUCING JITTERS OF VIDEO FRAMES

Faraday Technology Corp.,...

1. A method for reducing jitters of video frames, comprising:
dividing a first frame into a plurality of blocks;
selecting at least one of the plurality of blocks according to a variance of each of the plurality of blocks;
determining a global motion vector of the first frame in a direction according to the at least one selected block; and
performing motion compensation on the first frame according to the global motion vector in the direction,
wherein the first frame is one of a plurality of frames of a video, the video starts from a second frame, and the step of
performing motion compensation on the first frame comprises:

calculating a first relative position of each third frame of a continuous frame group which includes the first frame of the
video in the direction, wherein the first relative position is generated according to the global motion vector of each of
the frames from the second frame to the third frame of the video;

calculating a second relative position of the first frame in the direction according to the first relative position of each
of the third frames; and

performing motion compensation on the first frame according to the first relative position and the second relative position
of the first frame.

US Pat. No. 9,177,624

MEMORY GENERATING METHOD OF MEMORY COMPILER AND GENERATED MEMORY

Faraday Technology Corp.,...

1. A memory, comprising:
a logic controller generating a word line enabling signal and a boost enabling signal;
a word line driver receiving the word line enabling signal;
a boost circuit receiving the boost enabling signal;
plural capacitor circuits connected between the boost circuit and the word line driver;
plural memory cores, wherein each of the plural memory cores is connected with the word line driver through plural word lines;
plural selectors connected with the corresponding memory cores; and
plural output drivers connected with the corresponding selectors,
wherein the number of the plural memory cores is positively correlated with the number of the plural capacitor circuits.

US Pat. No. 9,385,733

CLOCK GENERATING APPARATUS AND FRACTIONAL FREQUENCY DIVIDER THEREOF

Faraday Technology Corp.,...

1. A fractional frequency divider, comprising:
a frequency divider, having an input terminal coupled to an output terminal of a multi-phase-frequency generating circuit
for receiving an output clock signal;

a plurality of samplers, having input terminals coupled to an output terminal of the frequency divider for receiving a frequency-divided
clock signal, and trigger terminals of the samplers coupled to the multi-phase-frequency generating circuit for receiving
a plurality of sampling clock signals, wherein the sampling clock signals have a same frequency and different phases;

a selector, having a plurality of input terminals respectively coupled to output terminals of the samplers, and an output
terminal coupled to a feedback terminal of the multi-phase-frequency generating circuit; and

a control circuit, providing a fraction code to a control terminal of the selector, so as to control the selector to selectively
couple the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.

US Pat. No. 9,946,294

DOUBLE DATA RATE GATING METHOD AND APPARATUS WITH REAL-TIME DETECTION CAPABILITY FOR PERFORMING GATING TO IMPROVE THE EFFICIENCY OF MEMORY ACCESS CONTROL

Faraday Technology Corp.,...

1. A double data rate (DDR) gating method applied to a memory controller, the DDR gating method comprising:outputting an outward clock signal to a memory from the memory controller, and receiving a backward clock signal corresponding to the outward clock signal from the memory, wherein the backward clock signal is utilized as reference for a data reading operation of the memory controller with respect to the memory; and
providing a reference signal to an input stage of the memory controller to generate gating-related information through single ended receiving of the input stage for performing gating when sampling the backward clock signal, and lengthening a preamble of the backward clock signal with aid of the single ended receiving of the input stage for increasing a detection margin of the preamble;
wherein the backward clock signal from the memory is implemented as a set of differential data strobe signals, and the memory controller obtains a received data strobe signal through differential receiving, wherein the operation of sampling the backward clock signal is implemented by sampling the received data strobe signal; and the memory controller obtains another received data strobe signal through the single ended receiving of the input stage, wherein the other received data strobe signal carries the gating-related information.

US Pat. No. 9,219,897

IMAGE SENSING APPARATUS AND COLOR-CORRECTION MATRIX CORRECTING METHOD AND LOOK-UP TABLE ESTABLISHING METHOD

Faraday Technology Corp.,...

1. A color-correction matrix correcting method adapted to an image sensing apparatus, the method comprising:
calculating, by a color-correction circuit, a block statistics value corresponding to a block of pixels in an image sensor
array;

determining, by the color-correction circuit, a covariance value corresponding to a current gain value based on a look-up
table; and

correcting, by the color-correction circuit, a color-correction matrix corresponding to the block of pixels according to the
covariance value and the block statistics value.

US Pat. No. 9,052,730

CALIBRATION CIRCUIT FOR VOLTAGE REGULATOR

Faraday Technology Corp.,...

1. A voltage regulator calibration circuit, comprising:
a voltage regulator, regulating an output voltage according to a reference voltage and a feedback voltage, wherein the feedback
voltage is in direct proportion to the output voltage; and

a calibration unit, coupled to the voltage regulator, and generating a control code through a binary search according to the
output voltage and a target voltage, wherein the control code determines a proportion of the feedback voltage to the output
voltage, wherein the calibration unit comprises:

a comparator, coupled to the voltage regulator, comparing the output voltage with the target voltage, and outputting a bit
value according to a result of the comparison; and

a control unit, coupled to the comparator and a multiplexer, and generating the control code through the binary search according
to the bit value,

wherein a bit number of the control code is K, K is a predetermined positive integer, a first bit of the control code is a
least significant bit (LSB), a Kth bit of the control code is a most significant bit (MSB); the control unit receives a clock signal, sets the control code to
an initial value during a first cycle of the clock signal, and latches the bit value as a (K?i+2)th bit of the control code during an ith cycle of the clock signal, wherein i is an integer and satisfies 2<=i<=K+1,

wherein the control unit receives an activating signal, and the control unit comprises:
K+1 first data flip-flops, wherein a clock terminal of each of the first data flip-flops receives the clock signal, a data
terminal of the jth first data flip-flop is coupled to an output terminal of the (j+1)th first data flip-flop, j is an integer and satisfies 0<=j<=K?1, and the data terminal of the Kth first data flip-flop receives the activating signal; and

K+1 second data flip-flops, respectively corresponding to the K+1 first data flip-flops, wherein a data terminal of each of
the second data flip-flops receives the bit value, a setting terminal of each of the second data flip-flop is coupled to the
output terminal of the corresponding first data flip-flop, an output terminal of the jth second data flip-flop is coupled to a clock terminal of the (j+1)th second data flip-flop, and the control code is formed by outputs of the 1 st second data flip-flop to the Kth second data flip-flop.

US Pat. No. 9,054,821

APPARATUS AND METHOD FOR FREQUENCY LOCKING

Faraday Technology Corp.,...

1. A frequency locking apparatus, adapted to a transmission interface without a quartz oscillator, and comprising:
a phase-locked loop, receiving a radio frequency signal, and locking a phase and a frequency of the radio frequency signal
to generate a recovery clock signal and a received data;

a local clock generator, generating a local clock signal;
a data buffer unit, coupled to the phase-locked loop and the local clock generator, writing the received data into an elastic
buffer in the data buffer unit according to a frequency of the recovery clock signal, and reading the received data from the
elastic buffer according to a frequency of the local clock signal;

a control unit, coupled to the data buffer unit and the local clock generator, wherein the control unit reads a write-in address
and a read-out address in the elastic buffer, and sends a control signal to the local clock generator for adjusting the frequency
of the local clock signal according to a relationship between the write-in address and the read-out address,

wherein the control unit comprises a calibration mode, wherein when the control unit is in the calibration mode, the control
unit

a. determines whether the radio frequency signal is received, and activates accessing of the elastic buffer when the radio
frequency signal is received;

b. determines whether the elastic buffer is full or empty when a first timing value is smaller than a value X, and increases
a digital value in the control signal when the elastic buffer is full, and decreases the digital value in the control signal
when the elastic buffer is empty;

c. determines whether a multiplication of a second timing value and a period of the recovery clock signal reaches a spread
spectrum clock period, and resets the first timing value and repeats the step b when the multiplication of the second timing
value and the period of the recovery clock signal does not reach the spread spectrum clock period; and

d. stores the digital value and resets the second timing value to zero when the multiplication of the second timing value
and the period of the recovery clock signal reaches the spread spectrum clock period.

US Pat. No. 9,948,244

AMPLIFIER WITH ADJUSTABLE GAIN

Faraday Technology Corp.,...

1. An amplifier with adjustable gain, comprising:a plurality of differential amplifiers, each of the differential amplifiers having at least one differential pair and two transistor strings, wherein two current terminals of each of the at least one differential pair are coupled by a connection structure, and the connection structure provides a negative feedback resistance, the differential amplifiers commonly receive a differential input signal pair, output terminals of the differential amplifiers are coupled to each other, the two transistor strings are respectively coupled between two load terminals and the two current terminals of each of the at least one differential pair, and the two transistor strings are turned on or turned off according to a control signal and a reference voltage; and
an output stage circuit, coupled to the output terminals of the differential amplifiers, and inverting a voltage on the output terminals of the differential amplifiers to generate an output voltage,
wherein a direct current gain of the amplifier with adjustable gain is determined by adjusting at least one of working numbers of the differential amplifiers and the differential pairs.

US Pat. No. 9,342,087

VOLTAGE REGULATOR CIRCUIT

Faraday Technology Corp.,...

1. A voltage regulator circuit, comprising:
a main regulator, providing an output voltage, and regulating the output voltage according to the output voltage and a reference
voltage, the main regulator comprises:

a voltage divider, providing a feedback voltage according to the output voltage, wherein the feedback voltage is a voltage
division of the output voltage;

a first transistor, coupled between a power voltage and the voltage divider, and providing a branch current of the main regulator,
wherein a junction of the first transistor and the voltage divider provides the output voltage; and

a first operational amplifier, coupled to the voltage divider and the first transistor, and regulating the branch current
of the main regulator according to the feedback voltage and the reference voltage; and

at least one auxiliary regulator, coupled to the main regulator, providing the output voltage, and regulating the output voltage
according to the output voltage and the reference voltage, wherein each of the main regulator and the at least one auxiliary
regulator provides the branch current of a same magnitude, and an output current of the voltage regulator circuit comprises
the branch currents provided by the main regulator and the at least one auxiliary regulator, wherein each of the at least
one auxiliary regulator comprises:

a second transistor, coupled between the power voltage and the voltage divider, and providing the branch current of the corresponding
auxiliary regulator;

a second operational amplifier, coupled to the second transistor, and regulating the branch current of the corresponding auxiliary
regulator according to the feedback voltage and the reference voltage; and

a feedback unit, coupling the gate of the first transistor and a gate of the second transistor through a virtual short circuit,
and coupled to the voltage divider and the second operational amplifier, and regulating the feedback voltage and providing
the regulated feedback voltage to the second operational amplifier.

US Pat. No. 9,537,449

CRYSTAL OSCILLATION CIRCUIT, GAIN STAGE OF CRYSTAL OSCILLATION CIRCUIT AND METHOD FOR DESIGNING SAME

Faraday Technology Corp.,...

1. A gain stage of crystal oscillation circuit, comprising:
a substrate, having at least a first zone and a second zone;
a first N doped region, disposed in the first zone;
a plurality of first gates, disposed parallel on the first N doped region;
a plurality of first P+ doped regions, disposed in the first N doped region;
a plurality of second P+ doped regions, disposed in the first N doped region, wherein the first P+ doped regions serve as
sources of a plurality of first transistors respectively, the first gates serve as gates of the first transistors respectively,
and the second P+ doped regions serve as drains of the first transistors respectively;

a first P doped region, disposed in the second zone, wherein the first P doped region is parallel to the first N doped region;
a plurality of second gates, disposed parallel on the first P doped region;
a plurality of first N+ doped regions, disposed in the first P doped region;
a plurality of second N+ doped regions, disposed in the first P doped region, wherein the first N+ doped regions serve as
sources of a plurality of second transistors respectively, the second gates serve as gates of the second transistors respectively,
and the second N+ doped regions serve as drains of the second transistors respectively; and

a plurality of metal wires, disposed parallel on the first N doped region and the first P doped region, wherein each of the
metal wires is electrically coupled to the drain of at least one corresponding first transistor among the first transistors
and the drain of at least one corresponding second transistor among the second transistors.

US Pat. No. 9,509,286

DRIVING CIRCUIT, DRIVING APPARATUS, AND METHOD FOR ADJUSTING OUTPUT IMPEDANCE TO MATCH TRANSMISSION LINE IMPEDANCE BY USING CURRENT ADJUSTMENT

Faraday Technology Corp.,...

1. A driving circuit used in a transmission line, comprising:
an operational amplifier, configured for receiving a voltage signal to generate an output;
an output circuit, coupled to the operational amplifier, configured for receiving the output of the operational amplifier
and determining a current passing through the output circuit to generate an output signal of the driving circuit to thereby
adjust an output impedance of the driving circuit;

an error amplifier, having a first input terminal of the output circuit, a second input terminal coupled to a reference voltage,
and an output terminal; and

a controlling circuit, coupled to the output terminal of the error amplifier, configured for receiving an output of the error
amplifier to adjust the current passing through the output circuit to thereby adjust the output impedance of the driving circuit;

wherein the output impedance of the driving circuit is adjustable and determined by the current passing through the output
circuit; the reference voltage is inputted to the operational amplifier to be used as an input signal of the operational amplifier
when the controlling circuit adjusts the current passing through the output circuit.

US Pat. No. 9,466,357

CIRCUIT FOR MITIGATING WRITE DISTURBANCE OF DUAL-PORT SRAM

Faraday Technology Corp.,...

1. A dual-port static random access memory (SRAM), comprising:
a memory cell comprising a word line of a first port, a bit line of the first port, an inverse bit line of the first port,
a word line of a second port, a bit line of the second port, an inverse bit line of the second port, and a latching circuit,
wherein an output terminal of the latching circuit is coupled to the bit line of the first port, and the bit line of the second
port, and an inverse output terminal of the latching circuit is coupled to the inverse bit line of the first port, and the
inverse bit line of the second port; and

a circuit for mitigating write disturbance, comprising:
a first discharge control path including a transistor m1 and a transistor m2, wherein the transistor m1 includes a first terminal connected to the bit line of the second port and a control terminal connected to a first control
line, wherein the transistor m2 includes a first terminal connected to a second terminal of the transistor m1 and a second terminal connected to the bit line of the first port and a control terminal connected to the inverse bit line
of the first port, and wherein a first discharge current flowing from the bit line of the second port to a low level voltage
is generated when the bit line of the second port is at a high level voltage, the bit line of the first port is at the low
level voltage, and the first control line operates; and

a second discharge control path, connected to the inverse bit line of the second port, the inverse bit line of the first port,
and the first control line, wherein a second discharge current flowing from the inverse bit line of the second port to the
low level voltage is generated when the inverse bit line of the second port is at the high level voltage, the inverse bit
line of the first port is at the low level voltage, and the first control line operates.

US Pat. No. 9,432,046

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER

FARADAY TECHNOLOGY CORPOR...

1. A successive approximation analog-to-digital converter, comprising:
a first capacitance bank comprising j capacitors, wherein first terminal of the j capacitors of the first capacitance bank
are connected with a first node;

a second capacitance bank comprising (i+1) capacitors, wherein first terminals of the (i+1) capacitors of the second capacitance
bank are connected with a second node;

a bridge capacitor connected between the first node and the second node;
a switch set comprising a first group having j switch elements and a second group having (i+1) switch elements, wherein first
terminals of the j switch elements of the first group are respectively connected with second terminals of the j capacitors
of the first capacitance bank, and first terminals of the (i+1) switch elements of the second group are respectively connected
with second terminals of the (i+1) capacitors of the second capacitance bank, wherein the (i+j+1) switch elements are controlled
according to a switching signal, wherein each of second terminals of the j switch elements of the first group is selectively
connected with one of a low reference level, a high reference level, an input level and an intermediate level, wherein each
of second terminals of the (i+1) switch elements of the second group is selectively connected with one of the low reference
level, the high reference level, the input level and the intermediate level;

a comparator, wherein a first input terminal of the comparator is connected with the first node, a second input terminal of
the comparator directly receives the intermediate level, and an output terminal of the comparator generates a comparing signal;
and

a successive approximation register logic circuit receiving the comparing signal according to a clock signal, and generating
the switching signal and a digital data signal;

wherein the switch set further comprises a sampling switch element that is controlled according to the switching signal, wherein
a first terminal of the sampling switch element receives the intermediate level, and a second terminal of the sampling switch
element is connected with the first node.

US Pat. No. 9,403,228

METHOD AND APPARATUS FOR PULSED ELECTROCHEMICAL GRINDING

FARADAY TECHNOLOGY, INC.,...

1. A method for electromechanical grinding comprising:
rotating an electrically conductive grinding wheel;
applying a first voltage between the electrically conductive grinding wheel and an electrically conductive workpiece;
applying a first force vector towards the electrically conductive workpiece via the electrically conductive grinding wheel
to remove material from the electrically conductive workpiece; and

after removing a desired percentage of material from the electrically conductive workpiece: a) applying a second force vector
towards the electrically conductive workpiece, the second force vector being less than the first force vector, and b) applying
a second voltage between the electrically conductive grinding wheel and the electrically conductive workpiece to further remove
material from the electrically conductive workpiece.

US Pat. No. 9,971,369

VOLTAGE REGULATOR

Faraday Technology Corp.,...

1. A voltage regulator connected with an input/output circuit, the voltage regulator comprising:a controlling circuit generating a first reference voltage, a second reference voltage, a first power start control signal and a second power start control signal;
a sink voltage generator receiving the first reference voltage and the first power start control signal; and
a source voltage generator receiving the second reference voltage and the second power start control signal,
wherein when the voltage regulator is in a normal working state, the controlling circuit inactivates the first power start control signal and the second power start control signal, the sink voltage generator generates a sink voltage according to the first reference voltage, and the source voltage generator generates a source voltage according to the second reference voltage.

US Pat. No. 9,806,923

RXLOS DEGLITCH APPARATUS AND METHOD

Faraday Technology Corp.,...

1. A RXLOS deglitch apparatus for a receiver, the RXLOS deglitch apparatus comprising:
a sampler receiving a recovered clock, and sampling a RXLOS signal according to the recovered clock, thereby generating a
sampled RXLOS signal;

an edge detecting unit receiving the RXLOS signal, wherein the edge detecting unit includes at least one D flip-flop having
a signal input terminal receiving a first logic level and a clock terminal receiving the RXLOS signal or an inverted RXLOS
signal, and when a logic level of the RXLOS signal is changed, an edge detection signal is activated by the edge detecting
unit; and

a finite state machine receiving the edge detection signal and the sampled RXLOS signal, generating an edge rest signal to
control the edge detecting unit, and outputting a filtered RXLOS signal.

US Pat. No. 9,773,534

NON-VOLATILE MEMORY ACCELERATOR AND METHOD FOR SPEEDING UP DATA ACCESS

Faraday Technology Corp.,...

1. A non-volatile memory accelerator comprising:
a data pre-fetching unit having a plurality of line buffers, one of the line buffers providing read data according to a read
command, or the data pre-fetching unit reading at least one cache data as the read data according to the read command, the
data pre-fetching unit further storing in at least one of the line buffers a plurality of pre-stored data with continuous
addresses according to the read command;

a cache unit coupled to the data pre-fetching unit and configured to store the at least one cache data and the pre-stored
data with the continuous addresses; and

an access interface circuit coupled to the data pre-fetching unit, the cache unit, and a non-volatile memory, the access interface
circuit acting as an interface circuit of the non-volatile memory,

wherein the data pre-fetching unit searches data stored in the line buffers according to the read command, if the line buffers
include required data corresponding to the read command, the required data stored in one of the line buffers is provided as
the read data, if the line buffers do not include the required data corresponding to the read command, the data pre-fetching
unit searches whether the cache unit includes the required data, and if the cache unit includes the required data, the data
pre-fetching unit reads the required data stored in the cache unit as the read data.

US Pat. No. 10,027,330

ARBITRATING CIRCUIT

Faraday Technology Corp.,...

1. An arbitrating circuit, comprising:a first NOR gate, wherein a first input terminal of the first NOR gate receives a first request signal, a second input terminal of the first NOR gate is connected with a first node, and an output terminal of the first NOR gate is connected with a second node;
a second NOR gate, wherein a first input terminal of the second NOR gate receives a second request signal, a second input terminal of the second NOR gate is connected with the second node, and an output terminal of the second NOR gate is connected with the first node;
a first transistor, wherein a source terminal of the first transistor is connected with the first node, a gate terminal of the first transistor is connected with the second node, and a drain terminal of the first transistor generates a first acknowledging signal;
a second transistor, wherein a source terminal of the second transistor is connected with a supply voltage, a gate terminal of the second transistor is connected with the second node, and a drain terminal of the second transistor is connected with the drain terminal of the first transistor;
a third transistor, wherein a source terminal of the third transistor is connected with the second node, a gate terminal of the third transistor is connected with the first node, and a drain terminal of the third transistor generates a second acknowledging signal;
a fourth transistor, wherein a source terminal of the fourth transistor is connected with the supply voltage, a gate terminal of the fourth transistor is connected with the first node, and a drain terminal of the fourth transistor is connected with the drain terminal of the third transistor; and
a pull-up circuit connected with the first node, the second node, the first input terminal of the first NOR gate and the first input terminal of the second NOR gate,
wherein if both of the first request signal and the second request signal have a low logic level, a voltage at the second node is pulled up to a high logic level by the pull-up circuit.

US Pat. No. 10,009,017

ON-CHIP APPARATUS AND METHOD FOR JITTER MEASUREMENT

Faraday Technology Corp.,...

1. An apparatus for jitter measurement comprising:a first delay circuit, arranged to use at least one delay element of the first delay circuit to preliminarily adjust a phase delay of an input signal for generating a delayed input signal;
a second delay circuit, coupled to the first delay circuit, for operating with the first delay circuit to receive the delayed input signal from the first delay circuit, and for fine tuning the phase delay of the delayed input signal by using at least one delay element of the second delay circuit to delay the delayed input signal; and
a control circuit, coupled to the first delay circuit and the second delay circuit, for controlling and adjusting amounts of delays of the first and the second delay circuits, fine tuning an amount of delay of the delayed input signal according to a unit delay of the at least one delay element of the first delay circuit and a unit delay of the at least one delay element of the second delay circuit, and estimating or calculating an amount of jitter of the input signal according to an adjustment result of the first delay circuit and an adjustment result of the second delay circuit.

US Pat. No. 9,965,430

INTEGRATED CIRCUIT AND OPERATION METHOD OF SERIALIZER/DESERIALIZER PHYSICAL LAYER CIRCUIT THEREOF

Faraday Technology Corp.,...

6. An integrated circuit, comprising:a first reference resistor pad, configured to electrically connect a reference resistor located outside the integrated circuit;
an upper layer circuit;
a first serializer/deserializer physical layer circuit, having a data pin electrically coupled to the upper layer circuit, and configured to transform first parallel data output by the upper layer circuit into first serial data, or transform second serial data into second parallel data for providing to the upper layer circuit, wherein the first serializer/deserializer physical layer circuit further has a reference resistor pin, a first calibration input pin and a first calibration output pin, the reference resistor pin is electrically connected to the first reference resistor pad, the first serializer/deserializer physical layer circuit enters a calibration state from a calibration preparation state so as to perform current calibration by using the reference resistor electrically connected to the first reference resistor pad when the first serializer/deserializer physical layer circuit is in the calibration preparation state and a signal of the first calibration input pin is in an enable state, the first serializer/deserializer physical layer circuit enters a calibration completion state from the calibration state to stop using the reference resistor and electrically connect the first calibration input pin to the first calibration output pin after the current calibration is completed, and the first serializer/deserializer physical layer circuit does not electrically connect the first calibration input pin to the first calibration output pin and sets a signal of the first calibration output pin to a disable state when the first serializer/deserializer physical layer circuit is not in the calibration completion state;
a second reference resistor pad, configured to electrically connect the reference resistor located outside the integrated circuit;
a second serializer/deserializer physical layer circuit, having a data pin electrically coupled to the upper layer circuit, and configured to transform third parallel data output by the upper layer circuit into third serial data, or transform fourth serial data into fourth parallel data for providing to the upper layer circuit, wherein the second serializer/deserializer physical layer circuit further has a reference resistor pin, a first calibration input pin and a first calibration output pin; and
an arbiter, coupled to the first calibration input pin of the first serializer/deserializer physical layer circuit, the first calibration output pin of the first serializer/deserializer physical layer circuit, the first calibration input pin of the second serializer/deserializer physical layer circuit and the first calibration output pin of the second serializer/deserializer physical layer circuit, wherein the arbiter provides an enable state signal to the first calibration input pin of the first serializer/deserializer physical layer circuit during to a first period to trigger the first serializer/deserializer physical layer circuit to enter the calibration state, the arbiter ends the first period when the signal of the first calibration output pin of the first serializer/deserializer physical layer circuit is in the enable state, the arbiter provides an enable state signal to the first calibration input pin of the second serializer/deserializer physical layer circuit during to a second period to trigger the second serializer/deserializer physical layer circuit to enter the calibration state, and the arbiter ends the second period when a signal of the first calibration output pin of the second serializer/deserializer physical layer circuit is in the enable state.

US Pat. No. 9,673,808

POWER ON-RESET CIRCUIT

Faraday Technology Corp.,...

1. A power-on-reset circuit, adapted to generate a reset signal in the beginning of power-on, the power-on-reset circuit comprising:
a first diode-connected transistor, having an anode and a cathode, wherein the cathode of the first diode-connected transistor
is coupled to a reference voltage;

a first resistor, having a first end and a second end, wherein the first end of the first resistor is coupled to a power voltage,
and the second end of the first resistor is directly coupled to the anode of the first diode-connected transistor;

a second diode-connected transistor, having an anode and a cathode, wherein the cathode of the second diode-connected transistor
is coupled to the reference voltage, and the anode of the second diode-connected transistor is directly coupled to the first
end of the first resistor; and

a current comparator circuit, coupled to the first diode-connected transistor and the second diode-connected transistor, and
comparing a current of the first diode-connected transistor and a current of the second diode-connected transistor to obtain
a comparing result, wherein the comparing result determines the reset signal.

US Pat. No. 9,753,515

ANTI-DEADLOCK CIRCUIT FOR VOLTAGE REGULATOR AND ASSOCIATED POWER SYSTEM

Faraday Technology Corp.,...

1. A power system, comprising:
a voltage regulator connected with an external voltage source, and receiving a control signal, wherein when the voltage regulator
is enabled by the control signal, the voltage regulator generates an output voltage and a proportional voltage, wherein when
the voltage regulator is disabled by the control signal, the voltage regulator stops generating the output voltage and the
proportional voltage, wherein there is a fixed ratio between the output voltage and the proportional voltage;

a digital circuit connected with the voltage regulator, wherein when the digital circuit receives the output voltage, the
digital circuit is operated, wherein when the digital circuit is not operated, an power down signal is activated; and

an anti-deadlock circuit comprises: a voltage detecting circuit receiving the proportional voltage, wherein if the proportional
voltage is higher than a threshold voltage, a notice signal is activated; a latching circuit connected with the voltage detecting
circuit, wherein when the notice signal is inactivated, a latched signal outputted from the latching circuit has a first voltage
level, wherein when the notice signal is activated, the latched signal outputted from the latching circuit has a second voltage
level; and a controlling circuit connected with the latching circuit and the digital circuit, and receiving the power down
signal;

wherein if the latched signal has the first voltage level, the controlling circuit uses the control signal to enable the voltage
regulator, wherein if the latched signal has the second voltage level and the power down signal is inactivated, the controlling
circuit uses the control signal to enable the voltage regulator, wherein if the latched signal has the second voltage level
and the power down signal is activated, the controlling circuit uses the control signal to disable the voltage regulator.

US Pat. No. 9,987,699

ELECTROCHEMICAL SYSTEM AND METHOD FOR ELECTROPOLISHING HOLLOW METAL BODIES

FARADAY TECHNOLOGY, INC.,...

1. A method for electrochemically machining a hollow body of a metal or metal alloy, the method comprising:positioning an electrode within a hollow body comprising a metal or metal alloy, wherein the hollow body has a variable internal diameter;
orienting the hollow body vertically, with the electrode oriented vertically therein;
at least partially filling the hollow body with an aqueous, acidic electrolyte solution, the electrolyte solution being devoid of hydrofluoric acid and having a viscosity less than 15 cP; and
passing an electric current between the hollow body and the electrode, wherein the electric current is comprised of a plurality of anodic pulses and a plurality of cathodic pulses, and wherein the cathodic pulses are interposed between at least some of the anodic pulses, and
wherein the hollow body and electrode do not rotate during the passing as electric current step.

US Pat. No. 9,938,632

APPARATUS AND METHOD FOR RECOVERY OF MATERIAL GENERATED DURING ELECTROCHEMICAL MATERIAL REMOVAL IN ACIDIC ELECTROLYTES

FARADAY TECHNOLOGY, INC.,...

1. A method for recycling metallic material produced by an electrochemical material removal process, the method comprising the steps of:flowing an electrolyte solution between an anode workpiece and a cathode tool in a first electrolytic process, the first electrolytic process comprising applying a first electrolytic current and voltage between the anode workpiece and the cathode tool and thereby causing metal ions to be removed from the anode workpiece and dissolved and substantially retained in the electrolyte solution;
flowing the electrolyte solution with the metal ions therein between an electrowinning cathode and an electrowinning anode in a second electrolytic process, the second electrolytic process comprising applying a second electrolytic current and voltage comprising a pulsed current and voltage between the electrowinning cathode and the electrowinning anode and thereby causing the metal ions to be removed from the electrolyte solution and deposited onto the electrowinning cathode; and
adjusting the second pulsed voltage waveform of the second electrolytic process to cause the rate at which the dissolved metal ions are deposited onto the electrowinning cathode to be approximately equal to the rate at which metal ions are removed from the anode workpiece during the first electrolytic process.

US Pat. No. 10,214,832

APPARATUS FOR RECOVERY OF MATERIAL GENERATED DURING ELECTROCHEMICAL MATERIAL REMOVAL IN ACIDIC ELECTROLYTES

FARADAY TECHNOLOGY, INC.,...

1. A system for recycling machined metal produced by an electrochemical material removal process, the system comprising:a machining unit comprising an anode to receive a workpiece, a cathode tool, and a first pulse generator to provide a voltage or current waveform between the anode and the cathode tool; and
an electrowinning unit comprising an electrowinning cathode, an electrowinning anode, and a second pulse generator to provide a voltage or current waveform between the electrowinning anode and the electrowinning cathode;
wherein the machining unit is in fluid communication with the electrowinning unit.

US Pat. No. 10,100,423

ELECTRODEPOSITION OF CHROMIUM FROM TRIVALENT CHROMIUM USING MODULATED ELECTRIC FIELDS

FARADAY TECHNOLOGY, INC.,...


US Pat. No. 10,268,226

VOLTAGE GENERATING DEVICE AND CALIBRATING METHOD THEREOF

Faraday Technology Corp.,...

1. A voltage generating device, comprising:a bandgap circuit, comprising a chopper amplifier and at least one bandgap circuit resistor, wherein the bandgap circuit provides a bandgap voltage;
a regulator circuit, coupled to the bandgap circuit to receive the bandgap voltage, generating an output voltage correspondingly according to the bandgap voltage, wherein the regulator circuit comprises at least one regulator resistor; and
a calibrating circuit, coupled to the bandgap circuit to receive the bandgap voltage, coupled to the regulator circuit to receive the output voltage, wherein
in a first stage of a calibration period, the calibrating circuit detects the bandgap voltage and correspondingly sets a resistance of at least one resistor among the at least one bandgap circuit resistor according to the bandgap voltage, and
in a second stage of the calibration period, the calibrating circuit detects the output voltage and correspondingly sets a resistance of at least one resistor among the at least one regulator resistor according to the output voltage;
wherein the calibrating circuit provides a clock signal to the chopper amplifier in the first stage of the calibration period, and the calibrating circuit does not provide the clock signal to the chopper amplifier in the second stage of the calibration period and a normal operation period.