US Pat. No. 9,525,424

METHOD FOR ENHANCING TEMPERATURE EFFICIENCY

ELITE SEMICONDUCTOR MEMOR...

1. A method for enhancing temperature efficiency, comprising:
generating a PTAT current by using a bandgap circuit;
generating a CTAT current by using the bandgap circuit;
generating an output current, wherein the output current equals to the PTAT current minus the CTAT current; and
providing the output current to an oscillator for generating an oscillating frequency;
wherein the bandgap circuit comprises:
a current generating circuit, used to generate the PTAT current and the CTAT current; and
an output circuit, comprising a plurality of transistors, and connected to the current generating circuit for receiving the
PTAT current and the CTAT current so as to generate the output current;

wherein the current generating circuit comprises:
a plurality of current mirrors, connected to a fixed voltage source; and
at least one amplifier, connected to a current mirror, configured to output the PTAT current and the CTAT current;
wherein the current generating circuit further comprises a level control unit, wherein the level control unit comprises a
plurality of transistors, and each of the transistors is connected to one of the current mirrors and one of the amplifiers
so as to control levels of the PTAT current and the CTAT current.

US Pat. No. 9,413,347

DUTY CYCLE CORRECTION APPARATUS

ELITE SEMICONDUCTOR MEMOR...

1. A duty cycle correction apparatus, comprising:
a first duty cycle corrector, receiving complementary external clocks to generate complementary first internal clocks;
a pump circuit, electrically connected to the first duty cycle corrector, receiving the first internal clocks to generate
complementary feedback clocks to the first duty cycle corrector to adjust duty cycles of the first internal clocks;

a phase detection apparatus, electrically connected to the first duty cycle corrector, being activated while the duty cycle
of the first internal clock is adjusted to a specific duty cycle, receiving the external clocks to generate complementary
second internal clocks, selecting the first internal clock as a reference clock, and comparing phases of the second internal
clock and the reference clock to generate a phase detection signal;

a comparator, electrically connected to the pump circuit for receiving the feedback clocks to generate a comparison signal;
a counter, electrically connected to the comparator through a first switch for receiving the comparison signal and the phase
detection apparatus through a second switch for receiving the phase detection signal, to generate complementary digital signals;
and

a digital-analog converter, electrically connected to the counter, for receiving the complementary digital signals to generate
complementary signals to the phase detection apparatus to adjust duty cycles of the second internal clocks;

wherein the duty cycle correction apparatus records codes of the complementary signals which make the duty cycle of the second
internal clock equal to the specific duty cycle, and after the codes are recorded, the phase detection apparatus is inactivated.

US Pat. No. 9,373,378

SEMICONDUCTOR DEVICE FOR DRIVING SUB WORD LINES

Elite Semiconductor Memor...

1. A semiconductor device, comprising:
a selected sub word line driver having an input node connected to a selected main word line, an output node connected to a
selected sub word line, a reference node supplied with a common reference voltage, and a power node;

a first voltage switching circuit configured to selectively supply one of a first power voltage, a second power voltage, and
the common reference voltage to the power node of the selected sub word line driver;

wherein, in an active mode, the first voltage switching circuit supplies the first power voltage to the power node of the
selected sub word line driver to pull the selected sub word line to a logic high level;

wherein, in a precharge mode, the first voltage switching circuit supplies the common reference voltage to the power node
of the selected sub word line driver and then supplies the second power voltage to the power node of the selected sub word
line driver, thereby pulling the selected sub word line to a logic low level; and

wherein a voltage level of the second power supply node is lower than a voltage level of the first power voltage and higher
than a voltage level of the common reference voltage.

US Pat. No. 9,147,444

VOLTAGE REGULATOR

ELITE SEMICONDUCTOR MEMOR...

1. A voltage regulator, comprising:
an over-drive circuit, for receiving a first voltage signal output from a sensing amplifier in a DRAM circuit, and regulating
the first voltage signal according to an over-drive signal; and

a control circuit, electrically connected to the over-drive circuit, for receiving a sense signal, and outputting the over-drive
signal according to the sense signal, wherein the sense signal is asserted when a bit line in the DRAM circuit is sensed that
an restoring operation is performed;

wherein the over-drive signal goes down to a level of a second voltage signal from a current level thereof dependent on an
external power merely when the sense signal is asserted but has not been asserted for a delay time, or otherwise, the over-drive
signal is equal to the external power;

wherein the over-drive circuit comprising:
a voltage divider, for outputting a divided voltage signal according to the first voltage signal;
a comparator, for comparing the divided voltage signal and a reference voltage signal to output a comparison signal;
a first PMOS transistor, a gate thereof receives the comparison signal, a source thereof is electrically connected to the
external power, and a drain thereof is electrically connected to the first voltage signal; and

a second PMOS transistor, a gate thereof receives the over-drive signal, a source thereof is electrically connected to the
external power, and a drain thereof is electrically connected to the first voltage signal.

US Pat. No. 9,141,124

BANDGAP REFERENCE CIRCUIT

Elite Semiconductor Memor...

1. A bandgap reference circuit, comprising:
first, second, and third current sources;
an operational amplifier coupled to the first, second and the third current sources;
a first bipolar transistor having a base, an emitter, and a collector, the emitter coupled to the first current source, the
base and the collector coupled to a ground voltage;

a voltage divider coupled between the emitter and the base of the first bipolar transistor, wherein the voltage divider provides
first and second voltages proportional to a base-emitter voltage of the first bipolar transistor;

a second bipolar transistor having a base, an emitter, and a collector, the base configured to receive the first voltage,
the emitter coupled to the second current source, and the collector coupled to the ground voltage;

a third bipolar transistor having a base, an emitter, and a collector, the base configured to receive the second voltage,
and the collector coupled to the ground voltage; and

a first resistor coupled between the third current source and the emitter of the third bipolar transistor.

US Pat. No. 9,298,557

METHOD OF BOOTING SYSTEM HAVING NON-VOLATILE MEMORY DEVICE WITH ERASE CHECKING AND CALIBRATION MECHANISM AND RELATED MEMORY DEVICE

Elite Semiconductor Memor...

1. A method of booting a system with a non-volatile memory device, comprising:
when the system is powered on, reading a status flag of at least a memory block of the non-volatile memory device, wherein
the status flag indicates whether an erase operation applied to the memory block is successfully completed;

determining whether to perform a leakage calibration process upon the memory block according to a status of the status flag;
and

booting the system according to a boot code stored in the non-volatile memory device.

US Pat. No. 9,300,281

TRIANGULAR WAVE GENERATING CIRCUIT TO PROVIDE CLOCK SYNCHRONIZATION

Elite Semiconductor Memor...

1. A triangular wave generating circuit, comprising:
a capacitor having an output for providing a triangular wave signal;
first and second constant current sources configured to charge the capacitor;
third and fourth constant current sources configured to discharge the capacitor;
a first switching unit comprising a first switch and a second switch, the first switching unit configured to couple the first
and third constant current sources to the capacitor in response to an internal clock signal;

a high/low level limiter comprising first and second comparing units, the first comparing unit configured to compare the triangular
wave signal with an upper limit reference voltage and generate an output signal when the triangular wave signal coincides
with the upper limit reference voltage, the second comparing unit configured to compare the triangular wave signal with a
lower limit reference voltage and generate an output signal when the triangular wave signal coincides with the lower limit
reference voltage;

a clock generator configured to generate the internal clock signal in response to the output signals from the first and second
comparing units;

a phase detecting unit configured to compare an externally supplied clock signal with the internal clock signal and generate
a first phase signal and a second phase signal base on a phase difference between the externally supplied clock signal and
the internal clock signal; and

a second switching unit comprising a third switch and a fourth switch, the third switch configured to couple the second constant
current source to the capacitor in response to the first phase signal, the fourth switch configured to couple the fourth constant
current source to the capacitor in response to the second phase signal.

US Pat. No. 9,325,283

MODULATION METHOD FOR SWITCHING MODULATOR

ELITE SEMICONDUCTOR MEMOR...

1. A modulation method for a switching modulator, comprising:
receiving a data signal;
generating a first output signal at a first output side of the switching modulator and a second output signal at a second
output side of the switching modulator according to the data signal received, wherein the first output signal is an addition
signal of a first pulse signal and the data signal, the second output signal is a second pulse signal, centers of the first
and the second pulse signals are aligned to each other, the first pulse and the second signals have a pulse width, and the
pulse width equals to a minimum resolution of the switching modulator, wherein the minimum resolution of the switching modulator
is 1/(fpwM*2N), wherein fPwM is a frequency of the data signal presented as a pulse width modulation signal, and N is a bit number of the data signal.

US Pat. No. 9,300,276

OSCILLATION CONTROL CIRCUIT FOR BIASING RING OSCILLATOR BY BANDGAP REFERENCE SIGNAL AND RELATED METHOD

Elite Semiconductor Memor...

1. An oscillation control circuit for a ring oscillator, comprising:
a bandgap reference circuit, for generating a bandgap reference signal by mirroring a proportional-to-absolute-temperature
current; and

an oscillation frequency control circuit, coupled to the bandgap reference circuit, for biasing the ring oscillator according
to the bandgap reference signal;

wherein the bandgap reference circuit comprises:
a first transistor, having a first connection node, a second connection node and a control node, the first connection node
of the first transistor being coupled to a first reference voltage, the control node of the first transistor being coupled
to a current source providing the proportional-to-absolute-temperature current and the first transistor mirrors the proportional-to-absolute-temperature
current to generate a first current;

a second transistor, having a first connection node, a second connection node and a control node, the first connection node
of the second transistor being coupled to the second connection node of the first transistor, and the control node of the
second transistor being coupled to the first connection node of the second transistor;

a third transistor, having a first connection node, a second connection node and a control node, the first connection node
of the third transistor being coupled to the first reference voltage, and the second connection node of the third transistor
being coupled to the control node of the third transistor;

a resistor, having a first end and a second end, the first end of the resistor being coupled to the second connection node
of the third transistor; and

a fourth transistor, having a first connection node, a second connection node and a control node, the first connection node
of the fourth transistor being coupled to the second end of the resistor, the second connection node of the fourth transistor
being coupled to a second reference voltage, and the control node of the fourth transistor being coupled to the control node
of the second transistor to mirror the first current flowing through the second transistor to generate a second current, wherein
the bandgap reference circuit generates the bandgap reference signal according to the second current, and the first transistor
and the fourth transistor have conductive channels of different types.

US Pat. No. 9,229,059

MEMORY TEST SYSTEM AND METHOD

ELITE SEMICONDUCTOR MEMOR...

1. A memory test system, comprising:
a memory device, comprising a memory die with a plurality of memory banks, a plurality of input circuits, and a plurality
of output circuits, wherein each of the input circuits has a first input pin and a second pin, the first input pins of the
input circuits are used to read a plurality of patches of data stored in memory cells of the memory banks, and the second
input pins are used to receive a compressed result;

a probe card, electrically connected to the output circuits; and
a tester, electrically connected to the probe card;
wherein the output circuits receive compressed signals output from the input circuits, and the probe card mixes compressed
output signals output from the output circuits to output a mixed compressed output signal to the tester.

US Pat. No. 9,378,822

METHOD FOR PROGRAMMING SELECTED MEMORY CELLS IN NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE THEREOF

ELITE SEMICONDUCTOR MEMOR...

9. An nonvolatile memory device, comprising:
a memory array, comprising a plurality of memory cells; and
a bit line decoder and a word line decoder, electrically connected to the memory array;
a first high voltage generator, electrically connected to the word line decoder, the first high voltage generator provides
a first word line programming signal being at plurality of voltage levels in different programming slots of a current programming
operation to the memory cells of the selected word line, wherein the first word line programming signal is a ramping voltage
signal; and then the first high voltage generator provides a second word line programming signal being at plurality of voltage
levels in different programming slots of a next programming operation to the memory cells of the selected word line, wherein
the second word line programming signal is another one ramping voltage signal; and

a second high voltage generator, electrically connected to the bit line decoder, outputting a bit line programming voltage,
and the bit line decoder outputs the bit line programming voltage as at least of bit line signals;

wherein a highest voltage level of the first word line programming signal is the same as that of the second word line programming
signal, and a number of the voltage levels of the first word line programming signal is larger than that of the second word
line programming signal.

US Pat. No. 9,117,546

METHOD FOR AUTO-REFRESHING MEMORY CELLS IN SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE USING THE METHOD

ELITE SEMICONDUCTOR MEMOR...

1. A method for auto-refreshing memory cells in a semiconductor memory device with an open bit line architecture, wherein
the semiconductor memory device comprises M memory banks, and each of the M memory banks has two particular sectors with a
same index and L remained sectors with different indices, and the method comprises:
selecting two word lines of the two particular sectors with the same index in the memory bank and (M?1) word lines of the
L remained sectors respectively in the other (M?1) memory banks in one cycle; and

refreshing the memory cells of the selected word lines.

US Pat. No. 9,859,894

LEVEL SHIFTING CIRCUIT AND INTEGRATED CIRCUIT

ELITE SEMICONDUCTOR MEMOR...

1. A level shifting circuit, comprising:
a first N-type metal-oxide-semiconductor (NMOS) transistor having a gate end for receiving a first input voltage, a source
end connected to a first logic low level, and a drain end;

a second NMOS transistor having a gate end for receiving a second input voltage, a source end connected to the first logic
low level, and a drain end, wherein the second input voltage is an inversion of the first input voltage;

a third NMOS transistor having a gate end connected to a first logic high level, a source end connected to the drain end of
the first NMOS transistor, and a drain end;

a fourth NMOS transistor having a gate end connected to the first logic high level, a source end connected to the drain end
of the second NMOS transistor, and a drain end;

a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate end, a source end connected to a second logic high
level, and a drain end;

a second PMOS transistor having a gate end, a source end connected to the second logic high level, and a drain end, wherein
the drain end of the second PMOS transistor is connected to the gate end of the first PMOS transistor and used to deliver
a first output voltage, the drain end of the first PMOS transistor is connected to the gate end of the second PMOS transistor
and used to deliver a second output voltage, and the second output voltage is an inversion of the first output voltage;

a third PMOS transistor having a gate end for receiving the second input voltage, a source end connected to the drain end
of the first PMOS transistor, and a drain end connected to the drain end of the third NMOS transistor;

a fourth PMOS transistor having a gate end for receiving the first input voltage, a source end connected to the drain end
of the second PMOS transistor, and a drain end connected to the drain end of the fourth NMOS transistor;

a fifth PMOS transistor having a gate end for receiving the second output voltage, a source end connected to the second logic
high level, and a drain end for delivering a third output voltage;

a fifth NMOS transistor having a gate end for receiving the second input voltage, a source end connected to the first logic
low level, and a drain end; and

a sixth PMOS transistor having a gate end, a source end connected to the drain end of the fifth PMOS transistor, and a drain
end connected to the gate end of the sixth PMOS transistor and the drain end of the fifth NMOS transistor.

US Pat. No. 9,275,691

PROGRAMMABLE VOLTAGE GENERATOR FOR NONVOLATILE MEMORY DEVICE

ELITE SEMICONDUCTOR MEMOR...

1. A programming voltage generator for a nonvolatile memory device, comprising:
a power circuit, for outputting a programming voltage according to a voltage control signal;
a detector, for detecting whether the programming voltage is larger than or equal to a breakdown voltage of the nonvolatile
memory device, so as to output an indication signal;

a switching circuit, for temporally dropping the programming voltage according to the indication signal;
a control signal generator, for generating a plurality of regulation control signals; and
a regulation circuit, for generating the voltage control signal according to the programming voltage and the regulation control
signals;

wherein the regulation circuit comprises:
a programmable voltage divider, for generating a divided voltage according to the programming voltage and the regulation control
signals; and

a comparator, for comparing the divided voltage and a reference voltage to output the voltage control signal.

US Pat. No. 9,654,068

QUATERNARY/TERNARY MODULATION SELECTING CIRCUIT AND ASSOCIATED METHOD

Elite Semiconductor Memor...

1. A quaternary/ternary modulation selecting circuit of an audio amplifier, comprising:
a signal generating circuit, for generating a ternary signal and a quaternary signal;
a pulse generating circuit, arranged to generate a plurality of pulses with fixed duty cycles; and
a selecting circuit arranged to select one of the quaternary signal, the ternary signal and the plurality of pulses for an
output stage of the audio amplifier.

US Pat. No. 9,575,114

TEST SYSTEM AND DEVICE

Elite Semiconductor Memor...

1. A test system for performing a wafer level burn-in testing, comprising:
a probe card, comprising:
m (m is a positive integer) first signal contacts for receiving m test signals from m first test channels of a tester;
n (n is a positive integer) second signal contacts for providing n test results to n second test channels of the tester; and
a contact array comprising (m+1) rows and n columns, each row having n contacts and each column having (m+1) contacts, wherein
each one of the contacts in a first row is electrically coupled to a respective one of the n second signal contacts, and each
one of the contacts in the ith row is electrically coupled to a respective one of the m first signal contacts, wherein i is
an integer and 2?i?(m+1); and

n chips, each one of the chips comprising:
m input pads, wherein each one of the input pads receives a respective one of the m test signals from the tester through the
m contacts in a respective one of the n columns of the contact array;

a detection circuit for receiving signals from the m input pads to generate an output signal at a check pad; and
the check pad for providing one of the n test results to the tester through one contact in a respective one of the n columns
of the contact array.

US Pat. No. 9,484,117

SEMICONDUCTOR MEMORY DEVICE HAVING COMPRESSION TEST MODE

Elite Semiconductor Memor...

1. A semiconductor memory device comprising:
a memory unit comprising m memory banks divided into n activating groups, the memory banks in one of the n activating groups
are activated simultaneously, wherein each memory bank comprises a plurality of sensing amplifiers for sensing and amplifying
data in bit lines;

i test pads;
a timing circuit to sequentially generate n control signals each for activating a plurality of sensing amplifiers in one of
the n activating groups;

a compression circuit to compress data sensed and amplified by the plurality of sensing amplifiers in each memory bank in
a compression test mode; and

a signal distribution circuit to distribute signals output from the compression circuit among the i test pads in rotation;
wherein m is a positive integer, n is a positive integer having a value of 1 or greater, and i is a positive integer having
a value of 1 or greater,

wherein when the number of the memory banks in one of the n activating groups is greater than 1, the i test pads generate
one-bit compress-data of the memory banks in the one of the n activating groups simultaneously, and

wherein when the number of the memory banks in one of the n activating groups is equal to 1, each of the i test pads generates
one-bit compress-data of the one memory bank in the one of the n activating groups by delaying a corresponding control signal
at different clock cycles.

US Pat. No. 9,118,320

INPUT BUFFER WITH CURRENT CONTROL MECHANISM

Elite Semiconductor Memor...

1. An input buffer, comprising:
a first driving circuit, arranged for receiving a first input signal to generate an output signal;
a second driving circuit, arranged for driving the output signal;
a pull up circuit, arranged for selectively controlling the second driving circuit to pull up the output signal according
to the first input signal and a second input signal; and

a pull down circuit, arranged for selectively controlling the second driving circuit to pull down the output signal according
to the first input signal and the second input signal;

wherein the second driving circuit comprises:
a first transistor, having a first terminal, a second terminal, and a third terminal, wherein the first terminal is coupled
to a first reference voltage, the second terminal is coupled to the pull up circuit, and the third terminal is coupled to
the output signal; and

a second transistor, having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the second
transistor is coupled to the output signal, the second terminal of the second transistor is coupled to the pull down circuit,
and the third terminal of the second transistor is coupled to a second reference voltage.

US Pat. No. 9,082,511

REDUNDANCY EVALUATION CIRCUIT FOR SEMICONDUCTOR DEVICE

ELITE SEMICONDUCTOR MEMOR...

1. A redundancy evaluation circuit, comprising:
(m+1) fuse boxes, wherein m is a bit number of a defective element address signal, and each of the fuse boxes comprises:
a common stage circuit, having a precharge transistor and an inverted latch, wherein the precharge transistor is controlled
by a precharge signal to pull up a common node to a logic high level, and the inverted latch outputs an inversion of a level
at the common node; and

k redundant cells, each redundant cell has a transistor and a fuse, wherein a first and second ends of the transistor is connected
to the common node and a low reference voltage through the fuse respectively, a gate of the transistor receive one of k selection
signals, wherein k is a number of circuit blocks; and

a comparator, enabled by a comparator enable signal, comparing a fuse status address signal and a defective element address
signal to generate a redundancy enable signal, wherein the m fuse boxes output the m inversions of the m levels at the m common
nodes thereof as the fuse status address signal, and the other one fuse box output the inversion of the level at the common
node thereof as the comparator enable signal; and

a control logic circuit, receiving an enable signal to generate the precharge signal to turn on the precharge transistors
to pull up the common nodes of the (m+1) fuse boxes to the logic high level, then turn off the precharge transistors, and
generate an evaluation enable signal; and

a decoder, enabled by the evaluation enable signal, decoding a circuit block address signal to output the k selection signal,
wherein the circuit block address signal has n bits, and 2n-1

US Pat. No. 9,600,013

BANDGAP REFERENCE CIRCUIT

ELITE SEMICONDUCTOR MEMOR...

1. A bandgap reference circuit, comprising:
a first amplifier having a first input, a second input and a first output;
a second amplifier having a third input, a fourth input and a second output;
a first current source coupled between a power supply node and the first input of the first amplifier;
a second current source coupled between the power supply node and the second input of the first amplifier;
a third current source coupled between the power supply node and the third input of the second amplifier;
a first bipolar transistor having a base, an emitter coupled to the first current source, and a collector coupled to a ground
voltage;

a second bipolar transistor having a base coupled to the base of the first bipolar transistor, an emitter, and a collector
coupled to the ground voltage;

a first resistor coupled between the second current source and the emitter of the second bipolar transistor;
a feedback device coupled between the third current source and the base of the second bipolar transistor, the feedback device
being controlled by the second output of the second amplifier; and

a voltage divider configured to divide a voltage difference between the third current source and the base of the second bipolar
transistor to provide a reference voltage;

wherein the fourth input of the second amplifier is couple to one of the first input of the first amplifier and the second
input of the first amplifier.

US Pat. No. 9,047,977

CIRCUIT AND METHOD FOR OUTPUTTING REFRESH EXECUTION SIGNAL IN MEMORY DEVICE

Elite Semiconductor Memor...

1. A circuit for outputting a refresh execution signal to a memory cell of a memory device in an auto-refresh mode, the circuit
comprising:
a first frequency dividing unit for receiving an auto-refresh signal from outside of the memory device and generating a plurality
of first divided signals;

a first selection circuit for generating a selection signal selected from one of the auto-refresh signal and the first divided
signals according to a data retention time of the memory cell;

a second frequency dividing unit for dividing the frequency of the selection signal and generating a plurality of second divided
signals; and

a second selection circuit for generating the refresh execution signal from one of the selection signal and the second divided
signals according to a temperature of the memory cell, wherein

the first frequency dividing unit includes a first frequency divider configured to provide a first one of the first divided
signals in response to the auto-refresh signal, and

the first frequency dividing unit includes a second frequency divider configured to provide a second one of the first divided
signals in response to the first one of the first divided signals.

US Pat. No. 9,660,588

QUATERNARY/TERNARY MODULATION SELECTING CIRCUIT AND ASSOCIATED METHOD

Elite Semiconductor Memor...

1. A quaternary/ternary modulation selecting circuit of an audio amplifier, comprising:
a quaternary signal generating circuit, for receiving complementary analog input signals to generate complementary quaternary
signals; and

a ternary signal generating circuit, for generating a ternary signal according to the complementary quaternary signals, wherein
the ternary signal comprises a positive ternary wave and a negative ternary wave;

wherein when a difference in amplitude between the complementary analog input signals is within a predetermined range of zero
amplitude, a phase of the positive ternary wave generated from the ternary signal generating circuit is identical to a phase
of the negative ternary wave generated from the ternary signal generating circuit.

US Pat. No. 9,479,169

CONTROL CIRCUIT APPLIED IN E-FUSE SYSTEM AND RELATED METHOD

Elite Semiconductor Memor...

1. A control circuit applied in an e-fuse system, wherein the control circuit selectively operates in a feeding mode and a
reading mode, wherein when the control circuit operates in the feeding mode, the control circuit is arranged to store a program
code for indicating whether to connect a fuse of the e-fuse system thereto; and when the control circuit operates in the reading
mode, the control circuit is arranged to read a state of the fuse of the e-fuse system coupled to the control circuit.

US Pat. No. 9,705,315

PROTECTION CIRCUIT FOR PREVENTING AN OVER-CURRENT FROM AN OUTPUT STAGE

Elite Semiconductor Memor...

1. A semiconductor device, comprising:
an output stage, comprising a PMOS, an NMOS and an output terminal, wherein a source terminal of the PMOS is connected to
a first supply voltage, a drain terminal of the PMOS is connected to a drain terminal of the NMOS and the output terminal,
a source terminal of the NMOS is connected to a second supply voltage, and the output terminal outputs an output signal; and

a protection circuit, comprising
a first voltage clamping circuit, comprising a first transistor, a second transistor and a first switch, wherein the first
transistor and the second transistor are arranged to clamp a gate voltage of the PMOS of the output stage and are connected
in series between the first supply voltage and a gate terminal of the PMOS, the first switch is coupled to the first supply
voltage and a node between the first transistor and the second transistor, and the first switch is arranged to selectively
couple the first supply voltage to the node between the first transistor and the second transistor.

US Pat. No. 9,997,230

REFERENCE VOLTAGE PRE-PROCESSING CIRCUIT AND REFERENCE VOLTAGE PRE-PROCESSING METHOD FOR A REFERENCE VOLTAGE BUFFER

Elite Semiconductor Memor...

1. A reference voltage pre-processing circuit for a reference voltage buffer, comprising:a first transistor, comprising a gate electrode configured to connect to a ground, a first electrode, and a second electrode;
a second transistor, comprising a gate electrode configured to connect to a voltage source, a first electrode connected to the second electrode of the first transistor, and a second electrode; and
an auxiliary voltage circuit, configured to interface the second transistor and the reference voltage buffer;
wherein the first transistor is a PMOS transistor, the second transistor is an NMOS transistor, one of the first electrode of the first transistor and the second electrode of the second transistor is configured to receive a first reference voltage and the other electrode is configured to provide a second reference voltage originating from the first reference voltage to the reference voltage buffer; and
wherein the auxiliary voltage circuit provides a third reference voltage to the reference voltage buffer if the second reference voltage is invalid and provides a fourth reference voltage to the reference voltage buffer if the second reference voltage is valid.

US Pat. No. 9,748,911

VARIABLE GAIN AMPLIFYING CIRCUIT

Elite Semiconductor Memor...

1. A variable gain amplifying circuit for amplifying a difference between a first input signal and a second input signal to
generate an amplified difference output signal, comprising:
an operational amplifier having a first input terminal, a second input terminal, and an output terminal providing the amplified
difference output signal;

an input device having a first terminal receiving the first input signal, and a second terminal coupled to the first input
terminal of the operational amplifier; and

a feedback device having a first terminal coupled to the first input terminal of the operational amplifier, and a second terminal
coupled to the output terminal of the operational amplifier;

a dynamic biasing circuit for generating a bias current according to a set value; and
a transconductance circuit for converting the difference between the first input signal and the second input signal into an
analog output current flowing through the feedback device;

wherein the input device has a constant resistance and the feedback device has a constant resistance; and
wherein the analog output current of the transconductance circuit is varied according to the bias current.

US Pat. No. 9,805,782

MEMORY DEVICE CAPABLE OF DETERMINING CANDIDATE WORDLINE FOR REFRESH AND CONTROL METHOD THEREOF

Elite Semiconductor Memor...

1. A memory device, comprising:
a plurality of normal wordlines;
a plurality of redundant wordlines;
an address generation circuit, for generating a first intermediate address according to a row address, wherein the first intermediate
address comprises a first wordline address and a first identification code, and the first identification code indicates whether
a first wordline indicated by the first wordline address is a normal wordline or a redundant wordline;

an address processing circuit, coupled to the address generation circuit, the address processing circuit arranged for referring
to the first intermediate address to generate a second intermediate address indicating a second wordline adjacent to the first
wordline, wherein the second intermediate address comprises a second wordline address and a second identification code, the
second wordline address indicates the second wordline, and the second identification code indicates whether the second wordline
is a normal wordline or a redundant wordline; and

a refresh control circuit, coupled to the address processing circuit, the refresh control circuit arranged for determining
a disturbance count of the second wordline each time the first wordline is activated, and referring to the disturbance count
to determine whether to output the second wordline address to refresh the second wordline, wherein the disturbance count indicates
a number of times the second wordline is disturbed due to activation of one or more wordlines adjacent to the second wordline.

US Pat. No. 10,008,930

BOOTSTRAP CIRCUIT AND ASSOCIATED DIRECT CURRENT-TO-DIRECT CURRENT CONVERTER APPLYING THE BOOTSTRAP CIRCUIT

Elite Semiconductor Memor...

1. A bootstrap circuit applied to a first transistor of a direct-current (DC) to DC converter, comprising:a second transistor;
a bootstrapping capacitor, having a first terminal and a second terminal, wherein the first terminal is coupled to a source terminal of the second transistor, and the source terminal of the second transistor is coupled to the first transistor; and
a clamping circuit, coupled between a gate terminal of the second transistor and the second terminal of the bootstrapping capacitor, the clamping circuit being arranged to maintain a voltage drop between the second terminal of the bootstrapping capacitor and the gate terminal of the second transistor;
wherein a drain terminal of the transistor is coupled to a first reference voltage, and a maximum of a voltage level of a gate terminal of the first transistor is greater than the first reference voltage.

US Pat. No. 9,977,459

CLOCK GENERATING CIRCUIT AND ASSOCIATED METHOD

Elite Semiconductor Memor...

1. A clock generating circuit, comprising:a generating circuit, arranged to generate a clock signal;
a reference circuit, coupled to the generating circuit, wherein the reference circuit is arranged to generate a reference signal to the generating circuit according to the clock signal, wherein a frequency of the clock signal is varied according to the reference signal when the reference signal is received by the generating circuit; and
an adjusting circuit, arranged to generate an adjusting signal and a trigger signal to the generating circuit, wherein the generating circuit refers to the trigger signal to decide whether to adjust the frequency of the clock signal according to the adjusting signal.

US Pat. No. 9,871,517

METHOD FOR DETERMINING RESISTANCE CALIBRATION DIRECTION IN ZQ CALIBRATION OF MEMORY DEVICE

Elite Semiconductor Memor...

1. A method for determining a resistance calibration direction in ZQ calibration of a memory device, comprising:
repeatedly comparing a reference voltage with an target voltage by a comparator to obtain an odd plurality of comparison outputs,
each of the comparison outputs being one of a high-level state and a low-level state;

determining a majority of the comparison outputs for their states by a ZQ calibration controller; and
determining a resistance calibration direction based on the majority by the ZQ calibration controller so that the ZQ calibration
controller generates a calibration code based on the resistance calibration direction and applies the calibration code to
a resistance calibration unit to adjust the target voltage via the resistance calibration unit.

US Pat. No. 10,008,292

MEMORY AUTO REPAIRING CIRCUIT PREVENTING TRANSMISSION OF AN ENABLE SIGNAL AND ASSOCIATED METHOD

Elite Semiconductor Memor...

1. A memory auto repairing circuit, comprising:a decoding circuit, arranged to compare a first input address with a plurality of fail addresses to generate a control signal;
a latch enable circuit, arranged to selectively generate a first enable signal at least according to the control signal; and
a first latch circuit, arranged to receive the first input address, and store the first input address when the first enable signal is received by the first latch circuit;
wherein when the control signal indicates that the first input address is identical to one of the plurality of fail addresses, the enable signal is prevented from being transmitted from the latch enable circuit to the first latch circuit.

US Pat. No. 10,014,848

COMPENSATION CIRCUIT FOR INPUT VOLTAGE OFFSET OF ERROR AMPLIFIER AND ERROR AMPLIFIER CIRCUIT

ELITE SEMICONDUCTOR MEMOR...

1. A compensation circuit used to compensate an input voltage offset of an error amplifier, comprising:a level shifter, used to shift levels of a feedback voltage and a predetermined reference voltage, and thus to output a level shifted feedback voltage and a level shifted reference voltage;
a first trimming circuit, connected to the level shifter and the error amplifier, used to adjust the level shifted reference voltage by trimming a first resistance thereof according to a trimming code, wherein the trimming code has the ratio relation of the input voltage offset and a resistance to be trimmed;
a second trimming circuit, connected to the level shifter and the error amplifier, used to adjust the level shifted feedback voltage by trimming a second resistance thereof according to a trimming code; and
a compensation current sinking device, connected to the first and second trimming circuits, used to sink currents passing through the first and second trimming circuits.

US Pat. No. 10,056,401

NON-VOLATILE MEMORY HAVING DISCRETE ISOLATION STRUCTURE AND SONOS MEMORY CELL, METHOD OF OPERATING THE SAME, AND METHOD OF MANUFACTURING THE SAME

ELITE SEMICONDUCTOR MEMOR...

1. A non-volatile memory having a first discrete isolation structure and a second discrete isolation structure and a SONOS (Silicon Oxide Nitride Oxide Silicon) memory cell, the non-volatile memory comprising:the first discrete isolation structure and the second isolation structure on a surface of a semiconductor substrate, wherein the first discrete isolation structure and the second discrete isolation structure are arranged parallel to a column direction and spaced apart in a row direction, the column direction being perpendicular to the row direction, the first discrete isolation structure being effectuated by a plurality of first gaps, the plurality of first gaps being distributed on a first column in the column direction to allow the first discrete isolation structure to be completely divided into a plurality of sections, the second discrete isolation structure being effectuated by a plurality of second gaps, the plurality of second gaps being distributed on a second column in the column direction to allow the second discrete isolation structure to be completely divided into a plurality of sections;
a source region of the SONOS memory cell, wherein the channel is disposed on a first row in the row direction, the channel being in communication with one of the first gaps and being disposed at one of the second gaps, wherein the one of the first gaps and the one of the second gaps are disposed in the first row;
a plurality of continuous isolation structures in the semiconductor substrate, each continuous isolation structure of the plurality of continuous isolation structures extending continuously in a column direction, such that each continuous isolation structure overlaps, in the row direction, an entirety of each of the plurality of sections of the first and second discrete isolation structures;
ONO (Oxide-Nitride-Oxide) structures on a surface of the semiconductor substrate;
a plurality of controlling gates on the ONO structures, wherein the plurality of controlling gates are arranged parallel to the row direction; and
at least one source line contact windows on the source region of the SONOS memory cell;
wherein, in plan view, the first discreet isolation structure has a same width in the row direction as the second discrete isolation structure;
wherein the second discrete isolation structure is flanked by two adjoining discrete isolation structures parallel to the second discrete isolation structure and the first discrete isolation structure is not flanked by any adjoining discrete isolation structures.

US Pat. No. 10,050,432

APPARATUS WITH LOAD DUMP PROTECTION

Elite Semiconductor Memor...

1. An apparatus for driving a load between first and second output nodes, comprising:a first half-bridge circuit comprising first and second transistors connected in series between a supply voltage and a reference voltage, with the first output node between the first and second transistors;
a second half-bridge circuit comprising third and fourth transistors connected in series between the supply voltage and the reference voltage, with the second output node between the third and fourth transistors;
a first comparator configured to compare the supply voltage with a first set voltage and generate a first comparison signal while the supply voltage exceeds the first set voltage;
a second comparator configured to compare the supply voltage with a second set voltage and generate a second comparison signal while the supply voltage exceeds the second set voltage;
a first clamping circuit configured to divide the supply voltage and provide a first divided voltage at the first output node in response to the second comparison signal; and
a second clamping circuit configured to divide the supply voltage and provide a second divided voltage at the second output node in response to the second comparison signal;
wherein the second set voltage is larger than the first set voltage; and
wherein the first, second, third, and fourth transistors are turned off in response to the first comparison signal.

US Pat. No. 10,256,722

OSCILLATOR AND ASSOCIATED DIRECT CURRENT-TO-DIRECT CURRENT CONVERTER APPLYING THE OSCILLATOR

Elite Semiconductor Memor...

1. An oscillator, comprising:a reference current generating circuit, arranged to generate a first reference current;
a modulator circuit, coupled to the reference current generating circuit, wherein the modulator circuit is arranged to generate a modulation current according to the first reference current and a feedback voltage, and the modulation current is negatively correlated with the feedback voltage, the modulator circuit comprising:
a first transistor, having a source terminal coupled to the first reference current, and a gate terminal coupled to the feedback voltage, wherein the first transistor is controlled by the feedback voltage; and
a current mirror, coupled to a drain terminal of the first transistor to generate the modulation current; and
an oscillating circuit, coupled to the modulator circuit, wherein the oscillating circuit is arranged to receive at least the modulation current and generate an oscillating signal with an oscillating frequency according to at least the modulation current, wherein the oscillating frequency is varied according to the modulation current.

US Pat. No. 10,297,607

NON-VOLATILE MEMORY HAVING DISCRETE ISOLATION STRUCTURE AND SONOS MEMORY CELL, METHOD OF OPERATING THE SAME, AND METHOD OF MANUFACTURING THE SAME

ELITE SEMICONDUCTOR MEMOR...

1. A non-volatile memory having a first discrete isolation structure and a second discrete isolation structure and a SONOS (Silicon Oxide Nitride Oxide Silicon) memory cell, the non-volatile memory comprising:the first discrete isolation structure and the second isolation structure on a surface of a semiconductor substrate, wherein the first discrete isolation structure and the second discrete isolation structure are arranged parallel to a column direction and spaced apart in a row direction, the column direction being perpendicular to the row direction, the first discrete isolation structure being effectuated by a plurality of first gaps, the plurality of first gaps being distributed on a first column in the column direction to allow the first discrete isolation structure to be completely divided into a plurality of sections, the second discrete isolation structure being effectuated by a plurality of second gaps, the plurality of second gaps being distributed on a second column in the column direction to allow the second discrete isolation structure to be completely divided into a plurality of sections;
a source region of the SONOS memory cell, wherein the channel is disposed on a first row in the row direction, the channel being in communication with one of the first gaps and being disposed at one of the second gaps, wherein the one of the first gaps and the one of the second gaps are disposed in the first row;
a plurality of continuous isolation structures in the semiconductor substrate, each continuous isolation structure of the plurality of continuous isolation structures extending continuously in a column direction, such that each continuous isolation structure overlaps, in the row direction, an entirety of each of the plurality of sections of the first and second discrete isolation structures;
ONO (Oxide-Nitride-Oxide) structures on a surface of the semiconductor substrate;
a plurality of controlling gates on the ONO structures, wherein the plurality of controlling gates are arranged parallel to the row direction; and
at least one source line contact windows on the source region of the SONOS memory cell;
wherein, in plan view, the first discreet isolation structure has a same width in the row direction as the second discrete isolation structure;
wherein the second discrete isolation structure is flanked by two adjoining discrete isolation structures parallel to the second discrete isolation structure and the first discrete isolation structure is not flanked by any adjoining discrete isolation structures.

US Pat. No. 10,462,860

CONTROLLER FOR SWITCHING REGULATOR, SWITCHING REGULATOR AND LED LIGHTING SYSTEM

ELITE SEMICONDUCTOR MEMOR...

1. A controller for a switching regulator of a LED lighting system, comprising:a current monitor, used to sense a LED current passing through a current sensing resistor of the switching regulator, and to generate a sensing current; and
a voltage divider, connected to the current monitor, used to receive the sensing current to generate a first through third divided voltages, wherein the first divided voltage is larger than the second divided voltage, and the second divided voltage is larger than the third divided voltage;
an integration circuit, connected to the voltage divider, used to compare the second divided voltage with a reference voltage, and to generate an integration voltage across a RC circuit thereof accordingly; and
a comparator circuit, connected to the integration circuit and the voltage divider, used to compare the integration voltage with the first divided voltage and the third divided voltage, and to generate a driving signal.

US Pat. No. 10,203,715

BANDGAP REFERENCE CIRCUIT FOR PROVIDING A STABLE REFERENCE VOLTAGE AT A LOWER VOLTAGE LEVEL

ELITE SEMICONDUCTOR MEMOR...

1. A bandgap reference circuit, comprising:a first amplifier having a first input, a second input, and a first output;
a second amplifier having a third input, a fourth input, and a second output;
a first current source coupled between a power supply node and the first input of the first amplifier;
a second current source coupled between the power supply node and the second input of the first amplifier;
a third current source coupled between the power supply node and the third input of the second amplifier;
a first bipolar transistor having a base, an emitter coupled to the first current source, and a collector coupled to a ground node;
a second bipolar transistor having a base, an emitter coupled to the second current source, and a collector coupled to the ground node;
a first resistor coupled between the third input of the second amplifier and the base of the first bipolar transistor;
a first feedback device coupled between the third current source and the base of the second bipolar transistor, the first feedback device being controlled by the second output of the second amplifier; and
a second resistor coupled between the base of the first bipolar transistor and the base of the second bipolar transistor;
wherein the fourth input of the second amplifier is coupled to one of the first input of the first amplifier and the second input of the first amplifier;
wherein a current flowing through the first resistor is a complimentary to an absolute temperature (CTAT) current; and
wherein a current flowing through the second resistor is a proportional to an absolute temperature (PTAT) current.

US Pat. No. 10,424,386

ERASING METHOD FOR FLASH MEMORY USING A MEMORY MANAGEMENT APPARATUS

ELITE SEMICONDUCTOR MEMOR...

1. An erasing method used in a flash memory comprising at least one memory block divided into a plurality of memory sectors, comprising:verifying whether the memory block or the memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enable signal, wherein the sector enable signal is determined according to whether the memory block has at least one over-erased transistor memory cell; and
erasing transistor memory cells of the memory block or the memory sector according to the sector enable signal if the memory block or the memory sector corresponding to the address has the under-erased transistor memory cell, wherein if the sector enable signal is asserted, and the memory sector corresponding to the address has the under-erased transistor memory cell, the transistor memory cells of the memory sector are injected with an erasing shot at least one time until the memory sector does not have the under-erased transistor memory cell.

US Pat. No. 10,404,227

QUATERNARY/TERNARY MODULATION SELECTING CIRCUIT AND ASSOCIATED METHOD

Elite Semiconductor Memor...

1. A quaternary/ternary modulation selecting circuit of an amplifier, comprising:a signal generating circuit, arranged to generate a ternary signal and a quaternary signal;
a detecting circuit, coupled to the signal generating circuit, wherein the detecting circuit is arranged to determine if a pulse loss phenomenon occurs to the ternary signal to generate a mode selecting signal; and
a selecting circuit, coupled to the signal generating circuit and the detecting circuit, wherein the selecting circuit is arranged to select and output one of the ternary signal and the quaternary signal to an output stage of the amplifier according to the mode selecting signal.

US Pat. No. 10,281,943

LOW DROPOUT REGULATOR WITH A CONTROLLED STARTUP

ELITE SEMICONDUCTOR MEMOR...

1. A low dropout voltage regulator, comprising:an N-channel MOS pass transistor having a drain coupled to receive an input voltage and a source coupled to generate an output voltage;
a main error amplifier having a positive input coupled to receive a portion of the output voltage, a negative input coupled to receive a reference voltage, and an amplifier output;
a first buffer circuit coupled between the amplifier output of the main error amplifier and a gate of the N-channel MOS pass transistor;
an auxiliary error amplifier which consumes less bias current than the main error amplifier, the auxiliary error amplifier having a first positive input coupled to receive the portion of the output voltage, a second positive input, a negative input coupled to receive the reference voltage, and an amplifier output;
a second buffer circuit coupled between the amplifier output of the auxiliary error amplifier and the gate of the N-channel MOS pass transistor; and
a decision circuit configured to compare the portion of the output voltage with a bias voltage to control the gate of the N-channel MOS pass transistor;
wherein a value of the bias voltage is less than the value of the reference voltage.

US Pat. No. 9,525,424

METHOD FOR ENHANCING TEMPERATURE EFFICIENCY

ELITE SEMICONDUCTOR MEMOR...

1. A method for enhancing temperature efficiency, comprising:
generating a PTAT current by using a bandgap circuit;
generating a CTAT current by using the bandgap circuit;
generating an output current, wherein the output current equals to the PTAT current minus the CTAT current; and
providing the output current to an oscillator for generating an oscillating frequency;
wherein the bandgap circuit comprises:
a current generating circuit, used to generate the PTAT current and the CTAT current; and
an output circuit, comprising a plurality of transistors, and connected to the current generating circuit for receiving the
PTAT current and the CTAT current so as to generate the output current;

wherein the current generating circuit comprises:
a plurality of current mirrors, connected to a fixed voltage source; and
at least one amplifier, connected to a current mirror, configured to output the PTAT current and the CTAT current;
wherein the current generating circuit further comprises a level control unit, wherein the level control unit comprises a
plurality of transistors, and each of the transistors is connected to one of the current mirrors and one of the amplifiers
so as to control levels of the PTAT current and the CTAT current.