US Pat. No. 9,380,668

PDM MODULATION OF LED CURRENT

Dialog Semiconductor (UK)...

1. An LED light dimming circuit, comprising:
a) a string of at least one LED device;
b) a control circuit providing primary side regulation configured to produce drive current and modulation; and
c) said control circuit configured to hold drive current constant at a predetermined level and varying a duty cycle of a pulse
density modulator (PDM) to change LED device illumination, wherein said control circuit is configured to produce a hysteresis
in the drive current between a fixed PDM duty cycle portion and a variable PDM duty cycle portion of the LED current to enable
a smooth transition in emitted LED light.

US Pat. No. 9,635,719

HIGH VOLTAGE CONVERTER WITHOUT AUXILIARY WINDING

Dialog Semiconductor (UK)...

1. A driver circuit which is configured to generate a drive voltage to a load subject to an input voltage, wherein the driver
circuit comprises
a power converter network comprising an inductor which is coupled to the input voltage;
a power transistor having a high voltage terminal which is coupled to the inductor and having a low voltage terminal;
a controller; and
a supply voltage capacitor for providing a logic supply voltage to the controller; wherein
the controller comprises a control transistor which is configured to couple the low voltage terminal of the power transistor
to a low voltage potential or to decouple the low voltage terminal from the low voltage potential, in order to put the power
transistor to a conduction-state or an off-state, respectively;

the controller comprises a charging transistor forming a serial arrangement with the supply voltage capacitor; wherein the
serial arrangement is arranged in parallel to the control transistor, and wherein the charging transistor is configured to
couple or to decouple the low voltage terminal of the power transistor to or from the supply voltage capacitor, in order to
put the power transistor to the conduction-state or off-state, respectively; and

the controller is configured to
put the power transistor to the conduction-state using the charging transistor within a first time interval and to
put the power transistor to the conduction-state using the control transistor within a second time interval.

US Pat. No. 9,559,597

DETECTING OPEN CONNECTION OF AUXILIARY WINDING IN A SWITCHING MODE POWER SUPPLY

Dialog Semiconductor Inc....

1. A power converter comprising:
a transformer including a primary winding coupled to an input voltage, a secondary winding coupled to an output of the power
converter, and an auxiliary winding, output voltage of the power converter being reflected as feedback across the auxiliary
winding;

a current source coupled to the auxiliary winding, the current source when activated supplying a current to the auxiliary
winding; and

a controller regulating the output voltage of the power converter based on the feedback across the auxiliary winding, the
controller adapted to measure a voltage across the auxiliary winding while the current source is activated and disable the
power converter responsive to detecting the voltage across the auxiliary winding is greater than a threshold voltage while
the current source is activated.

US Pat. No. 9,837,912

SINGLE STAGE SWITCHING POWER CONVERTER WITH IMPROVED PRIMARY ONLY FEEDBACK

DIALOG SEMICONDUCTOR INC....

1. A method of controlling a switching power converter, comprising:
comparing an on-time current produced from each cycle of a power switch to a current threshold to determine whether a sense
voltage pulse produced on an auxiliary winding from each cycle of the power switch is trustable or non-trustable, and wherein
consecutive cycles of a rectified input voltage are separated by a dead period in which the sense voltage pulses are non-trustable;

during each trustable sense voltage pulse, adjusting a reference voltage responsive to the trustable sense voltage pulse;
during each rectified input voltage cycle, determining a first trustable value of the voltage reference resulting from an
initial one of the trustable sense voltage pulses in the rectified input voltage cycle and determining a last trustable value
of the voltage reference resulting from a final one of the trustable sense voltage pulses in the rectified input voltage cycle;

for each dead period, extrapolating from the first trustable value of the reference voltage and the last trustable value to
produce an extrapolated reference voltage; and

controlling the cycling of the power switch during each dead period responsive to the extrapolated reference voltage.

US Pat. No. 9,509,205

POWER CONVERTER WITH NEGATIVE CURRENT CAPABILITY AND LOW QUIESCENT CURRENT CONSUMPTION

Dialog Semiconductor (UK)...

1. A power converter for converting a DC input voltage to a DC output voltage, the power converter comprising:
an output node;
a pass device connected to the output node of the power converter, the pass device being configured to operate in accordance
with a PWM signal and to supply at least a portion of an output current of the power converter;

a PWM comparator for generating the PWM signal for controlling operation of the pass device in accordance with a current conducted
by the pass device and a difference between an output voltage of the power converter and a reference voltage, the PWM comparator
having a first input terminal and a second input terminal;

a first current sensing circuit for outputting a first sense current depending on the current conducted by the pass device,
the first current sensing circuit being configured to sense the current conducted by the pass device if the current conducted
by the pass device has a given polarity, the first current sensing circuit further being connected to the PWM comparator in
such a manner that a voltage depending on the first sense current is supplied to the first input terminal of the PWM comparator;
and

a second current sensing circuit for outputting a second sense current depending on the current conducted by the pass device,
the second current sensing circuit being configured to sense the current conducted by the pass device if the current conducted
by the pass device has a polarity opposite to the given polarity, the second current sensing circuit further being connected
to the PWM comparator in such a manner that a voltage depending on the second sense current is supplied to the second input
terminal of the PWM comparator.

US Pat. No. 9,474,120

ACCURATE MAINS TIME-BASE FOR LED LIGHT DRIVER

Dialog Semiconductor (UK)...

1. A controller for a driver circuit of a solid state lighting, referred to as SSL, device, wherein the driver circuit comprises
a power converter configured to transfer energy from an input of the driver circuit to the SSL device; wherein the energy
at the input is derived from an AC mains voltage comprising a sequence of cycles; wherein the controller is configured to
determine a dim level for the SSL device;
determine a synchronization signal (411) by comparing a voltage derived from the AC mains voltage with a pre-determined threshold;

determine a sequence of PWM pulses based on the synchronization signal such that
the sequence of PWM pulses comprises one or more PWM pulses per half-cycle of the AC mains voltage; and
the one or more PWM pulses for a current half-cycle n depend on the synchronization signal (411) for at least one half-cycle prior to the current half-cycle n where n is an integer; and

operate the power converter in a first operation mode for supplying energy to the SSL device at a first energy level within
the sequence of PWM pulses, and operate the power converter in a second operation mode in between the PWM pulses; wherein
in the second operation mode the power converter is operated for supplying energy to the SSL device at a second energy level;
wherein the second energy level is lower than the first energy level; and wherein the first energy level and/or a width of
the one or more PWM pulses depend on the dim level.

US Pat. No. 9,450,490

AUTOMATIC REFERENCE GENERATOR IN SWITCHING BOOST CONVERTERS

Dialog Semiconductor (UK)...

1. A switching converter to minimize a regulation error comprising:
a port for a static reference voltage;
a window comparator configured to comparing the static reference voltage with a scaled output voltage of the switching converter
capable of setting control signals for an up and down counter with successive incremental corrections if a target range is
exceeded;

an auxiliary reference generator comprising the up and down counter, wherein an output of the auxiliary reference generator
equals the static reference voltage if the scaled output voltage of the switching converter does not exceed the target range
and the output of the auxiliary reference generator performs the successive incremental corrections of the static reference
voltage if the scaled output voltage of the switching converter exceeds the target range;

an error amplifier, configured to compare the scaled output voltage of the switching converter with the output of the auxiliary
reference generator; and

a clock source to clock the up and down counter.

US Pat. No. 10,001,795

LINEAR REGULATOR WITH IMPROVED STABILITY

Dialog Semiconductor (UK)...

1. A linear regulator comprisinga first amplifier stage having an input and an output, one of the inputs being coupled with the output of the linear regulator;
an intermediate amplifier stage having an input and an output, the input of the intermediate amplifier stage being coupled to the output of the first amplifier stage;
a driver stage having an input and an output;
a pass device driven by the output of the driver stage, the output of the pass device proving the output of the linear regulator; and
a voltage-to-current feedback circuit coupled with the driver stage and the output of the first amplifier stage for regulating the output resistance of the first amplifier stage depending on load conditions of the linear regulator, the voltage-to-current feedback circuit comprising a transistor and a current limitation circuit to limit the regulation of the output resistance of the first amplifier stage to low load conditions of the linear regulator,
wherein the input of the driver stage is coupled to said output of said intermediate amplifier stage and the gate of the transistor of said voltage-to-current feedback circuit is coupled with the gate of the pass device.

US Pat. No. 9,471,084

APPARATUS AND METHOD FOR A MODIFIED BROKAW BANDGAP REFERENCE CIRCUIT FOR IMPROVED LOW VOLTAGE POWER SUPPLY

Dialog Semiconductor (UK)...

15. A bandgap voltage reference circuit with improved operation at low voltage power supply, the circuit comprising:
a first npn bipolar transistor;
a second npn bipolar transistor wherein the base of said second npn bipolar transistor and first npn bipolar transistor are
electrically coupled;

a third npn bipolar transistor wherein the base of said third npn bipolar transistor is electrically connected to the base
of said first npn bipolar transistor and electrically connected to the collector of said third npn bipolar transistor;

a first resistor element electrically connected to the emitter of said second npn bipolar transistor;
a second resistor element electrically connected to the emitter of said first npn bipolar transistor;
a third resistor element electrically connected to the emitter of said third npn bipolar transistor;
a fourth resistor element electrically connected to the collector of said third npn bipolar transistor;
a first pnp bipolar transistor wherein said first pnp bipolar transistor base and collector are electrically connected to
said first npn bipolar transistor;

a second pnp bipolar transistor wherein said second pnp bipolar transistor base is electrically connected to said first pnp
bipolar transistor and electrically connected to said second npn bipolar transistor;

a third pnp bipolar transistor wherein said third pnp bipolar transistor base is electrically connected to said second pnp
bipolar transistor and electrically connected to said fourth resistor; and,

a bandgap voltage reference output wherein said bandgap voltage reference output is connected to said third pnp bipolar transistor,
and said fourth resistor; and,
wherein said base voltage of the first npn bipolar transistor is expressed as a function of Vbe, ?Vbe, and said first and
said second resistors
and the bandgap output voltage can be calculated as a function of Vbe, ?Vbe, and said first resistor, said third resistor,
and said fourth resistor element

US Pat. No. 9,312,747

FAST START-UP CIRCUIT FOR LOW POWER CURRENT MIRROR

Dialog Semiconductor (UK)...

1. A fast startup circuit, comprising:
a) a first capacitor charged to zero volts when a disable switch is closed
b) a second capacitor charged to a bias voltage when the disable switch is closed; and
c) a current mirror circuit enabled in which the disable switch is opened and a enable switch is closed, wherein the current
mirror circuit comprises the first and second capacitors, and wherein charge on the first and second capacitors equalize causing
current in the current mirror circuit to start at a steady state operating value.

US Pat. No. 9,392,661

LOW-OVERHEAD CURRENT GENERATOR FOR LIGHTING CIRCUITS

Dialog Semiconductor (UK)...

1. A lighting system comprising:
a plurality of light emitting diode, LED, circuits;
a power source for providing a drive voltage to the plurality of LED circuits;
for each LED circuit, a first variable resistance element connected between the respective LED circuit and ground;
for each LED circuit, a first feedback circuit configured to control a voltage at a first node between the respective LED
circuit and the respective first variable resistance element to a first voltage;

a current source; and
a second variable resistance element connected between the current source and ground,
wherein each first variable resistance element is configured to attain a resistance value depending on a resistance value
attained by the second variable resistance element.

US Pat. No. 9,240,762

METHOD AND CIRCUIT FOR IMPROVING THE SETTLING TIME OF AN OUTPUT STAGE

Dialog Semiconductor (UK)...

1. An amplifier comprising an output stage for providing an output current at an output voltage, in dependence of an input
voltage at a stage input node of the output stage; wherein the output stage comprises
a first input transistor; wherein a gate of the first input transistor is coupled to the stage input node of the output stage;
a first diode transistor; wherein the first diode transistor is arranged in series with the input transistor;
a pass device configured to provide the output current at the output voltage; wherein the first diode transistor and the pass
device form a current mirror; wherein a midpoint between the first input transistor and the first diode transistor is coupled
to a gate node of the pass device;

a second input transistor; wherein a gate of the second input transistor is coupled to the stage input node of the output
stage; wherein the second input transistor is configured to control a voltage level at a replica node, in dependence of the
input voltage; and

a buffer transistor; wherein a gate of the buffer transistor is coupled to the replica node and wherein an input node of the
buffer transistor is coupled to the gate node, such that the buffer transistor is configured to sink or source a charge current
at the gate node, subject to the voltage level at the replica node and the voltage level at the gate node.

US Pat. No. 9,575,500

SINK/SOURCE OUTPUT STAGE WITH OPERATING POINT CURRENT CONTROL CIRCUIT FOR FAST TRANSIENT LOADING

Dialog Semiconductor (UK)...

1. A voltage regulator comprising
an amplification stage configured to control a voltage level of a first gain node and of a second gain node in response to
an input voltage at an input node, in order to activate a first and a second output stage, respectively; wherein the second
gain node is different from the first gain node;

the first output stage configured to source a current at an output node of the voltage regulator from a first potential, in
dependence of the voltage level of the first gain node; wherein the first output stage is activated if the current which is
sourced at the output node exceeds a pre-determined first maintenance current;

the second output stage configured to sink a current at the output node to a second potential, in dependence of the voltage
level of the second gain node; wherein the first potential is different from the second potential; wherein the second output
stage is activated if the current which is sunk at the output node exceeds a pre-determined second maintenance current; and

a first operating point control circuit configured to set the voltage level of the first gain node such that the first maintenance
current is sourced by the first output stage, when the second output stage is activated; and/or

a second operating point control circuit configured to set the voltage level of the second gain node such that the second
maintenance current is sunk by the second output stage, when the first output stage is activated,
wherein
the first output stage comprises
a first control transistor having a gate which is coupled to the first gain node, and being configured to vary a first control
current through the first control transistor, subject to a voltage level at the first gain node; and

a first output amplifier configured to source an amplified version of the first control current to the output node; and/or
the second output stage comprises
a second control transistor having a gate which is coupled to the second gain node, and being configured to vary a second
control current through the second control transistor, subject to a voltage level at the second gain node; and

a second output amplifier configured to sink an amplified version of the second control current at the output node;wherein
the first output amplifier comprises a first current mirror with a first diode transistor and a first output transistor;
the first diode transistor is arranged in series with the first control transistor such that the first diode transistor is
traversed by the first control current;

a drain of the first output transistor is coupled to the output node;
the first output transistor is traversed by the amplified version of the first control current, which is sourced at the output
node;

the second output amplifier comprises a second current mirror with a second diode transistor and a second output transistor;
the second diode transistor is arranged in series with the second control transistor such that the second diode transistor
is traversed by the second control current;

a drain of the second output transistor is coupled to the output node; andthe second output transistor is traversed by the amplified version of the second control current, which is sunk at the output
node.

US Pat. No. 9,961,729

TRIMMING SYSTEM AND METHOD FOR REGULATED CURRENT MIRRORS

Dialog Semiconductor (UK)...

1. A trimming system for trimming a load current provided to a load terminal, the trimming system comprising:a reference current circuit branch with
a current source configured to generate a reference current;
a first variable resistance element; and
a first decoupling resistance element connected between the current source and the first variable resistance element;
a load current circuit branch with
the load terminal;
a second variable resistance element configured to attain a resistance value depending on a resistance value attained by the first variable resistance element; and
a second decoupling resistance element connected between the load terminal and the second variable resistance element;
a voltage regulator configured to regulate a second voltage at a node between the load terminal and the second decoupling resistance element depending on a first voltage at a node between the current source and the first decoupling resistance element,
a current regulator configured to regulate the load current provided to the load terminal based on a voltage difference between a first output terminal of the first decoupling resistance element and a second output terminal of the second decoupling resistance element.

US Pat. No. 9,379,610

BUCK VARIABLE NEGATIVE CURRENT

Dialog Semiconductor (UK)...

1. A switching mode power supply (SMPS), comprising:
a) a buck power regulator comprising a high-side PMOS pass transistor and a low side active diode;
b) the low-side active diode capable of continuously varying a threshold voltage;
c) a circuitry configured to control the threshold voltage of the active diode, comprising:
a first comparison circuit configured to compare a voltage representing an output voltage of the buck converter with a reference
voltage, wherein an output of the first comparison circuit is connected to a first terminal of a circuit having resistance
and to a first input of a second comparison circuit;

said circuit having resistance, wherein a second terminal of the circuit having resistance is connected to ground, wherein
a resistance of the circuit having resistance is capable of determining a threshold of the second comparison circuit permitting
some of an excess current that has built up in the buck regulator to be conducted each cycle by the low-side active diode
to Vss, or circuit ground;

said second comparison circuit, configured to detect a zero crossing of a voltage of a node (LX) located between the PMOS
pass transistor and the active diode, wherein a second input of the second comparison circuit is connected to the LX node
and an output of the second comparison circuit is connected to a first input of a logic AND circuit; and

said logic AND circuit capable of turning off the low-side active diode if the high side PMOS pass transistor is not being
driven by a signal and a voltage change across the low-side active diode is detected by the second comparison circuit, wherein
an output of the AND circuit is connected to a gate of the low-side active diode; and

d) said buck power regulator capable of discharging a portion of excess current to circuit ground when an overvoltage resulting
from a high output voltage causes the threshold voltage to rise to allow discharge of said portion of the excess current.

US Pat. No. 9,232,596

MAINS SYNCHRONIZED PWM DIMMING

Dialog Semiconductor (UK)...

1. A controller for a driver circuit of a solid state lighting, referred to as SSL, device, wherein the driver circuit comprises
a power converter configured to transfer energy from an input of the driver circuit to the SSL device; wherein the energy
at the input is derived from an AC mains voltage at a mains frequency; wherein the controller is configured to
determine a dim level for the SSL device;
if the dim level is above a pre-determined dim level threshold, operate the power converter continuously in a first operation
mode for supplying energy to the SSL device at a first energy level; and

if the dim level is below the pre-determined dim level threshold, operate the power converter in the first operation mode
at a time duration of PWM pulses, and operate the power converter in a second operation mode at a time duration in-between
the PWM pulses; wherein in the second operation mode the power converter is operated for supplying energy to the SSL device
at a second energy level; wherein the second energy level is lower than the first energy level; and wherein the PWM pulses
are synchronized with the AC mains voltage.

US Pat. No. 9,541,933

HIGH SPEED REGULATOR WITH LOW CAPACITOR VALUES

Dialog Semiconductor (UK)...

1. A regulator configured to provide a load current at an output voltage in dependence of an input voltage; wherein the regulator
comprises
a core regulator configured to provide a core current at a core output voltage in dependence of the input voltage;
current sensing means configured to provide an indication of the core current;
wherein the output voltage is dependent on the core output voltage and on a voltage drop at the current sensing means;
a current source configured to provide an auxiliary current based on the indication of the core current; wherein the load
current is dependent on the core current and on the auxiliary current; and

offset circuitry configured to offset a core input voltage to the core regulator relative to the input voltage, such that
the output voltage is proportional to the input voltage, thereby compensating the voltage drop at the current sensing means.

US Pat. No. 9,431,904

DC/DC CONVERTER EFFICIENCY IMPROVEMENT FOR LOW CURRENT LEVELS

Dialog Semiconductor (UK)...

1. A controller for controlling a power converter which is configured to convert electrical power at an input voltage into
electrical power at an output voltage, wherein the power converter comprises a first inverter stage comprising a first high
side switch and a first low side switch which are arranged in series between the input voltage and a reference voltage; wherein
the power converter further comprises a second inverter stage comprising a second high side switch and a second low side switch
which are arranged in series between the input voltage and the reference voltage; wherein a midpoint between the first high
side switch and the first low side switch is coupled with a midpoint between the second high side switch and the second low
side switch; and wherein the electrical power at the output voltage is drawn from the midpoint; wherein the power converter
comprises a pre-determined number N of inverter stages, N>1; wherein the controller is configured to
determine an indication of a requested level of the electrical power at the output voltage, and
activate or deactivate the second inverter stage based on the indication of the requested level of the electrical power at
the output voltage;

determine a default number n of active inverter stages based on the indication of the requested level of the electrical power
at the output voltage, with 0
operate the power converter with the default number n of active inverter stages wherein the default number n of active inverter
stages comprises the first inverter stage;

determine a peak of the requested level of the electrical power at the output voltage; and
operate the power converter with more than the default number n of active inverter stages, subject to determining a peak of
the requested level of the electrical power at the output voltage.

US Pat. No. 9,426,852

DUAL MODE ANALOG AND DIGITAL LED DIMMING VIA MAINS VOLTAGE

Dialog Semiconductor (UK)...

1. A method for controlling a lamp assembly, comprising the steps of:
detecting a mains voltage supplied to the lamp assembly;
evaluating the waveform of the mains voltage and determining a light control signal based on the mains voltage waveform;
applying a demodulation process to the mains voltage to demodulate a digital data signal;
deciding a control operation mode based on the result of applying a demodulation process to the mains voltage; and
generating a drive signal to drive a light source of the lamp assembly based on the determined light control signal or the
demodulated data signal depending on the decided control operation mode,

the method further comprising detecting whether a phase cut was applied to the mains voltage waveform and deciding the control
operation mode based on whether a phase cut is detected or a digital data signal can be demodulated.

US Pat. No. 10,054,970

ADAPTIVE GAIN CONTROL FOR VOLTAGE REGULATORS

Dialog Semiconductor (UK)...

1. A voltage regulator configured to provide an output current at an output voltage at an output node, based on an input voltage at an input node, wherein the voltage regulator comprises,an output amplification stage comprising
a pass transistor for deriving the output current at the output node from the input voltage at the input node; and
a driver stage configured to set a gate voltage at a gate of the pass transistor based on a drive voltage;
wherein a gain of the output amplification stage is adjustable;
a differential amplification unit configured to determine the drive voltage in dependence of the output voltage and in dependence of a reference voltage; and
a gain control circuit configured to adjust the gain of the output amplification stage in dependence of the output current; wherein the gain control circuit is configured to adjust the gain by a gain delta if the output current changes by a current delta; and wherein a ratio of the gain delta and the current delta is equal to or smaller than a pre-determined transition threshold.

US Pat. No. 9,383,764

APPARATUS AND METHOD FOR A HIGH PRECISION VOLTAGE REFERENCE

Dialog Semiconductor (UK)...

1. A voltage reference circuit between a power supply node and a ground node and configured for generating a reference voltage
comprising:
a first current mirror with a first NMOS transistor and a second NMOS transistor wherein said first NMOS transistor threshold
voltage is not equal to said second NMOS transistor threshold voltage;

a second current mirror with a first PMOS transistor, a second PMOS transistor and third PMOS transistor configured to be
coupled to said power supply node, wherein the first PMOS transistor is coupled to the gate of the second PMOS transistor,
and third PMOS transistor, and wherein said second PMOS transistor and third PMOS transistor drains are coupled to said first
NMOS transistor drain and said second NMOS transistor drain, respectively;

a current source configured to provide current to said second current mirror;
an amplifier configured with a first and second input configured to be connected to the drains of said first NMOS transistor
and said second NMOS transistor; and,

a feedback loop configured to be the output of said amplifier.

US Pat. No. 9,100,041

FLASH CONVERTER CAPACITANCE REDUCTION METHOD

Dialog Semiconductor (UK)...

1. A circuit for reduction of total harmonic distortion and noise in a multiple bit oversampling data conversion apparatus
with limited code transitions between digital code words representing an instantaneous analog signal level, comprising:
a most significant code word boundary comparator for determining if a previous data conversion code is equal to or greater
than a most significant code word boundary;

a least significant code word boundary comparator for determining if a previous data conversion code is equal to or less than
a least significant code word boundary; and

a code converter enabling circuit connected for generating and transferring an enabling/disabling signal to a plurality of
code converter circuits within the multiple bit data bit oversampling data conversion circuit for enabling and disabling groups
of the code converter circuits to reduce a capacitance loading on a delta-sigma modulator of the multiple bit oversampling
data conversion apparatus to reduce the total harmonic distortion and noise in the multiple bit oversampling data conversion
apparatus;

wherein when the most significant word boundary comparator indicates that the previous data conversion code is equal to or
greater than the most significant code word boundary, the group of code converters circuits designated to represent the most
significant data bits of a current data conversion code are enabled and the group of code converter circuits designated to
represent the least significant data bits of a current data conversion code are disabled;

wherein when the least significant word boundary comparator indicates that the previous data conversion code is equal to or
less than the least significant code word boundary, the group of code converters circuits designated to represent the least
significant data bits of a current data conversion code are enabled and the group of code converter circuits designated to
represent the most significant data bits of a current data conversion code are disabled.

US Pat. No. 9,532,427

LOW-OVERHEAD CURRENT GENERATOR FOR LIGHTING CIRCUITS

Dialog Semiconductor (UK)...

1. A lighting system comprising:
a light emitting diode, LED, circuit;
a power source for providing a drive voltage to the LED circuit; and
a programmable current source connected between the LED circuit and ground and configured to output an output current in accordance
with a digital input code representing a numerical value,

wherein the programmable current source comprises switching means for performing a switching operation in accordance with
the digital input code; and

the switching means is adapted to switch a predetermined number of bits on the least significant bit, LSB, side of the digital
input code in accordance with binary coding, and to switch a remaining number of bits on the most significant bit, MSB, side
of the digital input code in accordance with unary coding.

US Pat. No. 9,531,260

VOLTAGE DOUBLER AND VOLTAGE DOUBLING METHOD FOR USE IN PWM MODE

Dialog Semiconductor (UK)...

1. An apparatus for generating a pulse width modulated, PWM, signal with a first period of time and a second period of time,
wherein said PWM signal has a PWM pulse during the second period and does not have the PWM pulse during the first period,
the apparatus comprising:
a voltage source;
a capacitor;
an output node for outputting the PWM signal, to drive an electric motor;
a switchable circuit assembly for connecting the voltage source, the capacitor and the output node; and
control means for controlling switching of the switchable circuit assembly,
wherein the switchable circuit assembly is adapted to be switchable between a first circuit configuration in which the capacitor
is connected in parallel to the voltage source so as to be chargeable by the voltage source, and a second circuit configuration
in which the capacitor is connected in series between the voltage source and the output node such that polarities of the voltage
source and the capacitor are aligned with each other; and

wherein the control means is adapted to control the switchable circuit assembly to switch to the first circuit configuration
in the first period, and to switch to the second circuit configuration in the second period.

US Pat. No. 9,379,612

OUTPUT CURRENT MONITOR CIRCUIT FOR SWITCHING REGULATOR

Dialog Semiconductor (UK)...

1. A circuit providing switching regulation with an improved current monitor comprising:
an output stage configured to provide switching comprising a first and second transistor;
a sense circuit configured to provide signal sensing from the first transistor in said output stage;
a sampling switch circuit configured to provide sample signals from said sense circuit, wherein the sampling switch circuit
is configured to provide a first and second signal to said integrator;

an integrator circuit configured to provide sample signals from said sampling switch circuit;
a comparator configured to provide signals from said integrator circuit; and
a digital-to-analog converter (DAC) configured to provide feedback signal from said comparator.

US Pat. No. 9,231,542

AMPLIFIER COMMON-MODE CONTROL METHOD

Dialog Semiconductor (UK)...

1. A fully differential amplifier system with common-mode control having reduced sensitivity to random offsets and mismatches
and improved common-mode loop bandwidth, comprising:
a fully differential main amplifier configured to receiving input signals via a positive input port Vip and a negative input
port Vin, and to generating output signals to a positive output port Vop and to a negative output port Von, wherein the main
amplifier is provided with a continuous-time signal path feedback network, wherein a first terminal of a positive branch of
the continuous-time signal path feedback network is connected to the positive input port Vip and a second terminal of the
positive branch of the continuous-time signal path feedback network is connected to the negative output port Von, and a first
terminal of a negative branch of the continuous-time signal path feedback network is connected to the negative input port
Vin and a second terminal of the negative branch of the continuous-time signal path feedback network is connected to the positive
output port Vop; and

an common-mode control sub-amplifier, which is configured to sensing common-mode voltages of the fully differential main amplifier
at a node Vcmip within a positive branch of the continuous-time signal path feedback network and at a node Vcmin within a
negative branch of the continuous-time signal path feedback network, to comparing the common-mode voltage sensed at nodes
Vcmin and Vcmip with a target reference voltage, and to regulating, depending on the result of the comparison, the output
common-mode voltage via the continuous signal path feedback network.

US Pat. No. 9,537,396

POWER SWITCH CONTROL BY ADJUSTING THE BASE CURRENT OF A BIPOLAR TRANSISTOR

Dialog Semiconductor (UK)...

1. A control circuit configured to control a power switch of a switched-mode power converter; wherein the power switch comprises
a bipolar transistor; wherein a collector of the power switch is arranged in series with an inductive element of the power
converter: —wherein the control circuit is configured to
determine an indication of a time instant, at which the power switch is switched off;
adjust a basis current for controlling the power switch based on a time interval between a time instant, at which the switching
off of the power switch was initiated, and the time instant, at which the power switch is switched off;

determine an indication of an emitter current of the power switch; and
determine an indication of a collector current of the power switch based on the indication of the emitter current by offsetting
the indication of the emitter current with an offset; wherein the offset is dependent on a characteristic of the inductive
element.

US Pat. No. 9,471,071

APPARATUS, SYSTEM AND METHOD FOR VOLTAGE REGULATOR WITH AN IMPROVED VOLTAGE REGULATION USING A REMOTE FEEDBACK LOOP AND FILTER

Dialog Semiconductor (UK)...

1. A voltage regulator with improved voltage regulation comprising:
a power management unit (PMU);
a remote load;
a remote feedback network electrically connected to said remote load and whose output is electrically coupled to said power
management unit PMU;

a printed circuit board (PCB) comprising at least one said printed circuit board (PCB) trace electrically coupling said power
management unit (PMU) and said remote load;

a filtering capacitor; and
a remote feedback loop filter electrically coupled to said filtering capacitor and to said power management unit PMU.

US Pat. No. 9,436,205

APPARATUS AND METHOD FOR LOW VOLTAGE REFERENCE AND OSCILLATOR

Dialog Semiconductor (UK)...

1. A voltage reference circuit between a power supply node and a ground node and configured for generating a reference voltage,
comprising:
a current mirror function providing matching and sourcing network branches wherein a first p-channel MOSFET sources current;
a voltage generator network sourced from said current mirror providing a base-emitter voltage wherein said first p-channel
MOSFET sources current to said voltage generator network;

a current drive function network electrically sourced from said current mirror function wherein a second p-channel MOSFET
sources current for said current drive function;

an output network function sourced from said current mirror providing a voltage reference output voltage;
a first n-channel MOSFET device providing a base-emitter voltage (VBE);
wherein said current mirror function further comprises a third p-channel MOSFET which sources current for said output network
function, and a fourth p-channel MOSFET which sources current for said voltage generator network; and

wherein said voltage generator network comprises:
a first resistor element electrically coupled to the gate of said first n-channel MOSFET device;
a second resistor element electrically coupled to the gate of said first n-channel MOSFET device providing a PTAT function;
and,

a second n-channel MOSFET device whose MOSFET gate and MOSFET drain are electrically coupled to said second resistor element.

US Pat. No. 9,326,336

DUAL SWITCHER FLYBACK STRUCTURE FOR LED DRIVER

Dialog Semiconductor (UK)...

1. A controller for controlling a power converter to convert electrical power at an input voltage into electrical power at
an output voltage; wherein
the power converter comprises
a first switcher stage comprising a primary winding of a transformer which is arranged in series with a first power switch;
wherein the first switcher stage is arranged in parallel to the input voltage at an input of the power converter;

a second switcher stage comprising an auxiliary winding of the transformer which is arranged in series with a second power
switch;

wherein the second switcher stage is arranged in parallel to a reservoir capacitor; and
a secondary winding of the transformer which is arranged in parallel to the output voltage at an output of the power converter;
the controller is configured to
determine whether the input voltage is greater or smaller than a pre-determined voltage threshold;
operate the first switcher stage to transfer electrical power from the input of the power converter to the output of the power
converter, during a first time period when the input voltage is greater than the pre-determined voltage threshold; and

operate the second switcher stage to transfer electrical power from the reservoir capacitor to the output of the power converter,
during a second time period when the input voltage is smaller than the pre-determined voltage threshold.

US Pat. No. 9,407,144

METHOD FOR A CURRENT MODE BUCK-BOOST CONVERTER

Dialog Semiconductor (UK)...

7. A buck-boost converter with improved performance configured to generate separated Buck mode and Boost mode pulses, operating
with current mode control and having a continuous control signal, comprising:
circuitry configured for current sensing and slope ramp generation providing a first input to a buck-side comparator, wherein
a circuitry configured for error amplification and network compensation provides a control voltage VC,Buck as second input to the buck-side comparator, and wherein an output of the buck-side comparator provides a reset input to a
buck-side switching circuit configured to generate a buck duty cycle;

said circuitry configured for error amplification comprising a loop filter, generating a buck mode control voltage Vc,buck control voltage, and operating a compensation network, wherein said circuitry configured for error amplification has inputs
and an output, wherein a first input is a reference voltage, a second input is an output voltage of the buck-boost converter;

said buck-side comparator;
a circuitry configured for controlling a boost side comparator in relation to the buck mode control voltage Vc,Buck by generating a boost mode control voltage Vc,Boost, based on the buck mode control voltage Vc,Buck, according to an equation:
Vc,Boost=Vc,Buck??Vc, wherein Vc,Buck is the buck mode control voltage, and ?Vc defines a voltage shift, wherein the circuitry configured for controlling the boost side comparator has an input and an output,
wherein the input is the buck mode control voltage Vc,Buck and the output is the boost mode control voltage Vc,Boost, which is a second input to the boost side comparator;
said boost side comparator, wherein a boost-side circuitry configured for current sensing and slope ramp generation provides
a first input to the boost-side comparator and an output of the boost side comparator is a reset input to a boost-side switching
circuit configured to generate a boost duty cycle;

said buck-side switching circuit configured to generate a buck duty cycle, wherein a set input of the buck-side switching
circuit activates the generation of the buck duty cycle and an output of the buck-side switching circuit BuckFFOut is a first
input to a circuit configured to ensure that a buck-side switch is ON during boost mode;

wherein said buck-side switch is configured to generate buck mode pulses;
wherein said circuitry is configured to ensure that the buck-side switch is ON during Boost mode, wherein a signal BoostNext
is a second input;

wherein said boost-side switching circuit is configured to generate a boost duty cycle, wherein a set input of the boost-side
switching circuit activates the generation of the boost duty cycle and an output of the boost-side switching circuit controls
a boost side switch;

wherein said boost switch is configured to generate boost mode pulses, wherein the boost switch is OFF during buck mode; and
wherein a circuitry is configured to sample the output BuckFFOut of said buck-side switching circuit, is configured to generate
a buck duty cycle in order to compare the buck duty cycle with a reference buck duty cycle, and is configured to decide whether
a next pulse will be the Buck mode pulse or the Boost mode pulse, wherein an output of the circuitry configured to sampling
the output BuckFFOut is the signal BoostNext.

US Pat. No. 9,294,119

METHOD FOR IMPROVING THE ACCURACY OF AN EXPONENTIAL CURRENT DIGITAL-TO-ANALOG (IDAC) USING A BINARY-WEIGHTED MSB

Dialog Semiconductor (UK)...

1. A method to achieve an exponential current digital-to-analog converter (IDAC) having improved accuracy using a binary-weighted
most significant bit (MSB) comprising:
defining a differential non-linearity (DNL);
defining number of LSB bits needed for the targeted DNL with a binary weighted MSB;
calculating the number of bits to be used for the binary-weighted MSB to get the desired IDAC base;
deriving the minimum current for the Imax;
defining the LSB as an exponential current mirror according to the specified relationship for the ILSB;
defining a binary weighted MSB according to the specified relationship for IMSB; and
defining a differential non-linearity (DNL) according to the definition

US Pat. No. 9,520,788

APPARATUS AND METHOD FOR CURRENT SHARING IN A MULTI-PHASE SWITCHING REGULATOR

Dialog Semiconductor (UK)...

1. A multi-phase switching converter for minimizing direct current (d.c.) current, comprising:
a plurality of phases, wherein each phase comprises a driver circuit, and an output stage configured to connect to an inductor;
a plurality of current sense circuits for measuring current of each phase's output stage;
a current share circuit connected to receive an output of each of said current sense circuits wherein said current sense circuits
comprises a variable gain amplifier; and,

a control circuit for driving each of said driver circuits, wherein said current of each of said output stages is set to differ
among each of said phases, based on direct current (d.c.) resistance of said output stage and of said inductor.

US Pat. No. 9,444,342

CLOCKED PULSE FREQUENCY MODULATION BUCK DC-TO-DC CONVERTER

Dialog Semiconductor (UK)...

1. A hysteretic mode control circuit within a DC-to-DC converter that is configured for operating in a continuous mode or
a discontinuous mode, the hysteretic mode control circuit comprising:
a first current limit circuit configured for determining a first reference limit signal that is used for controlling activation
of a first switch of a switching section of the DC-to-DC converter for transferring current to a load device placed at an
output of the DC-to-DC converter, wherein the first current limit circuit comprises:

a first dynamic current limit circuit comprising:
a first reference current source configured for providing a first maximum reference current;
a first limit current mirror connected such that a reference leg of the first limit current mirror receives the first maximum
reference current and configured such that a mirror leg of the first limit current mirror is connected to provide the first
reference limit signal for an output of the first current limit circuit to determine the switching interval and duration of
the first switch to provide a current to the filter section of the DC-to-DC converter;

a comparator connected to receive the first reference limit signal and a feedback signal from the output of the DC-to-DC converter
and configured for determining if the feedback signal is greater than or less than the first reference limit signal to generate
an output signal; and

a comparison switching device connected to receive the output signal of the comparator that is activated or deactivated to
divert a current from the reference leg of the first limit current mirror and thus modify the current in the reference leg
and thus the mirror leg of the first limit current mirror and thus adjust the voltage level of the first reference limit signal;
and

a pulse width modulation/pulse frequency modulation control circuit configured for receiving the first reference limit signal,
configured for comparing an amplitude of the first reference limit signal with a feedback signal from a power switching section
of the DC-to-DC converter and configured for generating a first reset control signal and a second reset control signal for
controlling deactivation of the first switch and a second switch of the DC-to-DC converter;

wherein the first current limit circuit and the pulse width modulation/pulse frequency modulation control circuit are configured
for varying a current limit that controls an interval and duration of time at which the switching section of the DC-to-DC
converter is switched to permit the DC-to-DC converter to manage large changes in an output current load of the DC-to-DC converter
while operating in the discontinuous operation mode.

US Pat. No. 9,307,590

NON-LINEAR CURRENT IDAC WITH SYNTHESIS IN TIME DOMAIN

Dialog Semiconductor (UK)...

1. A method for supplying a specified electrical current to at least one light emitting diode (“LED”) included in a display
from a current (“I”) digital-to-analog converter (“IDAC”) (60), the IDAC (60) including a plurality of individual current sources/sinks (26):
a. for connecting in parallel to the LED so that a total amount of electrical current flowing through the LED equals the sum
of individual electrical currents respectively flowing through each of the current sources/sinks (26); and

b. at any instant in time connected current sources/sinks (26) being either:

i. turned on for supplying electrical current to the LED; or
ii. turned off thereby supplying no electrical current to the LED,the method for supplying the specified electrical current comprising the steps of:
a. when the specified electrical current exceeds a pre-established current threshold (94), increasing the electrical current flowing through the LED is effected by successively turning on individual current sources/sinks
(26) included in the IDAC (60) that had been previously turned off; and

b. when the specified electrical current is less that the pre-established current threshold (94), increasing the electrical current flowing through the LED is effected by turning on at least one additional current source/sink
(26) included in the IDAC (60) that had been previously turned off, the additional current source/sink (26) being alternatively initially turned on and then subsequently turned off so as to thereby generate a sequence of progressively
longer electrical current pulses (102) until the additional current source/sink (26) remains fully on.

US Pat. No. 9,559,587

HIGH VOLTAGE DC/DC CONVERTER WITH MASTER/SLAVE OUTPUT STAGE

Dialog Semiconductor (UK)...

1. A power converter configured to convert electrical power at an input voltage into electrical power at an output voltage,
wherein the power converter comprises
a first inverter stage with
a first half bridge comprising a first high side switch and a first low side switch which are arranged in series between the
input voltage and a reference voltage; and

a first high side driver for providing a first drive signal for the first high side switch, subject to a high side control
signal at a drive voltage level;

a first high side feedback unit configured to provide a first high side feedback signal by sensing the first drive signal
for the first high side switch;

a second inverter stage with
a second half bridge comprising a second high side switch and a second low side switch which are arranged in series between
the input voltage and the reference voltage; and

a second high side driver for providing a second drive signal for the second high side switch, subject to the high side control
signal at the drive voltage level; and

a second high side feedback unit configured to provide a second high side feedback signal by sensing the second drive signal
for the second high side switch; and

a single level shifting unit configured to convert a high side control signal at a logic voltage level into the high side
control signal at the drive voltage level for driving the first and second high side switches;

a high side combining unit configured to provide a combined high side feedback signal by combining the first and second high
side feedback signals; wherein the high side combining unit comprises an AND gate for combining the first and second high
side feedback signals; and

an inverse level shifting unit configured to shift the combined high side feedback signal from the drive voltage level to
the logic voltage level.

US Pat. No. 9,559,589

HIGH EFFICIENCY SWITCHING BOOST CONVERTER WITH REDUCED INDUCTOR CURRENT RIPPLE

Dialog Semiconductor (UK)...

1. A voltage or current regulated power converter, wherein
the power converter is configured to derive electrical power at an output voltage Vout at an output of the power converter from electrical power at an input voltage Vin at an input of the power converter;

the output voltage Vout is greater than or equal to the input voltage Vin;

the power converter comprises an inductor (L), a plurality of capacitors (C1, C2, C3, Cout) and a plurality of switches (S1, S2, S3, S4, S5, S6, S7), which are arranged within an input unit and an output unit of the power converter;

the input unit and the output unit are coupled via an intermediate point;
the output unit comprises a first output arrangement;
the input unit comprises a first input arrangement;
the power converter comprises a controller configured to control the plurality of switches such that a commutation cycle of
the power converter comprises a plurality of different operation phases;

the first output arrangement comprises
a second capacitor (C2) and a third capacitor (C3) which are arranged in series, wherein the serial arrangement of the second and third capacitor are arranged in parallel
to a positive and a negative contact of the output of the power converter;

a fifth switch (S5) configured to couple the intermediate point to the positive contact of the output;

a fourth switch (S4) configured to couple the intermediate point to a midpoint between the second capacitor and the third capacitor;

a seventh switch (S7) configured to couple the midpoint to ground; and

a sixth switch (S6) configured to couple the negative contact of the output to ground; and

the first input arrangement comprises
a first capacitor (C1) and the inductor (L);

a first switch (S1) configured to couple a second end of the inductor to the intermediate point; wherein a first end of the inductor is coupled
to a positive contact of the input of the power converter; wherein a first end of the first capacitor is coupled to the intermediate
point;

a second switch (S2) configured to couple the second end of the inductor to the second end of the first capacitor; and

a third switch (S3) configured to couple a second end of the first capacitor to ground; wherein a negative contact of the input of the power
converter is coupled to ground.

US Pat. No. 9,513,870

MODULO9 AND MODULO7 OPERATION ON UNSIGNED BINARY NUMBERS

Dialog Semiconductor (UK)...

1. A method to obtain simultaneous results of modulo7 and modulo9 operation on an unsigned number N, the method comprising
the steps of:
(1) representing the unsigned number N in binary format;
(2) Finding-finding a common multiple ‘M’ of 9 and 7 which is the closest to a number “d”, d being a power of 2;
(3) determining Lrem such that 0?Lrem?M, by application of the split-and-accumulate method multiple times if required, wherein
division of N by d (N/d) is performed by splitting binary representation of N into quotient qd and remainder rd, and subsequently adding them together to form the intermediate sum ‘qd+rd’; thereafter if this intermediate sum is greater than M, the split-and-accumulate method is applied again on the sum ‘qd+rd’, this is done repeatedly till the resulting sum ‘qd+rd’ is assured to be less than or equal to M, at which point Lrem is assigned the value of this sum ‘qd+rd’;

(4) determining N modulo7 according to equation N modulo7=(Lrem) modulo 7 by one or more split-and-accumulate operations
(5) determining N modulo9 according to equation N modulo9=(Lrem) modulo 9 by one or more split-and-accumulate operations and
(6) providing a circuitry comprising full adders and logic gates capable of performing full-addition operations, comparison
and multiplexing functions, configured to perform steps 3-5.

US Pat. No. 9,501,080

MULTIPLE OUTPUT OFFSET COMPARATOR

Dialog Semiconductor (UK)...

1. A multiple output comparator configured to compare a first input signal with a second input signal and at least one threshold
offset voltage level, comprising:
a difference circuit configured to receive a first input signal and a second input signal to determine when a magnitude of
the first input signal is greater than or lesser than the second input signal and configured to provide a true output signal
and a complement output signal that are indicative that magnitude of the first input signal is greater than or lesser than
the second input signal;

an output mirror driver circuit in communication with the difference circuit for receiving the true output signal and the
complement output signal comprising:

a first mirror circuit configured for receiving the true output signal from the difference circuit and configured for generating
at least one mirrored true output signal indicating that the first input signal is greater than or lesser than the second
input signal;

a second mirror circuit configured for receiving the complement output signal from the difference circuit and configured for
generating at least one mirrored complement output signal indicating that the first input signal is greater than or lesser
than the second input signal as offset by the at least one threshold offset voltage level wherein the at least one mirrored
complement output signal is combined with an associated at least one mirrored in-phase reference signal to form a plurality
of digital output signals; and

at least one offset generator in communication with the second mirror circuit and configured for accurately generating the
at least one threshold offset voltage level to ensure that the first input signal is greater than or lesser than the second
input signal as offset by the at least one threshold offset voltage level.

US Pat. No. 9,471,077

METHOD TO PRE-SET A COMPENSATION CAPACITOR VOLTAGE

Dialog Semiconductor (UK)...

1. A voltage mode controlled buck converter enabled for smooth transition from sleep mode to active mode, comprising:
a main output stage comprising a high side switch and a low side switch both connected in series, wherein a driver stage is
driving the main output stage;

a coil, wherein a first terminal of the coil is connected to a node between the high side switch and the low side switch and
a second terminal of the coil is connected to an output port of the buck converter configured to providing an output voltage
of the buck converter;

a PWM control loop configured to control the buck converter during active mode, comprising an error amplifier configured to
receiving an output voltage feedback of the buck converter and a reference voltage, a compensation capacitor connected between
an output of the error amplifier and ground, a PWM comparator configured to compare the output of the error amplifier with
an output of a ramp signal generator, and the driver stage driving the main output stage, wherein an output of the PWM comparator
provides input to the driver stage; and

a local PWM feedback loop, capable of, when enabled intermittently during sleep mode, to set an appropriate compensation capacitor
voltage regardless of the length of the sleep period, comprises:

a dummy output stage, comprising a high side switch and a low side switch both connected in series, wherein the dummy output
stage is configured to be driven by the output of the PWM comparator, wherein an output of the dummy output stage is connected
to a filter; and

said filter, configured to provide at its output an emulated output voltage of the buck converter, wherein the output of the
filter is connected, when enabled during sleep mode, to the error amplifier instead of the output voltage feedback the buck
converter during active mode.

US Pat. No. 9,455,710

CLOCK ENABLING CIRCUIT

Dialog Semiconductor (UK)...

1. A clock enabling circuit for providing a gated clock signal (CLK_G) in response to receiving clock request information
(REQ), the clock enabling circuit comprising:
a clock request input for receiving the clock request information (REQ);
a clock input for receiving a clock signal (CLK);
a flip-flop stage comprising at least a first and a second flip-flop, wherein an output of the first flip-flop is coupled
with the input of the second flip-flop;

a first sub-circuitry comprising at least a first input being coupled with the clock request input and an output being coupled
with the flip-flop stage for providing a set information (SET) to the flip-flop stage in response to receipt of the clock
request information (REQ), the flip-flop stage being configured to provide a clock enabling information (CLK_EN) in response
to receiving the set information (SET);

a second sub-circuitry comprising a first and a second input, the first input being coupled with the clock input for receiving
the clock signal (CLK) and the second input being coupled with the output of the flip-flop stage for receiving the clock enabling
information (CLK_EN), the second sub-circuitry comprising a triggering circuitry for providing, based on the clock enabling
information (CLK_EN), a synchronized clock enabling information (sCLK_EN) that is synchronized with an edge of the clock signal
(CLK), an output of the second sub-circuitry providing the gated clock signal in response to the synchronized clock enabling
information (sCLK_EN) and the clock signal (CLK).

US Pat. No. 9,455,717

DIGITAL COUNTER COMPRISING REDUCED TRANSITION DENSITY

Dialog Semiconductor (UK)...

1. A digital counter comprising:
at least a first counting module and a second counting module, said counting modules being serially coupled and forming a
counting module chain;

each counting module comprising at least a first digital storage cell and a second digital storage cell, each counting module
providing module counting information of at least two bits;

said counting modules being operative, during counting, to respectively change only one bit of said module counting information
between two successive counting state;
wherein the counting modules are coupled such that the start of counting of the second counting module is enabled by the first
counting module when said first counting module has passed through all counting states of said first counting module;wherein the digital storage cells of the first counting module comprise level-triggered latches and wherein the digital storage
cells of the first counting module are triggered by clock signals that are inverted with respect to each other; andwherein the digital storage cells of higher order counting modules comprise edge-triggered flip-flops.

US Pat. No. 9,323,265

VOLTAGE REGULATOR OUTPUT OVERVOLTAGE COMPENSATION

Dialog Semiconductor (UK)...

1. A multi-stage amplifier comprising
a pass device configured to source a load current at an output voltage to an output node; wherein the load current is drawn
from a high potential of the multi-stage amplifier;

a first driver circuit configured to control the pass device based on a reference voltage and based on a first feedback voltage
derived from the output voltage;

a sink transistor arranged in series with the pass device and configured to sink a first current from the output node to a
low potential of the multi-stage amplifier; wherein the output node corresponds to a midpoint between the pass device and
the sink transistor;

a bypass transistor configured to couple a sense voltage which is derived from the output voltage to the low potential, to
sink a second current from the output node to the low potential;

a second driver circuit configured to control the sink transistor and the bypass transistor, based on the reference voltage
and based on a second feedback voltage derived from the output voltage; and

a voltage divider arranged between the output node and the low potential and configured to derive the first feedback voltage,
the second feedback voltage and the sense voltage from the output voltage, such that the sense voltage is higher than the
first feedback voltage and such that the first feedback voltage is higher than the second feedback voltage.

US Pat. No. 9,214,953

GENERALIZED DATA WEIGHTED AVERAGING METHOD FOR EQUALLY WEIGHTED MULTI-BIT D/A ELEMENTS

Dialog Semiconductor (UK)...

1. A binary to thermometer encoder within a DAC circuit comprising:
a row element selector in communication with a multi-bit delta/sigma modulator to receive an oversampled binary coding representing
an amplitude of a sampling of an analog signal and configured for decoding the oversampled binary coding;

a binary to thermometer code conversion array in communication with the row element selector to receive the decoded oversampled
binary coding for selecting one element row of the binary to thermometer code conversion array and configured for retaining
or generating a multi-bit code representing an amplitude to be developed by each of DAC element of the DAC circuit; and

a plurality of column drivers configured such that each column is driver amplifies and conditions the output of each element
of one selected row for transfer through a rotational dynamic element matching circuit to one DAC element;

wherein contents of any row of the binary to thermometer code conversion array is determined as a product of each element
of a signed binary to thermometer code conversion array and a remainder of an non-Euclidian division of the signed numeric
designation of one row of a signed binary to thermometer code conversion array by a number of DAC elements within the DAC
circuit and added to the quotient of the non-Euclidian division, wherein the remainder has the same sign as the numeric designation
of the one row; and

wherein, the binary to thermometer code conversion array is assembled by repetitively executing the formula for determining
the contents of the rows of the binary to thermometer code conversion array.

US Pat. No. 9,207,696

ROBUST SINK / SOURCE OUTPUT STAGE AND CONTROL CIRCUIT

Dialog Semiconductor (UK)...

1. A multi-stage amplifier comprising
a first amplification stage configured to activate or to deactivate a first output stage in response to an input voltage at
an input node;

the first output stage configured to source a current at an output node of the multi-stage amplifier from a high potential,
when activated;

a second amplification stage configured to activate or to deactivate a second output stage in response to the input voltage
at the input node; and
the second output stage configured to sink a current at the output node of the multi-stage amplifier to a low potential, when
activated; wherein the first amplification stage and the second amplification stage are configured to activate the first output
stage and the second output stage in a mutually exclusive manner, wherein
the first amplification stage comprises
a first current source configured to provide a first current; and
a first input transistor arranged in series with the first current source; wherein a gate of the first input transistor is
coupled to the input node; wherein the first amplification stage is configured to control a voltage level at a first midpoint
between the first current source and the first input transistor, subject to the input voltage at the input node; wherein the
first output stage is coupled to the first midpoint; and

the second amplification stage comprises
a second current source configured to provide a second current; and
a second input transistor arranged in series with the second current source; wherein a gate of the second input transistor
is coupled to the input node; wherein the second amplification stage is configured to control a voltage level at a second
midpoint between the second current source and the second input transistor, subject to the input voltage at the input node;
wherein the second output stage is coupled to the second midpoint.

US Pat. No. 10,033,285

SECONDARY CONTROLLER FOR A FLYBACK CONVERTER INCLUDING A SENSE RESISTOR FAULT DETECTION

DIALOG SEMICONDUCTOR INC....

1. A secondary controller for a flyback converter, comprising; a measurement circuit configured to measure a sense resistor voltage across a sense resistor connected in series with a secondary winding in the flyback converter, wherein the measurement circuit comprises an operational amplifier having a first input connected through a first resistor to a first terminal of the sense resistor and having a second input connected through a second resistor to a second terminal of the sense resistor; an analog-to-digital converter; and a matched pair of current-source transistors such that an output of the operational amplifier is coupled to a gate of each current-source transistor and such that a source of a first one of the current-source transistors is coupled to the first input of the operational amplifier and a source of a second one of the current-source transistors is coupled to provide an input to the analog-to-digital converter; and a logic circuit coupled to the measurement circuit and configured to switch off an output power switch for the flyback converter responsive to the sense resistor voltage exceeding a first threshold.

US Pat. No. 9,641,369

CIRCUITS AND METHODS FOR DECODING AMPLITUDE MODULATED DATA SIGNALS FROM LARGE AMPLITUDE SINE WAVE CARRIER

Dialog Semiconductor (UK)...

1. A decoding circuit configured for assembling telegram data patterns from multiple encoded digital data frames demodulated
from a low frequency, large amplitude carrier signal modulated with higher frequency, multiple encoded digital data frames,
the decoding circuit comprising:
a period timer to establish an inter-transition time period between each transition within each of the multiple encoded digital
data frames wherein, the inter-transition time period is the time between each transition of the encoded digital data frames
between a first data level and a second data level and between the second data level and the first data level;

an inter-transition comparator in communication with the period timer and configured to compare each of the inter-transition
time periods with valid inter-transition time periods between each transition of the encoded digital data frames for determining
when the inter-transition time periods represent valid data frame patterns or are an error;

a data extractor configured to receive valid encoded digital data frames from the inter-transition comparator for extracting
transmitted digital data frames from within the valid data encoded digital data frames; and

a command formatter configured to receive the extracted digital data frames from the data extractor for assembling the telegram
data patterns for transfer for subsequent processing.

US Pat. No. 9,563,730

IMPROVING THE ACCURACY OF AN EXPONENTIAL CURRENT DIGITAL-TO-ANALOG CONVERTER (IDAC) USING A BINARY-WEIGHTED MSB

Dialog Semiconductor (UK)...

1. An apparatus for driving light emitting diode (LED) elements comprising:
an error amplifier;
a pulse width modulation comparator electrically connected to an output of said error amplifier;
a DC-DC converter electrically connected to an output of said pulse width modulation comparator and an output pad;
at least one light emitting diode (LED) electrically connected to an input of said error amplifier and to an output of a most
significant bit (MSB) network;

an output buffer having inputs and an output, wherein a first input is connected to the output of the MSB network and a second
input is connected to a drain of a MSB diode element and to a source of a control transistor and the output of the output
buffer is connected to a gate of the control transistor, wherein the output buffer creates an active cascode at an output
of the MSB network, which is also an output stage of an exponential current digital-to-analog converter (IDAC), wherein a
current through the control transistor is proportional to an output current of the MSB network flowing through the at least
one LED;

said control transistor having its drain connected to a drain of a first p-type transistor of a first current mirror, wherein
the gate of the first p-type transistor is connected to the gate of a second p-type transistor, and the first current mirror
is formed of the first and second p-type transistors wherein the sources of both transistors of the first current mirror are
connected to VDD voltage and the drain of the second p-type transistor is connected to an output current of a least significant
bit (LSB) network network;

wherein the IDAC comprises a least significant bit exponential current IDAC (LSBIDAC) comprising the LSB network and a binary
weighted most significant bit exponential current IDAC (MSBIDAC) comprising the MSB network, wherein a desired value of the
IDAC output current is set by a digital word whose first n bits form the most significant part (MSB code) and whose last bits
form the least significant bit part (LSB code), wherein said binary weighted most significant bit (MSBIDAC) is electrically
connected to said cathode of said light emitting diode (LED) and to an input of said error amplifier;
wherein said MSB network comprises:
said MSB diode element having its source connected to a voltage source and its gate to gates of a multitude of MSB current
mirror transistors;

said multitude of the MSB current mirror transistors, having their sources connected to the voltage source and each drain
of the current mirror transistors is connected to a first terminal of an own MSB code switch, wherein the number of the MSB
current mirror transistors corresponds to the number of bits in the MSB part of the digital word and wherein the sizes of
the MSB current mirror transistors are binary weighted in relation to the size of the MSB diode element depending on a relative
position within the MSB part of the digital word according to the equation: size=1/C×2MSB pos-1, wherein the position to find where each MSB current mirror transistor is located in a parallel deployment of transistors
in the MSB network, C corresponds to the size of the MSB diode element and MSBpos corresponds to the position of a MSB current mirror transistor related to a position of a correspondent bit of the MSB code;
and

said MSB code switches, wherein the second terminals of the MSB code switches are all connected to the output of the MSB network,
wherein each switch is closed or open according to the value of a correspondent bit of the MSB code, wherein the correspondent
bit relates to the position of the correspondent MSB current transistor it is connected to;
wherein the output current of the LSB network is mirrored by the first current mirror, furthermore flowing through the control
transistor, which is controlled by the buffer and is then mirrored by the current mirror formed by the MSB diode element and
the MSB current mirror transistors to become, dependent on the status of the switches, the output current of the exponential
current digital-to-analog converter (IDAC) is driving the LED elements.

US Pat. No. 9,461,487

BATTERY STACK CONFIGURATION IN A MULTI-BATTERY SUPPLY SYSTEM

Dialog Semiconductor (UK)...

1. A battery powerable device comprising:
i. at least two (2) rechargeable batteries;
ii. both:
a. at least one (1) buck DC-DC converter; and
b. at least one (1) boost DC-DC converter, each DC-DC converter having a power input that receives electrical power for energizing
DC-DC converter operation; and

iii. a power management circuit that:
a. when the device is connected to an electrical power source for recharging the batteries, connects the batteries in parallel
and the parallel connected batteries being connected to the power inputs of both the buck DC-DC converter and boost DC-DC
converter for energizing the operation thereof; and

b. when the device is not connected to an electrical power source for recharging the batteries, connects the batteries in
series with:

1. the series connected batteries being connected to the power input of the boost DC-DC converter for energizing the operation
thereof; and

2. one of the series connected batteries being connected to the power input of the buck DC-DC converter for energizing the
operation thereof,
whereby during battery powered operation of the device the boost DC-DC converter operates more efficiently in comparison with
operation thereof that is energized by the batteries connected in parallel.

US Pat. No. 10,034,336

CONTROLLING OUTPUT VOLTAGE TO ACHIEVE ULTRA-LOW STANDBY POWER IN DIM-TO-OFF LED APPLICATIONS

DIALOG SEMICONDUCTOR (UK)...

1. An electronic device, comprising:an integrated circuit (IC) configured to regulate an output voltage for powering a light emitting diode (LED);
a first transistor configured to be switched on or off by the IC to inductively couple or decouple a main power supply bus voltage from a primary winding of a transformer to a secondary winding of the transformer connectable to the LED; and
a second transistor coupled between the IC and the main power supply bus voltage, and configured to be switched on or off by the IC to selectively provide an IC power supply input voltage to the IC,
wherein the second transistor is configured to be switched on in response to:
the IC decreasing the output voltage to less than about one-third of a nominal operating voltage of the LED, and
detecting that the IC power supply input voltage is less than a first threshold voltage.

US Pat. No. 9,501,605

AUTO-CONSTRAINT CHIP-LEVEL ROUTING

Dialog Semiconductor (UK)...

1. A method of routing signal lines of an integrated circuit, IC, performed by a computer, wherein the IC comprises a plurality
of circuit topologies and a plurality of signal lines connecting the circuit topologies, the method comprising steps of:
receiving a first representation of the IC, the first representation of the IC relating to a netlist or a schematic database;
comparing, based on the first representation, the circuit topologies of the IC against a set of reference circuit topologies;
classifying signals propagating along respective signal lines of the IC into a plurality of categories based on a result of
the comparison; and

routing the signal lines of the IC in accordance with the categories of their respective signals, thereby generating a second
representation of the IC, the second representation of the IC relating to a layout for the IC that includes a relative arrangement
of the signal lines,

wherein the categories are representative of characteristics of the signals propagating along respective signal lines with
regard to mutual interference between signals.

US Pat. No. 9,958,487

METHOD AND APPARATUS FOR POWERING AN ELECTRONIC DEVICE

Dialog Semiconductor (UK)...

1. An apparatus for monitoring a process of powering an electronic device through a cable assembly, the cable assembly comprising a cable connected between a power supply and said electronic device, the apparatus comprising:a synchronization signal generator configured to generate a synchronization signal at a predetermined frequency;
a test signal generator configured to generate, based on the synchronization signal, a test signal and to apply the test signal to one end of the cable;
a filter unit configured to detect a response signal at the one end of the cable, the response signal resulting from applying the test signal to the cable assembly; andan impedance estimation unit configured to determine, based on the response signal and based on the synchronization signal, a first quantity indicative of a real part of an impedance of the cable assembly and a second quantity indicative of an imaginary part of the impedance of the cable assembly, wherein the impedance estimation unit further comprisesa first switching unit configured to apply, triggered by the synchronization signal, the response signal to an input of a first low pass filter; and
a second switching unit configured to apply, triggered by an inverted version of the synchronization signal, the response signal to an input of a second low pass filter.

US Pat. No. 9,608,582

METHOD FOR AN ADAPTIVE TRANSCONDUCTANCE CELL UTILIZING ARITHMETIC OPERATIONS

Dialog Semiconductor (UK)...

1. A operational transconductance amplifier, comprising:
a) a first and second voltage controlled current source circuit configured to provide an output current dependent on the product
of the output current of the first voltage controlled circuit, and the quotient of the input voltage of the second voltage
controlled current source circuit and the input voltage of the first voltage controlled current source circuit;

b) each of said voltage controlled current source circuits having an adaptive transconductance cell connected to a bias, set
by a feedback loop.

US Pat. No. 9,594,391

HIGH-VOLTAGE TO LOW-VOLTAGE LOW DROPOUT REGULATOR WITH SELF CONTAINED VOLTAGE REFERENCE

Dialog Semiconductor (UK)...

1. A low-dropout (LDO) regulator circuit providing a regulated, temperature compensated output voltage down from a high-voltage
supply comprising:
an output branch, comprising: a port for the regulated output voltage, a voltage-divider resistor network connected between
said port for the regulated output voltage and ground, wherein the resistor network is configured to provide a voltage (VBE1) which is connected to a base of a first transistor, wherein a current through the output branch is provided by an operational
amplifier;

an emulated proportional to absolute temperature (PTAT) circuit configured to generate a temperature-independent current through
a first transistor which is used as a reference current, wherein the PTAT circuit comprises;

a PTAT resistor having its first terminal connected to a node of the output branch, which is between a first and the second
resistor of the voltage divider resistor network and its second terminal connected to a collector and a base of a second transistor;
and

said second transistor having its base connected to a base of a third transistor and its emitter connected to ground voltage,
wherein the reference current through the second transistor is mirrored in a first current mirror by a ratio of N:1 to the
third transistor, wherein current mirror factor N is an integer number higher than 1;

said operational amplifier configured to inject current into the output branch; and
a second current mirror mirroring the current through the third transistor by a first p-channel MOSFET using a current mirror
ratio of 1:N, wherein N is the same current mirror factor as used by the first current mirror, to a second p-channel MOSFET,
wherein the current through the second MOSFET is flowing through the first transistor to ground and wherein a voltage of a
node between the second MOSFET and the first transistor is a regulation voltage of the operational amplifier; wherein the
first and the second current mirrors are configured to compare the reference current through the second transistor with the
current through the first transistor and a comparison result raises or lowers the voltage (VCTL) that regulates the operational
amplifier, wherein the voltage (VCTL) that regulates the operational amplifier is ground referenced for better PSSR and noise
immunity.

US Pat. No. 9,729,075

HIGH EFFICIENCY DC-TO-DC CONVERTER WITH ADAPTIVE OUTPUT STAGE

Dialog Semiconductor (UK)...

1. A power converter, comprising:
an adaptive output with a number of selected stages;
a first adaptive transconductance block whose inputs are electrically coupled to a sensor whose outputs are sense voltage,
average load current and power supply voltage configured to evaluate resistive power terms;

multiplier block configured to multiply a capacitor current by the number of selected stages to generate capacitive power
terms; and

a comparator configured to compare said resistive power terms and said capacitive power terms for determining the number of
selected stages of said adaptive output.

US Pat. No. 10,020,743

SINGLE STAGE SWITCHING POWER CONVERTER WITH IMPROVED PRIMARY ONLY FEEDBACK

DIALOG SEMICONDUCTOR INC....

1. A method of controlling a switching power converter, comprising:rectifying an AC mains voltage to produce a rectified sinusoidal voltage at an input of a primary winding of a transformer while cycling a power switch connected to the primary winding, wherein cycling the power switch comprises cycling the power switch through a series of power switch cycles, wherein each power switch cycle includes an on time for the power switch and an off time for the power switch;
during the on time for each power switch cycle, determining whether a current through the power switch is greater than a threshold value to classify each power switch cycle into either a trustable power switch cycle in which the current through the power switch is greater than the threshold value or into a non-trustable power switch cycle in which the current through the power switch cycle is not greater than the threshold value;
during the off time for each trustable power switch cycle, sensing a primary-only feedback voltage using primary-only feedback to regulate the cycling of the power switch; and during the off time for each non-trustable power switch cycle, interpolating from the primary-only feedback voltage to regulate the cycling of the power switch.

US Pat. No. 9,755,517

MULTI-THRESHOLD PANIC COMPARATORS FOR MULTI-PHASE BUCK CONVERTER PHASE SHEDDING CONTROL

Dialog Semiconductor (UK)...

1. A control circuit included within a multi-phase switched-mode converter and configured for adjusting operational signals
for operating a master power stage and a plurality of slave power stages of the multi-phase switched-mode converter to dynamically
respond to transient changes in load current, comprising:
a plurality of panic comparators, each panic comparator having an input terminal connected to receive a feedback voltage indicative
of an output voltage of the multi-phase switched-mode converter;

a plurality of panic reference voltage sources, each panic reference voltage source is connected to a reference terminal of
one panic comparator to provide a panic reference voltage to the one panic comparator, wherein each of the plurality of panic
comparators is configured to compare the feedback voltage with an associated panic reference voltages to generate one panic
indicator signal of a plurality of panic indicator signals at an output terminal of each of the panic comparators;

a pulse frequency modulation comparator connected for receiving the feedback voltage and configured for generating a discontinuous
control signal;

a pulse frequency modulation reference voltage source providing a pulse frequency modulation reference voltage to the pulse
frequency modulation comparator for comparison with the feedback voltage for determining if the feedback voltage is less than
or greater than the pulse frequency modulation reference voltage; and

a phase controller configured for activating and deactivating a master power stage and a plurality of slave power stages of
the multi-phase switched-mode converter, the phase controller comprising:

a pulse frequency modulation controller in communication with the pulse frequency modulation comparator for receiving the
discontinuous control signal and in communication with at least one of the plurality of panic comparators for receiving at
least one of the plurality of panic indicator signals and configured for providing conduction mode control signals to the
master power stage for operating in a discontinuous conduction mode of operation, wherein when the feedback voltage is greater
than a voltage level of the pulse frequency modulation reference voltage, the multi-phase switched-mode converter operates
in the discontinuous mode of operation and wherein when the feedback voltage is less than at least one of the panic reference
voltage levels, the multi-phase switched-mode converter operates in the continuous mode of operation;

a panic controller connected to each of the output terminals of the plurality of panic comparators to receive the plurality
of panic indicator signals from the plurality of panic comparators signifying that the feedback voltage is less than the panic
reference voltage of a second of the plurality reference voltage sources, wherein the panic controller determines which of
the slave power stages are to be activated to match the transient change to the load current.

US Pat. No. 9,660,703

ELECTRONIC CIRCUIT AND SYSTEM FOR WIRELESS CHARGING

DIALOG SEMICONDUCTOR (UK)...

1. An electronic circuit for a portable battery-powered electronic device, the electronic circuit being operable in a first
mode as an actuator and in a second mode as a wireless charging receiver;
wherein the electronic circuit comprises:
an electromechanical actuator comprising an inductor;
a capacitance selectively connectable to the inductor, at least in the second mode, to form therewith a resonant circuit for
inductively receiving an electromagnetic wireless charging signal; and

a multi-mode switching circuitry comprising one or more switching devices for switching the electronic circuit between its
different modes, at least one of the switching devices being configurable as a rectifying device, wherein:

in the first mode, the switching circuitry is configured to connect the actuator to an electrical power input of the electronic
circuit; and

in the second mode, the switching circuitry is configured as a rectifier circuit for rectifying a voltage induced in the resonant
circuit in response to a received electromagnetic wireless charging signal and for providing the rectified voltage at a power
output of the electronic circuit as a charging voltage for a battery of the portable electronic device, wherein said at least
one configurable switching device is configured as a rectifying device of the rectifier circuit.

US Pat. No. 9,484,899

DEBOUNCE CIRCUIT WITH DYNAMIC TIME BASE ADJUSTMENT FOR A DIGITAL SYSTEM

Dialog Semiconductor (UK)...

1. A debounce circuit for eliminating noise, glitches, or transient signal variations resulting from mechanical bounce in
electronic or mechanical devices occurring at an initiation of a change of state of at least one analog signals such that
the debounce circuit supports a dynamic debounce period alteration and time base variation without loss of the current debounce
state, the debounce circuit comprising:
a physical counter configured for being disposed within a virtual counter defined to have a number of bits sufficient to generate
a filter time for filtering the noise, glitches, or transient signal variations resulting from mechanical bounce occurring
at an initiation of a change of state of the at least one analog input signal from a source device;

a debounce clock controller configured for providing a fundamental clock to the physical counter, at least one time base signal
indicating a location within the virtual counter that the physical counter is situated within the virtual counter for generating
a debounce time to eliminate the noise, glitches, or transient signal variations resulting from mechanical bounce based on
a required debounce time of the at least one analog signal, at least one timer strobe configured to be a submultiple of and
aligned with the fundamental clock for incrementing the physical counter at the indicated location within the virtual counter
such that the least significant binary digit of the physical counter is located at the virtual location in the virtual counter
where two raised to the virtual location of the beginning binary digit of physical counter is the submultiple of the clock
determining the strobe time, and a debounce threshold indicating a count of the virtual counter at which the debounce time
has elapsed; and

a virtual debounce controller in communication with the physical counter and the debounce controller, configured for defining
the location of the physical counter within the virtual counter as defined by the at least one time base signal, and determining
when the count of the virtual counter has exceeded the debounce threshold.

US Pat. No. 9,705,399

ADAPTIVE THRESHOLD OF A ZERO CROSSING COMPARATOR

Dialog Semiconductor (UK)...

1. A buck converter device comprising:
a high-side switch device with a first parasitic bipolar junction transistor configured to provide a first sense signal depending
from a current flowing through the first parasitic bipolar junction transistor to a zero-cross comparator;

a low-side switch device with a second parasitic bipolar junction transistor configured to provide a second sense signal depending
from current flowing through the second parasitic bipolar junction transistor to the zero-cross comparator;

a sense capacitive element, wherein a first terminal of the sense capacitive element is connected to ground and a second terminal
of the sense capacitive element is connected to the zero-cross comparator, directly connected to a collector of the first
parasitic bipolar junction transistor and directly connected to a collector of the second parasitic bipolar junction transistor,
wherein the sense capacitive element is configured to provide an offset adjustment from said first and second sense signals
combined to the zero-cross comparator; and

the zero-cross comparator with an adaptive threshold configured with the offset adjustment provided from said first sense
signal and said second sense signal combined via said sense capacitive element.

US Pat. No. 9,705,559

METHOD AND APPARATUS FOR POWERING A PORTABLE DEVICE

Dialog Semiconductor (UK)...

13. An apparatus for monitoring a process of powering a portable device through a cable connected between a power supply and
said portable device, the apparatus comprising:
a current sink for applying a time-dependent current variation to one end of the cable in accordance with a spreading sequence;
voltage detecting means for detecting a time-dependent voltage variation at the one end of the cable, the time dependent voltage
variation resulting from said applying of the time-dependent current variation; and

computing means for determining a quantity indicative of an impedance of the cable assembly based on the time-dependent voltage
variation and the spreading sequence,

wherein the computing means comprises a multiplicator adapted to multiply the time-dependent voltage variation with the spreading
sequence, a numerical integrator adapted to time-average the result of said multiplication, and an impedance calculator adapted
to calculate the quantity indicative of the impedance of the cable assembly based on the time average.

US Pat. No. 9,651,960

CONSTANT OUTPUT AMPLIFIER

Dialog Semiconductor (UK)...

1. A multi-stage amplifier comprising
a first amplification stage configured to activate or to deactivate a first output stage in response to an input voltage at
an input node;

the first output stage configured to source a current at an output node of the multi-stage amplifier from a high potential,
when activated;

a second amplification stage configured to activate or to deactivate a second output stage in response to the input voltage
at the input node; and

the second output stage configured to sink a current at the output node of the multi-stage amplifier to a low potential, when
activated; wherein the first amplification stage and the second amplification stage are configured to activate the first output
stage and the second output stage in a mutually exclusive manner, wherein

the first output stage comprises
a first control transistor having a gate which is coupled to the first amplification stage, and being configured to vary a
first control current through the first control transistor, subject to a voltage level at the gate of the first control transistor;
and

a first output amplifier configured to source an amplified version of the first control current to the output node; and
the second output stage comprises
a second control transistor having a gate which is coupled to the second amplification stage, and being configured to vary
a second control current through the second control transistor, subject to a voltage level at the gate of the second control
transistor; and

a second output amplifier configured to sink an amplified version of the second control current at the output node.

US Pat. No. 10,075,121

PWM ACTUATOR CONTROL WITH PULSE REGULATION

Dialog Semiconductor (UK)...

1. A driver circuit for generating a sequence of pulses of a drive voltage from a supply voltage, wherein the drive voltage is used for operating an electrical actuator, wherein the driver circuit comprises,a sensing unit for providing an amplitude indication of an amplitude of the supply voltage, which is used for generating a first pulse of the sequence of pulses; wherein the sensing unit for providing an amplitude indication comprises a resistor which is arranged between the actuator and an integration unit; and
wherein the amplitude indication corresponds to a current through the resistor;
the integration unit configured to integrate the amplitude indication for a duration of the first pulse, thereby generating an integrated voltage;
a comparator configured to compare the integrated voltage with a reference voltage, thereby generating a comparator signal; wherein the reference voltage is indicative of a target energy which is to be provided to the actuator using the first pulse; and
a control unit configured to
terminate the first pulse in dependence of the comparator signal; and
initiate the generating of a pulse of the sequence of pulses in dependence of a pulse trigger signal; wherein the pulse trigger signal comprises triggers at a trigger frequency.

US Pat. No. 9,622,300

RESONANCE CONVERTER FOR DRIVING MULTIPLE AC LED STRINGS

Dialog Semiconductor (UK)...

1. An SSL assembly comprising
an alternating current, referred to as AC, solid state lighting, referred to as SSL, unit; wherein the AC SSL unit comprises
at least two SSL devices which are arranged in an anti-parallel manner with respect to one another; and

a driver circuit which comprises a resonant circuit that is configured to adapt an input AC drive voltage at an input of the
resonant circuit into an output AC drive voltage; wherein the output AC drive voltage is applied to the AC SSL unit; wherein

the SSL assembly comprises a plurality of AC SSL units which are arranged in parallel with respect to one another;
the driver circuit comprises a corresponding plurality of resonant circuits; wherein each resonant circuit of the plurality
of resonant circuits for a corresponding AC SSL unit of the plurality of AC SSL units exhibits a resonance frequency which
is dependent on an on-voltage of the corresponding AC SSL unit; and

each of the plurality of resonant circuits is configured to adapt the input AC drive voltage at the input of the respective
resonant circuit into an output AC drive voltage which is applied to the respective AC SSL unit.

US Pat. No. 9,887,535

SHORT CIRCUIT PROTECTION FOR A POWER SWITCH

Dialog Semiconductor (UK)...

1. A power providing circuit which is configured to provide a current at an output voltage to a load at an output of the power
providing circuit, wherein the power providing circuit comprises,
a power transistor which is configured to draw the current from a supply voltage, wherein a resistance of the power transistor
is controlled using a control voltage which is applied to a control port of the power transistor; and

short circuit protection circuitry which is configured to couple the control port of the power transistor with a first port
of the power transistor to put the power transistor in an off-state, subject to a drop of the output voltage; wherein the
short circuit protection circuitry comprises a short circuit control transistor which comprises a first port and a second
port which are configured to couple the control port and the first port of the power transistor; wherein a state of the short
circuit control transistor is controlled via a control port of the short circuit control transistor; and wherein a voltage
level at the control port of the short circuit control transistor depends on the output voltage; wherein the short circuit
protection circuitry is configured to couple the control port with the first port of the power transistor within a first reaction
time interval, subject to the drop of the output voltage; and

current limit circuitry which is configured to limit the current through the power transistor in accordance to a pre-determined
current limit; wherein the current limit circuitry is configured to limit the current through the power transistor in accordance
to the pre-determined current limit within a second reaction time interval, subject to the drop of the output voltage; and
wherein the first reaction time interval is smaller than the second reaction time interval.

US Pat. No. 9,693,417

LED MAINS VOLTAGE MEASUREMENT USING A CURRENT MIRROR

Dialog Semiconductor (UK)...

1. A measurement circuit configured to provide a sensed input voltage indicative of an input voltage, wherein the measurement
circuit comprises
a first resistor which is configured to be coupled at a first side to the input voltage;
current mirror circuitry coupled at an input to a second side of the first resistor, which is opposite to the first side of
the first resistor, and configured to translate an input current at the input of the current mirror circuitry into an output
current at an output of the current mirror circuitry, such that the output current is proportional to the input current by
a current mirror ratio;

a second resistor coupled to the output of the current mirror circuitry and configured to provide the sensed input voltage,
when the input voltage is coupled to the first side of the first resistor; and

a source follower circuit arranged between the second side of the first resistor and the input of the current mirror circuitry;
wherein the source follower circuit is configured to set a voltage level of the second side of the first resistor to a pre-determined
reference voltage.

US Pat. No. 9,672,878

MEMORY CIRCUIT

Dialog Semiconductor (UK)...

1. A memory circuit comprising
an input to receive a logic signal, and an output to output an output logic value; and
a plurality of logic elements, the plurality of logic elements being arranged such that, upon powering the memory circuit,
the output logic value has a greater probability of settling to a first logic value than a second logic value.

US Pat. No. 9,606,559

MULTI-PHASE SWITCHING CONVERTER WITH PHASE SHEDDING

Dialog Semiconductor (UK)...

1. A multi-phase switched-mode converter circuit configured for dropping or shedding and adding phases to dynamically maintain
an operating load while continuing to provide efficient operation and avoid any transient changes to an output voltage multi-phase
switched-mode converter circuit, the multi-phase switched-mode converter circuit comprising:
a control circuit configured to adjust operational signals of a master power stage and a plurality of slave power stages of
the multi-phase switched-mode converter circuit, the control circuit comprising:

a phase shedding control circuit configured to receive a shed threshold signal from a phase threshold comparator indicating
that a total output current magnitude has fallen below a total current magnitude threshold level such that the multi-phase
switched-mode power converter circuit is no longer operating efficiently and configured to generate a plurality of phase shedding
signals and a plurality of slave phase target signals, wherein each of the plurality of phase shedding signal is transferred
to one of the plurality of slave power stages; and

a plurality of phase control and feedback sections where in a master phase control and feedback section is connected to the
master power stage and each remaining phase control and feedback section is connected to one of the plurality of slave power
stages, wherein each of the plurality of phase control and feedback sections comprises:

a slave phase shedding switch comprising:
a common switching pole in communication with a current share amplifier of one of the slave power stages,
a first select pole connected to receive a phase target current level from a phase current sense circuit within the master
power phase,

a second select pole connected to receive a phase zero target current level from a target current voltage source, and
a control terminal connected to receive one of the slave phase target signals from the phase shedding control circuit such
that the slave phase shedding switch transfers a connection between the first pole and the common pole when the plurality
of slave power stages are operating to a connection between the second pole and the common pole to apply the phase zero target
current level to a current sense amplifier within each phase control and feedback section to bring an output current of each
of the plurality of slave power stages to approximately a zero level.

US Pat. No. 10,149,354

POWER CONVERTER CONTROLLER

Dialog Semiconductor (UK)...

1. A controller for controlling a power converter to convert electrical power at an input voltage into electrical power at an output voltage, the controllercomprising
an input port configured to receive a voltage representative of the input voltage;
an input voltage measuring unit configured to sample a measuring voltage and determine a measurement value that is representative of the input voltage;
a switch;
a diode connectable with a storage unit to provide a supply voltage for the controller during operation of the controller, and
a resistor which forms a voltage divider with an external resistor connected to the input port, the input voltage measuring unit connected with a terminal of the resistor to measure a portion of the input voltage, the portion determined by the voltage divider ratio;
wherein the switch is controlled to control charging of the storage unit from the voltage at the input port.

US Pat. No. 9,859,872

APPARATUS AND METHOD FOR TEMPERATURE MEASUREMENT AND/OR CALIBRATION VIA RESONANT PEAKS IN AN OSCILLATOR

Dialog Semiconductor (UK)...

1. A circuit providing resonant peaks for utilization for temperature measurements wherein a plurality of said resonant peaks
are utilized comprising
a resonant device consisting of an oscillator for providing an oscillating source;
a variable gain-bandwidth amplifier and/or constant bandwidth amplifier in parallel with said resonant device for providing
modulation of the gain and/or bandwidth driving said resonant device, and control of resonant peaks for selection for oscillation;

a first capacitor electrically coupled to the parallel combination of the input of said variable gain-bandwidth amplifier
and/or constant bandwidth amplifier, and said resonant device for providing charge storage for oscillation; and,

a second capacitor electrically coupled to parallel combination of the output of said variable gain-bandwidth amplifier and/or
said constant bandwidth amplifier, and said resonant device for providing charge storage for oscillation.

US Pat. No. 9,755,629

CURRENT-CONTROLLED ACTIVE DIODE

Dialog Semiconductor (UK)...

1. An active diode circuit for letting current pass in one direction and substantially blocking current in the opposite direction,
the active diode circuit comprising:
a transistor;
a control voltage generation circuit for generating a control voltage that is supplied to a control terminal of the transistor;
and

a sensing circuit for detecting a quantity indicative of a current flowing through the transistor,
wherein the control voltage generation circuit is configured to generate the control voltage in dependence on the detected
quantity; and

wherein the control voltage generation circuit is further configured to:
compare the detected quantity to a predetermined threshold; and
if the detected quantity exceeds the predetermined threshold, output, as the control voltage, a first voltage that is sufficient
to drive the transistor in the fully conducting state.

US Pat. No. 9,671,805

LINEAR VOLTAGE REGULATOR UTILIZING A LARGE RANGE OF BYPASS-CAPACITANCE

Dialog Semiconductor (UK)...

1. An amplifier comprising
a first amplification stage configured to provide an intermediate voltage, based on an outer feedback voltage and based on
a reference voltage;

an output stage configured to provide a load current at an output voltage based on the intermediate voltage; and
an outer feedback circuit configured to derive the outer feedback voltage from the output voltage;wherein the output stage comprises a buffer configured to provide a drive voltage based on the intermediate voltage and based
on an inner feedback voltage derived from the output voltage; and wherein the buffer comprises a pass device configured to
provide the load current at the output voltage based on the drive voltage, and wherein
the first amplification stage comprises a differential amplification stage;
the differential amplification stage comprises a differential transistor pair, and is configured to provide the intermediate
voltage at a stage output node of the
differential transistor pair, based on the outer feedback voltage at a first stage input node and based on the reference voltage
at a second stage input node;
the differential transistor pair further comprises a current feedback node;
the differential amplification stage further comprises an active load comprising a diode transistor directly coupled to the
current feedback node and a mirror transistor coupled to the stage output node, wherein the current feedback node comprises
a drain of the diode transistor; and

the amplifier further comprises a current feedback network configured to provide a feedback current to the current feedback
node, in dependence of a voltage at the pass device.

US Pat. No. 9,739,810

DUTY CYCLE INDEPENDENT COMPARATOR

Dialog Semiconductor (UK)...

1. A circuit configured to measure a pulsed current through a pass transistor of a switching circuit in order to detect, independently
of frequency and percentage of a duty cycle driving the switching circuit, if the current through the pass transistor has
reached a threshold value, comprising:
the pass transistor connected between a supply voltage and a load;
a node for a reference voltage; and
a circuit capable of comparing the reference voltage with a first voltage representing the pulsed current through the pass
transistor during a first phase of the duty cycle of the switching circuit driving the switching circuit, while the pass transistor
is ON, and of substituting the first voltage by the reference voltage during the remaining part of the duty cycle driving
the switching circuit while the pass transistor is OFF, wherein the comparison detects independently of frequency and percentage
of the duty cycle if an average current through the pass transistor has reached one or more threshold values over the duty
cycle;
wherein the circuit capable of comparing the reference voltage with a voltage representing the pulsed current through the
pass transistor further comprises:
a sense transistor connected between a supply voltage and a current source wherein the node for the reference voltage is deployed
between the sense transistor and the current source and wherein the node for the reference voltage is connected to a second
terminal of a second switch and to a second input of a comparator, wherein the sense transistor is matched to the pass transistor;

said current source connected between ground and said sense transistor;
a first switch, wherein a first terminal of the switch is connected to the load of the pass transistor and a second terminal
of the switch is connected to a first input of the comparator and to a first terminal of the second switch;

said second switch; and
said comparator wherein its output is used to detect if the current through the pass transistor has reached a threshold;
wherein the first switch is closed and the second switch is open during ON-time of the pass transistor and vice versa the
first switch is open and the second switch is closed during OFF-time of the pass transistor.

US Pat. No. 9,735,678

VOLTAGE CONVERTERS WITH ASYMMETRIC GATE VOLTAGES

Dialog Semiconductor (UK)...

1. A multi-phase switch converter, the device comprising:
a port for an input voltage (Vin);
a port for a reference common ground voltage (Vcom), wherein the switch converter is supplied by a voltage difference between
voltage Vin and voltage Vcom;

gate voltage driver circuits comprising for each phase of the multi-phase switch converter a high-side gate voltage driver
and a low-side gate voltage driver;

an intermediate voltage, wherein the intermediate voltage has an arbitrary intermediate voltage level between the supply voltage
and the Vcom voltage that is configured, if activated, to enable the high-side gate voltage drivers to switch between the
input voltage and the intermediate voltage and to enable the low-side gate voltage drivers to switch between the intermediate
voltage and the Vcom voltage, thus enabling reduced switching voltages, wherein the intermediate voltage is dynamically controlled
to optimize the efficiency of the switch converter at different loads or output voltages;

multi-phase switches connected to the gate driver circuits;
wherein the multi-phase switching converter is capable of turning the gate voltage of the gate voltage drivers and in consequence
of the multi-phase switches with lower switching voltages to provide lower switching losses and higher efficiency for low
and medium load currents.

US Pat. No. 9,698,691

CIRCUIT AND METHOD FOR MAXIMUM DUTY CYCLE LIMITATION IN SWITCHING CONVERTERS

Dialog Semiconductor (UK)...

1. An adaptive duty cycle limiting circuit included within a switching DC-to-DC converter, the adaptive duty cycle limiting
circuit comprising:
an inductor current feedback circuit for generating a current sense signal indicative of a level of current through an inductor
within the switching DC-to-DC converter; and

a limit circuit configured for generating an adaptive limit signal from a replica signal of the current sense signal that
is transferred through a parasitic resistance of a switching circuit of the switching DC-to-DC converter to generate a voltage
drop signal across the parasitic resistance, configured for comparing the voltage drop signal with a voltage having a level
indicative of a maximum current limit value to determine if a gain level of the switching DC-to-DC converter has decreased
even though the duty cycle has increased, and configured for transferring the adaptive limit signal is transferred to a switching
circuit for disabling a switch for limiting the duty cycle of the switching DC-to-DC converter such that the switching DC-to-DC
converter does not enter a region where the gain of the switching DC-to-DC converter has a negative slope, when the gain has
decreased.

US Pat. No. 9,653,997

RINGING SUPPRESSION METHOD AND APPARATUS FOR POWER CONVERTERS

Dialog Semiconductor (UK)...

1. A method of controlling a power converter for converting a DC input voltage to a DC output voltage, wherein the power converter
comprises an inductor, one or more switching elements for energizing and de-energizing the inductor, a drive circuit for controlling
switching operation of the one or more switching elements in accordance with a control signal, and a feedback circuit for
generating the control signal on the basis of a first feedback quantity indicative of an actual output voltage of the power
converter and in accordance with one or more circuit parameters of the feedback circuit, the method comprising:
detecting an open loop condition of feedback control by the feedback circuit; and
modifying at least one of the circuit parameters of the feedback circuit in such a manner that a time until the feedback control
returns to the closed loop condition is reduced,

wherein the feedback circuit generates the control signal on the basis of the first feedback quantity and a fourth feedback
quantity indicative of a sum of a fifth feedback quantity indicative of a result of a conversion of a second feedback quantity
indicative of an inductor current to a voltage value and a sixth feedback quantity indicative of a voltage output by a ramp
generator; and

modifying the at least one of the one or more circuit parameters involves:
increasing a gain factor that is applied in the conversion of the second feedback quantity to the voltage value.

US Pat. No. 9,948,185

FAST-TRANSIENT SWITCHING CONVERTER WITH TYPE III COMPENSATION

Dialog Semiconductor (UK)...

1. A control stage circuit within a switch mode DC/DC power converter comprising:a programmable feedback voltage offset generator configured for providing an offset voltage to the feedback voltage to generate an offset feedback voltage when the control loop monitor determines that the offset voltage is required to be provided to the feedback voltage for decreasing overshoot or undershoot of the output voltage of the switch mode DC/DC power converter;
an error amplifier current offset generator configured for generating offset current to be added to the output of the error amplifier;
a feed-forward compensation circuit configured for increasing the input range the feed-forward amplifier output and the error amplifier output; and
a control loop monitor connected to the programmable feedback voltage offset generator, the error amplifier current offset generator, and the feed-forward compensation circuit and configured for monitoring a difference between a feedback voltage developed from the output voltage of the switch mode DC/DC power converter and a positively offset reference voltage and a negatively offset reference voltage for determining if any line and/or load transient signal is an increase or a decrease in magnitude that will cause the overshoot or undershoot of the output voltage of the switch mode DC/DC power converter; and configured for generating output control signals for activating the programmable feedback voltage offset generator, the error amplifier current offset generator, and the feed-forward compensation circuit.

US Pat. No. 9,804,614

BANDGAP REFERENCE CIRCUIT AND METHOD FOR ROOM TEMPERATURE TRIMMING WITH REPLICA ELEMENTS

Dialog Semiconductor (UK)...

1. A method for trimming a bandgap reference circuit, wherein for providing the bandgap reference circuit the method comprises
the steps of:
arranging a first diode in series with a first resistor between a reference point and a reference potential;
arranging a second diode in series with a second resistor and a third resistor between the reference point and the reference
potential;

arranging a trimming network in series with a current source between the reference point and a supply voltage; wherein the
trimming network exhibits an adjustable resistance; wherein a bandgap reference voltage is provided at a midpoint between
the trimming network and the current source; and

coupling a first input of an operational amplifier to a midpoint between the first diode and the first resistor, wherein a
second input of the operational amplifier is coupled to a midpoint between the second resistor and the third resistor, and
wherein an output of the operational amplifier is used to control the current source;
wherein the method further comprises the steps of:
measuring a first diode voltage across a replica element of the first diode; the replica element of the first diode being
a copy of the first diode;

determining a first resistance of a replica element of the first resistor; the replica element of the first resistor being
a copy of the first resistor; and

setting the resistance of the adjustable resistance of the trimming network using the first diode voltage and the first resistance.

US Pat. No. 9,742,280

DYNAMIC CLOCK DIVIDE FOR CURRENT BOOSTING

Dialog Semiconductor (UK)...

14. A multiphase switching DC-to-DC converter with improved load transient response, comprising:
multiple phases comprising
one or more fast slave phases with inductors having low inductance; and
one or more slow slave phases with inductors, compared to the fast slave phases, having relative high inductance;
wherein said multiphase switching converter is configured to reduce a clock frequency of one or more of said multiple phases
upon detection of a load step, and to return said clock frequency to its normal rate once a current in said one or more of
said multiple phases reaches a predetermined level.

US Pat. No. 9,654,007

REGULATION OF A MULTIPLE STAGE SWITCH MODE POWER CONVERTER THROUGH AN INTERMEDIATE VOLTAGE CONTROL

Dialog Semiconductor (UK)...

1. A multiple phase, multiple stage switch mode power converter (SMPC) system comprising:
at least one single stage phase SMPC circuit configured for converting an input voltage of the multiple phase, multiple stage
SMPC system to an output voltage of the multiple phase, multiple stage SMPC system and connected to an electronic load circuit
for transferring the output voltage to the electronic electronic load circuit; and;

at least one multiple stage phase SMPC circuit comprising:
at least one primary stage phase SMPC circuit configured for converting an input voltage of the multiple phase, multiple stage
SMPC system to an intermediate voltage, and

at least one secondary stage phase of the multiple stage SMPC circuit that is connected to receive the intermediate voltage
from the at least one primary stage SMPC circuit and configured for converting the intermediate voltage to an output voltage
of the multiple phase, multiple stage SMPC system, wherein the at least one secondary stage of the multiple stage switch mode
power supply circuit comprises:

a voltage conditioner configured for transforming the intermediate voltage to be approximately the level of the output voltage
to act a reference voltage for the secondary stage in determining the switching characteristics of the secondary stage SMPC
circuit.

US Pat. No. 10,143,047

LIGHTING CONTROL SYSTEM AND METHOD FOR GENERATING SUPPLY CURRENTS FOR LED CHANNELS

Dialog Semiconductor (UK)...

1. A lighting control system for generating supply currents for a first LED channel and at least a second LED channel, the system comprisinga first controlled current source for generating a first supply current for the first LED channel based on a first control signal;
a second controlled current source for generating a second supply current for the second LED channel based on a second control signal;
a first signal combiner for generating the first control signal based on a synchronization signal that comprises periodic starting pulses and on a combination of a first magnitude dimming signal and a first pulse dimming signal; and
a second signal combiner for generating the second control signal based on the synchronization signal and on a combination of a second magnitude dimming signal and a second pulse dimming signal; wherein
the first and the second signal combiner are designed such that changes of the respective first and second control signals come into effect only with a respective time offset with respect to one of the starting pulses of the synchronization signal.

US Pat. No. 9,887,674

MULTI-STAGE AMPLIFIER WITH IMPROVED OPERATING EFFICIENCY

Dialog Semiconductor (UK)...

1. A linear regulator comprising:
a first amplifier stage having a differential input and an output, the output of the first amplifier stage being coupled with
a first terminal of a capacitor having a controllable capacitance, wherein the differential input comprises a reference input
and a feedback input, the reference input is coupled to a reference voltage Vref and the feedback input is coupled to a linear regulator output voltage Vout via a feedback factor;

a second amplifier stage having an input and an output, the input of the second amplifier stage being coupled to the output
of the first amplifier stage and the first terminal of the capacitor, the output of the second amplifier stage being coupled
to a second terminal of the capacitor and an output of the linear regulator;

a current sensing circuit having an input and an output, the input of the current sensing circuit being coupled with the output
of the linear regulator; and

a control signal generator being coupled between the output of the current sensing circuit and a control terminal of the capacitor,
wherein the control signal generator provides a control signal to the capacitor, wherein the capacitance of the capacitor
is controlled by the control signal.

US Pat. No. 9,864,386

OVERVOLTAGE CLAMP IN REGULATORS

Dialog Semiconductor (UK)...

14. A method for providing a load current at a regulator output voltage to a load, wherein the method comprises the steps
of:
providing a first intermediate voltage based on a difference between a reference voltage and a feedback voltage derived from
the regulator output voltage using a differential input stage;

providing a second intermediate voltage based on the first intermediate voltage using an intermediate amplification stage
which is coupled to an output of the differential input stage.

generating a control signal based on the second intermediate voltage;
providing the load current in dependence of the control signal using a pass transistor;
sensing an overvoltage indication by sensing the control signal, wherein the overvoltage indication indicates that the pass
transistor is being turned off; and

clamping the first intermediate voltage to a clamping voltage, if the overvoltage indication indicates that the pass transistor
is being turned off.

US Pat. No. 9,837,906

MULTIPHASE DCDC CONVERTER WITH ASYMMETRIC GM

Dialog Semiconductor (UK)...

1. A multi-phase DC-to-DC switching converter, comprising:
two or more asymmetric phases, each of said asymmetric phases configured for optimizing efficiency at different loads levels
of output current and, further comprising:

said asymmetric phases are connected in parallel;
each of said asymmetric phases comprises a controller, a high side switch and a low side switch;
said asymmetric phases having asymmetric transconductance, with said asymmetric transconductance of each said asymmetric phase
set according to an output current load range that said asymmetric phase is designed to operate in.

US Pat. No. 9,772,639

DYNAMIC CURRENT-LIMIT CIRCUIT

Dialog Semiconductor (UK)...

1. A comparator circuit which is configured to provide a control current and a control voltage based on a first input voltage
and a second input voltage, the comparator circuit comprising
an input amplifier configured to generate an output signal based on a delta voltage which corresponds to a difference between
the first input voltage and the second input voltage;

offset means configured to generate a first offset;
a first output circuit configured to generate the control current based on the output signal and based on the first offset;
and

a second output circuit configured to generate the control voltage based on the output signal and not based on the first offset;
wherein the second output circuit is configured to generate the control voltage such that the control voltage exhibits a swing
from a first potential to a second potential at a first delta voltage; and wherein the first output circuit is configured
to generate the control current such that the control current is substantially linear for delta voltages within a pre-determined
interval around the first delta voltage.

US Pat. No. 9,710,008

FAST BIAS CURRENT STARTUP WITH FEEDBACK

Dialog Semiconductor (UK)...

1. A fast start-up power circuit, comprising:
a) a current source configured to provide current to the start-up circuit;
b) a current mirror circuit configured to receive current from said current source, wherein a first transistor of the current
mirror circuit is directly connected to the current source, a second transistor of the current mirror circuit provides current
via an enable switch to a first terminal of an transistor of an input driver circuit and a third transistor of the current
mirror circuit provides a reference current;

c) said input driver circuit, configured to control a current mirror network, comprising said transistor of the input driver
circuit, wherein a gate of said transistor is directly connected to the first terminal of said transistor and a second terminal
of said transistor is connected to ground, said enable switch, an amplifier, configured to keep a gate voltage of the current
mirror network at the same potential as a gate voltage of said transistor until the start-up phase is completed, while both
gate voltages are connected only via the amplifier during start-up phase, wherein the amplifier is disabled upon completion
of the start-up phase;

d) said current mirror network comprising a plurality of transistors, whose gates are all connected together, wherein one
terminal of each transistor of the current mirror network is connected to ground, wherein a first transistor of the current
mirror network provides drive current for a comparison with the reference current generated by the third transistor of the
current mirror circuit, wherein each of the other transistors of the current mirror network generates bias current;

e) said amplifier;
f) a trigger circuitry, which is configured to set a signal when a current comparator detects that the reference current is
higher than the current generated by the first transistor of the current mirror network and, if it so, the first control switch
is opened;

g) said first control switch configured to be open during start-up phase only;
h) a capacitor connected between the gate of the first transistor of the current mirror network and ground.

US Pat. No. 9,698,681

CIRCUIT AND METHOD FOR MAXIMUM DUTY CYCLE LIMITATION IN STEP UP CONVERTERS

Dialog Semiconductor (UK)...

1. An adaptive duty cycle limiting circuit for use with a switching DC-to-DC converter comprising:
a ramp generator configured for receiving an output voltage of the switching DC-to-DC converter communicated from an output
terminal of the switching DC-to-DC converter and configured for generating an output ramp signal created from the output voltage
of the switching DC-to-DC converter;

a variable voltage source configured for receiving an adjusting voltage level indicating the voltage level of an input voltage
source and configured for generating an output voltage level that is a fractional value of the voltage level of the input
voltage source; and

a comparator circuit configured for receiving the output voltage level of the variable voltage source, and the output voltage
ramp signal, and configured for determining if the voltage level of the variable voltage source is less than or greater than
output voltage ramp signal to generate a duty cycle limit signal for transfer to a converter switching control circuit to
adjust the duty cycle of the switching DC-to-DC converter.

US Pat. No. 9,690,309

BANDGAP REFERENCE CIRCUIT AND METHOD FOR ROOM TEMPERATURE TRIMMING WITH REPLICA ELEMENTS

Dialog Semiconductor (UK)...

1. A method for trimming a bandgap reference circuit, wherein for providing the bandgap reference circuit the method comprises
the steps of:
arranging a first diode in series with a first resistor between a reference point and a reference potential;
arranging a second diode in series with a second resistor and a third resistor between the reference point and the reference
potential;

arranging a trimming network in series with a current source between the reference point and a supply voltage; wherein the
trimming network exhibits an adjustable resistance; wherein a bandgap reference voltage is provided at a midpoint between
the trimming network and the current source; and

coupling a first input of an operational amplifier to a midpoint between the first diode and the first resistor, wherein a
second input of the operational amplifier is coupled to a midpoint between the second resistor and the third resistor, and
wherein an output of the operational amplifier is used to control the current source;
wherein the method further comprises the steps of:
measuring a first diode voltage across a replica element of the first diode; the replica element of the first diode being
a copy of the first diode;

determining a first resistance of a replica element of the first resistor; the replica element of the first resistor being
a copy of the first resistor; and

setting the resistance of the adjustable resistance of the trimming network using the first diode voltage and the first resistance.

US Pat. No. 9,634,569

DC-TO-DC OUTPUT CURRENT SENSING

Dialog Semiconductor (UK)...

1. A buck converter enabled for output current measurement comprising:
a main output stage comprising a PMOS pass transistor and an NMOS pass transistor both connected in series, wherein the PMOS
pass transistor is connected to supply voltage VDD and the NMOS pass transistor is connected to ground;

a coil, wherein a first terminal of the coil is connected to a mid-node between the PMOS pass transistor and the NMOS pass
transistor and a second terminal of the coil is connected to an output port of the buck converter;

a circuitry configured to providing a first voltage node representing an output current limit of the buck converter and to
providing a second voltage node to be sampled in PFM mode, whenever either the PMOS pass device or the NMOS pass device is
on;

a switch, wherein a first terminal of the switch may contact multiple contact points and a second terminal of the switch is
connected to a filter, wherein the switch is configured in PFM mode to either sampling the second voltage node in order to
provide an average current during the output current pulse or to being connected to the supply voltage or a correspondent
voltage and in PWM mode to either sampling the mid-node voltage between the PMOS pass transistor and the NMOS pass transistor
or being connected to open circuit;
wherein the buck converter is configured to switch the PMOS pass transistor off when an output current through the coil reaches
a maximum current limit, which is indicated by the first voltage node, and then the current through the coil falls linearly
until the coil is completely discharged.

US Pat. No. 9,477,252

VOLTAGE REGULATOR

Dialog Semiconductor (UK)...

1. A voltage regulator comprising
an output node providing an output voltage for a load;
current sensing means for sensing an output current flowing at the output node;
voltage providing means for providing a digital representation of the output voltage or of an input voltage to the voltage
regulator;

output power determination means comprising a digitally controllable variable resistance circuit receiving the digital voltage
representation from the voltage providing means and generating a resistance depending thereon,

wherein the variable resistance circuit is connected to the current sensing means to obtain a signal that depends upon the
output current and generates a voltage depending on the generated resistance and the obtained signal; and

wherein the output power determining means are adapted to determine the output power of the voltage regulator based on the
voltage generated by the variable resistance circuit.

US Pat. No. 9,958,892

VOLTAGE REGULATOR WITH IMPEDANCE COMPENSATION

Dialog Semiconductor (UK)...

1. A regulator configured to provide at an output node a load current at an output voltage, wherein the regulator comprises,a pass transistor for providing the load current at the output node;
feedback means for deriving a feedback voltage from the output voltage at the output node;
a differential amplifier configured to control the pass transistor in dependence of the feedback voltage and in dependence of a reference voltage;
compensation means configured to
determine a sensed current which is indicative of the load current at the output node;
adjust an operation point of the regulator in dependence of the sensed current and in dependence of a value of a track impedance of a conductive track which links the output node to a load; and
generate a virtual node based on the output voltage, based on the sensed current and based on the value of the track impedance; and
a feedback capacitor which is arranged between the virtual load node and an internal node of the regulator.

US Pat. No. 9,823,677

POWER CONVERTER

Dialog Semiconductor (UK)...

1. A control circuit for a power converter that converts an input voltage into an output voltage, comprising
a power switch;
a power switch driver coupled with the power switch to control the switching state of the power switch so as to provide the
output voltage at an output port of the power converter, the output port for coupling with a first terminal of a load;

a load port for coupling with a second terminal of the load;
a switching element coupled with the load port to selectively connect the load port to ground, wherein the switching element
is controlled in synchronism with the power switch;

a circuit coupled with the load port, configured to provide an operating voltage to the control circuit; and
a logic unit coupled with the gate of the switching element, the logic unit for generating a gate drive signal for the switching
element so that the switching element is open during a portion of the time when the power switch is open.

US Pat. No. 9,826,309

OPTIMISED LOUDSPEAKER OPERATION

Dialog Semiconductor (UK)...

1. A loudspeaker driver circuit comprising:
a first power calculator for determining a playback power from incoming audio data;
a second power calculator for determining a feedback power from an actuator for driving the loudspeaker;
a decision logic circuit arranged to calculate a ratio of the playback power and the feedback power, and to generate a command
for adjusting a frequency response of the loudspeaker based on the ratio.

US Pat. No. 9,671,804

LEAKAGE REDUCTION TECHNIQUE FOR LOW VOLTAGE LDOS

Dialog Semiconductor (UK)...

1. A multi-stage voltage regulator comprising
a pass device configured to provide a load current at a regulated output voltage to an output node of the voltage regulator;
wherein a source of the pass device is coupled to a first potential of the voltage regulator;

a differential amplification stage configured to derive a first intermediate voltage at a stage output node of the differential
amplification stage, based on a difference between a reference voltage and a feedback voltage derived from the output voltage;

an intermediate amplification stage configured to derive a second intermediate voltage at a stage output node of the intermediate
amplification stage, based on the first intermediate voltage;

drive circuitry configured to control the pass device via a gate of the pass device, wherein the drive circuitry is coupled
to the stage output node of the intermediate amplification stage;

leakage reduction circuitry configured to pull-up the gate of the pass device using a second potential; wherein the second
potential is higher than the first potential

leakage compensation circuitry configured to sink a current from the output node to a reference potential of the voltage regulator;
wherein an amount of current which is sunk by the leakage compensation circuitry depends on the first intermediate voltage,
the leakage compensation circuitry comprises a sink transistor arranged between the output node and the reference potential,
and a gate of the sink transistor is connected to the stage output node of the differential amplification stage.

US Pat. No. 9,621,043

VERSATILE CURRENT SENSOR FOR SWITCHING REGULATOR

Dialog Semiconductor (UK)...

1. A switching converter, comprising:
an output stage with both high and low side pass devices;
a current sensor comprising:
a subtractor configured to receive output voltages of a sample and hold circuit, and of the drains of said high and low side
pass devices, and pass their difference to a switch;

a switch configured to be closed for a period, when said low side pass device is turned on, and open for a period, when said
low side pass device is turned off;

an integrator configured to integrate the voltage difference between said sample and hold output and the voltage at the drains
of said high and low side pass devices;

said sample and hold circuit configured to sample the output of said integrator from the previous period; and
wherein an output of the current sensor is an averaged sense voltage.

US Pat. No. 10,206,253

POWER CONVERTER CONTROLLER

Dialog Semiconductor (UK)...

1. A controller for controlling a power converter to convert electrical power at an input voltage into electrical power at an output voltage, the controllercomprising
an input port configured to receive a voltage representative of the input voltage;
an input voltage measuring unit configured to sample a measuring voltage and determine a measurement value that is representative of the input voltage;
a switch;
a diode connectable with a storage unit to provide a supply voltage for the controller during operation of the controller, and
a resistor which forms a voltage divider with an external resistor connected to the input port, the input voltage measuring unit connected with a terminal of the resistor to measure a portion of the input voltage, the portion determined by the voltage divider ratio;
wherein the switch is controlled to control charging of the storage unit from the voltage at the input port.

US Pat. No. 10,090,763

MULTI-LEVEL BUCK CONVERTER HAVING A REGULATED FLYING CAPACITOR VOLTAGE USED FOR HIGH-SIDE DRIVE

DIALOG SEMICONDUCTOR (UK)...

1. A multi-level buck converter, comprising:a plurality of four switch transistors having four switching states with respect to an inductor, the plurality of four switch transistors including a first switch transistor having a drain connected to an input voltage node, a second switch transistor having a source connected to an input node for the inductor and a drain connected to a source for the first switch transistor, a third switch transistor having a drain connected to the source of the second switch transistor, and a fourth switch transistor having a drain connected to a source for the third switch transistor and having a source connected to ground;
a flying capacitor having a positive terminal connected to the source of the first switch transistor and a negative terminal connected to the source of the third switch transistor;
a first gate driver for driving a gate for the first switch transistor;
a second gate driver for driving a gate of the second switch transistor;
a third gate driver for driving a gate of the third switch transistor, wherein the positive terminal of the flying capacitor is connected to a power supply node for the third gate driver;
a first boot capacitor connected between the source of the first switch transistor and a power supply node for the first gate driver; and
a second boot capacitor connected between the source of the second switch transistor and a power supply node for the second gate driver.

US Pat. No. 10,041,983

VDS EQUALIZER OFFSET COMPENSATION FOR A CURRENT SENSE CIRCUIT

Dialog Semiconductor (UK)...

1. A current sense circuit for a pass transistor, wherein the current sense circuit comprises,a sense transistor having an input port that is coupled to an input port of the pass transistor and having a gate that is coupled to a gate of the pass transistor;
a differential amplifier comprising a differential input and a differential output; wherein an output port of the pass transistor is coupled to a first port of the differential input and wherein an output port of the sense transistor is coupled to a second port of the differential input; and
a differential difference amplifier, referred to as DD amplifier, comprising a main differential input, an auxiliary differential input and an output; wherein the differential output of the differential amplifier is coupled to the auxiliary differential input of the DD amplifier; wherein the output port of the pass transistor is coupled to a first port of the main differential input and wherein the output port of the sense transistor is coupled to a second port of the main differential input; wherein the output of the DD amplifier is used to control a voltage drop across the sense transistor and the pass transistor; and
an output transistor which is controlled by the output of the DD amplifier; wherein an output port of the output transistor is coupled to the output port of the sense transistor; and wherein a sense current through the output transistor provides an indication of a current through the pass transistor,
wherein the sense current through the output transistor is fed back to the gates of the pass transistor and of the sense transistor to control the voltage drop across the sense transistor and the pass transistor.

US Pat. No. 9,997,991

SWITCHED-MODE POWER CONVERTER WITH A CURRENT LIMIT CIRCUIT

Dialog Semiconductor (UK)...

1. A switched-mode power converter comprisinga feedback loop for controlling the output voltage of the switched-mode power converter;
a first voltage comparison unit within the feedback loop configured to compare a voltage indicative of the output voltage with a reference voltage and to output an error voltage based on the comparison;
a current control unit for limiting an input current into the switched-mode power converter, the current control unit comprising
a current comparison unit configured to compare the input current with a current threshold and to output an intermediate voltage based on the comparison, and
a connection unit connected to the output of the current comparison unit and configured to connect, in case the input current exceeds the current threshold, the output of the current comparison unit to the output of the first voltage comparison unit;
wherein the current comparison unit comprises a voltage clamp whose output is connected to the output of the current comparison unit and the current comparison unit is configured to adjust the immediate voltage based on a clamp reference voltage at an input of the voltage clamp, and wherein the current control unit is configured to set, by adjusting the clamp reference voltage, the intermediate voltage such that an over-shoot of the input current is reduced.

US Pat. No. 9,929,653

MULTI-LEVEL BUCK CONVERTER WITH MULTIPLE CONTROL LOOPS AND FLYING CAPACITOR REGULATION

DIALOG SEMICONDUCTOR (UK)...

1. A multi-level buck converter, comprising:a plurality of switches having four switching states with respect to an inductor and a flying capacitor; and
a first error amplifier configured to produce a first error signal responsive to a difference between an output voltage and a first reference voltage;
a second error amplifier configured to produce a second error signal responsive to a difference between a voltage across the flying capacitor and a second reference voltage; and
a controller configured to generate a first control signal that is asserted at the beginning of each period for a first ramp signal and reset when the first ramp signal exceeds the first error signal and configured to generate a second control signal that is asserted at the beginning of each period for a second ramp signal and is reset when the second ramp signal exceeds the first error signal, wherein the controller is further configured to adjust the assertion of the first control signal and the second control signal responsive to the second error signal to produce an adjusted first control signal and an adjusted second control signal, and wherein the controller includes a logic circuit configured to select for respective ones of the four switching states responsive to a binary value for the adjusted first control signal and for the adjusted second control signal to maintain a regulation for the output voltage and for the voltage across the flying capacitor.

US Pat. No. 9,685,868

SYNCHRONOUS RECTIFIER FOR BUCK CONVERTER WITHOUT THE NEED FOR A COMPARATOR

Dialog Semiconductor (UK)...

1. A method for digitally controlling a synchronous rectifier within a switch mode power supply for monitoring a demagnetization
mode of operation and determining a polarity of an inductor current within the switch mode power supply for controlling an
operational state of a switching section of the switch mode power supply such that the inductor current becomes approximately
zero amperes at the end of a demagnetization phase of operation, the method comprising the steps of:
determining when the switch mode power supply is entering the continuous current mode demagnetization phase of operation;
setting a delay time to its base delay based on a delay code;
sensing an Inductor input voltage signal indicating a level of the voltage present at an input of a filter section of the
switch mode power supply;

examining a current sinking switch to determine if it has been deactivated after a period of time;
when the current sinking switch is deactivated, determining if the sensed inductor input voltage signal is greater than or
less than a reference voltage level;

when a current sinking switch is deactivated, incrementing or decrementing a delay counter based on a polarity of the inductor
current;

programing a delay circuit with an output of the delay counter;
activating a discontinuous current demagnetization signal at an activation of a continuous current demagnetization signal
indicating that the current sinking switch is making the current discontinuous;

initiating the delay circuit to determine the delay time; and
at the end of the delay time, deactivating the discontinuous current demagnetization signal to indicate that the current sinking
switch is to be deactivated and the inductor current is approximate a zero amp level.

US Pat. No. 9,673,702

NEGATIVE CURRENT CLOCKING

Dialog Semiconductor (UK)...

1. An overvoltage discharge circuit in communication with a switch mode power supply (SMPS) for eliminating an overvoltage
at an output of the SMPS, comprising:
an overvoltage detection circuit coupled to the SMPS for receiving an indication of an output voltage and for receiving a
target input voltage, and configured for determining that the output voltage is greater than the target input voltage and
providing an overvoltage indication signal, the overvoltage detection circuit is configured for adjusting the overvoltage
indication signal to a voltage that is not circuit ground;

a zero crossing comparator circuit coupled to the overvoltage detection circuit for receiving the overvoltage indication signal,
coupled to a common connection of a first switch and a second switch included in the SMPS for receiving a voltage level present
at the common connection between the first and second switch, configured for generating a negative current limit/active diode
select signal having a first voltage level when the overvoltage indication signal designates an overvoltage condition at the
output of the SMPS indicating that the negative current/active diode select signal is activated, generating a second voltage
level that is approximately ground when the voltage level at the common connection is approximately equal to the zero voltage
level indicating the second switch is activated; and

a switch control circuit coupled to the zero crossing comparator circuit and configured for generating a switch activation/deactivation
signal indicating that the second switch is to be activated when the voltage at the common connection is greater than the
first voltage level;

wherein adjusting the overvoltage indication signal to the voltage that is not circuit ground varies the current at which
the second switch turns off;

wherein when the overvoltage indication signal indicates an overvoltage at the output of the SMPS, the switch control circuit
activates the second switch to sink excess current to decrease the overvoltage at the output of the SMPS.

US Pat. No. 10,110,216

OVER VOLTAGE PROTECTION OF A TRANSISTOR DEVICE

Dialog Semiconductor (UK)...

1. A circuit comprising:a transistor comprising a control terminal, a first current carrying terminal and a second current carrying terminal; and
an over-voltage protection circuit comprising:
a level shifter arranged to feed back a level-shifted version of a channel voltage between said first and second current carrying terminals to the control terminal;
wherein the level shifter is configured so that a switching threshold voltage of the transistor is crossed when a predetermined value of the channel voltage is crossed.

US Pat. No. 10,044,259

LOW POWER DC-DC CONVERTER

Dialog Semiconductor (UK)...

1. A DC-DC converter comprising an oscillator with a charge pump wherein the oscillator comprises one or more source degenerated transistors, wherein each transistor comprises a degeneration impedance located between a source of the transistor and a ground connection, wherein the degeneration impedance comprises an inductor and a capacitor.

US Pat. No. 10,044,266

PEAK CURRENT SERVO

Dialog Semiconductor (UK)...

1. A peak current servo circuit, comprising:high side and low side devices for a switching converter;
a sampling circuit, configured to sample the peak high side device current just before the point when the high side device switches off;
a comparator, configured to compare said sample with a reference value, during a low side device on time;
a control loop, configured to successively increment or decrement a stored value in a counter, based on the output of said comparator;
wherein said peak current servo circuit is configured to use said stored value to generate an offset current to shift said peak high side device current up or down, and to match said high side device current to said reference value in cycles to come; and
a plurality of devices matched to said high side device, configured to supply a current for said reference value.

US Pat. No. 10,044,267

CURRENT EMULATION AUTO-CALIBRATION WITH PEAK-CURRENT SERVO

Dialog Semiconductor (UK)...

1. A DC-DC switching converter with current emulation auto-calibration, comprising:an integrating element configured to accumulate an emulated inductor current based on an output voltage and a supply voltage;
a first sampling circuit, configured to obtain a sample of an actual inductor current;
a second sampling circuit, configured to obtain a sample of said emulated inductor current;
a comparator configured to compare said sample of said actual inductor current with said sample of said emulated inductor current; and
a counter, configured to increment or decrement a stored value of said emulated inductor current, based on an output of said comparator.

US Pat. No. 10,044,269

SWITCHING CONVERTER WITH IMPROVED RECOVERY TIME

Dialog Semiconductor (UK)...

1. A converter for outputting an output voltage comprisinga switch operable between a first state for opposing a decrease in the output voltage and a second state for opposing an increase in the output voltage; and
a circuit adapted
to determine a time period during which the output voltage keeps decreasing, wherein during the time period the switch is in the first state; and
to calculate a time to turn the switch from the first state to the second state to prevent the output voltage increasing above a reference value;
wherein the converter has a duty cycle, and wherein the time to turn the switch to the second state is based on a product of a square root of the duty cycle and the time period.

US Pat. No. 10,044,273

MULTI-PHASE SWITCHING CONVERTER

Dialog Semiconductor (UK)...

1. A method of operating a multi-phase switching converter comprising a plurality of phase circuits, the method comprising the steps of:setting an adaptive voltage positioning parameter of an adaptive voltage positioning controller;
controlling an output voltage of the multi-phase switching converter using the adaptive voltage positioning controller;
generating a threshold voltage value based on the adaptive voltage positioning parameter;
comparing the output voltage of the multi-phase switching converter with the threshold voltage value; and
performing at least one of enabling and disabling a phase circuit based on the comparison.

US Pat. No. 10,033,199

BATTERY STACK CONFIGURATION IN A MULTI-BATTERY SUPPLY SYSTEM

Dialog Semiconductor (UK)...

1. A method for energizing operation of a device that includes at least two (2) rechargeable batteries, the device also including both at least one (1) buck DC-DC converter and at least one (1) boost DC-DC converter with each DC-DC converter respectively having a power input that receives electrical power for energizing DC-DC converter operation, the method comprising the step of connecting the batteries in series with:a. the series connected batteries being connected to the power input of the boost DC-DC converter for energizing the operation thereof; and
b. one of the series connected batteries being connected to the power input of the buck DC-DC converter for energizing the operation thereof,whereby during battery powered operation of the device the boost DC-DC converter operates more efficiently in comparison with operation thereof being energized by the batteries connected in parallel.

US Pat. No. 10,003,261

HIGH EFFICIENCY SWITCHING CHARGER WITH REDUCED INPUT VOLTAGE RIPPLE

Dialog Semiconductor (UK)...

1. A voltage or current regulated power converter for charging a battery, wherein the power converter is configured to derive electrical power at an output voltage Vout at an output of the power converter for charging the battery from electrical power at an input voltage Vin at an input of the power converter, wherein the power converter comprises an inductor (L), a capacitor cell, a plurality of switches (S1, S2, S3, S4, S5, S6, S7, S8) and a controller; wherein the capacitor cell comprises a single capacitor or a capacitive voltage divider; wherein the controller is configured to control the plurality of switches such that a commutation cycle of the power converter comprisesa first phase, during which the capacitor cell and the inductor are arranged in series between the input and the output of the power converter;
a second phase, during which the capacitor cell and the inductor are arranged in series parallel to the output of the power converter; and
a third phase, during which the capacitor cell is decoupled from the output of the power converter; during which a charge of the capacitor remains unaffected and during which the inductor is arranged between the input and the output of the power converter or parallel to the output of the power converter.

US Pat. No. 9,960,741

HIGH FREQUENCY COMMON MODE REJECTION TECHNIQUE FOR LARGE DYNAMIC COMMON MODE SIGNALS

Dialog Semiconductor (UK)...

1. A high frequency common mode rejection circuit for large dynamic common mode signals, comprising:a sense resistor, configured in series with a load;
a summing amplifier configured to sense current through said sense resistor, an output of said summing amplifier comprising said common mode signals;
a low pass filter between said sense resistor and said summing amplifier; and
a high voltage (HV) inverter, having a supply voltage of 8 or more volts, having its input connected to said sense resistor on a side of said sense resistor opposite to said load and having its output connected to said low pass filter.

US Pat. No. 9,941,795

CIRCUITS AND METHOD FOR EXTRACTING AVERAGE LOAD CURRENT IN DC-DC SWITCHING CONVERTERS

Dialog Semiconductor (UK)...

1. An average load current calculator circuit configured for determining an average load current within a switch mode power converter (SMPC) that includes at least one phase, comprising:at least one peak/valley detector in communication with the at least one phase of the SMPC and configured for receiving a current sense signal from the at least one phase of the SMPC indicating the magnitude of the current flowing through an inductor of the at least one phase of the SMPC and configured for determining and holding a peak or valley amplitude of the current sense signal;
a current corrector circuit connected for receiving an input voltage and an output voltage of the at least one phase SMPC and configured to receive an inductance value of the inductor of the at least one phase of the SMPC and configured for determining an average correction current of the peak or valley amplitude of the current sense signal from the input voltage, the output voltage and the inductance value; and
an average current generator in communication with the at least one peak/valley detector for receiving the peak or valley amplitude of the current sense signal and in communication with the current corrector circuit for receiving the average correction current, and configured for determining the average load current within a switch mode power converter (SMPC) by additively combining the peak or valley amplitude of the current sense signal and the average correction current.

US Pat. No. 9,933,807

IN-RUSH CURRENT CONTROLLER FOR A SEMICONDUCTOR SWITCH

Dialog Semiconductor (UK)...

1. An in-rush current controller configured to turn-on a semiconductor output switch, wherein the output switch is arranged in series with an output capacitor between an output supply voltage and ground, wherein the output switch comprises a switch control port for controlling an output current through the switch and for controlling an output voltage at an output node between the output switch and the output capacitor, wherein the controller comprisesan amplifier configured to source a switch control current to the switch control port from a control supply voltage or to sink a switch control current from the switch control port towards ground, for turning on the output switch; wherein the switch control current is dependent on an amplifier control current at an amplifier control port;
a reference current source configured to provide a reference current at the amplifier control port, subject to a control signal indicating that the output switch is to be turned on;
a feedback capacitor arranged to couple the output node to the amplifier control port, and configured to provide a feedback current at the amplifier control port in dependence of a variation of the output voltage, wherein the feedback current subtracts from the reference current; and
an auxiliary feedback capacitor arranged to directly couple the switch control port to the amplifier control port and configured to provide an auxiliary feedback current directly at the amplifier control port in dependence of a variation of a switch control voltage at the switch control port, wherein the auxiliary feedback current subtracts from the reference current.

US Pat. No. 9,928,079

CONDITIONAL PROCESSOR AUTO BOOT WITH NO BOOT LOADER WHEN COUPLED WITH A NONVOLATILE MEMORY

Dialog Semiconductor (UK)...

8. A computer system, comprising:a) a processor connected to a bus arbiter, wherein the processor is configured to fetch a first instruction of a non-volatile memory and to check upon this value of the first instruction if the first instruction of the non-volatile memory is un-programmed and, if it so, to decode the fetched value to a SLEEP instruction, to enter a stalled state and to resume operation after a trigger indicates that a firmware has been loaded from a host interface into the non-volatile memory or, if the first instruction of the non-volatile memory is programmed with firmware, to execute the firmware directly from the programmed memory without the need of a boot controller;
b) said bus arbiter connected to the host interface and to the non-volatile memory;
c) said non-volatile memory;
d) an instruction intercept circuit placed between the non-volatile memory and the processor configured to detect the un-programmed memory value and then to substitute the un-programmed memory value with the SLEEP opcode before it is decoded by the processor; and
e) said host interface configured to load firmware via the bus arbiter to the non-volatile memory, hence programming the non-volatile memory while execution of said processor is halted.

US Pat. No. 9,863,981

OFFSET NEUTRAL COMPENSATION FOR HIGH-ACCURACY CURRENT SENSING

Dialog Semiconductor (UK)...

1. Current sensing circuit for sensing a current flowing from a supply voltage into an electric load, the current sensing
circuit comprising:
a first circuit branch connected between the supply voltage and the electric load including a first resistive element;
a second circuit branch connected between the supply voltage and ground including a second resistive element;
an equalization circuit for equalizing a first voltage drop across the first resistive element and a second voltage drop across
the second resistive element and for generating an indication of a current flowing through the second circuit branch, wherein
the equalization circuit receives an indication of a difference between the first and second voltage drops as input;

an AC component generation circuit for generating an indication of an AC component of said difference between the first and
second voltage drops; and

an output node for outputting an indication of a sum of said indication of the current flowing through the second circuit
branch and said indication of the AC component of said difference between the first and second voltage drops.

US Pat. No. 9,857,817

SINK/SOURCE OUTPUT STAGE WITH OPERATING POINT CURRENT CONTROL CIRCUIT FOR FAST TRANSIENT LOADING

Dialog Semiconductor (UK)...

1. A voltage regulator, comprising
an amplification stage configured to control a voltage level of a first gain node and of a second gain node in response to
an input voltage at an input node, in order to activate a first and a second output stage, respectively; wherein the second
gain node is different from the first gain node;

the first output stage configured to source a current at an output node of the voltage regulator from a first potential, in
dependence of the voltage level of the first gain node; wherein the first output stage is activated if the current which is
sourced at the output node exceeds a pre-determined first maintenance current;

the second output stage configured to sink a current at the output node to a second potential, in dependence of the voltage
level of the second gain node; wherein the first potential is different from the second potential; wherein the second output
stage is activated if the current which is sunk at the output node exceeds a pre-determined second maintenance current; and

a first operating point control circuit configured to set the voltage level of the first gain node such that the first maintenance
current is sourced by the first output stage, when the second output stage is activated; and/or

a second operating point control circuit configured to set the voltage level of the second gain node such that the second
maintenance current is sunk by the second output stage, when the first output stage is activated,
wherein
the second operating point control circuit comprises a second reference current source configured to provide a second reference
current;

the second operating point control circuit comprises a second reference transistor arranged in series with the second reference
current source;

the second reference transistor is controlled based on a feedback current through the second output stage;
a midpoint between the second reference current source and the second reference transistor is coupled to a gate of a clamp
transistor configured to set the level of the second gain node; and

the second maintenance current is dependent on the second reference current;wherein the amplification stage is configured to activate the first output stage and the second output stage in a mutually
exclusive manner.

US Pat. No. 9,835,655

OUTPUT CURRENT MONITORING CIRCUIT

Dialog Semiconductor (UK)...

1. A current monitor, comprising:
a) a transistor, wherein a current flowing through this transistor is to be monitored and wherein this transistor is replicated
by a replica transistor;

b) said replica transistor, which is a scaled down version of the replicated transistor, wherein a drain of the replica transistor
is connected to a drain of the replicated transistor;

c) a sample and hold circuit, comprising a sampling switch, a resistor and a capacitor, is connected to a first input of an
operational transconductor, wherein the sample and hold circuit is configured to sample and hold input signals from a source
of the replica transistor during the time that the replicated transistor is powered on and hold the value of the input signals
during the time that the replicated transistor is switched off, wherein a first terminal of the sampling switch is connected
to a source of the replica transistor, a second terminal of the sampling switch is connected to a first terminal of the resistor,
a second terminal of the resistor is connected to a first terminal of the capacitor and to the first input of the operational
transconductor and a second terminal of the capacitor is connected to ground;

d) said operational transconductor (OTA) having two inputs and two current outputs, wherein the first input of said OTA is
connected via the sample and hold circuit to a source of the replica transistor and wherein a second input of said OTA is
connected to a source of the replicated transistor, wherein each output of the OTA is coupled to one of two current sources,
wherein the first current source is configured to drive a feedback loop to the source of the replica transistor and the second
current source is configured to provide an analog value of the replica transistor current to a current mode integrating analog
to digital converter for conversion into a digital current value;

e) said current mode integrating analog to digital converter (ADC) configured to provide a digital output of the current monitor;
and

f) wherein said replicated transistor is configured to produce the current to be monitored, wherein said OTA is configured
to control a source current of the replica transistor to be of a proportional current value as a source current of the replicated
transistor while said OTA is configured to produce an output current equivalent to the source current of the replicated transistors.

US Pat. No. 10,044,265

SWITCHING CONVERTER CONTROL ROBUST TO ESL RIPPLE

Dialog Semiconductor (UK)...

1. A switching converter, comprising:an output stage, configured to provide an output stage output voltage at an inductor, wherein said inductor is connected to an output capacitor at an output of said switching converter; and
a control block, configured to control said output stage based on a control input and a reference;
a logic gate, configured to invert said output stage output voltage, and configured to generate a signal swing proportional to said output stage output voltage;
a voltage divider, configured to attenuate an output voltage of said logic gate, and configured to generate a cancelling signal; and
an adder, configured to add said cancelling signal to a converter output voltage of said switching converter, to generate a control signal input.

US Pat. No. 9,997,946

BATTERY CHARGING SYSTEM WITH FEEDBACK CONTROL

Dialog Semiconductor (UK)...

1. A charging system for a battery of an electronic device, wherein the charging system comprises,an adapter configured to derive a transfer current at a transfer voltage from a power source;
a battery charger configured to charge a battery of the electronic device with a battery current at a battery voltage using the transfer current at the transfer voltage; wherein the battery charger comprises a power converter;
power transmission means configured to transmit the transfer current at the transfer voltage to the battery charger; and
communication means configured to repeatedly transmit feedback information from the battery charger to the adapter; wherein the feedback information is indicative of the battery voltage and/or the battery current; wherein the adapter is configured to set the transfer voltage and/or the transfer current in dependence of the feedback information;
wherein the adapter comprises a voltage regulator that is configured to form a regulation loop for regulating the battery voltage in dependence of the repeatedly transmitted feedback information, such that the battery voltage is regulated to a desired battery voltage using voltage step-down conversion with a conversion ratio of n performed by the power converter, with n being an integer equal to or greater than 1.

US Pat. No. 9,998,107

CURRENT-CONTROLLED ACTIVE DIODE

Dialog Semiconductor (UK)...

1. An active diode circuit for letting current pass in one direction and substantially blocking current in the opposite direction, the active diode circuit comprising:a transistor;
a control voltage generation circuit for generating a control voltage that is supplied to a control terminal of the transistor; and
a sensing circuit for detecting a quantity indicative of a current flowing through the transistor,
wherein the control voltage generation circuit is configured to generate the control voltage in dependence on the detected quantity,
wherein the control voltage generation circuit is further configured to:
detect oscillations in a voltage drop across the transistor; and
on detection of an oscillation, output, as the control voltage, a first voltage that is sufficient to drive the transistor in the fully conducting state,
wherein oscillations in the voltage drop are detected if a number of fluctuations of the voltage drop per time unit exceeds a predetermined threshold value for the number of fluctuations, counting only those fluctuations that are larger than a predetermined threshold for the fluctuations.

US Pat. No. 9,972,998

SHORT CIRCUIT SELF-PROTECTED DC-TO-DC BUCK CONVERTERS

Dialog Semiconductor (UK)...

1. A buck converter configured to operate in Continuous Conduction Modulation (CCM) Pulse Frequency Modulation (PFM), enabled for self-protection of the buck converter against short circuit or overload at the output of the buck converter by a self-protection loop, for managing a recovery from the short or overload condition of the buck converter and for an intrinsic soft start-up preventing excessive in-rush currents, comprising:an output stage comprising a high side switch and a low side switch both connected in series, wherein the output stage is configured to connected to a coil having a first terminal at a node between the high side switch and the low side switch;
a high-side current sense circuit, configured to sense a current through the high side switch;
a first overcurrent comparator configured to compare an output signal of the high-side current sense circuit with a reference current, wherein, in case of a short or an overload, an output signal of the first overcurrent comparator is enabled to control the high side switch, wherein the first overcurrent comparator is coupled to a minTon unit;
said minTon unit configured to define a minimum on-time of the high switch, wherein the minTon unit receives input from an AND logical gate;
a second overcurrent comparator configured to compare the output signal of the high-side current sense circuit with the reference current, wherein, in case of a short or an overload, an output signal of the first overcurrent comparator is triggered and initiates a signal CLK Limit to be set to low, wherein the CLK Limit signal is a second input of said AND logical gate, while the buck converter is set from a high impedance mode to a low impedance mode;
a minToff time unit configured to limit a maximum switching frequency of the buck converter, wherein the minToff time unit is coupled to an input of the output stage of the buck converter and to a first input of said logical AND gate;
said logical AND gate having inputs and an output, wherein a second input is the CLK Limit signal and a third input is an output of said voltage comparator, wherein the output of the logical AND gate is coupled to the output stage of the buck converter, wherein, in case of a short, a current in the coil is forced to decrease until it reaches a low crossing value Izero ref and at the moment the current through the coil reaches Izero ref, the signal CLK Limit is set high via the second overcurrent comparator, the buck converter is set in the high impedance mode again, the logical AND gate is no longer gated and the buck converter is enabled to recover normal operation and, if the short is not removed, the short self-protection loop is repeated;
said voltage comparator configured to compare an output voltage (Vout) of the buck converter with a reference voltage; and
a current coil low crossing detector configured to detect when the current through the coil reaches said defined low crossing value Izero ref.

US Pat. No. 9,960,755

LOW VOLTAGE SWITCHING GATE DRIVER UNDER A HIGH VOLTAGE RAIL

Dialog Semiconductor (UK)...

1. A switching gate driver, comprising:a first voltage source;
a clamping voltage source, configured to have a voltage that is less than that of said first voltage source;
a current path, for initial charging of a gate voltage of said switching gate, between said first voltage source and a ground source wherein said gate voltage is an input to a comparator and, wherein said current path is used to charge a gate capacitance; and
said comparator which is configured to clamp said gate voltage to said clamping voltage source as it approaches the voltage of said clamping voltage source.

US Pat. No. 9,946,276

VOLTAGE REGULATORS WITH CURRENT REDUCTION MODE

Dialog Semiconductor (UK)...

1. A voltage regulator configured to provide an output current at an output voltage at an output node, based on an input voltage at an input node, wherein the voltage regulator comprises,a pass transistor for deriving the output current at the output node from the input voltage at the input node;
a drive transistor forming a current minor in conjunction with the pass transistor, such that the output current through the pass transistor is dependent on a drive current through the drive transistor;
an auxiliary transistor arranged such that at least a fraction of the drive current through the drive transistor flows through the auxiliary transistor;
amplification circuitry configured to set the drive current through the drive transistor in dependence of the output voltage and in dependence of a reference voltage, if the voltage regulator is regulating the output voltage; and
control circuitry configured to
detect an indication for a dropout situation where a difference between the input voltage and the output voltage falls below a dropout voltage of the voltage regulator; and
in reaction to this, increase a resistance of the auxiliary transistor to reduce the fraction of the drive current flowing through the auxiliary transistor.

US Pat. No. 9,935,553

CONTROL SCHEME FOR HYSTERETIC BUCK CONTROLLER WITH INDUCTOR COIL CURRENT ESTIMATION

Dialog Semiconductor (UK)...

1. A power converter, comprisinga buck converter comprising a high side switch, an inductor and a low side switch;
a current sensing circuit configured to sense a current through the low side switch;
a positive slope inductor coil current estimator circuit configured to estimate a magnitude of a current through the inductor while the high side switch is ON, wherein an output voltage Vout of the power converter is one of parameters used for said estimation;
an error amplifier configured to sense the output of said buck converter;
a compensation network configured to receive a feedback signal from said error amplifier;
a first comparator configured to provide a comparison signal in parallel to said current sensing circuit and said positive slope inductor coil current estimator; and
a second comparator configured to provide a comparison signal in parallel to said positive slope inductor coil current estimator;
wherein said error amplifier and said compensation network are configured to provide a comparison signal by comparing by the error amplifier an output voltage of the power converter with a reference voltage, wherein the comparison signal is a base for a first error signal, which is shifted up by an offset voltage, wherein the first error signal is a first input to the first comparator, wherein a second input of the first comparator is an output of the positive slope inductor coil estimator and wherein the comparison signal is a base for a second error signal, which is shifted down by the offset voltage, wherein the second error signal is a first input to the second comparator, wherein a second input of the second comparator is an output of said current sensing circuit.

US Pat. No. 9,793,798

COMPENSATION OF ERRORS IN CURRENT LIMITERS

Dialog Semiconductor (UK)...

19. A current detector circuit comprising:
an extraction module arranged to extract an electrical parameter associated with a circuit component;
a slope extractor module arranged to store information about the rate of change of the extracted electrical parameter and
to extrapolate a measured electrical parameter value based on the stored rate of change information;

a converter module arranged to determine a boundary current value based on an extrapolated electrical parameter value.

US Pat. No. 10,122,260

SWITCHED-MODE POWER CONVERTER WITH A CURRENT LIMIT CIRCUIT

Dialog Semiconductor (UK)...

1. A switched-mode power converter comprisinga feedback loop for controlling the output voltage of the switched-mode power converter;
a first voltage comparison unit within the feedback loop configured to compare a voltage indicative of the output voltage with a reference voltage and to output an error voltage based on the comparison;
a current control unit for limiting an input current into the switched-mode power converter, the current control unit comprising
a current comparison unit configured to compare the input current with a current threshold and to output an intermediate voltage based on the comparison, and
a connection unit connected to the output of the current comparison unit and configured to connect, in case the input current exceeds the current threshold, the output of the current comparison unit to the output of the first voltage comparison unit;
wherein the current comparison unit comprises a voltage clamp whose output is connected to the output of the current comparison unit and the current comparison unit is configured to adjust the immediate voltage based on a clamp reference voltage at an input of the voltage clamp, and wherein the current control unit is configured to set, by adjusting the clamp reference voltage, the intermediate voltage such that an over-shoot of the input current is reduced.

US Pat. No. 10,116,207

HYSTERETIC CONTROLLER WITH FIXED-FREQUENCY CONTINUOUS CONDUCTION MODE OPERATION

DIALOG SEMICONDUCTOR (UK)...

1. A switching power converter, comprising:a hysteresis comparator configured to respond to an error current signal to produce a comparator output signal;
a pulse generator configured to generate a set pulse signal that is pulsed at a fixed frequency and configured to generate a reset pulse signal that is pulsed at the fixed frequency;
a first logic gate configured to process the comparator output signal with the set pulse signal to generate a latch set signal;
an inverter for inverting the comparator output signal to form an inverted comparator output signal;
a second logic gate configured to process the inverted comparator output signal with the reset pulse signal to generate a latch reset signal;
an operational transconductance amplifier configured to amplify a difference between an output voltage for the switching power converter and a reference voltage to generate the error current signal;
a clock source for clocking the pulse generator with a clock signal, wherein the clock signal has a switching frequency equal to twice the fixed frequency;
a power switch; and
a latch configured to close the power switch in response to an assertion of the latch set signal and configured to open the power switch in response to an assertion of the latch reset signal.

US Pat. No. 10,116,210

DAC SERVO

Dialog Semiconductor (UK)...

1. A switching converter, comprising:a Digital-to-Analog Converter (DAC) configured to supply a DAC voltage to said switching converter;
a servo block connected to receive a feedback voltage and configured to modify said DAC voltage for one or more modes of operation, wherein said servo block is configured independently of switching modes of said switching converter, and wherein said servo block further comprises a first GM stage driving a capacitor and a second GM stage driving a resistor, wherein said second GM stage is a PMOS transistor, and an output of said first GM stage is connected to a gate of said second GM stage;
control loops configured to receive an output of said servo block, and said feedback voltage;
switching logic configured to receive the output signals of said control loops; and
an output stage, driven by said switching logic, configured to supply the output voltage of said switching converter.

US Pat. No. 10,056,838

CIRCUIT AND METHOD FOR REDUCING ANALOG BUCK CURRENT CONTROL LOOP SENSITIVITY TO SUPPLY PATH RESISTANCE

Dialog Semiconductor (UK)...

1. A power converter circuit for converting an input voltage received at an input node and providing, at an output node, a current at the converted voltage, the power converter circuit comprising:a DC-DC converter circuit for generating the current at the output node under control of a control signal, wherein the DC-DC converter circuit is controlled by the control signal to reduce the current at the input node if there is a drop in the input voltage;
a current sensing circuit for sensing a current indicative of a current at the input node;
a voltage adjustment circuit for sensing a voltage indicative of the input voltage and generating an adjusted voltage on the basis of the sensed voltage and the sensed current; and
an error amplifier stage for generating the control signal on the basis of the adjusted voltage and a reference voltage,
wherein the adjusted voltage is generated by adding a portion of the sensed current, after conversion to a voltage domain, to the sensed voltage, so that a loop gain of a control loop for the current at the input node has reduced sensitivity to an input resistance of a supply path that is connected to the input node and supplies the input voltage.

US Pat. No. 10,038,328

DIGITAL TEMPERATURE CONTROL FOR POWER SUPPLY DEVICES

Dialog Semiconductor (UK)...

12. A power supply device for providing power to an external device, using a digital temperature control method comprising steps of:measuring a temperature of the power supply device;
converting the measured temperature to a digitized temperature;
comparing the digitized temperature to at least one temperature threshold;
selecting a digital control algorithm from a plurality of digital control algorithms and applying the selected digital control algorithm on a controlled system variable associated with the selected digital control algorithm, thereby obtaining a control value;
verifying the obtained control value; and
applying the verified control value to control the power supply device to supply the power to the external device.

US Pat. No. 9,917,510

MULTI-STAGED BUCK CONVERTER WITH EFFICIENT LOW POWER OPERATION

DIALOG SEMICONDUCTOR (UK)...

1. A method of operating a two-staged DC/DC power converter comprising:
dividing an input voltage in a charge pump clocked according to a first frequency for a clock signal to produce a charge pump
output voltage;

while the charge pump is clocked according to the first frequency, operating a multi-phase buck converter using each phase
in a plurality of phases to convert the charge pump output voltage into a regulated buck converter output voltage responsive
to an output load, each phase including an inductor, a high-side switch, and a low-side switch;

adjusting the clock signal to cycle at a second frequency lower than the first frequency;
clocking the charge pump according to the second frequency of the clock signal to divide the input voltage to produce the
charge pump output voltage; and

while the charge pump is clocked according to the second frequency, operating the multi-phase buck converter with a reduced
set of the phases to convert the charge pump output voltage into the regulated buck converter output voltage, wherein the
reduced set of phases is less than the plurality of phases by a phase reduction, and wherein the second frequency is lower
than the first frequency by a frequency reduction that is proportional to the phase reduction.

US Pat. No. 9,887,625

OUTPUT CURRENT MONITOR CIRCUIT FOR SWITCHING REGULATOR

Dialog Semiconductor (UK)...

1. A circuit providing switching regulation with an improved current monitor, comprising:
a pulse width modulation (PWM) controller configured to provide P- and N-drive signals;
an output stage connected to said PWM controller and configured to provide switching, comprising a high-side and low-side
transistor, driven by said P- and N-drive signals, respectively;

a sense circuit configured to provide output current sensing from said output stage during a sampling period when said N-drive
signal is active;

a sampling timing generator configured to provide an n-sampling signal to said sense circuit, wherein a start of said n-sampling
signal is delayed by a first delay after a start of said sampling period and said sampling period is ended by a second delay
after said n-sampling signal is ended, wherein said sampling timing generator comprises a first flip-flop coupled to a master
clock, a first delay circuit coupled to a second flip-fop, an inverter coupled to said first flip-flop, and an AND logic gate
coupled to said inverter

wherein said sampling timing generator comprises:
said first flip-flop coupled to a master clock configured to set by a rise of said master clock and configured to be reset
when said n-sampling signal is inactive; and

said first delay circuit coupled to a second flip-flop wherein said second flip-flop is configured to be set by a delayed
N-drive signal, and configured to reset when said N-drive signal is inactive or when said first flip-flop is active, and said
first delay circuit is configured to generate the delayed N-drive signal from said N-drive signal.

US Pat. No. 9,882,477

DRIVE SCHEME FOR WEAKLY COUPLED COILS

Dialog Semiconductor (UK)...

1. A switch converter, the device comprising:
a converter control circuit configured to receive input from an output monitor circuit and providing outputs to an array of
multiple phase control units;

said array of multiple phase control units, wherein each phase control unit is configured to control an assigned phase unit
of a multiphase switch;

a multi-phase switch configured to receive an input voltage of the switch converter, wherein the multi-phase switch comprises
at least two phase units, wherein each phase unit comprises a pair of complementary switches connected in series between said
input voltage and common ground, and is configured to control an assigned coil of an arrangement of mutually weakly coupled
inductive coils by a pair of complementary phase signals;

said arrangement of mutually weakly coupled inductive coils, wherein each coil is connected to the assigned phase unit of
the multi-phase switch;

wherein the switch converter is capable of tuning the inductance of the arrangement of mutually weakly coupled inductor coils
to provide a lower inductance for fast converter response or a higher inductance for suppression of current ripple, wherein
the inductance tuning is performed by phase delay control between switching times of the multi-phase switch and wherein each
phase unit of the multi-phase switch is capable of receiving phase control signals from said array of multiple phase control
units and transferring them into phases needed for sync modes and sleep modes;

wherein said arrangement of mutually weakly coupled inductive coils connected to output phase signals of the multi-phase switches
is configured to increase effective inductance of the weakly coupled inductive coils by operating the weakly inductive coils
in a same polarity or to decrease effective inductance of the weakly coupled inductive coils by operating the weakly inductive
coils in an opposite polarity.

US Pat. No. 9,806,617

SWITCH MODE POWER CONVERTER WITH OVERSHOOT AND UNDERSHOOT TRANSIENT CONTROL CIRCUITS

Dialog Semiconductor (UK)...

1. A control circuit for controlling overshoot and/or undershoot of the output voltage of a switch mode power converter (SMPC)
in response to very large and rapid load current increase or decrease comprising:
at least one load variation detector connected for sensing a large and rapid increase or decrease in load current at an output
of the SMPC comprising:

a first input terminal connected for receiving a feedback signal indicative of an output voltage of the SMPC,
a second input terminal is connected for receiving a variation limit threshold reference voltage,
a comparator for comparing the feedback signal with the variation limit threshold reference voltage to determine that a large,
rapid load current increase or decrease has occurred and generates a panic voltage when the feedback signal exceeds the variation
limit threshold reference, and

an output terminal connected to receive the panic voltage from the comparator for communication to a switch stage of the SMPC
such that when the feedback signal has exceeded the variation limit threshold reference voltage, the panic voltage commands
the switch stage to activate for sourcing current through or sinking current from a filter stage of the SMPC and thus to or
from the load circuit to compensate to the large, rapid load current variation; and

a slope detector connected for receiving the feedback signal and the target reference voltage and configured for creating
a slope signal indicative of a slope of the output voltage determined from difference of the feedback signal and a target
reference voltage and configured for determining when the slope of the output voltage changes polarity and generating a slope
polarity signal for activating the switch stage for preventing an overshoot or undershoot of the output voltage of the SMPC
once the large and rapid current transient has been compensated.

US Pat. No. 9,768,682

SWITCHED CAPACITORS WITH INVERTED BREAK-BEFORE-MAKE WITHOUT EXTERNAL FILTERING LOAD CAPACITOR

Dialog Semiconductor (UK)...

1. A switched-capacitor power electronic circuit, comprising:
two or more charge pump circuits connected in parallel, configured to provide an output power;
each of said charge pump circuits having a flying capacitor for providing a current to a load; and
said switched-capacitor power electronic circuit is configured to connect some of said flying capacitors to said load, in
make-before break fashion, simultaneously after a charging period of one of said flying capacitors and prior to a charging
period of the other said flying capacitor, wherein during a period when said one of said flying capacitors is being charged,
and is disconnected from the load, the other said flying capacitor is still connected to the load.

US Pat. No. 10,299,330

CURRENT REGULATOR

Dialog Semiconductor (UK)...

1. A current regulator for regulating a current through a circuit element, comprising:a first node at a first voltage, the current through the circuit element being dependent on the first voltage;
a positive feedback loop coupled to the first node; wherein
the positive feedback loop is arranged to provide a signal to remove a voltage shift from the first voltage in response to a decrease or increase of the first voltage by the voltage shift.

US Pat. No. 10,063,132

OVER-CURRENT PROTECTION CIRCUIT

Dialog Semiconductor (UK)...

1. A current protection circuit for use with a switching converter comprising an energy-storing element coupled to a power switch via a switching node, the protection circuit comprisinga current sensor adapted to sense a current at the switching node and to convert the current into a voltage;
a converter adapted to convert the voltage into a first current associated with a first domain;
a level shifter coupled to the converter; the level shifter being adapted to convert the first current into a second current associated with a second domain;
a current comparator adapted to compare the second current with a reference current and to provide a logic signal based on the comparison.

US Pat. No. 10,048,710

BYPASS MODE FOR VOLTAGE REGULATORS

Dialog Semiconductor (UK)...

1. A voltage regulator configured to provide at an output node a load current at an output voltage, wherein the voltage regulator comprises,a pass transistor for providing the load current at the output node from an input node;
a driver stage configured to set a gate voltage at a gate of the pass transistor based on a drive current;
voltage regulation means configured to set the drive current in dependence of an indication of the output voltage at the output node and in dependence of a reference voltage for the output voltage;
bypass regulation means configured to set the drive current in dependence of an indication of a gate-to-source voltage at the pass transistor and in dependence of a target voltage for the gate-to-source voltage; and
mode selection means configured to activate the voltage regulation means and/or the bypass regulation means.

US Pat. No. 9,806,613

COMBINED HIGH SIDE AND LOW SIDE CURRENT SENSING

Dialog Semiconductor (UK)...

1. A current sensing circuit for a high side current through a high side switch and/or for a low side current through a low
side switch of a half bridge comprising the high side switch and the low side switch, which are arranged in series between
a high side potential and a low side potential; wherein the high side switch and the low side switch are in respective on-phases
in a mutually exclusive manner; wherein the current sensing circuit comprises,
a high side sensing circuit configured to provide a sensed high side current which is indicative of the high side current
during an on-phase of the high side switch; wherein the high side sensing circuit comprises mirroring circuitry which is configured
to mirror a current from a first node of the high side sensing circuit to an output node of the high side sensing circuit;
wherein the sensed high side current is provided at the output node; and

a low side sensing circuit configured to provide a sensed low side current which is indicative of the low side current during
an on-phase of the low side switch; wherein the sensed low side current is fed to the first node, such that the current at
the output node is indicative of the sensed low side current during the on-phase of the low side switch; wherein, during the
on-phase of the high side switch, the mirroring circuitry is configured to transform a voltage drop across the high side switch
into the sensed high side current at the output node.

US Pat. No. 10,172,197

DIMMABLE SINGLE-STAGE POWER CONVERTER WITH ADAPTIVE SWITCHING FREQUENCY CONTROL

DIALOG SEMICONDUCTOR, INC...

1. A method for a circuit with adaptive switching frequency control, the method comprising:operating a controller of a dimmable single-stage power converter in pulse width modulation (PWM) mode at a first switching frequency level from a maximum dimming duty-ratio level until a first dimming duty-ratio level;
operating the controller in PWM mode, while reducing switching frequency from the first switching frequency level to a second switching frequency level, from the first dimming duty-ratio level until a second dimming duty-ratio level;
operating the controller in PWM mode at the second switching frequency level from the second dimming duty-ratio level until a current command (Vipk) falls below a predetermined low limit value; and
operating the controller in skip mode, while reducing the switching frequency from the second switching frequency level, until a minimum dimming duty-ratio level is reached.

US Pat. No. 10,083,926

STRESS RELIEF SOLUTIONS ON WLCSP LARGE/BULK COPPER PLANE DESIGN

Dialog Semiconductor (UK)...

1. A wafer level chip scale package comprising:at least one redistribution layer connected to a wafer through an opening through a first polymer layer to a metal pad on a top surface of said wafer wherein said redistribution layer has a roughened top surface and wherein holes are formed through said at least one redistribution layer in an area where said redistribution layer has an area exceeding 0.2 mm2; and
at least one UBM layer contacting said at least one redistribution layer through an opening in a second polymer layer wherein said second polymer layer contacts said first polymer layer within said holes promoting cohesion between said first and second polymer layers and wherein said roughened top surface promotes adhesion between said at least one redistribution layer and said second polymer layer.

US Pat. No. 10,070,220

METHOD FOR EQUALIZATION OF MICROPHONE SENSITIVITIES

Dialog Semiconductor (UK)...

1. A system for equalization of microphone sensitivities, comprising:a Signal Classifier configured to receive a set of inputs from N microphones to determine when a noise field is diffuse;
said Signal Classifier configured to use Magnitude Squared Coherence to separate a coherent signal from a diffuse signal; and
a Signal Mismatch Estimator/Compensator configured to calculate a microphone mismatch and to apply a gain compensation to each of said microphone inputs;
said Signal Mismatch Estimator/Compensator configured to use a Kalman Filter to calculate said microphone mismatch;
said Signal Mismatch Estimator/Compensator configured for gain compensation, resulting in a scaled output equivalent to using an array of matched microphones.

US Pat. No. 10,014,780

MULTIPHASE SWITCHING CONVERTER

Dialog Semiconductor (UK)...

1. A multiphase switching converter comprising a plurality of phase circuits coupled with a common output node, whereineach phase circuit comprises a drive signal generator to generate a separate drive signal for a switching element of the respective phase based on a feedback signal from the common output node,
the converter comprises at least one error signal generator for generating a separate error signal for each phase based on the output voltage of the converter at the common output node,
the drive signal generators of the phase circuits generate the drive signals based on the error signals of the respective phase, and
the at least one error signal generator comprises an error amplifier for each phase which each generate the respective error signal of the phase, each error amplifier comprising a first input for receiving a reference signal and a second input for receiving a feedback signal that is derived from the output voltage of the converter.

US Pat. No. 10,008,918

PHASE-SHIFTING OPTIMIZATION FOR ASYMMETRIC INDUCTORS IN MULTI-PHASE DC-DC CONVERTERS

Dialog Semiconductor (UK)...

1. A multiphase DC-DC switching converter, comprising:n phases, with a pair of power switches on each phase, where n is two or more;
n asymmetric inductors, each of said asymmetric inductors connected to one of said pairs of power switches;
a single output, connected in parallel to each of said asymmetric inductors;
an error amplifier having as inputs said single output and a reference voltage;
n comparators configured to compare an output of said error amplifier and n ramp generator output signals, resulting in n pulse width modulation (PWM) signals, configured to be used as input signals to said pairs of power switches; and
a clock generator, configured to generate n phase-shifted clock signals for said ramp generator output signals,
wherein a phase-shift configuration is determined by said asymmetric inductors of said phases and said phase-shifted clock signals.

US Pat. No. 9,991,784

DYNAMIC CURRENT LIMIT CIRCUIT

Dialog Semiconductor (UK)...

1. A dynamic current limit circuit, comprising:a first current Digital to Analog Converter (IDAC), configured to provide a reference current source, for a sync current output;
a dynamic sleep amplifier, configured to subtract current from said sync current output in dynamic sleep mode and not active in sync mode;
a first mirror circuit, configured to mirror the difference between said sync current output and a dynamic sleep mode current output;
a second current Digital to Analog Converter (IDAC), configured to provide a reference current source, for a sleep current output;
a second mirror circuit, configured to subtract said dynamic sleep mode current output from said sleep current output, setting the sleep current output; and
a third mirror circuit, configured for dynamic sleep mode.

US Pat. No. 9,970,979

MOS TRANSISTOR SATURATION REGION DETECTOR

Dialog Semiconductor (UK)...

1. A circuit for determining whether a first transistor device is in a predetermined operation mode, comprising:a second transistor device, wherein gate terminals of the first and second transistor devices are connected, and a drain terminal of the first transistor device is connected to a source terminal of the second transistor device;
a buffer amplifier connected between the drain terminal of the first transistor device and the source terminal of the second transistor device, wherein an output of the buffer amplifier is directly connected to the source terminal of the second transistor device and an input of the buffer amplifier is supplied by the drain terminal of the first transistor device; and
a circuitry for determining whether the first transistor device is in the predetermined operation mode based on an indication of a current flowing through the second transistor device.

US Pat. No. 9,806,698

CIRCUIT AND METHOD FOR A ZERO STATIC CURRENT LEVEL SHIFTER

Dialog Semiconductor (UK)...

1. A level shift circuit, comprising:
an input in low voltage domain and an output in a high voltage domain;
first and second gating device coupled to said input;
first and second error sensing devices coupled to a said first and second gating devices, respectively;
a logic block configured to monitor a state of said output and to control of said first and second gating devices; and
wherein said first and second error sensing devices are coupled to a memory device configured to store said state of said
output.

US Pat. No. 10,186,942

METHODS AND APPARATUS FOR DISCHARGING A NODE OF AN ELECTRICAL CIRCUIT

Dialog Semiconductor (UK)...

8. A circuit for discharging a node, comprising:a current source;
mirror circuitry that mirrors an input bias current from the current source to a pull down device coupled with the node, wherein said mirror circuitry is configured to receive the input bias current from the current source and sink a mirrored discharge current from the node, the mirrored discharge current being defined in relation to the input bias current by a transfer function;
an output device that is coupled between the current source and the mirror circuitry, and is coupled with the node; wherein
the output device is arranged to transition between a first discharging phase in which the mirror circuitry provides current mirror sinking to partially discharge the node and a second discharging phase in which the current mirror sinking stops operating and a resistance provided by the pull down device discharges the node;
wherein the node is discharged after completion of the second discharging phase; and
the second discharging phase occurs after the first discharging phase; and wherein the output device comprises a transistor which operates in a linear mode of operation and functions as a variable resistor while in the first discharging phase and which operates in a saturation mode of operation in the second discharging phase.

US Pat. No. 10,186,967

SWITCHING CONVERTER WITH RAMP-BASED OUTPUT REGULATION

Dialog Semiconductor (UK)...

11. A method of regulating an output value of a switching converter comprisinggenerating a ramp signal with a ramp generator to regulate an output of the converter;
detecting a parameter associated with the ramp signal;
providing a feedback circuit coupled to the ramp generator, wherein the feedback circuit comprises a controller adapted to output a tunable current based on the parameter of the ramp signal; and
adjusting a delay of the ramp signal based on the parameter by comparing the parameter associated with the ramp signal with a constant reference value and generating the tunable current based on the comparison;
wherein the ramp generator comprising a delay circuit comprising a current generator coupled to a delay capacitor; and wherein the delay circuit is adapted to receive the tunable current such that upon injection the tunable current changes a time required for charging the delay capacitor up to a voltage reference value.

US Pat. No. 10,181,792

SENSOR-LESS BUCK CURRENT REGULATOR WITH AVERAGE CURRENT MODE CONTROL

DIALOG SEMICONDUCTOR (UK)...

1. A buck converter controller integrated circuit comprising:a replica circuit including a replica transistor and a current sense amplifier, wherein the current sense amplifier is configured to drive the replica transistor with a first replica current equaling a scaled version of a current through a low-side switch transistor, and wherein the current sense amplifier is further configured to output a second replica current equaling another scaled version of the current through the low-side switch transistor;
a sample switch configured to sample the second replica current during a sampling window to produce a sampled signal;
an error amplifier configured to compare the sampled signal to a first reference signal to generate an error signal during the sampling window; and
a controller configured to control a cycling of a high-side switch transistor and the low-side switch transistor responsive to the error signal,
wherein the sample switch is disposed between the current sense amplifier and the error amplifier such that when the sample switch is open, the sampled signal is held at the error amplifier for the error signal.

US Pat. No. 10,181,794

TWO-STAGE MULTI-PHASE SWITCH-MODE POWER CONVERTER WITH INTER-STAGE PHASE SHEDDING CONTROL

DIALOG SEMICONDUCTOR (UK)...

1. A two-stage multi-phase switching power converter, comprising:a first stage including:
a plurality of first-stage phases configured to convert an input voltage into an intermediate output voltage;
a phase selection control circuit configured to activate an active number of first-stage phases selected from the plurality of first-stage phases responsive to an application of a load, wherein each first-stage phase includes a first-stage pulse-width modulator responsive to a first clock signal having a nominal frequency during a nominal mode of operation prior to the application of the load and having an increased frequency during a transition period responsive to the application of the load, wherein the increased frequency is greater than the nominal frequency; and
a second stage including a plurality of second-stage phases configured to convert the intermediate output voltage into an output voltage, wherein each second-stage phase includes a second-stage pulse-width modulator responsive to a second clock signal having a second frequency that is greater than the nominal frequency.

US Pat. No. 10,181,843

ADAPTIVE CONTROL OF THE NON-OVERLAP TIME OF POWER SWITCHES

Dialog Semiconductor (UK)...

1. Control circuitry for controlling a non-overlap time for a first switch and a second switch, which are arranged in series and which are controlled using a first control signal and a second control signal, respectively; wherein within a first state, the first switch is closed and the second switch is open, and within a second state, the first switch is open and the second switch is closed; wherein the first switch and the second switch are controlled to be alternatingly in the first state and in the second state; wherein the control circuitry comprises,a first auxiliary switch and a second auxiliary switch, which are arranged in series, and which are controlled using a first auxiliary control signal and a second auxiliary control signal, respectively, which are dependent on the first control signal and the second control signal, respectively; and
control means configured to
determine whether during a transition from the first state to the second state a current has flown through the serial arrangement of the first auxiliary switch and the second auxiliary switch; and
adapt a non-overlap time between the first control signal and the second control signal for controlling a following transition from the first state to the second state, dependent on whether during said transition from the first state to the second state a current has flown through the serial arrangement of the first auxiliary switch and the second auxiliary switch.

US Pat. No. 10,181,854

LOW POWER INPUT BUFFER USING FLIPPED GATE MOS

Dialog Semiconductor (UK)...

1. An input buffer circuit configured to operate with a high voltage supply and to receive an input signal at a first voltage range from a signal source operating at a low voltage supply, wherein the input buffer comprises:a dual reference voltage generator circuit comprising a current source, a normal transistor of the first conductivity type, and a flipped-gate anti-doped transistor of the first conductivity type connected between a power supply voltage source and a ground reference source and configured such that a first reference voltage is the threshold voltage of the flipped-gate anti-doped transistor of the first conductivity type and a second reference voltage is the threshold voltage of the flipped-gate anti-doped transistor of the first conductivity type less the threshold voltage of the normal transistor of the first conductivity type; and
a receiver connected to the dual reference voltage generator circuit to receive the first reference voltage and the second reference voltage, and connected to the signal source to receive the input signal, and configured to compare the input signal with the second reference voltage signal, when the output of the receiver is in the low output state, and when the input signal and compare the input signal with the first reference voltage signal, when the output of the receiver is in the high output state, when the input signal is less than the first reference voltage, the output of the receiver is set to the low output state.

US Pat. No. 10,170,992

ADAPTIVE AMPLIFICATION ACTIVE FILTER FOR DIVIDER-LESS HIGH FREQUENCY DC-DC CONVERTERS

Dialog Semiconductor (UK)...

1. A power converter for performing power conversion and for generating an output voltage in accordance with a reference voltage for the output voltage, the power converter comprising:a filter circuit for filtering the output voltage of the power converter;
an error amplifier circuit that receives the reference voltage as a first input voltage and receives the filtered output voltage as a second input voltage, for comparing the first input voltage and the second input voltage and for generating an error voltage in accordance with a result of the comparison; and
a driver circuit for driving one or more switching devices in dependence on the error voltage;
wherein the error amplifier circuit comprises:
a first differential circuit that receives the first input voltage and the second input voltage as inputs and a first bias current generation circuit for generating a first bias current for the first differential circuit;
a second differential circuit that receives the first input voltage and the second input voltage as inputs and a second bias current generation circuit for generating a second bias current for the second differential circuit; and
a bias current redistribution circuit for redistributing at least part of the first bias current to the second differential circuit or redistributing at least part of the second bias current to the first differential circuit.

US Pat. No. 10,152,071

CHARGE INJECTION FOR ULTRA-FAST VOLTAGE CONTROL IN VOLTAGE REGULATORS

Dialog Semiconductor (UK)...

1. A circuit for generating an output voltage and regulating the output voltage to a target voltage, the circuit comprising:a switchable voltage divider circuit configured to generate a voltage that is a variable fraction of the output voltage;
an error amplifier stage configured to generate a control voltage on the basis of a reference voltage and the variable fraction of the output voltage;
a buffer stage configured to generate the output voltage on the basis of the control voltage; and
a charge injection circuit configured to inject charge at an intermediate node between the error amplifier stage and the buffer stage to thereby modify the control voltage generated by the error amplifier stage,
wherein the charge injection circuit is configured to inject the charge at the intermediate node to quickly raise or lower the output voltage to the target voltage; and
wherein the charge injection circuit comprises:
a first capacitive element; and
a switching circuit configured to be switchable to a first configuration in which the first capacitive element is disconnected from the intermediate node and coupled between the output voltage and a first voltage level below the output voltage, and a second configuration in which the first capacitive element is coupled between the intermediate node and a second voltage level above the first voltage level.

US Pat. No. 10,128,757

BUCK-BOOST CONVERTER WITH SMALL DISTURBANCE AT MODE TRANSITIONS

Dialog Semiconductor (UK)...

1. A Buck-Boost switching power converter, comprising:a mode transition detector, configured to monitor Buck and Boost pulse-width modulation (PWM) input signals, and to detect skipping or regeneration of said input signals;
an error amplifier;
a main compensation capacitor, at an output of said error amplifier; and charge and discharge circuitry, comprising a PMOS current source, and a NMOS current source, configured to charge or discharge said main compensation capacitor during a mode transition, based on detection of said mode transition by said mode transition detector,
wherein for a mode transition from Buck to ½frequency Buck, from Buck to Buck-Boost, from Buck-Boost to Boost, and from ½frequency Boost to Boost, said PMOS current source is configured to be on, and
wherein for a mode transition from Boost to ½frequency Boost, from Boost to Buck-Boost, from Buck-Boost to Buck, and from ½frequency Buck to Buck, said NMOS current source is configured to be on.

US Pat. No. 10,103,633

SWITCHING CONVERTER WITH POWER LEVEL SELECTION

Dialog Semiconductor (UK)...

1. A switching converter comprising:a first power switch coupled to a second power switch via a switching node;
an inductor coupled to the switching node; and
a clamp circuit comprising a third power switch coupled in parallel to the first power switch;
the switching converter being adapted to disable the first power switch and to enable control of the third power switch upon identifying that the switching converter provides a low level of power;
wherein the third power switch comprises a power transistor having a first terminal coupled to a ground, a second terminal coupled to the switching node; and a third terminal coupled to a capacitor; wherein the first terminal is a gate terminal; and
the clamp circuit comprising a control switch coupled in parallel between the first terminal and the second terminal of the third power switch, and a resistor coupled in parallel between the first terminal and the third terminal of the third power switch.

US Pat. No. 10,007,289

HIGH PRECISION VOLTAGE REFERENCE CIRCUIT

Dialog Semiconductor (UK)...

1. A high precision voltage reference circuit, comprising:a first and second NMOS device, wherein the drain of said first NMOS device and the gates of said first and said second NMOS device are connected, and the gate and the source of said second NMOS device are connected at an output node;
a current mirror circuit, wherein said current mirror circuit supplies a first current to said drain and gate of said first NMOS device, and a second current to the drain of said second NMOS device; and
a resistor, wherein said resistor is connected to said output node, to modify the output of said current mirror.

US Pat. No. 10,334,667

POWER CONVERTER CONTROLLER

Dialog Semiconductor (UK)...

1. A controller for controlling a power converter to convert electrical power at an input voltage into electrical power at an output voltage, the controllercomprising
an input port configured to receive a voltage representative of the input voltage;
an input voltage measuring unit configured to sample a measuring voltage and determine a measurement value that is representative of the input voltage;
a switch;
a diode connectable with a storage unit to provide a supply voltage for the controller during operation of the controller, and
a resistor which forms a voltage divider with an external resistor connected to the input port, the input voltage measuring unit connected with a terminal of the resistor to measure a portion of the input voltage, the portion determined by the voltage divider ratio;
wherein the switch is controlled to control charging of the storage unit from the voltage at the input port.

US Pat. No. 10,298,112

CIRCUIT FOR DRIVING A POWER SWITCH

Dialog Semiconductor, Inc...

1. An electronic circuit comprising:a first power switch coupled to a second power switch via a switching node;
a driver coupled to the first power switch, wherein the driver comprises an energy storing element coupled to the switching node;
a sensor to sense an electrical parameter of the driver; and
a charger coupled to the sensor and to the energy storing element, the charger being adapted to provide a charge current to charge the energy storage element, and to control the charge current based on the electrical parameter;
wherein the driver is adapted to provide a drive voltage to the first power switch, and wherein the electrical parameter is indicative of the drive voltage;
wherein the driver comprises a first transistor adapted to control the drive voltage; and wherein the sensor comprises a second transistor coupled to a first current source; wherein the second transistor is substantially identical to the first transistor.

US Pat. No. 10,298,134

SWITCHING CONVERTER SOFT START METHOD USING SCALED SWITCH SIZE

Dialog Semiconductor (UK)...

1. A DC-DC switching converter, comprising:An output stage, comprising:
a high side switch, a low side switch, and a slew rate detector; and
a scaled device switching stage configured to include one or more high side switches and low side switches in parallel to said output stage,
wherein said scaled device switching stage comprises at least one scaled high side switch, configured to increase an on-resistance during a startup period of said switching converter; and
wherein said slew rate detector is configured to monitor a chance in an output voltage of said output stage and to determine when said output voltage has settled.

US Pat. No. 10,185,347

STACKED POWER SUPPLY FOR REDUCED CURRENT CONSUMPTION

Dialog Semiconductor (UK)...

7. A method for providing electrical energy to first power consuming circuitry and to second power consuming circuitry; wherein the first power consuming circuitry consumes electrical power at a first voltage; and wherein the second power consuming circuitry consumes electrical power at a second voltage; the method comprising the steps of:arranging a first capacitor and a second capacitor in series between a high potential and a low potential; wherein a magnitude of the sum of the first voltage and the second voltage is smaller than an absolute difference between the high potential and the low potential;
arranging the first power consuming circuitry in parallel to the first capacitor;
arranging the second power consuming circuitry in parallel to the second capacitor;
setting a voltage at the first capacitor in accordance to the first voltage; and
setting a voltage at the second capacitor in accordance to the second voltage
providing a first voltage source and a second voltage source which are arranged in series; wherein the first voltage source provides electrical power at the first voltage; wherein the second voltage source provides electrical power at the second voltage;
providing a first current mirror which is coupled to a high side port of the first voltage source and which is coupled to a high side port of the first power consuming circuitry; and
providing a second current mirror which is coupled to a high side port of the second voltage source and which is coupled to a high side port of the second power consuming circuitry.

US Pat. No. 10,177,654

DUAL-EDGE PULSE WIDTH MODULATION FOR MULTIPHASE SWITCHING POWER CONVERTERS WITH CURRENT BALANCING

DIALOG SEMICONDUCTOR (UK)...

1. A method comprising:comparing an output voltage for a multi-phase DC-DC switching power converter to a reference voltage to produce a control voltage;
for a first inductor in the multi-phase DC-DC switching power converter, generating a first dual-ramp voltage signal having a first DC voltage level;
level-shifting the first dual-ramp voltage signal to form a second dual-ramp voltage signal having a second DC voltage level different from the first DC voltage level; and;
switching on a first power switch coupled to the first inductor according to a duty cycle determined responsive to a comparison of the second dual-ramp voltage signal to the control voltage, wherein the level-shifting of the first dual-ramp voltage signal adjusts the duty cycle of the first power switch to balance a current in the first inductor with a current in a second inductor for the multi-phase DC-DC switching power converter.

US Pat. No. 10,177,659

NULLING REVERSE RECOVERY CHARGE IN DC/DC POWER CONVERTERS

Dialog Semiconductor (UK)...

1. A switching mode power converter circuit, comprising:a first transistor switch and a second transistor switch coupled in series between an input voltage level and ground;
a control circuit for controlling switching operation of the first transistor switch and the second transistor switch; and
a detection circuit for sensing a voltage at an intermediate node arranged between the first transistor switch and the second transistor switch, for deriving an indication of a slope of the sensed voltage, and for generating a switching control signal for the control circuit on the basis of the derived indication of the slope of the sensed voltage,
wherein the control circuit is configured to set a first timing for activating the first transistor switch and/or a second timing for activating the second transistor switch on the basis of the switching control signal;
the detection circuit comprises a slope detector circuit;
the slope detector circuit is configured to:
derive the indication of the slope of the sensed voltage; and
generate one or more intermediate signals indicative of respective timings at which a magnitude of the slope of the sensed voltage exceeds a predetermined threshold; and
the slope detector circuit comprises:
a current mirror of two gate-connected transistors; and
a comparator,
wherein each transistor of the current mirror is coupled in series with a respective current source;
a first node between one of the transistors and its respective current source is coupled to a second node between the other one of the transistors and its respective current source via a resistance element;
the first node is coupled to the intermediate node arranged between the first and second transistor switches;
the second node is coupled to an input port of the comparator; and
an output of the comparator serves as one of the one or more intermediate signals.

US Pat. No. 10,172,557

WEARABLE BIOMETRIC DEVICE AND METHOD OF PERFORMING BIOMETRIC MEASUREMENTS

DIALOG SEMICONDUCTOR (UK)...

1. Wearable biometric device, comprising:a biometric sensor system adapted to measure a physiological property of a user's body in relation to two or more different locations at the body surface and to provide for each such location an associated primary signal indicative of said measured physiological property;
a detector system adapted to detect a level of coupling of the biometric sensor system with the body at each of the locations and to provide for each of the locations an associated secondary signal indicative of said detected level of coupling;
a signal processing unit adapted to receive the primary signals and the associated secondary signals and to generate an output signal indicative of said physiological property as a function of the received primary and secondary signals, such that the output signal's functional dependency on a first one of the primary signals is less than its functional dependency on a second one of the primary signals, if the secondary signal associated with the first one of the primary signals indicates a lower coupling level than the secondary signal associated with the second one of the primary signals.

US Pat. No. 10,170,986

HYBRID BUCK

Dialog Semiconductor (UK)...

1. A Hybrid Buck switching converter, comprising:one or more peak-mode phases and
one or more valley-mode phases,
wherein said peak-mode phases and said valley-mode phases are in use at the same time, in a multiphase converter, and configured to have coil currents controlled by a common control signal from an operational transconductance amplifier (OTA), using a peak current servo.

US Pat. No. 10,170,995

MULTIPHASE POWER CONVERTER

Dialog Semiconductor (UK)...

1. A multiphase power converter comprising a first and a second constituent switched-mode power converter, whereinthe first constituent switched-mode power converter is configured to provide, both in a first mode of operation and in a second mode of operation, a first phase current to an output of the multiphase power converter,
the second constituent switched-mode power converter is configured to provide, in the second mode of operation, a second phase current to the output of the multiphase power converter, and
the multiphase power converter is configured to switch, depending on an operation condition of the multiphase power converter, between the first mode of operation and the second mode of operation, and configured to adapt a first transconductance of the first constituent switched-mode power converter when switching between the first mode of operation and the second mode of operation.

US Pat. No. 10,141,835

PWM CONTROLLED LOOP WITH ANTI-WINDUP PROTECTION

Dialog Semiconductor (UK)...

1. A system configured to regulate an output voltage based on a reference voltage, wherein the system comprises,an error amplifier configured to determine an error voltage by cumulating a deviation of a feedback voltage from the reference voltage; wherein the feedback voltage is indicative of the output voltage;
a PWM unit configured to generate a pulse width modulated, referred to as PWM, control signal based on the error voltage and based on a PWM clock; wherein the PWM clock indicates successive cycles of the PWM control signal;
a voltage setting unit configured to set the output voltage based on the PWM control signal;
a saturation detection unit configured to detect a saturation situation of the system, during which the error voltage is built up in a saturated direction without impacting the PWM control signal; and
clamping means configured to interrupt a further build-up of the error voltage in the saturated direction while allowing a modification of the error voltage in an opposite direction, opposite to the saturated direction, if the saturation situation is detected.

US Pat. No. 10,110,125

SYSTEM AND METHOD OF DRIVING A SWITCH CIRCUIT

Dialog Semiconductor (UK)...

11. A switching converter, comprising:a switch circuit comprising a first power switch coupled to a second power switch, and
a driver coupled to the switch circuit, the driver being adapted to apply sequentially an electrical parameter to at least one of the first power switch and the second power switch, based on at least one adjustable driving sequence; the driver comprising:
a first set of electronic circuits comprising a plurality of buffers, each buffer of the plurality of buffers being switchable between a first state wherein said each buffer has a first impedance and a second state wherein said each buffer has a second impedance, the first impedance being larger than the second impedance; and
a first controller coupled to the first set of electronic circuits, wherein the first controller is adapted to switch at least one buffer of the plurality of buffers between the first state and the second state based on the at least one adjustable driving sequence;
wherein said each buffer comprises an output, and wherein the outputs of the buffers are connected to each other;
wherein the at least one adjustable driving sequence comprises a plurality of adjustable driving levels, and a plurality of adjustable time windows, each time window of the plurality of adjustable time windows being associated with a driving level among the plurality of adjustable driving levels;
wherein the first controller comprises a first circuit for setting the plurality of adjustable time windows and a second circuit for setting the plurality of adjustable driving levels;
the driver further comprising a buffer control unit coupled to the first circuit and to the second circuit; wherein the buffer control unit is adapted to receive timing information from the first circuit and driving level information from the second circuit and to generate a control signal to control the output of said each buffer of the plurality of buffers.

US Pat. No. 10,103,628

SWITCHLESS CAPACITIVE HIGH VOLTAGE SENSING

Dialog Semiconductor (UK)...

14. A method of sensing a current flowing through a pass device of a voltage converter, wherein the pass device is switchable between a conducting state and a non-conducting state, and wherein the voltage converter further comprises:a node for providing an indication of the current flowing through the pass device;
a capacitive element, wherein a first terminal of the capacitive element is coupled to a terminal of the pass device and a second terminal of the capacitive element is connected to said node;
a first switching element connected between the first terminal of the capacitive element and ground; and
a second switching element connected between the second terminal of the capacitive element and ground,
the method comprising the steps of:
controlling the first and second switching elements such that said node is isolated from the terminal of the pass device through the capacitive element while the pass device is in the non-conducting state; and
controlling the first and second switching elements such and the voltage at the terminal of the pass device is applied to said node during a first period of time for which the pass device is in the conducting state.

US Pat. No. 10,310,526

QUIESCENT CURRENT LIMITATION FOR A LOW-DROPOUT REGULATOR IN DROPOUT CONDITION

Dialog Semiconductor (UK)...

1. A voltage regulator circuit for outputting a regulated output voltage, comprisingan output terminal for outputting the output voltage;
a first circuit branch connected between an input voltage level and the output terminal;
a second circuit branch connected between the input voltage level and a predetermined voltage level, the second circuit branch comprising a first switching element and a second switching element connected in series;
a first current mirror for mirroring a current flowing in the second circuit branch to the first circuit branch;
a first feedback circuit for controlling the first switching element in dependence on the output voltage to thereby regulate the output voltage; and
a second feedback circuit for controlling the second switching element,
wherein the second feedback circuit comprises a current sensing means for sensing a current that depends on a current flowing in the first circuit branch; and
the second feedback circuit is configured to control the second switching element such that the current flowing through the second circuit branch is limited to a current that is in a predetermined first ratio to the current sensed by the current sensing means,
thereby limiting a quiescent current at low load currents, wherein the second switching element is a transistor that forms a current mirror with another transistor that is coupled in series with the current sensing means and that conducts the sensed current.

US Pat. No. 10,298,210

APPARATUS AND METHOD FOR TEMPERATURE MEASUREMENT AND/OR CALIBRATION VIA RESONANT PEAKS IN AN OSCILLATOR

Dialog Semiconductor (UK)...

1. A method for providing a temperature measurement and calibration utilizing resonant peaks, comprising the steps of:(a) providing a circuit on a semiconductor chip, the circuit comprising a resonant device and amplifier,
(b) switching the chip on at low temperature in a high gain-bandwidth mode wherein the circuit starts oscillating at a first frequency;
(c) measuring a first frequency, using a reference source from a tester;
(d) changing the oscillator to a low gain-bandwidth mode wherein the circuit oscillations switch to a second frequency secondary peak, wherein said second frequency is lower than said first frequency
(e) measuring the second frequency, using the reference source from the tester;
(f) using an on-chip heater or external heater/cooler to change the temperature of the chip;
(g) measuring a third frequency, using the reference source from the tester;
(h) changing the oscillator to the high gain-bandwidth mode wherein the circuit oscillations switch back to the first frequency;
(i) measuring a fourth frequency, using the reference source from the tester;
(j) repeating steps e-h for as many additional temperature points as necessary; and
(k) constructing a model for frequency v temperature variation for the second frequency secondary resonant peak, using globally averaged values, taking into account any frequency offset as determined by the second frequency.

US Pat. No. 10,298,014

SYSTEM AND METHOD FOR CONTROLLING SOLID STATE LAMPS

Dialog Semiconductor (UK)...

1. A solid state lamp driver circuit comprising:a switching regulator;
an input detector arranged to receive an input power supply and output a control signal which depends on a frequency of the input power supply; and
a control device arranged to receive the control signal and to enable operation of the switching regulator or to short the switching regulator according to the control signal.

US Pat. No. 10,298,124

HYBRID DCDC POWER CONVERTER WITH INCREASED EFFICIENCY

Dialog Semiconductor (UK)...

1. A power converter configured to convert power between a first converter voltage at a first converter port and a second converter voltage at a second converter port; wherein the first and second converter voltages are relative to ground; wherein the power converter comprises,a first capacitor network;
an inductor; wherein the inductor exhibits a saturation current;
a first switching matrix configured to arrange the first capacitor network and the inductor within different states, including
a bypass state enabling current to flow from the first converter port through the first capacitor network via a bypass path to the second converter port without going through the inductor; and
an inductor state enabling current to flow from the first converter port or from ground through the inductor to the second converter port; and
a control unit configured to control the first switching matrix repeatedly in a recurrent sequence of different states; wherein the sequence of different states comprises the bypass state and the inductor state; wherein the control unit is configured to vary a duty cycle of the different states in dependence of a target conversion ratio between the first converter voltage and the second converter voltage; the control unit is configured to control the first switching matrix such that through the use of a bypass path bypassing the inductor a maximum total converter current at the second converter port is higher than the saturation current of the inductor; the control unit is configured to control the first switching matrix such that through the use of the bypass path bypassing the inductor a maximum total converter current at the second converter port is higher than the saturation current of the inductor.

US Pat. No. 10,298,163

APPARATUS AND METHOD FOR CONTROLLING A HAPTIC ACTUATOR

Dialog Semiconductor (UK)...

1. A haptic system comprisinga haptic actuator;
a voltage sensor coupled to the haptic actuator, to sense a voltage across the haptic actuator, wherein the voltage across the haptic actuator comprises a back electromotive force component; and
a current regulator coupled to the haptic actuator and to the voltage sensor; the current regulator being adapted to provide a current signal to drive the haptic actuator and to adjust the current signal based on the back electromotive force component;
wherein the current regulator comprises a current driver coupled to a current control loop.