US Pat. No. 9,491,819

HYSTERETIC POWER FACTOR CONTROL METHOD FOR SINGLE STAGE POWER CONVERTERS

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a transformer including a primary winding coupled to an input voltage and a secondary winding coupled to an output of the
switching power converter;

a switch coupled to the primary winding of the transformer, current passing through the primary winding while the switch is
turned on and not passing through while the switch is turned off;

a controller configured to generate a control signal to turn on and turn off the switch at each of a plurality of switching
cycles of the switch;

wherein for each alternating current (AC) half-cycle of the input voltage, the controller is further configured to:
determine a minimum value of a first signal representing an on-time of the switching power converter,
compare the determined minimum value with a threshold value of the first signal, the threshold value is used to determine
whether the switching power converter operates in a constant on-time mode or in a constant power mode, and

adjust the threshold value by increasing or decreasing the threshold value based on a result of the comparison; and
wherein the controller generates the control signal to operate the switching power converter in a constant power mode during
a first time period of the AC half-cycle, the first time period representing a duration where the threshold value is larger
than an instantaneous value of the first signal.

US Pat. No. 9,101,015

ADAPTIVE BIPOLAR JUNCTION TRANSISTOR GAIN DETECTION

Dialog Semiconductor Inc....

1. A power converter comprising:
a magnetic component coupled to an input voltage and to an output of the power converter, a shape of the input voltage having
a phase cutoff portion adjustable by a dimmer switch;

a bipolar junction transistor (BJT) coupled to the magnetic component;
a current control circuit configured to generate a control signal for controlling a base current of the BJT;
a gain detection circuit configured to, during a first mode, generate a first current setting signal for setting the base
current of the BJT to a first base current level and to determine a current gain of the BJT in a forward-active region based
on a feedback signal indicative of a level of current flowing through the BJT and the first base current level, the control
signal generated responsive to the first current setting signal in the first mode; and

a current calculation circuit configured to, during a second mode distinct in time from the first mode, generate a second
current setting signal for setting the base current of the BJT to a second base current level that operates the BJT in the
forward-active region during the phase cutoff portion of the shape of the input voltage, the current calculation circuit determining
the second base current level responsive to a target current level and the determined current gain of the BJT, the BJT drawing
current from the dimmer switch when operated in the forward-active region during the second mode, the control signal generated
responsive to the second current setting signal in the second mode,

the current control circuit generating the control signal to switch the BJT between a saturation region and a cutoff region
during a third mode distinct in time from the first mode and the second mode, the third mode substantially corresponding to
a portion of the input voltage that is not cutoff by the dimmer switch.

US Pat. No. 9,154,039

SWITCHING POWER CONVERTER WITH SECONDARY-SIDE DYNAMIC LOAD DETECTION AND PRIMARY-SIDE FEEDBACK AND CONTROL

Dialog Semiconductor Inc....

1. A switching power converter, comprising:
a transformer coupled between an input and an output of the switching power converter, the transformer including a primary
winding coupled to the input to receive an input voltage and a secondary winding coupled to the output of the switching power
converter;

a switch coupled to the primary winding of the transformer, current through the primary winding being generated while the
switch is turned on and not being generated while the switch is turned off;

a controller at a primary winding side of the transformer and configured to generate a control signal to turn on or turn off
the switch, the switch being turned on responsive to the control signal being in a first state and the switch being turned
off responsive to the control signal being in a second state;

a feedback circuit at the primary winding side of the transformer and configured to generate a feedback signal indicative
of an output voltage at the output of the switching power converter;

a load detection circuit at a secondary winding side of the transformer and separate from the feedback circuit, the load detection
circuit configured to detect a dynamic load condition occurring at a transition time from a disconnected state to a connected
state between a load and the output of the switching power converter, the load detection circuit further configured to generate
an alert signal indicative of the detected dynamic load condition; and

a coupling circuit coupled to the load detection circuit at the secondary winding side of the transformer and to the controller
at the primary winding side of the transformer, the coupling circuit configured to transmit the alert signal generated by
the load detection circuit to the controller,

wherein the controller is configured to regulate the output voltage based on the feedback signal generated at the primary
winding side of the transformer while detecting and responding to the dynamic load condition based on the alert signal generated
at the secondary winding side of the transformer.

US Pat. No. 9,420,645

CONSTANT CURRENT CONTROL BUCK CONVERTER WITHOUT CURRENT SENSE

Dialog Semiconductor Inc....

1. A method for controlling an output current of a power supply, an output of the power supply coupled to an inductor:
storing, in the inductor, power from the power supply when a switch is on and transferring power form the inductor to a load
when the switch is off;

sensing a voltage across the inductor;
sensing a voltage across a switching current sense resistor coupled in series to the switch and to the inductor;
determining a reset time of the inductor by determining a duration for the voltage across the inductor to decrease from a
first value to a second value;

determining a regulation voltage, wherein the regulation voltage is directly proportional to the switching period of the switch,
a nominal output current value and a resistance of the switching current sense resistor, and inversely proportional to the
sum of the reset time and the length of time the switch is in an on state;

generating a control signal responsive to a comparison between the voltage across the switching current sense resistor and
the regulation voltage, the control signal transitioning the switch to an off state responsive to the voltage across the switching
current sense resistor exceeding the regulation voltage.

US Pat. No. 9,155,152

INTENSITY CONTROL OF LEDS INTERFACING THREE-WAY SOCKETS

Dialog Semiconductor Inc....

1. A light-emitting diode (LED) lighting fixture configured to receive signals from a first input voltage line and a second
input voltage line, the LED lighting fixture comprising:
an LED bank including one or more LEDs; and
an LED controller configured to detect whether the first and second input voltage lines are active and to provide regulated
current to the LED bank, the LED controller configured to:

provide regulated output current at a first level to a first portion of the LED bank responsive to detecting the first input
voltage line is active and the second input voltage line is not active; and

provide a regulated output current at a second level to a second portion of the LED bank responsive to detecting the first
and second input voltage lines are active, the second portion of the LED bank at least partially overlapping the first portion.

US Pat. No. 9,288,864

ADAPTIVE HOLDING CURRENT CONTROL FOR LED DIMMER

Dialog Semiconductor Inc....

1. A light emitting diode (LED) controller comprising:
a current sensor coupled to a dimmer, the current sensor configured to detect a dimmer current;
a current controller coupled to an output of the current sensor, the current controller comprising a dimmer control unit configured
to:

determine a dimmer operating mode based on the detected dimmer current, wherein a first dimmer operating mode corresponds
to conditions at the beginning of operation after the dimmer is triggered and a second dimmer operating mode corresponds to
conditions that the detected dimmer current is maintained within a predetermined tolerance range of a threshold dimmer current,

compare the detected dimmer current to a threshold dimmer current value, and
generate a control signal during the first dimmer operating mode and during the second dimmer operating mode for regulating
the dimmer current based at least in part on a difference between the threshold current value and the detected dimmer current,
and the determined dimmer operating mode; and

a switch coupled to the current controller, the switch configured to receive the control signal generated by the dimmer control
unit and regulate an amount of additional dimmer current to be supplied to the dimmer through an additional current path based
on the control signal, the amount of additional current supplied to the dimmer based on the difference between the threshold
dimmer current value and the detected dimmer current.

US Pat. No. 9,184,667

SWITCHING POWER CONVERTER WITH PRIMARY-SIDE DYNAMIC LOAD DETECTION AND PRIMARY-SIDE FEEDBACK AND CONTROL

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a transformer including a first primary winding coupled to an input voltage, a second primary winding, a secondary winding
coupled to an output of the switching power converter, and an auxiliary winding on a primary side of the transformer, output
voltage across the secondary winding being reflected as feedback voltage across the auxiliary winding;

a first switch coupled to the first primary winding of the transformer, current in the primary winding being generated responsive
to the first switch being turned on and not generated responsive to the first switch being turned off, the feedback voltage
being generated across the auxiliary winding during off-cycles of the first switch;

a second switch coupled to the second primary winding of the transformer, current in the second primary winding being generated
responsive to the second switch being turned on and not being generated responsive to the second switch being turned off,
the feedback voltage being also generated across the auxiliary winding during off-cycles of the second switch; and

a controller coupled to the first switch and the second switch, the controller being configured to generate a first control
signal to turn on or turn off the first switch at a first switching frequency and, responsive to the first switching frequency
dropping below a threshold frequency, generate a second control signal to turn on or turn off the second switch at a second
switching frequency that is higher than the first frequency.

US Pat. No. 9,603,205

MULTI-FUNCTION TERMINAL CONFIGURABLE TO IMPLEMENT TWO FUNCTIONALITIES

Dialog Semiconductor Inc....

1. A power converter controller comprising:
a first terminal configured to provide supply voltage to the controller; and
a second terminal configured to couple to a switch external to the controller, the switch is part of a power converter controlled
by the controller, the controller sensing a current flowing through a primary winding of a transformer of the power converter,
wherein the second terminal is further configured to be used for an initial power up of the power converter when the switch
is turned on and to be used for a second functionality based on a voltage level of the second terminal being less than a sum
of a voltage level of the first terminal and a threshold voltage of the switch, the switch is a depletion-mode MOSFET.

US Pat. No. 9,337,714

POWER CONVERTER WITH FAST DISCHARGE CIRCUIT

Dialog Semiconductor Inc....

1. A power converter for providing power to a load, the power converter comprising:
a magnetic component coupled between an input of the power converter and an output of the power converter, the magnetic component
comprising a primary winding and a secondary winding;

a switch to control transfer of energy from the primary winding to the secondary winding according to on and off times of
the switch; and

a discharge circuit coupled to the output of the power converter, the discharge circuit adapted to receive a signal indicative
of whether the load is disconnected and to enable a discharge path coupled to the output to decrease an output voltage at
the output of the power converter in response to the signal indicative of whether the load is disconnected.

US Pat. No. 9,071,147

AVERAGE INPUT CURRENT ESTIMATION BASED ON PRIMARY SIDE CURRENT SENSE

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a magnetic component coupled to an input voltage and an output of the switching power converter;
a switch coupled to the magnetic component to control current through at least part of the magnetic component, current through
at least the part of the magnetic component generated while the switch is turned on and not being generated while the switch
is turned off;

a controller including a pin for sensing the current through at least the part of the magnetic component, the controller configured
to generate a control signal to turn on or turn off the switch during a plurality of switching cycles of the switch;

a resistive voltage divider including a first resistor and a second resistor, the current through at least the part of the
magnetic component flows through the first resistor but not through the second resistor; and

wherein the controller is configured to estimate an average input current of the switching power converter based on the following
equation:

where Iin—avg is the estimated average input current, DISENSE is a value representing a target peak current through at least the part of the magnetic component, RSNS is an impedance of the first resistor, Ton is an on-time of the switch during a switching cycle of the power converter, and Tp is a period of the switching cycle.

US Pat. No. 9,451,664

ADAPTIVE SWITCH MODE LED DRIVER

Dialog Semiconductor Inc....

1. A light-emitting diode (LED) driver for driving one or more LED strings, the LED driver comprising:
a first channel switch in series with a first LED string of the one or more LED strings, the first channel switch configured
to switch the first LED string on or off according to a first duty cycle signal applied to the first channel switch;

a first channel regulator coupled in series with the first LED string and the first channel switch, the first channel regulator
configured to receive a first signal at a first input terminal of the first channel regulator and to regulate current through
the first LED string, the first channel switch, and the first channel regulator according to the first signal, the current
flowing from a second input terminal of the first channel regulator to an output terminal of the first channel regulator;
and

a luminance controller configured to select a current level from a limited set of programmable current levels, to generate
the first signal based on the selected current level from the limited set of programmable current levels to control the first
channel regulator to regulate the current through the first LED string, the first channel switch and the first channel regulator,
and to generate the first duty cycle signal for driving the first channel switch as a function of the selected current level.

US Pat. No. 9,351,370

MODIFYING DUTY CYCLES OF PWM DRIVE SIGNALS TO COMPENSATE FOR LED DRIVER MISMATCHES IN A MULTI-CHANNEL LED SYSTEM

Dialog Semiconductor Inc....

1. An LED (Light Emitting Diode) controller comprising:
a first LED driver to generate a first PWM (Pulse Width Modulation) drive signal to turn on or turn off a first current through
a first LED string responsive to the first PWM drive signal; and

a first compensation circuit to generate the first PWM drive signal responsive to a first duty set signal, the first duty
set signal being a first predetermined target duty cycle set for the first PWM drive signal, the first compensation circuit
comprising:

a first error determination circuit to receive a first feedback signal indicative of the first current and to generate a first
error signal indicative of a difference between a first predetermined target value and the first feedback signal; and

a first PWM signal generation circuit to generate the first PWM drive signal to have the first duty cycle corresponding to
the first duty set signal adjusted by the first error signal.

US Pat. No. 9,112,498

DYNAMIC MOSFET GATE DRIVERS

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a transformer including a primary winding coupled to an input voltage and a secondary winding coupled to an output of the
switching power converter;

a field effect transistor switch coupled to the primary winding of the transformer, current through the primary winding being
generated while the field effect transistor switch is turned on and not being generated while the field effect transistor
switch is turned off; and

a driver control circuit configured to generate a control signal to turn on or turn off the field effect transistor switch
during a plurality of switching cycles of the field effect transistor switch, each of the switching cycles including a first
part during which the field effect transistor switch is turned on and a second part during which the field effect transistor
switch is turned off, and the driver control circuit adjusting a magnitude of current of the control signal from a first level
during a first duration of the first part of at least one of the switching cycles of the field effect transistor switch to
a second level that is greater than the first level during a second duration of the first part of said one of the switching
cycles, said second duration being later in time than said first duration.

US Pat. No. 9,224,340

PREDICTIVE POWER CONTROL IN A FLAT PANEL DISPLAY

Dialog Semiconductor Inc....

1. A method for controlling a power regulator comprising:
receiving, during a first cycle corresponding to a display duration of a current image, future image property information
related to a future image to be displayed on a display during a second cycle after display of the current image, said second
cycle occurring after said first cycle;

generating a power regulator control signal, prior to said second cycle and prior to display of the future image, based upon
the future image property information; and

precharging a power regulator output voltage based on the power regulator control signal, prior to said second cycle by a
duration of time that depends on the future image property information, and prior to the power regulator output voltage dropping
below a threshold value, said power regulator output voltage coupled to a switch that assists in displaying said future image
on said display during said second cycle.

US Pat. No. 9,629,207

SOLID STATE LAMP CONTROL

Dialog Semiconductor Inc....

1. A lamp for connection to an AC mains supply via a trailing edge phase cut dimmer switch and comprising:
an input stage comprising a capacitor;
an output stage including a solid state light source;
a power stage including a power switch for selectively coupling the power stage with the output stage;
a bleeder circuit including a load and a bleeder switch for selectively coupling a load with the input stage; and
a controller arranged to:
enable on and off switching cycles of the power switch throughout the course of a period that starts at a point of an AC mains
supply cycle corresponding to a first energy level of the capacitor, as determined by a regulation threshold and ends at a
point when the phase cut dimmer switch disconnects the AC mains from the lamp corresponding to a second energy level of the
capacitor that is lower than the first energy level, wherein the regulation threshold is determined by feedback from one or
more previous AC half cycles.

US Pat. No. 9,161,402

HIGH PERFORMANCE ADAPTIVE SWITCHED LED DRIVER

Dialog Semiconductor Inc....

1. A light-emitting diode (LED) driver for driving an LED string, the LED driver comprising:
an LED controller configured to generate a PWM signal;
a first transistor to turn on or off responsive to the PWM signal, the first transistor in series with the LED string, wherein
an LED current passes through the first transistor and the LED string when the first transistor is turned on;

a second transistor in series with the LED string and the first transistor, wherein a first portion of the LED current passes
through the second transistor when the first transistor is turned on;

a programmable trimming circuit in parallel with the second transistor, the programmable trimming circuit configured to pass
a trimming circuit current controlled by one or more trimming control signals, wherein the trimming circuit current comprises
a second portion of the LED current.

US Pat. No. 9,084,325

ADAPTIVE DIMMER DETECTION AND CONTROL FOR LED LAMP

Dialog Semiconductor Inc....

1. A light-emitting diode (LED) lamp controller for a switching power converter comprising a switch coupled to a winding that
supplies power to one or more LEDs, the LED lamp controller comprising:
a dimmer control circuit to detect a dimming amount of an input voltage from a dimmer switch, and to generate a dimming control
signal representative of the detected dimming amount;

a switch controller to receive the dimming control signal, a current sense signal representing a current through the winding
coupled to the switch, and a voltage sense signal representing a reset time of the switching power converter, and to control
switching of the switch based on the dimming control signal, the current sense signal, and the reset time to regulate a current
through the one or more LEDs such that the one or more LEDs achieve a dimming level corresponding to the detected dimming
amount.

US Pat. No. 9,307,593

DYNAMIC BLEEDER CURRENT CONTROL FOR LED DIMMERS

Dialog Semiconductor Inc....

1. A light-emitting diode (LED) lamp, comprising:
an LED string including one or more LEDs;
a rectifier circuit configured to receive an AC input voltage and to generate a rectified voltage corresponding to the AC
input voltage, the rectified voltage is a phase-cut AC input voltage indicating a dimming level;

a bleeder circuit coupled to the rectifier circuit and configured to turn on to provide a bleeder current at a first current
level responsive to the AC input voltage less than a first threshold voltage and to reduce the bleeder current to a second
current level responsive to the AC input voltage exceeding a second threshold voltage; and

an LED driver circuit configured to switch on or off a power stage switch according to a duty cycle based on the rectified
voltage, to regulate a driving current through the LED string.

US Pat. No. 9,444,364

ADAPTIVE PEAK POWER CONTROL

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a transformer including a primary winding coupled to an input voltage and a secondary winding coupled to an output of the
switching power converter;

a switch coupled to the primary winding of the transformer, current through the primary winding being generated while the
switch is turned on and not being generated while the switch is turned off; and

a controller configured to generate a control signal to turn on or turn off the switch, the switch being turned on responsive
to the control signal being in a first state and the switch being turned off responsive to the control signal being in a second
state, wherein:

responsive to an occurrence of a local minimum of a voltage across the switch and a current level at the output of the switching
power converter being greater than a first current level but less than a second current level, the second current level being
greater than the first current level, the controller is further configured to generate the control signal based on a first
operation mode;

responsive to satisfying a voltage-time product condition and a current at the output of the switching power converter being
greater than the second current level but less than a third current level, the third current level being greater than the
second current level, the controller is further configured to generate the control signal based on a second operation mode;
and

wherein at a transition point between the first operation mode and the second operation mode, the controller is further configured
to use a voltage-time product of the transformer prior to transitioning to the second operation mode as a reference point
to determine a turn-on time of the switch during the second operation mode.

US Pat. No. 9,391,525

POWER SYSTEM SWITCH PROTECTION USING OUTPUT DRIVER REGULATION

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a transformer coupled between an input voltage and an output of the switching power converter, the transformer including a
primary winding coupled to the input voltage and a secondary winding coupled to the output of the switching power converter;

a switch coupled to the primary winding of the transformer, current through the primary winding being generated while the
switch is turned on and not being generated while the switch is turned off; and

a controller configured to generate a control signal to turn on or turn off the switch, the switch being turned on responsive
to the control signal being in a first state and the switch being turned off responsive to the control signal being in a second
state,

wherein the controller includes a voltage protection circuit configured to receive a supply voltage and to generate a modified
supply voltage, based on the received supply voltage, to power one or more components of the controller, wherein the supply
voltage is the input voltage of the switching power converter, and wherein:

the modified supply voltage is equal to the supply voltage, responsive to the supply voltage being lower than a predetermined
threshold voltage; and

the modified supply voltage is substantially equal to a predetermined supply voltage, responsive to the supply voltage being
greater than the predetermined threshold voltage.

US Pat. No. 9,318,963

SWITCHING POWER CONVERTER WITH SECONDARY TO PRIMARY MESSAGING

Dialog Semiconductor Inc....

1. A switching power converter, comprising:
a transformer isolating a primary side of the switching power converter from a secondary side of the switching power converter,
the transformer including a primary winding coupled to an input and a secondary winding coupled to an output of the switching
power converter;

a first primary side switch coupled to the primary winding of the transformer, the first primary side switch to control current
flow through the primary winding based on switching of the first primary side switch;

a primary side controller to control switching of the first primary side switch to regulate the output of the switching power
converter based on primary-side sensing, and to select between a normal mode and a messaging mode, the primary side controller
to detect digital messages generated on the secondary side during the messaging mode based on primary side sensing of current
through the primary winding.

US Pat. No. 9,232,581

OUTPUT CURRENT COMPENSATION FOR JITTER IN INPUT VOLTAGE FOR DIMMABLE LED LAMPS

Dialog Semiconductor Inc....

1. An LED controller for reducing jitter of an LED lamp, the LED controller comprising:
a jitter detection circuit adapted to determine an amount of jitter in an input voltage signal, the input voltage signal including
a plurality of cycles and indicative of an amount of dimming for the LED lamp by durations of on-phases of the input voltage
signal during each cycle, wherein the amount of jitter corresponds to a difference between durations of on-phases of the input
voltage signal between at least two cycles or half-cycles of the input voltage signal; and

a jitter compensation circuit adapted to generate a control signal to control regulated current in the LED lamp such that
an output light intensity of the LED lamp substantially corresponds to the amount of dimming for the LED lamp, the control
signal enabling current delivery to the LED lamp during an entire duration of a shorter one of the at least two cycles or
half-cycles, disabling current delivery to the LED lamp during a portion of a longer one of the at least two cycles or half-cycles
that corresponds to the difference in duration of the on-phases of the input voltage signal to compensate for the determined
amount of jitter in the input voltage signal, and enabling current delivery to the LED lamp for a remaining portion of the
longer one of the at least two cycles or half-cycles, wherein the remaining portion of the longer one of the at least two
cycles or half-cycles is equivalent in duration to the entire duration of the shorter one of the at least two cycles or half-cycles.

US Pat. No. 9,369,054

REDUCING POWER CONSUMPTION OF A SYNCHRONOUS RECTIFIER CONTROLLER

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a magnetic component coupled to an input voltage and an output of the switching power converter;
a switch coupled to the magnetic component, energy stored in the magnetic component when the switch is in an on state;
a first controller configured to generate a first control signal to turn on or turn off the switch during each switching cycle
of the switch to maintain regulation of the output of the switching power converter;

a synchronous rectifier switch configured to rectify an output voltage at the output of the switching power converter, the
synchronous rectifier switch having at least a first terminal and a second terminal, the first terminal coupled to the magnetic
component;

a plurality of circuit components configured to output trigger signals that control operation of the synchronous rectifier
switch based on a voltage at a terminal of the synchronous rectifier switch, the plurality of circuit components including
a first comparator configured to output a first trigger signal that disables one or more of the plurality of circuit components
based on a comparison of the voltage at the terminal of the synchronous rectifier switch and a first reference signal; and

a second controller configured to receive the trigger signals and is configured to generate a second control signal to turn
on or turn off the synchronous rectifier switch during a plurality of switching cycles of the synchronous rectifier switch
based on the trigger signals;

wherein the second controller is further configured to receive the first trigger signal from the first comparator and disable
one or more of the plurality of circuit components during a switching cycle of the synchronous rectifier switch after the
synchronous rectifier switch is turned off during the switching cycle based on the first trigger signal received from the
first comparator.

US Pat. No. 9,419,527

REGULATION FOR POWER SUPPLY MODE TRANSITION TO LOW-LOAD OPERATION

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a transformer including a primary winding coupled to an input voltage and a secondary winding coupled to an output of the
switching power converter;

a switch coupled to the primary winding of the transformer, current through the primary winding being generated while the
switch is turned on and not being generated while the switch is turned off; and

a controller configured to generate a control signal to turn on or turn off the switch, the switch being turned on responsive
to the control signal being in a first state and the switch being turned off responsive to the control signal being in a second
state, wherein:

responsive to a load level at the output of the switching power converter being less than a first load level but greater than
a second load level, the second load level being less than the first load level, the controller is further configured to generate
the control signal based on a first operation mode, during the first operation mode the switching power converter regulating
a duty cycle of the control signal applied to the switch by performing one of:

varying a conduction pulse width of the control signal and keeping a switching period of the control signal constant, or
varying the conduction pulse width of the control signal and varying the switching period of the control signal;
responsive to the load at the output of the switching power converter being less than the second load level but greater than
a third load level, the third load level being less than the second load level, the controller is further configured to generate
the control signal based on a second operation mode, during the second operation mode the switching power converter regulating
the duty cycle of the control signal applied to the switch by keeping the conduction pulse width constant and varying the
switching period; and

wherein at a transition point between the first operation mode and the second operation mode, the controller is further configured
to use a point during the first operation mode when the switch would have been turned on prior to transitioning to the second
operation mode as a reference point to determine when to turn on the switch during the second operation mode.

US Pat. No. 9,331,589

PRIMARY FEEDBACK SWITCHING POWER CONVERTER CONTROLLER WITH INTELLIGENT DETERMINATION OF AND RESPONSE TO OUTPUT VOLTAGE DROPS DUE TO DYNAMIC LOAD CONDITIONS

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a transformer coupled between an input and an output of the switching power converter, the transformer including a primary
winding coupled to the input to receive an input voltage and a secondary winding coupled to the output of the switching power
converter;

a switch coupled to the primary winding of the transformer, current through the primary winding being generated while the
switch is turned on and not being generated while the switch is turned off;

a controller at a primary winding side of the transformer and configured to generate a control signal to turn on or turn off
the switch, the switch being turned on responsive to the control signal being in a first state and the switch being turned
off responsive to the control signal being in a second state;

a feedback circuit at the primary winding side of the transformer and configured to generate a feedback signal indicative
of an output voltage at the output of the switching power converter;

a load detection circuit at a secondary winding side of the transformer and separate from the feedback circuit, the load detection
circuit configured to generate a detection signal responsive to the output voltage reaching a voltage condition; and

wherein the controller is configured to:
receive the detection signal indicative that the output voltage reached the voltage condition;
responsive to determining that the output voltage reached the voltage condition due to a condition other than a dynamic load
condition occurring when a load is connected to the output of the switching power converter, disregarding the detection signal;
and

responsive to determining that the output voltage did not reach the voltage condition due to the condition other than the
dynamic load condition, determining that the output voltage reached the voltage condition due to the dynamic load condition.

US Pat. No. 9,124,185

CONFIGURABLE POWER CONTROLLER WITH COMBINATION INPUT/OUTPUT LINE

Dialog Semiconductor Inc....

1. A power supply comprising:
a transformer configured to provide power to an output load, the transformer coupled to a power source;
a switch, coupled to the transformer, configured to allow current to flow from the power source through the transformer when
closed and to prevent current from flowing from the power source through the transformer when open;

a sense circuit configured to provide a sense signal representative of the power provided to the output load, the sense circuit
comprising at least one resistor; and

a controller comprising a first comparator configured to compare a detected voltage across the at least one resistor to a
first reference voltage and to output a configuration signal based on the comparison when the controller is in a configuration
state, a second comparator configured to compare the sense signal to a second reference voltage and to output a comparison
signal based on the comparison, a current source, and a second switch, the second switch configured to be closed when the
controller is in the configuration state such that current flows from the current source and through a combination input/output
line, and the second switch configured to be open when the controller is in the operating state such that the current source
is isolated from the combination input/output line, the controller configured to:

responsive to being in the configuration state, output a current through the combination input/output line to the sense circuit
and detect the voltage across the at least one resistor; and

responsive to being in the operating state, receive the sense signal via the combination input/output line and control the
opening and closing of the switch based on the sense signal, the comparison signal, and a selected one of a plurality of operating
modes, the selected one of the plurality of operating modes selected based on the configuration signal.

US Pat. No. 9,584,008

SWITCHING POWER CONVERTER WITH ADAPTIVE POWER FACTOR CORRECTION

DIALOG SEMICONDUCTOR INC....

1. A flyback converter controller, comprising:
a multiplier configured to multiply an error signal with a reference signal to produce a peak current command signal;
a comparator configured to compare the peak current command signal corresponding to a desired peak value for a primary winding
current to an Isense signal that represents a primary winding current amplitude, the comparator configured to generate a power
switch off command responsive to an amplitude for the primary winding current equaling the desired peak value, and

a clamp circuit configured to clamp a signal selected from the reference signal and the Isense signal such that a peak value
for the primary winding current amplitude is maintained constant for a constant peak current period of each cycle of an input
voltage and such that a power switch on time is maintained constant in a remaining constant on time period of each cycle of
the input voltage.

US Pat. No. 9,413,241

SELF-POWERED BJT DRIVER FOR POWER SUPPLIES

Dialog Semiconductor Inc....

1. An apparatus comprising:
a high voltage semiconductor switch, the high voltage semiconductor switch including a first terminal, a second terminal,
and an third terminal; and

a driver comprising:
a first switch coupled to the third terminal of the high voltage semiconductor switch and to ground, the first switch turning
on and off based on a first control signal;

a second switch coupled to the first terminal of the high voltage semiconductor switch, the second switch turning on and off
based on the first control signal;

a third switch coupled to the first terminal of the high voltage semiconductor switch and to ground, the third switch turning
on and off based on the a second control signal; and

a diode, the diode including an anode terminal and a cathode terminal, the anode terminal of the diode coupled to the third
terminal of the high voltage semiconductor switch, and the cathode terminal of the diode coupled to the second switch.

US Pat. No. 9,301,360

INTEGRATED LED DIMMER CONTROLLER

Dialog Semiconductor Inc....

1. An integrated circuit for controlling a light emitting diode (LED), comprising:
a dimmer drive circuit configured to receive a driver control signal and to output a driving signal to a passive dimmer having
an adjustable control position, wherein the passive dimmer generates a dimmer signal from the driving signal, the dimmer signal
representing a control position of the adjustable control position of the passive dimmer;

a dimmer read circuit configured to receive a reader control signals and the dimmer signal from the passive dimmer and further
configured to generate a brightness signal representing a desired brightness level of the LED based on the dimmer signal;

a power controller coupled to the dimmer read circuit and configured to receive the brightness signal from the dimmer read
circuit, and generate one or more power control signals, the power control signals capable of causing the LED to emit light
at the desired brightness level; and

a unified timing controller coupled to the dimmer drive circuit and the dimmer read circuit, the unified timing controller
configured to receive one or more input signals generated by an LED power circuit coupled to the integrated circuit and a
signal indicative of a change in the control position of the passive dimmer, and further configured to generate, based on
the input signals, the driver control signal to control operation of the dimmer drive circuit and the reader control signals
to control operation of the dimmer read circuit.

US Pat. No. 9,413,249

SECONDARY-SIDE DYNAMIC LOAD DETECTION AND COMMUNICATION DEVICE

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a transformer including a primary winding coupled to an input voltage and a secondary winding coupled to an output of the
switching power converter;

a power switch coupled to the primary winding of the transformer, current in the primary winding being generated responsive
to the power switch being turned on and not generated responsive to the power switch being turned off;

a rectifier coupled to the secondary winding of the transformer, the rectifier conducting a rectified current to the output
of the switching power converter during off cycles of the power switch;

a detection circuit measuring voltage across the rectifier, the detection circuit detecting a decrease in the voltage across
the rectifier outside of a blanking period and generating one or more current pulses in the secondary winding of the transformer
in response to detecting the voltage decrease; and

a fast power-on-reset (POR) device coupled to the detection circuit, the fast POR device generating a startup signal to activate
the detection circuit at an end of the blanking period.

US Pat. No. 9,326,343

INTEGRATED LED DIMMER CONTROLLER

Dialog Semiconductor Inc....

1. An integrated circuit for controlling a light emitting diode (LED), comprising:
a dimmer drive circuit configured to receive a driver control signal and to output a driving signal to a passive dimmer having
an adjustable control position, wherein the passive dimmer generates a dimmer signal from the driving signal, the dimmer signal
representing a control position of the adjustable control position of the passive dimmer;

a dimmer read circuit configured to receive a reader control signals and the dimmer signal from the passive dimmer and further
configured to generate a brightness signal representing a desired brightness level of the LED based on the dimmer signal;

a power controller coupled to the dimmer read circuit and configured to receive the brightness signal from the dimmer read
circuit, and generate one or more power control signals, the power control signals capable of causing the LED to emit light
at the desired brightness level; and

a unified timing controller coupled to the dimmer drive circuit and the dimmer read circuit, the unified timing controller
configured to receive one or more input signals generated by an LED power circuit coupled to the integrated circuit and a
signal indicative of a change in the control position of the passive dimmer, and further configured to generate, based on
the input signals, the driver control signal to control operation of the dimmer drive circuit and the reader control signals
to control operation of the dimmer read circuit.

US Pat. No. 9,380,668

PDM MODULATION OF LED CURRENT

Dialog Semiconductor (UK)...

1. An LED light dimming circuit, comprising:
a) a string of at least one LED device;
b) a control circuit providing primary side regulation configured to produce drive current and modulation; and
c) said control circuit configured to hold drive current constant at a predetermined level and varying a duty cycle of a pulse
density modulator (PDM) to change LED device illumination, wherein said control circuit is configured to produce a hysteresis
in the drive current between a fixed PDM duty cycle portion and a variable PDM duty cycle portion of the LED current to enable
a smooth transition in emitted LED light.

US Pat. No. 9,060,408

THERMAL DE-RATING POWER SUPPLY FOR LED LOADS

Dialog Semiconductor Inc....

1. A power supply comprising:
an analog-to-digital converter (“ADC”) configured to:
receive a temperature signal representing a temperature of a light-emitting diode (“LED”); and
generate a digital temperature signal based on the received temperature signal;
an over-temperature protection (“OTP”) circuit configured to:
receive the digital temperature signal;
detect an LED over-temperature condition based on the received digital temperature signal; and
select a target output current for the LED based on the detected LED over-temperature condition; and
a driver circuit configured to:
provide an output current to the LED;
receive an output current rate of change selected based on the provided output current and the target output current; and
adjust the provided output current based on the received output current rate of change until the outputted current is substantially
equal to the target output current.

US Pat. No. 9,379,625

CURRENT METER FOR LOAD MODULATION COMMUNICATION RECEIVER ARCHITECTURE

Dialog Semiconductor Inc....

1. A switching power converter to provide power to an electronic device based on a digital message generated by the electronic
device, the electronic device generating the digital message by modulating a load current to the electronic device according
to a predefined pattern, the switching power converter comprising:
a transformer electrically isolating a secondary side of the switching power converter coupled to the electronic device from
a primary side;

a load current detector to obtain samples of a primary side voltage sense signal representative of a primary side voltage
and samples of a current sense signal representing a primary side current, the voltage sense signal and the current sense
signal varying based on the modulated load current to the electronic device, the load current detector to generate a load
current signal, representing a waveform of the modulated current to the electronic device based on the samples of the voltage
sense signal and the samples of the current sense signal;

a digital decoder to decode the load current signal to recover the digital message encoding by the electronic device; and
a power controller to control switching of a switch to control at least one of an output voltage and an output current to
the electronic device based on the voltage sense signal, the current sense signal, and the digital message.

US Pat. No. 9,380,670

GENERATING A VOLTAGE FEEDBACK SIGNAL IN NON-ISOLATED LED DRIVERS

Dialog Semiconductor Inc....

1. A light-emitting diode (LED) lamp, comprising:
one or more LEDs;
an inductor coupled to an input voltage source and the one or more LEDs;
a switch coupled to the inductor, current in the inductor being generated responsive to the switch being turned on and not
generated responsive to the switch being turned off;

a first current detector coupled between the input voltage source and a ground node of the LED lamp, the first current detector
detecting a current that is proportional to a bulk voltage across the input voltage source;

a second current detector coupled between the inductor and the ground node, the second current detector detecting a current
that is proportional to a drain voltage across the switch;

a current-to-voltage converter configured to:
convert a difference between the current detected by the first current detector and the current detected by the second current
detector to a voltage signal based on a resistance of the first current detector and a resistance of the second current detector,
and

generate a feedback signal proportional to a regulated output voltage from the LED lamp based on the voltage signal; and
a switch controller receiving the feedback signal and controlling switching of the switch based on the feedback signal to
regulate an output current through the one or more LEDs.

US Pat. No. 9,525,352

MAGNITUDE ADJUSTMENT OF THE DRIVE SIGNAL OF A SWITCHING TRANSISTOR OF A SWITCHING POWER CONVERTER

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a magnetic component coupled between a power source and a load;
a switch coupled to the magnetic component for coupling or decoupling the load to or from the power source through the magnetic
component; and

a switch controller coupled to the switch, the switch controller generating an output drive signal that alternates between
a first logic state and a second logic state, the first logic state defining an on-time of the switch and the second logic
state defining an off-time of the switch;

wherein the switch controller further generates a switch drive signal that is transmitted to the switch for turning on the
switch while the output drive signal is at the first logic state and for turning off the switch while the output drive signal
is at the second logic state, the switch controller adjusting a current magnitude or a voltage magnitude of the switch drive
signal while the output drive signal is at the first logic state, the current magnitude or the voltage magnitude of the switch
drive signal adjusted to be zero for a predetermined period of time at an end of the on-time of the switch while the output
drive signal is at the first logic state.

US Pat. No. 9,635,719

HIGH VOLTAGE CONVERTER WITHOUT AUXILIARY WINDING

Dialog Semiconductor (UK)...

1. A driver circuit which is configured to generate a drive voltage to a load subject to an input voltage, wherein the driver
circuit comprises
a power converter network comprising an inductor which is coupled to the input voltage;
a power transistor having a high voltage terminal which is coupled to the inductor and having a low voltage terminal;
a controller; and
a supply voltage capacitor for providing a logic supply voltage to the controller; wherein
the controller comprises a control transistor which is configured to couple the low voltage terminal of the power transistor
to a low voltage potential or to decouple the low voltage terminal from the low voltage potential, in order to put the power
transistor to a conduction-state or an off-state, respectively;

the controller comprises a charging transistor forming a serial arrangement with the supply voltage capacitor; wherein the
serial arrangement is arranged in parallel to the control transistor, and wherein the charging transistor is configured to
couple or to decouple the low voltage terminal of the power transistor to or from the supply voltage capacitor, in order to
put the power transistor to the conduction-state or off-state, respectively; and

the controller is configured to
put the power transistor to the conduction-state using the charging transistor within a first time interval and to
put the power transistor to the conduction-state using the control transistor within a second time interval.

US Pat. No. 9,559,597

DETECTING OPEN CONNECTION OF AUXILIARY WINDING IN A SWITCHING MODE POWER SUPPLY

Dialog Semiconductor Inc....

1. A power converter comprising:
a transformer including a primary winding coupled to an input voltage, a secondary winding coupled to an output of the power
converter, and an auxiliary winding, output voltage of the power converter being reflected as feedback across the auxiliary
winding;

a current source coupled to the auxiliary winding, the current source when activated supplying a current to the auxiliary
winding; and

a controller regulating the output voltage of the power converter based on the feedback across the auxiliary winding, the
controller adapted to measure a voltage across the auxiliary winding while the current source is activated and disable the
power converter responsive to detecting the voltage across the auxiliary winding is greater than a threshold voltage while
the current source is activated.

US Pat. No. 9,584,031

POWER SUPPLY WITH CONFIGURABLE CONTROLLER WITH COMBINATION INPUT/OUTPUT LINE

Dialog Semiconductor Inc....

1. A power supply comprising:
a transformer configured to provide power to an output load, the transformer coupled to a power source;
a switch, coupled to the transformer, configured to allow current to flow from the power source through the transformer when
closed and to prevent current from flowing from the power source through the transformer when open;

a sense circuit configured to provide a sense signal representative of the power provided to the output load, the sense circuit
comprising at least one resistor; and

a controller comprising a current source and a second switch, the second switch configured to allow current to flow from the
current source and out a combination input/output line when the controller is in a configuration state and to isolate the
current source from the combination input/output line when the controller is in an operating state, the controller configured
to:

responsive to being in the configuration state, output a current through the combination input/output line to the sense circuit
and detect a corresponding voltage across the at least one resistor; and

responsive to being in the operating state, receive the sense signal via the combination input/output line and control the
opening and closing of the switch based on the sense signal and one of a plurality of operating modes selected based on the
detected corresponding voltage.

US Pat. No. 9,543,819

ADAPTIVE BJT DRIVER FOR SWITCHING POWER CONVERTER

DIALOG SEMICONDUCTOR INC....

1. A switching power converter, comprising:
a bipolar junction transistor (BJT) power switch coupled to an inductor;
a base current driver configured to drive a base current into a base of the BJT power switch; and
a controller configured to control the base driver so that the BJT power switch cycles on and off according to the driving
of the base current, wherein the base current for each current cycle in at least some of the BJT power switch cycles starts
from a beginning value and is increased to a maximum value at a rate of change for the base current that is proportional to
a rate of change for a collector current for the BJT power switch in a previous cycle to the current cycle.

US Pat. No. 9,531,275

PRECISE OUTPUT POWER DETECTION

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a transformer including a primary winding coupled to an input voltage, a secondary winding coupled to an output of the switching
power converter, and an auxiliary winding on a primary side of the transformer, output voltage across the secondary winding
being reflected as feedback voltage across the auxiliary winding;

a switch coupled to the primary winding of the transformer, current in the primary winding being generated responsive to the
switch being turned on and not generated responsive to the switch being turned off, the feedback voltage being generated across
the auxiliary winding during off-cycles of the switch;

an output power detector configured to detect output current of the switching power converter based on a reset time of the
transformer and generate a control signal indicating output power of the switching power converter based on the detected output
current and the feedback voltage; and

a controller coupled to the switch, the controller configured to control switching of the switch based on the control signal
indicating the output power of the switching power converter to regulate the output power of the switching power converter
and deliver the output power above a power limit to a load.

US Pat. No. 9,564,085

SELECTIVE DIMMING TO REDUCE POWER OF A LIGHT EMITTING DISPLAY DEVICE

Dialog Semiconductor Inc....

1. A display device with selective dimming, comprising:
a display panel including a plurality of light emitting pixels that emit light;
an image processor to divide an image frame into a plurality of regions and to generate an adjusted image frame by determining
a maximum intensity difference between a lowest pixel intensity level and a highest pixel intensity level in a region of the
plurality of regions and reducing pixel intensity levels in the region responsive to the maximum intensity difference in the
region being less than a threshold difference in intensity; and

a display driver to convert data for the adjusted image frame into control signals for controlling brightness of the light
emitting pixels.

US Pat. No. 9,877,367

POWERING INTERNAL COMPONENTS OF LED LAMPS USING DISSIPATIVE SOURCES

Dialog Semiconductor Inc....

1. A light-emitting diode (LED) lamp, comprising:
one or more LEDs;
an LED driver receiving an input signal from a dimmer switch indicative of an amount of dimming for the LED lamp, the LED
driver controlling a regulated current through the one or more LEDs based on the input signal such that an output light intensity
of the one or more LEDs substantially corresponds to the amount of dimming for the LED lamp;

a regulated voltage providing operating power for a plurality of controllers of the LED lamp controlling a plurality of switches
of the LED lamp; and

a controller of the plurality of controllers regulating the regulated voltage, the controller selecting a power source for
charging the regulated voltage from two or more power sources comprising an input current of the LED lamp supplying the one
or more LEDs with the regulated current and a bleeder circuit that when activated generates a bleeder current in the dimmer
switch.

US Pat. No. 9,625,505

LINE FREQUENCY DETECTOR

Dialog Semiconductor Inc....

1. A line frequency detector for receiving an input signal representing a power source and detecting a line frequency of the
power source based on the input signal, the line frequency detector comprising:
a first band pass filter adapted to filter the input signal to generate a first characteristic signal, the first band pass
filter having a pass band centered approximately at an upper end of an expected frequency range of the input signal;

a second band pass filter adapted to filter the input signal to generate a second characteristic signal, the second band pass
filter having a pass band centered approximately at a lower end of an expected frequency range of the input signal;

a characteristic ratio calculator adapted to determine a characteristic ratio representing a division of the first characteristic
signal by the second characteristic signal; and

a mapping module adapted to map the characteristic ratio to the line frequency of the power source.

US Pat. No. 9,647,560

SECONDARY-SIDE DYNAMIC LOAD DETECTION AND COMMUNICATION DEVICE

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a transformer including a primary winding coupled to an input voltage and a secondary winding coupled to an output of the
switching power converter;

a power switch coupled to the primary winding of the transformer, current in the primary winding being generated responsive
to the power switch being turned on and not generated responsive to the power switch being turned off;

a rectifier coupled to the secondary winding of the transformer, the rectifier conducting a rectified current to the output
of the switching power converter during off cycles of the power switch; and

a detection circuit continuously measuring a voltage across the rectifier outside of a blanking period of the detection circuit,
the detection circuit detecting a decrease in the voltage across the rectifier outside of the blanking period and generating
one or more current pulses in the secondary winding of the transformer in response to detecting the voltage decrease, wherein
the blanking period ends when the voltage across the rectifier reaches a threshold or the blanking period is extended by a
predefined amount of time after the voltage across the rectifier reaches the threshold.

US Pat. No. 9,537,404

AC-DC POWER SUPPLY INPUT VOLTAGE DETECTION AND MONITORING

Dialog Semiconductor Inc....

1. A switching power converter, comprising:
a transformer coupled between an input and an output of the switching power converter, the transformer including a primary
winding coupled to the input to receive an input voltage and a secondary winding coupled to the output of the switching power
converter;

a switch coupled to the primary winding of the transformer, a current through the primary winding being generated while the
switch is turned on and not being generated while the switch is turned off; and

a controller at a primary winding side of the transformer and configured to:
generate a control signal to turn on or turn off the switch, the switch being turned on responsive to the control signal being
in a first state and the switch being turned off responsive to the control signal being in a second state,

indirectly detect the input voltage to the switching power converter based on the current through the primary winding generated
while the switch is turned on, and

detect a brown out condition resulting from a temporary decrease in the input voltage responsive to the indirectly detected
input voltage being below a minimum allowed value of the input voltage, the controller to detect the brown out condition by:

determining a threshold time it takes for the current through the primary winding to reach a current threshold during a switching
cycle of the switching power converter, and

determining timings at which the threshold time at the switching cycle reaches a reference time, the reference time being
set below a maximum possible value corresponding to the minimum allowed value of the input voltage.

US Pat. No. 9,837,912

SINGLE STAGE SWITCHING POWER CONVERTER WITH IMPROVED PRIMARY ONLY FEEDBACK

DIALOG SEMICONDUCTOR INC....

1. A method of controlling a switching power converter, comprising:
comparing an on-time current produced from each cycle of a power switch to a current threshold to determine whether a sense
voltage pulse produced on an auxiliary winding from each cycle of the power switch is trustable or non-trustable, and wherein
consecutive cycles of a rectified input voltage are separated by a dead period in which the sense voltage pulses are non-trustable;

during each trustable sense voltage pulse, adjusting a reference voltage responsive to the trustable sense voltage pulse;
during each rectified input voltage cycle, determining a first trustable value of the voltage reference resulting from an
initial one of the trustable sense voltage pulses in the rectified input voltage cycle and determining a last trustable value
of the voltage reference resulting from a final one of the trustable sense voltage pulses in the rectified input voltage cycle;

for each dead period, extrapolating from the first trustable value of the reference voltage and the last trustable value to
produce an extrapolated reference voltage; and

controlling the cycling of the power switch during each dead period responsive to the extrapolated reference voltage.

US Pat. No. 9,774,261

PROTOCOL FOR COMMUNICATION BETWEEN SECONDARY SIDE AND PRIMARY SIDE OF ISOLATED SWITCHING POWER CONVERTERS

Dialog Semiconductor Inc....

1. A power converter system, comprising:
a switching power converter having a primary side and a secondary side that are electrically isolated from each other;
a first controller on the primary side of the switching power converter, the first controller controlling a switch coupled
to a primary winding on the primary side in the switching power converter on or off at a switching frequency of the switching
power converter to regulate an output voltage of the switching power converter;

a second controller on the secondary side of the switching power converter, the second controller encoding information into
one or more pulses such that a first duration between consecutive ones of the pulses corresponds to a first logic level and
a second duration between consecutive ones of the pulses corresponds to a second logic level, the second duration being greater
than the first duration; and

a communication channel for transmitting the encoded information from the second controller to the first controller while
maintaining electrical isolation between the primary side and the secondary side,

the first controller further generating a control signal to turn on or off the switch to regulate the output voltage, based
on the encoded information and a feedback voltage across an auxiliary winding coupled to the primary winding.

US Pat. No. 9,844,113

ADJUSTING COLOR TEMPERATURE IN A DIMMABLE LED LIGHTING SYSTEM

DIALOG SEMICONDUCTOR INC....

1. A light emitting diode (LED) lighting system, comprising:
a phase-angle dimmer switch;
a rectifier configured to rectify an AC voltage into a rectified input voltage having a shape and/or magnitude responsive
to a dimming level set by the phase-angle dimmer switch;

a dimming detection module configured to receive the rectified input voltage, to detect a desired brightness level from the
magnitude and/or shape of the rectified input voltage, and to thereby generate a target current level signal that varies responsive
to a variation of the desired brightness level;

a single switching power regulator configured to generate a regulated current at an output of the single switching power regulator
responsive to the target current level signal;

an initial LED string coupled to the output of the single switching power regulator;
a first LED string coupled to the output of the single switching power regulator through the initial LED string and configured
to emit light of a first color temperature based on a first portion of the regulated current flowing through the first LED
string;

a second LED string coupled to the output of the single switching power regulator through the initial LED string and configured
to emit light of a second color temperature based on a second portion of the regulated current flowing through the second
LED string, the second color temperature being different than the first color temperature; and

circuitry configured to allocate the regulated current between the first portion of the regulated current flowing through
the first LED string and the second portion of the regulated current flowing through the second LED string responsive to changes
in the desired brightness level such that a light output from the LED lighting system increases in redness responsive to a
decrease in the desired brightness level, the circuitry comprising:

a first switch coupled in series with the first LED string, wherein a duty cycle of ON and OFF times of the first switch is
responsive to a first switch control signal; and

a color control module configured to generate the first switch control signal responsive to the target current level.

US Pat. No. 9,772,367

LOAD CONNECTION DETECTION

Dialog Semiconductor Inc....

1. An apparatus comprising:
an output port to be connected to a load;
a first input port to receive a first input signal;
a second input port coupled between the first input port and the output port, the second input port to receive a second input
signal;

a coupling circuit to couple the second input signal to the output port;
a frequency isolation circuit coupled between the first input port and the second input port, the frequency isolation circuit
having a frequency response to propagate the first input signal to the output port but prevent the second input signal from
propagating to the first input port; and

a detection circuit to detect whether the load is present or absent at the output port by determining a voltage of an output
signal at the output port, the detection circuit detecting that the load is absent at the output port responsive to determining
that an amplitude of the voltage is within a first amplitude range and detecting that the load is present at the output port
responsive to determining that the amplitude of the voltage is within a second amplitude range lower than the first amplitude
range.

US Pat. No. 9,768,686

FEEDBACK SCHEME FOR NON-ISOLATED POWER SUPPLY

Dialog Semiconductor Inc....

1. A switching power converter comprising:
a switch coupled between an input terminal for receiving an input voltage and a switching node;
an inductor coupled between the switching node and a first output terminal;
a diode coupled between the switching node and a second output terminal, the first and second output terminals configured
to provide an output voltage to a load; and

a controller coupled to the switching node, the controller configured to generate a control signal for turning on and turning
off the switch at each switching cycle of a plurality of switching cycles of the switch, wherein the controller comprises:

a reference signal generator circuit to generate a substantially constant reference voltage;
an integrator circuit comprising an operational amplifier to receive the substantially constant reference voltage on an inverting
input terminal and to receive a diode voltage across the diode on a non-inverting input terminal, the operational amplifier
to integrate a voltage difference between the substantially constant reference voltage and the diode voltage across the diode;
and

a switch control circuit to generate the control signal by processing the integrated voltage difference.

US Pat. No. 9,674,911

ARBITRARY PULSE ALIGNMENT TO REDUCE LED FLICKER

DIALOG SEMICONDUCTOR INC....

1. A system, comprising:
a light-emitting diode (LED);
a switch in series with the LED and configured to control a current through the LED responsive to the switch cycling on and
off such that the current flows through the LED while the switch is on and such that the current is stopped while the switch
is off; and

a pulse width modulation (PWM) controller configured to generate a plurality of pulses responsive to a corresponding plurality
of cycles of a synchronization clock to control the cycling of the switch, each pulse having a pulse width, wherein the PWM
controller is further configured to generate each pulse responsive to a target time defined with regard to a reference time
in the corresponding cycle of the synchronization clock such that the pulse has a leading portion of the pulse width that
precedes its target time and such that the pulse has a trailing portion of the pulse width subsequent to its target time,
and wherein the PWM controller is further configured to change the leading portion by a percentage of the pulse width across
successive pulses in a first subset of the plurality of pulses.

US Pat. No. 9,509,205

POWER CONVERTER WITH NEGATIVE CURRENT CAPABILITY AND LOW QUIESCENT CURRENT CONSUMPTION

Dialog Semiconductor (UK)...

1. A power converter for converting a DC input voltage to a DC output voltage, the power converter comprising:
an output node;
a pass device connected to the output node of the power converter, the pass device being configured to operate in accordance
with a PWM signal and to supply at least a portion of an output current of the power converter;

a PWM comparator for generating the PWM signal for controlling operation of the pass device in accordance with a current conducted
by the pass device and a difference between an output voltage of the power converter and a reference voltage, the PWM comparator
having a first input terminal and a second input terminal;

a first current sensing circuit for outputting a first sense current depending on the current conducted by the pass device,
the first current sensing circuit being configured to sense the current conducted by the pass device if the current conducted
by the pass device has a given polarity, the first current sensing circuit further being connected to the PWM comparator in
such a manner that a voltage depending on the first sense current is supplied to the first input terminal of the PWM comparator;
and

a second current sensing circuit for outputting a second sense current depending on the current conducted by the pass device,
the second current sensing circuit being configured to sense the current conducted by the pass device if the current conducted
by the pass device has a polarity opposite to the given polarity, the second current sensing circuit further being connected
to the PWM comparator in such a manner that a voltage depending on the second sense current is supplied to the second input
terminal of the PWM comparator.

US Pat. No. 9,866,123

POWER CONVERTER WITH DYNAMIC PRELOAD

Dialog Semiconductor Inc....

1. A power converter comprising:
a magnetic component coupled between an input and an output of the power converter, the output of the power converter having
an output voltage for providing power to a load;

a switch to control current through the magnetic component according to on and off times of the switch; and
a dynamic preload circuit coupled to the output of the power converter, the dynamic preload circuit dissipating power from
the output of the power converter and presenting a resistance to the output of the power converter that is adjusted responsive
to a signal indicative of the output voltage at the output of the power converter.

US Pat. No. 9,474,120

ACCURATE MAINS TIME-BASE FOR LED LIGHT DRIVER

Dialog Semiconductor (UK)...

1. A controller for a driver circuit of a solid state lighting, referred to as SSL, device, wherein the driver circuit comprises
a power converter configured to transfer energy from an input of the driver circuit to the SSL device; wherein the energy
at the input is derived from an AC mains voltage comprising a sequence of cycles; wherein the controller is configured to
determine a dim level for the SSL device;
determine a synchronization signal (411) by comparing a voltage derived from the AC mains voltage with a pre-determined threshold;

determine a sequence of PWM pulses based on the synchronization signal such that
the sequence of PWM pulses comprises one or more PWM pulses per half-cycle of the AC mains voltage; and
the one or more PWM pulses for a current half-cycle n depend on the synchronization signal (411) for at least one half-cycle prior to the current half-cycle n where n is an integer; and

operate the power converter in a first operation mode for supplying energy to the SSL device at a first energy level within
the sequence of PWM pulses, and operate the power converter in a second operation mode in between the PWM pulses; wherein
in the second operation mode the power converter is operated for supplying energy to the SSL device at a second energy level;
wherein the second energy level is lower than the first energy level; and wherein the first energy level and/or a width of
the one or more PWM pulses depend on the dim level.

US Pat. No. 9,450,490

AUTOMATIC REFERENCE GENERATOR IN SWITCHING BOOST CONVERTERS

Dialog Semiconductor (UK)...

1. A switching converter to minimize a regulation error comprising:
a port for a static reference voltage;
a window comparator configured to comparing the static reference voltage with a scaled output voltage of the switching converter
capable of setting control signals for an up and down counter with successive incremental corrections if a target range is
exceeded;

an auxiliary reference generator comprising the up and down counter, wherein an output of the auxiliary reference generator
equals the static reference voltage if the scaled output voltage of the switching converter does not exceed the target range
and the output of the auxiliary reference generator performs the successive incremental corrections of the static reference
voltage if the scaled output voltage of the switching converter exceeds the target range;

an error amplifier, configured to compare the scaled output voltage of the switching converter with the output of the auxiliary
reference generator; and

a clock source to clock the up and down counter.

US Pat. No. 9,686,834

POWERING INTERNAL COMPONENTS OF LED LAMPS USING DISSIPATIVE SOURCES

Dialog Semiconductor Inc....

1. A light-emitting diode (LED) lamp, comprising:
one or more LEDs;
a power converter receiving a primary side input current and supplying a regulated current to the one or more LEDs;
an LED driver receiving an input signal from a dimmer switch indicative of an amount of dimming for the LED lamp, the LED
driver controlling the power converter to provide the regulated current through the one or more LEDs based on the input signal
such that an output light intensity of the one or more LEDs substantially corresponds to the amount of dimming for the LED
lamp;

a regulated output providing operating power for the LED driver; and
a controller regulating the regulated output, the controller selecting a power source for charging the regulated output from
two or more power sources comprising the primary side input current and a bleeder circuit that when activated generates a
bleeder current in the dimmer switch, wherein the regulated output is charged by the selected power source.

US Pat. No. 9,312,747

FAST START-UP CIRCUIT FOR LOW POWER CURRENT MIRROR

Dialog Semiconductor (UK)...

1. A fast startup circuit, comprising:
a) a first capacitor charged to zero volts when a disable switch is closed
b) a second capacitor charged to a bias voltage when the disable switch is closed; and
c) a current mirror circuit enabled in which the disable switch is opened and a enable switch is closed, wherein the current
mirror circuit comprises the first and second capacitors, and wherein charge on the first and second capacitors equalize causing
current in the current mirror circuit to start at a steady state operating value.

US Pat. No. 9,392,661

LOW-OVERHEAD CURRENT GENERATOR FOR LIGHTING CIRCUITS

Dialog Semiconductor (UK)...

1. A lighting system comprising:
a plurality of light emitting diode, LED, circuits;
a power source for providing a drive voltage to the plurality of LED circuits;
for each LED circuit, a first variable resistance element connected between the respective LED circuit and ground;
for each LED circuit, a first feedback circuit configured to control a voltage at a first node between the respective LED
circuit and the respective first variable resistance element to a first voltage;

a current source; and
a second variable resistance element connected between the current source and ground,
wherein each first variable resistance element is configured to attain a resistance value depending on a resistance value
attained by the second variable resistance element.

US Pat. No. 10,001,795

LINEAR REGULATOR WITH IMPROVED STABILITY

Dialog Semiconductor (UK)...

1. A linear regulator comprisinga first amplifier stage having an input and an output, one of the inputs being coupled with the output of the linear regulator;
an intermediate amplifier stage having an input and an output, the input of the intermediate amplifier stage being coupled to the output of the first amplifier stage;
a driver stage having an input and an output;
a pass device driven by the output of the driver stage, the output of the pass device proving the output of the linear regulator; and
a voltage-to-current feedback circuit coupled with the driver stage and the output of the first amplifier stage for regulating the output resistance of the first amplifier stage depending on load conditions of the linear regulator, the voltage-to-current feedback circuit comprising a transistor and a current limitation circuit to limit the regulation of the output resistance of the first amplifier stage to low load conditions of the linear regulator,
wherein the input of the driver stage is coupled to said output of said intermediate amplifier stage and the gate of the transistor of said voltage-to-current feedback circuit is coupled with the gate of the pass device.

US Pat. No. 9,471,084

APPARATUS AND METHOD FOR A MODIFIED BROKAW BANDGAP REFERENCE CIRCUIT FOR IMPROVED LOW VOLTAGE POWER SUPPLY

Dialog Semiconductor (UK)...

15. A bandgap voltage reference circuit with improved operation at low voltage power supply, the circuit comprising:
a first npn bipolar transistor;
a second npn bipolar transistor wherein the base of said second npn bipolar transistor and first npn bipolar transistor are
electrically coupled;

a third npn bipolar transistor wherein the base of said third npn bipolar transistor is electrically connected to the base
of said first npn bipolar transistor and electrically connected to the collector of said third npn bipolar transistor;

a first resistor element electrically connected to the emitter of said second npn bipolar transistor;
a second resistor element electrically connected to the emitter of said first npn bipolar transistor;
a third resistor element electrically connected to the emitter of said third npn bipolar transistor;
a fourth resistor element electrically connected to the collector of said third npn bipolar transistor;
a first pnp bipolar transistor wherein said first pnp bipolar transistor base and collector are electrically connected to
said first npn bipolar transistor;

a second pnp bipolar transistor wherein said second pnp bipolar transistor base is electrically connected to said first pnp
bipolar transistor and electrically connected to said second npn bipolar transistor;

a third pnp bipolar transistor wherein said third pnp bipolar transistor base is electrically connected to said second pnp
bipolar transistor and electrically connected to said fourth resistor; and,

a bandgap voltage reference output wherein said bandgap voltage reference output is connected to said third pnp bipolar transistor,
and said fourth resistor; and,
wherein said base voltage of the first npn bipolar transistor is expressed as a function of Vbe, ?Vbe, and said first and
said second resistors
and the bandgap output voltage can be calculated as a function of Vbe, ?Vbe, and said first resistor, said third resistor,
and said fourth resistor element

US Pat. No. 9,426,852

DUAL MODE ANALOG AND DIGITAL LED DIMMING VIA MAINS VOLTAGE

Dialog Semiconductor (UK)...

1. A method for controlling a lamp assembly, comprising the steps of:
detecting a mains voltage supplied to the lamp assembly;
evaluating the waveform of the mains voltage and determining a light control signal based on the mains voltage waveform;
applying a demodulation process to the mains voltage to demodulate a digital data signal;
deciding a control operation mode based on the result of applying a demodulation process to the mains voltage; and
generating a drive signal to drive a light source of the lamp assembly based on the determined light control signal or the
demodulated data signal depending on the decided control operation mode,

the method further comprising detecting whether a phase cut was applied to the mains voltage waveform and deciding the control
operation mode based on whether a phase cut is detected or a digital data signal can be demodulated.

US Pat. No. 9,575,500

SINK/SOURCE OUTPUT STAGE WITH OPERATING POINT CURRENT CONTROL CIRCUIT FOR FAST TRANSIENT LOADING

Dialog Semiconductor (UK)...

1. A voltage regulator comprising
an amplification stage configured to control a voltage level of a first gain node and of a second gain node in response to
an input voltage at an input node, in order to activate a first and a second output stage, respectively; wherein the second
gain node is different from the first gain node;

the first output stage configured to source a current at an output node of the voltage regulator from a first potential, in
dependence of the voltage level of the first gain node; wherein the first output stage is activated if the current which is
sourced at the output node exceeds a pre-determined first maintenance current;

the second output stage configured to sink a current at the output node to a second potential, in dependence of the voltage
level of the second gain node; wherein the first potential is different from the second potential; wherein the second output
stage is activated if the current which is sunk at the output node exceeds a pre-determined second maintenance current; and

a first operating point control circuit configured to set the voltage level of the first gain node such that the first maintenance
current is sourced by the first output stage, when the second output stage is activated; and/or

a second operating point control circuit configured to set the voltage level of the second gain node such that the second
maintenance current is sunk by the second output stage, when the first output stage is activated,
wherein
the first output stage comprises
a first control transistor having a gate which is coupled to the first gain node, and being configured to vary a first control
current through the first control transistor, subject to a voltage level at the first gain node; and

a first output amplifier configured to source an amplified version of the first control current to the output node; and/or
the second output stage comprises
a second control transistor having a gate which is coupled to the second gain node, and being configured to vary a second
control current through the second control transistor, subject to a voltage level at the second gain node; and

a second output amplifier configured to sink an amplified version of the second control current at the output node;wherein
the first output amplifier comprises a first current mirror with a first diode transistor and a first output transistor;
the first diode transistor is arranged in series with the first control transistor such that the first diode transistor is
traversed by the first control current;

a drain of the first output transistor is coupled to the output node;
the first output transistor is traversed by the amplified version of the first control current, which is sourced at the output
node;

the second output amplifier comprises a second current mirror with a second diode transistor and a second output transistor;
the second diode transistor is arranged in series with the second control transistor such that the second diode transistor
is traversed by the second control current;

a drain of the second output transistor is coupled to the output node; andthe second output transistor is traversed by the amplified version of the second control current, which is sunk at the output
node.

US Pat. No. 9,379,610

BUCK VARIABLE NEGATIVE CURRENT

Dialog Semiconductor (UK)...

1. A switching mode power supply (SMPS), comprising:
a) a buck power regulator comprising a high-side PMOS pass transistor and a low side active diode;
b) the low-side active diode capable of continuously varying a threshold voltage;
c) a circuitry configured to control the threshold voltage of the active diode, comprising:
a first comparison circuit configured to compare a voltage representing an output voltage of the buck converter with a reference
voltage, wherein an output of the first comparison circuit is connected to a first terminal of a circuit having resistance
and to a first input of a second comparison circuit;

said circuit having resistance, wherein a second terminal of the circuit having resistance is connected to ground, wherein
a resistance of the circuit having resistance is capable of determining a threshold of the second comparison circuit permitting
some of an excess current that has built up in the buck regulator to be conducted each cycle by the low-side active diode
to Vss, or circuit ground;

said second comparison circuit, configured to detect a zero crossing of a voltage of a node (LX) located between the PMOS
pass transistor and the active diode, wherein a second input of the second comparison circuit is connected to the LX node
and an output of the second comparison circuit is connected to a first input of a logic AND circuit; and

said logic AND circuit capable of turning off the low-side active diode if the high side PMOS pass transistor is not being
driven by a signal and a voltage change across the low-side active diode is detected by the second comparison circuit, wherein
an output of the AND circuit is connected to a gate of the low-side active diode; and

d) said buck power regulator capable of discharging a portion of excess current to circuit ground when an overvoltage resulting
from a high output voltage causes the threshold voltage to rise to allow discharge of said portion of the excess current.

US Pat. No. 9,240,762

METHOD AND CIRCUIT FOR IMPROVING THE SETTLING TIME OF AN OUTPUT STAGE

Dialog Semiconductor (UK)...

1. An amplifier comprising an output stage for providing an output current at an output voltage, in dependence of an input
voltage at a stage input node of the output stage; wherein the output stage comprises
a first input transistor; wherein a gate of the first input transistor is coupled to the stage input node of the output stage;
a first diode transistor; wherein the first diode transistor is arranged in series with the input transistor;
a pass device configured to provide the output current at the output voltage; wherein the first diode transistor and the pass
device form a current mirror; wherein a midpoint between the first input transistor and the first diode transistor is coupled
to a gate node of the pass device;

a second input transistor; wherein a gate of the second input transistor is coupled to the stage input node of the output
stage; wherein the second input transistor is configured to control a voltage level at a replica node, in dependence of the
input voltage; and

a buffer transistor; wherein a gate of the buffer transistor is coupled to the replica node and wherein an input node of the
buffer transistor is coupled to the gate node, such that the buffer transistor is configured to sink or source a charge current
at the gate node, subject to the voltage level at the replica node and the voltage level at the gate node.

US Pat. No. 10,021,745

LED DIMMING WITH SLOW DATA CHANNEL TRANSMISSION

DIALOG SEMICONDUCTOR INC....

1. A data transmission method for an isolating device, comprising;adjusting one of a pulse period, a pulse width, and an off time for a data input pulse responsive to a desired analog value;
driving the data input pulse and a calibration input pulse through the isolating device to produce an output signal;
comparing the output signal to a threshold to generate a received calibration pulse resulting from the transmission of the calibration input pulse through the isolating device and to generate a received data pulse resulting from the transmission of the data input pulse through the isolating device, wherein a pulse width for the received data pulse equals the pulse width for the data input pulse minus a time difference resulting from a rising edge delay and a falling edge delay for the isolating device;
recovering the desired analog value without any distortion resulting from a rising edge delay and a falling edge delay for the isolating device by comparing the received data pulse to the received calibration pulse.

US Pat. No. 9,961,729

TRIMMING SYSTEM AND METHOD FOR REGULATED CURRENT MIRRORS

Dialog Semiconductor (UK)...

1. A trimming system for trimming a load current provided to a load terminal, the trimming system comprising:a reference current circuit branch with
a current source configured to generate a reference current;
a first variable resistance element; and
a first decoupling resistance element connected between the current source and the first variable resistance element;
a load current circuit branch with
the load terminal;
a second variable resistance element configured to attain a resistance value depending on a resistance value attained by the first variable resistance element; and
a second decoupling resistance element connected between the load terminal and the second variable resistance element;
a voltage regulator configured to regulate a second voltage at a node between the load terminal and the second decoupling resistance element depending on a first voltage at a node between the current source and the first decoupling resistance element,
a current regulator configured to regulate the load current provided to the load terminal based on a voltage difference between a first output terminal of the first decoupling resistance element and a second output terminal of the second decoupling resistance element.

US Pat. No. 9,541,933

HIGH SPEED REGULATOR WITH LOW CAPACITOR VALUES

Dialog Semiconductor (UK)...

1. A regulator configured to provide a load current at an output voltage in dependence of an input voltage; wherein the regulator
comprises
a core regulator configured to provide a core current at a core output voltage in dependence of the input voltage;
current sensing means configured to provide an indication of the core current;
wherein the output voltage is dependent on the core output voltage and on a voltage drop at the current sensing means;
a current source configured to provide an auxiliary current based on the indication of the core current; wherein the load
current is dependent on the core current and on the auxiliary current; and

offset circuitry configured to offset a core input voltage to the core regulator relative to the input voltage, such that
the output voltage is proportional to the input voltage, thereby compensating the voltage drop at the current sensing means.

US Pat. No. 9,431,904

DC/DC CONVERTER EFFICIENCY IMPROVEMENT FOR LOW CURRENT LEVELS

Dialog Semiconductor (UK)...

1. A controller for controlling a power converter which is configured to convert electrical power at an input voltage into
electrical power at an output voltage, wherein the power converter comprises a first inverter stage comprising a first high
side switch and a first low side switch which are arranged in series between the input voltage and a reference voltage; wherein
the power converter further comprises a second inverter stage comprising a second high side switch and a second low side switch
which are arranged in series between the input voltage and the reference voltage; wherein a midpoint between the first high
side switch and the first low side switch is coupled with a midpoint between the second high side switch and the second low
side switch; and wherein the electrical power at the output voltage is drawn from the midpoint; wherein the power converter
comprises a pre-determined number N of inverter stages, N>1; wherein the controller is configured to
determine an indication of a requested level of the electrical power at the output voltage, and
activate or deactivate the second inverter stage based on the indication of the requested level of the electrical power at
the output voltage;

determine a default number n of active inverter stages based on the indication of the requested level of the electrical power
at the output voltage, with 0
operate the power converter with the default number n of active inverter stages wherein the default number n of active inverter
stages comprises the first inverter stage;

determine a peak of the requested level of the electrical power at the output voltage; and
operate the power converter with more than the default number n of active inverter stages, subject to determining a peak of
the requested level of the electrical power at the output voltage.

US Pat. No. 9,232,596

MAINS SYNCHRONIZED PWM DIMMING

Dialog Semiconductor (UK)...

1. A controller for a driver circuit of a solid state lighting, referred to as SSL, device, wherein the driver circuit comprises
a power converter configured to transfer energy from an input of the driver circuit to the SSL device; wherein the energy
at the input is derived from an AC mains voltage at a mains frequency; wherein the controller is configured to
determine a dim level for the SSL device;
if the dim level is above a pre-determined dim level threshold, operate the power converter continuously in a first operation
mode for supplying energy to the SSL device at a first energy level; and

if the dim level is below the pre-determined dim level threshold, operate the power converter in the first operation mode
at a time duration of PWM pulses, and operate the power converter in a second operation mode at a time duration in-between
the PWM pulses; wherein in the second operation mode the power converter is operated for supplying energy to the SSL device
at a second energy level; wherein the second energy level is lower than the first energy level; and wherein the PWM pulses
are synchronized with the AC mains voltage.

US Pat. No. 9,907,131

ARBITRARY PULSE ALIGNMENT TO REDUCE LED FLICKER

DIALOG SEMICONDUCTOR INC....

1. A system, comprising:
a light-emitting diode (LED);
a switch configured to control a current through the LED responsive to the switch cycling on and off; and
a pulse width modulation (PWM) controller configured to generate a plurality of pulses responsive to a corresponding plurality
of cycles of a synchronization clock to control the cycling of the switch, each pulse having a pulse width, wherein the PWM
controller is further configured to generate each pulse responsive to a target time defined with regard to a reference time
in the corresponding cycle of the synchronization clock such that the pulse has a leading portion of the pulse width that
precedes its target time and such that the pulse has a trailing portion of the pulse width subsequent to its target time,
and wherein the PWM controller is further configured to change the leading portion by a percentage of the pulse width across
successive pulses in a first subset of the plurality of pulses.

US Pat. No. 9,383,764

APPARATUS AND METHOD FOR A HIGH PRECISION VOLTAGE REFERENCE

Dialog Semiconductor (UK)...

1. A voltage reference circuit between a power supply node and a ground node and configured for generating a reference voltage
comprising:
a first current mirror with a first NMOS transistor and a second NMOS transistor wherein said first NMOS transistor threshold
voltage is not equal to said second NMOS transistor threshold voltage;

a second current mirror with a first PMOS transistor, a second PMOS transistor and third PMOS transistor configured to be
coupled to said power supply node, wherein the first PMOS transistor is coupled to the gate of the second PMOS transistor,
and third PMOS transistor, and wherein said second PMOS transistor and third PMOS transistor drains are coupled to said first
NMOS transistor drain and said second NMOS transistor drain, respectively;

a current source configured to provide current to said second current mirror;
an amplifier configured with a first and second input configured to be connected to the drains of said first NMOS transistor
and said second NMOS transistor; and,

a feedback loop configured to be the output of said amplifier.

US Pat. No. 9,999,110

LED DRIVER WITH COMPREHENSIVE FAULT PROTECTIONS

Dialog Semiconductor Inc....

1. An LED fault detection circuit configured to detect one or more faults of an LED channel comprising one or more LEDs coupled to a drain node of a transistor and a resistor coupled to a source node of the transistor, the circuit comprising:a first fault detection circuit configured to detect a short fault across one or more of the LEDs, the first fault detection circuit coupled to the drain node of the transistor;
a second fault detection circuit coupled to a source node of the transistor and configured to:
when the LED fault detection circuit is operating in an operating mode, detect an open fault within the one or more LEDs; and
when the LED fault detection circuit is operating in a calibration mode, detect a short fault across the resistor, wherein the LED fault detection circuit is configured to operate in the calibration mode before being configured to operate in the operating mode;
a third fault detection circuit configured to detect a short fault across the drain node and the source node of the transistor, the third fault detection circuit coupled to the gate node of the transistor; and
a fourth fault detection circuit comprising a comparator, a second transistor, and a current source coupled to a drain node of the second transistor, the fourth fault detected circuit coupled to the source node of the transistor and configured to detect an open fault across the resistor by, when the second transistor is configured to operate as a closed switch, comparing the voltage at the source node of the transistor to a reference voltage and outputting a fault signal indicating a presence or absence of the open fault across the resistor based on the comparison.

US Pat. No. 9,532,427

LOW-OVERHEAD CURRENT GENERATOR FOR LIGHTING CIRCUITS

Dialog Semiconductor (UK)...

1. A lighting system comprising:
a light emitting diode, LED, circuit;
a power source for providing a drive voltage to the LED circuit; and
a programmable current source connected between the LED circuit and ground and configured to output an output current in accordance
with a digital input code representing a numerical value,

wherein the programmable current source comprises switching means for performing a switching operation in accordance with
the digital input code; and

the switching means is adapted to switch a predetermined number of bits on the least significant bit, LSB, side of the digital
input code in accordance with binary coding, and to switch a remaining number of bits on the most significant bit, MSB, side
of the digital input code in accordance with unary coding.

US Pat. No. 9,531,260

VOLTAGE DOUBLER AND VOLTAGE DOUBLING METHOD FOR USE IN PWM MODE

Dialog Semiconductor (UK)...

1. An apparatus for generating a pulse width modulated, PWM, signal with a first period of time and a second period of time,
wherein said PWM signal has a PWM pulse during the second period and does not have the PWM pulse during the first period,
the apparatus comprising:
a voltage source;
a capacitor;
an output node for outputting the PWM signal, to drive an electric motor;
a switchable circuit assembly for connecting the voltage source, the capacitor and the output node; and
control means for controlling switching of the switchable circuit assembly,
wherein the switchable circuit assembly is adapted to be switchable between a first circuit configuration in which the capacitor
is connected in parallel to the voltage source so as to be chargeable by the voltage source, and a second circuit configuration
in which the capacitor is connected in series between the voltage source and the output node such that polarities of the voltage
source and the capacitor are aligned with each other; and

wherein the control means is adapted to control the switchable circuit assembly to switch to the first circuit configuration
in the first period, and to switch to the second circuit configuration in the second period.

US Pat. No. 9,379,612

OUTPUT CURRENT MONITOR CIRCUIT FOR SWITCHING REGULATOR

Dialog Semiconductor (UK)...

1. A circuit providing switching regulation with an improved current monitor comprising:
an output stage configured to provide switching comprising a first and second transistor;
a sense circuit configured to provide signal sensing from the first transistor in said output stage;
a sampling switch circuit configured to provide sample signals from said sense circuit, wherein the sampling switch circuit
is configured to provide a first and second signal to said integrator;

an integrator circuit configured to provide sample signals from said sampling switch circuit;
a comparator configured to provide signals from said integrator circuit; and
a digital-to-analog converter (DAC) configured to provide feedback signal from said comparator.

US Pat. No. 9,100,041

FLASH CONVERTER CAPACITANCE REDUCTION METHOD

Dialog Semiconductor (UK)...

1. A circuit for reduction of total harmonic distortion and noise in a multiple bit oversampling data conversion apparatus
with limited code transitions between digital code words representing an instantaneous analog signal level, comprising:
a most significant code word boundary comparator for determining if a previous data conversion code is equal to or greater
than a most significant code word boundary;

a least significant code word boundary comparator for determining if a previous data conversion code is equal to or less than
a least significant code word boundary; and

a code converter enabling circuit connected for generating and transferring an enabling/disabling signal to a plurality of
code converter circuits within the multiple bit data bit oversampling data conversion circuit for enabling and disabling groups
of the code converter circuits to reduce a capacitance loading on a delta-sigma modulator of the multiple bit oversampling
data conversion apparatus to reduce the total harmonic distortion and noise in the multiple bit oversampling data conversion
apparatus;

wherein when the most significant word boundary comparator indicates that the previous data conversion code is equal to or
greater than the most significant code word boundary, the group of code converters circuits designated to represent the most
significant data bits of a current data conversion code are enabled and the group of code converter circuits designated to
represent the least significant data bits of a current data conversion code are disabled;

wherein when the least significant word boundary comparator indicates that the previous data conversion code is equal to or
less than the least significant code word boundary, the group of code converters circuits designated to represent the least
significant data bits of a current data conversion code are enabled and the group of code converter circuits designated to
represent the most significant data bits of a current data conversion code are disabled.

US Pat. No. 9,471,071

APPARATUS, SYSTEM AND METHOD FOR VOLTAGE REGULATOR WITH AN IMPROVED VOLTAGE REGULATION USING A REMOTE FEEDBACK LOOP AND FILTER

Dialog Semiconductor (UK)...

1. A voltage regulator with improved voltage regulation comprising:
a power management unit (PMU);
a remote load;
a remote feedback network electrically connected to said remote load and whose output is electrically coupled to said power
management unit PMU;

a printed circuit board (PCB) comprising at least one said printed circuit board (PCB) trace electrically coupling said power
management unit (PMU) and said remote load;

a filtering capacitor; and
a remote feedback loop filter electrically coupled to said filtering capacitor and to said power management unit PMU.

US Pat. No. 9,436,205

APPARATUS AND METHOD FOR LOW VOLTAGE REFERENCE AND OSCILLATOR

Dialog Semiconductor (UK)...

1. A voltage reference circuit between a power supply node and a ground node and configured for generating a reference voltage,
comprising:
a current mirror function providing matching and sourcing network branches wherein a first p-channel MOSFET sources current;
a voltage generator network sourced from said current mirror providing a base-emitter voltage wherein said first p-channel
MOSFET sources current to said voltage generator network;

a current drive function network electrically sourced from said current mirror function wherein a second p-channel MOSFET
sources current for said current drive function;

an output network function sourced from said current mirror providing a voltage reference output voltage;
a first n-channel MOSFET device providing a base-emitter voltage (VBE);
wherein said current mirror function further comprises a third p-channel MOSFET which sources current for said output network
function, and a fourth p-channel MOSFET which sources current for said voltage generator network; and

wherein said voltage generator network comprises:
a first resistor element electrically coupled to the gate of said first n-channel MOSFET device;
a second resistor element electrically coupled to the gate of said first n-channel MOSFET device providing a PTAT function;
and,

a second n-channel MOSFET device whose MOSFET gate and MOSFET drain are electrically coupled to said second resistor element.

US Pat. No. 9,231,542

AMPLIFIER COMMON-MODE CONTROL METHOD

Dialog Semiconductor (UK)...

1. A fully differential amplifier system with common-mode control having reduced sensitivity to random offsets and mismatches
and improved common-mode loop bandwidth, comprising:
a fully differential main amplifier configured to receiving input signals via a positive input port Vip and a negative input
port Vin, and to generating output signals to a positive output port Vop and to a negative output port Von, wherein the main
amplifier is provided with a continuous-time signal path feedback network, wherein a first terminal of a positive branch of
the continuous-time signal path feedback network is connected to the positive input port Vip and a second terminal of the
positive branch of the continuous-time signal path feedback network is connected to the negative output port Von, and a first
terminal of a negative branch of the continuous-time signal path feedback network is connected to the negative input port
Vin and a second terminal of the negative branch of the continuous-time signal path feedback network is connected to the positive
output port Vop; and

an common-mode control sub-amplifier, which is configured to sensing common-mode voltages of the fully differential main amplifier
at a node Vcmip within a positive branch of the continuous-time signal path feedback network and at a node Vcmin within a
negative branch of the continuous-time signal path feedback network, to comparing the common-mode voltage sensed at nodes
Vcmin and Vcmip with a target reference voltage, and to regulating, depending on the result of the comparison, the output
common-mode voltage via the continuous signal path feedback network.

US Pat. No. 9,537,396

POWER SWITCH CONTROL BY ADJUSTING THE BASE CURRENT OF A BIPOLAR TRANSISTOR

Dialog Semiconductor (UK)...

1. A control circuit configured to control a power switch of a switched-mode power converter; wherein the power switch comprises
a bipolar transistor; wherein a collector of the power switch is arranged in series with an inductive element of the power
converter: —wherein the control circuit is configured to
determine an indication of a time instant, at which the power switch is switched off;
adjust a basis current for controlling the power switch based on a time interval between a time instant, at which the switching
off of the power switch was initiated, and the time instant, at which the power switch is switched off;

determine an indication of an emitter current of the power switch; and
determine an indication of a collector current of the power switch based on the indication of the emitter current by offsetting
the indication of the emitter current with an offset; wherein the offset is dependent on a characteristic of the inductive
element.

US Pat. No. 9,326,336

DUAL SWITCHER FLYBACK STRUCTURE FOR LED DRIVER

Dialog Semiconductor (UK)...

1. A controller for controlling a power converter to convert electrical power at an input voltage into electrical power at
an output voltage; wherein
the power converter comprises
a first switcher stage comprising a primary winding of a transformer which is arranged in series with a first power switch;
wherein the first switcher stage is arranged in parallel to the input voltage at an input of the power converter;

a second switcher stage comprising an auxiliary winding of the transformer which is arranged in series with a second power
switch;

wherein the second switcher stage is arranged in parallel to a reservoir capacitor; and
a secondary winding of the transformer which is arranged in parallel to the output voltage at an output of the power converter;
the controller is configured to
determine whether the input voltage is greater or smaller than a pre-determined voltage threshold;
operate the first switcher stage to transfer electrical power from the input of the power converter to the output of the power
converter, during a first time period when the input voltage is greater than the pre-determined voltage threshold; and

operate the second switcher stage to transfer electrical power from the reservoir capacitor to the output of the power converter,
during a second time period when the input voltage is smaller than the pre-determined voltage threshold.

US Pat. No. 9,270,183

CONVERTER ONE PIN SENSING

1. A power converter configured to convert electrical energy at an input voltage into electrical energy at an output voltage,
the power converter comprising
a power switch configured to be switched between an on-state and an off-state;
a voltage divider coupled to the input voltage for providing a first measurement signal;
a transformer comprising a primary winding and an auxiliary winding for providing a second measurement signal; wherein the
primary winding is arranged in series to the power switch; and

a controller configured to generate a control signal for putting the power switch into the on-state and into the off-state,
respectively; wherein the control signal is generated based on the first and the second measurement signal from the power
converter external to the controller; wherein the controller comprises a sensing pin configured to sense the first measurement
signal when the power switch is in the on-state, and configured to sense the second measurement signal when the power switch
is in the off-state, wherein

the auxiliary winding is coupled to the sensing pin, thereby providing the second measurement signal;
the auxiliary winding is coupled to the sensing pin via a diode; and
the diode is reverse biased, when the power switch is in on-state, thereby decoupling the auxiliary winding from the sensing
pin, when the power switch is in on-state.

US Pat. No. 9,407,144

METHOD FOR A CURRENT MODE BUCK-BOOST CONVERTER

Dialog Semiconductor (UK)...

7. A buck-boost converter with improved performance configured to generate separated Buck mode and Boost mode pulses, operating
with current mode control and having a continuous control signal, comprising:
circuitry configured for current sensing and slope ramp generation providing a first input to a buck-side comparator, wherein
a circuitry configured for error amplification and network compensation provides a control voltage VC,Buck as second input to the buck-side comparator, and wherein an output of the buck-side comparator provides a reset input to a
buck-side switching circuit configured to generate a buck duty cycle;

said circuitry configured for error amplification comprising a loop filter, generating a buck mode control voltage Vc,buck control voltage, and operating a compensation network, wherein said circuitry configured for error amplification has inputs
and an output, wherein a first input is a reference voltage, a second input is an output voltage of the buck-boost converter;

said buck-side comparator;
a circuitry configured for controlling a boost side comparator in relation to the buck mode control voltage Vc,Buck by generating a boost mode control voltage Vc,Boost, based on the buck mode control voltage Vc,Buck, according to an equation:
Vc,Boost=Vc,Buck??Vc, wherein Vc,Buck is the buck mode control voltage, and ?Vc defines a voltage shift, wherein the circuitry configured for controlling the boost side comparator has an input and an output,
wherein the input is the buck mode control voltage Vc,Buck and the output is the boost mode control voltage Vc,Boost, which is a second input to the boost side comparator;
said boost side comparator, wherein a boost-side circuitry configured for current sensing and slope ramp generation provides
a first input to the boost-side comparator and an output of the boost side comparator is a reset input to a boost-side switching
circuit configured to generate a boost duty cycle;

said buck-side switching circuit configured to generate a buck duty cycle, wherein a set input of the buck-side switching
circuit activates the generation of the buck duty cycle and an output of the buck-side switching circuit BuckFFOut is a first
input to a circuit configured to ensure that a buck-side switch is ON during boost mode;

wherein said buck-side switch is configured to generate buck mode pulses;
wherein said circuitry is configured to ensure that the buck-side switch is ON during Boost mode, wherein a signal BoostNext
is a second input;

wherein said boost-side switching circuit is configured to generate a boost duty cycle, wherein a set input of the boost-side
switching circuit activates the generation of the boost duty cycle and an output of the boost-side switching circuit controls
a boost side switch;

wherein said boost switch is configured to generate boost mode pulses, wherein the boost switch is OFF during buck mode; and
wherein a circuitry is configured to sample the output BuckFFOut of said buck-side switching circuit, is configured to generate
a buck duty cycle in order to compare the buck duty cycle with a reference buck duty cycle, and is configured to decide whether
a next pulse will be the Buck mode pulse or the Boost mode pulse, wherein an output of the circuitry configured to sampling
the output BuckFFOut is the signal BoostNext.

US Pat. No. 9,307,590

NON-LINEAR CURRENT IDAC WITH SYNTHESIS IN TIME DOMAIN

Dialog Semiconductor (UK)...

1. A method for supplying a specified electrical current to at least one light emitting diode (“LED”) included in a display
from a current (“I”) digital-to-analog converter (“IDAC”) (60), the IDAC (60) including a plurality of individual current sources/sinks (26):
a. for connecting in parallel to the LED so that a total amount of electrical current flowing through the LED equals the sum
of individual electrical currents respectively flowing through each of the current sources/sinks (26); and

b. at any instant in time connected current sources/sinks (26) being either:

i. turned on for supplying electrical current to the LED; or
ii. turned off thereby supplying no electrical current to the LED,the method for supplying the specified electrical current comprising the steps of:
a. when the specified electrical current exceeds a pre-established current threshold (94), increasing the electrical current flowing through the LED is effected by successively turning on individual current sources/sinks
(26) included in the IDAC (60) that had been previously turned off; and

b. when the specified electrical current is less that the pre-established current threshold (94), increasing the electrical current flowing through the LED is effected by turning on at least one additional current source/sink
(26) included in the IDAC (60) that had been previously turned off, the additional current source/sink (26) being alternatively initially turned on and then subsequently turned off so as to thereby generate a sequence of progressively
longer electrical current pulses (102) until the additional current source/sink (26) remains fully on.

US Pat. No. 9,520,788

APPARATUS AND METHOD FOR CURRENT SHARING IN A MULTI-PHASE SWITCHING REGULATOR

Dialog Semiconductor (UK)...

1. A multi-phase switching converter for minimizing direct current (d.c.) current, comprising:
a plurality of phases, wherein each phase comprises a driver circuit, and an output stage configured to connect to an inductor;
a plurality of current sense circuits for measuring current of each phase's output stage;
a current share circuit connected to receive an output of each of said current sense circuits wherein said current sense circuits
comprises a variable gain amplifier; and,

a control circuit for driving each of said driver circuits, wherein said current of each of said output stages is set to differ
among each of said phases, based on direct current (d.c.) resistance of said output stage and of said inductor.

US Pat. No. 9,471,077

METHOD TO PRE-SET A COMPENSATION CAPACITOR VOLTAGE

Dialog Semiconductor (UK)...

1. A voltage mode controlled buck converter enabled for smooth transition from sleep mode to active mode, comprising:
a main output stage comprising a high side switch and a low side switch both connected in series, wherein a driver stage is
driving the main output stage;

a coil, wherein a first terminal of the coil is connected to a node between the high side switch and the low side switch and
a second terminal of the coil is connected to an output port of the buck converter configured to providing an output voltage
of the buck converter;

a PWM control loop configured to control the buck converter during active mode, comprising an error amplifier configured to
receiving an output voltage feedback of the buck converter and a reference voltage, a compensation capacitor connected between
an output of the error amplifier and ground, a PWM comparator configured to compare the output of the error amplifier with
an output of a ramp signal generator, and the driver stage driving the main output stage, wherein an output of the PWM comparator
provides input to the driver stage; and

a local PWM feedback loop, capable of, when enabled intermittently during sleep mode, to set an appropriate compensation capacitor
voltage regardless of the length of the sleep period, comprises:

a dummy output stage, comprising a high side switch and a low side switch both connected in series, wherein the dummy output
stage is configured to be driven by the output of the PWM comparator, wherein an output of the dummy output stage is connected
to a filter; and

said filter, configured to provide at its output an emulated output voltage of the buck converter, wherein the output of the
filter is connected, when enabled during sleep mode, to the error amplifier instead of the output voltage feedback the buck
converter during active mode.

US Pat. No. 9,444,342

CLOCKED PULSE FREQUENCY MODULATION BUCK DC-TO-DC CONVERTER

Dialog Semiconductor (UK)...

1. A hysteretic mode control circuit within a DC-to-DC converter that is configured for operating in a continuous mode or
a discontinuous mode, the hysteretic mode control circuit comprising:
a first current limit circuit configured for determining a first reference limit signal that is used for controlling activation
of a first switch of a switching section of the DC-to-DC converter for transferring current to a load device placed at an
output of the DC-to-DC converter, wherein the first current limit circuit comprises:

a first dynamic current limit circuit comprising:
a first reference current source configured for providing a first maximum reference current;
a first limit current mirror connected such that a reference leg of the first limit current mirror receives the first maximum
reference current and configured such that a mirror leg of the first limit current mirror is connected to provide the first
reference limit signal for an output of the first current limit circuit to determine the switching interval and duration of
the first switch to provide a current to the filter section of the DC-to-DC converter;

a comparator connected to receive the first reference limit signal and a feedback signal from the output of the DC-to-DC converter
and configured for determining if the feedback signal is greater than or less than the first reference limit signal to generate
an output signal; and

a comparison switching device connected to receive the output signal of the comparator that is activated or deactivated to
divert a current from the reference leg of the first limit current mirror and thus modify the current in the reference leg
and thus the mirror leg of the first limit current mirror and thus adjust the voltage level of the first reference limit signal;
and

a pulse width modulation/pulse frequency modulation control circuit configured for receiving the first reference limit signal,
configured for comparing an amplitude of the first reference limit signal with a feedback signal from a power switching section
of the DC-to-DC converter and configured for generating a first reset control signal and a second reset control signal for
controlling deactivation of the first switch and a second switch of the DC-to-DC converter;

wherein the first current limit circuit and the pulse width modulation/pulse frequency modulation control circuit are configured
for varying a current limit that controls an interval and duration of time at which the switching section of the DC-to-DC
converter is switched to permit the DC-to-DC converter to manage large changes in an output current load of the DC-to-DC converter
while operating in the discontinuous operation mode.

US Pat. No. 9,294,119

METHOD FOR IMPROVING THE ACCURACY OF AN EXPONENTIAL CURRENT DIGITAL-TO-ANALOG (IDAC) USING A BINARY-WEIGHTED MSB

Dialog Semiconductor (UK)...

1. A method to achieve an exponential current digital-to-analog converter (IDAC) having improved accuracy using a binary-weighted
most significant bit (MSB) comprising:
defining a differential non-linearity (DNL);
defining number of LSB bits needed for the targeted DNL with a binary weighted MSB;
calculating the number of bits to be used for the binary-weighted MSB to get the desired IDAC base;
deriving the minimum current for the Imax;
defining the LSB as an exponential current mirror according to the specified relationship for the ILSB;
defining a binary weighted MSB according to the specified relationship for IMSB; and
defining a differential non-linearity (DNL) according to the definition

US Pat. No. 9,985,532

PULSE FREQUENCY MODULATION MODE TRANSITIONS FOR SINGLE STAGE POWER CONVERTER

DIALOG SEMICONDUCTOR INC....

1. A method of regulating a power switch in a switching power converter, comprising:while operating in a constant voltage pulse frequency modulation mode of operation having a current switching period; determining a peak voltage for constant voltage pulse frequency modulation operation for a current cycle of the power switch;
determining a peak voltage for constant current operation for the current cycle of the power switch responsive to the current switching period;
determining whether the peak voltage for constant current operation is less than or equal to the peak voltage for constant voltage frequency modulation operation; and
responsive to a determination that the peak voltage for constant current operation is less than or equal to the peak voltage for constant voltage pulse frequency modulation operation, transitioning to a constant current mode of operation for the current cycle of the power switch.

US Pat. No. 9,501,080

MULTIPLE OUTPUT OFFSET COMPARATOR

Dialog Semiconductor (UK)...

1. A multiple output comparator configured to compare a first input signal with a second input signal and at least one threshold
offset voltage level, comprising:
a difference circuit configured to receive a first input signal and a second input signal to determine when a magnitude of
the first input signal is greater than or lesser than the second input signal and configured to provide a true output signal
and a complement output signal that are indicative that magnitude of the first input signal is greater than or lesser than
the second input signal;

an output mirror driver circuit in communication with the difference circuit for receiving the true output signal and the
complement output signal comprising:

a first mirror circuit configured for receiving the true output signal from the difference circuit and configured for generating
at least one mirrored true output signal indicating that the first input signal is greater than or lesser than the second
input signal;

a second mirror circuit configured for receiving the complement output signal from the difference circuit and configured for
generating at least one mirrored complement output signal indicating that the first input signal is greater than or lesser
than the second input signal as offset by the at least one threshold offset voltage level wherein the at least one mirrored
complement output signal is combined with an associated at least one mirrored in-phase reference signal to form a plurality
of digital output signals; and

at least one offset generator in communication with the second mirror circuit and configured for accurately generating the
at least one threshold offset voltage level to ensure that the first input signal is greater than or lesser than the second
input signal as offset by the at least one threshold offset voltage level.

US Pat. No. 9,455,710

CLOCK ENABLING CIRCUIT

Dialog Semiconductor (UK)...

1. A clock enabling circuit for providing a gated clock signal (CLK_G) in response to receiving clock request information
(REQ), the clock enabling circuit comprising:
a clock request input for receiving the clock request information (REQ);
a clock input for receiving a clock signal (CLK);
a flip-flop stage comprising at least a first and a second flip-flop, wherein an output of the first flip-flop is coupled
with the input of the second flip-flop;

a first sub-circuitry comprising at least a first input being coupled with the clock request input and an output being coupled
with the flip-flop stage for providing a set information (SET) to the flip-flop stage in response to receipt of the clock
request information (REQ), the flip-flop stage being configured to provide a clock enabling information (CLK_EN) in response
to receiving the set information (SET);

a second sub-circuitry comprising a first and a second input, the first input being coupled with the clock input for receiving
the clock signal (CLK) and the second input being coupled with the output of the flip-flop stage for receiving the clock enabling
information (CLK_EN), the second sub-circuitry comprising a triggering circuitry for providing, based on the clock enabling
information (CLK_EN), a synchronized clock enabling information (sCLK_EN) that is synchronized with an edge of the clock signal
(CLK), an output of the second sub-circuitry providing the gated clock signal in response to the synchronized clock enabling
information (sCLK_EN) and the clock signal (CLK).

US Pat. No. 10,033,288

AUXILIARY LOAD APPLICATION FOR INCREASING DATA RATE OF MESSAGES OR FOR INCREASING THE RESPONSE SPEED TO TRANSMITTED MESSAGES IN A FLYBACK CONVERTER

DIALOG SEMICONDUCTOR INC....

1. A circuit, comprising:an output voltage terminal for providing an output voltage to a client device;
a ground terminal for providing ground to the client device;
an auxiliary load in series with a first switch, wherein the auxiliary load and the first switch are connected between the output voltage terminal and the ground terminal;
a second switch configured to interrupt a rectification of a secondary winding current conducted in a secondary winding of a transformer; and
a controller configured to respond to a need to transmit voltage pulses to a drain of a power switch transistor connected to a primary winding of the transformer at a desired rate that is greater than a current switching rate for the power switch transistor by, after a resonant oscillation of the drain voltage of the power switch transistor has ceased oscillating, closing the first switch and the second switch to lower the output voltage and to interrupt the rectification of the secondary current to transmit a voltage pulse to the drain of the power switch transistor.

US Pat. No. 9,641,369

CIRCUITS AND METHODS FOR DECODING AMPLITUDE MODULATED DATA SIGNALS FROM LARGE AMPLITUDE SINE WAVE CARRIER

Dialog Semiconductor (UK)...

1. A decoding circuit configured for assembling telegram data patterns from multiple encoded digital data frames demodulated
from a low frequency, large amplitude carrier signal modulated with higher frequency, multiple encoded digital data frames,
the decoding circuit comprising:
a period timer to establish an inter-transition time period between each transition within each of the multiple encoded digital
data frames wherein, the inter-transition time period is the time between each transition of the encoded digital data frames
between a first data level and a second data level and between the second data level and the first data level;

an inter-transition comparator in communication with the period timer and configured to compare each of the inter-transition
time periods with valid inter-transition time periods between each transition of the encoded digital data frames for determining
when the inter-transition time periods represent valid data frame patterns or are an error;

a data extractor configured to receive valid encoded digital data frames from the inter-transition comparator for extracting
transmitted digital data frames from within the valid data encoded digital data frames; and

a command formatter configured to receive the extracted digital data frames from the data extractor for assembling the telegram
data patterns for transfer for subsequent processing.

US Pat. No. 9,559,587

HIGH VOLTAGE DC/DC CONVERTER WITH MASTER/SLAVE OUTPUT STAGE

Dialog Semiconductor (UK)...

1. A power converter configured to convert electrical power at an input voltage into electrical power at an output voltage,
wherein the power converter comprises
a first inverter stage with
a first half bridge comprising a first high side switch and a first low side switch which are arranged in series between the
input voltage and a reference voltage; and

a first high side driver for providing a first drive signal for the first high side switch, subject to a high side control
signal at a drive voltage level;

a first high side feedback unit configured to provide a first high side feedback signal by sensing the first drive signal
for the first high side switch;

a second inverter stage with
a second half bridge comprising a second high side switch and a second low side switch which are arranged in series between
the input voltage and the reference voltage; and

a second high side driver for providing a second drive signal for the second high side switch, subject to the high side control
signal at the drive voltage level; and

a second high side feedback unit configured to provide a second high side feedback signal by sensing the second drive signal
for the second high side switch; and

a single level shifting unit configured to convert a high side control signal at a logic voltage level into the high side
control signal at the drive voltage level for driving the first and second high side switches;

a high side combining unit configured to provide a combined high side feedback signal by combining the first and second high
side feedback signals; wherein the high side combining unit comprises an AND gate for combining the first and second high
side feedback signals; and

an inverse level shifting unit configured to shift the combined high side feedback signal from the drive voltage level to
the logic voltage level.

US Pat. No. 9,513,870

MODULO9 AND MODULO7 OPERATION ON UNSIGNED BINARY NUMBERS

Dialog Semiconductor (UK)...

1. A method to obtain simultaneous results of modulo7 and modulo9 operation on an unsigned number N, the method comprising
the steps of:
(1) representing the unsigned number N in binary format;
(2) Finding-finding a common multiple ‘M’ of 9 and 7 which is the closest to a number “d”, d being a power of 2;
(3) determining Lrem such that 0?Lrem?M, by application of the split-and-accumulate method multiple times if required, wherein
division of N by d (N/d) is performed by splitting binary representation of N into quotient qd and remainder rd, and subsequently adding them together to form the intermediate sum ‘qd+rd’; thereafter if this intermediate sum is greater than M, the split-and-accumulate method is applied again on the sum ‘qd+rd’, this is done repeatedly till the resulting sum ‘qd+rd’ is assured to be less than or equal to M, at which point Lrem is assigned the value of this sum ‘qd+rd’;

(4) determining N modulo7 according to equation N modulo7=(Lrem) modulo 7 by one or more split-and-accumulate operations
(5) determining N modulo9 according to equation N modulo9=(Lrem) modulo 9 by one or more split-and-accumulate operations and
(6) providing a circuitry comprising full adders and logic gates capable of performing full-addition operations, comparison
and multiplexing functions, configured to perform steps 3-5.

US Pat. No. 9,461,487

BATTERY STACK CONFIGURATION IN A MULTI-BATTERY SUPPLY SYSTEM

Dialog Semiconductor (UK)...

1. A battery powerable device comprising:
i. at least two (2) rechargeable batteries;
ii. both:
a. at least one (1) buck DC-DC converter; and
b. at least one (1) boost DC-DC converter, each DC-DC converter having a power input that receives electrical power for energizing
DC-DC converter operation; and

iii. a power management circuit that:
a. when the device is connected to an electrical power source for recharging the batteries, connects the batteries in parallel
and the parallel connected batteries being connected to the power inputs of both the buck DC-DC converter and boost DC-DC
converter for energizing the operation thereof; and

b. when the device is not connected to an electrical power source for recharging the batteries, connects the batteries in
series with:

1. the series connected batteries being connected to the power input of the boost DC-DC converter for energizing the operation
thereof; and

2. one of the series connected batteries being connected to the power input of the buck DC-DC converter for energizing the
operation thereof,
whereby during battery powered operation of the device the boost DC-DC converter operates more efficiently in comparison with
operation thereof that is energized by the batteries connected in parallel.

US Pat. No. 9,455,717

DIGITAL COUNTER COMPRISING REDUCED TRANSITION DENSITY

Dialog Semiconductor (UK)...

1. A digital counter comprising:
at least a first counting module and a second counting module, said counting modules being serially coupled and forming a
counting module chain;

each counting module comprising at least a first digital storage cell and a second digital storage cell, each counting module
providing module counting information of at least two bits;

said counting modules being operative, during counting, to respectively change only one bit of said module counting information
between two successive counting state;
wherein the counting modules are coupled such that the start of counting of the second counting module is enabled by the first
counting module when said first counting module has passed through all counting states of said first counting module;wherein the digital storage cells of the first counting module comprise level-triggered latches and wherein the digital storage
cells of the first counting module are triggered by clock signals that are inverted with respect to each other; andwherein the digital storage cells of higher order counting modules comprise edge-triggered flip-flops.

US Pat. No. 9,214,953

GENERALIZED DATA WEIGHTED AVERAGING METHOD FOR EQUALLY WEIGHTED MULTI-BIT D/A ELEMENTS

Dialog Semiconductor (UK)...

1. A binary to thermometer encoder within a DAC circuit comprising:
a row element selector in communication with a multi-bit delta/sigma modulator to receive an oversampled binary coding representing
an amplitude of a sampling of an analog signal and configured for decoding the oversampled binary coding;

a binary to thermometer code conversion array in communication with the row element selector to receive the decoded oversampled
binary coding for selecting one element row of the binary to thermometer code conversion array and configured for retaining
or generating a multi-bit code representing an amplitude to be developed by each of DAC element of the DAC circuit; and

a plurality of column drivers configured such that each column is driver amplifies and conditions the output of each element
of one selected row for transfer through a rotational dynamic element matching circuit to one DAC element;

wherein contents of any row of the binary to thermometer code conversion array is determined as a product of each element
of a signed binary to thermometer code conversion array and a remainder of an non-Euclidian division of the signed numeric
designation of one row of a signed binary to thermometer code conversion array by a number of DAC elements within the DAC
circuit and added to the quotient of the non-Euclidian division, wherein the remainder has the same sign as the numeric designation
of the one row; and

wherein, the binary to thermometer code conversion array is assembled by repetitively executing the formula for determining
the contents of the rows of the binary to thermometer code conversion array.

US Pat. No. 9,563,730

IMPROVING THE ACCURACY OF AN EXPONENTIAL CURRENT DIGITAL-TO-ANALOG CONVERTER (IDAC) USING A BINARY-WEIGHTED MSB

Dialog Semiconductor (UK)...

1. An apparatus for driving light emitting diode (LED) elements comprising:
an error amplifier;
a pulse width modulation comparator electrically connected to an output of said error amplifier;
a DC-DC converter electrically connected to an output of said pulse width modulation comparator and an output pad;
at least one light emitting diode (LED) electrically connected to an input of said error amplifier and to an output of a most
significant bit (MSB) network;

an output buffer having inputs and an output, wherein a first input is connected to the output of the MSB network and a second
input is connected to a drain of a MSB diode element and to a source of a control transistor and the output of the output
buffer is connected to a gate of the control transistor, wherein the output buffer creates an active cascode at an output
of the MSB network, which is also an output stage of an exponential current digital-to-analog converter (IDAC), wherein a
current through the control transistor is proportional to an output current of the MSB network flowing through the at least
one LED;

said control transistor having its drain connected to a drain of a first p-type transistor of a first current mirror, wherein
the gate of the first p-type transistor is connected to the gate of a second p-type transistor, and the first current mirror
is formed of the first and second p-type transistors wherein the sources of both transistors of the first current mirror are
connected to VDD voltage and the drain of the second p-type transistor is connected to an output current of a least significant
bit (LSB) network network;

wherein the IDAC comprises a least significant bit exponential current IDAC (LSBIDAC) comprising the LSB network and a binary
weighted most significant bit exponential current IDAC (MSBIDAC) comprising the MSB network, wherein a desired value of the
IDAC output current is set by a digital word whose first n bits form the most significant part (MSB code) and whose last bits
form the least significant bit part (LSB code), wherein said binary weighted most significant bit (MSBIDAC) is electrically
connected to said cathode of said light emitting diode (LED) and to an input of said error amplifier;
wherein said MSB network comprises:
said MSB diode element having its source connected to a voltage source and its gate to gates of a multitude of MSB current
mirror transistors;

said multitude of the MSB current mirror transistors, having their sources connected to the voltage source and each drain
of the current mirror transistors is connected to a first terminal of an own MSB code switch, wherein the number of the MSB
current mirror transistors corresponds to the number of bits in the MSB part of the digital word and wherein the sizes of
the MSB current mirror transistors are binary weighted in relation to the size of the MSB diode element depending on a relative
position within the MSB part of the digital word according to the equation: size=1/C×2MSB pos-1, wherein the position to find where each MSB current mirror transistor is located in a parallel deployment of transistors
in the MSB network, C corresponds to the size of the MSB diode element and MSBpos corresponds to the position of a MSB current mirror transistor related to a position of a correspondent bit of the MSB code;
and

said MSB code switches, wherein the second terminals of the MSB code switches are all connected to the output of the MSB network,
wherein each switch is closed or open according to the value of a correspondent bit of the MSB code, wherein the correspondent
bit relates to the position of the correspondent MSB current transistor it is connected to;
wherein the output current of the LSB network is mirrored by the first current mirror, furthermore flowing through the control
transistor, which is controlled by the buffer and is then mirrored by the current mirror formed by the MSB diode element and
the MSB current mirror transistors to become, dependent on the status of the switches, the output current of the exponential
current digital-to-analog converter (IDAC) is driving the LED elements.

US Pat. No. 9,559,589

HIGH EFFICIENCY SWITCHING BOOST CONVERTER WITH REDUCED INDUCTOR CURRENT RIPPLE

Dialog Semiconductor (UK)...

1. A voltage or current regulated power converter, wherein
the power converter is configured to derive electrical power at an output voltage Vout at an output of the power converter from electrical power at an input voltage Vin at an input of the power converter;

the output voltage Vout is greater than or equal to the input voltage Vin;

the power converter comprises an inductor (L), a plurality of capacitors (C1, C2, C3, Cout) and a plurality of switches (S1, S2, S3, S4, S5, S6, S7), which are arranged within an input unit and an output unit of the power converter;

the input unit and the output unit are coupled via an intermediate point;
the output unit comprises a first output arrangement;
the input unit comprises a first input arrangement;
the power converter comprises a controller configured to control the plurality of switches such that a commutation cycle of
the power converter comprises a plurality of different operation phases;

the first output arrangement comprises
a second capacitor (C2) and a third capacitor (C3) which are arranged in series, wherein the serial arrangement of the second and third capacitor are arranged in parallel
to a positive and a negative contact of the output of the power converter;

a fifth switch (S5) configured to couple the intermediate point to the positive contact of the output;

a fourth switch (S4) configured to couple the intermediate point to a midpoint between the second capacitor and the third capacitor;

a seventh switch (S7) configured to couple the midpoint to ground; and

a sixth switch (S6) configured to couple the negative contact of the output to ground; and

the first input arrangement comprises
a first capacitor (C1) and the inductor (L);

a first switch (S1) configured to couple a second end of the inductor to the intermediate point; wherein a first end of the inductor is coupled
to a positive contact of the input of the power converter; wherein a first end of the first capacitor is coupled to the intermediate
point;

a second switch (S2) configured to couple the second end of the inductor to the second end of the first capacitor; and

a third switch (S3) configured to couple a second end of the first capacitor to ground; wherein a negative contact of the input of the power
converter is coupled to ground.

US Pat. No. 9,323,265

VOLTAGE REGULATOR OUTPUT OVERVOLTAGE COMPENSATION

Dialog Semiconductor (UK)...

1. A multi-stage amplifier comprising
a pass device configured to source a load current at an output voltage to an output node; wherein the load current is drawn
from a high potential of the multi-stage amplifier;

a first driver circuit configured to control the pass device based on a reference voltage and based on a first feedback voltage
derived from the output voltage;

a sink transistor arranged in series with the pass device and configured to sink a first current from the output node to a
low potential of the multi-stage amplifier; wherein the output node corresponds to a midpoint between the pass device and
the sink transistor;

a bypass transistor configured to couple a sense voltage which is derived from the output voltage to the low potential, to
sink a second current from the output node to the low potential;

a second driver circuit configured to control the sink transistor and the bypass transistor, based on the reference voltage
and based on a second feedback voltage derived from the output voltage; and

a voltage divider arranged between the output node and the low potential and configured to derive the first feedback voltage,
the second feedback voltage and the sense voltage from the output voltage, such that the sense voltage is higher than the
first feedback voltage and such that the first feedback voltage is higher than the second feedback voltage.

US Pat. No. 9,207,696

ROBUST SINK / SOURCE OUTPUT STAGE AND CONTROL CIRCUIT

Dialog Semiconductor (UK)...

1. A multi-stage amplifier comprising
a first amplification stage configured to activate or to deactivate a first output stage in response to an input voltage at
an input node;

the first output stage configured to source a current at an output node of the multi-stage amplifier from a high potential,
when activated;

a second amplification stage configured to activate or to deactivate a second output stage in response to the input voltage
at the input node; and
the second output stage configured to sink a current at the output node of the multi-stage amplifier to a low potential, when
activated; wherein the first amplification stage and the second amplification stage are configured to activate the first output
stage and the second output stage in a mutually exclusive manner, wherein
the first amplification stage comprises
a first current source configured to provide a first current; and
a first input transistor arranged in series with the first current source; wherein a gate of the first input transistor is
coupled to the input node; wherein the first amplification stage is configured to control a voltage level at a first midpoint
between the first current source and the first input transistor, subject to the input voltage at the input node; wherein the
first output stage is coupled to the first midpoint; and

the second amplification stage comprises
a second current source configured to provide a second current; and
a second input transistor arranged in series with the second current source; wherein a gate of the second input transistor
is coupled to the input node; wherein the second amplification stage is configured to control a voltage level at a second
midpoint between the second current source and the second input transistor, subject to the input voltage at the input node;
wherein the second output stage is coupled to the second midpoint.

US Pat. No. 10,129,939

HIGH EFFICIENCY FLICKER ATTENUATOR FOR LIGHTING

DIALOG SEMICONDUCTOR INC....

1. An electronic circuit, comprising:a flicker resisting metal oxide semiconductor field effect transistor (MOSFET) in series with a light emitting diode (LED);
a current sensing circuit adapted to sense a current conducted by the LED; and
a controller coupled to the flicker resisting MOSFET, wherein the controller is configured to:
sense a level of the current conducted through the LED; and
operate the flicker resisting MOSFET in linear mode at a lower level of the current conducted by the LED and to operate the flicker resisting MOSFET in saturation mode at a higher level of the current conducted by the LED, wherein the controller includes a reference voltage generator coupled to the current sensing element and configured to provide a reference voltage that varies inversely with the sensed drain current.

US Pat. No. 10,033,285

SECONDARY CONTROLLER FOR A FLYBACK CONVERTER INCLUDING A SENSE RESISTOR FAULT DETECTION

DIALOG SEMICONDUCTOR INC....

1. A secondary controller for a flyback converter, comprising; a measurement circuit configured to measure a sense resistor voltage across a sense resistor connected in series with a secondary winding in the flyback converter, wherein the measurement circuit comprises an operational amplifier having a first input connected through a first resistor to a first terminal of the sense resistor and having a second input connected through a second resistor to a second terminal of the sense resistor; an analog-to-digital converter; and a matched pair of current-source transistors such that an output of the operational amplifier is coupled to a gate of each current-source transistor and such that a source of a first one of the current-source transistors is coupled to the first input of the operational amplifier and a source of a second one of the current-source transistors is coupled to provide an input to the analog-to-digital converter; and a logic circuit coupled to the measurement circuit and configured to switch off an output power switch for the flyback converter responsive to the sense resistor voltage exceeding a first threshold.

US Pat. No. 9,936,547

MULTI-MODE CONTROL FOR SOLID STATE LIGHTING

Dialog Semiconductor Inc....

1. A light emitting diode (LED) controller providing a regulated current across a LED from an unregulated voltage source, the LED controller comprising:a current controller configured to detect an output current at an output of the LED controller; and
a firing angle detection circuit configured to detect a firing angle of a voltage waveform output by a dimmer switch, the dimmer switch coupled to receive the unregulated voltage source, wherein a firing angle sense input of the firing angle detection circuit is directly connected to both inputs of a diode bridge circuit coupled to the dimmer switch;
the current controller further configured to:
generate a control signal to turn on or turn off a switch, the switch being turned on responsive to the control signal being in a first state and the switch being turned off responsive to the control signal being in a second state, the switch configured to receive the control signal and regulate an amount of current to be supplied to the LED based on the control signal, wherein for each switching cycle:
responsive to the detected firing angle of the voltage waveform output by the dimmer switch being less than a first firing angle threshold, corresponding to a first regulation mode, generate the control signal in the second state when the detected output current at the output of the LED controller satisfies a first output current threshold;
responsive to the detected firing angle of the voltage waveform output by the dimmer switch being greater than a second firing angle threshold, corresponding to a second regulation mode, generate the control signal in the second state when the detected output current at the output of the LED controller satisfies a second output current threshold; and
responsive to the detected firing angle of the voltage waveform output by the dimmer switch being greater than the first threshold and less than the second threshold, corresponding to a third regulation mode, generate the control signal in the second state when the detected output current at the output of the LED controller satisfies the first output current threshold.

US Pat. No. 9,906,151

MINIMUM OFF-TIME ADAPTIVE TO TIMING FAULT CONDITIONS FOR SYNCHRONOUS RECTIFIER CONTROL

DIALOG SEMICONDUCTOR INC....

9. A method comprising:
switching off a synchronous rectifier switch coupled to a second winding of a transformer following a first on-time period
responsive to a switch voltage across the synchronous rectifier switch rising above an off-time threshold voltage to cause
the voltage to begin cycling through resonant oscillations;

switching on the synchronous rectifier switch for a second on-time period responsive to one of the resonant oscillations causing
the switch voltage to drop below an on-time threshold voltage;

detecting a fault condition responsive to the second on-time period being less than or equal to a sum of the minimum on-time
period and a guard band period; and

increasing a minimum off-time period for the synchronous rectifier switch responsive to the detection of the fault condition
to prevent the switch voltage from again falling below the on-time threshold voltage responsive to the resonant oscillations.

US Pat. No. 9,501,605

AUTO-CONSTRAINT CHIP-LEVEL ROUTING

Dialog Semiconductor (UK)...

1. A method of routing signal lines of an integrated circuit, IC, performed by a computer, wherein the IC comprises a plurality
of circuit topologies and a plurality of signal lines connecting the circuit topologies, the method comprising steps of:
receiving a first representation of the IC, the first representation of the IC relating to a netlist or a schematic database;
comparing, based on the first representation, the circuit topologies of the IC against a set of reference circuit topologies;
classifying signals propagating along respective signal lines of the IC into a plurality of categories based on a result of
the comparison; and

routing the signal lines of the IC in accordance with the categories of their respective signals, thereby generating a second
representation of the IC, the second representation of the IC relating to a layout for the IC that includes a relative arrangement
of the signal lines,

wherein the categories are representative of characteristics of the signals propagating along respective signal lines with
regard to mutual interference between signals.

US Pat. No. 10,103,636

SINGLE-STAGE POWER CONVERTER WITH POWER FACTOR CORRECTION

DIALOG SEMICONDUCTOR INC....

1. A method for a circuit with power factor correction (PFC), the method comprising:providing, by a combination of a resistor and a capacitor within a single-stage power converter, a delay in phase between a peak current command and a rectified input voltage such that a phase of a transformer current intentionally lags behind a phase of the rectified input voltage to maintain a power factor (PF) level and a total harmonic distortion (THD) level for the single-stage power converter.

US Pat. No. 10,034,336

CONTROLLING OUTPUT VOLTAGE TO ACHIEVE ULTRA-LOW STANDBY POWER IN DIM-TO-OFF LED APPLICATIONS

DIALOG SEMICONDUCTOR (UK)...

1. An electronic device, comprising:an integrated circuit (IC) configured to regulate an output voltage for powering a light emitting diode (LED);
a first transistor configured to be switched on or off by the IC to inductively couple or decouple a main power supply bus voltage from a primary winding of a transformer to a secondary winding of the transformer connectable to the LED; and
a second transistor coupled between the IC and the main power supply bus voltage, and configured to be switched on or off by the IC to selectively provide an IC power supply input voltage to the IC,
wherein the second transistor is configured to be switched on in response to:
the IC decreasing the output voltage to less than about one-third of a nominal operating voltage of the LED, and
detecting that the IC power supply input voltage is less than a first threshold voltage.

US Pat. No. 9,958,487

METHOD AND APPARATUS FOR POWERING AN ELECTRONIC DEVICE

Dialog Semiconductor (UK)...

1. An apparatus for monitoring a process of powering an electronic device through a cable assembly, the cable assembly comprising a cable connected between a power supply and said electronic device, the apparatus comprising:a synchronization signal generator configured to generate a synchronization signal at a predetermined frequency;
a test signal generator configured to generate, based on the synchronization signal, a test signal and to apply the test signal to one end of the cable;
a filter unit configured to detect a response signal at the one end of the cable, the response signal resulting from applying the test signal to the cable assembly; andan impedance estimation unit configured to determine, based on the response signal and based on the synchronization signal, a first quantity indicative of a real part of an impedance of the cable assembly and a second quantity indicative of an imaginary part of the impedance of the cable assembly, wherein the impedance estimation unit further comprisesa first switching unit configured to apply, triggered by the synchronization signal, the response signal to an input of a first low pass filter; and
a second switching unit configured to apply, triggered by an inverted version of the synchronization signal, the response signal to an input of a second low pass filter.

US Pat. No. 9,608,582

METHOD FOR AN ADAPTIVE TRANSCONDUCTANCE CELL UTILIZING ARITHMETIC OPERATIONS

Dialog Semiconductor (UK)...

1. A operational transconductance amplifier, comprising:
a) a first and second voltage controlled current source circuit configured to provide an output current dependent on the product
of the output current of the first voltage controlled circuit, and the quotient of the input voltage of the second voltage
controlled current source circuit and the input voltage of the first voltage controlled current source circuit;

b) each of said voltage controlled current source circuits having an adaptive transconductance cell connected to a bias, set
by a feedback loop.

US Pat. No. 9,594,391

HIGH-VOLTAGE TO LOW-VOLTAGE LOW DROPOUT REGULATOR WITH SELF CONTAINED VOLTAGE REFERENCE

Dialog Semiconductor (UK)...

1. A low-dropout (LDO) regulator circuit providing a regulated, temperature compensated output voltage down from a high-voltage
supply comprising:
an output branch, comprising: a port for the regulated output voltage, a voltage-divider resistor network connected between
said port for the regulated output voltage and ground, wherein the resistor network is configured to provide a voltage (VBE1) which is connected to a base of a first transistor, wherein a current through the output branch is provided by an operational
amplifier;

an emulated proportional to absolute temperature (PTAT) circuit configured to generate a temperature-independent current through
a first transistor which is used as a reference current, wherein the PTAT circuit comprises;

a PTAT resistor having its first terminal connected to a node of the output branch, which is between a first and the second
resistor of the voltage divider resistor network and its second terminal connected to a collector and a base of a second transistor;
and

said second transistor having its base connected to a base of a third transistor and its emitter connected to ground voltage,
wherein the reference current through the second transistor is mirrored in a first current mirror by a ratio of N:1 to the
third transistor, wherein current mirror factor N is an integer number higher than 1;

said operational amplifier configured to inject current into the output branch; and
a second current mirror mirroring the current through the third transistor by a first p-channel MOSFET using a current mirror
ratio of 1:N, wherein N is the same current mirror factor as used by the first current mirror, to a second p-channel MOSFET,
wherein the current through the second MOSFET is flowing through the first transistor to ground and wherein a voltage of a
node between the second MOSFET and the first transistor is a regulation voltage of the operational amplifier; wherein the
first and the second current mirrors are configured to compare the reference current through the second transistor with the
current through the first transistor and a comparison result raises or lowers the voltage (VCTL) that regulates the operational
amplifier, wherein the voltage (VCTL) that regulates the operational amplifier is ground referenced for better PSSR and noise
immunity.

US Pat. No. 10,003,269

SMART GROUPING CONTROL METHOD FOR POWER CONVERTER SWITCHING NOISE MANAGEMENT

DIALOG SEMICONDUCTOR INC....

1. A switching power converter controller, comprising:a loop filter for filtering an error signal to produce a control voltage;
a loop control logic circuit configured to quantize a first function of a difference between the control voltage and a threshold voltage to determine an integer number of pulses for each pulse in a pulse train responsive to the control voltage being within a group mode control voltage range for a group pulse mode of operation and to determine a group period for the pulse train that is proportional to a product of a default group period and a second function of the difference, wherein the loop control logic circuit is further configured to command a power switch to cycle according to the integer number of pulses within the group period responsive to the control voltage being within the group mode control voltage range, wherein the group mode control voltage range is divided into a plurality of equal control voltage steps, and wherein the first function of the difference equals a ratio of the difference to the equal control voltage step, and wherein the loop control logic circuit is configured to quantize the first function by taking a nearest integer value of the first function.

US Pat. No. 10,020,743

SINGLE STAGE SWITCHING POWER CONVERTER WITH IMPROVED PRIMARY ONLY FEEDBACK

DIALOG SEMICONDUCTOR INC....

1. A method of controlling a switching power converter, comprising:rectifying an AC mains voltage to produce a rectified sinusoidal voltage at an input of a primary winding of a transformer while cycling a power switch connected to the primary winding, wherein cycling the power switch comprises cycling the power switch through a series of power switch cycles, wherein each power switch cycle includes an on time for the power switch and an off time for the power switch;
during the on time for each power switch cycle, determining whether a current through the power switch is greater than a threshold value to classify each power switch cycle into either a trustable power switch cycle in which the current through the power switch is greater than the threshold value or into a non-trustable power switch cycle in which the current through the power switch cycle is not greater than the threshold value;
during the off time for each trustable power switch cycle, sensing a primary-only feedback voltage using primary-only feedback to regulate the cycling of the power switch; and during the off time for each non-trustable power switch cycle, interpolating from the primary-only feedback voltage to regulate the cycling of the power switch.

US Pat. No. 9,966,859

MOSFET DRIVER WITH REDUCED POWER CONSUMPTION

Dialog Semiconductor Inc....

13. A method for operating a flyback switching power converter, comprising:configuring the power converter to operate in a low power mode;
generating a first driver pulse voltage configured to discharge an output capacitance of a switch of the power converter by a first amount and to provide a first amount of output power to a load coupled to the power converter, the first amount of output power exceeding a minimum power threshold required by the load;
after generating the first driver pulse voltage, generating a second driver pulse voltage smaller than the first driver pulse voltage and configured to discharge the output capacitance of the switch by a second amount less than the first amount and to provide a second amount of output power to the load, the second amount of output power less than the first amount of output power;
after generating the second driver pulse voltage and responsive to a determination that the second amount of output power does not exceed the minimum power threshold, generating a third driver pulse voltage greater than the second driver pulse voltage and configured to discharge the output capacitance of the switch by a third amount greater than the second amount and to provide a third amount of output power to the load, the third amount of output power greater than the second amount of output power;
responsive to a determination that the third amount of output power exceeds the minimum power threshold, storing the third driver pulse voltage for use during the remainder of the low power mode; and
responsive to a determination that the third amount of output power does not exceed the minimum power threshold, configuring the power converter to stop operation in the low power mode.

US Pat. No. 9,729,075

HIGH EFFICIENCY DC-TO-DC CONVERTER WITH ADAPTIVE OUTPUT STAGE

Dialog Semiconductor (UK)...

1. A power converter, comprising:
an adaptive output with a number of selected stages;
a first adaptive transconductance block whose inputs are electrically coupled to a sensor whose outputs are sense voltage,
average load current and power supply voltage configured to evaluate resistive power terms;

multiplier block configured to multiply a capacitor current by the number of selected stages to generate capacitive power
terms; and

a comparator configured to compare said resistive power terms and said capacitive power terms for determining the number of
selected stages of said adaptive output.

US Pat. No. 9,755,517

MULTI-THRESHOLD PANIC COMPARATORS FOR MULTI-PHASE BUCK CONVERTER PHASE SHEDDING CONTROL

Dialog Semiconductor (UK)...

1. A control circuit included within a multi-phase switched-mode converter and configured for adjusting operational signals
for operating a master power stage and a plurality of slave power stages of the multi-phase switched-mode converter to dynamically
respond to transient changes in load current, comprising:
a plurality of panic comparators, each panic comparator having an input terminal connected to receive a feedback voltage indicative
of an output voltage of the multi-phase switched-mode converter;

a plurality of panic reference voltage sources, each panic reference voltage source is connected to a reference terminal of
one panic comparator to provide a panic reference voltage to the one panic comparator, wherein each of the plurality of panic
comparators is configured to compare the feedback voltage with an associated panic reference voltages to generate one panic
indicator signal of a plurality of panic indicator signals at an output terminal of each of the panic comparators;

a pulse frequency modulation comparator connected for receiving the feedback voltage and configured for generating a discontinuous
control signal;

a pulse frequency modulation reference voltage source providing a pulse frequency modulation reference voltage to the pulse
frequency modulation comparator for comparison with the feedback voltage for determining if the feedback voltage is less than
or greater than the pulse frequency modulation reference voltage; and

a phase controller configured for activating and deactivating a master power stage and a plurality of slave power stages of
the multi-phase switched-mode converter, the phase controller comprising:

a pulse frequency modulation controller in communication with the pulse frequency modulation comparator for receiving the
discontinuous control signal and in communication with at least one of the plurality of panic comparators for receiving at
least one of the plurality of panic indicator signals and configured for providing conduction mode control signals to the
master power stage for operating in a discontinuous conduction mode of operation, wherein when the feedback voltage is greater
than a voltage level of the pulse frequency modulation reference voltage, the multi-phase switched-mode converter operates
in the discontinuous mode of operation and wherein when the feedback voltage is less than at least one of the panic reference
voltage levels, the multi-phase switched-mode converter operates in the continuous mode of operation;

a panic controller connected to each of the output terminals of the plurality of panic comparators to receive the plurality
of panic indicator signals from the plurality of panic comparators signifying that the feedback voltage is less than the panic
reference voltage of a second of the plurality reference voltage sources, wherein the panic controller determines which of
the slave power stages are to be activated to match the transient change to the load current.

US Pat. No. 9,484,899

DEBOUNCE CIRCUIT WITH DYNAMIC TIME BASE ADJUSTMENT FOR A DIGITAL SYSTEM

Dialog Semiconductor (UK)...

1. A debounce circuit for eliminating noise, glitches, or transient signal variations resulting from mechanical bounce in
electronic or mechanical devices occurring at an initiation of a change of state of at least one analog signals such that
the debounce circuit supports a dynamic debounce period alteration and time base variation without loss of the current debounce
state, the debounce circuit comprising:
a physical counter configured for being disposed within a virtual counter defined to have a number of bits sufficient to generate
a filter time for filtering the noise, glitches, or transient signal variations resulting from mechanical bounce occurring
at an initiation of a change of state of the at least one analog input signal from a source device;

a debounce clock controller configured for providing a fundamental clock to the physical counter, at least one time base signal
indicating a location within the virtual counter that the physical counter is situated within the virtual counter for generating
a debounce time to eliminate the noise, glitches, or transient signal variations resulting from mechanical bounce based on
a required debounce time of the at least one analog signal, at least one timer strobe configured to be a submultiple of and
aligned with the fundamental clock for incrementing the physical counter at the indicated location within the virtual counter
such that the least significant binary digit of the physical counter is located at the virtual location in the virtual counter
where two raised to the virtual location of the beginning binary digit of physical counter is the submultiple of the clock
determining the strobe time, and a debounce threshold indicating a count of the virtual counter at which the debounce time
has elapsed; and

a virtual debounce controller in communication with the physical counter and the debounce controller, configured for defining
the location of the physical counter within the virtual counter as defined by the at least one time base signal, and determining
when the count of the virtual counter has exceeded the debounce threshold.

US Pat. No. 9,917,519

FREQUENCY HOPPING FOR REDUCING SWITCHING NOISE IN A SWITCHING POWER CONVERTER

DIALOG SEMICONDUCTOR INC....

1. A switching power converter comprising:
a power switch;
a controller configured to cycle the power switch at a first switching frequency in a first pulse-width modulation mode to
produce a first peak current through the power switch responsive to an amplitude of a control signal being within a first
output power range extending from a first minimum power to a first maximum power and to cycle the power switch at a second
switching frequency in a second pulse-width modulation mode to produce a second peak current through the power switch responsive
to the amplitude of the control signal being within a second output power range extending from the first maximum power to
a second maximum power, wherein a first ratio of the first peak current to the second peak current at a boundary between the
first output power range and the second output power range equals a square root of a second ratio of the second switching
frequency to the first switching frequency.

US Pat. No. 9,660,703

ELECTRONIC CIRCUIT AND SYSTEM FOR WIRELESS CHARGING

DIALOG SEMICONDUCTOR (UK)...

1. An electronic circuit for a portable battery-powered electronic device, the electronic circuit being operable in a first
mode as an actuator and in a second mode as a wireless charging receiver;
wherein the electronic circuit comprises:
an electromechanical actuator comprising an inductor;
a capacitance selectively connectable to the inductor, at least in the second mode, to form therewith a resonant circuit for
inductively receiving an electromagnetic wireless charging signal; and

a multi-mode switching circuitry comprising one or more switching devices for switching the electronic circuit between its
different modes, at least one of the switching devices being configurable as a rectifying device, wherein:

in the first mode, the switching circuitry is configured to connect the actuator to an electrical power input of the electronic
circuit; and

in the second mode, the switching circuitry is configured as a rectifier circuit for rectifying a voltage induced in the resonant
circuit in response to a received electromagnetic wireless charging signal and for providing the rectified voltage at a power
output of the electronic circuit as a charging voltage for a battery of the portable electronic device, wherein said at least
one configurable switching device is configured as a rectifying device of the rectifier circuit.

US Pat. No. 9,651,960

CONSTANT OUTPUT AMPLIFIER

Dialog Semiconductor (UK)...

1. A multi-stage amplifier comprising
a first amplification stage configured to activate or to deactivate a first output stage in response to an input voltage at
an input node;

the first output stage configured to source a current at an output node of the multi-stage amplifier from a high potential,
when activated;

a second amplification stage configured to activate or to deactivate a second output stage in response to the input voltage
at the input node; and

the second output stage configured to sink a current at the output node of the multi-stage amplifier to a low potential, when
activated; wherein the first amplification stage and the second amplification stage are configured to activate the first output
stage and the second output stage in a mutually exclusive manner, wherein

the first output stage comprises
a first control transistor having a gate which is coupled to the first amplification stage, and being configured to vary a
first control current through the first control transistor, subject to a voltage level at the gate of the first control transistor;
and

a first output amplifier configured to source an amplified version of the first control current to the output node; and
the second output stage comprises
a second control transistor having a gate which is coupled to the second amplification stage, and being configured to vary
a second control current through the second control transistor, subject to a voltage level at the gate of the second control
transistor; and

a second output amplifier configured to sink an amplified version of the second control current at the output node.

US Pat. No. 9,622,300

RESONANCE CONVERTER FOR DRIVING MULTIPLE AC LED STRINGS

Dialog Semiconductor (UK)...

1. An SSL assembly comprising
an alternating current, referred to as AC, solid state lighting, referred to as SSL, unit; wherein the AC SSL unit comprises
at least two SSL devices which are arranged in an anti-parallel manner with respect to one another; and

a driver circuit which comprises a resonant circuit that is configured to adapt an input AC drive voltage at an input of the
resonant circuit into an output AC drive voltage; wherein the output AC drive voltage is applied to the AC SSL unit; wherein

the SSL assembly comprises a plurality of AC SSL units which are arranged in parallel with respect to one another;
the driver circuit comprises a corresponding plurality of resonant circuits; wherein each resonant circuit of the plurality
of resonant circuits for a corresponding AC SSL unit of the plurality of AC SSL units exhibits a resonance frequency which
is dependent on an on-voltage of the corresponding AC SSL unit; and

each of the plurality of resonant circuits is configured to adapt the input AC drive voltage at the input of the respective
resonant circuit into an output AC drive voltage which is applied to the respective AC SSL unit.

US Pat. No. 9,310,824

STATIC OFFSET REDUCTION IN A CURRENT CONVEYOR

1. A current sensing circuit configured to provide an indication of a load current provided to a load, the current sensing
circuit comprising:
a first resistance having a first end that is coupled to an input node;
an input current source transistor configured to provide a bias current;
an input gain transistor arranged in series with the input current source transistor such that the serial input gain transistor
is traversed by the bias current, wherein a voltage level at the input node corresponds to the voltage drop across the input
current source transistor and the input gain transistor;

an intermediate gain transistor forming a first current mirror with the input gain transistor;
an intermediate current source transistor arranged in series with the intermediate gain transistor such that a current through
the intermediate current source transistor corresponds to a current through the intermediate gain transistor;

an output current source transistor forming a second current mirror with the intermediate current source transistor; and
an output gain transistor arranged in series with the output current source transistor such that a current through the output
current source transistor corresponds to a current through the output gain transistor, and forming a third current mirror
with the input gain transistor, wherein a voltage level at an output node corresponds to the voltage drop across the output
current source transistor and the output gain transistor; wherein

the first resistance provides a load current to a load arranged in parallel to the serial input gain transistor and input
current source transistor;

the current sensing circuit comprises an output transistor arranged in parallel to the serial output gain transistor and output
current source transistor; and

the current through the output transistor provides an indication of the load current.

US Pat. No. 9,705,399

ADAPTIVE THRESHOLD OF A ZERO CROSSING COMPARATOR

Dialog Semiconductor (UK)...

1. A buck converter device comprising:
a high-side switch device with a first parasitic bipolar junction transistor configured to provide a first sense signal depending
from a current flowing through the first parasitic bipolar junction transistor to a zero-cross comparator;

a low-side switch device with a second parasitic bipolar junction transistor configured to provide a second sense signal depending
from current flowing through the second parasitic bipolar junction transistor to the zero-cross comparator;

a sense capacitive element, wherein a first terminal of the sense capacitive element is connected to ground and a second terminal
of the sense capacitive element is connected to the zero-cross comparator, directly connected to a collector of the first
parasitic bipolar junction transistor and directly connected to a collector of the second parasitic bipolar junction transistor,
wherein the sense capacitive element is configured to provide an offset adjustment from said first and second sense signals
combined to the zero-cross comparator; and

the zero-cross comparator with an adaptive threshold configured with the offset adjustment provided from said first sense
signal and said second sense signal combined via said sense capacitive element.

US Pat. No. 9,705,559

METHOD AND APPARATUS FOR POWERING A PORTABLE DEVICE

Dialog Semiconductor (UK)...

13. An apparatus for monitoring a process of powering a portable device through a cable connected between a power supply and
said portable device, the apparatus comprising:
a current sink for applying a time-dependent current variation to one end of the cable in accordance with a spreading sequence;
voltage detecting means for detecting a time-dependent voltage variation at the one end of the cable, the time dependent voltage
variation resulting from said applying of the time-dependent current variation; and

computing means for determining a quantity indicative of an impedance of the cable assembly based on the time-dependent voltage
variation and the spreading sequence,

wherein the computing means comprises a multiplicator adapted to multiply the time-dependent voltage variation with the spreading
sequence, a numerical integrator adapted to time-average the result of said multiplication, and an impedance calculator adapted
to calculate the quantity indicative of the impedance of the cable assembly based on the time average.

US Pat. No. 9,232,582

DRIVER CIRCUITS FOR SOLID STATE LIGHT BULB ASSEMBLIES

1. A driver circuit for a solid state light source, the driver circuit comprising
a first power converter stage configured to convert an input voltage into an intermediate voltage;
a second power converter stage configured to convert the intermediate voltage into a drive voltage for the light source; and
a controller comprising
a first control unit configured to generate a first control signal for the first power converter stage;
a second control unit configured to generate a second control signal for the second power converter stage; and
a state control unit configured to determine a target state of the light source; wherein the first and second control units
are configured to receive information indicative of the target state; and wherein the first and second control units are configured
to generate the first and second control signals based on the information indicative of the target state;

wherein the first and second control units are configured to exchange control data indicative of the first and second control
signals, respectively.

US Pat. No. 9,693,417

LED MAINS VOLTAGE MEASUREMENT USING A CURRENT MIRROR

Dialog Semiconductor (UK)...

1. A measurement circuit configured to provide a sensed input voltage indicative of an input voltage, wherein the measurement
circuit comprises
a first resistor which is configured to be coupled at a first side to the input voltage;
current mirror circuitry coupled at an input to a second side of the first resistor, which is opposite to the first side of
the first resistor, and configured to translate an input current at the input of the current mirror circuitry into an output
current at an output of the current mirror circuitry, such that the output current is proportional to the input current by
a current mirror ratio;

a second resistor coupled to the output of the current mirror circuitry and configured to provide the sensed input voltage,
when the input voltage is coupled to the first side of the first resistor; and

a source follower circuit arranged between the second side of the first resistor and the input of the current mirror circuitry;
wherein the source follower circuit is configured to set a voltage level of the second side of the first resistor to a pre-determined
reference voltage.

US Pat. No. 9,672,878

MEMORY CIRCUIT

Dialog Semiconductor (UK)...

1. A memory circuit comprising
an input to receive a logic signal, and an output to output an output logic value; and
a plurality of logic elements, the plurality of logic elements being arranged such that, upon powering the memory circuit,
the output logic value has a greater probability of settling to a first logic value than a second logic value.

US Pat. No. 10,054,970

ADAPTIVE GAIN CONTROL FOR VOLTAGE REGULATORS

Dialog Semiconductor (UK)...

1. A voltage regulator configured to provide an output current at an output voltage at an output node, based on an input voltage at an input node, wherein the voltage regulator comprises,an output amplification stage comprising
a pass transistor for deriving the output current at the output node from the input voltage at the input node; and
a driver stage configured to set a gate voltage at a gate of the pass transistor based on a drive voltage;
wherein a gain of the output amplification stage is adjustable;
a differential amplification unit configured to determine the drive voltage in dependence of the output voltage and in dependence of a reference voltage; and
a gain control circuit configured to adjust the gain of the output amplification stage in dependence of the output current; wherein the gain control circuit is configured to adjust the gain by a gain delta if the output current changes by a current delta; and wherein a ratio of the gain delta and the current delta is equal to or smaller than a pre-determined transition threshold.

US Pat. No. 9,606,559

MULTI-PHASE SWITCHING CONVERTER WITH PHASE SHEDDING

Dialog Semiconductor (UK)...

1. A multi-phase switched-mode converter circuit configured for dropping or shedding and adding phases to dynamically maintain
an operating load while continuing to provide efficient operation and avoid any transient changes to an output voltage multi-phase
switched-mode converter circuit, the multi-phase switched-mode converter circuit comprising:
a control circuit configured to adjust operational signals of a master power stage and a plurality of slave power stages of
the multi-phase switched-mode converter circuit, the control circuit comprising:

a phase shedding control circuit configured to receive a shed threshold signal from a phase threshold comparator indicating
that a total output current magnitude has fallen below a total current magnitude threshold level such that the multi-phase
switched-mode power converter circuit is no longer operating efficiently and configured to generate a plurality of phase shedding
signals and a plurality of slave phase target signals, wherein each of the plurality of phase shedding signal is transferred
to one of the plurality of slave power stages; and

a plurality of phase control and feedback sections where in a master phase control and feedback section is connected to the
master power stage and each remaining phase control and feedback section is connected to one of the plurality of slave power
stages, wherein each of the plurality of phase control and feedback sections comprises:

a slave phase shedding switch comprising:
a common switching pole in communication with a current share amplifier of one of the slave power stages,
a first select pole connected to receive a phase target current level from a phase current sense circuit within the master
power phase,

a second select pole connected to receive a phase zero target current level from a target current voltage source, and
a control terminal connected to receive one of the slave phase target signals from the phase shedding control circuit such
that the slave phase shedding switch transfers a connection between the first pole and the common pole when the plurality
of slave power stages are operating to a connection between the second pole and the common pole to apply the phase zero target
current level to a current sense amplifier within each phase control and feedback section to bring an output current of each
of the plurality of slave power stages to approximately a zero level.

US Pat. No. 9,596,541

POST-FILTER FOR HANDLING RESONANCE-INDUCED ECHO COMPONENTS

1. An echo suppression unit for an electronic device comprising a loudspeaker and a microphone; wherein the microphone is
configured to capture a transmit signal; wherein the transmit signal comprises an echo of a receive signal rendered by the
loudspeaker; wherein the electronic device exhibits N different distorting frequencies, with N>1; wherein the rendering of
a receive signal comprising at least one of the N distorting frequencies triggers resonances of the electronic device; wherein
the echo suppression unit is configured to apply a first analysis filter of N pre-determined analysis filters to the receive
signal to yield a first analysis filtered signal: wherein the N analysis filters are configured to isolate frequency components
of the receive signal at the N distorting frequencies, respectively; wherein the first analysis filters are configured to
isolate a first frequency component of the receive signal at a first distorting frequency of the N distorting frequencies;
determine, based on the first analysis filtered signal, whether the receive signal comprises a first frequency component at
the first distorting frequency causing the echo of the receive signal to comprise a distortion component; wherein the distortion
component comprises one or more frequencies which are not comprised within the first frequency component; and apply a first
post-filter of N pre-determined post-filters to the transmit signal, if it is determined that the receive signal comprises
the first frequency component; wherein the first post-filter is configured to selectively attenuate the distortion component
triggered by the first distorting frequency; wherein the N post-filters are dependent on the N distorting frequencies, respectively.

US Pat. No. 9,285,397

TEMPERATURE AND SUPPLY VOLTAGE INDEPENDENT DC-DC CURRENT SENSING

1. A current sensing circuit configured to provide an indication of a load current through a pass device, wherein the current
sensing circuit comprises
a sensing replica of the pass device;
a sensing resistor arranged in series with the sensing replica, such that a voltage drop at the sensing resistor provides
an indication of the load current through the pass device; wherein the voltage drop at the sensing resistor is dependent on
an on-resistance of the pass device; and

a transformation circuit configured to transform the voltage drop at the sensing resistor into an output current, such that
the output current is indicative of the voltage drop at the sensing resistor divided by a compensation resistance of a compensation
circuit; wherein the compensation resistance exhibits a dependency on the on-resistance of the pass device which corresponds
to the dependency on the on-resistance of the pass device of the voltage drop at the sensing resistor.

US Pat. No. 9,277,609

BACK-UP CAPACITOR

1. A driver circuit configured to provide, at an output of the driver circuit, electrical energy at a drive voltage, derived
from electrical energy at an input voltage at an input of the driver circuit, the driver circuit comprising:
a power converter configured to convert the electrical energy at the input voltage into the electrical energy at the drive
voltage, wherein the power converter comprises a power switch;

a controller configured to control the power switch such that the power converter provides the electrical energy at the drive
voltage;

a supply voltage capacitor coupled to the controller and configured to provide a supply voltage to the controller;
a start up resistor coupled to the input of the driver circuit and configured to charge the supply voltage capacitor when
coupled to the supply voltage capacitor, wherein the start up resistor is coupled to the supply voltage capacitor during a
start up phase of the driver circuit;

a back-up capacitor coupled to the output of the driver circuit and arranged to receive electrical energy from the output
of the driver circuit; and

a back-up switch configured to couple the back-up capacitor with the supply voltage capacitor if a voltage at the back-up
capacitor exceeds the supply voltage by a forward voltage threshold, and configured to decouple the back-up capacitor from
the supply voltage capacitor if the supply voltage exceeds the voltage at the back-up capacitor by a reverse voltage threshold.

US Pat. No. 9,104,218

CLEAN STARTUP AND POWER SAVING IN PULSED ENABLING OF LDO

1. A method to achieve a clean start-up process and power saving of pulsed enabled electronic devices having an output capacitor
and components requiring biasing during normal operating conditions, comprising the following steps:
(1) providing a pulsed enabled electronic device having an output capacitor and components requiring biasing; and
(2) biasing internal nodes of the device from the output capacitor during power down of the electronic device; and
(3) using the energy stored in the output capacitor for the next process of the electronic device.

US Pat. No. 10,044,277

REGULATION OF THE POWER SUPPLY VOLTAGE FOR A FLYBACK CONVERTER CONTROLLER

DIALOG SEMICONDUCTOR INC....

11. A method, comprising:cycling a power switch to provide power to a load during an active period, wherein each cycle of the power switch produces a reflected voltage pulse from an output voltage at a secondary side of a transformer for a switching power converter;
sampling the reflected voltage pulses at a transformer reset time when a secondary winding current for the transformer ramps to zero to sample the output voltage;
entering a dormant period in which the power switch is not cycled in response to the sampling of the reflected voltage pulse indicating that no load is being applied to the switching power converter;
rectifying and filtering each reflected voltage pulse to produce a controller power supply voltage for a controller controlling the cycling of the power switch, the controller receiving inputs from only a primary side of a switching power converter; and
during the dormant period in which the power switch was not being cycled, triggering a controller-power-supply-voltage cycle of the power switch responsive to the controller power supply voltage falling below a threshold voltage.

US Pat. No. 9,454,164

METHOD AND APPARATUS FOR LIMITING STARTUP INRUSH CURRENT FOR LOW DROPOUT REGULATOR

1. A low dropout device with limiting startup inrush current, the device comprising:
an error amplifier;
a pass transistor coupled to said error amplifier;
a feedback network electrically connected to said pass transistor wherein an output of said feedback network is electrically
coupled to an input of said error amplifier;

a current limit control network whose current limit control network input is electrically connected to said pass transistor
and an electrical output of said error amplifier and whose current limit control network output provides a current limit;

a Bypass mode current control limit comparator, wherein an input of said Bypass mode current control limit comparator comprises
a supply voltage, and an output of said pass transistor;

a Low Dropout (LDO) mode current control limit comparator, wherein an input of said Low Dropout (LDO) mode current limit comparator
comprises a reference voltage and the output of said feedback network; and

a Low Dropout (LDO) mode/Bypass mode select network whose inputs are the output of said Low Dropout (LDO) mode current control
limit comparator, and said Bypass mode current control limit comparator, and whose Low Dropout (LDO) mode/Bypass mode select
network output is coupled to said current limit control network to reduce the current limit at startup of the low dropout
device.

US Pat. No. 9,323,266

METHOD AND SYSTEM FOR GAIN BOOSTING IN LINEAR REGULATORS

1. A linear regulator configured to derive an output voltage from an input voltage, the linear regulator comprising,
an amplifier configured to derive an amplifier output signal from an amplifier input signal;
a pass device configured to convert the amplifier output signal into the output voltage;
a positive feedback loop configured to determine a positive feedback signal from the amplifier output signal, using a positive
feedback gain ?;

a negative feedback loop configured to determine a negative feedback signal from the output voltage, using a negative feedback
gain ?; and

a combining unit configured to determine the amplifier input signal from the input voltage, from the positive feedback signal
and from the negative feedback voltage; wherein a transfer function of the linear regulator exhibits a first and a second
pole at a first frequency wp1 and at a second frequency wp2, respectively,
wherein
the differential amplifier comprises a differential pair comprising a first input transistor and a second input transistor;
the first and second input transistors are arranged in series with a first and second load diode, respectively;
the positive feedback loop comprises a first mirror transistor forming a current mirror with the first load diode and a second
mirror transistor forming a current mirror with the second load diode;

the first mirror transistor is arranged in series with the second input transistor; and
the second mirror transistor is arranged in series with the first input transistor.

US Pat. No. 9,083,281

DC BLOCKER FOR A HIGH GAIN COMPLEX CIRCUIT

1. An amplifying circuit, comprising
an analog amplifying circuit having an analog input for receiving an analog input signal to be amplified and an analog output
for outputting an amplified analog signal, wherein the amplifying circuit comprises an implementation of a complex transfer
function; and

a feedback circuit having a feedback circuit input and a feedback circuit output, wherein the feedback circuit comprises an
implementation of an inverse transfer function that is an estimation of a complex inverse of at least a DC component of the
complex transfer function of the analog amplifying circuit; wherein

the feedback circuit input is arranged for receiving a signal that is based on the amplified analog signal of the analog amplifying
circuit; and

the analog circuit is arranged for receiving a bias signal that is based on the feedback circuit output.

US Pat. No. 10,090,671

SHORT CIRCUIT PROTECTION FOR DATA INTERFACE CHARGING

DIALOG SEMICONDUCTOR INC....

12. A power converter, comprising:an output capacitor having an output node for storing a power supply voltage;
a power bus switch transistor coupled between the output node and a power bus terminal for a power bus, the power bus being contained within a data cable for charging a device; and
a controller configured to softly switch on the power bus switch transistor at a beginning of a soft-start period responsive to a detection that the device has connected to the data cable for receiving power over the power bus, wherein the power bus switch transistor has a greater resistance when softly switched on than when fully switched on, the controller further configured to switch off the power bus switch transistor during the soft-start period responsive to a determination that the power supply voltage has dropped below a short circuit threshold voltage.

US Pat. No. 10,075,063

DUAL STAGE VCC CHARGING FOR SWITCHED MODE POWER SUPPLY

DIALOG SEMICONDUCTOR INC....

1. A startup circuit in a switching power converter, comprising:a high impedance charging path including a high impedance resistor;
a low impedance charging path including a low impedance resistor, wherein an impedance of the high impedance resistor is greater than an impedance of the low impedance resistor;
an impedance switch transistor configured to couple the high impedance charging path to a power supply capacitor while the impedance switch transistor is off and to couple the low impedance charging path to the power supply capacitor while the impedance switch transistor is on; and
a switch controller configured to switch the impedance switch transistor off while a power supply voltage stored on the power supply capacitor is less than a threshold voltage and to switch the impedance switch transistor on while the power supply voltage is greater than the threshold voltage.

US Pat. No. 9,671,805

LINEAR VOLTAGE REGULATOR UTILIZING A LARGE RANGE OF BYPASS-CAPACITANCE

Dialog Semiconductor (UK)...

1. An amplifier comprising
a first amplification stage configured to provide an intermediate voltage, based on an outer feedback voltage and based on
a reference voltage;

an output stage configured to provide a load current at an output voltage based on the intermediate voltage; and
an outer feedback circuit configured to derive the outer feedback voltage from the output voltage;wherein the output stage comprises a buffer configured to provide a drive voltage based on the intermediate voltage and based
on an inner feedback voltage derived from the output voltage; and wherein the buffer comprises a pass device configured to
provide the load current at the output voltage based on the drive voltage, and wherein
the first amplification stage comprises a differential amplification stage;
the differential amplification stage comprises a differential transistor pair, and is configured to provide the intermediate
voltage at a stage output node of the
differential transistor pair, based on the outer feedback voltage at a first stage input node and based on the reference voltage
at a second stage input node;
the differential transistor pair further comprises a current feedback node;
the differential amplification stage further comprises an active load comprising a diode transistor directly coupled to the
current feedback node and a mirror transistor coupled to the stage output node, wherein the current feedback node comprises
a drain of the diode transistor; and

the amplifier further comprises a current feedback network configured to provide a feedback current to the current feedback
node, in dependence of a voltage at the pass device.

US Pat. No. 9,285,412

HIGH SPEED, HIGH CURRENT, CLOSED LOOP LOAD TRANSIENT TESTER

1. A test device configured to generate a load current to be drawn at an output of a voltage regulator, the test device comprising
a load connector for coupling the test device to the output of the voltage regulator;
a transistor configured to modulate the current through the load connector subject to a control signal; wherein the current
through the load connector corresponds to the load current;

a current sense resistor arranged in series with the transistor and configured to provide a feedback voltage which is substantially
proportional to the load current; and

an operational amplifier configured to generate the control signal based on the feedback voltage and based on a target voltage;
wherein the operational amplifier is configured to generate the control signal, such that an absolute difference between the
feedback voltage and the target voltage is reduced.

US Pat. No. 9,231,544

AGC CIRCUIT FOR AN ECHO CANCELLING CIRCUIT

1. A method for reducing distortions incurred by an audio signal when being rendered by an electronic device, the method comprising:
receiving an input signal;
determining a signal strength based on the input signal;
determining a frequency-dependent AGC filter; wherein the frequency-dependent AGC filter is configured to selectively attenuate
the input signal within a number N of predetermined frequency ranges, N being an integer, N>0, according to corresponding
N degrees of attenuation; wherein the N predetermined frequency ranges depend upon a rendering characteristic of the electronic
device; wherein the N degrees of attenuation depend upon the signal strength; wherein each of the N predetermined frequency
ranges comprises a center frequency and an distortion bandwidth; wherein the input signal comprises non-distorting components
at frequencies which are not comprised within the N predetermined frequency ranges; and the non-distorting components are
not substantially attenuated by the frequency-dependent AGC filter; and

attenuating the input signal using the frequency-dependent AGC filter to obtain an output signal for rendering by the electronic
device.

US Pat. No. 9,859,872

APPARATUS AND METHOD FOR TEMPERATURE MEASUREMENT AND/OR CALIBRATION VIA RESONANT PEAKS IN AN OSCILLATOR

Dialog Semiconductor (UK)...

1. A circuit providing resonant peaks for utilization for temperature measurements wherein a plurality of said resonant peaks
are utilized comprising
a resonant device consisting of an oscillator for providing an oscillating source;
a variable gain-bandwidth amplifier and/or constant bandwidth amplifier in parallel with said resonant device for providing
modulation of the gain and/or bandwidth driving said resonant device, and control of resonant peaks for selection for oscillation;

a first capacitor electrically coupled to the parallel combination of the input of said variable gain-bandwidth amplifier
and/or constant bandwidth amplifier, and said resonant device for providing charge storage for oscillation; and,

a second capacitor electrically coupled to parallel combination of the output of said variable gain-bandwidth amplifier and/or
said constant bandwidth amplifier, and said resonant device for providing charge storage for oscillation.

US Pat. No. 9,698,691

CIRCUIT AND METHOD FOR MAXIMUM DUTY CYCLE LIMITATION IN SWITCHING CONVERTERS

Dialog Semiconductor (UK)...

1. An adaptive duty cycle limiting circuit included within a switching DC-to-DC converter, the adaptive duty cycle limiting
circuit comprising:
an inductor current feedback circuit for generating a current sense signal indicative of a level of current through an inductor
within the switching DC-to-DC converter; and

a limit circuit configured for generating an adaptive limit signal from a replica signal of the current sense signal that
is transferred through a parasitic resistance of a switching circuit of the switching DC-to-DC converter to generate a voltage
drop signal across the parasitic resistance, configured for comparing the voltage drop signal with a voltage having a level
indicative of a maximum current limit value to determine if a gain level of the switching DC-to-DC converter has decreased
even though the duty cycle has increased, and configured for transferring the adaptive limit signal is transferred to a switching
circuit for disabling a switch for limiting the duty cycle of the switching DC-to-DC converter such that the switching DC-to-DC
converter does not enter a region where the gain of the switching DC-to-DC converter has a negative slope, when the gain has
decreased.

US Pat. No. 9,653,997

RINGING SUPPRESSION METHOD AND APPARATUS FOR POWER CONVERTERS

Dialog Semiconductor (UK)...

1. A method of controlling a power converter for converting a DC input voltage to a DC output voltage, wherein the power converter
comprises an inductor, one or more switching elements for energizing and de-energizing the inductor, a drive circuit for controlling
switching operation of the one or more switching elements in accordance with a control signal, and a feedback circuit for
generating the control signal on the basis of a first feedback quantity indicative of an actual output voltage of the power
converter and in accordance with one or more circuit parameters of the feedback circuit, the method comprising:
detecting an open loop condition of feedback control by the feedback circuit; and
modifying at least one of the circuit parameters of the feedback circuit in such a manner that a time until the feedback control
returns to the closed loop condition is reduced,

wherein the feedback circuit generates the control signal on the basis of the first feedback quantity and a fourth feedback
quantity indicative of a sum of a fifth feedback quantity indicative of a result of a conversion of a second feedback quantity
indicative of an inductor current to a voltage value and a sixth feedback quantity indicative of a voltage output by a ramp
generator; and

modifying the at least one of the one or more circuit parameters involves:
increasing a gain factor that is applied in the conversion of the second feedback quantity to the voltage value.

US Pat. No. 9,465,086

ON-CHIP TEST TECHNIQUE FOR LOW DROP-OUT REGULATORS

1. A test circuit for a voltage regulator, comprising: a) a finite state machine (FSM) formed on an integrated circuit chip
to test a plurality of low drop out (LDO) voltage regulators included on the integrated circuit chip, wherein the FSM is initiated
by automatic test equipment (ATE) to select an LDO voltage regulator of the plurality of LDO voltage regulators and perform
on-chip tests to determine that an output voltage of the LDO is within specified limits under specified test conditions, wherein
the FSM is to receive a communication from the ATE initiating on-chip testing, to communicate with the LDO selected for on-chip
test to connect to an on-chip measurement (OCM) circuitry providing an analog signal that is measured by the OCM while at
the same time the FSM communicates with the OCM which measurements are to be performed and the FSM is to send test results,
received from the OCM, to the ATE;
b) wherein said measurements performed by the OCM circuitry comprise measurements of the output voltage of the LDO regulator
circuit at specified currents and wherein said measurements performed by the OCM circuitry comprise output voltage measurements
of an output driver circuit connected to the LDO regulator circuit, wherein a current mirror circuit controlled by a current
DAC controls current of the output driver circuit;

c) said output driver of the LDO voltage regulator comprising a plurality of driver transistors connected in parallel and
selected separately to avoid current limits of the ATE; and

d) said tests performed with each driver transistor of the plurality of driver transistors separately selected by the FSM.

US Pat. No. 9,257,965

VCC CHARGE AND FREE-WHEELING DETECTION VIA SOURCE CONTROLLED MOS TRANSISTOR

1. A control circuit configured to control a switching state of a power switch; wherein a first port of the power switch is
coupled to an inductor; wherein
the control circuit is configured to be coupled to a control port of the power switch; wherein the control port of the power
switch is different from the first port of the power switch;

the control circuit comprises a control unit configured to generate a control signal for controlling the switching state of
the power switch; wherein the control signal is to be provided to the control port of the power switch; and

the control circuit comprises free-wheeling sensing means configured to detect a change of a voltage at a measurement port
of the power switch; wherein the measurement port of the power switch is different from the first port of the power switch;
and wherein the change of the voltage at the measurement port is indicative of free-wheeling of the inductor.

US Pat. No. 9,054,737

ANALOG TO DIGITAL CONVERTER CIRCUIT

1. An analog-to-digital converter circuit comprising:
voltage control means configured to control a voltage applied to each of a plurality of output lines;
comparing means connected to a first common line and a second common line and configured to receive a first signal from the
first common line, and to receive a second signal from the second common line, wherein the comparing means is further configured
to compare the first signal with the second signal, and to send a resulting comparative signal to the voltage control means;

first input means configured to receive a first input voltage;
first Digital-to-Analog Converter, DAC, means comprising an output and a plurality of inputs, wherein the output is connected
to the first common line of the comparing means, and wherein the plurality of inputs is configured to be controlled by a first
plurality of output lines of the voltage control means;

first switching means configured to keep the first input means connected to the first common line of the comparing means during
a sampling phase, and to keep the first input means disconnected from the first common line of the comparing means during
a conversion phase which follows the sampling phase;

second Digital-to-Analog Converter, DAC means comprising an output and a plurality of inputs, wherein the output is connected
to the second common line of the comparing means, and the plurality of inputs is configured to be controlled by a second plurality
of the output lines of the voltage control means during the conversion phase;

second switching means configured to keep connected the first input means to the plurality of inputs of the second DAC and
to keep the plurality of output lines of the voltage control means disconnected from the plurality of inputs of the second
DAC during the sampling phase, and to keep the plurality of output lines of the voltage control means connected to the plurality
of inputs of the second DAC and to keep disconnected the first input means from the plurality of inputs of the second DAC
during the conversion phase which follows the sampling phase;

third switching means configured to keep a second voltage input connected to the second common line of the comparing means
during the sampling phase and to keep the second voltage input disconnected from the second common line of the comparing means
during the conversion phase which follows the sampling phase;

wherein the voltage control means is further configured to change the voltage values applied to the plurality of the output
lines based on the resulting comparative signal received from the comparing means.

US Pat. No. 10,063,073

USB POWER CONVERTER WITH BLEEDER CIRCUIT FOR FAST CORRECTION OF OUTPUT VOLTAGE BY DISCHARGING OUTPUT CAPACITOR

Dialog Semiconductor Inc....

16. A universal serial bus (USB) charger for providing power to a client device comprising:a USB connector configured to interface with the client device, and to receive a request for an output voltage at one of a plurality of voltage levels including a first voltage level and a second voltage level;
a converter circuit, an output of the converter circuit coupled to the USB connector, the converter circuit configured to convert an input voltage level to an output voltage level, the converter circuit comprising an output capacitor coupled to the USB connector;
a bleeder circuit coupled to the output capacitor of the converter circuit, the bleeder circuit configured to discharge the output capacitor of the converter circuit responsive to the output voltage level of the converter circuit being greater than the first voltage level, the bleeder circuit comprising:
a first switch coupled to the output controller,
a first bleeder resistor coupled to the output capacitor and the first switch, the first bleeder resistor configured to discharge the output capacitor when the first switch is closed,
a second switch coupled to the output controller, and
a second bleeder resistor coupled to the output capacitor and the second switch, the second bleeder resistor having a resistance higher than the first bleeder resistor, the second bleeder resistor configured to provide a slow discharge of the output capacitor when the first switch is opened; and
an output controller coupled to the converter circuit and the bleeder circuit, the output controller configured to:
turn on the first switch and the second switch responsive to determining that the output voltage level of the USB charger is at a second voltage level, the second voltage level higher than the first voltage level;
turn off the first switch responsive to determining that the output voltage level of the USB charger is at a third voltage level, the third voltage level higher than the first voltage level and lower than the second voltage level; and
turn off the second switch responsive to determining that the output voltage level of the USB charger is within a threshold level of the first voltage level.

US Pat. No. 9,948,185

FAST-TRANSIENT SWITCHING CONVERTER WITH TYPE III COMPENSATION

Dialog Semiconductor (UK)...

1. A control stage circuit within a switch mode DC/DC power converter comprising:a programmable feedback voltage offset generator configured for providing an offset voltage to the feedback voltage to generate an offset feedback voltage when the control loop monitor determines that the offset voltage is required to be provided to the feedback voltage for decreasing overshoot or undershoot of the output voltage of the switch mode DC/DC power converter;
an error amplifier current offset generator configured for generating offset current to be added to the output of the error amplifier;
a feed-forward compensation circuit configured for increasing the input range the feed-forward amplifier output and the error amplifier output; and
a control loop monitor connected to the programmable feedback voltage offset generator, the error amplifier current offset generator, and the feed-forward compensation circuit and configured for monitoring a difference between a feedback voltage developed from the output voltage of the switch mode DC/DC power converter and a positively offset reference voltage and a negatively offset reference voltage for determining if any line and/or load transient signal is an increase or a decrease in magnitude that will cause the overshoot or undershoot of the output voltage of the switch mode DC/DC power converter; and configured for generating output control signals for activating the programmable feedback voltage offset generator, the error amplifier current offset generator, and the feed-forward compensation circuit.

US Pat. No. 9,735,678

VOLTAGE CONVERTERS WITH ASYMMETRIC GATE VOLTAGES

Dialog Semiconductor (UK)...

1. A multi-phase switch converter, the device comprising:
a port for an input voltage (Vin);
a port for a reference common ground voltage (Vcom), wherein the switch converter is supplied by a voltage difference between
voltage Vin and voltage Vcom;

gate voltage driver circuits comprising for each phase of the multi-phase switch converter a high-side gate voltage driver
and a low-side gate voltage driver;

an intermediate voltage, wherein the intermediate voltage has an arbitrary intermediate voltage level between the supply voltage
and the Vcom voltage that is configured, if activated, to enable the high-side gate voltage drivers to switch between the
input voltage and the intermediate voltage and to enable the low-side gate voltage drivers to switch between the intermediate
voltage and the Vcom voltage, thus enabling reduced switching voltages, wherein the intermediate voltage is dynamically controlled
to optimize the efficiency of the switch converter at different loads or output voltages;

multi-phase switches connected to the gate driver circuits;
wherein the multi-phase switching converter is capable of turning the gate voltage of the gate voltage drivers and in consequence
of the multi-phase switches with lower switching voltages to provide lower switching losses and higher efficiency for low
and medium load currents.

US Pat. No. 9,755,629

CURRENT-CONTROLLED ACTIVE DIODE

Dialog Semiconductor (UK)...

1. An active diode circuit for letting current pass in one direction and substantially blocking current in the opposite direction,
the active diode circuit comprising:
a transistor;
a control voltage generation circuit for generating a control voltage that is supplied to a control terminal of the transistor;
and

a sensing circuit for detecting a quantity indicative of a current flowing through the transistor,
wherein the control voltage generation circuit is configured to generate the control voltage in dependence on the detected
quantity; and

wherein the control voltage generation circuit is further configured to:
compare the detected quantity to a predetermined threshold; and
if the detected quantity exceeds the predetermined threshold, output, as the control voltage, a first voltage that is sufficient
to drive the transistor in the fully conducting state.

US Pat. No. 9,654,007

REGULATION OF A MULTIPLE STAGE SWITCH MODE POWER CONVERTER THROUGH AN INTERMEDIATE VOLTAGE CONTROL

Dialog Semiconductor (UK)...

1. A multiple phase, multiple stage switch mode power converter (SMPC) system comprising:
at least one single stage phase SMPC circuit configured for converting an input voltage of the multiple phase, multiple stage
SMPC system to an output voltage of the multiple phase, multiple stage SMPC system and connected to an electronic load circuit
for transferring the output voltage to the electronic electronic load circuit; and;

at least one multiple stage phase SMPC circuit comprising:
at least one primary stage phase SMPC circuit configured for converting an input voltage of the multiple phase, multiple stage
SMPC system to an intermediate voltage, and

at least one secondary stage phase of the multiple stage SMPC circuit that is connected to receive the intermediate voltage
from the at least one primary stage SMPC circuit and configured for converting the intermediate voltage to an output voltage
of the multiple phase, multiple stage SMPC system, wherein the at least one secondary stage of the multiple stage switch mode
power supply circuit comprises:

a voltage conditioner configured for transforming the intermediate voltage to be approximately the level of the output voltage
to act a reference voltage for the secondary stage in determining the switching characteristics of the secondary stage SMPC
circuit.

US Pat. No. 9,673,971

AUTOMATIC CLOCK CALIBRATION OF A REMOTE UNIT USING PHASE DRIFT

1. A calibrated clock, comprising:
a) a portable part coupled to a fixed part by wireless communications; and
b) a first clock in said portable part automatically adjusted to be aligned with a second clock in the fixed part, wherein
the frequency of the first clock varied until the first clock is synchronous with the second clock, and wherein a clock register
value is stored in a non-volatile memory if after a predetermined number of data frames the first clock remains in synchronization
with the second clock; wherein the fixed and the portable part periodically communicate wirelessly, wherein the fixed part
provides periodically a synchronization signal looking for a response from the portable part and the portable part provides
periodically to the fixed part parameter data, comprising environmental temperatures of the portable part and wherein for
each of the predetermined number of data frames, which are in synchronization with the second clock, phase and Tap data is
stored in buffers in the portable part, wherein phase is a phase relationship between fixed part and portable part clocks
in decimal units and TAP provides a greater resolution of the phase relationship between the fixed part and portable part
clocks.

US Pat. No. 9,484,909

ANTI-SHOOT-THROUGH AUTOMATIC MULTIPLE FEEDBACK GATE DRIVE CONTROL CIRCUIT

1. A system capable of an automatic and robust anti-shoot-through glitch-free operation of half-bridge control pre-driver
and power stage circuits using at least two feedback loops from each branch of the half-bridge, comprising:
one input port receiving an input signal;
one output port;
a high-side branch and a low-side branch arranged in parallel, wherein both branches are connected to the input port, each
branch comprising:

a power transistor having a gate controlled by n pre-drivers connected in series, wherein n is an integer number equal or
higher than 2;

said n pre-drivers driving the power transistor of the correspondent branch; and
a number of logic control blocks connected in series enabling to switch to ON state or to switch to OFF state of the power
transistor of the correspondent branch via the n pre-drivers of the correspondent branch wherein a first of the number of
logic control blocks is connected to the input port and a last logic control block is connected to a first of the n pre-drivers,
and wherein the logic blocks comprise either logical NOT AND (NAND) logic gates or NOT OR (NOR) logic gates;

wherein both power transistors are connected in series between VDD voltage and ground, wherein a source of the high side power
transistor is connected to VDD voltage, a drain of the high side power transistor is connected to a drain of the low side
power transistor, the source of the low side power transistor is connected to ground, wherein the drains of both power transistors
are connected to the output port, wherein only the drains of the power transistors provide input to the output port, and wherein
two or more feedback loops from each branch are implemented from each branch to the logic control blocks of the opposite branch
in order to be capable of preventing cross-conduction between both power transistors of the low side and of the high side.

US Pat. No. 9,473,033

PROGRAMMING OF A TWO TERMINAL DEVICE

DIALOG SEMICONDUCTOR, INC...

1. A device, comprising:
a first terminal;
a second terminal;
a current switch coupled between the two terminals; and
a controller configured to respond to a first voltage modulation of an input signal received through the first and second
terminals by triggering a write of at least one digital word to a memory, and wherein the controller is further configured
to respond to a second voltage modulation of the input signal by cycling the current switch to read out the at least one digital
word from the memory through a current modulation of a current flowing between the first and second terminals.

US Pat. No. 9,313,836

CIRCUIT AND METHOD FOR DETECTING THE DURATION OF THE INTERRUPTION OF A MAINS INPUT

1. A light bulb assembly comprising:
an electrical connection module configured to electrically connect to a mains power supply, thereby providing electrical energy
at an input voltage;

a driver circuit configured to provide electrical energy at a drive voltage from the electrical energy at the input voltage,
said driver circuit comprising:

a power converter configured to convert the electrical energy at the input voltage into electrical energy at the drive voltage;
a controller configured to control the power converter such that the power converter provides the electrical energy at the
drive voltage, wherein the controller is configured to stop operation subsequent to an interruption of electrical energy provided
at the input of the driver circuit, and resume operation subsequent to the provision of electrical energy at the input of
the driver circuit; and

a timing circuit coupled to the controller, wherein a timing voltage at the timing circuit decays with a pre-determined time
constant if not maintained, and wherein the controller is configured to maintain the timing voltage at or above a first voltage
level when the controller is in operation, determine an indication of a residual level of the timing voltage when the controller
resumes operation after an interruption of electrical energy provided at the input of the driver circuit, and determine an
indication of the duration of the interruption of electrical energy provided at the input of the driver circuit based on the
first voltage level, the pre-determined time constant, and an indication of the residual level of the timing voltage; and

a light source configured to provide light using the electrical energy at the drive voltage.

US Pat. No. 9,292,026

CIRCUITS AND METHOD FOR CONTROLLING TRANSIENT FAULT CONDITIONS IN A LOW DROPOUT VOLTAGE REGULATOR

9. A low dropout voltage regulator circuit comprising:
a local control loop connected to provide a balancing current to an active load of a differential amplifier within a low dropout
voltage regulator to clamp an output voltage level of the differential amplifier near an operational voltage level to insure
fast response in controlling the gate of a pass transistor to minimize overshoot when a transient fault condition at the input
terminal or the output terminal of the low dropout voltage regulator is ending and the voltage level present at the input
terminal or output current level present at the output terminal is returned to its normal operating conditions.

US Pat. No. 9,173,273

SOLID STATE LIGHTENING DRIVER WITH MIXED CONTROL OF POWER SWITCH

1. A control unit for a driver circuit which is configured to drive a solid state lightening, referred to as SSL device, subject
to an input voltage derived from a mains voltage using a phase-cut dimmer, wherein the driver circuit comprises a transistor
operable in a first mode and in a second mode; and a power converter network; wherein the driver circuit further comprises
current sensing means configured to determine a feedback signal indicative of the level of the current through the transistor;
and wherein the control unit is configured to
control the transistor to selectively operate in the first and second mode; wherein in the first mode, the transistor alternates
between an on-state and an off-state at a commutation cycle rate, thereby providing a switched-mode power converter in conjunction
with the power converter network; wherein in the second mode, the transistor is controlled via a gate control signal applied
to the gate of the transistor so that it is traversed by a controlled current, thereby providing a controlled load to the
mains voltage; and

control the level of the current through the transistor, when in the second mode, by determining the gate control signal based
on the feedback signal.

US Pat. No. 9,122,289

CIRCUIT TO CONTROL THE EFFECT OF DIELECTRIC ABSORPTION IN DYNAMIC VOLTAGE SCALING LOW DROPOUT REGULATOR

20. An apparatus for compensating for the dielectric absorption current from the recharging of the output load capacitor of
a low dropout voltage regulator comprising:
means for requesting the low voltage regulator to decrease its output voltage;
means for enabling an internal load current source to decrease the output voltage of the low dropout voltage regulator by
adjusting the charge of the output load capacitor;

means for ramping down an output voltage level of the low dropout voltage regulator until it brought to a to a lower voltage
level;

means for disabling the internal load voltage source; and
means for applying a profile compensation current after the low dropout voltage regulator is disabled to counteract the dielectric
absorption current of the recharging output load capacitor to prevent the low dropout voltage regulator from becoming unregulated.

US Pat. No. 9,112,406

HIGH EFFICIENCY CHARGE PUMP CIRCUIT

1. A charge pump circuit configured to generate an output voltage Vout at an output of the circuit from an input voltage Vin
at an input of the circuit, wherein a level of the output voltage Vout is greater than a level of the input voltage Vin; wherein
the charge pump circuit comprises
a first P-type switch comprising an input node and an output node; wherein the input node of the first P-type switch is coupled
to the input of the circuit;

a boosting capacitor coupled at a first side to the output node of the first P-type switch and coupled at a second side to
a capacitor control signal;

a second P-type switch comprising an input node and an output node; wherein the input node of the second P-type switch is
coupled to the output node of the first P-type switch, and wherein the output node of the second P-type switch is coupled
to the output of the circuit; and

control circuitry configured to provide a capacitor control signal which alternates between a low level and a high level,
and configured to generate first and second control signals based on the capacitor control signal for alternating the first
and second P-type switches between on-states and off-states, respectively, such that electrical energy is transferred from
the input to the output of the circuit using the boosting capacitor; wherein the control circuitry is configured to generate
the second control signal, such that the second P-type switch is closed, during a discharging phase, when the capacitor control
signal is at high level, to discharge the boosting capacitor towards the output of the circuit; and/or such that the second
P-type switch is open, during a charging phase, when the capacitor control signal is at low level; wherein the control circuitry
comprises a control capacitor arranged between a gate node of the second P-type switch and an inverted version of the capacitor
control signal; and a control switch arranged between a power supply and the gate node of the second P-type switch; wherein
the control switch is configured to couple the gate node to the power supply for charging the control capacitor and for closing
the second P-type switch; and wherein the control switch is configured to decouple the gate node from the power supply for
opening the second P-type switch.

US Pat. No. 9,084,330

SHORT CIRCUIT DETECTION FOR LIGHTING CIRCUITS

1. A fault-tolerant controller for a lighting system comprising a plurality of LED circuits and a controllable power source
providing a drive voltage to power the plurality of LED circuits, the fault-tolerant controller comprising:
a control unit configured to cause regulation of the drive voltage based on a determination of a plurality of feedback voltages,
one feedback voltage for each of the plurality of LED circuits; and

a fault condition detecting means configured to identify one or more fault conditions from the plurality of feedback voltages,
wherein at least one of the LED circuits is determined as a fault circuit having a fault condition for which the respective
feedback voltage is below a first fault circuit condition threshold, wherein the fault condition detecting means is further
configured, in response to a detected fault condition, to apply a test voltage to a cathode of the fault-circuit and, if the
feedback voltage of the fault circuit remains below a second fault circuit condition threshold, the fault circuit is determined
to have a short circuit condition, wherein the fault condition detecting means comprises a plurality of pull-up circuits,
each pull-up circuit provided between ground voltage and a cathode for each LED circuit, wherein each pull-up circuit comprises
a voltage source and a switch, the fault condition detecting means being configured to cause closing of the switch associated
with the fault circuit upon detecting a fault condition to apply the test voltage to the cathode of the fault circuit.

US Pat. No. 9,065,335

ARTIFICIAL RAMP GENERATING IN PWM MODULATOR FOR CURRENT CONTROL MODE

11. A circuit for artificial ramp signal generation for pulse-width modulators for current control mode switch mode power
supplies (SMPS), comprising:
an input port connected to a current sensing circuit;
said current sensing circuit capable of measuring a current through an inductor of the SMPS, wherein the measurement result
is amplified by a current amplifier;

said current amplifier configured to having an output current comprising the measurement result amplified plus a biasing pedestal
current and the output is connected directly to an output of a pedestal constant current source and to a voltage sense node;

said pedestal constant current source capable of generating a current of a value of about the pedestal current, wherein the
current generated by the pedestal constant current source is subtracted from the output current of the amplifier in order
to have the current at the voltage sense node free from the portion of the pedestal current;

a resistor connected between the voltage sense node and ground;
a capacitor, configured to generating a sawtooth pulse, connected between the voltage sense node and a first input of a PWM
comparator, wherein the capacitor is discharged after each clock period by two switches, wherein a first terminal of the capacitor
is connected to a first input terminal of the PWM comparator and a second terminal of the capacitor is connected to the voltage
sense node and wherein a current generated by one biasing constant current source biasing the capacitor is fed to the capacitor
on the side of the first terminal of the capacitor;

said one biasing constant current source capable of biasing the capacitor;
said two switches, wherein each terminal of the capacitor is connected via one switch to ground; and
said PWM comparator.

US Pat. No. 10,149,354

POWER CONVERTER CONTROLLER

Dialog Semiconductor (UK)...

1. A controller for controlling a power converter to convert electrical power at an input voltage into electrical power at an output voltage, the controllercomprising
an input port configured to receive a voltage representative of the input voltage;
an input voltage measuring unit configured to sample a measuring voltage and determine a measurement value that is representative of the input voltage;
a switch;
a diode connectable with a storage unit to provide a supply voltage for the controller during operation of the controller, and
a resistor which forms a voltage divider with an external resistor connected to the input port, the input voltage measuring unit connected with a terminal of the resistor to measure a portion of the input voltage, the portion determined by the voltage divider ratio;
wherein the switch is controlled to control charging of the storage unit from the voltage at the input port.

US Pat. No. 10,148,170

SWITCHING POWER CONVERTER WITH MAGNETIZING CURRENT SHAPING

DIALOG SEMICONDUCTOR INC....

10. A switching power converter, comprising:a power switch;
a dimmer configured to apply a phase cut dimming to an AC input voltage responsive to a dimming command to produce a processed AC input voltage;
a dimmer detection circuit configured to determine whether the dimmer applied the phase cut dimming to the processed AC input voltage;
a controller including a power factor control (PFC) feedback loop configured to determine a desired peak current responsive to a determination by the dimmer detection circuit that the dimmer applied the phase cut dimming, and wherein, prior to a zero crossing time for the AC input voltage, the controller is further configured to cycle the power switch to conduct a first magnetizing current equaling the desired peak current while the desired peak current is greater than a first threshold and to clamp the first magnetizing current to equal the first threshold while the desired peak current is less than the first threshold, and wherein, subsequent to the zero crossing time for the AC input voltage, the controller is further configured to cycle the power switch to conduct a second magnetizing current equaling the desired peak current while the desired peak current is greater than a second threshold and to clamp the second magnetizing current to equal the second threshold while the desired peak current is less than the second threshold, wherein the second threshold is greater than the first threshold.

US Pat. No. 9,772,639

DYNAMIC CURRENT-LIMIT CIRCUIT

Dialog Semiconductor (UK)...

1. A comparator circuit which is configured to provide a control current and a control voltage based on a first input voltage
and a second input voltage, the comparator circuit comprising
an input amplifier configured to generate an output signal based on a delta voltage which corresponds to a difference between
the first input voltage and the second input voltage;

offset means configured to generate a first offset;
a first output circuit configured to generate the control current based on the output signal and based on the first offset;
and

a second output circuit configured to generate the control voltage based on the output signal and not based on the first offset;
wherein the second output circuit is configured to generate the control voltage such that the control voltage exhibits a swing
from a first potential to a second potential at a first delta voltage; and wherein the first output circuit is configured
to generate the control current such that the control current is substantially linear for delta voltages within a pre-determined
interval around the first delta voltage.

US Pat. No. 9,739,810

DUTY CYCLE INDEPENDENT COMPARATOR

Dialog Semiconductor (UK)...

1. A circuit configured to measure a pulsed current through a pass transistor of a switching circuit in order to detect, independently
of frequency and percentage of a duty cycle driving the switching circuit, if the current through the pass transistor has
reached a threshold value, comprising:
the pass transistor connected between a supply voltage and a load;
a node for a reference voltage; and
a circuit capable of comparing the reference voltage with a first voltage representing the pulsed current through the pass
transistor during a first phase of the duty cycle of the switching circuit driving the switching circuit, while the pass transistor
is ON, and of substituting the first voltage by the reference voltage during the remaining part of the duty cycle driving
the switching circuit while the pass transistor is OFF, wherein the comparison detects independently of frequency and percentage
of the duty cycle if an average current through the pass transistor has reached one or more threshold values over the duty
cycle;
wherein the circuit capable of comparing the reference voltage with a voltage representing the pulsed current through the
pass transistor further comprises:
a sense transistor connected between a supply voltage and a current source wherein the node for the reference voltage is deployed
between the sense transistor and the current source and wherein the node for the reference voltage is connected to a second
terminal of a second switch and to a second input of a comparator, wherein the sense transistor is matched to the pass transistor;

said current source connected between ground and said sense transistor;
a first switch, wherein a first terminal of the switch is connected to the load of the pass transistor and a second terminal
of the switch is connected to a first input of the comparator and to a first terminal of the second switch;

said second switch; and
said comparator wherein its output is used to detect if the current through the pass transistor has reached a threshold;
wherein the first switch is closed and the second switch is open during ON-time of the pass transistor and vice versa the
first switch is open and the second switch is closed during OFF-time of the pass transistor.

US Pat. No. 9,698,681

CIRCUIT AND METHOD FOR MAXIMUM DUTY CYCLE LIMITATION IN STEP UP CONVERTERS

Dialog Semiconductor (UK)...

1. An adaptive duty cycle limiting circuit for use with a switching DC-to-DC converter comprising:
a ramp generator configured for receiving an output voltage of the switching DC-to-DC converter communicated from an output
terminal of the switching DC-to-DC converter and configured for generating an output ramp signal created from the output voltage
of the switching DC-to-DC converter;

a variable voltage source configured for receiving an adjusting voltage level indicating the voltage level of an input voltage
source and configured for generating an output voltage level that is a fractional value of the voltage level of the input
voltage source; and

a comparator circuit configured for receiving the output voltage level of the variable voltage source, and the output voltage
ramp signal, and configured for determining if the voltage level of the variable voltage source is less than or greater than
output voltage ramp signal to generate a duty cycle limit signal for transfer to a converter switching control circuit to
adjust the duty cycle of the switching DC-to-DC converter.

US Pat. No. 9,509,300

ANTI-SHOOT-THROUGH AUTOMATIC MULTIPLE FEEDBACK GATE DRIVE CONTROL CIRCUIT

1. A system capable of an automatic and robust anti-shoot-through glitch-free operation of half-bridge control pre-driver
and power stage circuits using at least two feedback loops from each branch of the half-bridge, comprising:
one input port receiving an input signal;
one output port;
a high-side branch and a low-side branch arranged in parallel, wherein both branches are connected to the input port, each
branch comprising:

a power transistor having a gate controlled by n pre-drivers connected in series, wherein n is an integer number equal or
higher than 2;

said n pre-drivers driving the power transistor of the correspondent branch; and
a number of logic control blocks connected in series enabling to switch to ON state or to switch to OFF state of the power
transistor of the correspondent branch via the n pre-drivers of the correspondent branch wherein a first of the number of
logic control blocks is connected to the input port and a last logic control block is connected to a first of the n pre-drivers,
and wherein the logic blocks comprise either logical NOT AND (NAND) logic gates or NOT OR (NOR) logic gates;

wherein both power transistors are connected in series between VDD voltage and ground, wherein a source of the high side power
transistor is connected to VDD voltage, a drain of the high side power transistor is connected to a drain of the low side
power transistor, the source of the low side power transistor is connected to ground, wherein the drains of both power transistors
are connected to the output port, wherein only the drains of the power transistors provide input to the output port, and wherein
two or more feedback loops from each branch are implemented from each branch to the logic control blocks of the opposite branch
in order to be capable of preventing cross-conduction between both power transistors of the low side and of the high side.

US Pat. No. 9,477,252

VOLTAGE REGULATOR

Dialog Semiconductor (UK)...

1. A voltage regulator comprising
an output node providing an output voltage for a load;
current sensing means for sensing an output current flowing at the output node;
voltage providing means for providing a digital representation of the output voltage or of an input voltage to the voltage
regulator;

output power determination means comprising a digitally controllable variable resistance circuit receiving the digital voltage
representation from the voltage providing means and generating a resistance depending thereon,

wherein the variable resistance circuit is connected to the current sensing means to obtain a signal that depends upon the
output current and generates a voltage depending on the generated resistance and the obtained signal; and

wherein the output power determining means are adapted to determine the output power of the voltage regulator based on the
voltage generated by the variable resistance circuit.

US Pat. No. 9,454,170

LOAD TRANSIENT, REDUCED BOND WIRES FOR CIRCUITS SUPPLYING LARGE CURRENTS

1. A method to improve dynamic load transient performance of circuits supplying high current, comprising the following steps:
(1) providing an electronic circuit supplying high currents and having parasitic resistances and a differential error amplifier,
wherein said parasitic resistances comprise resistances of one or more bond wires, metallization of one or more pass devices,
and substrate routings;

(2) including parasitic resistances in a separate loop for fast loop response, wherein the separate loop for fast loop response
is connected between an output of the differential error amplifier and a separate pad connected to feedback voltage divider
VFB;

(3) implementing a stabilizing circuit within said fast loop response, wherein the stabilization circuit is achieved by splitting
a main pass device into two unequal parts, namely a smaller part of the pass device and a larger part of the pass device and
by placing a controlled impedance in series with the smaller part of the main pass device and including this controlled impedance
to the parasitic resistances of the fast loop response; and

(4) deploying the separate pad for the fast loop response directly connected to feedback voltage divider VFB.

US Pat. No. 9,391,501

VCC CHARGE AND FREE-WHEELING DETECTION VIA SOURCE CONTROLLED MOS TRANSISTOR

1. A control circuit configured to re-charge supply voltage provisioning means and configured to control the switching state
of a power switch; wherein the supply voltage provisioning means are configured to provide a supply voltage to a gate of the
power switch; the control circuit comprising
a control switch configured to
couple an output of the power switch to ground, when an input of the control switch is coupled to the output of the power
switch, to put the power switch to an on-state; and

decouple the output of the power switch from ground, to put the power switch to an off-state; and
charging circuitry configured to enable a charging current flowing from the output of the power switch to the supply voltage
provisioning means and configured to disable a current flowing from the supply voltage provisioning means to the output of
the power switch, when an input of the charging circuitry is coupled to the output of the power switch and when an output
of the charging circuitry is coupled to the gate of the power switch and to the supply voltage provisioning means; wherein
the charging current is derived from a current flowing through an input-to-output capacitance arranged between an input and
the output of the power switch.

US Pat. No. 9,348,780

CIRCUIT AND METHODS TO USE AN AUDIO INTERFACE TO PROGRAM A DEVICE WITHIN AN AUDIO STREAM

1. A method for controlling at least one digitized analog communication device from a control circuit communicating with the
at least one digitized analog communication device with a serial digitized analog protocol over a network of a plurality of
digitized analog communication devices, the method comprising the steps of:
periodically sampling and digitizing an analog signal by one digitized analog communication device;
placing the digitized analog signal into periodic frames by the one digitized analog communication device;
serializing each frame of the digitized analog signal by the one digitized analog communication device;
truncating at least one of each frame of the digitized analog signal at a least significant bit location of the at least one
frame of the digitized analog signal to create a sub-channel within the at least one frame of the digitized analog signal
by the one digitized analog communication device;

multiplexing a command word received from the control circuit within the sub-channel of at least one of the periodic frames,
wherein the command word comprises at least one keyword packet of a plurality of keyword packets followed by at least one
command packet of a plurality of command packets;

transmitting the truncated serial digitized signal with the command word multiplexed within the sub-channels of the frames
over the network; and

executing a command designated by the command word by at least one other digitized analog device iteratively receiving, extracting,
and counting the command word based upon two or more receptions of the sub-channels of the frames.