US Pat. No. 9,202,758

METHOD FOR MANUFACTURING A CONTACT FOR A SEMICONDUCTOR COMPONENT AND RELATED STRUCTURE

GLOBALFOUNDRIES Inc., Gr...

1. A method for manufacturing a semiconductor component, comprising:
providing a semiconductor material;
forming a layer of silicon nitride directly on the semiconductor material;
forming a layer of dielectric material directly on the layer of silicon nitride using Sub-Atmospheric Chemical Vapor Deposition
(SACVD), the layer of dielectric material comprising doped silicate glass;

forming a contact hole in the layer of dielectric material, the contact hole having sidewalls and exposing a portion of the
semiconductor material; and

forming a layer of tungsten nitride in the contact hole and on the exposed portion;
wherein all processing temperatures for manufacturing the semiconductor component are less than about 450 degrees Celsius;
wherein forming the layer of dielectric material includes using ozone as a carrier gas.

US Pat. No. 9,380,248

REMOTE CONTROL SYSTEM

CYPRESS SEMICONDUCTOR COR...

1. A system comprising:
a remote control configured to transmit one or more radio frequency (RF) packets to a first communication interface; and
a host device configured to transfer command information to the remote control through the first communication interface in
response to the one or more RF packets including one or more requests from the remote control, the one or more requests identifying
one or more devices, wherein the host device is configured to identify and select the command information including one or
more command codes from a remote library based on the one or more devices identified by the one or more requests, the one
or more command codes being specific to the one or more devices identified by the one or more requests, wherein the host device
is configured to receive an input indicating that the command information specific to the one or more devices is not stored
in the remote library, wherein the host device is further configured to generate the command information and transmit the
command information to the remote control via the first communication interface responsive, at least in part, to receiving
the input,

wherein the remote control is configured to control a plurality of remote devices, using the command information, through
a second communication interface, and wherein the host device is configured to retrieve the command information from a remote
computer through a third communication interface prior to the transfer of the command information to the remote control through
the first communication interface.

US Pat. No. 9,600,384

SYSTEM-ON-CHIP VERIFICATION

Cypress Semiconductor Cor...

1. A computer implemented method of verifying a system-on-chip to re-use a common set of software codes between software and
hardware domains while achieving hardware-driven verification coverage, comprising:
employing an interconnect between a processing subsystem and a plurality of peripherals,
wherein the interconnect includes a plurality of communication protocols, and
wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and
wherein the processing subsystem comprises at least one of a central processing unit (CPU) or a CPU subsystem; and
implementing a common set of software codes by at least one of the plurality of applications for a software development process
and a hardware verification process; and

causing the interconnect to configure at least one of the plurality of communication protocols to choose from software models
or register-transfer level (RTL) models.

US Pat. No. 9,449,655

LOW STANDBY POWER WITH FAST TURN ON FOR NON-VOLATILE MEMORY DEVICES

Cypress Semiconductor Cor...

1. An apparatus comprising:
a non-volatile memory device comprising a plurality of drivers; and
a standby control circuit coupled to the non-volatile memory device, the standby control circuit comprising:
a standby detection circuit to detect a standby condition;
a wake-up detection circuit to detect a wake condition; and
a bias control circuit coupled to the plurality of drivers, the standby detection circuit, and the wake-up detection circuit,
the bias control circuit to control bias currents supplied to the plurality of drivers based on at least one of the standby
condition and the wake condition, wherein an output frequency of at least one of the plurality of drivers is adjustable responsive
to a change in the bias current.

US Pat. No. 9,252,154

NON-VOLATILE MEMORY WITH SILICIDED BIT LINE CONTACTS

CYPRESS SEMICONDUCTOR COR...

1. A method comprising:
disposing a first dielectric layer on a substrate;
disposing a dielectric charge trapping layer on the first dielectric layer;
disposing a second dielectric layer on the dielectric trapping layer;
patterning a hard mask on the second dielectric layer;
disposing an oxide spacer on sidewalls of the hard mask to leave exposed a bit line contact region;
removing portions of the second dielectric layer, dielectric trapping layer and first dielectric layer within the bit line
contact region;

removing portions of the oxide spacer to leave exposed a portion of the second dielectric layer; and
removing the exposed portion of the second dielectric layer to thereby yield extended portions of the dielectric trapping
layer and first dielectric layer.

US Pat. No. 9,129,686

SYSTEMS AND METHODS FOR PROVIDING HIGH VOLTAGE TO MEMORY DEVICES

Cypress Semiconductor Cor...

1. An apparatus, comprising:
a low voltage input to receive a first voltage; and
a two-rail level shifting circuit coupled to the low voltage input, the two-rail level shifting circuit to one of:
increase the first voltage to a second voltage that is greater than the first voltage when programming and erasing a memory
device, wherein an amount of the second voltage is based on an amount of the first voltage, and

decrease the first voltage to a third voltage that is less than or equal to a ground potential when programming and erasing
the memory device, wherein an amount of the third voltage is based on an amount of the first voltage.

US Pat. No. 9,252,026

BURIED TRENCH ISOLATION IN INTEGRATED CIRCUITS

Cypress Semiconductor Cor...

1. A method, comprising:
forming a trench in a substrate, the trench having a closed end within the substrate and an open end adjacent a surface of
the substrate;

forming a seed layer in the trench before initiating a reshaping of portion of the substrate surrounding the open end of the
trench;

initiating the reshaping of portion of the substrate surrounding the open end of the trench;
closing the open end of the trench with substrate material to form an isolation region within the substrate; and
creating first and second devices on the surface of the substrate on opposite sides of the isolation region.

US Pat. No. 9,293,441

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

CYPRESS SEMICONDUCTOR COR...

1. A wireless communications device, comprising:
a flash memory comprising:
a plurality of stacked semiconductor chips, at least one of the semiconductor chips comprising:
a semiconductor substrate;
a first insulating layer on a top face and side faces of the semiconductor substrate with concavities on side faces thereof,
wherein said concavities have planar side surfaces that extend vertically from a first edge at the top face of the semiconductor
substrate to a second edge at the bottom face of the semiconductor substrate, wherein the first edge is beveled;

first metal layers that are provided in center portions of the concavities in a direction that is orthogonal to a direction
of the top face and above the top face in a direction that is parallel to the direction of the top face; and

second metal layers that are provided in the concavities above and contacting the first metal layers and filling the concavities;
a processor;
a communications component;
a transmitter;
a receiver; and
an antenna connected to the transmitter circuit and the receiver circuit.

US Pat. No. 9,251,117

RECONFIGURABLE CIRCUIT WITH SUSPENSION CONTROL CIRCUIT

CYPRESS SEMICONDUCTOR COR...

1. A reconfigurable circuit comprising:
a reconfigurable arithmetic execution unit array comprising:
a plurality of arithmetic execution units, and
a network circuit configured to provide reconfigurable connections between the arithmetic execution units;
a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic
execution unit array; and

a buffer circuit comprising:
a counter configured to output a count value;
a temporary storage unit; and
a selector configured to:
supply the reconfigurable arithmetic execution unit array with a first data from an external buffer in response to the count
value being equal to zero; and

supply the reconfigurable arithmetic execution unit array with a second data from the temporary storage unit in response to
the count value being equal to one or larger than one.

US Pat. No. 9,226,355

STOCHASTIC SIGNAL DENSITY MODULATION FOR OPTICAL TRANSDUCER CONTROL

Cypress Semiconductor Cor...

1. An apparatus, comprising:
a current supply coupled to a light source; and
a controller coupled to the current supply including:
a comparator comprising a first input, a second input and an output,
a stochastic state machine, coupled to the first input of the comparator, to generate a plurality of stochastic values, and
a signal density register, coupled to the second input of the comparator, to hold a signal density value,
wherein the output of the comparator is based on a stochastic value of the plurality of stochastic values and the signal density
value,

wherein the controller is configured to provide a stochastic control signal to the current supply, the stochastic control
signal to control a light intensity output of the light source.

US Pat. No. 9,165,661

SYSTEMS AND METHODS FOR SWITCHING BETWEEN VOLTAGES

Cypress Semiconductor Cor...

1. A system for switching between a plurality of voltages, comprising:
an output;
a first switch coupled to the output;
a second switch coupled to the output;
a first controlled transmission gate coupled to the first switch and configured to be coupled to and receive a first negative
voltage and a positive voltage from a first voltage source; and

a second controlled transmission gate coupled to the second switch and configured to be coupled to and receive a second negative
voltage and the positive voltage from a second voltage source.

US Pat. No. 9,336,890

SIMULTANEOUS PROGRAMMING OF MANY BITS IN FLASH MEMORY

Cypress Semiconductor Cor...

1. A semiconductor device comprising:
a plurality of memory cells;
a plurality of local bit lines connected to respective memory cells of the plurality of memory cells; and
a first amplifier configured to:
receive read data from each local bit line of the plurality of local bit lines,
determine a transition speed of an output level of the first amplifier in response to receiving a combination of at least
two pieces of read data, and

transfer multivalued data of the read data to a read global bit line based on the determined transition speed.

US Pat. No. 9,244,576

USER INTERFACE WITH CHILD-LOCK FEATURE

Cypress Semiconductor Cor...

16. A method comprising:
receiving data from a seat occupant classification system to classify a seat occupant as a child or an adult; and
setting a capacitive touch detection threshold of an input touch-sensing device based on the received data, wherein the input
touch-sensing device is to detect a touch by comparing an amount of capacitance induced by the touch at a location of a capacitive
sense element of a plurality of capacitive sense elements comprised by the input touch-sensing device to the capacitive touch
detection threshold.

US Pat. No. 9,240,440

METHOD MINIMIZING IMPRINT THROUGH PACKAGING OF F-RAM

Cypress Semiconductor Cor...

1. A method of minimizing imprint in a ferroelectric capacitor comprising using an AC field to electrically depole the ferroelectric
capacitor before being packaged, wherein the AC field is generated using a series of two voltage pulses including a first
strong voltage pulse followed by a second weak voltage pulse,
wherein the second weak voltage pulse comprises a voltage less than a minimum operating voltage of the ferroelectric capacitor.

US Pat. No. 9,098,144

ADAPTIVE AMBIENT LIGHT AUTO-MOVEMENT BLOCKING IN OPTICAL NAVIGATION MODULES

Cypress Semiconductor Cor...

1. A method comprising:
collecting from a photo diode (PD) in an optical navigation module (ONM) a plurality of PD signal samples;
determining a peak-to-peak variation (?PD) in the plurality of PD signal samples;
comparing ?PD to a specified threshold peak-to-peak variation (?PDSPEC); and

if ?PD is less than ?PDSPEC, suppressing reporting of motion data derived from signals from a photo detector array (PDA) in the ONM to block auto-movement
in an output from the ONM.

US Pat. No. 9,472,947

PROTECTING CIRCUIT AND INTEGRATED CIRCUIT

CYPRESS SEMICONDUCTOR COR...

1. A protecting circuit, comprising:
a discharge switch configured to connect to a first terminal and a second terminal;
a trigger circuit comprising load devices configured to be connected in series between the first terminal and the second terminal,
each of the load devices being configured to consume power; and

a shunt circuit comprising, between the trigger circuit and the first terminal or the second terminal, a first shunt pathway
configured to be capable of bypassing at least one of the load devices but not at least a second one of the load devices and
a second shunt pathway configured to be capable of bypassing the at least one of the load devices and the at least second
one of the load devices,

wherein the trigger circuit is configured to turn on the discharge switch when a voltage between the first terminal and the
second terminal is higher than a first voltage value,

wherein the shunt circuit is configured to electrically connect the first shunt pathway when the voltage is higher than a
second voltage value that is greater than the first voltage value, and wherein the shunt circuit is configured to electrically
connect the second shunt pathway when the voltage is higher than a third voltage value that is greater than the first voltage
value.

US Pat. No. 9,466,496

SPACER FORMATION WITH STRAIGHT SIDEWALL

Cypress Semiconductor Cor...

1. A method of fabricating a semiconductor device, comprising:
disposing a gate structure on a substrate, the gate structure comprising:
a gate, a first dielectric disposed beneath the gate, and a second dielectric at least on sidewalls of the gate and over the
gate;

disposing a first layer of material over the second dielectric;
disposing a second layer of material over the first layer of material;
etching the second layer of material such that portions of the second layer of material remain on sidewalls of the first layer
of material;

etching the first layer of material with an etchant having substantially higher selectivity to the first layer of material
than to the second layer of material; and

etching the portions of the second layer of material remaining on the sidewalls of the first layer of material.

US Pat. No. 9,368,606

MEMORY FIRST PROCESS FLOW AND DEVICE

CYPRESS SEMICONDUCTOR COR...

1. A semiconductor device, comprising:
a memory gate, disposed in a first region of the semiconductor device, wherein the memory gate includes a first gate conductor
layer disposed such that it overlaps a charge trapping dielectric;

a first select gate disposed in the first region adjacent to a sidewall of the memory gate;
a second select gate disposed adjacent to the first select gate in the first region such that the first select gate is disposed
between the memory gate and the second select gate;

a sidewall dielectric disposed between the sidewall of the memory gate and the first select gate; and
a dielectric layer disposed beneath the first select gate and the second select gate, wherein the dielectric layer is disposed
such that it is separated from the charge trapping layer and the memory gate by the sidewall dielectric.

US Pat. No. 9,317,475

MULTIPLEXING AUXILIARY PROCESSING ELEMENT AND SEMICONDUCTOR INTEGRATED CIRCUIT

Cypress Semiconductor Cor...

1. A method of using a multiplexing auxiliary processing element (PE), comprising:
receiving input signals from a plurality of upstream processing elements (PEs) arranged on an input side, wherein each of
the input signals includes a plurality of data bits and one or more valid signal bits;

comparing the one or more valid signal bits with a configuration signal;
if a predetermined condition is satisfied, supplying the input signals to a multiplex PE, wherein the multiplex PE processes
the input signals to generate processed signals;

delaying the one or more valid signal bits by a designated cycle;
receiving, from the multiplex PE, the processed signals; and
supplying, in accordance with the delayed one or more valid signal bits, the processed signals to a plurality of downstream
PEs arranged on an output side.

US Pat. No. 9,292,091

FEEDBACK MECHANISM FOR USER DETECTION OF REFERENCE LOCATION ON A SENSING DEVICE

Cypress Semiconductor Cor...

1. A method comprising:
determining a first position of a conductive object, manipulated by a user, proximate to a touch-screen;
determining a proximity of the first position to a reference location of the touch-screen;
determining, by a processing device, a first active feedback attribute based on the proximity of the first position to the
reference location, wherein an active feedback attribute is variable according to a proximity of the conductive object and
the reference location; and

providing a first active feedback having the first active feedback attribute to the user to allow detection of the reference
location on the touch-screen by the user, wherein providing the first active feedback includes providing at least a portion
of the first active feedback prior to a key activation associated with the reference location.

US Pat. No. 9,276,007

SYSTEM AND METHOD FOR MANUFACTURING SELF-ALIGNED STI WITH SINGLE POLY

Cypress Semiconductor Cor...

1. A method for manufacturing a memory device, the method comprising:
performing a shallow trench isolation process on a semiconductor material to form a plurality of active regions over the semiconductor
material, the plurality of active regions having a plurality of sharp corners;

forming a plurality of isolation regions separating the plurality of active regions, the plurality of sharp corners of the
plurality of active regions being exposed during the forming of the plurality of isolation regions;

rounding the plurality of sharp corners;
filling the plurality of isolation regions with an insulator material;
forming a plurality of charge trapping structures over the plurality of active regions, wherein the plurality of charge trapping
structures are self-aligned, are separated from each other, and wherein each charge trapping structure corresponds specifically
to a different active region of the plurality of active regions; and

forming a first layer of semiconductor or conductive material over the charge trapping structure.

US Pat. No. 9,263,398

SEMICONDUCTOR PACKAGING IDENTIFIER

Cypress Semiconductor Cor...

1. A semiconductor package frame comprising:
a material comprising a plurality of wire openings;
a die-mounting surface area comprising a die-mounting surface; and
a plurality of identification markings included within the die-mounting surface, the plurality of identification markings
to uniquely identify the semiconductor package frame from among other semiconductor package frames comprising different identification
markings.

US Pat. No. 9,104,284

INTERFACE AND SYNCHRONIZATION METHOD BETWEEN TOUCH CONTROLLER AND DISPLAY DRIVER FOR OPERATION WITH TOUCH INTEGRATED DISPLAYS

Cypress Semiconductor Cor...

1. An apparatus comprising:
a display panel comprising a substrate and a shared layer of electrodes for touch functionality and display functionality;
a plurality of storage elements to store an excitation signal pattern to control how the shared layer of electrodes is driven
by excitation signals for multi-phase capacitance scanning of the display panel; and

an integrated circuit (IC) positioned on the substrate and coupled to the shared layer of electrodes, wherein the IC to drive
the shared layer of electrodes with display signals in a first mode and to drive the shared layer of electrodes with a plurality
of excitation signals in a second mode according to the pattern of excitations signals stored in the plurality of storage
elements, wherein the excitation signal pattern comprises a data structure of values for the plurality of excitation signals,
and wherein each of the values is at least one of a first value that indicates an in-phase excitation signal to be applied
to a corresponding electrode of the shared layer of electrodes, a second value that indicates an out-of-phase excitation signal
to be applied to the corresponding electrode or a third value that indicates a high-impedance output to remove the IC's influence
on the corresponding electrode, and wherein the data structure comprises at least one of the third value.

US Pat. No. 9,299,643

RUTHENIUM INTERCONNECT WITH HIGH ASPECT RATIO AND METHOD OF FABRICATION THEREOF

Cypress Semiconductor Cor...

1. An electronic structure comprising:
a first conductive body, wherein the first conductive body is a silicide layer formed on and in contact with a source/drain
of a transistor, a gate oxide and a gate, wherein the gate is a word line of a memory array;

a second conductive body, wherein the second conductive body is a bit line of the memory array;
a dielectric layer between and in contact with the first and second conductive bodies, the dielectric layer defining an opening
therethrough, an upper surface of the dielectric layer forming a plane, the second conductive body formed on the upper surface,
wherein the dielectric layer comprises a silicon nitride layer;

an adhesion layer within the opening in the dielectric layer; and
an elongated electrically conductive interconnect in the opening providing electrically conductive connection between the
first and second conductive bodies, the electrically conductive interconnect comprising ruthenium, wherein the ruthenium entirely
fills the opening in the dielectric layer;

wherein the ratio of the length of the electrically conductive interconnect to the minimum cross-sectional width of the electrically
conductive interconnect is 20:1 or greater wherein a portion of the first conductive body extends laterally beyond the sides
of the ruthenium body and wherein respective portions of the first conductive body do not laterally extend beyond the furthest
lateral endpoints of the source/drain of the transistor.

US Pat. No. 9,281,384

ULTRAVIOLET BLOCKING STRUCTURE AND METHOD FOR SEMICONDUCTOR DEVICE

Cypress Semiconductor Cor...

1. A semiconductor device comprising:
an oxide-nitride-oxide (ONO) film formed on a semiconductor substrate;
a gate electrode formed on the ONO film;
a lower layer insulation film formed on the ONO film and the gate electrode; and
an ultraviolet (UV) blocking layer comprising
a plurality of granular particles scattered in one or more insulation films formed on the lower layer insulation film,
wherein each particle of the plurality of granular particles has a first extinction coefficient,
wherein each insulation film of the one or more insulation films has a second extinction coefficient,
wherein the first extinction coefficient of a first particle is higher than the second extinction coefficient of a first insulation
film corresponding to the first particle,

wherein at least one of the one or more insulation films comprises Boron-Phosphorous Silicate Glass (BPSG), and
a plurality of stacked curved portions physically separated by a plurality of metal plugs above the lower layer insulation
film and the ONO film,

wherein at least a first metal plug of the plurality of metal plugs contacts the semiconductor substrate.

US Pat. No. 9,196,495

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Cypress Semiconductor Cor...

1. A semiconductor device comprising:
a semiconductor substrate comprising a groove;
a bit line that is formed on both sides of the groove in the semiconductor substrate and acts as a source and a drain, the
bit line has a different conductivity type than the semiconductor substrate;

a pocket implantation region that has a similar conductivity type as the semiconductor substrate and has a dopant concentration
higher than that of the semiconductor substrate, the pocket implantation region and the bit line form a PN junction, the bit
line is located on a part of the pocket implantation region, side surfaces of the lower half of the groove are free of the
pocket implantation region;

a bottom insulating membrane that is formed on and contacts a side surface of the groove; and
a charge accumulation layer that is formed on and contacts a side surface of the bottom insulating membrane.

US Pat. No. 9,412,598

EDGE ROUNDED FIELD EFFECT TRANSISTORS AND METHODS OF MANUFACTURING

CYPRESS SEMICONDUCTOR COR...

1. A method comprising:
forming a tunneling dielectric region on a substrate;
forming a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping
region by depositing a nitride or silicon rich nitride layer, forming an oxide layer on the nitride or silicon rich nitride
layer, etching back the oxide layer and a portion of the nitride or silicon rich nitride layer, and then oxidizing a portion
of the remaining nitride or silicon rich nitride layer to form an oxynitride or silicon oxynitride layer on a final nitride
or silicon rich nitride layer;

nitridating a surface of the blocking dielectric region;
forming a gate region on the nitridated blocking dielectric region; and
oxidizing the gate region to form a sidewall dielectric layer, wherein edge encroachment of the gate region during oxidizing
the gate region to form the sidewall dielectric layer is suppressed by the nitridated blocking dielectric region.

US Pat. No. 9,298,531

WATCHDOG TIMER WITH MODE DEPENDENT TIME OUT

Cypress Semiconductor Cor...

1. A method comprising:
receiving an indication of a change in a mode of operation in a processing system having a time out functionality, wherein
the change in the mode of operation comprises at least one of a change in operating frequency of the processing system or
a change in power used by the processing system;

changing a first time out period to a second time out period in response to the change in the mode of operation; and
in response to an expiration of the second time out period, providing a signal to the processing system.

US Pat. No. 9,218,978

METHOD OF ONO STACK FORMATION

Cypress Semiconductor Cor...

1. A method, comprising:
forming a dielectric stack on a wafer, wherein the dielectric stack includes tunneling dielectric on the wafer, a charge-trapping
layer, and a cap layer overlaying the charge-trapping layer;

patterning the dielectric stack to form a non-volatile (NV) gate stack of a non-volatile memory (NVM) transistor in a first
region of the wafer while concurrently removing the dielectric stack in a second region of the wafer; and

performing a two-step gate oxidation process to concurrently oxidize at least a first portion of the cap layer of the NV gate
stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second
region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second
oxidation step of the two-step gate oxidation process.

US Pat. No. 9,152,496

HIGH PERFORMANCE FLASH CHANNEL INTERFACE

CYPRESS SEMICONDUCTOR COR...

1. A method comprising:
configuring a flash memory controller to be connected to a first flash memory device to facilitate executing flash memory
access operations on a first subset of data associated with the first flash memory device;

analyzing a block of data, comprising the first subset of data and error correction information associated with the first
subset of data, as the block of data is being read from the first flash memory device and transferred to a buffer to facilitate
detecting and correcting one or more erroneous bits of data in the first subset of data based at least in part on the error
correction information;

storing the first subset of data and the error correction information in the buffer after the analyzing of the block of data;
correcting the one or more erroneous bits of data in the first subset of data based at least in part on the error correction
information while the first subset of data and the error correction information are stored in the buffer to produce a first
subset of corrected data, based at least in part on results obtained from the analyzing of the first subset of data and the
error correction information, wherein, to facilitate the correcting of the one or more erroneous bits of data in the first
subset of data while the first subset of data and the error correction information are stored in the buffer, the buffer has
a storage size that is sufficient to simultaneously store the first subset of data and the error correction information of
the block of data when the block of data is transferred to the buffer, wherein the error correction information is a set of
redundant bytes of data, wherein the set of redundant bytes of data was generated in connection with a write operation to
write the first subset of data to the first flash memory device, associated with the first subset of data, and stored with
the first subset of data in the first flash memory device during the write operation, and is usable to facilitate the correcting
of the one or more erroneous bits of data; and

transferring the first subset of corrected data as an output from the buffer.

US Pat. No. 9,455,027

POWER MANAGEMENT SYSTEM FOR HIGH TRAFFIC INTEGRATED CIRCUIT

Cypress Semiconductor Cor...

1. An integrated circuit (IC) device, comprising:
a memory array section comprising a plurality of memory arrays that each include memory cells for storing data values;
a data path section having switching circuits configured to enable data paths between the memory arrays and a plurality of
input/outputs (I/Os) of the IC device;

a power fill control circuit configured to activate power-fill circuits in the IC device to perform non-mission mode operations
that consume current, the amount of non-mission mode operations varying in response to mission mode circuit activity in the
IC device; and

at least one power-fill configuration register;
wherein the amount of non-mission mode operations is configurable according to a data value stored in the power-fill configuration
register; and

wherein mission mode circuit activity includes circuit activity resulting from a user input to the IC device.

US Pat. No. 9,196,496

METHOD OF INTEGRATING A CHARGE-TRAPPING GATE STACK INTO A CMOS FLOW

CYPRESS SEMICONDUCTOR COR...

8. A method comprising:
forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the
surface of the substrate and a charge-trapping layer on the tunneling dielectric;

forming a cap layer on the charge-trapping layer;
patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate
and to remove the cap layer and the charge-trapping layer from a second region of the substrate; and

removing at least a portion of the cap layer in the first region of the substrate;
performing an oxidation process to form a gate oxide overlying the surface of the substrate in the second region while concurrently
oxidizing a remaining portion of the cap layer to form a blocking oxide on the charge-trapping layer.

US Pat. No. 9,167,647

CONTROL CIRCUIT AND CONTROL METHOD FOR DIMMING A LIGHTING DEVICE

Cypress Semiconductor Cor...

1. A control circuit comprising:
a power supply unit that includes a first switch which is turned on and off in response to a drive signal and a second switch
which is turned on and off in response to a control signal, the power supply unit configured to generate a voltage to be supplied
to a load by turning on and off the first switch and control a flow of a drive current to the load by turning on and off the
second switch:

a first controller configured to perform a first PWM control of the drive signal, based on a measurement value of the drive
current;

a second controller configured to perform a second PWM control of the control signal, based on an external signal; and
a synchronous controller configured to synchronize an on-period of one period of the control signal to be a multiple of one
period of the drive signal,

wherein, during the on-period of the control signal, an inductor current for generating the drive current is cut off for a
portion of every period of the drive signal.

US Pat. No. 9,425,691

LOW THERMAL DESIGN FOR DC-DC CONVERTER

CYPRESS SEMICONDUCTOR COR...

1. A DC-DC converter comprising:
an input terminal receiving voltage input;
first and second switching circuits connected in parallel between the input terminal and a ground;
an output terminal outputting converted voltage; and
a controller configured to operate the first and second switching circuits in first and second predetermined cycles by inputting,
into each of the first and second switching circuits, a control signal that turns the first and second switching circuits
on individually, wherein during the first predetermined cycle, the first switch circuit is turned on first, and during the
second predetermined cycle, the second switch circuit is turned on first.

US Pat. No. 9,317,445

RAPID MEMORY BUFFER WRITE STORAGE SYSTEM AND METHOD

Cypress Semiconductor Cor...

1. A memory write method comprising:
issuing a first program command to a memory;
loading data into a buffer of said memory;
breaking page program commands into a first phase in which at least a portion of a data input command cycle is forwarded to
said memory, and a second phase in which at least a portion of a load command cycle with row address information is forwarded
to said memory, wherein said portion of said data input command cycle is forwarded before said portion of said load command
cycle with row address information; and

issuing a program confirm command.

US Pat. No. 9,299,568

SONOS ONO STACK SCALING

Cypress Semiconductor Cor...

1. A method of fabricating a nonvolatile trapped-charge memory device, comprising:
forming a channel region in a substrate, the channel region electrically connecting a source region and a drain region in
the substrate, wherein the channel region comprises polysilicon;

forming a tunneling layer on the substrate over the channel region, wherein forming the tunneling layer comprises oxidizing
the substrate to form an oxide film and nitridizing the oxide film;

forming a multi-layer charge trapping layer comprising an oxygen-rich first layer on the tunneling layer and an oxygen-lean
second layer over the first layer; and

forming a blocking layer on the multi-layer charge trapping layer,
wherein forming the multi-layer charge trapping layer further comprises forming an anti-tunneling layer comprising an oxide
separating the first layer from the second layer.

US Pat. No. 9,293,063

FINGER POSITION SENSING FOR HANDHELD SPORTS EQUIPMENT

Cypress Semiconductor Cor...

1. A device, comprising:
a receiving surface for at least one human hand to grip thereon;
a plurality of capacitive sensor elements disposed within at least one location on the receiving surface, wherein the capacitive
sensor elements generate capacitance measurements;

a sense circuit coupled to the capacitive sensor elements configured to compare the capacitance measurements with threshold
capacitance values, wherein the sense circuit is further configured to generate a signal when the capacitance measurements
indicate close proximity of at least a portion of the at least one human hand to the capacitive sensor elements; and

an indicator configured to receive the signal from the sense circuit and generate an indicator notification when the position
of the at least one human hand relative to the receiving surface corresponds with the at least one location on the receiving
surface.

US Pat. No. 9,122,288

LOW POWER USB 2.0 SUBSYSTEM

Cypress Semiconductor Cor...

1. A USB physical layer subsystem comprising:
a protection circuit including a power supply interface and a plurality of pin interfaces;
a pin identifier circuit in communication with the protection circuit for detecting a device coupling to a pin connected to
a pin interface of the plurality of pin interfaces;

a USB physical interface; and
a dual power supply regulator including a first regulator, a second regulator, and a third regulator, the dual power supply
configured to receive power via the power supply interface from an external power supply, to continuously supply a first voltage
to the protection circuit, and to selectively provide a second voltage and a third voltage to the pin identifier circuit and
the USB physical interface, wherein the second regulator is configured to supply the second voltage to the third regulator.

US Pat. No. 9,400,298

CAPACITIVE FIELD SENSOR WITH SIGMA-DELTA MODULATOR

Cypress Semiconductor Cor...

1. A capacitive sensor, comprising:
a switching capacitor circuit to reciprocally couple a sensing capacitor in series with a modulation capacitor during a first
switching phase and to discharge the sensing capacitor during a second switching phase;

a comparator coupled to compare a voltage potential on the modulation capacitor to a reference and to generate a modulation
signal in response; and

a charge dissipation circuit coupled to the modulation capacitor to selectively discharge the modulation capacitor in response
to the modulation signal.

US Pat. No. 9,368,588

INTEGRATED CIRCUITS WITH NON-VOLATILE MEMORY AND METHODS FOR MANUFACTURE

CYPRESS SEMICONDUCTOR COR...

1. A method of manufacturing a semiconductor device that includes a first region, a second region, and a third region, comprising:
forming a select gate in the first region;
forming a first logic gate in the second region;
disposing a charge trapping dielectric in the first, second, and third regions;
removing the charge trapping dielectric from the third region;
disposing a gate conductor layer on the third region and over the charge trapping dielectric in the first and second regions;
and

etching the gate conductor layer to define a memory gate on a sidewall of the select gate and a second logic gate in the third
region.

US Pat. No. 9,319,162

SIGNAL PROCESSOR AND COMMUNICATION DEVICE

Cypress Semiconductor Cor...

1. A signal processor configured to allow a communication device to recognize the end of communication of a frame, based on
a received signal, and to start a communication action of a next frame, the signal processor comprising:
a controller configured to halt a beginning of the communication action of the next frame;
an output processing section configured to instruct the controller to halt the beginning of the communication action of the
next frame, upon detection of a first signal pattern in a period currently being used for communication of the frame, and
until the period currently being used for communication of the frame ends, and

wherein the output processing section is further configured to output the received signal to the controller.

US Pat. No. 9,142,209

DATA PATTERN ANALYSIS

CYPRESS SEMICONDUCTOR COR...

1. An apparatus comprising:
a controller; and
a plurality of senone scoring units configured to receive a plurality of senone scoring requests from the controller and to
concurrently provide a plurality of senone scores for one or more portions of a data stream.

US Pat. No. 9,493,874

DISTRIBUTION OF GAS OVER A SEMICONDUCTOR WAFER IN BATCH PROCESSING

CYPRESS SEMICONDUCTOR COR...

1. An apparatus for injecting gas onto a wafer, the apparatus comprising:
an arrangement comprising a plurality of wafers configured for batch processing;
a plurality of injectors, wherein an outlet of each injector of the plurality of injectors is aligned with a plane of a corresponding
wafer of the plurality of wafers and is configured to direct a corresponding portion of a gas substantially parallel to the
plane of the corresponding wafer; and

a plurality of rectification wings, wherein:
each pair of rectification wings from among the plurality of rectification wings is coupled to a corresponding injector of
the plurality of injectors and is configured to deflect the corresponding portion of the gas away from a center of the corresponding
wafer;

at least one rectification wing from among the plurality of rectification wings extends along the plane of the corresponding
wafer and overlaps at least a portion of the corresponding wafer; and

the outlet of each injector of the plurality of injectors is interposed between a corresponding pair of rectification wings
from among the plurality of rectification wings.

US Pat. No. 9,378,821

ENDURANCE OF SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) MEMORY CELLS

Cypress Semiconductor Cor...

1. A method comprising:
controlling a pulse shape of a pulse signal to include four or more phases for both programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon
(SONOS) memory cell during a write cycle, wherein the controlling the pulse shape further includes

controlling a first ramp rate of the pulse signal, and
controlling a second ramp rate, which is different from the first ramp rate, of the pulse signal; and
performing the write cycle to program or erase the SONOS memory cell each with the pulse signal with the four or more phases.

US Pat. No. 9,293,420

ELECTRONIC DEVICE HAVING A MOLDING COMPOUND INCLUDING A COMPOSITE MATERIAL

Cypress Semiconductor Cor...

1. An electronic device, comprising:
an integrated circuit die having a top surface; and
a molding compound encapsulating the integrated circuit die, the molding compound comprising approximately 20 wt % to approximately
25 wt % zinc and a concentration of zinc of approximately 0.2 ?mol/cm2 to approximately 0.5 ?mol/cm2, wherein the zinc is provided in the form of zinc borate.

US Pat. No. 9,252,221

FORMATION OF GATE SIDEWALL STRUCTURE

Cypress Semiconductor Cor...

1. A method of making a semiconductor device, comprising:
forming a gate stack on a substrate, wherein the gate stack includes a mask layer disposed over an additional mask layer that
is disposed between the mask layer and a first gate conductor layer;

laterally etching the first gate conductor layer so that an overhanging portion of the mask layer extends beyond the additional
mask layer and the first gate conductor layer in a direction parallel to a surface of the substrate;

forming a sidewall structure layer such that the sidewall structure layer is disposed beneath the overhanging portion of the
mask layer; and

removing the mask layer.

US Pat. No. 9,400,546

LOW-POWER IMPLEMENTATION OF TYPE-C CONNECTOR SUBSYSTEM

CYPRESS SEMICONDUCTOR COR...

1. A device comprising:
a processor; and
a Universal Serial Bus (USB) Type-C subsystem, wherein the Type-C subsystem is configured at least to:
operate an Ra termination circuit coupled to a Vconn line of the Type-C subsystem, wherein the Ra termination circuit consumes
no more than 100 ?A of current after being applied to the Vconn line; and

operate one or more standby reference circuits in a deep-sleep state of the device to perform detection on a Configuration
Channel (CC) line of the Type-C subsystem, wherein the device consumes no more than 100 ?A of current in the deep-sleep state;

wherein to operate the Ra termination circuit, the Type-C subsystem is configured to:
maintain the Ra termination circuit “ON” while the Type-C subsystem is unpowered;
detect when the Vconn line is powered; and
enable a negative charge pump when the Vconn line reaches above a threshold voltage, in order to disable the Ra termination
circuit;

wherein the device is an integrated circuit (IC) chip.

US Pat. No. 9,310,953

FULL-WAVE SYNCHRONOUS RECTIFICATION FOR SELF-CAPACITANCE SENSING

Cypress Semiconductor Cor...

1. An apparatus comprising:
a first integrating capacitor;
a first modulator operatively coupled to the first integrating capacitor;
a second integrating capacitor; and
a second modulator operatively coupled to the second integrating capacitor, wherein the first modulator in conjunction with
the first integrating capacitor and the second modulator in conjunction with the second integrating capacitor measure a self-capacitance
of a capacitive-sense array by performing a full-wave synchronous rectification.

US Pat. No. 9,442,144

CAPACITIVE FIELD SENSOR WITH SIGMA-DELTA MODULATOR

Cypress Semiconductor Cor...

8. A method comprising:
responsive to a charging signal, charging a modulation capacitor based on a capacitance of a sensing capacitor;
generating a modulation signal having a characteristic that changes in a first direction in response to a change in capacitance
of the sensing capacitor and changes in a second direction in response to noise.

US Pat. No. 9,362,287

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Cypress Semiconductor Cor...

1. A semiconductor device comprising:
a first transistor and a second transistor disposed in or on a silicon substrate;
a first well disposed in a formation area of the first transistor, and a second well disposed in a formation area of the second
transistor, wherein the second well surrounds the first well in a plan view of the silicon substrate; and

a third well disposed under an entirety of the first well, but less than an entirety of the second well, and wherein the third
well is electrically connected to the second well,

wherein the semiconductor device does not include an element isolation structure including an element isolation film disposed
in the silicon substrate between the first transistor and the second transistor, and wherein the first transistor is an N-type
transistor, the second transistor is a P-type transistor, the first well is a P-well, the second well is an N-well, and the
third well is an N-well.

US Pat. No. 9,299,578

TRANSISTOR FORMATION METHOD USING SIDEWALL MASKS

Cypress Semiconductor Cor...

1. A method for fabricating a semiconductor device comprising:
forming a first film on a base layer;
forming a first mask pattern on the first film, the first mask pattern having first mask portions and sidewalls, wherein a
width of each of the first mask portions and a space between adjacent first mask portions are the same;

forming first sidewall films on the sidewalls of the first mask pattern by etch back of a deposited second film, each of the
first sidewall films comprising a vertical side surface and a curved side surface;

removing the first mask pattern;
forming second sidewall films by etchback of a deposited third film on the first sidewall films, the second sidewall films
comprising first portions adjacent to the vertical side surfaces and second portions adjacent to the curved side surfaces
of the first sidewall films;

wherein the first portions of the second sidewall films have a width of one-quarter the width of each first mask portion,
and wherein the first sidewall films and the second sidewall films define portions of a second mask pattern.

US Pat. No. 9,280,421

ERROR CORRECTION FOR FLASH MEMORY

CYPRESS SEMICONDUCTOR COR...

1. A computer system that corrects bit errors in a memory device, comprising:
at least one of a computer or a distributed computer network further comprising a set of memory cells within the memory device
and at least one processor;

a reference component that executes a program on the at least one processor to establish a suspect region between bit level
distributions of the set of memory cells, wherein the bit level, distributions comprise respective ranges of memory cell values
that correspond respectively with a program state or an erase state of the set of memory cells, and the suspect region defines
suspected error bits of the set of memory cells; and

an error detection component that executes a swapping algorithm on the at least one processor, configured to change a logical
association of one or more bits to a subset of the suspected error bits in an order related to a probability of error, wherein
one of the suspected error bits is identified as an error bit or as a non-error bit by the execution of the swapping algorithm
on the at least one processor.

US Pat. No. 9,142,301

DATA WRITING METHOD AND SYSTEM

Cypress Semiconductor Cor...

1. A data writing method for writing data to a flash memory comprising a data storage area and an error correction code storage
area, the method comprising:
writing an initial value to the data storage area;
setting a write flag based on the writing of the initial value;
determining, based on the write flag, whether or not the writing of the initial value is performed normally;
writing data to the data storage area when the writing is performed normally; and
erasing a block comprising the data storage area when the writing is not performed normally.

US Pat. No. 9,142,311

SCREENING FOR REFERENCE CELLS IN A MEMORY

CYPRESS SEMICONDUCTOR COR...

1. A method, comprising:
selecting an array from among a plurality of arrays in a memory as a reference array;
evaluating memory cells within the reference array to select a first reference cell associated with a first operation of the
memory, the evaluating comprising:

selecting a memory cell as the first reference cell when a threshold voltage associated with the memory cell is within a target
voltage range;

obtaining a plurality of measured RTN values from the memory cells within the reference array;
calculating a delta RTN value by taking a difference between two measured RTN values of the memory cells within the reference
array; and

determining whether the delta RTN value is less than a predetermined target RTN value of the first reference cell.

US Pat. No. 9,098,270

DEVICE AND METHOD OF ESTABLISHING SLEEP MODE ARCHITECTURE FOR NVSRAMS

CYPRESS SEMICONDUCTOR COR...

1. A method of operating a device alternatively in a normal power mode, an auto-store power mode and a sleep power mode, wherein
the device is configured to be divided into a normal, an auto-store and a sleep power domains, the method comprising:
receiving an indication at the sleep power domain to transition the device from the sleep power mode into the normal power
mode;

monitoring a state of the auto-store power domain during the transition;
storing an n-bit semaphore value by a controller in a particular storage location in the auto-store power domain when the
state of the auto-store power domain is such that reliable data transfer may take place to and from circuits outside of the
auto-store power domain;

monitoring contents of the particular storage location in an ongoing fashion, wherein the particular storage location is a
register; and

removing isolation for signals to and from the auto-store power domain.

US Pat. No. 9,431,503

INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE

CYPRESS SEMICONDUCTOR COR...

1. An integrated circuit, comprising: at least one first poly-silicon gate region including a first poly-silicon layer, a
second poly-silicon layer disposed over the first poly-silicon layer, a plurality of first poly-silicon fingers associated
with the first poly-silicon layer, and at least one second poly-silicon finger associated with the second poly-silicon layer,
wherein the plurality of first poly-silicon fingers and the at least one second poly-silicon finger are orientated in a substantially
orthogonal manner relative to each other; and wherein a gap between adjacent ones of the first poly-silicon fingers is filled
with silicon oxide having a same thickness as a thickness of the first poly-silicon fingers; and at least one second poly-silicon
gate region including the first poly-silicon layer, wherein the at least one first poly-silicon gate region and the at least
one second poly-silicon gate region each have different poly-silicon gate structures.

US Pat. No. 9,361,994

METHOD OF INCREASING READ CURRENT WINDOW IN NON-VOLATILE MEMORY

Cypress Semiconductor Cor...

1. A memory structure comprising:
an array of cells arranged in rows and columns, each cell including a non-volatile memory (NVM) transistor having a body bias
terminal; and

a control system to adjust a body bias voltage coupled to the body bias terminals during read operations compensate for shifts
in threshold voltages (VTH) of the NVM transistors to maintain a read current window (IRCW) between a cell in which the NVM transistor is ON and a sum of leakage current through cells in which the NVM transistor
is OFF.

US Pat. No. 9,355,725

NON-VOLATILE MEMORY AND METHOD OF OPERATING THE SAME

Cypress Semiconductor Cor...

1. A memory structure comprising:
a memory array of a plurality of memory cells arranged in rows and columns, the plurality of memory cells including a first
pair of adjacent memory cells in a row of the memory array,

wherein the first pair of adjacent memory cells comprise a first shared source-line formed from a first metal layer deposited
over transistors in the memory cells through which each of the memory cells in the first pair of adjacent memory cells is
coupled to a voltage source,

wherein the first metal layer further includes a first pad and a width of each memory cell in the row of the memory array
is substantially equal to a sum of a ½ a width of the first shared source-line, a first spacing between the first shared source-line
and the first pad, a width of the first pad, and a ½ a second spacing between the first pad and a second pad in a second pair
of adjacent memory cells.

US Pat. No. 9,334,578

ELECTROPLATING APPARATUS AND METHOD WITH UNIFORMITY IMPROVEMENT

Cypress Semiconductor Cor...

1. An electroplating system, comprising:
a divided electrode that includes a conductive disc that is divided into a plurality of separate electrode elements, each
electrode element having a plurality of electrode fingers, wherein the divided electrode is arranged to substantially simultaneously
provide a plurality of line currents for an electroplating process via the plurality of separate electrode elements;

a power supply; and
a current control component arranged between the divided electrode and the power supply, wherein the current control component
comprises:

a plurality of current control elements coupled to the divided electrode, wherein each of the plurality of current control
elements is configured to sense a magnitude of a corresponding one of the plurality of line currents and generate a corresponding
sensing signal, and

a controller circuit coupled to the plurality of current control elements, the controller circuit includes a processor that
is configured to receive the corresponding sensing signal and generate a corresponding feedback signal to each of the plurality
of current control elements.

US Pat. No. 9,143,322

COMMUNICATION APPARATUS, DATA COMMUNICATION METHOD, AND NETWORK SYSTEM

Cypress Semiconductor Cor...

1. A communication apparatus, comprising:
a storage part configured to store a first key generated according to authentication with a transmission source on a network;
a determining part configured to determine whether a topology of the network has changed in response to an initialization
of a coupling status;

an acquisition part configured to acquire a public key, in response to the determining part determining that the topology
of the network has changed, from the transmission source corresponding to first information, wherein the first information
comprises an isochronous channel number of the transmission source;

a selecting part configured to select the first key responsive to the isochronous channel number; and
a calculation part configured to generate an encryption key for encryption or decryption of data transmitted by the transmission
source, based on the first key, and the public key.

US Pat. No. 9,124,264

LOAD DRIVER

Cypress Semiconductor Cor...

1. A method comprising:
receiving an input signal;
determining an appropriate output voltage based on the input signal;
determining a desired output voltage range based on the input signal;
configuring an output driver to a first mode of operation to drive an output terminal to a first voltage within the desired
output voltage range; and

configuring the output driver to a second mode of operation to take place in response to the output terminal voltage reaching
the first voltage within the desired output voltage range, wherein the output driver to drive the output terminal to a second
voltage approximately equal to the appropriate output voltage.

US Pat. No. 9,508,736

THREE-DIMENSIONAL CHARGE TRAPPING NAND CELL WITH DISCRETE CHARGE TRAPPING FILM

Cypress Semiconductor Cor...

1. A three-dimensional semiconductor device, comprising:
a substrate;
a plurality of insulating layers;
a plurality of second functional elements interleaved with the plurality of insulating layers, inner walls of the plurality
of insulating layers and the plurality of second functional elements defining a channel hole, and each second functional element
and adjacent insulating layers defining a recess;

a first functional element disposed in the channel hole and extending vertically from the substrate; and
a plurality of charge trap structures, each disposed between the first functional element and a corresponding second functional
element,

wherein the charge trap layers each comprises at least three sub-layers, wherein the at least three sub-layers comprise a
first oxide layer and a second oxide layer;

wherein each of the charge trap layers is separate and discrete from the other charge trap layers; and
wherein the charge trap layers share the first oxide layer, and wherein the first oxide layer is in physical contact with
the first functional element and extends into the recesses.

US Pat. No. 9,362,293

CT-NOR DIFFERENTIAL BITLINE SENSING ARCHITECTURE

CYPRESS SEMICONDUCTOR COR...

1. A semiconductor memory device, comprising:
a first array of transistors arranged electrically in serial from source to drain, one end of the first array is electrically
coupled to a gate of a pass transistor and an opposite end of the first array is electrically coupled to a metal bitline of
the semiconductor memory device; and

a second metal bitline coupled to a first end of a channel region and the metal bitline coupled to a second end of the channel
region of the pass transistor, wherein a state of a transistor of the first array of transistors is determined from a difference
in an electrical characteristic of the metal bitline relative to the second metal bitline.

US Pat. No. 9,262,340

PRIVILEGED MODE METHODS AND CIRCUITS FOR PROCESSOR SYSTEMS

Cypress Semiconductor Cor...

1. A system, comprising:
a processor coupled to a bus;
protection registers coupled to the bus, the protection registers configured to store first protection values and second protection
values;

a first memory coupled to the bus, the first memory including a privileged portion;
a second memory coupled to the bus, the second memory including a privileged supervisory portion, wherein the first protection
values are configured to limit access to the privileged portion and the privileged supervisory portion according to a first
protection mode and the second protection values are configured to limit access to the privileged portion and the privileged
supervisory portion according to a second protection mode;

a boot sequence stored in the privileged portion that configures the processor to decode first values stored in the supervisory
portion into the first protection values;

an interrupt handler configured to place a processor into a privileged mode to access second values stored in the supervisory
portion to decode the second values into the second protection values; and

a privileged mode emulation circuit comprising a storage element accessible by a system call to the privileged portion of
the first memory in response to a nonmaskable interrupt (NMI) to the processor, the storage element having a privileged mode
output coupled to a signal line of the bus, wherein the values of the storage element establish the privileged mode for the
system.

US Pat. No. 9,177,616

SUPPLY POWER DEPENDENT CONTROLLABLE WRITE THROUGHPUT FOR MEMORY APPLICATIONS

Cypress Semiconductor Cor...

1. A method of managing throughput in a memory device, comprising:
monitoring a power supply level;
determining an appropriate memory write throughput based on a number of cells to which the memory device can write at a time
at the monitored power supply level;

generating a control signal based on the determined memory write throughput, wherein the control signal is configured to cause
a driver circuit to activate a portion of a memory array consistent with said determined memory write throughput.

US Pat. No. 9,103,658

OPTICAL NAVIGATION MODULE WITH CAPACITIVE SENSOR

Cypress Semiconductor Cor...

12. An optical navigation module comprising:
a light source to illuminate at least a portion of a surface relative to which the optical navigation module is moved; and
an integrated circuit (IC) including a photo-detector array (PDA) to detect a light pattern propagated onto the PDA from the
surface;

a signal processor to translate changes in the light pattern propagated onto the PDA into data representing motion of the
optical navigation module relative to the surface;

a substrate overlying and affixed to the IC, wherein the substrate comprises an optically opaque material and is patterned
to form an aperture in a light path between the surface and the PDA;

a capacitive sensor configured to detect a lift height between the surface and the optical navigation module; and
a controller electrically coupled to the capacitive sensor and IC, the controller programmable to specify a maximum lift height
at which the optical navigation module can track due to variations in roughness or pigmentation of the surface.

US Pat. No. 9,750,097

STOCHASTIC SIGNAL DENSITY MODULATION FOR OPTICAL TRANSDUCER CONTROL

Cypress Semiconductor Cor...

1. A method comprising:
generating a first signal with a stochastic density;
comparing the first signal to an input signal with a density register value;
generating a modulation signal from the comparing the first signal and input signal; and
driving a controllable current supply with the modulation signal, the controllable current supply coupled to a light-emitting
diode (LED).

US Pat. No. 9,490,126

RESISTIVE MEMORY ARRAY USING P-I-N DIODE SELECT DEVICE AND METHODS OF FABRICATION THEREOF

Cypress Semiconductor Cor...

1. An electronic structure comprising:
a resistive memory device; and
a P-I-N diode in operative association with the resistive memory device, wherein the electronic structure is a pillar, wherein
the P-I-N diode comprises a body comprising a first region of a first selected conductivity type, a second region of a second
selected conductivity type opposite the first conductivity type, and an intrinsic region between the first and second regions,
wherein the first and second regions and the intrinsic region are stacked in a column, wherein the first region is linearly
elongated such that the first region forms a first selected conductivity type region of a second P-I-N diode of a linear plurality
of P-I-N diodes and each of the first region, the second region and the intrinsic region of each P-I-N diode of the linear
plurality of P-I-N diodes are of similar dimensions to each of the first region, the second region, and the intrinsic region
of another P-I-N diode of the linear plurality of P-I-N diodes, and wherein the first region that is linearly elongated corresponds
to a bit line associated with the resistive memory device.

US Pat. No. 9,461,562

LOW VOLTAGE DETECTOR

CYPRESS SEMICONDUCTOR COR...

1. An apparatus comprising:
a voltage monitoring device to generate a brownout indication; and
a mode control device configured to receive a sampled power supply voltage, and further configured to adjust a temporal response
of the voltage monitoring device from a first mode to a second mode in response to the sampled power supply voltage dropping
below a first threshold voltage level, the temporal response being a response time of the voltage monitoring device to a change
in the power supply voltage, wherein the voltage monitoring device has a faster temporal response in the second mode as compared
to the first mode, and

wherein the voltage monitoring device is configured to generate the brownout indication signal based on the mode of the voltage
monitoring device and in response to sampled power supply voltage dropping below a second threshold voltage level.

US Pat. No. 9,431,549

NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION

Cypress Semiconductor Cor...

1. A memory device comprising:
a channel electrically connecting a first diffusion region and a second diffusion region of the memory device; and
a gate stack adjoining at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a
charge-trapping layer abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the charge-trapping layer,

wherein the charge-trapping layer includes a first charge-trapping layer comprising an oxygen-rich nitride closer to the tunnel
oxide, and a second charge-trapping layer comprising a silicon-rich nitride overlying the first charge-trapping layer, and

wherein the multi-layer blocking dielectric comprises a first dielectric layer abutting the charge-trapping layer comprising
an oxidized portion of the second charge-trapping layer and a second dielectric layer abutting the first dielectric layer,
the first dielectric layer having a dielectric constant in the range of 3.5-4.5, and the second dielectric layer comprising
a silicate and having a dielectric constant higher than a dielectric constant of the first dielectric layer.

US Pat. No. 9,306,025

MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE

Cypress Semiconductor Cor...

1. A semiconductor device comprising:
an oxide-nitride-oxide (ONO) dielectric stack on a surface of a substrate, the ONO dielectric stack comprising a multi-layer
charge storage layer including a silicon-rich, oxygen-lean top silicon nitride layer and an oxygen-rich bottom silicon nitride
layer; and

a high work function gate electrode formed over a surface of the ONO dielectric stack, the high work function gate electrode
comprising a P+doped polysilicon layer.

US Pat. No. 9,305,614

MEMORY DEVICE WITH INTERNAL COMBINATION LOGIC

Cypress Semiconductor Cor...

1. A memory integrated circuit (IC), comprising:
a data access component configured to provide an address;
a memory array, coupled to the data access component, configured to receive the address provided by the data access component
and provide data stored at a location associated with the address;

a data holding component, coupled to the memory array, configured to receive the data provided by the memory array; and
a logic component, coupled to the data access component and the data holding component, unrelated to the memory array, configured
to receive the data from the data holding component, execute a dedicated task using the data, and determine if an exit condition
has been met, wherein the exit condition tests whether a search string has been found or whether an end of a graph has been
encountered.

US Pat. No. 9,196,624

LEAKAGE REDUCING WRITELINE CHARGE PROTECTION CIRCUIT

CYPRESS SEMICONDUCTOR COR...

1. A method of fabricating a wordline structure for a flash memory cell, the method comprising:
forming a polysilicon structure adjacent to a core region;
doping the polysilicon structure in a first region adjacent to the core region and in a second region adjacent to a spine
region;

leaving an un-doped region between the first and second regions, the un-doped region having a first end in contact with the
first region and a second end in contact with the second region; and

forming a conductive layer directly on a portion of the un-doped region and one of the first and second regions of the polysilicon
structure and arranged such that the conductive layer does not overlap at least one of the first end and the second end.

US Pat. No. 9,111,985

SHALLOW BIPOLAR JUNCTION TRANSISTOR

Cypress Semiconductor Cor...

1. A shallow bipolar junction transistor comprising:
a high voltage n+ well implanted into a semiconductor substrate;
an oxide nitride oxide (ONO) layer, an n+ collector, and a bit line residual oxide removal (BLROE)/spacer over etch (SPXOE)
layer above said high voltage n+ well;

a bit line n+ implant (BNI) above said high voltage n+ well, wherein a portion of said ONO layer is formed around a portion
of said BNI;

a plurality of emitters in a central region of the transistor, a base laterally separated from the plurality of emitters,
and an n+ core implant surrounding the plurality of emitters to isolate the base and the plurality of emitters, wherein the
n+ core implant defines a difference between said base and an emitter;

a high voltage gate oxide (HVGOX) above said n+ collector and around said base; and
a p+ source/drain implant (PP) layer around said base.

US Pat. No. 9,390,783

MEMORY DEVICES AND SYSTEMS INCLUDING CACHE DEVICES FOR MEMORY MODULES

CYPRESS SEMICONDUCTOR COR...

1. A memory apparatus, comprising:
a memory controller;
a plurality of channel buses coupled to the memory controller, each channel bus configured to receive a plurality of in line
memory modules; and

at least one cached in-line memory module (IMM) coupled to one of the channel buses, the cached IMM including
a substrate comprising connections for interfacing with the one of the channel buses,
a plurality of dynamic random access memory (DRAM) circuits mounted on the substrate, the DRAM circuits configured to store
data at one or more memory addresses, and

a module cache device mounted on the substrate configured to cache the data for the DRAM circuits by storing the data that
is stored by the DRAM circuits, the module cache device configured to output the data stored by the module cache device in
response to receiving an access request corresponding to the one or more memory addresses, without accessing the DRAM circuits
in response to the access request.

US Pat. No. 9,378,165

INTER-BUS COMMUNICATION INTERFACE DEVICE

Cypress Semiconductor Cor...

1. An interface device, comprising:
a buffer coupled to a first bus and a second bus and configured to store communication data received via the first bus;
a register coupled to the first bus and the second bus in parallel to the buffer, wherein the register is configured to store
communication control information received via the first bus, wherein the control information is used to process the communication
data;

a status register configured to store a status of the buffer and the register; and
a control circuit configured to transfer the communication data and the communication control information via the second bus
based on the status stored in the status register.

US Pat. No. 9,330,251

AUTHENTICATING FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) DEVICE AND METHOD

Cypress Semiconductor Cor...

8. A radio frequency identification (RFID) system comprising:
a host system; and
a memory device comprising:
a ferroelectric memory array comprising a user memory space;
control logic configured to provide external read and write access for the host system to the user memory space upon authentication
between the host system and the memory device;

address, data and control buses through which the host system accesses the user memory space and communicates with the control
logic;

a memory interface configured to interface between the address, data and control buses and the control logic, and through
which the host system communicates with the control logic;

a gate interposed on the address, data and control buses operable by the control logic for selectively providing or inhibiting
the external read and write access to the user memory space; and

a cipher engine in communication with the control logic and the memory interface,
the cipher engine comprising a hardware random number generator and an encryption/decryption block.

US Pat. No. 9,165,795

HIGH PERFORMANCE LOW PROFILE QFN/LGA

CYPRESS SEMICONDUCTOR COR...

1. A method for manufacturing a semiconductor device comprising:
flip chip mounting a first side of a semiconductor die to a substrate comprising a plurality of conductive traces, wherein
a second side of the semiconductor die is subjected to one of polishing, etching, and grinding to reduce a thickness of the
semiconductor die to be no greater than 2 mils prior to the flip chip mounting;

encapsulating the semiconductor die and substrate with an encapsulating material;
subjecting a top side of the encapsulating material to one of polishing, etching, and grinding to expose the second side of
the semiconductor die;

subjecting the bottom side of the substrate to one of polishing, etching, and grinding to remove the substrate; and
reducing a thickness of the plurality of conductive traces by continuing the one of polishing, etching, and grinding after
the substrate has been removed, wherein the substrate is removed and then the thickness of the plurality of conductive traces
is reduced in one continuous step.

US Pat. No. 9,129,437

LINE PLOTTING METHOD

Cypress Semiconductor Cor...

1. A line plotting method comprising:
a first correcting, using a plotting device in a graphic chip, of a first axis coordinate of a starting point or an ending
point in accordance with a pixel of a prescribed frame intersecting a line having the starting point and the ending point,

wherein the first axis coordinate corresponds to a greater of a first difference and a second difference, the first difference
being a difference between X-coordinates of the starting point and the ending point and the second difference being a difference
between Y-coordinates of the starting point and the ending point of the line; and

a second correcting, using the plotting device in the graphic chip, of a second axis coordinate of the starting point or the
ending point by adding or subtracting, respectively, a calculated value to the second axis coordinate,

wherein the calculated value is determined based on a product of a moving distance of the first axis coordinate and an inclination
value of the line.

US Pat. No. 9,104,273

MULTI-TOUCH SENSING METHOD

CYPRESS SEMICONDUCTOR COR...

1. An apparatus comprising:
a drive circuit to generate a drive signal on a first plurality of sensor elements oriented in a first direction;
a second plurality of sensor elements oriented in a second direction, wherein intersections of the first plurality of sensor
elements and the second plurality of sensor elements form a plurality of sensor locations;

a first voltage divider coupled to a first sensor element of the second plurality of sensor elements and coupled to ground,
wherein the first voltage divider is configured to decrease a first voltage at the first sensor element to a second voltage
at an output of the first voltage divider;

a second voltage divider coupled to a second sensor element of the second plurality of sensor elements and coupled to the
ground, wherein the second voltage divider is configured to decrease a third voltage at the second sensor element to a fourth
voltage at an output of the second voltage divider;

a voltage subtractor comprising a first input coupled to the output of the first voltage divider and a second input coupled
to the output of the second voltage divider, the voltage subtractor configured to generate a difference signal based on a
difference in measured signals on the first sensor element and the second sensor element, wherein the measured signals represent
mutual capacitances at the intersections of the first sensor element and the second sensor element, wherein, responsive to
proximity of a conductive object closer to the first sensor element than the second element, the difference signal is a positive
signal, and wherein, responsive to proximity of the conductive object closer to the second sensor element than the first element,
the difference signal is a negative signal; and

an amplitude detect circuit configured to receive the drive signal and to receive the difference signal, the amplitude detect
circuit configured to reject noise in the difference signal that is out of phase with the drive signal.

US Pat. No. 9,496,144

METHOD OF FABRICATING A CHARGE-TRAPPING GATE STACK USING A CMOS PROCESS FLOW

Cypress Semiconductor Cor...

1. A method, comprising:
forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric over the substrate and a
charge-trapping layer over the tunneling dielectric;

forming a first cap layer comprising an oxide over the dielectric stack by performing a first oxidation process of at least
a top layer of the charge-trapping layer;

forming a second cap layer comprising a nitride over the first cap layer;
patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device in a first region
of the substrate;

removing at least a portion of the second cap layer; and
performing a second oxidation process to form a blocking oxide over the charge-trapping layer.

US Pat. No. 9,354,272

AUTOMATED LOADING/UNLOADING OF DEVICES FOR BURN-IN TESTING

Cypress Semiconductor Cor...

1. A method comprising:
stacking boards in a carrier at a station with semiconductor devices loaded into each board, the carrier for supporting a
plurality of boards in a stacked array;

transporting the carrier and boards to a burn-in oven;
placing the carrier and boards into the burn-in oven with an electrical contact on each board abutting an electrical connector
of the burn-in oven; and

engaging the electrical contact of a board with the abutting electrical connector of the burn-in oven using a component of
a door of the burn-in oven.

US Pat. No. 9,286,254

MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP WITH PROGRAMMABLE INTERCONNECT

CYPRESS SEMICONDUCTOR COR...

1. An integrated circuit comprising:
a plurality of programmable analog blocks;
a plurality of programmable digital blocks;
a programmable interconnect coupled to at least one of the programmable analog blocks and at least one of the programmable
digital blocks;

a programmable Input/Output (I/O) interface coupled to the programmable interconnect and
a plurality of configuration register bits coupled to the programmable I/O interface.

US Pat. No. 9,092,098

METHOD AND APPARATUS TO IMPROVE NOISE IMMUNITY OF A TOUCH SENSE ARRAY

Cypress Semiconductor Cor...

1. A method comprising:
interleaving between listening for a level of noise and performing a scan of a touch sense array, the listening for the level
of noise comprising:

receiving a response signal, which is generated in an absence of the scan, at a capacitive sensing circuit from the touch
sense array;

measuring a noise component of the response signal;
determining whether the level of noise is above a threshold; and
when a level of noise within a passband of the capacitive sensing circuit is greater than a threshold, changing at least one
parameter of the capacitive sensing circuit to move the passband substantially outside the frequency spectrum of the noise
component.

US Pat. No. 9,368,393

LINE-EDGE ROUGHNESS IMPROVEMENT FOR SMALL PITCHES

Cypress Semiconductor Cor...

1. A method of mitigating line-edge roughness in a semiconductor device, the method comprising:
providing a substrate with a plurality of layers formed on the substrate, wherein the plurality of layers comprise: an organic
antireflective coating/silicon oxynitride (oARC/SiON) film stack, a high density plasma oxide (HDP) film and a tetraethyl
orthosilicate (TEOS) film;

providing a patterned photoresist layer over the plurality of layers formed over the substrate, wherein the patterned photoresist
layer is in contact with the oARC/SiON film stack; and

etching the plurality of layers formed on the substrate, using the patterned photoresist layer as an etching mask to form
at least one trench in the plurality of layers, wherein a bottom electrode in contact with the semiconductor device has a
temperature approximately in a range of 10-15 degrees Celsius during at least the oARC/SiON film etching.

US Pat. No. 9,325,239

POWER SUPPLY DEVICE, CONTROL CIRCUIT, ELECTRONIC DEVICE AND CONTROL METHOD FOR POWER SUPPLY

Cypress Semiconductor Cor...

1. A method for controlling crossover frequency in a power supply, comprising:
supplying an input voltage to a switch circuit;
feeding back an inductance value of a coil coupled between the switch circuit and an output terminal from which an output
voltage is outputted;

adjusting a slope voltage based on the inductance value of the coil; and
adding the slope voltage to a reference voltage.

US Pat. No. 9,318,498

BURIED HARD MASK FOR EMBEDDED SEMICONDUCTOR DEVICE PATTERNING

CYPRESS SEMICONDUCTOR COR...

1. A method of manufacturing an embedded semiconductor device, comprising:
forming a core region of the semiconductor device, wherein the core region is configured to contain one or more memory devices;
forming a periphery region of the semiconductor device, wherein the periphery region is configured to contain logical gates
to control the one or more memory devices;

disposing a first polysilicon layer over the core and periphery regions of the semiconductor device;
forming a first mask on the first polysilicon layer;
disposing a second polysilicon layer such that the second polysilicon layer covers the first mask;
forming a second mask on the second polysilicon layer in the core region without forming the second mask in the periphery
region; and

removing portions of the first and second polysilicon layers that are uncovered by either of the first and second masks.

US Pat. No. 9,171,470

WIRELESS LOCATING AND MONITORING SYSTEM

Cypress Semiconductor Cor...

1. A method, comprising:
locating, by an object, a network connection to a wireless data network node available to the object, wherein the wireless
data network node is a terrestrial node; and

transmitting, from the object and using the network connection, information about the location of the object to the terrestrial
node as a first node to receive the information about the location of the object and to a receiver node, wherein the transmitting
the information about the location of the object comprises transmitting logged object data corresponding to a path of the
movement of the object over a period of time.

US Pat. No. 9,507,465

TECHNIQUE FOR INCREASING THE SENSITIVITY OF CAPACITIVE SENSOR ARRAYS

Cypress Semiconductor Cor...

1. A method comprising:
electrically coupling capacitance sense electrodes of a capacitive sense array into a first group of a plurality of groups,
each of the plurality of groups comprising two or more capacitance sense electrodes, wherein the capacitive sense array is
configured to sense capacitance indicative of a touch proximate the capacitive sense array;

measuring, at a first time, a first single value of a capacitance of the first group comprising the two or more capacitance
sense electrodes;

electrically coupling the capacitance sense electrodes of the capacitive sense array into a second group of the plurality
of groups, wherein the first group and the second group of the plurality of groups are different groups and comprise at least
one capacitance sense electrode in common;

measuring a second single value of a capacitance of the second group at a second time, the second time being different from
the first time; and

analyzing at least the first single value and the second single value to determine a location of a user interaction with the
capacitive sense array.

US Pat. No. 9,436,339

TOUCH SENSOR PATTERN

CYPRESS SEMICONDUCTOR COR...

1. A capacitive sensor array comprising:
a first sensor element; and
a second sensor element intersecting the first sensor element to form an intersection associated with a unit cell, the second
sensor element comprising, within the unit cell, a first primary trace crossing the unit cell and second primary trace crossing
the unit cell, a first secondary trace connecting the first primary trace and the second primary trace, and a first tertiary
trace branching away from the first secondary trace between the first primary trace and the second primary trace, wherein
an area of the first sensor element is greater than an area of the second sensor element within the unit cell.

US Pat. No. 9,406,574

OXIDE FORMATION IN A PLASMA PROCESS

CYPRESS SEMICONDUCTOR COR...

1. A method comprising:
forming a tunneling layer over a channel connecting a source and a drain formed in a surface of a substrate;
forming a charge storage layer overlying the tunneling layer, the charge storage layer comprises forming a substantially trap
free first layer over the tunneling layer, and forming a trap dense second layer over the first layer;

forming a blocking structure on the charge storage layer by high density plasma (HDP) oxidation, wherein a thickness of the
charge storage layer is reduced through oxidation of a portion of the charge storage layer during forming the blocking structure;

removing at least a portion of the blocking structure;
measuring the thickness of the charge storage layer, and if a measured thickness exceeds a predetermined thickness repeating
the forming and removing of the blocking structure to further reduce the thickness of the charge storage layer; and

if the measured thickness is less than the predetermined thickness forming a final blocking structure on the charge storage
layer.

US Pat. No. 9,373,514

NON-VOLATILE FINFET MEMORY ARRAY AND MANUFACTURING METHOD THEREOF

Cypress Semiconductor Cor...

1. A method for manufacturing an electronic device, comprising:
providing a substrate comprising a plurality of fin-type projections separated by an isolation dielectric material and laterally
coextending in a first direction through a memory cell region and select gate regions abutting said memory cell region, said
plurality of fin-type projections configured to include lower semiconducting sections and upper masking layer sections;

removing a portion of said dielectric isolation material in said memory cell region to expose said lower semiconducting sections
in said memory cell region, such that said dielectric isolation material in said memory cell region has a lower thickness
than a thickness of said lower semiconducting sections of said plurality of fin-type projections, and said dielectric isolation
material in said select gate regions has a greater thickness than said thickness of said lower semiconducting sections of
said plurality of fin-type projections;

removing said upper masking sections;
forming a plurality of gate layers on said substrate, such that gate layers formed in said select gate regions are at least
partially disposed on sidewalls of said dielectric isolation material in said select gate regions; and

processing said plurality of gate layers to define a plurality of gate features coextending in a second direction transverse
to said first direction.

US Pat. No. 9,110,552

ELIMINATING COMMON MODE NOISE IN OTUCH APPLICATIONS

CYPRESS SEMICONDUCTOR COR...

1. A method comprising:
scanning, during a first operation, a first plurality of electrodes along a first axis in a capacitive sense array to generate
a first plurality of signals corresponding to a mutual capacitance at electrode intersections of the capacitive sense array,
the first plurality of signals to identify a first coordinate of a conductive object proximate to the capacitive sense array;

scanning, during a second operation, a second plurality of electrodes along a second axis in the capacitive sense array to
generate a second plurality of signals corresponding to the mutual capacitance at the electrode intersections of the capacitive
sense array, the second plurality of signals to identify a second coordinate of the conductive object, wherein the second
operation occurs during a different period of time than the first operation;

determining, by a processing device during a third operation, the first coordinate of the conductive object proximate to the
capacitive sense array based on the first plurality of signals and the second coordinate of the conductive object based on
the second plurality of signals, the first coordinate and the second coordinate comprising a first location of the conductive
object on the capacitive sense array;

scanning, during the third operation, the first plurality of electrodes to generate a third plurality of signals, the third
plurality of signals to identify a third coordinate of the conductive object, wherein each of the first plurality of electrodes
are scanned during the third operation regardless of a result of the first and second; and

determining, during a fourth operation, a third coordinate of the conductive object based on the third plurality of signals,
the second coordinate and the third coordinate comprising a second location of the conductive object on the capacitive sense
array.

US Pat. No. 9,105,512

SONOS STACK WITH SPLIT NITRIDE MEMORY LAYER

Cypress Semiconductor Cor...

1. A semiconductor device comprising:
a first oxide layer overlying a channel connecting a source and a drain formed in a substrate;
a first nitride layer overlying the first oxide layer;
a second oxide layer overlying the first nitride layer;
a second nitride layer overlying the second oxide layer;
a dielectric layer overlying the second nitride layer; and
a gate layer overlying the dielectric layer,
wherein the first nitride layer is oxygen-rich relative to the second nitride layer, the second nitride layer comprises a
silicon-rich, oxygen-lean nitride.

US Pat. No. 9,397,025

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF

CYPRESS SEMICONDUCTOR COR...

9. A method of manufacturing a semiconductor device, the method comprising:
stacking a plurality of semiconductor devices; and
mechanically and electrically coupling the plurality of semiconductor devices to each other by a conductive pin being inserted
through a recessed portion provided on a lead frame and an opening provided in a resin section of each of the plurality of
semiconductor devices, the recessed portion comprises unfilled space defined by sidewalls in the recessed portion that surround
without contacting the conductive pin wherein a hole and the recessed portion are in the lead frame and the opening is in
the resin section wherein from a plan perspective the opening and the recessed portion are rectangular in shape and the hole
is circular in shape wherein the opening has the greatest width and the hole the smallest width.

US Pat. No. 9,349,877

NITRIDATION OXIDATION OF TUNNELING LAYER FOR IMPROVED SONOS SPEED AND RETENTION

Cypress Semiconductor Cor...

1. A nonvolatile trapped-charge memory device, comprising:
a tunneling layer on a substrate, the tunneling layer including a nitrided oxide film;
a charge trapping layer on the tunneling layer; and
a blocking layer on the charge trapping layer,
wherein the nitrided oxide film comprises a first region comprising approximately 25% of the tunneling layer thickness proximate
to the substrate, a second region comprising approximately 25% of the tunneling layer thickness proximate to the charge trapping
layer, and a middle region between the first region and the second region, and wherein a concentration of nitrogen in the
second region monotonically increases from the middle region to at least approximately 5×1022 atoms/cm3 at a first interface between the second region and the charge trapping layer, and monotonically decreases from the middle
region to a second interface between the first region and the substrate.

US Pat. No. 9,176,636

LOW POWER CAPACITIVE SENSOR BUTTON

CYPRESS SEMICONDUCTOR COR...

1. An apparatus, comprising:
a timer circuit configured to generate a repetitive trigger signal;
a low power oscillator block configured to generate a clock signal having a higher frequency than the repetitive trigger signal;
a sensing block coupled with the timer circuit and the oscillator block and configured to, in response to the repetitive trigger
signal, detect a presence of a conductive object at a capacitive sensor button by applying an excitation signal based on the
clock signal to the capacitive sensor button during a measurement period; and

a wake logic block coupled with the sensing block and configured to transition a processing unit from a low power consumption
state to a high power consumption state in response to the sensing block detecting the presence of the conductive object at
the capacitive sensor button.

US Pat. No. 9,171,612

RESISTIVE CHANGING MEMORY CELL ARCHITECTURE HAVING A SELECT TRANSISTOR COUPLED TO A RESISTANCE CHANGING MEMORY ELEMENT

CYPRESS SEMICONDUCTOR COR...

5. A resistance changing memory array architecture, comprising:
an array of memory unit cells, each memory unit cell comprising:
a current control component; and
a resistance changing memory element coupled to the current control component;
wherein the array is arranged in columns and rows, and wherein at least two columns of the array are coupled to a data line,
and wherein each of the memory unit cells of the at least two columns are coupled to the data line via the current control
component of the respective memory unit cell;

a first plurality of signal lines coupled to the columns of memory unit cells, wherein a control terminal of the current control
component of each memory unit cell along a respective column is coupled to a respective signal line of the first plurality
of signal lines;

a second plurality of signal lines coupled to the rows of memory unit cells wherein the resistance changing memory element
of each memory unit cell along a respective row is coupled to a respective signal line of the second plurality of signal lines;
and

a control circuit configured to provide a unique sequence of control signals on the signal lines of the first plurality of
signal lines coupled to the at least two columns based on a predetermined sequence of resistance changing memory elements
along a given column to be programmed, and based on a data value to be programmed therein.

US Pat. No. 9,153,596

ADJACENT WORDLINE DISTURB REDUCTION USING BORON/INDIUM IMPLANT

Cypress Semiconductor Cor...

1. A semiconductor device comprising:
a semiconductor substrate;
two or more parallel bitlines formed within the semiconductor substrate;
a charge storage layer capable of storing a negative charge formed over the semiconductor substrate and the two or more parallel
bitlines;

two or more parallel wordlines formed over the charge storage layer, the semiconductor substrate and the two or more parallel
bitlines, the two or more parallel wordlines being perpendicular to the two or more parallel bitlines;

one or more wordline spaces comprising the area between the two or more parallel wordlines; and
an implant comprising at least one of boron, indium, and a combination thereof embedded into the floor of at least one space
of the one or more wordline spaces, wherein the implant forms an implant region which is adjacent the two or more parallel
wordlines and located over the charge storage layer and the semiconductor substrate.

US Pat. No. 9,092,582

LOW POWER, LOW PIN COUNT INTERFACE FOR AN RFID TRANSPONDER

Cypress Semiconductor Cor...

1. A serial interface comprising:
a clock node;
a first bidirectional data port;
a second bidirectional data port; and
shift register circuitry coupled to the first bidirectional data port and the second bidirectional data port, the shift register
circuitry including a first shift register to load data onto the first bidirectional data port, a second shift register to
receive data from the first bidirectional data port, a third shift register to load data onto the second bidirectional data
port, and a fourth shift register to receive data from the second bidirectional data port,

wherein the shift register circuitry is configured such that a leading edge and a falling edge of a clock signal associated
with the clock node are used to shift data in each of the first shift register, second shift register, third shift register
and fourth shift register.

US Pat. No. 9,625,988

TYPE-C CONNECTOR SUBSYSTEM

Cypress Semiconductor Cor...

1. An apparatus, comprising:
a Universal Serial Bus (USB) Type-C subsystem comprising a standby reference circuit, wherein the USB Type-C subsystem is
disposed in an integrated circuit (IC) chip, the USB Type-C subsystem configured to:

enable the standby reference circuit in an active state of the IC chip;
transition from the active state to a low power mode of the IC chip;
operate the standby reference circuit in the low power mode to perform detection on Configuration Channel (CC) lines of the
Type-C subsystem, wherein the IC chip is configured to consume no more than a predetermined amount of current in the low power
mode;

enable a precise Rd termination detector or a precise Ra termination detector when attachment of termination is detected on
one of the CC lines; and

enable the standby reference circuit after the attachment of termination is detected.

US Pat. No. 9,472,511

ESD CLAMP WITH A LAYOUT-ALTERABLE TRIGGER VOLTAGE AND A HOLDING VOLTAGE ABOVE THE SUPPLY VOLTAGE

Cypress Semiconductor Cor...

1. A device, comprising:
at least one n-channel metal-oxide-semiconductor (MOS) transistor formed on a lightly doped p-substrate, including:
a gate,
a heavily doped n-drain region isolated from the gate and formed at least partially within an intermediately doped n-well
region, wherein the intermediately doped n-well region is formed at least partially within a lightly doped deep n-well region,
the intermediately doped n-well region including at least one vertical side edge and a bottom edge that are in direct contact
with the lightly doped deep n-well region, wherein doping levels of the n-drain region, the n-well region and the deep n-well
region are in a descending order, and

a heavily doped n-source region; and
a heavily doped p-collection region spaced apart from the heavily doped n-source region, wherein the heavily doped n-source
region and the heavily doped p-collection region are formed at least partially within an intermediately doped p-well region.

US Pat. No. 9,449,831

OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS

Cypress Semiconductor Cor...

1. A memory device comprising:
an electrically conducting channel formed from a semiconducting material overlying a surface on a substrate connecting a source
and a drain of the memory device; and

a gate having multiple surfaces abutting the channel, the gate comprising:
a tunnel oxide layer overlying the channel; and
a multi-layer charge storing layer including a first oxynitride layer closer to the tunnel oxide layer, and a second oxynitride
layer, wherein the first oxynitride layer is separated from the second oxynitride layer by an anti-tunneling layer comprising
an oxide,

wherein the first oxynitride layer is a substantially trap free, oxygen-rich, oxynitride layer, and the second oxynitride
layer is a trap dense, oxygen-lean, oxynitride layer further comprising a concentration of carbon selected to increase a number
of traps therein.

US Pat. No. 9,411,594

CLOCK DATA RECOVERY CIRCUIT AND CLOCK DATA RECOVERY METHOD

Cypress Semiconductor Cor...

1. A processor comprising:
an arithmetic unit configured to execute instructions;
an instruction decode part configured to decode the instructions executed in the arithmetic unit and to output opcodes;
an interrupt register configured to receive an interrupt signal; and
a sequencer configured to store a series of instructions to be processed by continuous instructions included in the instructions,
wherein the sequencer outputs the series of instructions to the instruction decode part in response to the instruction decode
part detecting the continuous instructions,

wherein the instruction decode part comprises an instruction code map that is configured to store the opcodes in correspondence
to instructions and to output the opcodes in accordance with the instructions inputted, and

the instruction code map is further configured to store a plurality of opcodes to be output to a second arithmetic unit as
switch opcodes corresponding to additional instructions, the additional instructions being a part of the instructions, and
to switch the plurality of the switch opcodes in accordance with the interrupt signal.

US Pat. No. 9,349,824

OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS

CYPRESS SEMICONDUCTOR COR...

1. A method comprising:
forming a tunneling layer on a substrate;
forming on the tunneling layer a multi-layer charge storing layer including at least a first charge storing layer comprising
an oxygen-rich oxynitride overlying the tunneling layer formed in a chemical vapor deposition (CVD) tool using a process gas
comprising dichlorosilane (SiH2Cl2), deuterated-ammonia (ND3) and nitrous oxide (N2O), and a second charge storing layer overlying the first charge storing layer formed sequentially in the same CVD tool using
a process gas comprising Bis-tertiaryButylAminoSilane (BTBAS) and ammonia (NH3), the second charge storing layer comprising an oxynitride layer that is oxygen-lean relative to the first charge storing
layer and comprises a majority of charge traps distributed in the multi-layer charge storing layer; and

forming a blocking layer on the second oxynitride layer; and forming a gate layer on the blocking layer.

US Pat. No. 9,218,073

DETERMINING FORCES OF CONTACTS BETWEEN STYLUSES AND OBJECTS

Cypress Semiconductor Cor...

1. An apparatus comprising:
a stylus housing having an end;
a transmit (TX) drive circuit disposed at least partially inside the stylus housing;
a tip shield configured to be coupled to the TX drive circuit to receive a TX potential from the TX drive circuit;
a conductive tip disposed at least partially inside the stylus housing and extending from the end, the conductive tip configured
to receive the TX potential from the TX drive circuit and capacitively couple a transmit signal to a sense array when the
tip shield is coupled to the TX drive circuit, when the tip shield is not coupled to the TX drive circuit, and without a change
in contact between the conductive tip and a touch surface;

a force sensor coupled to the conductive tip and configured to measure a force of a contact between the conductive tip and
the touch surface; and

a switch configured to electrically couple the tip shield to the conductive tip when the measured force of contact indicates
that the conductive tip is not in contact with the touch surface.

US Pat. No. 9,196,608

METHOD OF CHIP POSITIONING FOR MULTI-CHIP PACKAGING

Cypress Semiconductor Cor...

1. A method for multi-chip packaging, the method comprising:
positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact
with the substrate package;

confirming a first alignment of the first IC based on a second set of reference markers in physical contact with the substrate
package and at a different location on the substrate package than the first set of reference markers;

positioning a second IC on the substrate package based on the first set of reference markers, wherein the second IC is stacked
onto the first IC; and

confirming a second alignment of the second IC based on the second set of reference markers.

US Pat. No. 9,590,079

USE DISPOSABLE GATE CAP TO FORM TRANSISTORS, AND SPLIT GATE CHARGE TRAPPING MEMORY CELLS

Cypress Semiconductor Cor...

1. A method of fabricating a semiconductor device having a first, second, and third region on a substrate, comprising:
disposing a first gate layer over a first dielectric on the substrate;
disposing a cap layer over the first gate layer;
forming a plurality of memory cells in the first region, comprising,
etching through the cap layer and the first gate layer in the first region to define at least one select gate disposed over
the first dielectric,

disposing a second dielectric over the at least one select gate and the substrate in at least the first region,
disposing a second gate layer over the second dielectric,
etching the second gate layer to define at least one memory gate disposed over the second dielectric, each of the at least
one memory gates adjacent to a corresponding sidewall of one of the at least one select gates, and

forming a first doped region in the substrate adjacent to one side of the at least one select gate and a second doped region
in the substrate adjacent to an opposite side of the memory gate adjacent to the at least one select gate;

etching through the cap layer and the first gate layer in the second region to define a first transistor gate having an initial
thickness substantially equal to a thickness of the cap layer and the first gate layer;

forming a third doped region in the substrate adjacent to the first transistor gate;
removing the cap layer;
etching through the first gate layer in the third region to define a second transistor gate having a thickness substantially
equal to the thickness of the first gate layer; and

forming a fourth doped region in the substrate adjacent to the second transistor gate, wherein the third doped region extends
deeper in the substrate than the fourth doped region, and wherein a final thickness of the first transistor gate is substantially
equal to the thickness of the second transistor gate.

US Pat. No. 9,588,695

MEMORY ACCESS BASES ON ERASE CYCLE TIME

CYPRESS SEMICONDUCTOR COR...

1. A method, comprising:
measuring an erase-time of a memory block in a memory device;
comparing the erase-time with a threshold value;
storing at least one indicator for the memory block, a value of the at least one indicator being based on the comparing;
selecting a reference cell from a plurality of reference cells based on the value of the indicator; and
reading data from the memory block with the selected reference cell.

US Pat. No. 9,502,979

OUTPUT SWITCHING CIRCUIT

CYPRESS SEMICONDUCTOR COR...

1. A comparison unit for a switching circuit, comprising:
a comparator configured to compare an input signal with a feedback signal to provide a first signal;
a sampling circuit configured to sample the first signal according to a reference clock to provide a sampling signal, the
sampling signal having a first level or a second level; and

a comparison signal generating circuit configured to provide a comparison signal having the first level when the sampling
signal is at the first level for a longer time duration than the second level or having the second level when the sampling
signal is at the first level for a shorter time duration than the second level.

US Pat. No. 9,500,686

CAPACITANCE MEASUREMENT SYSTEM AND METHODS

CYPRESS SEMICONDUCTOR COR...

1. A system for measuring capacitance comprising:
a current source coupled to a first node of a first capacitor and to a first node of a second capacitor, the current source
configured to supply charge to the first and second capacitors, wherein the charge supplied to the first and second capacitors
generates a voltage potential across the first and second capacitors;

a first switch configured to couple the current source and the first node of the first capacitor to the first node of the
second capacitor;

a second switch configured to couple the first node of the first capacitor to a second node of the second capacitor; and
a circuit configured to measure the voltage potential across the first and second capacitors, wherein,
the second capacitor is coupled to the measurement circuit after the current source is configured and coupled to the first
node of the first capacitor and after a voltage potential across the first capacitor has reached a settling voltage, and

the current source is configured to provide a charge on the first capacitor according to a predetermined charge rate.

US Pat. No. 9,472,564

SYSTEM WITH MEMORY HAVING VOLTAGE APPLYING UNIT

CYPRESS SEMICONDUCTOR COR...

1. A system, the system comprising
a processor;
a cache;
a user input component; and
a memory comprising flash memory, the flash memory comprising:
a semiconductor region located in a semiconductor layer formed on an isolating layer;
an oxide nitride oxide (ONO) film on the semiconductor region;
a plurality of bit lines on either side of the semiconductor region, the plurality of bit lines being located in the semiconductor
layer, and being in contact with the isolating layer;

a device isolating region on two different sides of the semiconductor region opposite from the sides on which the plurality
of bit lines are located, the device isolating region being in contact with the isolating layer; and

a first voltage applying unit that is coupled to the semiconductor region, wherein the semiconductor region is surrounded
by the plurality of bit lines and the device isolating region, and is electrically isolated from other semiconductor regions.

US Pat. No. 9,473,144

INTEGRATED CIRCUIT DEVICE WITH PROGRAMMABLE ANALOG SUBSYSTEM

CYPRESS SEMICONDUCTOR COR...

1. An integrated circuit (IC) device, comprising:
a plurality of analog blocks, including
at least one fixed function analog circuit, and
a plurality of reconfigurable analog circuit blocks;
at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and
a digital section comprising digital circuits, wherein each analog block includes dedicated signal lines coupled to the at
least one analog routing block and at least one of the reconfigurable analog circuit blocks includes at least one direct signal
line coupling the at least one of the reconfigurable analog circuit blocks to an external connection of the IC device without
passing through any switch, wherein at least one of the analog blocks comprises a programmable reference block (PRB) configured
to generate at least four programmable reference values.

US Pat. No. 9,437,573

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF

CYPRESS SEMICONDUCTOR COR...

1. A method of manufacturing a semiconductor device comprising:
temporarily bonding a first electrode formed on a mount portion to a second electrode, the second electrode comprising a protrusion
formed on a mounted portion, wherein temporarily bonding comprises selectively heating a leading end of the protrusion;

exposing the first electrode, the second electrode and a solder comprised in a bonding terminal disposed on the first electrode
to a reducing gas; and

bonding, subsequent to the temporarily bonding, the first electrode to the second electrode by reflowing the solder on at
least part of a side surface of the protrusion with the solder comprised in the bonding terminal, wherein

the protrusion is formed on the mounted portion by bringing the leading end of the protrusion into contact with the bonding
terminal, and

at least one of the mount portion and the mounted portion comprises a semiconductor chip.

US Pat. No. 9,407,257

REDUCING POWER CONSUMPTION IN A LIQUID CRYSTAL DISPLAY

Cypress Semiconductor Cor...

1. An apparatus, comprising:
a bias voltage generator to generate a plurality of bias voltages; and
a drive buffer to drive a passive liquid crystal display (LCD) pixel or segment from a particular one of the bias voltages,
wherein the drive buffer actively drives the passive LCD segment or pixel in a first phase, and wherein the drive buffer comprises:

a first buffer configured to actively drive a voltage, applied to the passive LCD pixel or segment, to a threshold level that
is different from the particular one of the bias voltages, wherein the first buffer includes a current source that is configured
to drive the voltage applied to the passive LCD pixel or segment to the threshold level; and

a second buffer in parallel with the first buffer configured to actively further modify the voltage, applied to the passive
LCD pixel or segment, from the threshold level to approximate the particular one of the bias voltages;

wherein the drive buffer is configured to actively drive the passive LCD segment or pixel by adjusting the voltage, applied
to the passive LCD pixel or segment, to approximate the particular one of the bias voltages, and by compensating a leakage
associated with the passive LCD pixel or segment to provide a constant voltage at the passive LCD pixel or segment in a low-drive
mode; and

wherein the second buffer is activated during the low-drive mode.

US Pat. No. 9,373,321

GENERATION OF WAKE-UP WORDS

Cypress Semiconductor Cor...

1. A method for generating one or more wake-up words, the method comprising:
receiving, using a keyboard, a text representation of the one or more wake-up words;
determining a strength of the text representation of the one or more wake-up words based on one or more static measures, wherein
the determining the strength of the text representation comprises applying a Kullback-Leibler (KL) divergence calculation
between the one or more wake-up words and words unrelated to the one or more wake-up words;

comparing a result of the KL divergence calculation to a predetermined distance score associated with a decoding accuracy
of a speech recognizer;

receiving, using a microphone, an audio representation of the one or more wake-up words;
determining a strength of the audio representation of the one or more wake-up words based on one or more dynamic measures;
and

providing a message on a display device, wherein the message comprises one or more improvements to a likelihood that the speech
recognizer recognizes the one or more wake-up words based on the strengths of the text and audio representations.

US Pat. No. 9,356,035

EMBEDDED SONOS BASED MEMORY CELLS

Cypress Semiconductor Cor...

1. A device, comprising:
a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising an indium doped
channel and a gate stack on the substrate overlying the channel, the gate stack including a dielectric layer on the substrate
and a charge-trapping layer on the dielectric layer and an oxide layer overlying the charge-trapping layer, a first gate overlying
the oxide layer, and a first silicide region overlying the first gate;

a metal-oxide-semiconductor (MOS) transistor formed in a second region of the substrate, the MOS transistor comprising a gate
oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and a second silicide region overlying
the second gate; and

a nitride layer overlying at least directly over and in direct contact with the first silicide region of the NVM transistor.

US Pat. No. 9,355,051

APPARATUS, METHOD, AND MANUFACTURE FOR USING A READ PREAMBLE TO OPTIMIZE DATA CAPTURE

Cypress Semiconductor Cor...

1. A memory device, comprising:
a memory; and
a memory controller configured to:
in response to a burst read command that includes a target address, provide, to first and second data lines, data stored in
the memory at the target address after a plurality of dummy clock cycles; and

provide first and second preambles on the first and second data lines, respectively, during at least a portion of the plurality
of dummy clock cycles such that the first and second preambles comprises first and second data training patterns, respectively;

wherein the first and second data training patterns are designed to be used to determine a period of time that valid data
is concurrently available on the first and second data lines, and wherein the period of time comprises a minimum period of
time during a clock cycle for data capture; and

wherein each of the first and second preambles comprises: 1) at least one 0 to 1 and 1 to 0 transition on both the first and
second data lines; 2) at least one 0 to 1 transition on the first data line concurrently with a 1 to 0 transition on the second
data line; and 3) at least one 1 to 0 transition on the first data line concurrently with a 0 to 1 transition on the second
data line.

US Pat. No. 9,304,953

MEMORY CONTROLLER DEVICES, SYSTEMS AND METHODS FOR TRANSLATING MEMORY REQUESTS BETWEEN FIRST AND SECOND FORMATS FOR HIGH RELIABILITY MEMORY DEVICES

Cypress Semiconductor Cor...

1. A device, comprising:
an interface circuit configured to translate memory access requests at a controller interface of the interface circuit into
signals at a memory device interface of the interface circuit that is different from the controller interface, the interface
circuit including

a write buffer memory configured to store a predetermined number of data values received at a write input of the controller
interface, and

a read buffer memory configured to mirror a predetermined number of data values stored in the write buffer memory; wherein
the memory device interface comprises
an address output configured to transmit address values,
a write data output configured to transmit write data on rising and falling edges of a periodic signal, and
a read data input configured to receive read data at the same rate as the write data.

US Pat. No. 9,236,448

METHOD FOR ACHIEVING VERY SMALL FEATURE SIZE IN SEMICONDUCTOR DEVICE BY UNDERTAKING SILICIDE SIDEWALL GROWTH AND ETCHING

Cypress Semiconductor Cor...

1. A method of fabricating an electronic device comprising:
providing a structure over an insulating layer and a substrate, the structure comprising a first body comprising a polysilicon
and a second body comprising polysilicon reacted with at least some nickel from a nickel layer disposed over the first body,
the second body comprising first, second, and third portions, the first portion being disposed between the second and third
portions;

removing the first portion of the second body, with at least a part of the second and third portions of the second body remaining;
and

removing an area of the first body using the second and third portions of the second body as a mask over a remaining area
of the first body,

wherein a side surface of the second portion is vertically aligned with a side surface of the first body and a side surface
of the third portion is vertically aligned with an opposite side surface of the first body,

further wherein a bottom surface of each of the second portion and the third portion is lower than a bottom surface of the
first portion.

US Pat. No. 9,164,640

BARRIER ELECTRODE DRIVEN BY AN EXCITATION SIGNAL

CYPRESS SEMICONDUCTOR COR...

1. An apparatus comprising a capacitance-sensing circuit coupled to a capacitive-sense array comprising a plurality of electrodes,
wherein the capacitance-sensing circuit comprises a plurality of sensing channels and is operative to:
measure signals on a first subset of the plurality of electrodes using the plurality of sensing channels, wherein each of
the plurality of sensing channels is coupled to one of the first subset of the plurality of electrodes;

drive a first barrier electrode of the plurality of electrodes with an excitation signal while measuring the signals on the
first subset, wherein the excitation signal is greater in magnitude than the measured signals, and wherein the first barrier
electrode is adjacent to an edge electrode of the first subset of the plurality of electrodes coupled to one of the plurality
of sensing channels;

drive a second barrier electrode of the plurality of electrodes with the excitation signal while measuring the signals on
the first subset, wherein the second barrier electrode is adjacent to another edge electrode of the first subset of the plurality
of electrodes coupled to another one of the plurality of sensing channels;

drive a second subset of the plurality of electrodes with a shield signal while measuring the signals on the first subset,
wherein the excitation signal is greater in magnitude than the shield signal,
wherein the plurality of electrodes of the capacitive-sense array comprises a plurality of row electrodes and a plurality
of column electrodes, and

wherein the first barrier electrode is a first column electrode of the plurality of column electrodes, the second barrier
electrode is a second column electrode of the plurality of column electrodes, and the first subset includes column electrodes
of the plurality of column electrodes, the column electrodes being between the first column electrode and the second column
electrode.

US Pat. No. 9,166,621

CAPACITANCE TO CODE CONVERTER WITH SIGMA-DELTA MODULATOR

CYPRESS SEMICONDUCTOR COR...

1. A method comprising:
measuring a mutual capacitance on a sense element of a matrix-scanning device using a modulation circuit, wherein the matrix-scanning
device comprises a plurality of drive lines and a plurality of sense lines and the sense element is located at an intersection
of one of the plurality of drive lines and one of the plurality of sense lines, wherein the measuring the mutual capacitance
comprises:

applying a drive signal to the one of the plurality of drive lines using an excitation source; and
sensing, by the modulation circuit, the drive signal on the one of the plurality of sense lines to measure the mutual capacitance
of the sense element; and

switching the sense element to be coupled and decoupled to a capacitor of the modulation circuit using a first plurality of
switches, wherein the first plurality of switches are controlled by a clock;

converting the mutual capacitance measured on the sense element to a first digital value;
measuring a self-capacitance on at least one of the plurality of drive lines;
switching the at least one of the plurality of drive lines to be coupled and decoupled to the capacitor using a second plurality
of switches, wherein the second plurality of switches are controlled by the clock; and

converting the self-capacitance measured on the at least one of the plurality of drive lines to a second digital value.

US Pat. No. 9,135,918

REAL-TIME DATA PATTERN ANALYSIS SYSTEM AND METHOD OF OPERATION THEREOF

CYPRESS SEMICONDUCTOR COR...

1. A method comprising:
storing a plurality of senones in a memory module;
transferring the plurality of senones from the memory module to an integrated data transfer module at 256 bits per transfer
and greater;

transferring the plurality of senones from the integrated data transfer module to the computational unit;
comparing processed data to the plurality of senones using the computational unit to generate one or more senone scores, wherein
the memory module, integrated data transfer module, and computational unit are integrated on the same integrated circuit,
and wherein the processed data is received by the integrated circuit from an external source; and

transferring the one or more senone scores off-chip from the integrated circuit.

US Pat. No. 9,123,642

METHOD OF FORMING DRAIN EXTENDED MOS TRANSISTORS FOR HIGH VOLTAGE CIRCUITS

Cypress Semiconductor Cor...

1. A method comprising:
implanting ions of a first-type at a first energy level in a first drain portion in a drain extended metal-on-semiconductor
(DE_MOS) region of a substrate where a first DE_MOS transistor is to be formed, while concurrently implanting ions of the
first-type at the first energy level in a high-voltage metal-on-semiconductor (HV_MOS) region of the substrate where a first
HV MOS transistor is to be formed to adjust a threshold voltage of the first HV_MOS transistor;

implanting ions of the first-type at a second energy level in a low-voltage metal-on-semiconductor (LV_MOS) region of the
substrate where a first LV_MOS transistor is to be formed to adjust a threshold voltage of the first LV_MOS transistor, while
concurrently implanting ions of the first-type at the second energy level in the first drain portion; and

implanting ions of a second-type at the first energy level in a second drain portion where a second DE_MOS transistor is to
be formed in the DE_MOS region while concurrently implanting ions of the second-type at the first energy level in the HV_MOS
region of the substrate where a second HV_MOS transistor is to be formed to adjust the threshold voltage of the second HV_MOS
transistor.

US Pat. No. 9,111,944

METHOD OF FABRICATING A FERROELECTRIC CAPACITOR

Cypress Semiconductor Cor...

1. A method comprising:
depositing a ferro stack over a surface of a substrate, the ferro stack including a bottom electrode layer electrically coupled
to a bottom electrode contact extending through the substrate, a top electrode layer and ferroelectric layer there between;

forming a hard-mask over the ferro stack;
forming a ferroelectric capacitor, wherein forming the ferroelectric capacitor comprises:
etching through the top electrode layer and at least partially through the ferroelectric layer to form a top electrode;
forming a non-conductive barrier deposited directly on a top surface and sidewalls of the ferroelectric capacitor formed by
etching through the top electrode layer and at least partially through the ferroelectric layer;

forming a first patterned photoresist over a portion of the non-conductive barrier located on the top surface of the ferroelectric
capacitor and not the sidewalls;

etching the non-conductive barrier using the first patterned photoresist to expose a surface of a bottom electrode layer;
and

forming a bottom electrode, wherein forming the bottom electrode comprises etching the bottom electrode layer using the non-conductive
barrier as a mask, and wherein conductive residues generated by the etching of the bottom electrode layer are electrically
isolated from the top electrode by the non-conductive barrier that covers the sidewalls and the top surface of the ferroelectric
capacitor,

wherein the ferro stack further comprises a conductive oxygen (O2) barrier layer deposited on the surface of the substrate between the substrate and the bottom electrode layer, and further
comprises etching the conductive O2 barrier layer to form an O2 barrier, wherein the bottom electrode is electrically coupled to the bottom electrode contact through the O2 barrier, and wherein a thickness of the non-conductive barrier on the sidewalls of the ferroelectric capacitor is reduced
while etching the bottom electrode layer and the conductive O2 barrier layer.

US Pat. No. 9,105,740

SONOS TYPE STACKS FOR NONVOLATILE CHANGETRAP MEMORY DEVICES AND METHODS TO FORM THE SAME

Cypress Semiconductor Cor...

1. A nonvolatile charge trap memory device, comprising:
a tunnel dielectric layer on a surface of a substrate, the tunnel dielectric layer comprising a nitrided first oxide layer
formed by a first decoupled plasma nitridation process;

a charge-trapping layer on the tunnel dielectric layer; and
a blocking dielectric layer on the charge-trapping layer, the blocking dielectric layer formed by a second decoupled plasma
nitridation process.

US Pat. No. 9,047,237

POWER SAVINGS APPARATUS AND METHOD FOR MEMORY DEVICE USING DELAY LOCKED LOOP

CYPRESS SEMICONDUCTOR COR...

1. A memory apparatus, comprising:
a delay locked loop (DLL) having a DLL lock time;
a memory device having an initial data access latency time; and
a memory controller having a controller latency time, and configured to receive a memory access instruction, the memory controller
providing a DLL turn-on command to the DLL based on receipt of the memory access instruction, the controller latency time,
the initial data access latency time and the DLL lock time,

wherein the sum of controller latency time and initial data access latency time exceeds the DLL lock time.

US Pat. No. 9,922,833

CHARGE TRAPPING SPLIT GATE EMBEDDED FLASH MEMORY AND ASSOCIATED METHODS

Cypress Semiconductor Cor...

1. A method of making a semiconductor device, comprising:
forming a dielectric layer at a first region and a second region of a semiconductor substrate;
disposing a gate conductor layer over the dielectric layer formed in the first and second regions of the semiconductor substrate;
disposing a first mask layer over the first and second regions;
patterning the first mask layer to form a select gate mask only in the first region;
forming a split gate memory cell in the first region of the semiconductor substrate, wherein the split gate memory cell has
a first gate length, wherein forming the split gate gate memory cell comprises etching the gate conductor layer, using the
select gate mask, to define a select gate and disposing a charge trapping dielectric in contact with a top portion of the
select gate; disposing a second mask layer in contact with the select gate in the first region; and etching the second region
to define a logic gate, wherein the logic gate has a second gate length, wherein disposing the first mask layer on the second
region comprises disposing a hard mask layer over the first region, wherein the hard mask layer over the first region is different
from the second mask layer over the first region.

US Pat. No. 9,612,987

DYNAMICALLY RECONFIGURABLE ANALOG ROUTING CIRCUITS AND METHODS FOR SYSTEM ON A CHIP

Cypress Semiconductor Cor...

1. An integrated circuit device comprising:
a dynamically or statically reconfigurable analog signal switching fabric comprising:
a plurality of global buses configured to be selectively connected to and disconnected from external pins by pin connection
circuits in response to first analog routing data; and

a plurality of local buses configured to be selectively connected to at least one of one or more analog blocks and one or
more of the global buses by routing connection circuits in response to second analog routing data and in response to third
analog data, to be selectively connected to a first of the one or more analog blocks and a second of the one or more analog
blocks to connect the first and second analog blocks, wherein the first and second analog blocks are configured to provide
an analog function, when connected to one another;

at least one processor circuit;
a programmable logic section comprising a plurality of digital programmable blocks; and
a digital system interconnect configured to provide, to the analog switching fabric, analog routing data received from the
programmable logic section and analog routing data received from the at least one processor circuit.

US Pat. No. 9,588,626

CAPACITIVE SENSING BUTTON ON CHIP

CYPRESS SEMICONDUCTOR COR...

1. An integrated circuit package comprising:
a plurality of sensor elements arranged within the integrated circuit package; and
a controller arranged within the integrated circuit package and coupled to the plurality of sensor elements, wherein the controller
is configured to apply a transmit signal to a first sensor element of the plurality of sensor elements and receive a receive
signal from a second sensor element of the plurality of sensor elements, the receive signal representing a mutual capacitance
of the first sensor element and the second sensor element.

US Pat. No. 9,514,833

SUPPLY POWER DEPENDENT CONTROLLABLE WRITE THROUGHPUT FOR MEMORY APPLICATIONS

CYPRESS SEMICONDUCTOR COR...

1. A method comprising:
monitoring a power supply;
determining a power supply level;
determining a first number of bitlines which a memory device can activate at a time based on the power supply level;
generating a control signal based on the first number of bitlines; and
activating a portion of the memory device corresponding to the first number of bitlines with a driver circuit in response
to the control signal.

US Pat. No. 9,515,081

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF

Cypress Semiconductor Cor...

1. A method for manufacturing a semiconductor device, comprising:
forming a bit line in a semiconductor substrate;
forming along a surface of the semiconductor substrate an oxide-nitride-oxide (ONO) film that includes a tunnel oxide film,
a trap layer made of a nitride film, and a top oxide film;

etching the top oxide film in a middle portion between the bit lines along the surface of the semiconductor substrate; and
oxidizing the trap layer under a portion where the top oxide film is etched.

US Pat. No. 9,507,688

EXECUTION HISTORY TRACING METHOD

Cypress Semiconductor Cor...

1. A method, comprising:
recording trace information about a tracing target during a first instruction execution cycle in a buffer;
grouping the recorded trace information with additional trace information recorded during a second instruction execution cycle,
wherein the additional trace information corresponds to the tracing target; and

generating a single instruction notation for the first and second execution cycles based on the grouped recorded trace information
and the additional trace information.

US Pat. No. 9,489,326

MULTI-PORT INTEGRATED CIRCUIT DEVICES AND METHODS

Cypress Semiconductor Cor...

1. An integrated circuit device, comprising:
a first integrated circuit (IC) portion having a memory array configured to store data units at respective storage locations,
and burst access circuitry configured to sequentially access, through a single burst access, N related storage locations within
the memory array, wherein N>1, the N related storage locations within the memory array comprise related addressed that are
addressable based on a single base address, wherein the burst access circuitry is configured to sequentially access the N
related storage locations and transfer the respective data unit at the respective storage location to a second IC portion
responsive to the single base address in the single burst access; and

the second IC portion comprising a plurality of burst access registers coupled to the burst access circuitry, each burst access
register having register locations to store at least N data units of the N related storage locations, and coupled to a corresponding
port, of a plurality of ports of the second IC, by a single data unit access path, wherein a data bandwidth between the first
IC portion and the second IC portion is greater than a sum of maximum data bandwidths of the plurality of ports, and wherein
a first data transfer between one of the plurality of burst access registers and the first IC portion is according to the
single burst access the respective ones of the data units corresponding to the N related storage locations within the memory
array and a second data transfer between the one burst access register and at least one of the plurality of ports of the second
IC portion is according to non-burst access of the respective one of the at least N data units stored in the one burst access
register.

US Pat. No. 9,461,247

METHOD OF FORMING CONTROLLABLY CONDUCTIVE OXIDE

Cypress Semiconductor Cor...

1. A method of fabricating a memory device, the method comprising:
forming a first electrode,
wherein the first electrode is a single layer;
forming an alloy on the first electrode;
oxidizing the alloy to provide an oxide;
implanting material in the oxide to form an implanted material layer comprising the oxide and the material,
the implanted material layer having a conductivity higher than a conductivity of the oxide before material implantation,
wherein an increase in the conductivity of the implanted material layer is proportional to an amount of the material implanted
in the oxide; and

forming a second electrode,
wherein the second electrode overlays the oxide and the implanted material layer.

US Pat. No. 9,385,014

FLIP-CHIP PACKAGE COVERED WITH TAPE

Cypress Semiconductor Cor...

1. A semiconductor device comprising:
a first semiconductor chip that is flip-chip mounted on a front surface of a substrate;
a second semiconductor chip that is flip-chip mounted on a back surface of the substrate;
a fluid hardened void restrained resin portion configured in accordance with a fluid pressure, formed from a melted under
fill, wherein the resin portion is formed between the first and second semiconductor chips and the substrate;

a resin sheet that covers the first and second semiconductor chips and the resin portion;
a plurality of openings formed within the resin sheet extending from a top surface of the resin sheet to a top surface of
the first and second semiconductor chips, wherein the plurality of openings enable vacuum absorption of the first and second
semiconductor chips;

a plurality of electrodes disposed on the front surface and the back surface of the substrate; and
the first semiconductor chip and the second semiconductor chip are affixed to the substrate via the plurality of electrodes
through a plurality of openings in the resin portion.

US Pat. No. 9,343,470

INTEGRATION OF SEMICONDUCTOR MEMORY CELLS AND LOGIC CELLS

Cypress Semiconductor Cor...

1. A method for manufacturing a semiconductor device having a memory cell area and a logic cell area, comprising:
preparing a silicon substrate;
forming a polysilicon gate electrode in the memory cell area;
forming a dummy polysilicon gate electrode in the logic cell area;
removing the dummy polysilicon gate electrode from the logic cell area;
forming a gate insulation film and a metal gate electrode having a recess portion, in place of the removed dummy polysilicon
gate electrode;

forming contact holes on source regions and drain regions of the memory cell area and the logic cell area;
filling the recess portion of the metal gate electrode and the contact holes concurrently with a wiring metal; and
planarizing the wiring metal by polishing.

US Pat. No. 9,317,138

METHOD AND APPARATUS FOR SENSING MOVEMENT OF A HUMAN INTERFACE DEVICE

Cypress Semiconductor Cor...

1. A method comprising:
in response to receiving at a computing device a radio signal transmitted from a peripheral device, transmitting a return
radio signal from the computing device and changing a state of an output signal;

identifying time periods for multiple radio signals, including the received radio signal and the return radio signal, to travel
between the peripheral device and the computing device; and

determining a direction of movement of the peripheral device based on a change in the frequency of the output signal, wherein
the frequency of the output signal is a function of a distance between the peripheral device and the computing device, and
wherein an increasing distance between the peripheral device and the computing device corresponds to a decreasing frequency
of the output signal.

US Pat. No. 9,312,252

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A CHIP MOUNTED ON AN INTERPOSER

Cypress Semiconductor Cor...

1. A method for manufacturing a semiconductor device, comprising the steps of:
mounting via an adhesive, a second semiconductor chip of a second semiconductor package on an upper surface of a first molding
resin of a first semiconductor package, the second semiconductor chip being mounted to a second interposer of the second semiconductor
package by flip-chip bonding, wherein the adhesive is provided directly on the second semiconductor chip;

sealing an area between the first molding resin and the second interposer by filling the area between the first molding resin
and the second interposer with a supporting member so as to cover side surfaces of the second semiconductor chip; and

forming, on an upper surface of a first interposer comprised in the first semiconductor package, a second molding resin that
surrounds and seals the first molding resin, which surrounds and seals a first semiconductor chip of the first semiconductor
package, and surrounds and seals side surfaces of the supporting member that covers the side surfaces of the second semiconductor
package.

US Pat. No. 9,269,828

LATERAL CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR WORDLINE

Cypress Semiconductor Cor...

1. A semiconductor device, comprising:
a semiconductor layer including a trench extending in a first direction;
a plurality of charge storage layers formed at both side surfaces of the trench;
a first wordline buried in the trench and formed in the semiconductor layer in contact with the plurality of charge storage
layers wherein the first wordline is laterally confined within vertical boundaries established by sidewalls of the trench;

a plurality of source-drain regions formed in the semiconductor layer at both sides of the trench; and
a plurality of interconnection layers extending in a second direction and parallel to one another, and configured to be selectively
coupled to the plurality of source-drain regions, wherein each of the plurality of interconnection layers is coupled to only
one of the plurality of source-drain regions along the first direction,

wherein the second direction is perpendicular to the first direction.

US Pat. No. 9,224,748

METHOD OF FORMING SPACED-APART CHARGE TRAPPING STACKS

Cypress Semiconductor Cor...

1. A semiconductor memory device comprising:
a silicon substrate;
a first insulating element and a second insulating element disposed on the silicon substrate;
a first bit line region disposed in the silicon substrate underlying the first insulating element and a second bit line region
disposed in the silicon substrate underlying the second insulating element;

a first charge storage node disposed along a sidewall of the first insulating element and a second charge storage node disposed
along a sidewall of the second insulating element; wherein a third charge storage node and a fourth charge storage node are
disposed along other sidewalls of the first and second insulating elements, respectively, and wherein the first, second, third,
and fourth charge storage nodes are each disposed along a portion less than the full height of each respective insulating
element sidewall;

oxidized epitaxially grown silicon disposed on the silicon substrate between the first charge storage node and the second
charge storage node, wherein edges of the first and second charge storage nodes contact opposite edges of the oxidized epitaxially
grown silicon, wherein a height of the oxidized epitaxially grown silicon isles than a height of the charge storage nodes
disposed along respective insulating element sidewalls, wherein the epitaxially grown silicon is substantially all oxidized,
and wherein a portion of the silicon substrate underlying the oxidized epitaxially grown silicon is oxidized; and

a control gate layer contiguously overlying the charge storage nodes, the first and second insulating elements, and the oxidized
epitaxially grown silicon.

US Pat. No. 9,223,726

APPARATUS AND METHOD FOR PROGRAMMABLE READ PREAMBLE WITH TRAINING PATTERN

Cypress Semiconductor Cor...

1. A memory device, comprising:
a preamble memory that is arranged to store a read preamble such that the read preamble includes two training patterns that
are suitable for:

aligning a capture point for read data on two communication lines; and
determining a period of time within a clock cycle the read data is simultaneously available on the two communication lines,
wherein the training patterns can be altered at least once subsequent to manufacture of the preamble memory, wherein the preamble
memory is configured such that the read preamble is programmable during power up, and further configured such the read preamble
is locked after power up is complete; and

a memory controller that is configured, in response to a read command, to:
provide the read preamble stored in the preamble memory; and
provide the read data.

US Pat. No. 9,201,511

OPTICAL NAVIGATION SENSOR AND METHOD

Cypress Semiconductor Cor...

1. An input device comprising:
a button configured in a first mode of operation of the input device to receive user input when a surface of the button is
pressed;

an optical navigation sensor (ONS) housed within the button, the ONS configured in a second mode of operation of the input
device to illuminate an object in proximity to the surface of the button through a window in the surface of the button, and
to sense and provide input related to motion of the object; and

a circuit configured to disable input from the ONS in the first mode of operation, the circuit comprising circuitry configured
to enable input from the ONS and disable input from the button in the second mode of operation.

US Pat. No. 9,152,284

APPARATUS AND METHOD FOR REDUCING AVERAGE SCAN RATE TO DETECT A CONDUCTIVE OBJECT ON A SENSING DEVICE

Cypress Semiconductor Cor...

1. An apparatus comprising:
a processing device comprising a plurality of capacitance sensors and a plurality of pins; and
a switch circuit coupled to the processing device and to a plurality of capacitive sense elements coupled to the plurality
of pins, wherein the processing device is to select a first capacitance sensor of the plurality of capacitance sensors to
couple to a first group of two or more of the plurality of capacitive sense elements via the switch circuit in a first mode
and to couple the first capacitance sensor to an individual one of the two or more of the plurality of capacitive sense elements
in a second mode.

US Pat. No. 9,104,251

FULL-BRIDGE TIP DRIVER FOR ACTIVE STYLUS

Cypress Semiconductor Cor...

1. An active stylus comprising:
a full bridge tip driver comprising:
a first bridge branch output coupled to a tip of the active stylus; and
a second bridge branch output coupled to an electrical contact positioned in a casing of the active stylus, wherein the electrical
contact coupled to the second bridge branch output is to provide a capacitance of a body of a user to a second bridge branch.

US Pat. No. 9,368,644

GATE FORMATION MEMORY BY PLANARIZATION

Cypress Semiconductor Cor...

1. A method of forming a semiconductor device, comprising:
forming, on a substrate, a gate structure that includes a charge trapping dielectric formed between the substrate and a first
poly layer, a top dielectric formed over the first poly layer, and a sidewall dielectric formed on a first side of the first
poly layer and on a second side of the first poly layer, wherein the second side is an opposite side from the first side;

forming a second poly layer over the gate structure such that the second poly layer includes a vertical portion that is in
contact with the sidewall dielectric and a top portion;

removing the sidewall dielectric formed on the second side of the first poly layer; and
removing the top portion of the second poly layer.

US Pat. No. 9,325,320

SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING

Cypress Semiconductor Cor...

1. An apparatus, comprising:
a plurality of functional elements located in a same integrated circuit, wherein at least one of the functional elements comprises
a micro-controller;

a configuration data store in the integrated circuit to store configuration values;
a plurality of I/O pins configured to connect the integrated circuit to external signals; and
a programmable interconnect, located in the integrated circuit, configured to programmably connect a first functional element
of the plurality of functional elements to a first I/O pin of the plurality of I/O pins and to connect the first functional
element to the micro-controller according to the configuration values loaded into the configuration data store.

US Pat. No. 9,318,333

DIELECTRIC EXTENSION TO MITIGATE SHORT CHANNEL EFFECTS

CYPRESS SEMICONDUCTOR COR...

1. A method comprising:
patterning a layer of gate electrode material such that apertures are created in the layer of gate electrode material and
passivants accumulate on sidewalls of the apertures, wherein the patterning uses a first etching composition;

patterning a layer of gate dielectric material to form openings in the layer of gate dielectric material, wherein the patterning
the layer of gate dielectric material leaves behind a portion of the passivants accumulated on the sidewalls of the apertures;

removing at least some of the portion of the passivants accumulated on the sidewalls to create dielectric extensions that
extend out into the apertures, wherein the removing the at least some of the portion of the passivants creates dielectric
extensions that are configured to retard implantation of dopants into a substrate; and

implanting dopants into a substrate that underlies the layer of gate dielectric material to establish source/drain regions
in the substrate, wherein the source/drain regions each have a length that is approximately equal to a distance between adjacent
openings in the layer of gate dielectric material so as to have an effect of lengthening a channel of a semiconductor device
and mitigating a short channel effect experienced by the semiconductor device.

US Pat. No. 9,245,774

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Cypress Semiconductor Cor...

1. A method of manufacturing a semiconductor device comprising:
flip-chip connecting a semiconductor element to a substrate over a plurality of solder balls mounted on the substrate such
that a space is formed between the substrate and the semiconductor element;

forming a molding portion to entirely enclose a plurality of side surfaces of the semiconductor element, the molding portion
comprising a plurality of separate, inclined portions;

fabricating the molding portion so that no portion of an upper surface of the semiconductor element is enclosed by the molding
portion;

applying an affixing agent over a top surface of the semiconductor element; and
mounting a built-in semiconductor device over the semiconductor element via the affixing agent; and
electrically coupling the built-in semiconductor device to an upper surface of a wire-connecting pad, the upper surface of
the wire-connecting pad being substantially level with an upper surface of the substrate,

wherein a thermal conductivity of the molding portion is lower than a thermal conductivity of the semiconductor element,
further wherein the built-in semiconductor device is mounted over the semiconductor element via the affixing agent such that
the affixing agent extends horizontally beyond a bottom surface of the built-in semiconductor device.

US Pat. No. 9,245,895

ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB

Cypress Semiconductor Cor...

1. A memory device structure comprising: two memory cell structures on a semiconductor substrate, each of the structures comprising
two undercut openings separated by a dielectric, said openings being disposed under a monolithic first poly gate wherein said
monolithic first poly gate defines the upper surface of each of said undercut openings, a charge storage node positioned within
each undercut opening, wherein the charge storage node comprises one of an oxide/nitride/oxide tri-layer, an oxide/nitride
bi-layer, a nitride/oxide bi-layer, an oxide/tantalum oxide bi-layer (Si02/Ta205), an oxide/tantalum oxide/oxide tri-layer
(Si02FFa205/Si02), an oxide/strontium titanate bi-layer (Si02/SrTi03), an oxide/barium strontium titanate bi-layer (Si02/BaSrTi02),
an oxide/strontium titanate/oxide tri-layer (Si02/SrTi03/Si02), an oxide/strontium titanate/barium strontium titanate tri-layer
(Si02/SrTi03/BaSrTi02) and an oxide-nitride-polysilicon-nitride-oxide (ORPRO);
a bit line opening, comprising a bit line trench, disposed between the two structures wherein the trench extends into the
semiconductor substrate;

spacers along the bit line openings, the spacers extending into the semiconductor substrate;
the bit line openings comprising p-type pocket implant regions disposed therein, the pocket implant regions adjacent and below
said charge storage nodes wherein an upper boundary of each pocket implant region is congruent with a lower boundary of the
adjacent charge storage node and a first n-type bit line implant region, having a first width, disposed within the bit line
opening adjacent to and extending below said pocket implant regions.

US Pat. No. 9,209,197

MEMORY GATE LANDING PAD MADE FROM DUMMY FEATURES

Cypress Semiconductor Cor...

1. A semiconductor device, comprising:
a substrate;
a first memory cell gate disposed on the substrate;
a dummy feature disposed on the substrate;
a counterpart memory cell gate disposed on the substrate, wherein the counterpart memory cell gate is located between the
first memory cell gate and the dummy feature so as to form a bridge portion that is below opposing edges of the first memory
cell gate and the dummy feature; and

a contact at least partially disposed on the bridge portion and at least partially disposed on the dummy feature,
wherein the counterpart memory cell gate is a memory gate disposed over a charge trapping dielectric.

US Pat. No. 9,157,150

METHOD OF OPERATING A PROCESSING CHAMBER USED IN FORMING ELECTRONIC DEVICES

Cypress Semiconductor Cor...

1. A method of processing an electronic device comprising:
loading a workpiece into a processing chamber, the processing chamber at a loading temperature;
operating the processing chamber at a first temperature while the workpiece is being processed;
decreasing the temperature within the processing chamber from a first temperature to a second temperature less than the first
temperature and less than the loading temperature;

removing the workpiece and a carrier holding the workpiece from the processing chamber while decreasing the temperature within
the processing chamber, by turning off power to all heating elements used to control the temperature within the processing
chamber, from the second temperature to a third temperature lower than the first temperature and the second temperature;

increasing the temperature within the processing chamber to a fourth temperature greater than the second temperature and less
than the first temperature while the processing chamber has no workpiece or carrier within; and

maintaining the temperature within the processing chamber at the fourth temperature for a time period to perform an outgassing
operation closing a shutter adjacent to and outside of the processing chamber after the workpiece and the carrier are removed,
wherein closing the shutter is performed after removing the workpiece and before increasing the temperature, the shutter not
sealing the processing chamber from the ambient environment.

US Pat. No. 9,159,568

METHOD FOR FABRICATING MEMORY CELLS HAVING SPLIT CHARGE STORAGE NODES

Cypress Semiconductor Cor...

4. A method of fabricating a memory array of memory cells having a split charge storage node, said method comprising:
forming a semiconductor substrate from semiconductor material;
forming a plurality of memory cells on said semiconductor substrate wherein the formation of each of the plurality of memory
cells comprises:

forming a first trench and an adjacent second trench in said semiconductor substrate, the first trench and the second trench
each defining a first sidewall and a second sidewall respectively;

forming a first source/drain region in the substrate and a second source/drain region in the substrate, the first source/drain
region and the second source/drain region formed substantially under the first trench and the second trench in the semiconductor
substrate respectively;

forming a rectangular bit line punch through barrier in the substrate between the source and the drain of the first source/drain
region and the second source/drain region,

forming a discrete first oxide layer on each of the first and second sidewalls of the first and second trenches, the discrete
first oxide layers of the first trench contacting a portion of the first source/drain region and the discrete first oxide
layers of the second trench contacting a portion of the second source/drain region;

forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall
of the second trench wherein a portion of the punch through barrier is formed above portions of the first and the second storage
elements;

forming a second oxide layer on the first and second sidewalls of the first and second trenches, the second oxide layer being
formed contiguously over the first and second storage elements and the discrete first oxide layers of the first and second
trenches;

forming a word line in contact with the first storage element and the second storage element; and
forming a plurality of contacts for each of said plurality of memory cells that are formed on said semiconductor substrate.

US Pat. No. 9,154,160

CAPACITANCE TO CODE CONVERTER WITH SIGMA-DELTA MODULATOR

CYPRESS SEMICONDUCTOR COR...

9. An apparatus comprising:
a sensing device comprising a plurality of drive lines and a plurality of sense lines to form a plurality of sense elements,
wherein the plurality of sense elements comprises intersections between the plurality of drive lines and the plurality of
sense lines, wherein the plurality of sense elements is represented as capacitors;

an excitation signal source to provide a drive signal;
a modulation circuit to be selectively coupled to one or more of the plurality of sense elements; and
a switching circuit having a plurality of switches controlled by a variable-period clock, wherein the modulation circuit is
to measure mutual capacitances of the plurality of sense elements using the plurality of switches, and wherein the modulation
circuit is to convert the measured mutual capacitances to digital values, wherein the modulation circuit is to measure one
or more of the mutual capacitances of the one or more of one of the plurality of sense elements by applying the drive signal
to a respective one of the plurality of drive lines and sensing the drive signal on a corresponding one of the plurality of
sense lines.

US Pat. No. 9,153,541

SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR CHIP MOUNTED ON AN INSULATOR FILM AND COUPLED WITH A WIRING LAYER, AND METHOD FOR MANUFACTURING THE SAME

Cypress Semiconductor Cor...

1. A semiconductor device comprising:
a first insulator film having a first opening and a first surface;
a first wiring layer comprising first portions that extend from the first opening onto the first surface of the first insulator
film in first and second directions and a second portion, situated between the first portions, that comprises a first surface
that is coplanar with the first surface of the first insulator film onto which the first portions extend and a second surface
that is coplanar with a second surface of the first insulator film wherein the first surface of the first insulator film and
the second surface of the first insulator film are single leveled;

a first semiconductor chip mounted on the first insulator film and electrically coupled with the first wiring layer;
a resin portion applied onto the first insulator film and adjacent to the sides of the semiconductor chip and adjacent to
the surface of the semiconductor chip that faces away from the first insulator film and the first wiring layer;

a second insulator film having a second opening applied onto the resin portion; and
a second wiring layer extending between the second insulator film and the resin portion, wherein the resin portion fills the
volume between the semiconductor chip and the second insulator film, between the semiconductor chip and the second wiring
layer, between the first insulator film and the second insulator film, and between the first wiring layer and the second wiring
layer.

US Pat. No. 9,116,581

EDGE ACCURACY IN A CAPACITIVE SENSE ARRAY

Cypress Semiconductor Cor...

1. A capacitive sense array, the array comprising:
a first set of sense elements having a plurality of non-homogenous pitches, the first set of sense elements disposed in a
first longitudinal axis of the capacitive sense array, wherein a pitch of a sense element of the first set of sense elements
comprises a width of the sense element and a spacing between the sense element and an adjacent sense element of the first
set of sense elements, wherein the sense element is not directly coupled to any other of the first sense elements through
a conductor, the width of the sense element is different from a width of the adjacent sense element, and spacing between a
plurality of sense elements of the first set of sense elements is non-homogenous.

US Pat. No. 9,098,641

CONFIGURABLE BUS

Cypress Semiconductor Cor...

1. A device comprising:
an analog block array;
a first analog bus segment coupled to the analog block array;
a second analog bus segment coupled to the analog block array;
a third analog bus segment coupled to the analog block array;
a fourth analog bus segment, coupled to the analog block array;
a first I/O pin selectively couplable to the first analog bus segment;
a second I/O pin selectively couplable to the second analog bus segment;
a third I/O pin selectively couplable to the third analog bus segment;
a fourth I/O pin selectively couplable to the fourth analog bus segment;
a first switch configured to selectively propogate a first analog signal on the first analog bus segment to the second analog
bus segment;

a second switch configured to selectively propogate a second analog signal on the first analog bus segment to the third analog
bus segment;

a third switch configured to selectively propogate a third analog signal on the second analog bus segment to the fourth analog
bus segment;

a fourth switch configured to selectively propogate a fourth analog signal on the third analog bus segment to the fourth analog
bus segment;

wherein,
in a first mode of operation, the first, second, third, and fourth switches are open,
in a second mode of operation, the first switch is closed, and
in a third mode of operation, the second switch is closed.

US Pat. No. 9,508,651

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Cypress Semiconductor Cor...

1. A semiconductor device comprising:
a semiconductor chip;
a bump electrode, at least partially spheroidal in shape, having a height of approximately 300 micrometers, formed on an upper
face of the semiconductor chip wherein the bump electrode physically contacts the upper face of the semiconductor chip, wherein
an upper face of the bump electrode is flat and wherein a lower face of the bump electrode that physically contacts the upper
surface of the semiconductor chip is flat;

a molding portion that seals an entire side face of the semiconductor chip and seals the bump electrode so that a part of
the bump electrode is exposed;

a planar redistribution layer formed on an upper face of the molding portion and connected to the exposed part of the bump
electrode, electrically coupled to the semiconductor chip via the bump electrode, wherein the height of the bump electrode
is measured from the planar redistribution layer to the upper face of the semiconductor chip; and

a spheroidal outer connection electrode formed on an upper face of the redistribution layer that extends laterally beyond
the redistribution layer, wherein the spheroidal outer connection electrode is electrically coupled to the bump electrode
via the redistribution layer, wherein the spheroidal outer connection electrode is one of a plurality of outer connection
electrodes that each lie laterally beyond sides of the semiconductor chip and wherein the bump electrode and the spheroidal
outer connection electrode are positioned on opposite sides of the redistribution layer, wherein the redistribution layer
is positioned directly underneath and connected to the spheroidal outer connection electrode.

US Pat. No. 9,472,563

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR

Cypress Semiconductor Cor...

1. A method of fabricating a semiconductor device, comprising the steps of:
providing a semiconductor substrate;
forming bit lines in the semiconductor substrate in a first direction by injecting ions into the semiconductor substrate,
wherein the bit lines are spaced apart from one another by an interval;

forming an oxide-nitride-oxide (ONO) film on the semiconductor substrate;
forming a polycrystalline silicon film on the ONO film;
patterning the polycrystalline silicon film to form a plurality of word lines and at least one dummy layer on the ONO film,
the plurality of word lines extending in a second direction that is perpendicular to the first direction, and the at least
one dummy layer is formed in the interval and in a bit-line contact region between a first one of the plurality of word lines
and a second one of the plurality of word lines adjacent to the first one;

wherein a first maximum spacing between the at least one dummy layer and the first one of the plurality of word lines is substantially
equal to a second maximum spacing between the at least one dummy layer and the second one of the plurality of word lines.

US Pat. No. 9,466,374

SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE LINES

Cypress Semiconductor Cor...

1. A method comprising:
receiving a first voltage at a first transistor, the first transistor coupled to a second transistor, the first transistor
and second transistor included in a first memory cell;

receiving a second voltage at a third transistor, the third transistor coupled to a fourth transistor, the third transistor
and fourth transistor included in a second memory cell, the first memory cell and the second memory cell coupled to a common
source line;

receiving a third voltage at the second transistor and at the fourth transistor; and
receiving a fourth voltage at the first transistor, the fourth voltage causing, via Fowler-Nordheim tunneling, a change in
one or more electrical properties of a charge storage layer included in the first transistor.

US Pat. No. 9,455,352

HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE

CYPRESS SEMICONDUCTOR COR...

1. A dual-bit memory cell comprising:
a charge trapping dielectric stack disposed overlying an essentially planar upper surface of a semiconductor substrate;
a poly gate disposed overlying the charge trapping dielectric stack;
p-type pocket implant regions having a first portion under a peripheral portion of the charge trapping dielectric stack and
a second portion adjacent to the charge trapping dielectric stack and disposed in a bit line opening;

spacers laterally adjacent the charge trapping dielectric stack and poly gate, wherein a first portion of each spacer overlies
the second portion of each pocket implant region;

a bit line implant region disposed in the semiconductor substrate adjacent the charge trapping dielectric stack and under
the bit line opening wherein the bit line implant region has an upper surface congruent with the upper surface of the semiconductor
surface; and

a word line.

US Pat. No. 9,396,959

SEMICONDUCTOR DEVICE WITH STOP LAYERS AND FABRICATION METHOD USING CERIA SLURRY

Cypress Semiconductor Cor...

1. A method of fabricating a semiconductor device comprising:
forming a first metal layer partially above a substrate;
etching the first metal layer and the substrate using a first mask to form first wiring layers and a trench in the substrate;
forming a first interlayer insulating film between and on the first wiring layers and planarizing the first interlayer insulating
film so that the trench is filled and a top surface of the first interlayer insulating film is above the first wiring layers;

forming a second metal layer partially above the first interlayer insulating film, and forming silicon oxynitride on the second
metal layer;

etching the silicon oxynitride and the second metal layer using a second mask to form second wiring layers partially above
the first interlayer insulating film, and stop layers on the second wiring layers;

forming a cover film between and on the first layers, so that a top surface of the cover film above a region between stop
layers is higher than top surfaces of the stop layers, wherein the first cover film comprises silicon dioxide; and

forming an embedded layer between the second wiring layers and stop layers, by polishing the cover film to the stop layers
using chemical mechanical polishing (CMP).

US Pat. No. 9,361,973

MULTI-CHANNEL, MULTI-BANK MEMORY WITH WIDE DATA INPUT/OUTPUT

CYPRESS SEMICONDUCTOR COR...

1. An integrated circuit (IC) device, comprising:
M memory banks, where M is greater than 2, and each memory bank is separately accessible according to a received address value;
N channels, where N is greater than 2, and each channel includes its own data connections, address connections, and control
input connections for executing a read or write access to one of the memory banks in synchronism with a clock signal, and
wherein each channel is configured to transfer greater than one bit on each read or write access; and

a controller subsystem configured to control accesses between each channel of the N channels and each memory bank of the M
memory banks, and wherein the controller subsystem is configured to control a first access on every channel of the N channels
during a first cycle of the clock signal, wherein each access of the first access on every channel is responsive to a different
memory address, and control a second access on every channel of the N channels during a second cycle of the clock signal wherein
the first cycle and the second cycle are consecutive cycles of the clock signal.

US Pat. No. 9,305,995

METHODS OF FABRICATING AN F-RAM

CYPRESS SEMICONDUCTOR COR...

1. A method comprising:
forming a contact extending through a first dielectric layer on a surface of a substrate;
forming a barrier structure over the contact, wherein forming the barrier structure comprises, depositing a barrier layer
over the first dielectric layer and the contact, patterning the barrier layer to form the barrier structure over the contact,
and depositing a second dielectric layer over the patterned barrier layer and the first dielectric layer, and planarizing
the second dielectric layer to expose a top surface of the barrier structure;

depositing a ferro-stack over the barrier structure, the ferro-stack including a bottom electrode layer deposited on the barrier
structure and second dielectric layer, a ferroelectric layer on the bottom electrode layer and a top electrode on the ferroelectric
layer; and

patterning the ferro-stack to form a ferroelectric capacitor over the barrier structure, wherein the barrier layer is conductive
and a bottom electrode of the ferroelectric capacitor is electrically coupled to the contact through the barrier structure.

US Pat. No. 9,263,988

CRYSTAL OSCILLATION CIRCUIT

Cypress Semiconductor Cor...

1. A crystal oscillation circuit, comprising:
a crystal oscillator;
an inverter unit coupled in parallel with the crystal oscillator, the inverter unit comprising a plurality of inverters,
a current supply unit configured to supply a first current to at least a first inverter of the plurality of inverters;
a signal converter configured to supply a second current to at least a last inverter of the plurality of inverters and output
an output voltage to an external circuit; and

a current controller configured to control the first current according to a voltage level of the output voltage,
wherein the plurality of inverters comprises an odd number of three or more of inverters.

US Pat. No. 9,252,659

DC-DC CONVERTER WITH ADAPTIVE PHASE COMPENSATION CONTROLLER

CYPRESS SEMICONDUCTOR COR...

1. A DC-DC converter for generating an output voltage from an input voltage, comprising:
an error amplifier configured to receive a feedback voltage at a first input in accordance with the output voltage, to receive
a reference voltage at a second input, and to output an amplified voltage, the amplified voltage corresponding to a difference
between the feedback voltage and the reference voltage;

a phase compensation circuit configured to adjust a phase of the feedback voltage, the phase compensation circuit having at
least one variable impedance element controlled by a control voltage and coupled to the error amplifier; and

a phase compensation controller configured to generate the control voltage by amplifying a voltage difference between the
input voltage and output voltage to control a phase compensation component of the phase compensation circuit.

US Pat. No. 9,251,914

TEST CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME

Cypress Semiconductor Cor...

1. A test control circuit comprising:
an address sequencer that generates a first address for selecting a cell in a predetermined order;
a register that stores a second address of a cell that is determined to be a fail by a verify determination;
a selector that selects the first address generated by the address sequencer or the second address stored in the register
based on whether or not one or more predetermined number of addresses have been stored in the register; and

a verify determination circuit that performs a verify determination of a cell which is indicated by the address selected by
the selector;

wherein the verify determination circuit performs a first verify determination of a cell which is indicated by the first address
generated by the address sequencer and performs a second verify determination of one or more cells which are indicated by
the one or more predetermined number of addresses after a predetermined voltage has been applied to a plurality of cells of
an erase unit where there is a cell determined to be a fail in the first verify determination in a state in which the one
or more predetermined number of addresses have been stored in a register, and

wherein the selector selects the first address generated by the address sequencer after the second verify determination has
been finished.

US Pat. No. 9,246,387

OUTPUT VOLTAGE CONTROLLER, ELECTRONIC DEVICE, AND OUTPUT VOLTAGE CONTROL METHOD

Cypress Semiconductor Cor...

18. An output voltage controller, comprising:
an input voltage terminal configured to receive an input voltage;
an output voltage terminal configured to output an output voltage;
an inductor coupled between the input voltage terminal and the output voltage terminal;
a first controller configured to control a current supply to an inductor based on an output voltage and to generate an output
signal;

a second controller comprising a delay circuit and configured to control the current supply by based on the input voltage
by generating a first adjustment signal, a second adjustment signal, and a control signal; and

a logic circuit configured to generate a driving signal for controlling the current supply based on the output signal and
the first adjustment signal, the second adjustment signal and the control signal.

US Pat. No. 9,164,605

FORCE SENSOR BASELINE CALIBRATION

Cypress Semiconductor Cor...

1. An apparatus, comprising:
one or more inputs configured to receive a force signal from a force sensor and a touch signal from a touch sensor, wherein
the force signal indicates a magnitude of a force applied at a sensing surface, and wherein the touch sensor includes a capacitance
sensor; and

processing logic coupled with the one or more inputs, wherein the processing logic is configured to
determine a relative force magnitude based on the force signal and a baseline measurement of the force sensor, and
update the baseline measurement of the force sensor in response to the touch signal received from the capacitance sensor that
indicates a removal of one or more touches from the sensing surface, the force signal being received after a detecting of
the removal of the one or more touches from the sensing surface, the force signal being a raw force signal,

wherein the update of the baseline measurement of the force sensor comprises setting the baseline measurement equal to a signal
level of the force signal, wherein the signal level corresponds to a time during which the touch signal indicates that the
one or more touches are removed from the sensing surface.

US Pat. No. 9,589,805

SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE

Cypress Semiconductor Cor...

1. A method of making a semiconductor device, comprising:
forming a dielectric layer on a substrate;
forming a gate stack having a first gate conductor and a gate dielectric structure between the first gate conductor and the
dielectric layer;

forming an inter-gate dielectric structure at a sidewall of the gate stack; and
forming an L-shaped second gate conductor adjacent to the inter-gate dielectric structure and on the dielectric layer, wherein
a vertical portion of the L-shaped second gate conductor is located on a side of the L-shaped second gate conductor that is
opposite, relative to a center of the L-shaped second gate conductor, from a conductive structure that is higher than at least
a horizontal portion of the L-shaped second gate conductor.

US Pat. No. 9,514,816

NON-VOLATILE STATIC RAM AND METHOD OF OPERATION THEREOF

CYPRESS SEMICONDUCTOR COR...

1. A memory device, comprising:
a static random access memory (SRAM) circuit including a first data latch node and a second data latch node, the first data
latch node configured to be maintained at a first voltage representing one bit of binary data and the second data latch node
configured to be maintained at a second voltage representing one bit of complementary binary data;

a non-volatile (NV) circuit including a first ferroelectric capacitor (F-Cap) coupled to the first data latch node and configured
to store the one bit of binary data, wherein the first F-Cap is further coupled to a first bit-line and configured to output
the one bit of binary data thereto; and

a discharge circuit including first and second discharge transistors controllable by a common discharge signal, wherein a
source terminal of the first discharge transistor is configured to be coupled to ground and a drain terminal of the first
discharge transistor is coupled to the first F-Cap to provide a discharge path for charges accumulated thereat.

US Pat. No. 9,250,299

UNIVERSAL INDUSTRIAL ANALOG INPUT INTERFACE

Cypress Semiconductor Cor...

1. A sensor system comprising:
a plurality of sensors configured to generate a plurality of electrical signals in response to at least one condition;
a measurement subsystem configured to convert the electrical signals to digitized values,
wherein the plurality of sensors is ohmically isolated from the measurement subsystem, and
wherein at least one of the plurality of sensors is coupled to the measurement subsystem through an analog isolation circuit;
and

a configuration circuit for adjusting the electrical signals of the plurality of sensors, wherein the configuration circuit
comprises a resistor network, a multiplexor coupled between the resistor network and the analog optoisolator, and a microcontroller
configured to send signals to the multiplexor to connect and disconnect resistors in the resistor network based on expected
electrical signals from each of the plurality of sensors.

US Pat. No. 9,210,571

SECURE WIRELESS COMMUNICATION

Cypress Semiconductor Cor...

1. A method comprising:
sending a request for a public key from a remote node to a host;
receiving the public key at the remote node, wherein the public key corresponds to a private key that is kept at the host;
encrypting a session key into an encrypted session key at the remote node using the public key;
sending the encrypted session key from the remote node to the host; and
using the session key at the remote node in encrypted wireless communication with the host.

US Pat. No. 9,177,617

METHODS CIRCUITS APPARATUSES AND SYSTEMS FOR PROVIDING CURRENT TO A NON-VOLATILE MEMORY ARRAY AND NON-VOLATILE MEMORY DEVICES PRODUCED ACCORDINGLY

CYPRESS SEMICONDUCTOR COR...

1. A power supply circuit for a non-volatile memory (NVM) array, said circuit comprising:
a voltage source adapted to output an array supply current at substantially a target voltage;
a regulating transistor whose channel is in series between an output terminal of said voltage source and an input terminal
of the NVM array; and

a bulk regulating circuit branch coupled to a bulk of said regulating transistor and adapted to reduce a bulk-voltage of said
regulating transistor when a voltage at the regulating transistor output terminal exceeds a first defined threshold voltage.

US Pat. No. 9,171,936

BARRIER REGION UNDERLYING SOURCE/DRAIN REGIONS FOR DUAL-BIT MEMORY DEVICES

CYPRESS SEMICONDUCTOR COR...

1. A memory cell, comprising:
a substrate having a thickness;
a stacked gate structure disposed on the substrate, the stacked gate structure comprising a charge trapping dielectric layer
that is adapted to store at least one bit of data;

a source in the substrate, the source disposed at a side of the stacked gate structure;
a drain in the substrate, the drain disposed at the other side of the stacked gate structure; and
a barrier region disposed substantially beneath the source or the drain and comprising at least one of helium, neon, argon,
krypton, or xenon,

wherein the barrier region is characterized by a retrograde doping profile that varies across a vertical thickness of the
substrate.