US Pat. No. 9,552,889

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

Conversant Intellectual P...

1. A system comprising:
a memory controller; and
at least one non-volatile memory device communicatively coupled to the memory controller, the non-volatile memory device comprising:
a non-volatile memory array;
a mode selection circuit to put the non-volatile memory device in either a first mode of operation or a second mode of operation;
a reference voltage input terminal configured to receive a reference voltage;
a first clock terminal configured to receive a positive clock signal;
a second clock terminal configured to receive a negative clock signal;
a common address and data terminal configured to receive a data input signal that include write data to be programmed into
the non-volatile memory array;

a data input buffer including a first comparator circuit to receive the data input signal and the reference voltage, and
i) when the non-volatile memory device is in the first mode of operation, the data input buffer is configured to compare the
data input signal to the reference voltage in providing a buffered data input signal; and

ii) when the non-volatile memory device is in the second mode of operation, the data input buffer is configured to provide
the buffered data input signal independent of the reference voltage; and

a clock input buffer including a second comparator circuit to receive the positive clock signal and the negative clock signal,
and

i) when the non-volatile memory device is in the first mode of operation, the clock input buffer is configured to compare
the positive clock signal and the negative clock signal in providing a buffered clock input signal; and

ii) when the non-volatile memory device is in the second mode of operation, the clock input buffer is configured to provide
the buffered clock input signal based on either the positive clock input signal or the negative clock input signal.

US Pat. No. 9,722,605

LOW LEAKAGE AND DATA RETENTION CIRCUITRY

Conversant Intellectual P...

1. A system for controlling power consumption within an integrated circuit, the system comprising:
a power island including a first circuit, the first circuit configured to:
receive input signals,
receive a hold signal,
process the input signals, and
retain data during a sleep state having low leakage based on the hold signal;
a sleep circuitry coupled to the first circuit, the sleep transistor configured to:
receive a voltage sleep signal, and
reduce power consumption of the first circuit during the sleep state, the first circuit having low leakage based on the sleep
signal while concurrently retaining the data; and

a source follower circuitry in parallel with said sleep circuitry, the source follower circuitry configured to provide a moderate
impedance while the sleep circuitry is in a sleep mode and reduce leakage in the first circuit by reducing the voltage across
the first circuit.

US Pat. No. 9,986,585

RELAY SYSTEMS AND METHODS FOR WIRELESS NETWORKS

CONVERSANT INTELLECTUAL P...

1. A method comprising, by a relay device in a wireless network that comprises an access point and one or more relay devices, the method comprising:detecting a relay-service desirability indication transmitted from a wireless station;
generating at least one link-quality-parameter measurement with respect to the wireless station;
transmitting information related to the at least one link-quality-parameter measurement to the access point;
forwarding the relay-service desirability indication to the access point;
detecting at least one uplink transmission transmitted by the wireless station, the at least one uplink transmission being intended for the access point, the at least one uplink transmission comprising the identifier of the wireless station;
looking up the identifier of the wireless station in client information stored in a memory of the relay device; and
responsive to the identifier for the wireless station being found in the client information, forwarding the at least one uplink transmission to the access point.

US Pat. No. 9,300,291

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

Conversant Intellectual P...

1. A method for controlling the impedance of a buffer having a plurality of pull-up transistors and a plurality of pull-down
transistors, the method comprising:
receiving a data output signal, the data output signal being selected from one of a test data output signal and a normal data
output signal;

receiving an output enable signal;
receiving a termination enable signal;
receiving a first plurality of impedance control bits, a second plurality of impedance control bits, a third plurality of
impedance control bits, and a fourth plurality of impedance control bits;

enabling, when the output enable signal is in a first state and the data output signal is in a first state, one or more of
the plurality of pull-up transistors determined by the first plurality of impedance control bits;

enabling, when the output enable signal is in a first state and the data output signal is in a second state, one or more of
the plurality of pull-down transistors determined by the second plurality of impedance control bits; and

enabling, when the termination enable signal is in a first state, one or more of the plurality of pull-up transistors determined
by the third plurality of impedance control bits and one or more of the plurality of pull-down transistors determined by the
fourth plurality of impedance control bits;

wherein the first and second pluralities of impedance control bits are independently controlled with respect to the third
and fourth pluralities of bits.

US Pat. No. 9,281,047

DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION

CONVERSANT INTELLECTUAL P...

1. A dynamic random access memory (DRAM) device, comprising:
a plurality memory banks each having a plurality of wordlines, each of the plurality of wordlines being connected to a plurality
of data store cells that are refreshable in a self-refresh mode;

a first storage for storing first bits, each of the first bits corresponding to a respective one of the plurality of memory
banks, to indicate whether or not the respective memory bank is to be refreshed in the self-refresh mode, and one or more
memory banks of the plurality of memory banks being indicated, by the first bits, to be refreshed in the self-refresh mode;
and

a second storage for storing second bits, the second bits indicating which subblocks of the one or more memory banks are to
be refreshed in the self-refresh mode, and

wherein, in the self-refresh mode, the DRAM device performs a self-refresh operation only for the subblocks of the one or
more memory banks to be refreshed.

US Pat. No. 9,183,892

DATA STORAGE AND STACKABLE CHIP CONFIGURATIONS

Conversant Intellectual P...

1. A system comprising:
a first memory device for storing data;
a second memory device for storing data, the second memory device having a same input/output layout configuration as the first
memory device;

a stack including the second memory device secured to the first memory device, the second memory device rotated 180 degrees
with respect to the first memory device such that outputs of the first memory device are positioned adjacent to corresponding
inputs to the second memory device; and

connectivity between the outputs of the first memory device and the inputs of the second memory device, the connectivity including
connections between surface pads on a plane of the first memory device and through-holes of the second memory device.

US Pat. No. 9,237,518

POWER SAVING IN WIRELESS NETWORK ENTITIES

Conversant Intellectual P...

1. A method comprising:
receiving, at a wireless station in a wireless network that comprises a wireless access point and the wireless station, a
notification, from the wireless access point, that the wireless station will become a delegate for transmitting beacons normally
transmitted by the wireless access point; and

transmitting, by the wireless station, beacons normally transmitted by the wireless access point and also information reflecting
remained duration of absence of the wireless access point.

US Pat. No. 9,263,146

FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME

Conversant Intellectual P...

1. A method for storing data in a memory cell of a selected memory block of a plurality of memory blocks, the method comprising:
erasing all memory cells of the selected memory block concurrently to have an erased state in an erase voltage domain; and,
programming the memory cell to have any one of a first portion of programmed states distinct from the erased state in the
erase voltage domain and a second portion programmed states in a program voltage domain;

wherein programming includes programming the memory cell to one of the first portion of programmed states, and the programming
further includes verifying the one of the first portion of programmed states by

precharging a bitline connected to the memory cell to a voltage level,
driving a wordline connected to the memory cell with a reference voltage in the erase voltage domain, and
sensing a change in the voltage level of the bitline when the memory cell conducts current in response to the reference voltage.

US Pat. No. 9,214,233

METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE

Conversant Intellectual P...

1. A flash memory device comprising:
a plurality of floating gate memory cell transistors;
a plurality of main word lines;
a plurality of local word lines;
first circuitry configured to provide a positive well bias voltage to enable a p-well for the plurality of floating gate memory
cell transistors to be biased to the positive well bias voltage;

second circuitry configured to provide a negative word line voltage to enable a selected main word line of the plurality of
main word lines to be biased to the negative word line voltage;

third circuitry configured to provide a positive word line voltage to enable a plurality of unselected main word lines of
the plurality of main word lines to be biased to the positive word line voltage; and

driver circuits configured to:
i) pass the negative word line voltage on the selected main word line to at least one selected local word line of the plurality
of local word lines, the at least one selected local word line being connected to gate terminals of selected ones of the floating
gate memory cell transistors, and the difference between the positive well bias voltage and the negative word line voltage
being sufficient to erase selected memory cells; and

ii) pass the positive word line voltage on the unselected main word lines to a plurality of unselected local word lines of
the plurality of local word lines, the unselected local word lines being connected to gate terminals of unselected ones of
the floating gate memory cell transistors.

US Pat. No. 9,166,412

POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Conversant Intellectual P...

1. A system comprising:
an integrated circuit comprising:
a semiconductor substrate; and
a plurality of power islands disposed on the semiconductor substrate having associated power consumptions, each of the power
consumptions being independently controllable by changing a supply voltage and an operating frequency;

an operating system software;
a first power manager configured to communicate with the operating system software and configured to receive a power control
command identifying one of the plurality of power islands and a rate of operation of the identified one of the plurality of
power islands; and

a second power manager disposed on the semiconductor substrate, the second power manager configured to communicate with the
first power manager to individually change the power consumptions, wherein the first power manager is configured to send a
power consumption change request to the second power manager in response to the power control command.

US Pat. No. 9,098,430

COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION

Conversant Intellectual P...

1. A composite semiconductor memory device, comprising:
a plurality of nonvolatile memory devices; and
an interface device connected to the plurality of nonvolatile memory devices and for connection to a memory controller, the
interface device comprising an error correction coding (ECC) engine, the interface device being coupled with each of the plurality
of nonvolatile memory devices through a dedicated connection, wherein the dedicated connection includes a link for an interface
channel that supports communication between the interface device and the plurality of nonvolatile memory devices, and wherein
the ECC engine is in communication with the plurality of nonvolatile memory devices via the dedicated connection.

US Pat. No. 9,484,097

MULTIPAGE PROGRAM SCHEME FOR FLASH MEMORY

Conversant Intellectual P...

1. A multi-page programming method for a NAND flash memory device comprising:
sequentially storing M pages of data in the NAND flash memory device before execution of a single multi-page programming cycle,
where M is an integer value greater than 1;

loading bitline access circuitry with the M pages of data; and
initiating, with respect to the M pages of data, the single multi-page programming cycle in the NAND flash memory device for
programming the M pages of data to a single physical page of memory cells by storing up to 2M threshold voltages in memory cells of the NAND flash memory device, wherein the single multi-page programming cycle includes

driving a selected wordline with different time periods for each of 2M?1 threshold voltages while bitlines are biased to enable or inhibit programming based on a combination of logic states of
the M pages of data.

US Pat. No. 9,350,349

LOW LEAKAGE AND DATA RETENTION CIRCUITRY

Conversant Intellectual P...

1. An integrated circuit comprising:
a plurality of power islands having associated power consumptions capable of being dynamically changed, each of the power
islands including circuitries and sleep transistors in coupled relation with the circuitries; and

a sleep generator in communication with at least one of the power islands to provide a variable voltage, and
the sleep transistors being included within the integrated circuit to facilitate reduction of power consumed by the circuitries,
and the sleep transistors being configured to receive the variable voltage that is:

i) generated by the sleep generator based on a control signal receivable from an adaptive leakage controller; and
ii) changed under control of the adaptive leakage controller.

US Pat. No. 9,330,765

NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE

Conversant Intellectual P...

1. A method comprising:
issuing a first command to a flash memory device having a plurality of planes, the first command including a first plane address
specifying a first plane and a first row address specifying a first row in the first plane;

issuing a second command to the flash memory device, the second command including a second plane address specifying a second
plane and a second row address specifying a second row in the second plane, to instruct the flash memory device to simultaneously
sense and transfer data stored in the first row and the second row to a first page buffer of the first plane and a second
page buffer of the second plane respectively;

issuing a third command to the flash memory device to instruct the flash memory device to output data from a first one of
the first and second page buffers;

receiving the data from the first one of the first and second page buffers;
issuing a fourth command to the flash memory device to instruct the flash memory device to output data from a second different
one of the first and second page buffers; and

receiving the data from the second different one of the first and second page buffers.

US Pat. No. 9,202,931

STRUCTURE AND METHOD FOR MANUFACTURE OF MEMORY DEVICE WITH THIN SILICON BODY

Conversant Intellectual P...

1. A semiconductor device comprising:
a semiconductor substrate having an upper surface;
a first strip comprised of a first dielectric material, the first strip having a first length in a first direction and a first
width, smaller than the first length, in a second direction, the first direction being parallel to the upper surface, and
the second direction also being parallel to the upper surface and substantially perpendicular to the first direction, and
the first strip having a first sidewall and a second sidewall along the first direction, the first and second sidewalls being
opposite to each other;

a second strip comprised of a second dielectric material different from the first dielectric material, the second strip having
a second length in the first direction and a second width, smaller than both the second length and the first width, in the
second direction, the second and first strips forming a first stack with the first strip being stacked on the second strip,
and the second strip having a third sidewall and a fourth sidewall along the first direction, the third and fourth sidewalls
being opposite to each other;

a third strip comprised of a conducting or semiconducting material, the third strip having a third length in the first direction
and a third width in the second direction, the third width being smaller than the third length, and the third strip having
a fifth sidewall and a sixth sidewall along the first direction, the fifth and sixth sidewalls being opposite to each other,
and the third strip covering a part of the second strip, at a same height location thereof, so that the fifth sidewall is
in contact with the third sidewall and the sixth sidewall is substantially coplanar with the first sidewall;

a fourth strip comprised of a conducting or semiconducting material, the fourth strip having a fourth length substantially
identical to the third length in the first direction and a fourth width smaller than the fourth length, the fourth width being
substantially identical to the third width in the second direction, and the fourth strip having a seventh sidewall and an
eighth sidewall along the first direction, the seventh and eighth sidewalls being opposite to each other, and the fourth strip
covering a part of the second strip, at a same height location thereof, so that the seventh sidewall is in contact with the
fourth sidewall and the eighth sidewall is substantially coplanar with the second sidewall;

a fifth strip comprised of a conducting or semiconducting material, the fifth strip having a fifth length in the second direction
and a fifth width in the first direction, the fifth width being smaller than the first, second, third, fourth and fifth lengths,
and the fifth strip being formed over portions of the first stack, covering a part of the top of the first strip and covering
parts of the first, second, sixth and eighth sidewalls, and

wherein the first sidewall is protruding relative to the third sidewall and the second sidewall is protruding relative to
the fourth sidewall.

US Pat. No. 9,159,380

BRIDGE DEVICE ARCHITECTURE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM

Conversant Intellectual P...

1. An apparatus comprising:
a host system comprising a processing device;
a memory controller operable to communicate with the host system;
a plurality of composite memory devices operable to communicate with the memory controller, each composite memory device operable
to be assigned a unique global device address, each composite memory device comprising:

a bridge device operable to receive a global command comprising global memory control signals having a first format, the bridge
device operable to convert the global memory control signals into local memory control signals having a second format; and

a plurality of discrete memory devices each operable to execute one or more memory operations in response to reception of
the local memory control signals.

US Pat. No. 9,158,344

CPU WITH STACKED MEMORY

Conversant Intellectual P...

1. A multi-chip package comprising:
a substrate having electrical contacts for connection to an external device;
a CPU die disposed on the substrate and being in communication with the substrate; the CPU die comprising:
a plurality of processor cores occupying a first area of the CPU die; and
an SRAM cache occupying a second area of the CPU die; and
a DRAM cache disposed on the CPU die and being in communication with the CPU die,
the DRAM cache comprising a plurality of stacked DRAM dies,
the plurality of stacked DRAM dies being substantially aligned with the second area of the CPU die; and
the plurality of stacked DRAM dies substantially not overlapping the first area of the CPU die.

US Pat. No. 9,257,193

MEMORY WITH OUTPUT CONTROL

Conversant Intellectual P...

1. A flash memory device comprising:
a flash memory array;
a page buffer for receiving read data from the flash memory array;
a clock input pin for receiving a clock signal; and
a data interface, synchronized with the clock signal, for providing the read data in the page buffer on a first number of
first edges of the clock signal, and for receiving command data at the data interface, the data interface having

a common command and data input for receiving input data and the command data at necessarily different times; and
an output enable pin for receiving an output enable signal set to a logic level for a same number of second edges of the clock
signal as the first number of the first edges, and the output enable signal for enabling the data interface to provide the
read data.

US Pat. No. 9,252,993

FREQUENCY DIVISION MULTIPLEXING SYSTEM WITH SELECTABLE RATE

Conversant Intellectual P...

1. An orthogonal frequency division multiplex (OFDM) communications apparatus employing a set of sub-carriers, which are orthogonal
over a time T, and symbols being expressed by superpositions of the sub-carriers, said apparatus being configured to transmit
a first OFDM symbol with duration of T and an associated guard time of TG, preceded or followed by a second OFDM symbol with duration of KT and an associated guard time of KTG, where K is a positive integer greater than 1 and where the first OFDM symbol and the second OFDM symbol have the same set
of sub-carriers.

US Pat. No. 9,230,654

METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE

Conversant Intellectual P...

1. A flash memory device comprising:
a flash memory array;
a page buffer to receive read data from the flash memory array;
a clock input pin to receive a clock signal; and
a data interface to provide the read data in the page buffer on a first number of first edges of the clock signal, and to
receive command data at the data interface, the data interface including:

a common command and data input to receive input data and the command data at different times; and
a control input pin to receive a control signal set to a logic level for a same number of second edges of the clock signal
as the first number of the first edges, and the control signal to enable the data interface to provide the read data.

US Pat. No. 9,583,496

MEMORY DEVICE WITH MANUFACTURABLE CYLINDRICAL STORAGE NODE

Conversant Intellectual P...

1. A memory device having a semiconductor substrate that includes a substrate surface, the memory device comprising:
a first conductive plate;
a second conductive plate;
a select transistor on the substrate surface, the select transistor including a source end and a drain end;
a conducting line having a location thereon that makes electrical connection to the source end of the select transistor;
a cylindrical storage element connected to the drain end of the select transistor, the cylindrical storage element including
a cylindrical conductive element, the cylindrical conductive element penetrating through at least the first conductive plate
and the second conductive plate;

an insulating film including:
a sidewall portion at least substantially perpendicular to the substrate surface and covering a side surface of the cylindrical
conductive element; and

a bottom portion at least substantially parallel to the substrate surface, and the insulating film intervening between the
first conductive plate and the cylindrical conductive element, and the insulating film further intervening between the second
conductive plate and the cylindrical conductive element; and

a hole defined by the bottom portion of the insulating film, and the cylindrical conductive element penetrating through the
hole and being electrically connected to the drain end of the select transistor.

US Pat. No. 9,384,847

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

CONVERSANT INTELLECTUAL P...

1. A semiconductor device comprising:
a mode selection circuit to put the semiconductor device in either a first mode of operation or a second mode of operation;
a reference voltage input terminal configured to receive a reference voltage;
a data terminal configured to receive a data input signal;
a first clock terminal configured to receive a first clock signal;
a second clock terminal configured to receive a second clock signal, and one of the first and second clock signals being a
positive clock input signal;

a first comparator to: i) receive the reference voltage and the data input signal; and ii) provide a first data signal;
a first buffer to: i) receive the data input signal; and ii) provide a second data signal;
a selector circuit to: i) receive the first data signal and the second data signal; and ii) provide an internal data signal;
a second comparator to: i) receive the first clock signal and the second clock signal; and ii) provide a third clock signal;
a second buffer to receive the positive clock input signal and provide a fourth clock signal; and
a clock generator circuit to: i) receiving the third clock signal and the fourth clock signal; and ii) provide an internal
clock signal, and

wherein the selector circuit provides the internal data signal based on the first data signal in the first mode of operation
and on the second data signal in the second mode of operation, and the clock generator circuit provides the internal clock
signal based on the third clock signal in the first mode of operation and on the fourth clock signal in the second mode of
operation.

US Pat. No. 9,236,095

METHOD AND APPARATUS FOR SHARING INTERNAL POWER SUPPLIES IN INTEGRATED CIRCUIT DEVICES

Conversant Intellectual P...

1. A multichip system, said system including:
a first integrated circuit device with an internal power supply having a regulator connected to a regulator output terminal;
and

a second integrated circuit device with a respective internal power supply controllable by a signal produced by said regulator
output terminal, wherein said signal produced by said regulator output terminal controls voltage of said second integrated
circuit device, and wherein the internal power supply of said second integrated circuit device includes a respective regulator,
said first and second integrated circuit devices including respective regulator enable terminals providing a corresponding
signal for selectively enabling and disabling said regulators.

US Pat. No. 9,201,489

CIRCUIT, SYSTEM AND METHOD FOR SELECTIVELY TURNING OFF INTERNAL CLOCK DRIVERS

Conversant Intellectual P...

1. A clock control method comprising:
generating, by a first circuit element of clock control circuitry, a first signal indicating idle time in a memory device
that comprises a memory array,

generating, by a second circuit element of the clock control circuitry, a second signal indicating an absence of a read/write
burst operation; and

selectively gating, by clock gating circuitry of the clock control circuitry, a system clock in response to a gating signal,
the gating signal being generating based at least in part on the first signal and the second signal.

US Pat. No. 9,177,863

MULTI-CHIP PACKAGE WITH OFFSET DIE STACKING AND METHOD OF MAKING SAME

Conversant Intellectual P...

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate having a plurality of electrical connections;
mounting a first semiconductor die from a first group of semiconductor dice to the substrate such that a first plurality of
bonding pads arranged along a first bonding edge of the first semiconductor die is oriented to face in a first direction;

mounting the remaining semiconductor dice from the first group of semiconductor dice to the substrate such that:
a first plurality of bonding pads arranged along a first bonding edge of each of the first group of semiconductor dice is
oriented to face in the first direction; and

each remaining semiconductor die of the first group of semiconductor dice is laterally offset relative to the first semiconductor
die in a second direction opposite the first direction by a respective lateral offset distance;

mounting a second group of semiconductor dice, intermixed with or over the first group of semiconductor dice, to the substrate
such that:

a first plurality of bonding pads arranged along a first bonding edge of each of the second group of semiconductor dice is
oriented to face in the second direction; and

each semiconductor die of the second group of semiconductor dice is laterally offset relative to the first semiconductor die
in the first direction by a respective lateral offset distance; and

connecting bond wires between the plurality of electrical connections of the substrate and the respective bonding pads of
the first and second groups of semiconductor dice after mounting the first and second groups of semiconductor dice to the
substrate.

US Pat. No. 9,123,394

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE

Conversant Intellectual P...

1. A device comprising:
a plurality of semiconductor dies stacked and connected together, at least one of the dies comprising a plurality of partitions;
and

a plurality of vaults, at least one vault comprising a grouping of the partitions in one of the dies, each vault having an
independent connection to a logic die by at least one wide bus;

wherein the independent connection of the logic die to the at least one vault is reallocated from a first wide bus to a second
wide bus in the event of a malfunction in the first wide bus.

US Pat. No. 9,117,685

RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES

Conversant Intellectual P...

1. A method of operating a plurality of stacked integrated circuit dice, the dice being serially connected in a ring topology,
each die including a plurality of vias extending therethrough for providing external access to signals on the die, the vias
of each die being connected to the vias of an adjacent die, the method comprising:
causing the vias of at least one die to assume a signaling connection configuration in which native circuitry of the at least
one die is connected by selected ones of the vias for signaling with an adjacent die; and

causing the vias of the at least one die to assume a signaling disconnect configuration in which the native circuitry of the
at least one die is not connected for signaling with the adjacent die.

US Pat. No. 9,972,381

MEMORY WITH OUTPUT CONTROL

Conversant Intellectual P...

1. A flash memory device comprising:a flash memory comprising a plurality of erasable blocks, each erasable block comprising a plurality of pages, each page comprising a plurality of flash memory cells;
a clock input port configured to receive a clock signal;
at least one common data interface configured to transfer command data, address data, input data and output data, wherein at least one of command data, address data, input data and output data is transferred in synchronization with both rising and falling edges of the clock signal when the flash memory device is in a double data rate configuration;
a control input port configured to receive a control signal, wherein a transition of the control signal from an inactive state to an active state indicates a beginning of command data being received at the at least one common data interface;
a control circuitry configured to execute a page program operation to store the input data on a selected page, and to execute a read operation to retrieve the output data from the flash memory cells in accordance to the command data and address data received at the at least one common data interface; and
a status register configured to indicate a status of the flash memory device.

US Pat. No. 9,917,511

CIRCUIT FOR CLAMPING CURRENT IN A CHARGE PUMP

Conversant Intellectual P...

1. A charge pump comprising:
a first capacitor coupled to an output of the charge pump;
a pump up current path comprising:
a first transistor coupled between a first power supply and a first node, the gate of the first transistor coupled to a first
output of a phase detector, and

a second transistor coupled between the first node and said first capacitor, the gate of the second transistor coupled to
a first bias input;

a pump down current path comprising:
a third transistor coupled between a second power supply and a second node, the gate of the third transistor coupled to a
second output of said phase detector, and

a fourth transistor coupled between the second node and the first capacitor, the gate of the fourth transistor coupled to
a second bias input;

a first alternate current path coupled to a first intermediate node and said first bias input, the first alternate current
path configured to conduct current when said first transistor is switched to an off state;

a second alternate current path coupled to a second intermediate node and said first power supply second bias input, the second
alternate current path configured to conduct current when said third transistor is switched to an off state;

wherein said first alternate current path comprises a fifth transistor coupled between the first node and an output node of
an analog repeater circuit,

wherein said second alternate current path comprises a sixth transistor coupled between the second node and the output node
of the analog repeater circuit, and

wherein said output of the analog repeater circuit replicates a voltage across the first capacitor.

US Pat. No. 9,245,640

NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES

Conversant Intellectual P...

1. A memory device comprising:
a memory for storing data;
input/output logic for enabling access to the data in the memory;
a first input pin for receiving a first external voltage to power the input/output logic;
a second input pin to receive a second external voltage, a magnitude of the second external voltage being greater than a magnitude
of the first external voltage; and

power management circuitry for receiving the second external voltage and converting the second external voltage into at least
a first internal voltage, a second internal voltage, and a third internal voltage, the first, second, and third internal voltages
each having a magnitude different than one another and the magnitude of the second external voltage, and

wherein modification of the data in the memory is enabled at least in part by the first, second, and third internal voltages
provided by the power management circuitry.

US Pat. No. 9,236,394

THREE DIMENSIONAL NONVOLATILE MEMORY CELL STRUCTURE WITH UPPER BODY CONNECTION

Conversant Intellectual P...

1. A non-volatile memory device, comprising:
a substrate comprising a source line region of a first conductivity type formed at a surface of the substrate; and
a NAND flash memory array formed over the substrate comprising a plurality of NAND flash strings, each comprising a vertical
channel string body connected between the source line region and an upper semiconductor layer which extends parallel to the
surface of the substrate, where the upper semiconductor layer comprises:

a horizontal string body region connected to each vertical channel string body,
a drain region of the first conductivity type connected to each horizontal string body region, and
a body line contact region of a second, opposite conductivity type connected to each horizontal string body region.

US Pat. No. 9,213,630

NON-VOLATILE MEMORY DEVICES AND CONTROL AND OPERATION THEREOF

Conversant Intellectual P...

1. A system comprising:
control apparatus;
a non-volatile memory integrated circuit chip including:
a non-volatile memory array organized into divisions, and the non-volatile memory array being further divided into subdivisions,
each in a respective division of the divisions, and the subdivisions being blocks that include a plurality of general use
erase blocks and redundant erase blocks; and

a control circuit including a storage configured to have redirect information programmed therein, and the control circuit
configured to receive an extended memory address referencing a first erase block in a first division of the divisions, the
extended memory address including a first portion associated with a normal address space, and a second portion associated
with general use access to available unutilized redundant erase blocks in the divisions, and the control circuit also configured
to redirect accesses, from the first erase block in the first division to a second erase block in a second division of the
divisions, by referencing the redirect information in the storage; and

an address communications path coupling the control apparatus to the non-volatile memory integrated circuit chip.

US Pat. No. 9,213,389

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH POWER-SAVING FEATURE

Conversant Intellectual P...

1. A method comprising:
causing a non-volatile semiconductor memory device to switch from a first operational state to a second operational state
in response to recognizing an erase command or a program command received by the non-volatile semiconductor memory device;

electrically connecting a voltage supply terminal of the non-volatile semiconductor memory device to a node of the non-volatile
semiconductor memory device when the non-volatile semiconductor memory device is in the first operational state;

electrically decoupling the voltage supply terminal from the node when the non-volatile semiconductor memory device is in
the second operational state;

causing the non-volatile semiconductor memory device to switch from the second operational state back to the first operational
state; and

issuing a status signal to indicate that the non-volatile semiconductor memory device is ready, after the non-volatile semiconductor
memory device is caused to switch back to the first operational state.

US Pat. No. 9,595,336

VERTICAL GATE STACKED NAND AND ROW DECODER FOR ERASE OPERATION

CONVERSANT INTELLECTUAL P...

1. A method, comprising:
erasing a first erase block of three-dimensional NAND memory strings by selectively applying a first erase voltage to only
a first source line connected to the first erase block of three-dimensional NAND memory strings;

while applying the first erase voltage to the first source line, concurrently applying a second voltage to a second source
line connected to a second erase block to prevent erasure of the second erase block, each of the first erase block and the
second erase block being separately erasable; and

inputting a row address into a row decoding circuitry, the row decoding circuitry comprising a plurality of pass blocks, and
the row address comprising block address bits and page address bits, each pass block comprising a plurality of pass transistors
for passing wordline, string select line and source line voltages.

US Pat. No. 9,490,014

METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE

Conversant Intellectual P...

14. A solid state mass storage system comprising:
a controller; and
a plurality of non-volatile memory devices coupled to the controller, each of the plurality of non-volatile memory devices
comprising:

a chip select input for receiving a chip select signal from the controller for activating the plurality of non-volatile memory
banks, each of the plurality of non-volatile memory banks being independently operable and comprising control circuitry, row
decoding circuitry, column decoding circuitry, sense amplifier circuitry, and non-volatile memory cell array;

a common interface for receiving a plurality of data streams, each data stream comprising command data, address data and write
data receivable at different times;

a first addressing circuitry for parsing a first data stream to extract a first memory bank identifier of a first of the plurality
of non-volatile memory banks;

a first memory bank status register for updating a first memory bank status by setting a bit value in the first memory bank
status register to indicate that the first non-volatile memory bank is busy;

a first data register for routing a first write data of the first data stream between the common interface and the non-volatile
memory cell array of the first non-volatile memory bank;

a second addressing circuitry for parsing a second data stream to extract a second memory bank identifier of a second of the
plurality of non-volatile memory banks, the second data stream being received at the common interface while the first non-volatile
memory bank is busy;

a second memory bank status register for updating a second memory bank status by setting a bit value in the second memory
bank status register to indicate that the second of the plurality of non-volatile memory banks is busy; and

a second data register for routing a second write data of the second data stream between the common interface and the non-volatile
memory cell array of the second non-volatile memory bank while the first non-volatile memory bank is busy.

US Pat. No. 9,325,811

METHOD AND SYSTEM FOR PACKET PROCESSING

Conversant Intellectual P...

1. An integrated circuit comprising:
a data processor disposed on the integrated circuit, the data processor comprising a plurality of processors each operable
to process data;

an input port operable to receive packets of data;
at least one port operable to communicate with each of the plurality of processors;
a first processor, also disposed on the integrated circuit, in communication with the at least one port and operable to process
received data to insert a header including a list of processes to perform on at least one of the packets of received data
and an ordering of the processes specified in the header, the header stored within a packet of data to which the header relates;

a buffer that is operable to store data from the at least one port; and
a buffer controller of the buffer, the buffer controller operable to:
determine, based on the header, a destination processor of the plurality of processors to process the data packet; and
to provide the data packet to the at least one port for provision to the destination processor.

US Pat. No. 9,142,557

COST EFFECTIVE METHOD OF FORMING EMBEDDED DRAM CAPACITOR

Conversant Intellectual P...

1. An integrated circuit device comprising:
a semiconductor substrate comprising one or more active circuits and at least a first conductive contact structure; and
a stacked interconnect structure formed on the semiconductor substrate with multiple interconnect levels, each interconnect
level comprising:

a metal-based damascene interconnect structure comprising a first directional diffusion barrier liner layer located on a sidewall
of a first opening in one or more patterned dielectric layers; and

a damascene capacitor structure comprising a second directional diffusion barrier liner layer located on a sidewall of a second
opening in the one or more patterned dielectric layers and a plurality of capacitor layers formed on the directional diffusion
barrier liner layer,

where the metal-based damascene interconnect structures in each interconnect level are aligned for electrical connection to
the one or more active circuits, and where the damascene capacitor structures in each interconnect level are aligned to form
a single capacitor having a first capacitor plate electrically connected to the first conductive contact structure.

US Pat. No. 9,928,918

NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES

Conversant Intellectual P...

1. A NAND flash memory device comprising:a NAND flash memory configured to store data;
I/O logic configured to enable access to the data in the NAND flash memory;
a first power input pin configured to receive an external Vcc power supply voltage;
a second power input pin configured to receive an external Vpp power supply voltage, the external Vpp power supply voltage being greater than the external Vcc power supply voltage;
a third power input pin configured to receive an external Vccq power supply voltage, the external Vccq power supply voltage powering the I/O logic;
a device information register configured to indicate whether the NAND flash memory device supports the external Vpp power supply voltage;
a device control register configured to enable the external Vpp power supply voltage via a configuration command; and
power management circuitry configured to convert the external Vpp power supply voltage into a plurality of internal voltages when the external Vpp power supply voltage is enabled by the device control register and convert the external Vcc power supply voltage into the plurality of internal voltages when the external Vpp power supply voltage is not enabled by the device control register, the plurality of internal voltages being of sufficient magnitude to permit a number of selectively differing voltage applications to cells of the NAND flash memory to enable at least one operation in relation to the data.

US Pat. No. 9,588,883

FLASH MEMORY SYSTEM

Conversant Intellectual P...

1. A method for programming a multiple bit per cell (MBC) flash memory device configured to store up to N pages of data per
physical row, N being an integer greater than one, the method comprising:
issuing a group of program commands for programming multiple pages of data to a subdivision having at least one physical row
of the flash memory device,

the group of program commands being limited to addressing a subset of logical page addresses selected from all possible logical
page addresses corresponding to each of the at least one physical row, where each program command comprises a row address
having at least one bit representing a selected physical row and at least one bit representing a logical page address of the
subset of logical page addresses corresponding to the selected physical row; and

programming less than N pages to each of the at least one physical row of the flash memory device in response to the subset
of logical page addresses indicated in the row addresses in the program commands.

US Pat. No. 9,524,778

DEVICE SELECTION SCHEMES IN MULTI CHIP PACKAGE NAND FLASH MEMORY SYSTEM

Conversant Intellectual P...

1. A memory system comprising:
a memory controller; and
a plurality of memory devices connected to the memory controller via a common bus with a multi-drop connection, each memory
device composing a burst data controller that, when a device identifier of the memory device matches a selected portion of
a received input address, causes the memory device to be selected while a command input is in progress and while an address
input is in progress,

wherein:
the memory controller is configured to perform device selection by the command comprising a command op code portion and the
device identifier portion that together form not more than one byte of the command,

the plurality of memory devices comprises a plurality of NAND flash devices,
each of the NAND flash devices comprises a NAND memory cell array,
the NAND memory cell array is subdivided into blocks, and each block of the blocks is further subdivided into pages, and each
page of the pages comprises a j-byte data storage region and a k-byte spare field.

US Pat. No. 9,384,838

SPLIT BLOCK DECODER FOR A NONVOLATILE MEMORY DEVICE

CONVERSANT INTELLECTUAL P...

1. A method for operating a non-volatile memory device having a memory array, wherein the memory array includes a plurality
of memory blocks organized as groups of memory blocks, the method comprising:
selecting, by row decoding circuitry, a group of the plurality of memory blocks in response to a first row address;
selecting, by the row decoding circuitry, a memory block of the group for receiving row signals in response to a second row
address; and

providing, by first decoder logic of the row decoding circuitry, a super block signal corresponding to each group of the plurality
of memory blocks in response to the first row address.

US Pat. No. 9,214,235

U-SHAPED COMMON-BODY TYPE CELL STRING

Conversant Intellectual P...

1. A flash device comprising:
a semiconductor substrate;
a well impurity region within the semiconductor substrate; and
a U-shape flash cell string including a first vertical portion, a second vertical portion and a horizontal portion connecting
the first vertical portion and the second vertical portion, wherein

the first vertical portion includes a first channel portion, the second vertical portion includes a second channel portion
and the horizontal portion includes a third channel portion,

the first channel portion and the second channel portion include a semiconductor material,
the first channel portion and the second channel portion are in contact with a top surface of the semiconductor substrate
and extend vertically to the surface of the semiconductor substrate, and

the third channel portion is located within the semiconductor substrate and forms an integral part of the semiconductor substrate
and the well impurity region.

US Pat. No. 9,196,319

PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES

Conversant Intellectual P...

1. A system comprising:
a voltage generator circuit to generate a pre-charge voltage signal for pre-charging at least one signal in a memory circuit,
the voltage generator circuit operable to:

receive an input signal indicating an operational mode of the memory circuit;
generate the pre-charge voltage signal with a first magnitude within a first voltage range when the received input signal
indicates that the operational mode of the memory circuit is a power saving mode, the first magnitude being a magnitude that
reduces a voltage difference between the pre-charge voltage and a voltage of the at least one signal.

US Pat. No. 9,116,764

BALANCED PSEUDO-RANDOM BINARY SEQUENCE GENERATOR

Conversant Intellectual P...

1. An electronic circuit for producing a digital output in response to edges of a received clock signal, the circuit comprising:
first generator circuitry for generating an unbalanced, pseudo-random binary output of said first circuitry;
second generator circuitry having an input for the received clock signal, said second circuitry generating a sub-rate clock
version of the received clock; and

logic gate circuitry for effectively multiplying said sub-rate clock with said pseudo-random binary output of the first circuitry
to produce a balanced, pseudo-random binary output.

US Pat. No. 9,779,804

FLASH MEMORY SYSTEM

Conversant Intellectual P...

1. A NAND flash memory device comprising:
at least two NAND flash memory banks being independently operable by having respective control circuitry, row decoding circuitry,
sense amplifier circuitry and page buffer circuitry;

a chip select input configured to receive a chip select signal;
a clock input configured to receive a clock signal;
a common command, address, data input configured to receive, all at different times, command data, address data and page data
while the chip select signal is at an active low logic state, wherein the address data is including bank address data to identify
the first NAND flash memory bank as addressed for performing a page program operation carried out thereon;

a first control input configured to receive a first of two control signals;
a second control input configured to receive a second of the two control signals;
circuitry configured to execute the page program operation on the first NAND flash memory bank corresponding to the command
data;

a first bank status indicator configured to indicate that the first NAND flash memory bank is being utilized during the page
program operation on the first NAND flash memory bank; and

latch circuitry configured to:
latch the command data while only the first of the two control signals is held at an active high logic state for at least
a duration of time that the command data is received at the common input, and

latch the page data in synchronization with both rising and falling edges of the clock signal.

US Pat. No. 9,762,120

CIRCUIT FOR CLAMPING CURRENT IN A CHARGE PUMP

Conversant Intellectual P...

1. A charge pump comprising:
a first capacitor;
a pump up current path comprising a first transistor coupled between a first power supply and a first node, the gate of the
first transistor coupled to a first output of a pump up phase detector, and a second transistor coupled between the first
node and said first capacitor, the gate of the second transistor coupled to a first bias input;

a pump down current path comprising a third transistor coupled between a second power supply and a second node; the gate of
the third transistor coupled to a second output of a pump down phase detector, and a fourth transistor coupled between the
second node and the first capacitor, the gate of the fourth transistor coupled to a second bias input;

a first alternate current path coupled between a first intermediate node and said second power supply configured to conduct
current for a first period of time when said first transistor is switched to the off state; and

a second alternate current path coupled between a second intermediate node and said first power supply configured to conduct
current for a second period of time when said third transistor is switched to the off state,

wherein said first alternate current path further comprises a fifth transistor coupled to the first node and a third node,
a sixth transistor coupled to the third node and the second power supply and, and a first inverter whose input is coupled
to the first output of the pump up phase detector and whose output is coupled to a second capacitor,

wherein said second alternate current path further comprises a seventh transistor coupled to the second node and a fourth
node, an eighth transistor coupled to the fourth node and said first power supply, and a second inverter whose input is coupled
to the second output of the pump down phase detector and whose output is coupled to a third capacitor, and

wherein each of the second capacitor and the third capacitor acts to pump additional charge into the third and fourth nodes
respectively during the switching off of the first and third transistors.

US Pat. No. 9,704,580

INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES

CONVERSANT INTELLECTUAL P...

1. A non-volatile memory comprising:
at least first and second groups of a plurality of non-volatile memory cells, each non-volatile memory cell including a respective
cell transistor that includes a source terminal, a drain terminal, a gate terminal and a body terminal, each of the first
and second groups of non-volatile memory cells commonly sharing first and second cell bodies respectively, the first cell
body being constituted by the body terminals of the cell transistors of the first group of non-volatile memory cells, the
second cell body being constituted by the body terminals of the cell transistors of the second group of non-volatile memory
cells, the first cell body being different and electrically isolated from the second cell body, the body terminals of the
cell transistors of the first group of non-volatile memory cells being configured to receive an erase voltage to erase the
first group of non-volatile memory cells, and the body terminals of the cell transistors of the second group of non-volatile
memory cells being configured to receive the erase voltage to erase the second group of non-volatile memory cells; and

a row circuit decoder configured to provide i) memory array signals to the gate terminals of the cell transistors of one of
the first and second groups of non-volatile memory cells; and ii) the erase voltage to one of the first and second cell bodies
for carrying out associated erasure in response to a row address,

wherein the row decoder includes pass block circuits for receiving global memory array signals and a global erase voltage,
the row decoder further configured to enable a subset of the pass block circuits for passing the global memory array signals
as the memory array signals and passing the global erase voltage as the erase voltage to the respective cell body of the one
of the first and second groups of non-volatile memory cells for erasing the one of the first and second groups of non-volatile
memory cells.

US Pat. No. 9,240,227

DAISY CHAIN CASCADING DEVICES

Conversant Intellectual P...

1. A flash memory system comprising:
a plurality of flash memory devices including at least a first flash memory device and a second flash memory device, the plurality
of flash memory devices being connected in a serial arrangement with each other,

the first flash memory device having
a control input port configured to receive a first input enable signal,
a data input port,
a data input circuit coupled to the data input port, the data input circuit being configured to receive the first input enable
signal from the control input port through a first control signal path,

a data output port,
a data output circuit coupled to the data output port, the data output circuit being coupled to the control input port through
a second control signal path, the second control signal path including

an output control circuit configured to receive the first input enable signal from the control input port and to output a
control signal having an active logic level to the data output circuit when the first input enable signal is at an active
logic level,

a clock input port, and
a control output port,
the first flash memory device configured
to receive
first input information at the data input port in a predetermined sequence including a p-byte target device address, a q-byte
command, and an r-byte address, synchronously with a clock signal received at the clock input port, each of p, q and r being
an integer value equal to or greater than 1, and

the first input enable signal having an active logic level at the control input port from an external source device, the data
input circuit configured to capture the received first input information when the first input enable signal is at an active
logic level to enable the data output circuit in response to the control signal at an active logic level, and to output the
captured first input information through the enabled data output circuit as output information from the data output port and

a second input enable signal from the control output port; and
the second flash memory device being associated with a unique device identification number and having
a data input port,
a data output port
a clock input port, and
a control input port,
the second flash memory device configured
to capture the output information of the first flash memory device as second input information at its data input port while
the second input enable signal is at the predetermined logic level at the control input port, and

to compare the p-byte target device address included in the captured second input information to the unique device identification
number of associated with the second flash memory to determine whether the second flash memory device is a target device.

US Pat. No. 9,123,402

DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR

Conversant Intellectual P...

1. A memory device comprising:
a plurality of storage cells for storing data;
a plurality of selectively activatable charge pumps for providing a boosted voltage for operation of the memory device; and
a controller for selectively activating the plurality of charge pumps,
the memory device being operable in a plurality of modes including an auto-refresh mode and a self-refresh mode, each mode
being characterized by the activation of a different number of the plurality of charge pumps.

US Pat. No. 9,117,527

NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE

Conversant Intellectual P...

1. A flash memory device, comprising:
a memory bank comprising a plurality of planes each having a page buffer for storing write data for programming to a corresponding
plane, the plurality of planes being organized into a plurality of tiles each including two planes coupled to a shared row
decoder for driving wordlines in each of the two planes; and

a page size configurator operable to selectively enable, at the same time, at least a first plane of a first tile and a second
plane of a second tile.

US Pat. No. 9,769,080

METHOD AND APPARATUS FOR REDUCING POOL STARVATION IN A SHARED MEMORY SWITCH

Conversant Intellectual P...

1. A switch comprising:
a plurality of reserved pools of buffers in a shared memory, each reserved pool of buffers associated with one of a plurality
of egress ports and reserved to store data to be forwarded to the egress port;

a shared pool of buffers in the shared memory, the shared pool of buffers configured to store data to be forwarded to any
of the plurality of egress ports;

a multicast pool of buffers in the shared memory reserved to store Multicast packets received from any ingress port to be
forwarded to at least one egress port to members of a Multicast group; and

a pool select logic comprising a first counter and a second counter, the pool select logic configured to select a free buffer
to allocate from the multicast pool of buffers based on counts stored in: i) the first counter configured to count a total
number of free buffers; and ii) the second counter configured to count a number of buffers in the multicast pool of buffers,
and

wherein the first counter is further configured to be preset to a total number of buffers in the shared memory which is less
than a sum of: i) free buffers in the shared pool of buffers; ii) free buffers in the reserved pools of buffers; and iii)
free buffers in the multicast pool of buffers.

US Pat. No. 9,236,127

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Conversant Intellectual P...

1. A non-volatile memory device, comprising:
a substrate;
a plurality of string stacks disposed over the substrate,
each string stack comprising a long axis and a short axis in a plane parallel to the substrate, the long axis extending along
a y-direction and the short axis extending along an x-direction,

each string stack comprising a plurality of strings being stacked in a direction vertical to the substrate and having a first
end and a second end at different locations in the y-direction,

the plurality of string stacks comprising a first and a second set of string stacks,
the first set of string stacks comprising at least two string stacks located at the same location in the y-direction and at
different locations in the x-direction forming a repetitive pattern with a pitch A,

the second set of string stacks being adjacent to the first set of string stacks and comprising at least two string stacks
located at the same location in the y-direction and at different locations in the x-direction forming a repetitive pattern
with a pitch A,

the first set of string stacks and the second set of string stacks being at different locations in the y-direction,
at least some of the string stacks of the first set of string stacks being offset along the x-direction from at least some
of the string stacks of the second set of string stacks by a distance B, the distance B being different from an integer multiple
of the pitch A.

US Pat. No. 9,836,391

SYSTEM AND METHOD OF PAGE BUFFER OPERATION FOR MEMORY DEVICES

Conversant Intellectual P...

1. A method for controlling a plurality of flash memory devices connected with a controller through a common bus, each of
the plurality of flash memory devices having a page buffer and memory cells, the method comprising:
selecting at least one accessible flash memory device of the plurality of flash memory devices by providing a first control
signal to the selected at least one accessible flash memory device, the selected at least one accessible flash memory device
being selected at least partially based on having an empty page buffer;

writing data from a data storage of the controller to the page buffer of the selected at least one accessible flash memory
device by providing a second control signal to the selected at least one accessible flash memory device; and

reading back the data from the page buffer of the selected at least one accessible flash memory device to the data storage
of the controller by providing a third control signal to the selected at least one accessible flash memory device, prior to
programming the data from the page buffer into the memory cells of the selected at least one accessible flash memory device.

US Pat. No. 9,524,783

FLASH MEMORY SYSTEM

Conversant Intellectual P...

1. A system comprising:
at least two flash memory banks being independently operable by having respective row decoding circuitry and sense amplifier
circuitry, a first of the flash memory banks forming a part of a flash memory device of the system, and the flash memory device
including:

a clock input configured to receive a clock signal;
a common command, address, data input configured to receive input data, address data and command data, all at different times,
and the address data identifying the first flash memory bank as addressed for having an operation carried out thereon;

a first control input configured to receive a first of two control signals;
a second control input configured to receive a second of the two control signals;
circuitry configured to execute the operation on the first flash memory bank corresponding to the command data; and
latch circuitry configured to:
latch the command data while the first of the two control signals is held at an active logic level for at least a duration
of time that the command data is received at the common input, and

latch the input data in synchronization with both rising and falling edges of the clock signal; and
a memory controller communicatively coupled to the flash memory device, and the memory controller being configured to source
the input data, the address data and the command data to the flash memory device.

US Pat. No. 9,576,675

NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES

Conversant Intellectual P...

1. A method for generating internal voltages in a non-volatile semiconductor memory device, the method comprising:
receiving an external Vcc power supply voltage;
receiving an external Vccq power supply voltage;
receiving an external Vpp power supply voltage greater in magnitude than the external Vcc power supply voltage;
setting a configuration register to enable the external Vpp power supply;
powering I/O logic of the non-volatile semiconductor memory device with the external Vccq power supply voltage;
converting the external Vpp power supply voltage to a plurality of internal program voltages;
converting the external Vpp power supply voltage to an internal pass voltage; and
applying the internal program voltages to selected memory cells and the internal pass voltage to unselected memory cells in
a program operation.

US Pat. No. 9,348,786

SEMICONDUCTOR MEMORY DEVICE WITH PLURAL MEMORY DIE AND CONTROLLER DIE

CONVERSANT INTELLECTUAL P...

1. A system comprising:
a memory controller configured to supply a global clock signal and an external read command via an external control bus; and
a memory device separate from the memory controller and comprising a plurality of memory dies and a controller die, the memory
device being communicatively coupled to the external control bus to receive the global clock signal and the external read
command, and the controller die being configured to provide an internal read command to a selected one of the memory dies
in response to the external read command and provide an internal clock signal synchronized with the global clock signal;

wherein the selected memory die is configured to provide read data to the controller die in response to the internal read
command, wherein a first latency from when the internal read command is sent by the controller die and the read data is received
by the controller die differs for at least two of the memory dies, the first latency differing depending on which of the at
least two memory dies is selected as the selected memory die;

wherein the controller die is further configured to output the read data on an external data bus, wherein a second latency
from when the controller die receives the external read command to when the controller die outputs the read data on the external
data bus is uniform for the at least two memory dies when selected as the selected memory die;

wherein the memory controller is communicatively coupled to the controller die via the external data bus.

US Pat. No. 9,966,133

FLASH MEMORY DEVICE

Conversant Intellectual P...

1. A flash memory device comprising:a flash memory array;
a first control port configured to receive a chip select signal from a memory controller;
a first clock port configured to receive a first clock signal from the memory controller;
a second clock port configured to transmit a second clock signal, referenced to the first clock signal, to the memory controller;
at least one common data port configured to receive command data and address data in synchronization with the first clock signal while the chip select signal is at an active low logic state;
core circuitry configured to retrieve a read data from the flash memory array in response to the command data; and
data output circuitry configured to transmit the read data to the memory controller in synchronization with the second clock signal.

US Pat. No. 9,411,680

COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION

CONVERSANT INTELLECTUAL P...

1. A method for writing data in a composite memory device, the composite memory device including an interface device with
an external interface for communicating with an external controller, an ECC engine, and a plurality of internal interfaces
for communicating with a plurality of non-volatile memory devices, the method comprising:
receiving a write command via the external interface;
receiving write input data via the external interface;
generating write parity data in the ECC engine using the write input data;
transferring the write input data together with the write parity data to any selected one of the plurality of non-volatile
memory devices; and

programming the write input data together with the write parity data in the selected one of the plurality of non-volatile
memory devices.

US Pat. No. 9,343,473

STRUCTURE AND METHOD FOR MANUFACTURE OF MEMORY DEVICE WITH THIN SILICON BODY

Conversant Intellectual P...

1. A method for forming a first memory stack in fabrication of a nonvolatile memory device, the method comprising:
depositing a first dielectric layer above an upper surface of a semiconductor substrate;
depositing a second dielectric layer of a material different from the first dielectric layer above the first dielectric layer;
carrying out anisotropic etching of the second dielectric layer and the first dielectric layer sequentially, so as to create
a first dielectric pattern and a second dielectric pattern above the first dielectric pattern;

carrying out isotropic etching of the first and second dielectric patterns, and the isotropic etching for the first dielectric
pattern is at a higher etch rate than the isotropic etching for the second dielectric layer, and the isotropic etching removing
at least a portion of the first dielectric pattern and forming at least one undercut space under the second dielectric pattern;

depositing a first film of a conducting or a semiconducting material at least on a sidewall of the second dielectric pattern
and in the at least one undercut space;

carrying out dry etching in a manner so as to remove the first film from the sidewall of the second dielectric pattern and
to leave the first film in the at least one undercut space;

depositing a third dielectric layer over at least a sidewall of the first film; and
depositing a second film of a conducting or a semiconducting material over the third dielectric layer, so that a topmost portion
of the second film is at a location higher than a topmost portion of the second dielectric pattern and a bottom-most portion
of the second film is at a lower location that the first film.

US Pat. No. 9,070,461

NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES

Conversant Intellectual P...

1. A NAND Flash memory comprising:
a first memory block with a first NAND cell string;
a second memory block with a second NAND cell string;
a first well sector including the first memory block configured to selectively receive an erase voltage during an erase operation;
a second well sector including the second memory block configured to be inhibited from receiving the erase voltage during
the erase operation;

a bitline (BLk) electrically connected to the first NAND cell string and the second NAND cell string, the bitline comprising:
a first bitline segment electrically connected to the first NAND cell string of the first well sector, and
a second bitline segment electrically connected to the second NAND cell string of the second well sector; and
a page buffer electrically connected to the bitline.

US Pat. No. 9,935,110

MEMORY DEVICE WITH MANUFACTURABLE CYLINDRICAL STORAGE NODE

Conversant Intellectual P...

1. A method for manufacturing a semiconductor device, comprising:forming a conductive pad;
forming a first insulating layer directly on the conductive pad;
forming a second insulating layer over the first insulating layer;
forming a first hole within the first and the second insulating layer such that an upper surface portion of the conductive pad is exposed;
forming a conformal dielectric layer within the first hole and directly on an exposed portion of the conductive pad, the conformal dielectric layer partially filling the first hole;
forming a conformal first conductive layer within the first hole and over the conformal dielectric layer, the first conductive layer partially filling the first hole;
etching the first conductive layer and the conformal dielectric layer using an anisotropic etch process such that a sidewall portion of the first conductive layer along the height of the first hole and a sidewall portion of the conformal dielectric layer along the height of the first hole remain unremoved and at least a bottom portion of the first conductive layer and a bottom portion of the conformal dielectric layer within the first hole are removed to expose a portion of the conductive pad;
forming a second conductive layer within the first hole and on the first conductive layer such that the second conductive layer is in direct contact with the first conductive layer and the conductive pad;
forming a third insulating layer over the second insulating layer;
forming a second hole in the third insulating layer such that at least one of the first and the second conductive layers is exposed; and
forming a third conductive layer within the second hole, the third conductive layer being in direct contact with the exposed at least one of the first and the second conductive layers.

US Pat. No. 9,767,881

DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION

Conversant Intellectual P...

1. A dynamic random access memory (DRAM) device comprising:
a clock input to receive a clock signal;
a plurality of command and address inputs to receive command and address signals in synchronization with the clock signal;
a plurality of memory banks each having a plurality of wordlines, each of the plurality of wordlines being connected to a
plurality of data store cells that are refreshable in a self-refresh mode;

a partial array self-refresh (PASR) configuration register configured to store bits, each of the bits corresponding to a respective
one of the plurality of memory hanks to indicate whether or not the respective memory bank is to be refreshed in the self-refresh
mode, the number of bits equivalent to the number of memory banks; and

a command decoder to decode a configuration register set command in synchronization with the clock signal in order to configure
the configuration register,

wherein, in the self-refresh mode, a self-refresh operation is performed only for the one or more memory banks to be refreshed.

US Pat. No. 9,360,878

CIRCUIT FOR CLAMPING CURRENT IN A CHARGE PUMP

Conversant Intellectual P...

1. A charge pump comprising:
a plurality of transistors;
at least one capacitor;
a first path configured to communicate current with the at least one capacitor, wherein a first transistor of the plurality
of transistors is located on the first path and generates a first temporary parasitic spike in current when the first transistor
switches off in response to a control signal changing from a first value to a second value; and

a current clamping circuit configured to:
open an additional path for current from the first transistor when the control signal changes from the first value to the
second value such that the first temporary parasitic spike is only partially communicated through the first path; and

close the additional path after the additional path has been open for a period of time and the first temporary parasitic spike
has dissipated.

US Pat. No. 9,343,152

CELL ARRAY WITH A MANUFACTURABLE SELECT GATE FOR A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

CONVERSANT INTELLECTUAL P...

11. A NAND Flash memory cell array with strings, each comprising a plurality of series-connected cell transistors having gates
connected to corresponding word lines, first and second string select transistors having first and second self-aligned gates
connected, respectively, to first and second string select lines, a source line contact connected to a source line, and a
ground select transistor having a gate connected to a ground select line,
wherein each string has a bit line end-to-source line end orientation which extends from a corresponding bit line and source
line contact to extend past the corresponding source line contact to form an electrically floating string section, wherein
the first string select transistor is connected between the corresponding bit line and the plurality of series-connected cell
transistors, and wherein the second string select transistor is positioned along the electrically floating string section;
and

wherein first and second strings having opposite bit line end-to-source line end orientations are placed adjacent to on another
such that the first string select transistor of the first string is adjacent to the second string select transistor of the
second string such that the first self-aligned gate of the first string select transistor and the second self-aligned gate
of the second string select transistor share a common self-aligned gate electrode that is completely confined laterally in
a space between the first and second strings.

US Pat. No. 9,318,499

LITHOGRAPHY-FRIENDLY LOCAL READ CIRCUIT FOR NAND FLASH MEMORY DEVICES AND MANUFACTURING METHOD THEREOF

Conversant Intellectual P...

1. A vertical NAND flash device comprising:
a semiconductor substrate;
NAND Flash cells formed in vertical pillars above the semiconductor substrate, the vertical pillars having bottom portions
in contact with the semiconductor substrate and top portions;

a bit line connected to the top portions of the vertical pillars; and
a sensing circuit comprising at least three gate electrodes adjacent to each other, the gate electrodes being formed on channel
regions, the channel regions being a part of the semiconductor substrate,

wherein the gate electrodes extend in evenly spaced line patterns running perpendicular to the bit line.

US Pat. No. 10,004,060

SCHEDULING SYSTEMS AND METHODS FOR WIRELESS NETWORKS

Conversant Intellectual P...

1. A method comprising, by a base station in a wireless network:receiving from a user device a request to reconfigure already-active uplink semi-persistent scheduling (SPS);
wherein the already-active uplink SPS grants the user device a resource block allocation (RBA) and a modulation and coding scheme (MCS) for periodic uplink transmissions;
wherein the already-active uplink SPS comprises a time-interval parameter, the time-interval parameter specifying a time interval between the periodic uplink transmissions;
wherein the request comprises information related to a proposed adjustment of the time-interval parameter and the request is specified in at least one of the following portions of a media access control (MAC) protocol data unit (PDU);
a reserved bit of a header of the MAC PDU;
a control-element field of a payload of the MAC PDU; and
a padding field of the payload; and
reconfiguring the already-active uplink SPS, the reconfiguring comprising modifying the time-interval parameter based, at least in part, on the information.

US Pat. No. 9,852,788

MULTIPAGE PROGRAM SCHEME FOR FLASH MEMORY

CONVERSANT INTELLECTUAL P...

1. A NAND flash memory device comprising:
a plurality of I/O ports configured to receive a single multi-page program request from a memory controller, the single multi-page
program request comprising at least two iterative command and data input sequences, each command and data input sequence comprising
command data, address data and write data;

a ready/busy port configured to output a ready/busy signal indicating a busy status of the NAND flash memory device, the ready/busy
signal indicates a busy status in between the at least two iterative command and data input sequences;

a flash memory array comprising NAND type memory cells connected to wordlines and coupled to bitlines, each wordline corresponding
to a single physical page comprising M logical pages, M being an integer greater than 1;

bitline access circuitry configured to store M logical pages of data before execution of a single multi-page programming cycle,
and bias the bitlines to one of enable and inhibit programming for each of 2M?1 programming iterations based on a combination of bits corresponding to each bitline from the M logical pages of data during
execution of the single multi-page programming cycle, each logical page of data being provided from the write data; and

row circuits configured to drive a selected wordline with different time periods for each of the 2M?1 programming iterations while the bitlines are biased to enable or inhibit programming based on a combination of logic states
of the M logical pages of data, and program the M logical pages of data to a single physical page of memory cells in the single
multi-page programming cycle.

US Pat. No. 9,202,578

VERTICAL GATE STACKED NAND AND ROW DECODER FOR ERASE OPERATION

Conversant Intellectual P...

1. A three-dimensional non-volatile memory device, comprising:
a memory array comprising a plurality of vertical gate NAND memory cell strings formed in a plurality of different layers
over a substrate and sharing a common set of word lines, comprising a first plurality of NAND memory cell strings forming
a first erase block and second plurality of NAND memory cell strings forming a second erase block;

a first source line structure and one or more first string select structures connected respectively on opposite ends of the
first plurality of NAND memory cell strings, where the first source line structure controls erasure of the first erase block;

a second source line structure and one or more second string select structures connected respectively on opposite ends of
the second plurality of NAND memory cell strings, where the second source line structure controls erasure of the second erase
block; and

a source line selection circuit for selecting between the first source line structure and the second source line structure
when erasing the first erase block or second erase block.

US Pat. No. 9,583,204

NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES

Conversant Intellectual P...

1. A NAND flash memory comprising:
at least first and second well sectors, each of the first and second well sectors including at least one memory block;
a first bitline segment connected to the at least one memory block of the first well sector;
a second bitline segment connected to the at least one memory block of the second well sector; and
isolation circuitry connected between the first bitline segment and second bitline segment, the isolation circuitry configured
to:

i)be turned off during at least one memory operation of a plurality of different possible memory operations performable within
the NAND flash memory; and

ii)be turned on at certain times other than during the at least one memory operation.

US Pat. No. 9,836,227

METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE

Conversant Intellectual P...

1. A flash memory system comprising:
at least one flash memory device, each flash memory device comprising:
a plurality of memory banks configured to perform operations concurrently to each other, each memory bank comprising a separate
row decoder and a separate page buffer;

a chip select input configured to activate the plurality of memory banks for the respective flash memory device;
a status register for each memory bank, each status register configured to indicate whether the respective memory bank is
busy; and

a plurality of interfaces, each interface configured to receive data streams from a memory controller, each data stream comprising
the command data, address data, and write data receivable at different times; and

the memory controller communicatively coupled to the at least one flash memory device and configured to select any one of
the plurality of interfaces of the at least one flash memory device in order to provide data streams to the selected interface.

US Pat. No. 9,740,407

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

CONVERSANT INTELLECTUAL P...

1. A system comprising:
a memory controller configured to provide a chip enable signal, a first input signal, a second input signal, common data signals,
and setting information for configurable buffers; and

at least one non-volatile memory device communicatively coupled to the memory controller, the at least one non-volatile memory
device comprising:

at least two non-volatile memory banks;
a chip enable input port configured to receive the chip enable signal for enabling the at least one non-volatile memory device;
a first input port and a second input port configured to receive the first input signal and the second input signal, respectively,
wherein the second input signal is complementary to the first input signal;

a reference voltage input port configured to receive an external reference voltage;
one or more common data ports configured to receive the common data signals carrying command data and at least one of address
data and write data, the write data to be latched in synchronization with both rising and falling edges of at least the first
input signal and to be programmed into one of the at least two non-volatile memory banks addressable by the address data;

a first configurable input buffer configured to be able to switch from a single ended signaling configuration to a differential
signaling configuration, the differential signaling configuration configured to utilize the first input signal and the second
input signal as differential signals, and the single ended signaling configuration configured to utilize one of the first
input signal and the second input signal as a single ended signal;

a second configurable input buffer configured to be able to utilize the external reference voltage for determining a logic
level of the common data signals; and

a configurable output buffer configured to set an output drive strength to provide data from one of the at least two non-volatile
memory banks in response to a read command from the memory controller.

US Pat. No. 9,595,534

U-SHAPED COMMON-BODY TYPE CELL STRING

CONVERSANT INTELLECTUAL P...

1. A NAND flash memory device comprising:
a substrate formed of a semiconducting material, the substrate having an intermediate substrate region free from any source/drain
region;

at least first and second vertical pillars each including a plurality of memory cells, and the second vertical pillar being
adjacent to the first vertical pillar, and the first vertical pillar including a first body portion, a first bottom portion
and a first top portion, and the second vertical pillar including a second body portion, a second bottom portion and a second
top portion, and the first and second body portions being in contact with the substrate and comprised of first and second
semiconductor films respectively, and the first and second bottom portions also being in contact with the substrate, and the
intermediate substrate region of the substrate being located between the first and second bottom portions;

a first gate electrode that is not a part of a memory cell, the first gate electrode surrounding the first and second bottom
portions such that the first and second body portions each penetrate the first gate electrode, and the first gate electrode
being located on at least the intermediate substrate region with only a gate dielectric intervening between the first gate
electrode and the intermediate substrate region; and

first and second source/drain regions, the first source/drain region being located at the first top portion of the first vertical
pillar, the second source/drain region being located at the second top portion of the second vertical pillar.

US Pat. No. 10,074,655

MEMORY DEVICE WITH MANUFACTURABLE CYLINDRICAL STORAGE NODE

Conversant Intellectual P...

1. A method for fabricating a DRAM device, the method comprising:forming a transistor having a source/drain region in a semiconductor substrate;
forming a vertical conductive structure directly on the source/drain region;
forming a first layered structure on the vertical conductive structure, the first layered structure comprising at least a first dielectric layer;
forming a first hole in the first layered structure such that an upper surface portion of the vertical conductive structure is exposed;
forming a first capacitor dielectric layer within the first hole, the first capacitor dielectric layer partially filling the first hole;
forming a first conductive layer within the first hole and over the first capacitor dielectric layer, the first conductive layer partially filling the first hole;
etching the first conductive layer and the first capacitor dielectric layer using an anisotropic etch process such that a sidewall portion of the first conductive layer along the height of the first hole and a sidewall portion of the first capacitor dielectric layer along the height of the first hole remain and a bottom portion of the first conductive layer and a bottom portion of the first capacitor dielectric layer within the first hole are at least partially removed such that the upper surface portion of the vertical conductive structure is partially exposed;
forming a second conductive layer within the first hole and on the first conductive layer such that the second conductive layer is in direct contact with the first conductive layer and the vertical conductive structure, and such that the second conductive layer has an upper surface;
forming an upper capacitor structure on the second conductive layer, such that an electrode is formed in direct contact with the upper surface of the second conductive layer.

US Pat. No. 10,091,044

SYSTEM AND METHOD FOR FREQUENCY SYNCHRONIZATION OF DOPPLER-SHIFTED SUBCARRIERS

CONVERSANT INTELLECTUAL P...

1. A method comprising:receiving an Orthogonal Frequency Division Multiplexing (OFDM) signal comprising a plurality of Doppler-shifted OFDM subcarriers of a subband;
determining an average frequency shift factor corresponding to the plurality of Doppler-shifted OFDM subcarriers;
wherein determining the average frequency shift factor comprises:
calculating a frequency shift factor for each Doppler-shifted OFDM subcarrier of the plurality of Doppler-shifted OFDM subcarriers, thereby yielding a plurality of subcarrier-specific frequency shift factor values; and
calculating an average of the plurality of subcarrier-specific frequency shift factor values as the average frequency shift factor corresponding to the plurality of Doppler-shifted OFDM subcarriers; and
calculating, for each Doppler-shifted OFDM subcarrier, a frequency offset by multiplying the average frequency shift factor by a frequency index of the each subcarrier, the frequency offset for at least two Doppler-shifted OFDM subcarriers of the subband being different from each other.

US Pat. No. 9,660,616

POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Conversant Intellectual P...

1. A system comprising:
an integrated circuit;
a plurality of power islands of the integrated circuit having associated power consumptions; and
a first power manager and a second power manager, the first power manager being a power management processor for executing
power management software to individually control each of the power consumptions, and the power management processor being
configured to:

i) monitor one or more power consumption signals that indicate one or more of the power consumptions;
ii) determine power trade-offs between the power islands to support needs and operation of the integrated circuit; and
iii) after the power trade-offs are determined, send a power consumption change request to the second power manager in order
to change power consumption in at least one of the power islands.

US Pat. No. 9,570,123

NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE

CONVERSANT INTELLECTUAL P...

1. A memory system comprising:
a memory bank including
a first page buffer coupled to bitlines, the first page buffer having a sequential enabler for shifting a first logic level
to select a first group of the bitlines for providing read data in parallel in response to a read operation and for receiving
write data in parallel in response to a write operation,

and a parallel/serial data converter for converting the read data into serial bitstream read data and for converting serial
bitstream write data into the write data; and,

a serial data path for coupling the serial bitstream read data and the serial bitstream write data between the memory bank
and an input/output interface
wherein the memory bank includes:
a first bank half coupled to first n parallel datalines for receiving the read data from the first page buffer, where n is
an integer value greater than 0,

a second bank half coupled to second n parallel datalines, and
the parallel/serial data converter is configured to selectively convert one of the first and the second n parallel datalines
into the serial bitstream read data, and for selectively converting the serial bitstream write data into parallel data for
one of the first and the second n parallel datalines
and wherein the parallel/serial data converter includes:
a first parallel/serial data converter for sequentially coupling each of the first n parallel datalines to a first terminal,
a second parallel/serial data converter for sequentially coupling each of the second n parallel datalines to a second terminal,
and

a data path selector for selectively coupling one of the first terminal and the second terminal to a bidirectional serial
data line.

US Pat. No. 10,007,439

NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE

Conversant Intellectual P...

1. A non-volatile memory system comprising:at least one non-volatile memory device; and
a memory controller communicatively coupled to the least one non-volatile memory device, the memory controller configured to provide to the at least one non-volatile memory device a chip select signal, a clock signal, and at least one common data signal carrying command data, address data and write data,
the at least one non-volatile memory device comprising:
a plurality of non-volatile memory banks,
a chip select input configured to receive the chip select signal for enabling the non-volatile memory banks,
a clock input configured to receive the clock signal for synchronizing the at least one common data signal, and
at least one common data input configured to receive the at least one common data signal for providing the command data, the address data and the write data to the non-volatile memory banks,
wherein each non-volatile memory bank comprises:
a first non-volatile memory sector having non-volatile memory cells coupled to first bitlines and first wordlines, the first bitlines being arranged as m segments where m is an integer value greater than 0,
a second non-volatile memory sector having non-volatile memory cells coupled to second bitlines and second wordlines, the second bitlines being arranged as m segments, and
a page buffer disposed between the first non-volatile memory sector and the second non-volatile memory sector for selectively coupling one of the first bitlines and the second bitlines of each of the m segments to a predetermined number of data lines, the predetermined number of data lines containing at least a portion of the write data, the page buffer including
a first self-decoding page buffer stage for sensing data from a first bitline, and for providing sensed data corresponding to the first bitline on a corresponding data line in response to an active column select bit latched in a clock signal state, the first self-decoding page buffer stage including an output terminal for providing the active column select bit; and
a second self-decoding page buffer stage having an input terminal for receiving the active column select bit from the output terminal of the first self-decoding page buffer stage, for sensing data from a second bitline, and providing sensed data corresponding to the second bitline on the corresponding data line in response to the active column select bit latched in a subsequent clock signal state.

US Pat. No. 9,685,536

VERTICAL TRANSISTOR HAVING A VERTICAL GATE STRUCTURE HAVING A TOP OR UPPER SURFACE DEFINING A FACET FORMED BETWEEN A VERTICAL SOURCE AND A VERTICAL DRAIN

Conversant Intellectual P...

1. A vertical transistor structure extending in a direction substantially normal to a semiconductive region of a substrate,
comprising:
a vertical transistor gate region oriented in a vertical plane from the substrate surface, including at least two overlying
layers of epitaxially grown silicon, each epitaxial layer comprising a single silicon crystal having a top or upper surface
defining a facet;

a vertical transistor source including a diffusion region adjacent to said transistor gate region within the semiconductive
region; and

a vertical transistor drain including a diffusion region adjacent to said transistor gate region within the semiconductive
region.

US Pat. No. 9,780,073

USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING

CONVERSANT INTELLECTUAL P...

1. An integrated circuit apparatus comprising:
a semiconductor substrate;
an active circuit and interconnect layer provided on said semiconductor substrate;
a plurality of vias extending through said semiconductor substrate from said active circuit and interconnect layer to a surface
of said semiconductor substrate opposite said active circuit and interconnect layer;

a plurality of bottom bond pads provided on said surface, said bond pads axially aligned with and electrically connected to
respective ones of said vias; and

a plurality of top bond pads on said active circuit and interconnect layer, each top bond pad being axially aligned with its
respective one of said vias, a first top bond pad of said top bond pads being electrically connected to its respective first
via, and a second top bond pad of said top bond pads being:

electrically isolated relative to its respective second via; and
electrically coupled to an offset via that is offset from the respective second via.

US Pat. No. 9,893,084

U-SHAPED COMMON-BODY TYPE CELL STRING

Conversant Intellectual P...

1. A method of forming a semiconductor device comprising at least three U-shaped flash cell strings in a memory cell region
and a peripheral transistor in a periphery of the semiconductor device, each U-shaped flash cell string comprising a bottom
pass transistor, the method comprising for each of the at least three U-shaped flash cell strings:
forming a bottom pass transistor of a respective U-shaped flash cell string in the memory cell region, the bottom pass transistor
for the respective U-shaped flash cell string extending in a word line direction that is substantially perpendicular to a
bit line direction; and

forming a first vertical portion and a second vertical portion of the respective U-shaped flash cell string, the bottom pass
transistor of the respective U-shaped flash cell string being comprised in a horizontal portion of the respective U-shaped
flash cell string joining the first vertical portion and the second vertical portion,

wherein the at least three U-shaped flash cell strings are formed concurrently,
wherein the at least three U-shaped flash cell strings are formed adjacent to each other so as to be aligned in the bit line
direction, and

wherein the bottom pass transistors of the at least three U-shaped flash cell strings are formed concurrently with the peripheral
transistor, such that a gate electrode of the bottom pass transistor for each of the at least three U-shaped flash cell strings
is isolated from gate electrodes of the other bottom pass transistors.

US Pat. No. 9,899,096

NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES

Conversant Intellectual P...

1. A NAND Flash memory comprising:
an internal voltage generator configured to provide an erase voltage; and
a plurality of memory planes coupled to the internal voltage generator, each memory plane comprising:
a plurality of memory blocks, each memory block having a plurality of NAND cell strings and a plurality of wordlines, each
wordline coupled to corresponding gates of the NAND cell strings;

a plurality of well sectors, each well sector having one or more memory blocks, the erase voltage being applied to a selected
well sector during a block erase operation;

a plurality of bitlines, each bitline coupled to a corresponding NAND cell string at each memory block; and
a page buffer coupled to the plurality of memory blocks via the plurality of bitlines.

US Pat. No. 9,893,076

ACCESS TRANSISTOR OF A NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING SAME

CONVERSANT INTELLECTUAL P...

1. A nonvolatile memory device, comprising:
a nonvolatile memory array comprising a plurality of memory cell pillars extending from a substrate with an access transistor
located at the bottom of each memory cell pillar, the access transistor comprising:

a drain in said memory cell pillar,
a vertical channel body portion of said memory cell pillar connected between the drain and the substrate,
an elevated source region protruding from a top surface of the substrate and being adjacent to the vertical channel body portion,
a horizontal channel body portion formed in the substrate between the vertical channel body portion and the elevated source
region, and

a lower select line gate electrode formed around the bottom of said memory cell pillar to be insulated from and at least partially
positioned between the vertical channel body and the elevated source region for said memory cell pillar, the elevated source
region being confined within a region shifted laterally from the vertical channel body portion along the top surface of the
substrate, such that the lower select line gate electrode is intervening between the vertical channel body portion and the
elevated source region.

US Pat. No. 10,140,028

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

Conversant Intellectual P...

1. A configurable non-volatile memory device comprising:plurality of non-volatile memory blocks;
a chip enable port configured to receive a chip enable signal for enabling the configurable non-volatile memory device;
a first clock input port configured to receive a first clock input signal;
a second clock input port configured to receive a second clock input signal, the second clock input signal being complementary to the first clock input signal;
a clock output port configured to transfer a clock output signal, wherein the clock output signal is referenced to the first clock input signal;
one or more common data ports configured to transfer common data signals carrying at least one of command data, address data, input data and output data, the input data to be programmed into one of the plurality of non-volatile memory blocks accessible based on the command data and the address data, and the output data to be retrievable from the one of the plurality of non-volatile memory blocks;
a configurable clock input buffer configurable to one of a single ended signaling configuration and a differential signaling configuration, the differential signaling configuration for utilizing the first clock input signal and the second clock input signal as differential signals, and the single ended signaling configuration for utilizing one of the first clock input signal and the second clock input signal as a single ended signal; and
one or more configurable output buffers configurable to one of a plurality of output buffer drive strengths to transfer the output data retrieved from the one of the plurality of non-volatile memory blocks, the output data synchronized with the clock output signal in a double data rate configuration.

US Pat. No. 9,996,274

FLASH MEMORY SYSTEM

Conversant Intellectual P...

1. A multiple bit per cell (MBC) flash memory system comprising:an MBC flash memory device comprising:
a plurality of MBC flash memory banks,
a plurality of erasable blocks in each MBC flash memory bank, and
a plurality of physical pages in each erasable block, each physical page configured to store a maximum of N logical pages, N being an integer greater than two, and each of the erasable blocks configured to operate in a plurality of storage modes, the plurality of modes comprising:
a full MBC storage mode for programming all of the N logical pages for each physical page;
a partial MBC storage mode for programming a subset of the N logical pages comprising at least two and less than the N logical pages for each physical page; and
a single bit per cell (SBC) storage mode for programming a single logical page for each physical page; and
a memory controller communicatively coupled to the MBC flash memory device, the memory controller configured to: determine one of the plurality of storage modes for each erasable block of the at least one MBC flash memory device, and issue a page program command packet set comprising at least one page program command packet, the page program command packet set limited to addressing a subset of logical page addresses selected from all possible logical page addresses corresponding to each physical page of the MBC flash memory device, each page program command packet comprising a row address having at least one bit representing a selected physical page and at least one bit representing a logical page address of the subset of logical page addresses corresponding to the selected physical page when the partial MBC storage mode is determined.

US Pat. No. 10,122,369

WIDE FREQUENCY RANGE DELAY LOCKED LOOP

Conversant Intellectual P...

1. A delay locked loop comprising:a digital delay circuit comprising a plurality of identical first delay elements, the digital delay circuit configured to enable the plurality of identical first delay elements to provide coarse phase adjustment in the delay locked loop, and provide a coarse delayed clock signal;
an analog delay circuit comprising a plurality of identical second delay elements, each second delay element comprising parallel loads configurable by a control signal to change an effective resistance of the analog delay circuit, the analog delay circuit configured to receive the coarse delayed clock signal, provide fine phase adjustment in the delay locked loop in response to the control signal using the plurality of identical second delay elements, and produce a fine delayed clock signal;
a phase detector configured to detect a phase difference between an external clock signal and the fine delayed clock signal; and
a lock detector communicatively coupled to the phase detector and the analog delay circuit, the lock detector configured to hold the digital delay circuit at a fixed delay, and provide the control signal to the analog delay circuit.

US Pat. No. 9,806,925

FREQUENCY DIVISION MULTIPLEXING SYSTEM WITH SELECTABLE RATE

Conversant Intellectual P...

1. A transmitter for signal transmission using orthogonal frequency division multiplexing (OFDM) employing a set of orthogonal
sub-carriers which are orthogonal over a time T, the transmitter comprising:
an inverse fast Fourier transform (IFFT) block converting a group of input bits to an OFDM signal expressed by superpositions
of said set of sub-carriers; and

a prefix and window block selectively performing a cyclic prefixing and windowing on said OFDM signal at least to form a first
OFDM symbol and a second OFDM symbol for transmission, wherein the duration of said first OFDM symbol equals a symbol of duration
T plus a guard time TG and wherein the duration of said second OFDM symbol equals a symbol of duration KT plus a guard time KTG, where K is a positive integer greater than 1, wherein said first OFDM symbol is transmitted after or before said second
OFDM symbol.

US Pat. No. 9,971,518

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

Conversant Intellectual P...

1. A method for controlling a configurable flash memory device, the method comprising:providing to the configurable flash memory device a chip enable signal to enable the configurable flash memory device;
providing to the configurable flash memory device a reference voltage;
providing to the configurable flash memory device a first input signal and a second input signal, wherein the second input signal is complementary to the first input signal;
providing to the configurable flash memory device common data signals, wherein the common data signals comprise command data, address data and write data for an operation in the configurable flash memory device;
configuring the configurable flash memory device to enable use of the reference voltage for determining logic levels of the common data signals; and
configuring the configurable flash memory device to enable a differential signaling configuration, the differential signaling configuration configured to utilize the first input signal and the second input signal as differential signals.

US Pat. No. 9,977,731

BRIDGING DEVICE HAVING A CONFIGURABLE VIRTUAL PAGE SIZE

Conversant Intellectual P...

1. A composite memory device configured in a multi-chip-package (MCP), the composite memory device comprising:a plurality of discrete NAND flash memory dies, each discrete NAND flash memory die comprising at least two memory planes, a respective page buffer for each memory plane, and a NAND flash memory interface for the NAND flash memory die; and
a bridge device coupled to the plurality of discrete NAND flash memory dies, the bridge device comprising:
a bridge chip I/O interface for communicating with a memory controller and receiving a command in a first format and data in the first format;
a command format converter for converting the command from the first format to a second format, the second format being a format for the NAND flash memory dies;
a data format converter configured to convert the data from the first format to the second format;
a plurality of bridge chip memory device interfaces, each bridge chip memory device interface coupled to the NAND flash memory interface of the corresponding one of plurality of discrete NAND flash memory dies and configured to receive the command in the second format and the data in the second format;
a plurality of virtual page buffers, each virtual page buffer corresponding to one memory plane of the plurality of discrete NAND flash memory dies and having a configurable page buffer size that is equal or less than the maximum size of the respective page buffer of the corresponding memory plane; and
a virtual page size configurator configured to latch virtual page size configuration codes from the bridge chip I/O interface at different time periods, each of the page size configuration codes received at one of the different time periods corresponding to a different discrete NAND flash memory die.

US Pat. No. 10,368,307

SYSTEM AND METHOD FOR CONTROLLING A WIRELESS NETWORK

Conversant Intellectual P...

11. An access point (AP) in a wireless, the wireless network comprising the AP and a plurality of wireless stations associated with the AP, the AP comprising:a transmitting/receiving unit; and
at least one processing unit communicatively coupled to the transmitting/receiving unit, the at least one processing unit configured to:
define one or more criteria for categorizing the plurality of wireless stations in the wireless network into a plurality of categories, the plurality of categories comprising at least a first category and a second category, the one or more criteria comprising at least a link-quality-parameter;
determine each of the plurality of wireless stations as belonging to one of the plurality of the categories, wherein more than one of the plurality of wireless stations are determined to belong to the first category and at least one of the plurality of wireless stations is determined to belong to the second category;
notify the wireless stations of one or more first scheduled time periods and one or more second scheduled time periods;
during the one or more first scheduled time periods, transmit first user data to a first wireless station in the first category, and transmit a first collision avoidance control message related to the first user data using a first signaling transmission power; and
during the one or more second scheduled time periods, transmit second user data to a first wireless station in the second category, and transmit a second collision avoidance control message related to the second user data using a second signaling transmission power, the second signaling transmission power being different from the first signaling transmission power.

US Pat. No. 10,243,542

POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Conversant Intellectual P...

1. A method of managing power on an integrated circuit including a plurality of power islands, the method comprising:determining a target power level for one power island of the plurality of power islands based on needs and operation of the integrated circuit where power consumption of each power island within the plurality of power islands is independently controlled within each of the power islands, said each power island operating at a frequency among a set of predetermined frequencies associated with said each power island;
determining an action among a plurality of actions to change a power consumption level of the one power island of the plurality of power islands to the target power level; and
performing the action to change the power consumption level of the one power island of the plurality of power islands to the target power level, wherein the plurality of actions comprises powering-up/off one power island of the plurality of power islands, selecting an operating frequency from the set of predetermined frequencies for the one power island of the plurality of power islands, and selecting a source voltage vdd for one power island of the plurality of power islands,
wherein the selecting an operating frequency for the one power island of the plurality of power islands comprises:
sending a request from a first power manager to a second power manager to change the operating frequency of the one power island of the plurality of power islands,
receiving the request by the second power manager, and
selecting, by the second power manager, the operating frequency from the set of predetermined frequencies for the one power island of the plurality of power islands.

US Pat. No. 10,303,370

FLASH MEMORY SYSTEM

CONVERSANT INTELLECTUAL P...

1. A non-volatile memory system comprising:a non-volatile memory device comprising;
a plurality of non-volatile memory blocks, each non-volatile memory block comprising a plurality of physical rows, each physical row configured to store a maximum of N logical rows, N being an integer greater than two, and each non-volatile memory block configured to operate in a plurality of storage modes, the plurality of storage modes comprising:
a first storage mode for programming all of the N logical rows for each physical row;
a second storage mode for programming a subset of the N logical rows comprising at least two and less than the N logical rows for each physical row; and
a third storage mode for programming a single logical row for each physical row; and
a memory controller communicatively coupled to the non-volatile memory device, the memory controller configured to: determine one of the plurality of storage modes for each non-volatile memory block of the non-volatile memory device, and issue a program command packet set comprising at least one program command packet, the program command packet set limited to addressing a subset of logical row addresses selected from all possible logical row addresses corresponding to each physical row of the non-volatile memory device, each program command packet comprising a row address having at least one bit representing a selected physical row and at least one bit representing a logical row address of the subset of logical row addresses corresponding to the selected physical row when the second storage mode is determined.

US Pat. No. 10,199,933

CIRCUIT FOR CLAMPING CURRENT IN A CHARGE PUMP

Conversant Intellectual P...

1. A charge pump comprising:a first capacitor coupled to an output of the charge pump;
a pump up current path comprising a first transistor coupled between a first power supply and a first node, the gate of the first transistor coupled to a first output of said phase detector, and a second transistor coupled between the first node and said first capacitor, the gate of the second transistor coupled to a first bias input;
a pump down current path comprising a third transistor coupled between a second power supply and a second node, the gate of the third transistor coupled to a second output of said phase detector, and a fourth transistor coupled between the second node and the first capacitor, the gate of the fourth transistor coupled to a second bias input;
a first alternate current path coupled between the first intermediate node and said second power supply configured to conduct current for a first period of time when said first transistor is switched to an off state; and
a second alternate current path coupled between the second intermediate node and said first power supply configured to conduct current for a second period of time when said third transistor is switched to an off state,
wherein said first alternate current path further comprises a fifth transistor coupled to the first node and a third node, a sixth transistor coupled to the third node and the second power supply, and a first inverter whose input is coupled to the first output of the phase detector and whose output is coupled to the gate of the fifth transistor, the gate of the sixth transistor coupled to a third bias input,
wherein said second alternate current path further comprises a seventh transistor coupled to the second node and a fourth node, an eighth transistor coupled to the fourth node and said first power supply, and a second inverter whose input is coupled to the second output of the phase detector and whose output is coupled to the seventh transistor, the gate of the eighth transistor coupled to a fourth bias input.

US Pat. No. 10,200,015

POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Conversant Intellectual P...

1. A method of managing power on an integrated circuit including a plurality of power islands, the method comprising:determining a target power level for one power island of the plurality of power islands based on needs and operation of the integrated circuit where power consumption of each power island within the plurality of power islands is independently controlled within each of the power islands, said each power island operating at a frequency among a set of predetermined frequencies associated with said each power island;
determining an action among a plurality of actions to change a power consumption level of the one power island of the plurality of power islands to the target power level; and
performing the action to change the power consumption level of the one power island of the plurality of power islands to the target power level, wherein the plurality of actions comprises powering-up/off one power island of the plurality of power islands, selecting an operating frequency from the set of predetermined frequencies for the one power island of the plurality of power islands, and selecting a source voltage vdd for one power island of the plurality of power islands,
wherein the selecting an operating frequency for the one power island of the plurality of power islands comprises:
sending a request from a first power manager to a second power manager to change the operating frequency of the one power island of the plurality of power islands,
receiving the request by the second power manager, and
selecting, by the second power manager, the operating frequency from the set of predetermined frequencies for the one power island of the plurality of power islands.

US Pat. No. 10,199,113

NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES

Conversant Intellectual P...

11. A non-volatile memory system comprising:a first power supply voltage;
a second power supply voltage being greater than the first power supply voltage;
a memory device, the memory device comprising:
a NAND flash memory configured to store data,
a first power input pin configured to receive the first power supply voltage for operating the memory device,
a second power input pin configured to receive the second power supply voltage,
a power management circuitry configured to generate plurality of internal voltages from at least one of the first power supply voltage and the second power supply voltage, the plurality of internal voltages configured to be utilized by the NAND flash memory,
a first register configured to indicate whether the memory device supports the second power supply voltage, and
a second register configured to be set for enabling the second power supply voltage; and
a memory controller communicatively coupled to the memory device and configured to read a value of the first register of the memory device, and enable a bit of the second register of the memory device to enable utilization of the second power supply voltage for generating the plurality of internal voltages by the power management circuitry of the memory device when the value read from the first register of the memory device indicates that the memory device supports the second power supply.

US Pat. No. 10,403,766

NAND FLASH MEMORY WITH VERTICAL CELL STACK STRUCTURE AND METHOD FOR MANUFACTURING SAME

Conversant Intellectual P...

1. A flash memory comprising:a substrate in a memory array;
a plurality of source lines, each of the plurality of source lines extending in a main direction;
a plurality of cell stacking layers formed on the substrate of the memory array containing the source lines;
a plurality of cell pillars in the cell stacking layers, each cell pillar having a pillar body, each pillar body being such that during an erase operation, the pillar body and an ion-implanted well form a single node; and
a plurality of bitlines and a plurality of wordlines, each of the plurality of bitlines extending in the main direction parallel to the plurality of source lines which are formed in the substrate and perpendicular to the plurality of wordlines.