US Pat. No. 9,134,698

THREE DIMENSIONAL DISPLAY COMPUTE SYSTEM

Coherent Logix, Incorpora...

1. A non-transitory computer accessible memory medium that stores program instructions for video holography, wherein the program
instructions are executable by at least one processor to implement: receiving information regarding a two dimensional (2D)
hogel array, comprising a plurality of hogel apertures, wherein the information regarding the 2D hogel array specifies number,
size, and spacing of the hogel apertures;
receiving information regarding a 3D scene to be rendered, including a scaling factor that maps the 3D scene to a 3D display
volume;

for each hogel of a sparse subset of the hogels in the 2D hogel array:
computing a 2D perspective rendering of the 3D scene from the point of view (POV) of the hogel of the sparse subset;
computing a color radiation intensity pattern based on the 2D perspective rendering;
for each hogel of a complementary subset of the hogels with respect to the sparse subset:
interpolating the color radiation intensity patterns of three or more hogels of the sparse subset in a neighborhood of the
hogel, thereby generating an interpolated color radiation intensity pattern for the hogel of the complementary subset;

computing a full set of color radiation intensity patterns for the 2D hogel array based on the color radiation intensity patterns
of the sparse subset of hogels and the interpolated color radiation intensity patterns for the complementary subset of the
hogels; and

storing the full set of color radiation intensity patterns for the 2D hogel array, wherein the full set of color radiation
intensity patterns for the 2D hogel array is useable to render a video holographic view of the 3D scene on a video display
device.

US Pat. No. 9,292,464

MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK

Coherent Logix, Incorpora...

1. A multiprocessor system, comprising:
a plurality of processors, each comprising a plurality of processor ports;
a plurality of memories;
a plurality of routers, wherein the plurality of routers form a primary interconnection network;
wherein the plurality of processors, the plurality of memories and the plurality of routers are coupled together in a interspersed
fashion;

a plurality of interface units, wherein each interface unit is coupled to a respective processor and a respective router;
wherein the plurality of interface units are coupled together to form a secondary interconnection network;
a bus controller coupled to at least one specified interface unit, wherein the bus controller is configured to send data to
and receive data from the at least one specified interface unit;

wherein the bus controller is configured to arbitrate requests for access to the at least one specified interface unit;
a processor interface block coupled to the bus controller and also coupled to a specified router associated with the at least
one specified interface unit, wherein the processor interface block is configured to allow any of a plurality of processors
in the multiprocessor system to use the primary interconnection network to access the secondary interconnection network through
the specified router.

US Pat. No. 9,325,329

AUTOMATIC SELECTION OF ON-CHIP CLOCK IN SYNCHRONOUS DIGITAL SYSTEMS

Coherent Logix, Incorpora...

1. A synchronous digital system comprised on a chip, the synchronous digital system comprising:
synchronous digital logic configured to operate using a primary clock signal;
an on-chip clock signal generator configured to generate a first clock signal independent of an external clock signal received
by the synchronous digital system; and

clock signal selector circuitry configured to select between a plurality of clock signals for use as the primary clock signal,
wherein the plurality of clock signals comprises the first clock signal and a signal dependent on the external clock signal,
wherein the clock signal selector circuitry is further configured to:

when a clock selection override signal indicates normal operation, select between the plurality of clock signals based at
least in part on the contents of a software-configurable register; and

when the clock selection override signal indicates a condition requiring selection of a clock signal generated on-chip for
use as the primary clock signal, select the first clock signal;

wherein the clock selection override signal comprises a tamper detection signal, and wherein the clock selection override
signal indicating a condition requiring selection of a clock signal generated on-chip for use as the primary clock signal
comprises the tamper detection signal indicating possible tampering with the synchronous digital system.

US Pat. No. 9,252,920

PARALLEL PROCESSING OF OVERLAPPING SUBSEQUENCES TO GENERATE SOFT ESTIMATES

Coherent Logix, Incorpora...

1. A method comprising:
operating in parallel on overlapping subsequences of a first symbol data sequence, wherein the first symbol data sequence
is received from a channel, and represents a channel-perturbed version of a transmitted symbol data sequence, wherein the
first symbol data sequence includes a temporal sequence of symbol values, wherein said operating in parallel is performed
by a first set of one or more processors, wherein each of the one or more processors operates on a respective group of one
or more of the overlapping subsequences, wherein each of the overlapping subsequences of the first symbol data sequence corresponds
to a respective portion of a first trellis, wherein the first trellis represents redundancy in the first symbol data sequence,
wherein said operating in parallel generates soft estimates for first information bits associated with the transmitted symbol
data sequence;

wherein the soft estimates are useable to form a receive message corresponding to the first information bits.

US Pat. No. 9,323,714

PROCESSING SYSTEM WITH SYNCHRONIZATION INSTRUCTION

Coherent Logix, Incorpora...

1. A system, comprising:
a plurality of processors, wherein each processor of the plurality of processors includes a plurality of processor ports and
a synchronization adapter, wherein the synchronization adapter includes a plurality of adapter ports;

a plurality of controllers, wherein each controller of the plurality of controllers includes a plurality of controller ports,
wherein each controller port of the plurality of controller ports is coupled to adapter port of a neighboring processor of
the plurality of processors;

wherein each processor of the plurality of processors is configured to:
send, selectively, a synchronization signal through one or more adapter ports to a respective one or more controllers of the
plurality of controllers; and

pause execution of program instructions dependent upon a response from the one or more controllers;
wherein each controller of the plurality of controllers is configured to:
receive one or more synchronization signals from a respective one or more processors of the plurality of processors; and
send a response to each of the respective one or more processors of the plurality of processors dependent upon the received
one or more synchronization signals.

US Pat. No. 9,450,590

CLOCK DISTRIBUTION NETWORK FOR MULTI-FREQUENCY MULTI-PROCESSOR SYSTEMS

COHERENT LOGIX, INCORPORA...

1. A method for reconfiguring clock generation circuitry in a clock distribution network of a synchronous digital system,
the method comprising:
generating a first clock signal using the clock generation circuitry;
selecting the first clock signal as a primary clock for the synchronous digital system, wherein the synchronous digital system
is comprised on a chip;

detecting a signal indicating possible tampering with the synchronous digital system;
selecting a second clock signal as the primary clock in response to the detecting, wherein the second clock signal is generated
by an on-chip oscillator that is independent of external clock signals, wherein the selecting the second clock signal comprises
causing the second clock signal to replace the first clock signal as the primary clock without causing clock-induced errors
in the synchronous digital system;

reconfiguring the clock generation circuitry during the time that the second clock signal is acting as the primary clock;
and

selecting the first clock signal as the primary clock for the synchronous digital system after the clock generation circuitry
has stabilized, wherein the selecting the first clock signal comprises causing the first clock signal to replace the second
clock signal as the primary clock without causing clock-induced errors in the synchronous digital system.

US Pat. No. 9,442,461

THREE DIMENSIONAL DISPLAY SYSTEM

Coherent Logix, Incorpora...

1. A non-transitory computer accessible memory medium that stores program instructions executable by at least one processor
to implement:
receiving information regarding a two dimensional (2D) hogel array, comprising a plurality of hogel apertures, wherein the
information regarding the 2D hogel array specifies number, size, and spacing of the plurality of hogel apertures;

receiving information regarding a 3D scene to be rendered, including a scaling factor that maps the 3D scene to a 3D display
volume;

for each hogel aperture of a sparse subset of the plurality of hogel apertures in the 2D hogel array:
computing a 2D perspective rendering of the 3D scene from the point of view (POV) of the hogel aperture of the sparse subset;
and

computing a color radiation intensity pattern based on the 2D perspective rendering;
for each hogel aperture of a complementary subset of the hogel apertures that are complementary with respect to the sparse
subset:

interpolating the color radiation intensity patterns of a plurality of hogel apertures of the sparse subset in a specified
neighborhood of the hogel aperture, thereby computing an interpolated color radiation intensity pattern for the hogel aperture
of the complementary subset;

computing a full set of color radiation intensity patterns for the 2D hogel array based on the color radiation intensity patterns
of the sparse subset of hogel apertures and the interpolated color radiation intensity patterns for the complementary subset
of the hogel apertures; and

storing the full set of color radiation intensity patterns for the 2D hogel array, wherein the full set of color radiation
intensity patterns for the 2D hogel array is useable to display a holographic view of the 3D scene.

US Pat. No. 9,362,981

MECHANISMS FOR LOW-AMPLITUDE ECHO ESTIMATION

Coherent Logix, Incorpora...

1. A non-transitory memory medium for identifying minor echoes present in an input signal in the situation where two or more
major echoes, also present in the input signal, have already been identified, wherein the memory medium stores program instructions,
wherein the program instructions, when executed by one or more processors, cause the one or more processors to:
(a) subtract a weighted power spectrum SM from a weighted power spectrum of the input signal to obtain a difference spectrum, wherein the weighted power spectrum SM is a weighted power spectrum of a spectrum F, wherein the spectrum F corresponds to a sum of the major echoes; and

(b) estimate one or more of the minor echoes from a time-domain signal to obtain echo parameters for the one or more minor
echoes, wherein the time-domain signal is determined based at least in part on the difference spectrum and the spectrum F;

remove the two or more major echoes and the one or more minor echoes from the input signal to obtain an equalized signal;
recover information bits from the equalized signal; and
provide an output signal to an output device, wherein the output signal is generated based on the information bits.

US Pat. No. 9,515,776

WIRELESS TRANSMISSION OF MULTIMEDIA STREAMS WHICH USES CONTROL INFORMATION TO ASSOCIATE ERROR CORRECTION CODING WITH AN AUDIOVISUAL STREAM

Coherent Logix, Incorpora...

1. A system for transmitting audiovisual information in a wireless manner, the system comprising:
an input for receiving audiovisual information;
transmit logic coupled to the input, wherein the transmit logic is configured to generate a first stream and a separately
transmittable second stream, wherein one or more of the first stream and the second stream comprise first audiovisual information,
wherein one or more of the first stream and the second stream comprise first error correction coding information associated
with the first audiovisual information, wherein one or more of the first stream and the second stream comprise control information
indicating that the first stream and the second stream are associated;

a transmitter coupled to the transmit logic, wherein the transmitter is configured to transmit the first stream and the second
stream in a wireless manner.

US Pat. No. 9,363,543

WIRELESS SYSTEM WITH VARIABLE TRAINING INFORMATION BASED ON DEVICE TYPE

Coherent Logix, Incorpora...

1. A method for broadcasting audiovisual information in a wireless manner, the method comprising:
storing training information in a memory;
generating a plurality of packets,
wherein the plurality of packets comprise audiovisual information intended for one or more types of receivers;
wherein the plurality of packets comprises the training information, wherein an amount of the training information depends
on time of transmission of the plurality of packets, wherein the amount is greater at times when mobile receivers are estimated
to represent a greater proportion of receiving devices;

wherein at least one of the plurality of packets comprises first information which identifies a first training pattern of
a plurality of possible training patterns, wherein the first training pattern specifies one or more locations of the training
information in the plurality of packets;

wherein the first information is useable by the receiver to determine the first training pattern of the plurality of possible
training patterns;

transmitting the plurality of packets on a signal modulated in the frequency domain in a wireless manner.

US Pat. No. 9,195,575

DYNAMIC RECONFIGURATION OF APPLICATIONS ON A MULTI-PROCESSOR EMBEDDED SYSTEM

Coherent Logix, Incorpora...

1. A method for performing application swapping in a multiprocessor system, the method comprising:
loading a plurality of applications on the multiprocessor system, wherein the multiprocessor system comprises a plurality
of processors and a plurality of memories interspersed among the processors, wherein said loading comprises distributing instructions
and data from the plurality of applications among different respective ones of the plurality of memories for execution by
associated processors;

executing the plurality of applications on the multiprocessor system, wherein the plurality of applications execute together
and communicate with each other to perform a real time operation, wherein the real time operation performs at least one of
input or output with real time data, wherein the plurality of applications process the real time data, wherein the plurality
of applications comprise a first application and a plurality of other applications;

swapping the first application with a second application, wherein the second application is not one of the plurality of applications
that was previously loaded and executing on the multiprocessor system, wherein said swapping is performed without stopping
the plurality of other applications, wherein the plurality of other applications continue to execute during said swapping
to perform the real time operation and process the real time data;

wherein after said swapping, the plurality of other applications continue to execute with the second application, and wherein
at least a subset of the plurality of other applications communicate with the second application to perform the real time
operation and process the real time data;

wherein said swapping includes loading the second application into two or more of the memories, wherein said loading comprises
sending program instructions of the second application through the multiprocessor system along two or more swapping routes,
wherein each of the swapping routes is associated with one of the two or more memories; and

wherein the two or more swapping routes share a first part in common, wherein the first part includes a route from an I/O
port of the multiprocessor system to an endpoint within the multiprocessor system, and wherein the first part is specified
by user input.

US Pat. No. 9,154,142

MULTI-FREQUENCY CLOCK SKEW CONTROL FOR INTER-CHIP COMMUNICATION IN SYNCHRONOUS DIGITAL SYSTEMS

Coherent Logix, Incorpora...

1. An apparatus comprising:
a reference clock generator configured to generate a reference clock signal; and
a plurality of integrated circuit chips, each chip of the plurality of integrated circuit chips comprising:
clock generation circuitry configured to generate a primary clock signal dependent upon the reference clock signal;
synchronizing signal generation circuitry configured to generate a synchronizing signal that is edge-aligned to the primary
clock signal, wherein the respective synchronizing signals of the plurality of chips are phase-aligned as a result of their
common dependence upon the reference clock signal;

clock divider circuitry configured to:
receive a delayed version of the primary clock signal and a delayed version of the synchronizing signal; and
generate a frequency-adjusted clock signal having a frequency that is a function of a frequency of the delayed version of
the primary clock signal, wherein the frequency-adjusted clock signal is edge-aligned to the delayed version of the primary
clock signal and phase-aligned to the delayed version of the synchronizing signal; and

input/output (I/O) circuitry configured to:
receive as a clock input the frequency-adjusted clock signal; and
communicate with the respective I/O circuitry of another chip of the plurality of chips;
wherein a first chip of the plurality of integrated circuit chips is configured to generate a respective primary clock signal
at a first frequency, and a second chip of the plurality of integrated circuit chips is configured to generate a respective
primary clock signal at a second, different frequency, wherein both the first chip and the second chip are configured to generate
respective frequency-adjusted clock signals at a third frequency, wherein the frequency-adjusted clock signal of the first
chip is phase-aligned with the frequency-adjusted clock signal of the second chip.

US Pat. No. 9,438,459

MULTI-PARTITION RADIO FRAMES

Coherent Logix, Incorpora...

1. A mobile device, comprising:
a wireless radio;
one or more antennas; and
one or more processors;
wherein the mobile device is configured to:
receive, using the wireless radio, a frame of wireless data that includes:
a plurality of partitions that each include multiple orthogonal frequency-division multiplexing (OFDM) symbols, wherein different
ones of the partitions have different frequency transform sizes; and

partition data that indicates the frequency transform sizes for the ones of the partitions, wherein a first one of the plurality
of partitions has a first frequency transform size that is adapted for decoding by mobile devices moving at velocities up
to a first maximum velocity and wherein a second one of the plurality of partitions has a second frequency transform size
that is adapted for decoding by mobile devices that are moving at velocities up to a second, different maximum velocity;

select, based on the partition data, one or more but not all of the plurality of partitions; and
decode the selected one or more partitions to determine data represented by the OFDM symbols in the selected one or more partitions.

US Pat. No. 9,424,441

MULTIPROCESSOR FABRIC HAVING CONFIGURABLE COMMUNICATION THAT IS SELECTIVELY DISABLED FOR SECURE PROCESSING

Coherent Logix, Incorpora...

1. A method for disabling communication in a multiprocessor fabric, the method comprising:
receiving a configuration for the multiprocessor fabric, wherein the multiprocessor fabric comprises a plurality of processors
and a plurality of communication elements, wherein the configuration specifies disabling of communication paths between one
or more of:

one or more processors and one or more communication elements;
one or more processors and one or more other processors; or
one or more communication elements and one or more other communication elements;
automatically configuring, in hardware, the multiprocessor fabric to disable the communication paths specified by the configuration,
wherein after said automatically configuring, the disabled communication paths are not restorable via software; and

operating the multiprocessor fabric to execute a software application, wherein the multiprocessor fabric operates according
to the configuration.

US Pat. No. 9,424,213

PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS DMA-FIFO

Coherent Logix, Incorpora...

1. A system, comprising:
a plurality of processors, each comprising a plurality of processor ports; and
a plurality of configurable communication elements coupled to the plurality of processors in an interspersed fashion, wherein
each configurable communication element comprises:

a plurality of communication ports;
a routing engine coupled the plurality of communication ports;
a plurality of memories, wherein each memory is coupled to a subset of processors;
a plurality of direct memory access (DMA) engines, wherein each DMA engine of the plurality of DMA engines is coupled to a
respective one of the plurality of communication ports, and wherein each DMA engine is configured to:

transfer data between a subset of the plurality of memories, and the respective one of the communication ports; and
process the transferred data;
wherein each subset of one or more subsets of the plurality of DMA engines is configured to operate on a common portion of
a memory of the plurality of memories to implement one of a plurality of first in first out (FIFO) buffers;

wherein each DMA engine of a given subset of the one or more subsets of the plurality of DMA engines is configured to:
receive a respective input data stream of a plurality of input data streams;
perform a respective calculation on the respective data stream to generate a respective data signature of a plurality of data
signatures;

a DMA controller configured to:
control the operation of one or more of the plurality of DMA engines; and
control one of the one or more subsets of the plurality of DMA engines;
wherein to control the operation of the one or more subsets of the plurality of DMA engines, the DMA controller is further
configured to reorder data among the plurality of input data streams and compare the plurality of data signatures, wherein
a result of the comparison is available for use by application software.

US Pat. No. 9,250,867

PROGRAMMING A MULTI-PROCESSOR SYSTEM

Coherent Logix, Incorpora...

1. A computer-implemented method for creating a program for a multi-processor system, wherein the multi-processor system comprises
an array of processors and a plurality of memories coupled to the processors, wherein the plurality of memories are interspersed
among the plurality of processors within an apparatus, wherein each of the processors is coupled to at least one other processor,
the method comprising:
storing source code in response to user input, wherein the source code specifies first functionality, wherein the source code
is intended to execute on the multi-processor system, wherein the source code specifies a plurality of tasks and communication
of data among the plurality of tasks, wherein the source code further does not specify allocation of local variables among
the plurality of tasks;

creating machine language instructions based on the source code, wherein the machine language instructions are designed to
execute on the array of processors;

determining an assignment of tasks to respective processors in the multi-processor system;
subsequent to the determining, selecting communication mechanisms between tasks assigned to the respective processors based
on location of the respective processors in the array and required communication of data, wherein the selecting includes:

allocating local variables to memories proximate to two or more processors assigned to execute tasks that own the local variables;
and

configuring message passing links via a plurality of communications units coupled to processors in the array of processors,
wherein the message passing links are for tasks that are assigned to processors that do not share proximate memories, and
wherein the configuring includes synthesizing the message links between processors by binding communication requirements in
the source code to routing logic; and

storing the machine language instructions in various ones of the plurality of memories, wherein the multi-processor system
is operable to execute the machine language instructions using the allocated local variables and configured message passing
links to implement the first functionality.

US Pat. No. 9,535,877

PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS AND COMMUNICATION ELEMENTS HAVING IMPROVED COMMUNICATION ROUTING

COHERENT LOGIX, INCORPORA...

1. A system, comprising:
a plurality of processors, each comprising a plurality of processor ports; and
a plurality of dynamically configurable communication elements, each comprising a plurality of communication ports, a first
memory, and a routing engine;

wherein the plurality of dynamically configurable communication elements are interspersed among the plurality of processors
and coupled to respective ones of the plurality of processors;

wherein each the plurality of dynamically configurable communication elements is configured to be used by at least two of
the plurality of processors;

wherein, for each respective one of the processors, a first portion of the plurality of processor ports are coupled to a respective
subset of the plurality of dynamically configurable communication elements and a second portion of the plurality of processor
ports are directly coupled to a respective subset of the plurality of processors that are physically adjacent to the processor;

wherein, for each of the dynamically configurable communication elements, the plurality of communication ports comprise a
first subset of communication ports coupled to a subset of the plurality of said processors and a second subset of communication
ports coupled to a second subset of the plurality of dynamically configurable communication elements; and

wherein, for each of at least a plural subset of said dynamically configurable communication elements, the first memory of
a respective dynamically configurable communication element is shared among a respective subset of the processors.

US Pat. No. 9,477,585

REAL TIME ANALYSIS AND CONTROL FOR A MULTIPROCESSOR SYSTEM

COHERENT LOGIX, INCORPORA...

1. A method for testing a device under test (DUT) that comprises a multiprocessor array (MPA) executing application software,
the method comprising:
storing application software that is desired to be tested, wherein the application software is deployable to execute on first
hardware resources of the MPA, wherein the MPA includes a plurality of processing elements, a plurality of memories, and an
interconnection network (IN) communicatively coupling the plurality of processing elements and the plurality of memories;

modifying the application software that is desired to be tested to include testing code, thereby creating modified application
software, wherein the testing code in the modified application software includes at least one auxiliary send statement;

deploying the modified application software on hardware resources of the MPA, wherein said deploying comprises deploying the
application software to use the first hardware resources of the MPA and deploying the test code to execute on at least one
of the first hardware resources and configured to use one or more second hardware resources of the MPA, wherein the second
hardware resources are different from the first hardware resources and are not used by the application software, wherein the
MPA executing the modified application software in real time at full operational speed comprises the device under test (DUT);

receiving, by the modified application software, input data to stimulate the DUT;
generating, by the modified application software, first data in the DUT based on the input data;
executing, by the modified application software, a first send statement which provides the first data for use in the modified
application software, wherein the first send statement executes on one of the first hardware resources of the MPA;

executing, by the modified application software, an auxiliary send statement on one of the first hardware resources to provide
at least a subset of the first data to a pin at an edge of the MPA using at least one of the one or more second hardware resources
of the MPA; and

receiving the at least a subset of the first data provided by the auxiliary send statement, wherein the first data are useable
for analyzing operation of the DUT.

US Pat. No. 9,430,422

PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS WITH MULTI-LAYER INTERCONNECT

Coherent Logix, Incorpora...

1. An apparatus, comprising:
a plurality of processors; and
a plurality of configurable communication elements coupled to the plurality of processors in an interspersed arrangement,
wherein each configurable communication element of the plurality of configurable communication elements includes:

a local memory coupled to a subset of the plurality of processors; and
a plurality of routing engines, wherein each routing engine of the plurality of routing engines is configured to:
receive one or more messages from a plurality of sources, wherein each message of the one or more messages includes one or
more data words;

assign each message of the one or more messages to a given destination of a plurality of destinations dependent upon configuration
information;

forward each message of the one or more messages to the destination assigned to the message;
wherein the plurality of destinations includes:
the local memory; and
a set of routing engines comprising the plurality of routing engines included in a first subset of the plurality of configurable
communication elements;

wherein to forward each message of one or more messages each routing engine of the plurality of routing engines is further
configured to change the receive status of each assigned destination responsive to the completion of sending a message to
each assigned destination.

US Pat. No. 9,430,369

MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS

Coherent Logix, Incorpora...

1. An apparatus, comprising:
an execution unit;
a fetch unit configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields;
and

a plurality of address generator units;
wherein a first address generator unit of the plurality of address generator units is configured to perform a first arithmetic
operation for a first thread of sub-instructions dependent upon a first field of the plurality of fields and store a result
of the first arithmetic operation in a register;

wherein a second address generator unit is configured to generate at least one address of a plurality of addresses, wherein
each address of the plurality of addresses is dependent upon a respective field of the plurality of fields, wherein the apparatus
is configured to use the at least one address to access one or more input operands for the execution unit for a second thread
of sub-instructions; and

wherein the apparatus is configured to use the result of the first arithmetic operation stored in the register to access one
or more input operands for the execution unit for a sub-instruction in the first thread of sub-instructions in a subsequent
multi-part instruction.

US Pat. No. 10,033,566

MULTI-PORTION RADIO TRANSMISSIONS

Coherent Logix, Incorpora...

1. An apparatus, comprising:one or more processing elements configured to:
receive, via a wireless radio, wireless data that includes:
a plurality of portions that each include multiple orthogonal frequency-division multiplexing (OFDM) symbols, wherein different ones of the portions have different frequency transform sizes and different sampling rates; and
control data that indicates the frequency transform sizes and sampling rates for the ones of the portions;
select, based on the control data and a determined velocity of the apparatus, one or more but not all of the plurality of portions; and
decode the selected one or more portions to determine data represented by the OFDM symbols in the selected one or more portions.

US Pat. No. 9,960,787

WIRELESS TRANSPORT FRAMEWORK WITH UNCODED TRANSPORT TUNNELING

Coherent Logix, Incorpora...

1. A method for transmitting packetized information according to multiple service versions of a transport framework in a wireless manner, the method comprising:processing first information for transmission according to a first service version of a transport framework and second information for transmission according to a second service version of the transport framework, comprising encoding the first information and second information using a first type of error correction coding, wherein after processing according to the first service version, the processed first information comprises error correction coding information according to the first type of error correction coding, wherein after processing according to the second service version, the processed second information remains uncoded according to the first type of error correction coding;
generating control information indicating that the second information remains uncoded according to the first type of error correction coding, wherein the indication that the second information remains uncoded according to the first type of error correction coding signals to receivers that the second information is processed according to the second service version of the transport framework;
generating a plurality of packets comprising the processed first information, the processed second information, and the control information; and
transmitting the plurality of packets in a wireless manner.

US Pat. No. 9,558,150

PROCESSING SYSTEM WITH SYNCHRONIZATION INSTRUCTION

Coherent Logix, Incorpora...

1. A system, comprising:
a plurality of processors, wherein each processor of the plurality of processors includes a plurality of processor ports and
a synchronization adapter, wherein the synchronization adapter includes a plurality of adapter ports;

a plurality of controllers, wherein each controller of the plurality of controllers includes a plurality of controller ports,
wherein each controller port of the plurality of controller ports is coupled to adapter port of a neighboring processor of
the plurality of processors;

wherein each processor of the plurality of processors is configured to:
execute a plurality of threads, wherein each thread of the plurality of threads includes a plurality of program instructions;
send, selectively, a plurality of synchronization signals through a given adapter port to a respective controller of the plurality
of controllers; and

pause execution of program instructions included in a given thread of the plurality of threads dependent upon a response from
the respective controller;

wherein each controller of the plurality of controllers is configured to:
receive a respective plurality of synchronization signals from each processor of one or more processors of the plurality of
processors; and

send a response to each processor of the one or more processors dependent upon a corresponding plurality of synchronization
signals of the received respective plurality of synchronization signals.

US Pat. No. 10,075,857

PARAMETERIZED RADIO WAVEFORM TECHNIQUES FOR OPERATING IN MULTIPLE WIRELESS ENVIRONMENTS

Coherent Logix, Incorpora...

1. An apparatus, comprising:one or more processors; and
one or more memory elements having program instructions stored thereon that are executable by the one or more processors to:
receive a first parameter value set from a first broadcast transmitter of a wireless network, wherein the first parameter value set is selected, by a configuration controller that is located remotely from the first broadcast transmitter, from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first target range of wireless transmission;
wherein, for each of two or more parameters, each of the parameter value sets in the group includes a corresponding value, wherein the two or more parameters include one or more parameters based upon which the apparatus is configured to determine subcarrier spacing and one or more parameters that indicate a cyclic prefix size;
reconfigure the apparatus to receive wireless broadcast transmissions from the first broadcast transmitter using the first parameter value set;
receive wireless broadcast transmissions from the first broadcast transmitter and decode the received wireless broadcast transmissions from the first broadcast transmitter using the first parameter value set;
receive a second parameter value set selected from a group of multiple parameter value sets from a second broadcast transmitter of a wireless network, wherein the second parameter value set is appropriate for a second target radio operating environment that corresponds to one or more of: a second, different level of mobility of user devices or a second, different target range of wireless transmission;
reconfigure the apparatus to receive wireless broadcast transmissions from the second broadcast transmitter using the second parameter value set; and
receive wireless broadcast transmissions from the second broadcast transmitter and decode the received wireless broadcast transmissions from the second broadcast transmitter using the second parameter value set;
wherein the two or more parameters specify both sampling rate and frequency transform size and wherein the first parameter value set specifies a first frequency transform size and the second parameter value set specifies a second, smaller frequency transform size.

US Pat. No. 9,612,984

MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK

COHERENT LOGIX, INCORPORA...

1. A multiprocessor system, comprising:
a plurality of processors, each comprising a plurality of processor ports;
a plurality of memories;
a plurality of routers, wherein the plurality of routers form a primary interconnection network;
wherein the plurality of processors, the plurality of memories and the plurality of routers are coupled together in an interspersed
fashion;

a plurality of interface units, wherein each interface unit is coupled to a respective processor and a respective router;
wherein the plurality of interface units are coupled together to form a secondary interconnection network; and
a bus controller coupled to at least one specified interface unit, wherein the bus controller is configured to:
send data to and receive data from the at least one specified interface unit;
arbitrate requests for access to the at least one specified interface unit; and
perform a comparison between messages received from each of two or more processors and perform a particular one of a plurality
of actions based upon results of the comparison.

US Pat. No. 10,327,235

SCRAMBLING SEQUENCE DESIGN FOR MULTI-MODE BLOCK DISCRIMINATION ON DCI BLIND DETECTION

Coherent Logix, Incorpora...

1. A base station comprising:a radio; and
a processing element coupled to the radio;
wherein the radio and the processing element are configured to:
represent user equipment (UE)-specific control information as two or more sequences of bits, wherein the two or more sequences of bits comprise a frozen bit sequence and an information bit sequence of a polar code;
generate two or more pseudorandom sequences from two or more respective identifiers, wherein the two or more respective identifiers comprise a UE identifier and an identifier of the base station;
modulate the frozen bit sequence with the pseudorandom sequence generated from the UE identifier, and modulate the information bit sequence with the pseudorandom sequence generated from the identifier of the base station to produce modulated control information;
encode the modulated control information to obtain encoded modulated control information, wherein encoding the modulated control information uses the polar code to perform the encoding; and
wirelessly transmit the encoded modulated control information.

US Pat. No. 10,114,739

REAL TIME ANALYSIS AND CONTROL FOR A MULTIPROCESSOR SYSTEM

Coherent Logix, Incorpora...

1. A method, comprising:analyzing application software;
developing test software based, at least in part, on results of analyzing the application software;
deploying the application software on a first hardware resource of a multi-processor array (MPA), wherein the MPA includes a plurality of processing elements, a plurality of memories, and an interconnection network communicatively coupling the plurality of processing elements to the plurality of memories, wherein the first hardware resource includes at least a first subset of the plurality of processing elements;
deploying the test software on a second hardware resource of the MPA, wherein the second hardware resource includes at least a second subset of the plurality of processing elements different than the first subset of the plurality of processing elements;
executing the application software on the first hardware resource; and
executing the test software on the second hardware resource, wherein executing the test software includes:
polling, by a first processing element included in the second hardware resource, one or more registers associated with a direct memory access (DMA) transfer in the first hardware resource resulting from executing one or more program commands included in the application software; and
sending, by the first processing element, auxiliary data retrieved from the one or more registers to a storage location for analysis, wherein an amount of auxiliary data is less than an amount of data generated by the application software; and
rebuilding the application software based on the auxiliary data.

US Pat. No. 10,007,806

SECURE BOOT SEQUENCE FOR SELECTIVELY DISABLING CONFIGURABLE COMMUNICATION PATHS OF A MULTIPROCESSOR FABRIC

Coherent Logix, Incorpora...

1. A system, comprising:a multiprocessor fabric, wherein the multiprocessor fabric comprises a plurality of processors and a plurality of communication elements;
configuration logic, wherein the configuration logic is configured to:
receive a configuration for the multiprocessor fabric, wherein the configuration specifies disabling of communication paths between one or more of:
one or more processors and one or more communication elements;
one or more processors and one or more other processors; or
one or more communication elements and one or more other communication elements; and
perform a secure boot sequence automatically upon resetting or powering up the multiprocessor fabric, wherein the secure boot sequence includes automatically configuring the multiprocessor fabric to disable the communication paths specified by the configuration, wherein after said automatically configuring, the disabled communication paths are not restorable via software;
wherein, after said configuring, the multiprocessor fabric is configured to execute a software application, wherein the multiprocessor fabric operates according to the configuration.

US Pat. No. 9,749,879

PARAMETERIZED RADIO WAVEFORM FOR OPERATING IN MULTIPLE WIRELESS ENVIRONMENTS

COHERENT LOGIX, INCORPORA...

1. A method for operating a configuration controller of a wireless network in a plurality of radio operating environments,
the method comprising:
performing operations by a computer system of the configuration controller, wherein the operations include:
selecting a first parameter value set from a library of two or more parameter value sets, wherein, for each of two or more
communication-related parameters, each of the parameter value sets includes a corresponding value for the communication-related
parameter, wherein the two or more communication-related parameters include nominal subcarrier spacing and cyclic prefix size,
wherein the first parameter value set is appropriate for a first target radio operating environment, wherein the first target
radio operating environment corresponds to a first value of mobility of user devices and a first value of range of infrastructure
radio transmission, wherein said selecting the first parameter value set is performed for a first set of one or more infrastructure
radios that are to be operated in the first target radio operating environment, wherein the one or more infrastructure radios
of the first set are located remotely relative to the configuration controller;

applying the first parameter value set to the first set of one or more infrastructure radios so that the first set of one
or more infrastructure radios will start using the first parameter value set to wirelessly communicate with the user devices
in the first target radio operating environment, wherein said applying the first parameter value set is performed by sending
first information to each infrastructure radio of the first set of one or more infrastructure radios, wherein the first information
identifies the first parameter value set;

selecting a second parameter value set from the library of two or more parameter value sets, wherein the second parameter
value set is appropriate for a second target radio operating environment different from the first target radio operating environment,
wherein the second target radio operating environment corresponds to a second value of mobility and a second value of range
of infrastructure radio transmission, wherein said selecting the second parameter value set is performed for a second set
of one or more infrastructure radios that are to be operated in the second target radio operating environment; and

applying the second parameter value set to the second set of one or more infrastructure radios so that the second set of one
or more infrastructure radios will start using the second parameter value set to wirelessly communicate with user devices,
wherein said applying the second parameter value set is performed by sending second information to the second set of one or
more infrastructure radios, wherein the second information identifies the second parameter value set.

US Pat. No. 9,990,241

PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS WITH MULTI-LAYER INTERCONNECTION

Coherent Logix, Incorpora...

1. An apparatus, comprising:a plurality of processors;
a plurality of configurable communication elements coupled to the plurality of processors in an interspersed arrangement;
wherein a particular configurable communication element of the plurality of configurable communication elements is coupled to a first subset of the plurality of processors, and to a second subset of the plurality of processors different from the first subset; and
wherein the particular configurable communication element is configured to receive one or more messages from a particular processor included in the first or second subset of the plurality of processors, and forward the one or more messages to another configurable communication element of the plurality of configurable communication elements using configuration information; and
wherein one or more configurable communication elements of the plurality of configurable communication elements are interspersed between the another configurable communication element and the particular configurable communication element.

US Pat. No. 9,913,153

PARAMETERIZED RADIO WAVEFORM TECHNIQUES FOR OPERATING IN MULTIPLE WIRELESS ENVIRONMENTS

Coherent Logix, Incorpora...

1. An apparatus, comprising:
one or more processors; and
one or more memory elements storing program instructions that are executable by the processor to perform operations comprising:
receiving a first parameter value set from a first broadcast transmitter of a wireless network, wherein the first parameter
value set is selected, by a configuration controller that is located remotely from the first broadcast transmitter, from a
group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating
environment that corresponds to one or more of: a first level of mobility of user devices or a first target range of wireless
transmission;

wherein, for each of two or more parameters, each of the parameter value sets in the group includes a corresponding value,
wherein the two or more parameters include a first parameter based upon which the apparatus is configured to determine subcarrier
spacing and a second parameter that indicates a cyclic prefix size;

reconfiguring the apparatus to receive wireless broadcast transmissions from the first broadcast transmitter using the first
parameter value set;

receiving wireless broadcast transmissions from the first broadcast transmitter and decoding the received wireless broadcast
transmissions from the first broadcast transmitter using the first parameter value set;

receiving a second parameter value set selected from a group of multiple parameter value sets from a second broadcast transmitter
of a wireless network, wherein the second parameter value set is appropriate for a second target radio operating environment
that corresponds to one or more of: a second, different level of mobility of user devices or a second, different target range
of wireless transmission;

reconfiguring the apparatus to receive wireless broadcast transmissions from the second broadcast transmitter using the second
parameter value set; and

receiving wireless broadcast transmissions from the second broadcast transmitter and decoding the received wireless broadcast
transmissions from the second broadcast transmitter using the second parameter value set;

wherein the first parameter specifies both sampling rate and frequency transform size and wherein the first parameter value
set specifies a first frequency transform size for the first parameter and the second parameter value set specifies a second,
smaller frequency transform size for the first parameter.

US Pat. No. 9,904,542

MULTIPROCESSOR PROGRAMMING TOOLKIT FOR DESIGN REUSE

Coherent Logix, Incorpora...

1. A non-transitory computer-accessible memory medium that stores a library of software code deployable on a multiprocessor
array (MPA), wherein the software code comprises:
a cell definition that includes:
first program instructions executable to perform a first function; and
one or more first language constructs which are user configurable to specify one or more communication ports and one or more
parameter inputs;

wherein the one or more communication ports are user configurable to specify communication with other software code in a software
application;

wherein the one or more parameter inputs are user configurable to specify a set of hardware resources usable to execute the
software code, wherein the hardware resources include a plurality of processors and a plurality of memories; and

wherein multiple instances of the first program instructions specified by the cell definition are deployable, based on user
input selecting the cell and specifying one or more different communication ports and one or more different parameter inputs
for ones of the instances, in different hardware portions of at least one MPA to perform the first function in one or more
software applications;

wherein each instance of the cell comprises a respective configuration of the one or more communication ports specifying connectivity
of the one or more communication ports with other software code deployed on the MPA; and

wherein amounts of hardware resources in the respective hardware portion on which one or more respective instances of the
cell are deployed are different and are based on the user-specified one or more parameter inputs.

US Pat. No. 9,560,403

GENERATING CONTROL INFORMATION FOR USE IN TRANSMISSION WITH A MULTIMEDIA STREAM TO AN AUDIOVISUAL DEVICE

COHERENT LOGIX, INCORPORA...

1. A method for generating control information for use in transmission with a multimedia stream to an audiovisual device,
the method comprising:
generating first control information, wherein the first control information is for configuring the audiovisual device to present
a multimedia stream according to a first service type;

generating a first data structure, wherein the first data structure comprises information about the first control information,
wherein the first data structure specifies that the first control information is associated with the first service type;

generating and transmitting a first plurality of packets, the first plurality of packets comprising a multimedia stream according
to the first service type, the first control information, and the first data structure;

generating second control information, wherein the second control information is for configuring the audiovisual device to
present a multimedia stream according to a second service type;

modifying the first data structure to include additional information about the second control information, wherein the modified
first data structure specifies that the second control information is associated with the second service type, wherein the
modified first data structure retains the information about the first control information;

generating and transmitting a second plurality of packets, wherein the second plurality of packets comprise the modified first
data structure, the first control information, a multimedia stream according to the first service type, the second control
information, and a multimedia stream according to the second service type;

wherein the first data structure is separate from the first control information.

US Pat. No. 10,034,147

NEXT GENERATION BROADCAST SYSTEM AND METHOD

Coherent Logix, Incorpora...

1. A method for operating a server, wherein the server is part of an Internet Protocol (IP) network, the method comprising:performing operations to facilitate a non-realtime transfer of a data file to a user equipment (UE) device, the operations including:
receiving segments of the data file from a broadcast gateway, wherein the broadcast gateway is configured to provide the segments to a broadcast transmission system for transmission as a Radio Frequency (RF) signal, wherein the RF signal includes a Uniform Resource Locator (URL) of the server, and wherein the broadcast gateway is configured to receive the segments of the data file from an external network;
establishing a connection, that has been initiated using the URL, with the UE device;
receiving one or more missing segment indications through the IP network from the UE device, the one or more missing segment indications being generated by the UE device based on the RF signal and identifying one or more segments that the UE device is not able to successfully recover from the RF signal, wherein each of the one or more missing segment indications includes:
a sequence number of a respective one of the one or more segments that the UE device is not able to successfully recover from the RF signal; and
a time-stamp associated with the respective one of the one or more segments that the UE device is not able to successfully recover from the RF signal; and
sending the one or more segments identified by the missing segment indications to the UE device through the IP network.

US Pat. No. 10,007,293

CLOCK DISTRIBUTION NETWORK FOR MULTI-FREQUENCY MULTI-PROCESSOR SYSTEMS

Coherent Logix, Incorpora...

1. A synchronous digital system comprised on a chip, the synchronous digital system comprising:synchronous digital logic configured to operate using a primary clock signal;
an on-chip clock signal generator configured to generate a first clock signal independent of an external clock signal received by the synchronous digital system; and
clock signal selector circuitry configured to:
select between a plurality of clock signals for use as the primary clock signal, wherein the plurality of clock signals comprises the first clock signal and a second clock signal dependent on the external clock signal;
select the first clock signal in response to a determination that a tamper detection signal indicates possible tampering with the synchronous digital system; and
select between the plurality of clock signals based at least in part on contents of a software-configurable register when the synchronous digital system has not determined that the tamper detection signal indicates possible tampering with the synchronous digital system.

US Pat. No. 10,129,601

SHARED SPECTRUM ACCESS FOR BROADCAST AND BI-DIRECTIONAL, PACKET-SWITCHED COMMUNICATIONS

Coherent Logix, Incorpora...

1. A broadcast base station, comprising:at least one radio transmitter;
one or more processors coupled to the at least one radio transmitter;
wherein the broadcast base station is configured to:
wirelessly broadcast a common set of audio and video data to a plurality of broadcast receiver devices using a particular frequency band, wherein the broadcast base station is not configured to receive content data from any of the broadcast receiver devices;
discontinue broadcasting in the particular frequency band during a scheduled time interval, to enable one or more cellular base stations to perform bi-directional packet-switched wireless data communications using the particular frequency band;
transmit control signaling during a pre-determined portion of the scheduled time interval, wherein the control signaling includes synchronization information to enable one or more broadcast receiver devices to remain connected to the broadcast base station during the scheduled time interval such that the receiver devices remain synchronized with the broadcast base station at the end of the scheduled time interval; and
resume broadcasting in the particular frequency band after the scheduled time interval and after use of the particular frequency band by one or more cellular base stations performing bi-directional packet-switched wireless data communications using the particular frequency band.

US Pat. No. 9,990,227

DYNAMIC RECONFIGURATION OF APPLICATIONS ON A MULTI-PROCESSOR EMBEDDED SYSTEM

Coherent Logix, Incorpora...

1. A method, comprising:loading a plurality of applications on a multiprocessor system, wherein the plurality of applications includes a first application and a plurality of other applications;
wherein the multiprocessor system includes a plurality of processors and a plurality of memories interspersed among the plurality of processors coupled together to form a first communication fabric, and a second communication fabric, wherein the second communication fabric includes a serial bus;
wherein loading the plurality of applications includes distributing instructions and data from the plurality of applications among different respective ones of the plurality of memories for execution by associated processors;
executing the plurality of applications on the multiprocessor system, wherein the plurality of applications executes together and communicates with each other to perform a real time operation, wherein executing the plurality of applications includes copying, from an input of an isolator cell, data that includes a plurality of data elements to an output of the isolator cell;
sending a command to a master task by a system controller via the serial bus included in the multiprocessor system;
initiating application swapping by the master task in response to receiving the command from a system controller; and
swapping the first application of the plurality of applications with a second application;
wherein swapping the first application with the second application includes continuing execution of each application of the plurality of other applications, and in response to determining the first application is upstream to the isolator cell, repeatedly sending, by the isolator cell, previously stored data from one or more buffers included in the isolator cell, to an application downstream of the isolator cell; and
wherein upon completion of the swapping, the plurality of other applications continues to execute with the second application, and wherein at least a subset of the plurality of other applications communicates with the second application to perform the real time operation.

US Pat. No. 9,900,364

MULTIMEDIA STREAMS WHICH USE CONTROL INFORMATION TO ASSOCIATE AUDIOVISUAL STREAMS

Coherent Logix, Incorpora...

1. A wireless device configured to wirelessly receive audiovisual information, the wireless device comprising:
a receiver configured to wirelessly receive a first stream, a separate second stream, and control information, wherein each
of the first stream and the second stream comprise audiovisual information, wherein each of the first stream and the second
stream comprise error correction coding information, wherein the control information indicates that the first stream and the
second stream are associated; and

receiver logic coupled to the receiver, wherein the receiver logic is configured to associate the first stream and the second
stream based on the control information indicating that the first stream and the second stream are associated.

US Pat. No. 9,720,867

PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS WITH MULTI-LAYER INTERCONNECTION

COHERENT LOGIX, INCORPORA...

1. An apparatus, comprising:
a plurality of processors;
a plurality of configurable communication elements coupled to the plurality of processors in an interspersed arrangement;
wherein each configurable communication element included in a subset of the plurality of configurable communication elements
is coupled to at least one processor of a subset of the plurality of processors, and is configured to selectively protect
at least some communication messages;

wherein to selectively protect the at least some communication messages, each configurable communication element of the subset
of the plurality of configurable communication elements is further configured to:

receive a message from a particular processor excluded from the subset of the plurality of processors; and
relay the message to another processor excluded from the subset of the plurality of processors dependent upon configuration
information.

US Pat. No. 9,973,301

MEMORY MANAGEMENT AND PATH SORT TECHNIQUES IN A POLAR CODE SUCCESSIVE CANCELLATION LIST DECODER

Coherent Logix, Incorpora...

10. A method for performing successive cancellation list (SCL) decoding on received encoded communication data, the method comprising:receiving the encoded communication data from a channel;
decoding the encoded communication data, by repetitively:
performing, by a plurality of processing elements comprised within a processor, decoding operations, wherein each processing element performs decoding operations on a respective bit path in a first list of bit paths, wherein each bit path is a potential decode of a portion of the encoded communication data, wherein the performing decoding operations comprises generating first bit statistics associated with bits in the bit paths;
sorting the first list of bit paths based on the first bit statistics;
determining to abandon a subset of the first list of bit paths based on the sorting of the first list of paths;
generating, from each bit path that was determined not to be abandoned, two lengthened bit paths, wherein the lengthened bit paths comprise a second list of bit paths; and
for each respective processing element associated with a bit path that was determined not to be abandoned:
copying, from a first memory associated with the respective processing element, to a second memory associated with a processing element associated with a second bit path that was determined to be abandoned, one of the lengthened bit paths and bit statistics associated with the respective processing element.

US Pat. No. 10,110,345

PATH SORT TECHNIQUES IN A POLAR CODE SUCCESSIVE CANCELLATION LIST DECODER

Coherent Logix, Incorpora...

1. A method for decoding encoded data, comprising:receiving the encoded data from a channel;
decoding the encoded data to obtain decoded data, wherein said decoding comprises: performing decoding operations and generating bit statistics on a plurality of bit paths, wherein each bit path is a potential decode of a portion of the encoded data;
creating a plurality of first new bit paths, wherein each of the plurality of first new bit paths comprises one of the plurality of bit paths with an added likely bit;
creating a plurality of second new bit paths, wherein each of the plurality of second new bit paths comprises one of the plurality of bit paths with an added unlikely bit value;
sorting a list of the plurality of first new bit paths and the plurality of second new bit paths based on the bit statistics, wherein said sorting comprises:
sorting a list of the plurality of first new bit paths in a first order to obtain a first sorted list;
sorting a list of the plurality of second new bit paths in a second different order to obtain a second sorted list; and
replacing one or more bit paths in the first sorted list with one or more bit paths from the second sorted list to obtain a third sorted list of bit paths; and
storing one of the bit paths from the third sorted list of bit paths in a memory as the decoded data.

US Pat. No. 9,965,258

PROGRAMMING A MULTI-PROCESSOR SYSTEM

Coherent Logix, Incorpora...

1. A computer-implemented method, comprising:creating a program for a multi-processor system, wherein the multi-processor system comprises an array of processors and a plurality of memories coupled to the processors, wherein the plurality of memories are interspersed among the plurality of processors within an apparatus, wherein each of the processors is coupled to at least one other processor, and wherein the creating includes:
creating machine language instructions based on source code, wherein the machine language instructions are designed to execute on the array of processors, wherein the source code specifies first functionality, and wherein the source code specifies a plurality of tasks and communication of data among the plurality of tasks;
selecting communication mechanisms between tasks to perform at least a portion of the specified communication of data, wherein the communication mechanisms include shared local variables and message passing pathways, wherein the message passing pathways are via a plurality of communications units coupled to processors in the array of processors;
using dependency information to detect potential conflicts for communication resources between messages;
selecting or adjusting the message passing pathways to send potentially conflicting messages using different hardware routing resources, thereby avoiding conflicts for communication resources;
determining an assignment of tasks to respective processors in the multi-processor system based on the selected communication mechanisms, including assigning tasks that use one or more shared local variables to different first and second processors that neighbor a shared memory and are both configured to access the shared memory, wherein the shared memory is selected to store the one or more shared local variables; and
storing the machine language instructions in various ones of the plurality of memories, wherein the multi-processor system is operable to execute the machine language instructions using the local variables and the message passing pathways to implement the first functionality.

US Pat. No. 10,383,106

SCRAMBLING SEQUENCE DESIGN FOR EMBEDDING UE ID INTO FROZEN BITS FOR DCI BLIND DETECTION

Coherent Logix, Incorpora...

1. A base station comprising:a radio; and
a processing element coupled to the radio;
wherein the radio and the processing element are configured to:
represent user equipment (UE)-specific control information as a plurality of frozen bits and a plurality of information bits of a polar code;
modulate at least a subset of the plurality of frozen bits based on a UE-specific identifier to produce modulated control information, wherein at least the subset of the plurality of frozen bits are selected for modulation whereby at least the subset of the plurality of frozen bits occur within the control information after an information bit with a predetermined threshold level of reliability, wherein the plurality of information bits of the control information is not modulated based on the UE-specific identifier;
encode the modulated control information using the polar code to obtain encoded modulated control information; and
wirelessly transmit the encoded modulated control information.

US Pat. No. 10,185,608

PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS WITH MULTI-LAYER INTERCONNECTION

Coherent Logix, Incorpora...

1. An apparatus, comprising:a plurality of processors; and
a plurality of configurable communication elements coupled to the plurality of processors in an interspersed arrangement, wherein a particular configurable communication element of the plurality of configurable communication elements is coupled to at least one processor of the plurality of processors, and wherein the particular configurable communication element is configured to:
receive one or more messages from the at least one processor; and
forward the one or more messages to a different configurable communication element of the plurality of configurable communication elements via one or more other configurable communication elements of the plurality of configurable communication elements; and
wherein a given one of the one or more other configurable communication elements is configured to receive at least part of the one or more messages.

US Pat. No. 10,185,672

MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK

Coherent Logix, Incorpora...

1. A multichip system, comprising:a first integrated circuit chip including:
a first plurality of processors;
a plurality of memories;
a first plurality of routers coupled together to form a first primary interconnection network;
a plurality of interface units coupled together to form a secondary interconnection network, wherein each interface unit is coupled to a respective processor of the first plurality of processors and a respective router of the first plurality of routers;
a bus controller coupled to at least a particular interface unit of the plurality of interface units;
wherein the first plurality of processors, the plurality of memories, and the first plurality of routers are coupled together in an interspersed fashion; and
a second integrated circuit chip coupled to the first integrated circuit chip via an inter-chip interconnect, wherein the second integrated circuit chip includes a second plurality of processors;
wherein a particular processor of the second plurality of processors is configured to send first data, via the inter-chip interconnect, to the bus controller; and
wherein the bus controller is configured to:
relay the first data to the particular interface unit; and
arbitrate requests for access to the particular interface unit from a plurality of circuit blocks.

US Pat. No. 10,206,126

PARAMETERIZED RADIO WAVEFORM TECHNIQUES FOR OPERATING IN MULTIPLE WIRELESS ENVIRONMENTS

Coherent Logix, Incorpora...

1. A method, comprising:transmitting, by a first broadcast transmitter, a first parameter value set, wherein the first parameter value set is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of receiver devices or a first target range of wireless transmission;
wherein, for each of two or more parameters, each of the parameter value sets in the group includes a corresponding value, wherein the two or more parameters include one or more parameters based upon which a receiver device is configured to determine subcarrier spacing and one or more parameters that indicate a cyclic prefix size;
wherein the first parameter value set enables reconfiguration of the receiver device to receive wireless broadcast communications from the first broadcast transmitter using the first parameter value set;
transmitting, by the first broadcast transmitter, wireless broadcast communications using the first parameter value set;
transmitting, by a second broadcast transmitter, a second parameter value set selected from a group of multiple parameter value sets, wherein the second parameter value set is appropriate for a second target radio operating environment that corresponds to one or more of: a second, different level of mobility of receiver devices or a second, different target range of wireless transmission;
wherein the second parameter value set enables reconfiguration of one or more receiver devices to receive wireless broadcast communications from the second broadcast transmitter using the second parameter value set; and
transmitting, by the second broadcast transmitter, wireless broadcast communications using the second parameter value set;
wherein the two or more parameters specify both sampling rate and frequency transform size and wherein the first parameter value set specifies a first frequency transform size and the second parameter value set specifies a second, smaller frequency transform size.

US Pat. No. 10,425,673

GENERATING CONTROL INFORMATION FOR USE IN TRANSMISSION WITH A MULTIMEDIA STREAM TO AN AUDIOVISUAL DEVICE

Coherent Logix Incorporat...

1. A method for generating control information for use in transmission of a data stream to a wireless receiver device, the method comprising:generating first control information, wherein the first control information is for configuring the receiver device to decode a wirelessly received data stream, wherein the first control information is generated according to a first protocol version parameter and a first physical layer parameter;
generating first data, wherein the first data includes said first protocol version parameter and said first physical layer parameter indicating a physical layer structure of the first control information;
transmitting the first control information, the first data, and a first plurality of packets that include information specifying at least one data stream;
generating second control information, wherein the second control information is for configuring the receiver device to decode a data stream, wherein the second control information is generated according to a second protocol version parameter and a second physical layer parameter indicating a physical layer structure of the second control information;
generating second data, wherein the second data includes said second protocol version parameter and said second physical layer parameter indicating a structure of the second control information, wherein a value of said second physical layer parameter is different than a value of said first physical layer parameter, and wherein the physical layer structure of the second control information is different than the physical layer structure of the first control information; and
transmitting the second control information, the second data, and a second plurality of packets that include information specifying at least one data stream.

US Pat. No. 10,425,462

MULTIMEDIA STREAMS WHICH USE CONTROL INFORMATION TO ASSOCIATE AUDIOVISUAL STREAMS

Coherent Logix Incorporat...

1. A wireless device, comprising:an antenna; and
receiver logic,
wherein the antenna and the receiver logic are configured to:
receive control information indicating that a first stream and a second stream are associated;
receive the first stream, wherein the first stream comprises audiovisual information and forward error correction;
receive the second stream, wherein the second stream comprises audiovisual information and forward error correction,
wherein the audiovisual information comprised in the first stream and the audiovisual information comprised in the second stream are at least partially complementary; and
associate the first stream and the second stream based at least in part on the control information.

US Pat. No. 10,560,932

SCRAMBLING SEQUENCE DESIGN FOR EMBEDDING RECEIVER ID INTO FROZEN BITS FOR BLIND DETECTION

COHERENT LOGIX, INCORPORA...

1. A transmitter comprising:a radio; and
a processor coupled to the radio;
wherein the radio and the processor are configured to:
represent receiver-specific control information as a plurality of frozen bits and a plurality of information bits of a polar code;
modulate at least a subset of the plurality of frozen bits based on a receiver-specific identifier to produce modulated control information, wherein at least the subset of the plurality of frozen bits are selected for modulation whereby at least the subset of the plurality of frozen bits occur within the control information after an information bit with a predetermined threshold level of reliability, wherein the plurality of information bits of the control information is not modulated based on the receiver-specific identifier;
encode the modulated control information using the polar code to obtain encoded modulated control information; and
wirelessly transmit the encoded modulated control information.

US Pat. No. 10,560,299

MULTI-PORTION RADIO TRANSMISSIONS

COHERENT LOGIX, INCORPORA...

1. An apparatus, comprising:one or more processing elements configured to:
receive, via a wireless radio, a transport frame of broadcast wireless data that includes:
a plurality of portions, wherein different ones of the portions encode different types of video content; and
control data that indicates the types of video content encoded by the ones of the portions;
select, based on the control data and whether the apparatus is a fixed or mobile device, one or more of the plurality of portions; and
decode the selected one or more portions to determine data represented by symbols in the selected one or more portions.

US Pat. No. 10,567,971

BROADCAST/BROADBAND CONVERGENCE NETWORK

COHERENT LOGIX, INCORPORA...

1. A spectrum server for allocating available broadcast spectrum resources under carrier aggregation, the spectrum server comprising:one or more processors, and
a memory storing program instructions that when executed by the one or more processors, cause the one or more processors to perform operations including:
querying a broadcast exchange server representing one or more broadcast networks for information indicative of available broadcast spectrum;
in response to said querying, receiving the information indicative of the available broadcast spectrum from the broadcast exchange server, wherein, for each of a plurality of frequency bands in a regulatory domain, the information indicates available or non-available status of each channel in a set of channels corresponding to the frequency band;
combining a contiguous group of the channels that are of available status, to form a contiguous band;
assigning a contiguous portion of the contiguous band to a wireless broadband network in response to a request from an entity representing the wireless broadband network, wherein said assigned contiguous portion is defined by an interval of resource block numbers, wherein the resource block numbers correspond to a partition of the contiguous band into resource blocks of fixed width, wherein the resource block numbers are consecutively numbered, in order of frequency; and
transmitting a message to the entity representing the wireless broadband network, wherein the message identifies the interval of resource block numbers by its endpoints, wherein the message also indicates a period of time that said contiguous portion is assigned.

US Pat. No. 10,567,981

PARAMETERIZED RADIO WAVEFORM TECHNIQUES FOR OPERATING IN MULTIPLE WIRELESS ENVIRONMENTS

COHERENT LOGIX, INCORPORA...

1. An apparatus, comprising:one or more processors; and
one or more memory elements having program instructions stored thereon that are executable by the one or more processors to:
receive a first parameter value set from a broadcast transmitter of a wireless network, wherein the first parameter value set is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first target range of wireless transmission;
wherein, for each of two or more parameters, each of the parameter value sets in the group includes a corresponding value, wherein the two or more parameters include one or more parameters based upon which the apparatus is configured to determine subcarrier spacing and one or more parameters that indicate a cyclic prefix size;
reconfigure the apparatus to receive wireless broadcast transmissions from the broadcast transmitter using the first parameter value set;
receive wireless broadcast transmissions from the broadcast transmitter and decode the received wireless broadcast transmissions from the broadcast transmitter using the first parameter value set;
receive a second parameter value set selected from a group of multiple parameter value sets from the broadcast transmitter, wherein the second parameter value set is appropriate for a second target radio operating environment that corresponds to one or more of: a second, different level of mobility of user devices or a second, different target range of wireless transmission;
reconfigure the apparatus to receive wireless broadcast transmissions from the broadcast transmitter using the second parameter value set; and
receive wireless broadcast transmissions from the broadcast transmitter and decode the received wireless broadcast transmissions from the broadcast transmitter using the second parameter value set;
wherein the two or more parameters specify both sampling rate and frequency transform size and wherein the first parameter value set specifies a first frequency transform size and the second parameter value set specifies a second, smaller frequency transform size.

US Pat. No. 10,536,305

SCRAMBLING SEQUENCE DESIGN FOR MULTI-MODE BLOCK DISCRIMINATION ON DCI BLIND DETECTION

COHERENT LOGIX, INCORPORA...

1. A user equipment (UE) configured to wirelessly communicate with a base station, the UE comprising:a radio; and
a processor operably coupled to the radio, wherein the UE is configured to:
determine whether a downlink message was successfully received from the base station;
based on the determination whether the downlink message was successfully received, modulate a plurality of frozen bits of a polar code based on a hybrid automatic repeat request (HARQ) acknowledgment message to produce a plurality of modulated frozen bits;
encode, using a polar code, the plurality of modulated frozen bits and a plurality of information bits to obtain an encoded HARQ acknowledgment message; and
wirelessly transmit the encoded HARQ acknowledgment message to the base station.

US Pat. No. 10,521,285

PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS WITH MULTI-LAYER INTERCONNECTION

COHERENT LOGIX, INCORPORA...

1. An apparatus, comprising:a plurality of processors;
a plurality of communication circuits coupled to the plurality of processors in an interspersed arrangement, wherein each one of the plurality of communication circuits is coupled to a plurality of interconnection networks, and wherein a particular one of the plurality of communication circuits is configured to:
receive a message that includes one or more data words via a particular interconnection network of the plurality of interconnection networks; and
forward the message, based on routing information included in the message, to another communication circuit of the plurality of communication circuits using a different one of the plurality of interconnection networks.