US Pat. No. 9,256,121

MASK PLATE AND A METHOD FOR PRODUCING A SUBSTRATE MARK

Boe Technology Group Co.,...

1. A mask plate comprising:
a display region mask part;
at least one pair of test mark mask parts, a test mark mask part of the pair of test marks mask parts being located on either
side of the display region mask part respectively and the two test mark mask parts' positions being opposite to each other;
and

a protection mark mask part correspondingly disposed on the outside of each test mark mask part relative to the display region
mask part, wherein the pattern outline of the protection mark mask part is larger than that of the test mark mask part.

US Pat. No. 9,311,869

DISPLAY SYSTEM

BOE Technology Group Co.,...

1. A display system, comprising at least one jointed screen which is composed of a plurality of liquid crystal display panels
jointed with each other, in which:
each liquid crystal display panel is provided with a first polarizer only at a light entering side thereof, so that a visible
angle at which contents displayed by the liquid crystal display panel can be seen from a light exiting side of the liquid
crystal display panel is an obtuse angle;

two adjacent jointed liquid crystal display panels are jointed with each other at their adjacent sides, and a joint angle
formed at the light exiting side is greater than a right angle, such that the light exiting side of each liquid crystal display
panel is located in a region covered by an angle range of the visible angle of at least one liquid crystal display panels
other than said liquid crystal display panel.

US Pat. No. 9,256,298

DISPLAY PANEL AND OPERATION CONTROL METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display panel comprising a bendable flexible substrate, and further comprising a sensor control circuit and a sensitive
element provided on the flexible substrate, the sensor control circuit being connected to the sensitive element;
a sensitive parameter of the sensitive element varies with a bending degree of the flexible substrate so that a detected signal
passing through the sensitive element varies with the bending degree of the flexible substrate;

the sensor control circuit including a signal generating circuit and a feedback circuit,
wherein,
the signal generating is used for inputting the detected signal into the sensitive element;
the feedback circuit is used for converting the detected signal passing through the sensitive element into a feedback signal
indicating the bending degree of the flexible substrate and for sending it to a control system connected to the display panel,
so that the control system performs corresponding control operations in accordance with the feedback signal,

wherein, at least two second pins are provided on the sensor control circuit, and the two pins are respectively connected
to two terminals of the sensitive element.

US Pat. No. 9,240,485

THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor comprising:
a substrate;
a gate electrode, a source electrode, a drain electrode and a semiconductor layer formed on the substrate;
a gate insulating layer between the gate electrode and the semiconductor layer or between the gate electrode and the source
and drain electrodes;

an etching stop layer between the semiconductor layer and the source and drain electrodes having a source contact hole and
a drain contact hole therein; and

a source buffer layer between the source electrode and the semiconductor layer and a drain buffer layer between the drain
electrode and the semiconductor layer,

wherein the source and drain electrodes are metal Cu electrodes, and the source and drain buffer layers are Cu alloy layer;
wherein the source buffer layer directly contacts the etching stop layer, and the drain buffer layer directly contacts the
etching stop layer; the source buffer layer directly contacts the source electrode, and the drain buffer layer directly contacts
the drain electrode.

US Pat. No. 9,311,852

PIXEL CIRCUIT AND ORGANIC LIGHT-EMITTING DISPLAY COMPRISING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A pixel circuit comprising a driving thin film transistor and a light-emitting diode, wherein the light-emitting diode
and the driving thin film transistor are connected between a low level input terminal and a high level input terminal of a
driving power supply in series, wherein the pixel circuit further comprises a first capacitor and a driving control unit,
and wherein the driving control unit is connected with a gate line and a data line and comprises a second driving control
transistor and a third driving control transistor, wherein
a gate of the second driving control transistor is connected with the gate line, a first electrode of the second driving control
transistor is connected with the second electrode of the driving thin film transistor, a second electrode of the second driving
control transistor is connected with the gate of the driving thin film transistor,

a gate of the third driving control transistor is connected with the gate line, a first electrode of the third driving control
transistor is connected with a first terminal of the first capacitor, and a second electrode of the third driving control
transistor is connected with the first electrode of the driving thin film transistor,

during a data writing stage, the third driving control transistor is turned on so as to connect the first terminal of the
first capacitor to the first electrode of the driving thin film transistor and connect the gate of the driving thin film transistor
to the second electrode of the driving thin film transistor, such that the driving thin film transistor is turned on.

US Pat. No. 9,310,659

COLORFUL LIQUID CRYSTAL THIN FILM, METHOD OF MANUFACTURING THEREOF AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method of manufacturing a colorful liquid crystal thin film, comprising:
adjusting a voltage applied across a liquid crystal cell filled with a blue phase liquid crystal until the liquid crystal
cell shows a first required color;

radiating a first portion of the liquid crystal cell needed to show the first required color by a mercury lamp and then radiating
the first portion of the liquid crystal cell needed to show the first required color by ultraviolet rays, while the voltage
is maintained across the liquid crystal cell, a pitch of the blue phase liquid crystal in the first portion of the liquid
crystal cell being adjusted and fixed accordingly;

suspending applying the voltage across the liquid crystal cell until a remaining portion of the liquid crystal cell returns
to a clear state, while the first portion of the liquid crystal cell shows the first required color;

reapplying and adjusting the voltage across the liquid crystal cell until the remaining portion of the liquid crystal cell
shows a second required color, while the first portion of the liquid crystal cell shows the first required color; and

radiating a second portion of the liquid crystal cell needed to show the second required color by ultraviolet rays, the second
portion being at least part of the remaining portion of the liquid crystal cell.

US Pat. No. 9,245,876

LIGHT EMITTING DIODE ASSEMBLY, BACKLIGHT MODULE, LIQUID CRYSTAL DISPLAY AND ILLUMINATION DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An LED assembly, comprising:
a lamp base, a central portion of the lamp base being inwardly concave to form a mounting groove;
at least one pair of LED dies, wherein each pair of LED dies is mounted on a bottom surface of the mounting groove, two LED
dies in each pair of LED dies are disposed symmetrically about an axis of the mounting groove, light exit surfaces of the
two LED dies are opposite to the bottom surface of the mounting groove, and among angles formed by intersection of planes
where the light exit surfaces of the two LED dies lie, an angle facing the bottom surface of the mounting groove is greater
than 0 degree and less than 180 degrees.

US Pat. No. 9,312,286

DISPLAY DEVICE HAVING BYPASS ELECTRODE ON COMMON ELECTRODE IN PERIPHERAL CIRCUIT OF COLOR FILTER SUBSTRATE

BOE TECHNOLOGY GROUP CO.,...

1. A display device, comprising an array substrate and a color filter substrate, the array substrate comprising data lines
in a periphery circuit area, and the color filter substrate comprising a common electrode; wherein a portion of the common
electrode of the color filter substrate corresponding to the periphery circuit area of the array substrate comprises a plurality
of stripe electrodes separated from each other, extending in a length direction of the data lines and overlapped with the
data lines; for each data line, two adjacent stripe electrodes among the plurality of stripe electrodes overlapped with the
data line are connected through a bypass electrode which is not overlapped with the data line.

US Pat. No. 9,477,347

TOUCH SCREEN AND TOUCH DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A touch screen, which comprises a plurality of common electrodes, a plurality of driving electrodes and a plurality of
sensing electrodes, the common electrodes and the driving electrodes are alternately provided in the same layer, the common
electrodes, the driving electrodes and the sensing electrodes are insulated from each other, wherein
the sensing electrodes are correspondingly provided in an orthographic projection direction of the common electrodes, each
of the sensing electrodes includes a plurality of electrode strips, and distribution densities of the electrode strips in
edge regions adjacent to the driving electrodes are larger than that in a center region far away from the driving electrodes.

US Pat. No. 9,239,503

ARRAY SUBSTRATE AND DISPLAY DEVICE INCLUDING PIXEL UNITS WITH MULTIPLE DISPLAY REGIONS

BOE Technology Group Co.,...

1. An array substrate, comprising a base substrate, a plurality of gate lines and a plurality of data lines formed on the
base substrate, and a plurality of pixel units defined by the plurality of gate lines and the plurality of data lines intersecting
with each other, wherein:
each pixel unit is driven by a same gate line and a same data line;
each pixel unit includes a thin film transistor structure and at least two display regions, each display region includes a
pixel electrode, the thin film transistor structure drives the pixel electrodes in the at least two display regions simultaneously
and causes voltages applied on the pixel electrodes in the at least two display regions different from one another;

the thin film transistor structure is a composite thin film transistor that includes a gate electrode, a common source electrode,
two drain electrodes, and two channels formed respectively between the common source electrode and the two drain electrodes;
and

the two channels formed respectively between the common source electrode and the two drain electrodes are different from each
other in channel width.

US Pat. No. 9,313,924

HEAT SINKING PAD AND PRINTED CIRCUIT BOARD

BOE TECHNOLOGY GROUP CO.,...

1. A heat sinking pad, a surface of the heat sinking pad on which electronic components are placed comprising a solder loading
area used for being coated with solder and a solder non-loading area, wherein
the solder non-loading area comprises heat collection passages for collecting heat on the heat sinking pad and heat dissipation
passages communicated with the heat collection passages, and openings of the heat dissipation passages are positioned at edges
of the heat sinking pad so as to discharge the heat collected by the heat collection passages to outside of the heat sinking
pad.

US Pat. No. 9,310,639

LIQUID CRYSTAL DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A liquid crystal display panel comprising an array substrate, an opposite substrate and a backlight module, wherein the
liquid crystal display panel includes a light-filtering layer arranged between the backlight module and the array substrate,
the light-filtering layer includes a plurality of light-filtering sub-units corresponding in a one-to-one manner to sub-pixels
on the array substrate, every three of the light-filtering sub-units form one light-filtering unit in which the three light-filtering
sub-units are capable of filtering out red light, green light and blue light from light emitted by the backlight module, respectively.

US Pat. No. 9,310,616

3D DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

9. A manufacturing method of a 3D-OLED display device, comprising:
on a lower substrate, forming a control-circuit;
on the lower substrate formed with the control-circuit, forming an EL layer, wherein, the EL layer comprises a metal cathode,
a pixel-electrode configured for an anode and an organic light-emitting material located between the metal cathode and the
pixel-electrode; the pixel-electrode of each pixel-unit comprises mutually-spaced at least two left-viewing-field pixel-electrodes
and at least two right-viewing-field pixel-electrodes; the control-circuit of each pixel-unit comprises a first sub-control-circuit
connected with the left-viewing-field pixel-electrodes and a second sub-control-circuit connected with the right-viewing-field
pixel-electrodes, and a width of the left-viewing-field pixel-electrodes is different from that of the right-viewing-field
pixel-electrodes;

on an encapsulation layer, forming a grating layer, the grating layer comprising a parallax barrier or a lens-grating; and
disposing the encapsulation layer formed with the grating layer to cover the lower substrate.

US Pat. No. 9,240,422

TFT ARRAY SUBSRATE, FABRICATION METHOD, AND DISPLAY DEVICE THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A TFT array substrate, comprising: a plurality of gate lines, a plurality of data lines, a plurality of pixel units defined
by the gate lines and the data lines, wherein each pixel unit comprises: a common electrode line and a pixel electrode, and
a gate insulating layer as well as a passivation layer formed in this order between the common electrode line and the pixel
electrode; wherein in each pixel unit, a backup common electrode line is disposed at a position between the gate insulating
layer and the passivation layer and opposite to the common electrode line; and the backup common electrode line is electrically
insulated from the data line.

US Pat. No. 9,307,684

LIQUID CRYSTAL DISPLAY PANEL COMPRISING AT LEAST ONE SHIELDING LAYER HAVING OPENINGS POSITIONED ABOVE A PLURALITY OF SIGNAL LEADS

BOE TECHNOLOGY GROUP CO.,...

1. A liquid crystal display (LCD) panel having a display region and a periphery region and comprising an array substrate and
a color filter substrate opposite to each other, wherein the array substrate comprises a plurality of pixel regions defined
by intersecting signal lines in the display region, each pixel region comprises a thin film transistor, and signal leads are
disposed in the periphery region and connected to the signal lines; the LCD panel further comprising:
at least one shielding layer located in the periphery region, which is grounded and electrically conductive,
wherein, the at least one shielding layer is formed on the array substrate and covers at least part of the signal leads, and
an insulating layer is disposed between the at least one shielding layer and the signal leads; and

wherein openings are positioned in the at least one shielding layer above at least the signal leads.

US Pat. No. 9,282,613

PIXEL UNIT DRIVING CIRCUIT AND DRIVING METHOD, PIXEL UNIT AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A pixel unit driving circuit for driving a light-emitting device to emit light, comprising a first thin film transistor,
a second thin film transistor, a third thin film transistor and a storage capacitor, wherein the first to third thin film
transistors comprise gates, first electrodes and second electrodes;
the gate of the first thin film transistor is connected with a control line, the first electrode thereof is connected with
a data line, and the second electrode thereof is connected with a first node;

the second thin film transistor has two gates, one gate thereof is connected with the control line and another gate is connected
with a second scan line, the first electrode thereof is connected with the storage capacitor, and the second electrode thereof
is connected with a second node;

the third thin film transistor has two gates, one gate thereof is connected with the first node and another gate is connected
with the second scan line, the first electrode thereof is connected with a power supply, and the second electrode thereof
is connected with the second node;

one terminal of the storage capacitor is connected with the first node, and the other terminal thereof is connected with the
first electrode of the second thin film transistor;

one terminal of the light-emitting device is connected with the second node, and the other terminal thereof is grounded, and
wherein the second node is a node formed by directly connecting the three terminals of the second electrode of the second
thin film transistor, the second electrode of the third thin film transistor and one terminal of the light-emitting device
together.

US Pat. No. 9,273,248

BLUE PHASE LIQUID CRYSTAL COMPOSITE MATERIAL AND LIQUID CRYSTAL DISPLAY CONTAINING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A blue phase liquid crystal composite material formed by photopolymerization of material components comprising a parent
blue phase liquid crystal, a photo-polymerizable monomer, a photoinitiator, and inorganic nanoparticles, wherein the photo-polymerizable
monomer is a non-liquid crystal acrylate monomer, and the non-liquid crystal acrylate monomer is a mixture of mono-functional
monomers and multi-functional monomers, wherein the molar ratio of the mono-functional monomers to the multi-functional monomers
are 1:1-1:9 in the non-liquid crystal acrylate monomer.

US Pat. No. 9,246,329

ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. An electrostatic discharge protection circuit comprising: a first depletion mode thin-film transistor, a second depletion
mode thin-film transistor, a third depletion mode thin-film transistor and a voltage dividing unit, wherein
the first thin-film transistor has a drain connected to a first level line without intervention of any transistor, a gate
connected to a signal line, and a source connected to a gate of the second thin-film transistor and the voltage dividing unit
without intervention of any transistor;

the second thin-film transistor has a drain connected to the first level line, the gate connected to the source of the first
thin-film transistor, and a source connected to the signal line;

the third thin-film transistor has a drain connected to the signal line, a source connected to a second level line, and a
gate connected to a third level line; and

the voltage dividing unit is connected to the source of the first thin-film transistor and the second level line without intervention
of any transistor,

wherein the signal line, the first level line, the second level line, and the third level line are different from each other,
the third level line is not connected to the voltage dividing unit, and electrostatic charges on the signal line are discharged
to the first level line or the second level line according to a polarity of the electrostatic charges on the signal line.

US Pat. No. 9,310,053

LIGHT MIXING ELEMENT, LIGHT GUIDE PLATE, BACKLIGHT MODULE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A backlight module (BLM) of a display device, comprising: light sources, a plurality of light guide plates, and a plurality
of light mixing elements, disposed between every two adjacent light guide plates, wherein
each light mixing element, in a shape of prism, a cylinder of the prism of the light mixing element including:
a light mixing element first light-emitting inclined surface;
a light mixing element second light-emitting inclined surface, of which one side is connected with one side of the light mixing
element first light-emitting inclined surface to form a top angle;

a bottom surface arranged opposite to the top angle formed by the light mixing element first light-emitting inclined surface
and the light mixing element second light-emitting inclined surface;

a light mixing element incident surface connected between one side of the bottom surface and the other side of the light mixing
element first light-emitting inclined surface; and

a reflecting inclined surface connected between the other side of the bottom surface and the other side of the light mixing
element second light-emitting inclined surface and arranged opposite to the light mixing element incident surface and the
light mixing element first light-emitting inclined surface;

the light sources are arranged opposite to the light mixing element incident surfaces of the light mixing elements;
a cross section of each light guide plate takes a shape of a trapezoid, of which the upper bottom is downwards; surfaces,
on which two sides of the trapezoid are disposed, are respectively a light guide plate first incident inclined surface and
a light guide plate second incident inclined surface provided respectively corresponding to the light mixing element first
light-emitting inclined surface of one light mixing element and the light mixing element second light-emitting inclined surface
of the other light mixing element;

in two adjacent light mixing elements, a light mixing element first light-emitting inclined surface of one light mixing element
and a light mixing element second light-emitting inclined surface of the other light mixing element are respectively adhered
to a light guide plate first incident inclined surface and a light guide plate second incident inclined surface of one light
guide plate disposed between the two adjacent light mixing elements; and vertexes of top angles of the two light mixing elements
abut against vertexes of two base angles of the light guide plate respectively.

US Pat. No. 9,281,325

ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method of manufacturing an array substrate, wherein, a common electrode and a pixel electrode are formed at the same
time through a single process; comprising:
sequentially forming a gate metal layer and a gate insulating layer on a base substrate, the gate metal layer comprising patterns
of a gate electrode and a gate line;

forming a pattern of an active layer on the substrate formed with the gate insulating layer;
forming patterns of a data line, a source electrode and a drain electrode on the substrate formed with the active layer, and
forming a pattern of a conductive layer having at least one slit in a pixel region;

forming a pattern of a passivation layer on the substrate formed with the data line, the source electrode, the drain electrode
and the conductive layer, the passivation layer having a passivation layer slit in a one-to-one correspondence with the slit
in the conductive layer;

forming a transparent conductive layer on the substrate formed with the passivation layer, the transparent conductive layer
comprising two layers, one of which is formed over the passivation layer to form a common electrode, and the other of which
is located in the slit region, in the same layer as and electrically connected to the conductive layer to form a pixel electrode.

US Pat. No. 9,252,166

CAPACITOR FOR TFT ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DEVICES ASSOCIATED WITH THE SAME

BOE Technology Group Co.,...

1. A capacitor for a TFT array substrate, the TFT array substrate comprising a TFT gate layer, a gate insulation layer, a
first ITO layer, a TFT active layer, a TFT source-drain layer, a passivation layer and a second ITO layer formed sequentially
on a substrate comprising a display region and a non-display region, wherein the capacitor is formed by portions of the TFT
gate layer, the gate insulation layer, the first ITO layer, the passivation layer and the second ITO layer within the non-display
region.

US Pat. No. 9,398,685

FLEXIBLE DEVICE CARRIER AND METHOD FOR ATTACHING MEMBRANE ON FLEXIBLE DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A flexible device carrier for a flexible display panel, comprising:
a bottom plate;
a position-limiting plate provided opposite to the bottom plate and detachably mounted on the bottom plate through a position-limiting
mechanism, wherein a slotted hole is provided on the position-limiting plate to match with one side of the bottom plate facing
the position-limiting plate, so as to form a positioning groove for the flexible device.

US Pat. No. 9,230,811

ACTIVE LAYER ION IMPLANTATION METHOD AND ACTIVE LAYER ION IMPLANTATION METHOD FOR THIN-FILM TRANSISTOR

BOE TECHNOLOGY GROUP CO.,...

1. An active layer ion implantation method for TFT comprising:
applying a photoresist on an active layer; and
exposing the photoresist using a TFT source/drain electrode mask for forming the TFT source/drain electrode pattern to form
a photoresist completely retained region and a photoresist partially retained region;

wherein an exposed region of the TFT source/drain electrode mask corresponds to the photoresist-partially-retained region
and a graphics region of the TFT source/drain electrode mask corresponds to the photoresist-completely-retained region; and

implanting ions into a first region of the active layer that corresponds to a TFT channel region through the photoresist-partially
retained region, wherein the photoresist-partially-retained region has a thickness designed to allow the ions to pass through
the photoresist-partially-retained region and the photoresist completely retained region has a thickness designed to prevent
the ions from passing through the photoresist completely retained region.

US Pat. No. 9,281,326

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing an array substrate, wherein the array substrate includes a plurality of thin film transistors,
and the method for manufacturing an array substrate includes steps of:
preparing a base substrate, on which sources and drains of thin film transistors are formed;
forming an insulation layer on the base substrate, so that the insulation layer includes a plurality of spacer regions and
a plurality of strip-shaped electrode regions, and every two adjacent strip-shaped electrode regions are separated from each
other by the spacer region;

forming a spacer layer on the spacer regions of the insulation layer;
forming a pattern including strip-shaped electrodes on the strip-shaped electrode regions of the insulation layer; and
peeling off the spacer layer on the spacer region.

US Pat. No. 9,201,445

GATE DRIVING CIRCUIT FOR THIN FILM TRANSISTOR LIQUID CRYSTAL DISPLAY AND THIN FILM TRANSISTOR LIQUID CRYSTAL DISPLAY

BOE Technology Group Co.,...

1. A gate driving circuit comprising a plurality of shift register connected in cascade, the shift register comprising:
a signal outputting circuit which receives a forward direction clock signal from an external circuit and comprises a clock
transistor and a level transistor, wherein the signal outputting circuit outputs the forward direction clock signal when the
clock transistor is turned on and outputs a constant-low level signal when the level transistor is turned on;

a signal inputting circuit which is connected to a gate of the clock transistor and receives an output signals from a previous
shift register, and turns on the clock transistor when the received output signal of the previous shift register is valid;

an inverting circuit which is connected to the gate of the clock transistor and a gate of the level transistor, and receives
an inverse direction clock signal from the external circuit, wherein the inverting circuit turns off the clock transistor
and turns on the level transistor at the same time when the inverse direction clock signal is valid;

a logic circuit which is connected to the clock transistor and holds the clock transistor as being turned on before the level
transistor is turned on.

US Pat. No. 9,262,966

PIXEL CIRCUIT, DISPLAY PANEL AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A pixel circuit comprising a charging sub-circuit, a first driving sub-circuit, a second driving sub-circuit, a first capacitor
and a second capacitor, wherein
a first terminal of the first capacitor is connected to a first terminal of the first driving sub-circuit and a first terminal
of the second driving sub-circuit, and a second terminal of the first capacitor is connected to the charging sub-circuit and
a first terminal of the second capacitor;

a second terminal of the first driving sub-circuit is connected to a first light emitting device, and a second terminal of
the second driving sub-circuit is connected to a second light emitting device, wherein the flow direction of the driving current
flowing into the first light emitting device from the first driving sub-circuit is opposite to that of the driving current
flowing into the second light emitting device from the second driving sub-circuit; and

the charging sub-circuit is used to charge the first capacitor, the second capacitor is used to maintain the voltage at the
second terminal of the first capacitor, and when the first capacitor discharges, the first driving sub-circuit drives the
first light emitting device to emit light or the second driving sub-circuit drives the second light emitting device to emit
light.

US Pat. No. 9,279,674

METHOD OF TESTING BLOCKING ABILITY OF PHOTORESIST BLOCKING LAYER FOR ION IMPLANTATION

BOE TECHNOLOGY GROUP CO.,...

1. A method of testing a blocking ability of a photoresist blocking layer for ion implantation, comprising:
forming a photoresist blocking layer on a substrate;
measuring a first thickness of the photoresist blocking layer at an arbitrary position on the substrate, the first thickness
being a thickness of the photoresist blocking layer;

implanting a predetermined amount of ions into the photoresist blocking layer;
measuring a second thickness of the photoresist blocking layer at the arbitrary position, the second thickness being a thickness
of a hardened portion in the photoresist blocking layer; and

determining blocking ability of the photoresist blocking layer with the first thickness for ion implantation based on the
second thickness.

US Pat. No. 9,052,515

LENS PANEL, METHOD FOR MANUFACTURING THE SAME AND 3D DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A lens panel, comprising:
a first transparent substrate;
a second transparent substrate, disposed opposite to the first transparent substrate;
positive electrodes and negative electrodes, which are in a strip shape, and disposed at a side of the first transparent substrate
opposed to the second transparent substrate parallel to each other and alternately;

a second transparent liquid and a first transparent liquid, filled between the first transparent substrate and the second
transparent substrate in this order from the second transparent substrate to the first transparent substrate, the first transparent
liquid and the second transparent liquid being immiscible, and reflectance of the first transparent liquid being larger than
reflectance of the second transparent liquid,

wherein the first transparent liguid is an optical fluid, and the optical fluid is liquid crystal or liquid polymer.

US Pat. No. 9,207,485

FLEXIBLE TRANSPARENT LIQUID CRYSTAL DISPLAY AND METHOD FOR PREPARING SAME

BOE TECHNOLOGY GROUP CO.,...

1. A flexible transparent liquid crystal display comprising: a first flexible substrate provided with a common electrode layer;
and a second flexible substrate provided with an array of pixel electrodes and thin film field effect transistors; wherein
at least one bi-stable state polymer dispersed liquid crystal layer is provided between the first flexible substrate and the
second flexible substrate.

US Pat. No. 9,366,797

SIDE TYPE BACKLIGHT MODULE, METHOD FOR PRODUCING THE SAME AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A side type backlight module, comprising:
a LED source;
a light guide plate;
a wedge-shaped light guide portion located between the LED source and the light guide plate;
two reflectors having reflective faces located on a top and a bottom of the wedge-shaped light guide portion and inclined
with respect to an upper surface or a lower surface of the light guide plate, for adjusting the light emitting angle of the
LED source; and

a silicon gel part located between the LED source and the wedge-shaped light guide portion,
wherein a notch extending in a width direction of the light guide plate is provided on a side of the wedge-shaped light guide
portion facing the LED source, the silicon gel part being provided in the notch.

US Pat. No. 9,285,646

DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display panel, comprising:
an optical component for reflecting light with a specific wavelength and transmitting other light; and
a first Guest Host (GH) liquid crystal cell and a second GH liquid crystal cell located at two opposite sides of the optical
component, the first GH liquid crystal cell and the second GH liquid crystal cell each comprising a plurality of pixel units
which have a first operation state and a second operation state, the pixel units transmitting natural light under the first
operation state and transmitting linearly polarized light under the second operation state,

wherein when the pixel units are under the second operation state, a polarization direction of the light reflected by the
optical component is substantially perpendicular to an extension direction of a polarization axis of the pixel units, thereby
achieving a dark state display.

US Pat. No. 9,276,233

ENCAPSULATING STRUCTURE OF OLED DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An encapsulating structure of an OLED device, comprising an upper substrate and a lower substrate that are disposed in
opposition to each other, an OLED device, and a frit wall for sealing peripheries of the upper substrate and the lower substrate;
wherein two faces of the upper substrate and the lower substrate that are opposed abut against each other, the lower substrate
has a recessed section, which is opened toward the upper substrate and within which the OLED device is positioned; the upper
substrate has a first annular groove that is opened toward the lower substrate, the lower substrate has a second annular groove
that is opposed to the first annular groove and opened toward the upper substrate, an upper bound of the frit wall is located
in the first annular groove, and a lower bound of the frit wall is located in the second annular groove.

US Pat. No. 9,281,282

SUBSTRATE CAPABLE OF ELECTROSTATIC SELF-PROTECTION AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A substrate capable of electrostatic self-protection, comprising:
a panel area, comprising a plurality of panel units each configured to form a display panel after splitting; and
a first gate metal layer and a source/drain metal layer disposed on at least one side of the panel area and disposed outside
of the plurality of panel units,

wherein the first gate metal layer and the source/drain metal layer are arranged parallel to each other in a longitudinal
direction and adjacent to each other; at least one tip is protruded from the first gate metal layer towards the source/drain
metal layer; and/or at least one tip is protruded from the source/drain metal layer towards the first gate metal layer.

US Pat. No. 9,280,017

LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

BOE Technology Group Co.,...

1. A liquid crystal display device, comprising: a liquid crystal panel and a first optical compensation structure and a second
optical compensation structure located at two sides of the liquid crystal panel respectively, the first optical compensation
structure comprises a first compensation film layer, a second compensation film layer and a first polarizing film layer located
between the first compensation film layer and the second compensation film layer, wherein, the second optical compensation
structure comprises: a polarizing film layer, a compensation film layer and a biaxial film layer, wherein,
the polarizing film layer is located between the compensation film layer and the biaxial film layer;
the biaxial film layer is located between the polarizing film layer and the liquid crystal panel;
wherein the second compensation film layer is located between the first polarizing film layer and the liquid crystal panel
and

wherein the in-plane direction phase difference of the second compensation film layer and the thickness direction phase difference
of the second compensation film layer are both 0 nm.

US Pat. No. 9,252,186

PIXEL ARRAY AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A pixel array, comprising a two-dimensional array that is formed by arranging a plurality of color sub-pixels and a plurality
of white sub-pixels in a row direction and in a column direction, the plurality of color sub-pixels include color sub-pixels
in three different colors, wherein,
in a same row, color sub-pixels with a same color lie in odd-numbered columns and even-numbered columns of the two-dimensional
array, respectively, so as to form odd-numbered column sub-pixels and even-numbered column sub-pixels;

for color sub-pixels with each color in each row, color sub-pixels with the same color in the same row are arranged so that,
the odd-numbered column sub-pixels and the even-numbered column sub-pixels alternate one by one, or they are disposed by way
of groups each including two odd-numbered column sub-pixels alternating with even-numbered column sub-pixels or by way of
groups each including two even-numbered column sub-pixels alternating with odd-numbered column sub-pixels.

US Pat. No. 9,244,304

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A display device, comprising:
an array substrate and a color filter substrate which are cell-assembled, the array substrate and the color filter substrate
being formed with two-dimensionally arranged sub-pixel regions correspondingly;

wall-shaped electrodes formed on the array substrate or the color filter substrate and interposed between the array substrate
and the color filter substrate, the wall-shaped electrodes separating a row of or a column of the sub-pixel regions to divide
each row or column of sub-pixel regions into two rows or two columns of sub-subpixel regions that form transmissive regions
and reflective regions respectively; and

a liquid crystal layer interposed between the array substrate and the color filter substrate and comprising transmissive region
liquid crystal and reflective region liquid crystal filled in the transmissive regions and the reflective regions,

wherein the transmissive region liquid crystal and the reflective region liquid crystal use different liquid crystal and light
of the transmissive region and the reflective region have a same optical path difference,

wherein difference of refractive index of the liquid crystal in the transmissive regions is two times that of the reflective
regions.

US Pat. No. 9,281,353

ORGANIC THIN FILM TRANSISTOR ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An organic thin film transistor array substrate, comprising a pixel structure formed on a transparent substrate, wherein
the pixel structure includes: a gate line, a data line, an organic thin film transistor, a pixel electrode, a common electrode
line and a common electrode;
the organic thin film transistor includes: a gate electrode, a gate insulating layer, an organic semiconductor layer, a source
electrode and a drain electrode;

above the data line, the source electrode, the drain electrode and the pixel electrode, there are disposed in order a first
bank insulating layer and a second bank insulating layer from bottom to top;

in the first bank insulating layer, there are provided a first through hole, a first opening and a second opening;
the source electrode and the drain electrode are located on two sides of the first through hole;
in the first opening, there is formed the gate line by printing, and in the second opening, there is formed the common electrode
line by printing;

in the first through hole, there are formed in order the organic semiconductor layer, the gate insulating layer and the gate
electrode by printing from bottom to top, the gate electrode is connected with the gate line, and the organic semiconductor
layer is connected with the source electrode and the drain electrode.

US Pat. No. 9,280,028

ELECTROCHROMIC DISPLAY DEVICE AND METHOD OF PRODUCING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A method for producing an electrochromic display device comprising:
using a first electrode substrate, electrochromic fluid, and a second electrode substrate to form an electrochromic cell,
wherein the electrochromic fluid is distributed between the first and the second electrode substrate; and

forming at least one dividing wall in the electrochromic cell, wherein the dividing wall is located between the first and
the second electrode substrates, contacts the first and the second electrode substrates, respectively, and is used for isolating
the electrochromic fluid in various pixel areas,

wherein:
the electrochromic fluid is formed by mixing at least three materials including electrochromic material, electrolyte, and
photoactive small molecules; and wherein

forming at least one dividing wall in the electrochromic cell comprises: exposing the electrochromic fluid in a contacting
area of adjacent pixel areas in the electrochromic cell to UV light to photopolymerize the photoactive small molecules in
the contacting area, to form the dividing wall.

US Pat. No. 9,310,937

TOUCH DRIVING CIRCUIT, OPTICAL IN CELL TOUCH PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A touch driving circuit comprising a photosensitive sub-module, a driving sub-module and a controlling sub-module, wherein,
a first signal input terminal of the photosensitive sub-module is connected with a switch signal terminal, a second signal
input terminal of the photosensitive sub-module is connected with a gate signal terminal, a signal output terminal of the
photosensitive sub-module is connected with a first signal input terminal of the driving sub-module; the photosensitive sub-module
is configured to output a touch signal to the driving sub-module under controls of the switch signal terminal and the gate
signal terminal;

a second signal input terminal of the driving sub-module is connected with a reference signal terminal, a third signal input
terminal of the driving sub-module is connected with a control signal terminal and a first signal input terminal of the controlling
sub-module, respectively, a signal output terminal of the driving sub-module is connected with a second signal input terminal
of the controlling sub-module; the driving sub-module is configured to output a touch sensing signal to the controlling sub-module
under a control of the touch signal, the touch sensing signal decreasing as an intensity of light irradiated on the photosensitive
sub-module increases; and

a signal output terminal of the controlling sub-module is connected with a touch signal reading terminal; the controlling
sub-module is configured to output the touch sensing signal to the touch signal reading terminal when the control signal terminal
controls the controlling sub-module to be in a turn-on state,

wherein the photosensitive sub-module further comprises a photosensitive transistor;
wherein a gate of the photosensitive transistor is connected with the switch signal terminal, a source of the photosensitive
transistor is connected with the gate signal terminal, and a drain of the photosensitive transistor is connected with the
first signal input terminal of the driving sub-module.

US Pat. No. 9,285,645

DISPLAY PANEL AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A display panel, comprising:
a first substrate and a second substrate opposed to each other;
a blue phase liquid crystal layer arranged between the first substrate and the second substrate;
a first polarizer located on a side of the first substrate away from the blue phase liquid crystal layer;
a second polarizer located on a side of the second substrate away from the blue phase liquid crystal layer;
a first electrode located on a side of the first substrate facing the blue phase liquid crystal layer;
a second electrode located on a side of the second substrate facing the blue phase liquid crystal layer, the first electrode
and the second electrode being configured to generate a vertical electrical field;

a first prism layer located between the blue phase liquid crystal layer and the first polarizer and configured to deflect
an incident light and direct the deflected incident light towards the blue phase liquid crystal layer; and

a second prism layer located between the blue phase liquid crystal layer and the second polarizer and configured to deflect
the incident light having passed through the blue phase liquid crystal layer and direct the deflected incident light towards
the outside of the display panel;

wherein the first prism layer comprises a plurality of first triangular prisms and the second prism layer comprises a plurality
of second triangular prisms and both the first triangular prisms and the second triangular prisms are isosceles triangular
prisms;

wherein the first triangular prisms each comprise a bottom face which is parallel to the first substrate and two refractive
faces which are inclined at an angle of 30˜80 degrees with respect to the bottom face thereof; and/or the second triangular
prisms each comprise a bottom face which is parallel to the second substrate and two refractive faces which are inclined at
an angle of 30˜80 degrees with respect to the bottom face of the second triangular prism; and

wherein the first triangular prisms have the same size as that of the second triangular prisms, and the first triangular prisms
and the second triangular prisms are arranged such that their tops are opposed to each other.

US Pat. No. 9,312,146

MANUFACTURING METHOD OF A THIN FILM TRANSISTOR

BOE TECHNOLOGY GROUP CO.,...

1. A manufacturing method of a thin film transistor, the thin film transistor comprising a gate electrode, a gate insulation
layer, an active layer, an ohmic contact layer, a source electrode and a drain electrode,
wherein the method comprises: forming the ohmic contact layer by an injection process;
wherein the method comprises: forming a first groove and a second groove communicated with each other in the gate insulation
layer; forming the active layer in the first groove: and forming the ohmic contact layer in the second groove by the injection
process;

wherein a conductivity of the ohmic contact layer is not uniform, and the method comprises:
forming a photoresist layer on the gate insulation layer;
performing exposing and developing processes on the photoresist layer by using a multi-tone mask plate so as to form a photoresist-completely-removed
region, a first to n-th photoresist-partially-retained regions and a photoresist-completely-retained region, wherein n is
an integer equal to or greater than 2, thicknesses of the photoresist in the first to n-th photoresist-partially-retained
regions are gradually increased, and the photoresist-completely-removed region corresponds to a region where the active layer
is to be formed, the first to n-th photoresist-partially-retained regions correspond to a region where the ohmic contact layer
is to be formed, and the photoresist-completely-retained region corresponds to other region;

etching the gate insulation layer in this photoresist-completely-removed region to form the first groove, and then forming
the active layer in the first groove;

removing the photoresist in the first photoresist-partially-retained region and etching the gate insulation layer in this
region to form a first portion of the second groove, and then forming a first sub-ohmic-contact-layer in the first portion
of the second groove by using the injection process;

removing the photoresist in the second photoresist-partially-retained region and etching the gate insulation layer in this
region to form a second portion of the second groove, and then forming a second sub-ohmic-contact-layer in the second portion
of the second groove by using the injection process;

in the same way as that for forming the first sub-ohmic-contact-layer and the second sub-ohmic-contact-layer, forming other
sub-ohmic-contact-layers until

removing the photoresist in the n-th photoresist-partially-retained region, etching the gate insulation layer in this region
to form a n-th portion of the second groove and forming a n-th sub-ohmic-contact-layer in the n-th portion of the second groove
by using the injection process; and

removing the photoresist in the photoresist-completely-retained region.

US Pat. No. 9,281,324

ARRAY SUBSTRATE, FABRICATION METHOD THEREOF AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. An array substrate, comprising: gate lines, data lines, and pixel units defined by the gate lines and the data lines crossing
with each other, and each pixel unit comprises a first thin film transistor, a gate of which is electrically connected to
a gate line of the gate lines, wherein each pixel unit further comprises:
an auxiliary turn-on structure for forming a turn-on voltage at a channel of the first thin film transistor when the first
thin film transistor is switched into conduction,

wherein the auxiliary turn-on structure is a second thin film transistor, a gate of the second thin film transistor and the
gate of the first thin film transistor are electrically connected with each other, and a drain of the second thin film transistor
is used to form the turn-on voltage at the channel of the first thin film transistor,

wherein an insulating spacer layer is provided between a source-drain electrode layer of the second thin film transistor and
a source-drain electrode layer of the first thin film transistor; a source of the second thin film transistor is connected
to an active layer of the second thin film transistor and the gate line; and the drain of the second thin film transistor
is connected to the active layer of the second film transistor and is at least partially located in a region corresponding
to the channel of the first thin film transistor.

US Pat. No. 9,263,539

THIN-FILM TRANSISTOR AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A thin-film transistor, comprising a gate electrode, an active layer, source and drain electrodes, and a gate insulating
layer provided between the gate electrode and the active layer, wherein:
the gate electrode comprises:
a gate electrode metal layer,
a first protection layer, the first protection layer being provided between the gate electrode metal layer and the gate insulating
layer to isolate the active layer from the gate electrode metal layer, and the first protection layer comprising a third gate
protection layer and a fourth gate protection layer, at least one of the third gate protection layer and the fourth gate protection
layer being a multi-layer structure; and

a second protection layer, the second protection layer being provided on an side of the gate electrode metal layer opposite
to the first protection layer, and the second protection layer comprising a first gate protection layer and a second gate
protection layer, the second gate protection layer being a multi-layer structure and provided between the first gate protection
layer and the gate electrode metal layer.

US Pat. No. 9,273,390

APPARATUS AND METHOD FOR COATING ORGANIC FILM

BOE TECHNOLOGY GROUP CO.,...

1. An apparatus for coating an organic film, wherein the apparatus comprises:
an evaporation device, an electron emission device and a spray device;
wherein said evaporation device comprises an evaporation container, said evaporation container is a linear evaporation container,
in which a uniform organic gas is generated;

said electron emission device is horizontally arranged over the evaporation container such that the organic gas evaporated
in the evaporation container is uniformly charged and becomes charged organic gas;

said spray device is provided with an electric field, under which the charged organic gas is moved toward a substrate so as
to deposit the organic film on the substrate; and

a movable barrier arranged neighboring to the evaporation opening for opening or closing said evaporation opening;
wherein said evaporation container comprises a slit-like evaporation opening arranged at top of the evaporation container,
said electron emission device comprises an electron emission port arranged over the evaporation opening;

wherein the spray device comprises an electrode plate, a spray chamber and a spray head;
wherein said electrode plate is arranged in top of the spray chamber, said spray head is arranged at bottom of the spray chamber;
a bias voltage provided by an exterior power supply is applied to the electrode plate and an vertically downward electric
field is generated, the charged organic gas is moved under effect of the electric field from an upper portion to an lower
portion of the spray chamber and then sprayed out of the spray head;

wherein a gas channel is arranged between said evaporation container and said spray chamber, said charged organic gas is horizontally
moved from the evaporation chamber into the spray chamber through the gas channel.

US Pat. No. 9,276,014

ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME, AND LIQUID CRYSTAL DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising a gate, a gate line, a gate insulation layer, a semiconductor layer, a first transparent
electrode, a second transparent electrode, a source, a drain and a passivation layer, wherein
the passivation layer covers the gate line, the gate, the gate insulation layer, the semiconductor layer and the first transparent
electrode;

the second transparent electrode is provided above the passivation layer;
the source and the drain are provided above the passivation layer and are electrically connected to the semiconductor layer
through a source via and a drain via provided in the passivation layer, respectively;

the gate and the gate line comprise a first transparent conductive material layer, the first transparent conductive material
layer is provided in the same layer as the first transparent electrode;

the gate insulation layer is provided between the gate and the semiconductor layer and is not provided between the first transparent
electrode and the second transparent electrode; and

the source and the drain comprise a second transparent conductive material layer and a source-drain metal layer provided on
the second transparent conductive material layer, the second transparent conductive material layer is provided in the same
layer as the second transparent electrode.

US Pat. No. 9,268,161

METHOD FOR MANUFACTURING A LIQUID CRYSTAL PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a liquid crystal panel, comprising the followings steps:
bonding a first substrate with a second substrate so as to form a mother substrate;
forming an array pattern on a first substrate side of the mother substrate, the first substrate side being away from the second
substrate;

separating the first substrate and the second substrate of the mother substrate; and
bonding the separated first substrate and the second substrate so that the array pattern is located between the first and
second substrates.

US Pat. No. 9,263,387

GOA CIRCUIT OF ARRAY SUBSTRATE AND DISPLAY APPARATUS

BOE Technology Group Co.,...

1. A Gate driver On Array (GOA) circuit, comprising:
a GOA unit;
a Vertical StarT pulse (STV) signal wire electrically connected to the GOA unit, the STV signal wire comprising a first part
and a second part;

a first transparent electrode; and
an insulating layer arranged between the first transparent electrode and the first part, the first transparent electrode,
the first part and the insulating layer forming a first capacitor.

US Pat. No. 9,245,661

CONDUCTIVE FILM WITH DOPED LAYERS, METHOD FOR PRODUCING THE SAME, AND ARRAY SUBSTRATE COMPRISING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate comprising a plurality of metal layers, wherein at least one of the plurality of metal layers is a combined
film formed by a first conductive film, a copper film, and a second conductive film laminated in sequence, each of the first
and second conductive film comprising a base film which is made of copper or copper alloy and in which hydrogen and/or carbon
atoms are distributed.

US Pat. No. 9,269,313

GOA CIRCUIT, ARRAY SUBSTRATE, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A GOA circuit comprising clock signal input lines and more than two GOA units connected in cascade, wherein
each of the GOA units comprises a selection signal output sub-unit and a selection sub-unit;
the selection signal output sub-unit is configured to receive a source signal; and to output a selection signal in accordance
with the source signal;

the selection sub-unit is configured to receive the selection signal and N clock signals, and to output a received signal
in accordance with the selection signal; and

the number of the clock signal input lines is at least equal to N, and the clock signal input lines are configured to input
the clock signals to the selection sub-unit, where N is an integer number which is higher than or equal to two.

US Pat. No. 9,263,480

METHOD FOR FABRICATING ARRAY SUBSTRATE OF DISPLAY USING MULTIPLE PHOTORESISTS

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate comprising a substrate; a plate electrode, a gate electrode, a gate line, a gate insulating film, a
semiconductor silicon island, a source electrode, a drain electrode, a data line, a slit electrode formed on the substrate,
and the substrate is also provided with a gate line through hole and a data line through hole, wherein
the gate electrode and the gate line comprise a first transparent conductive material and a gate metal material stacked sequentially;
the slit electrode is directly connected to the drain electrode;
a second transparent conductive material is connected to the gate line through the gate line through hole; and connected to
the data line through the data line through hole,

wherein the gate insulating film is arranged between the gate electrode and the semiconductor silicon island as well as between
the plate electrode and the slit electrode.

US Pat. No. 9,244,303

WIDE-VIEWING-ANGLE LIQUID CRYSTAL DISPLAY PANEL, COLOR FILM BASE PLATE AND MANUFACTURING METHOD THEREOF AS WELL AS DISPLAY DEVICE

BOE Technology Group Co.,...

1. A color filter substrate, applied to a wide view angle LCD panel comprising an array substrate and the color filter substrate,
wherein the array substrate comprising a planar electrode and a slit electrode, which are overlapped and insulated with each
other and configured to produce an electric field capable of driving liquid crystal molecules to rotate; and the color filter
substrate comprising:
a transparent substrate; and
a color filter arranged on the transparent substrate;
wherein after the array substrate and the color filter substrate are arranged opposite to each other, the color filter corresponds
to the slit electrode on the array substrate, and a ratio between light transmittance T1 of any one position on the color filter and light transmittance T2 of any other position on the color filter is equal to a ratio between LC efficiency X2 at a position, corresponding to the any other position, on the slit electrode and LC efficiency X1 at a position, corresponding to the any one position, on the slit electrode.

US Pat. No. 9,281,348

DISPLAY PANEL AND FABRICATING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A display panel, comprising:
a first substrate;
a second substrate, arranged parallel to the first substrate;
an anode/cathode, formed on the first substrate;
a cathode/anode, formed on the second substrate;
a first alignment layer, provided on the anode/cathode and comprising a plurality of first sub-alignment layers having a first
alignment direction and a plurality of second sub-alignment layers having a second alignment direction alternately arranged
in a first direction, and a angle between the first alignment direction and the second alignment direction being 90 degrees;

a second alignment layer, provided on the cathode/anode and comprising a plurality of third sub-alignment layers having the
first alignment direction and a plurality of fourth sub-alignment layers having the second alignment direction alternately
arranged in the first direction, and the first sub-alignment layers corresponding to the third sub-alignment layers in a position,
and the second sub-alignment layers corresponding to the fourth sub-alignment layers in a position; and

a light emitting layer, provided between the first alignment layer and the second alignment layer, which comprises a liquid
crystal polymer doped with organic light emitting material and is configured to emit a polarized light wherein a plurality
of sub-pixel units comprises a plurality of red sub-pixel units, a plurality of green sub-pixel units and a plurality of blue
sub-pixel units, wherein the light emitting layer corresponding to the red sub-pixel units comprises a fluorene/D-A type naphthothiadiazole/benzoselenadiazole
copolymer or a fluorene/thiophene/benzoselenadiazole copolymer, the light emitting layer corresponding to the green sub-pixel
units comprises poly(9,9-dioctylfluorene-alt-benzothiadiazole)(PFBT) or vinyl fluorene-vinyl phenothiazine copolymer, and
the light emitting layer corresponding to the blue sub-pixel units comprises poly(9,9-dihexylfluorene)(PF2/6) or dioctylfluorene(PFO),

the first alignment layer and the second alignment layer are a doping polyimide alignment layers, the doping polyimide alignment
layer is a polyimide alignment layer doped with star-amine or a polyphenylene vinylene prepolymer alignment layer.

US Pat. No. 9,262,981

DISPLAY DRIVING CIRCUIT, DISPLAY DRIVING METHOD AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A display driving circuit comprising N gate driving units for being connected to N gate lines on an array substrate, respectively,
wherein the display driving circuit further comprises a timing control unit, n pre-charging units and n scanning control units,
the N gate driving units, the n pre-charging units and the n scanning control units are all connected to the timing control
unit, n represents a number of groups into which the N gate lines on the array substrate are divided in advance and is an
integer greater than or equal to 2;
the n pre-charging units are connected to the n gate line groups pre-divided on the array substrate, respectively, the timing
control unit is used to control the gate driving units to input scanning signals to the gate lines, respectively; the timing
control unit is further used to control an ith pre-charging unit to insert a pre-charging signal into an ith gate line group before the scanning signals are input to the gate lines in the ith gate line group and control an ith scanning control unit to pause the input of scanning signals at the same time, the pre-charging signal is used to turn on
thin film transistors directly connected to the gate lines in the ith gate line group, such that the timing control unit controls data lines to pre-charge pixel units connected to the thin film
transistors, the ith scanning control unit triggers the gate driving units corresponding to the ith gate line group to input the scanning signals to the gate lines in the gate line group after the insertion is completed, wherein
i=1, 2, . . . , n, 1

US Pat. No. 9,521,791

ASSEMBLY EQUIPMENT AND ASSEMBLY METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. An assembly equipment for assembling a flexible screen with a curved backplane, comprising:
a supporting part used for supporting and fixing the curved backplane; and
a holding part used for holding the flexible screen and assembling the flexible screen with the curved backplane in a fit
manner.

US Pat. No. 9,273,244

METHOD OF PREPARING FLUORESCENT NANOPARTICLES

BOE TECHNOLOGY GROUP CO.,...

1. A method of preparing nanoparticles of ZnSexS1-x wherein 0 S1-1: in accordance with a molar ratio of selenium to sulfur in the nanoparticles ZnSexS1-x, mixing selenium powders, and sulfur powders with octadecylene, heating and stirring the mixture to dissolve the selenium
powders, and the sulfur powders, and cooling the mixture to give a first precursor solution comprising selenium and sulfur
elements;

S1-2: mixing zinc oxide, oleic acid or laurie acid, octadecylene, and benzophenone, heating and stirring the mixture to dissolve
the zinc oxide, to give a second precursor solution comprising zinc element, wherein a molar ratio of the zinc oxidg, the
oigis acid or lauric acid, the octadecylene, and the benzophenone is 1:10:28:0.3;

S2: in accordance with a ratio of zinc, selenium and sulfur in nanoparticles of ZnSexS1-x, adding the first precursor solution into the second precursor solution and heating the resultant precursor solution mixture
to allow the precursors to undergo a reaction at a temperature of from 270°C to 290° C. for a time of 5 min to 10 min to form
a reaction solution; and

S3: pouring the reaction solution into a polar organic solvent to precipitate a raw product, washing and isolating the precipitate
by centrifugation, and then dissolving the isolated materials with a non-polar organic solvent to give nanoparticles of ZnSexS1-x.

US Pat. No. 9,263,594

THIN FILM TRANSISTOR ARRAY BASEPLATE

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor (TFT) array substrate comprising: a base substrate and a thin film transistor functioning as a switching
element, the thin film transistor comprising a gate electrode, a semiconductor layer, a semiconductor protective layer, a
source electrode and a drain electrode,
wherein the semiconductor protective layer is disposed adjacent to the semiconductor layer and comprises a composite lamination
structure, which comprises a protective layer formed of silicon oxide or a metal oxide and being in contact with the semiconductor
layer and an insulating layer formed of an organic insulating material.

US Pat. No. 9,220,174

PEDESTAL FOR FLAT PANEL DISPLAY DEVICE AND FLAT PANEL DISPLAY DEVICE

BOE Technology Group Co.,...

1. A pedestal for a flat panel display device, the pedestal comprising:
a supporting frame, comprising a horizontally arranged base plate and a framework vertically fixed on the base plate, the
framework having a supporting plate on its top, and the supporting plate being configured to support an underside of a display
panel of the flat panel display device;

at least one circuit board, vertically disposed on the framework;
a front shell and a rear shell, respectively fixed connected with the framework, and said front shell and rear shell have
strip-type notches on their tops respectively, opening directions of the strip-type notches facing to each other and being
configured to horizontally limit a position of the display panel.

US Pat. No. 9,279,995

3D DISPLAY DEVICE AND 3D DISPLAY SYSTEM

BOE TECHNOLOGY GROUP CO.,...

1. A 3D display device, comprising:
a reflecting unit, reflecting light incident thereon;
a polarization display unit, formed at a reflected light emitting side of the reflecting unit, and the polarization display
unit for displaying images, converting incident natural light into polarized light and transmitting or blocking light reflected
by the reflecting unit; and

a polarization direction adjustment unit, formed at a reflected light emitting side of the polarization display unit, for
converting the reflected light emitted from the polarization display unit into two sets of polarized light with different
polarization directions,

wherein the polarization display unit is a liquid crystal display panel, the polarization display unit displays an using by
using the incident natural light, the 3D display device does not comprise any backlight source.

US Pat. No. 9,281,455

LED PACKAGING STRUCTURE HAVING CONCAVE LENS STRUCTURE AT LIGHT-EMITTING SIDE OF LED CHIP

BOE TECHNOLOGY GROUP CO.,...

1. A lighting emitting diode (LED) packaging structure comprising a support having a cavity and at least one LED chip placed
in the cavity, wherein a light emitting side of the LED chip is provided with at least one concave lens structure,
wherein the packaging structure further comprises from its bottom to top:
a metal layer including a first electrode area and a second electrode area, disposed at a bottom of the cavity;
a fluorescent adhesive portion filled inside the cavity, wherein an upper surface of the fluorescent adhesive portion opposite
to the bottom of the cavity includes at least one outward convex surface; and

a transparent packaging adhesive portion located on the fluorescent adhesive portion, wherein an upper surface of the transparent
packaging adhesive portion opposite to the bottom of the cavity includes at least one inward concave surface,

wherein the at least one LED chip is secured on the metal layer, and an anode and a cathode of the at least one LED chip are
respectively connected with the first electrode area and the second electrode area through gold lines.

US Pat. No. 9,311,873

POLARITY INVERSION DRIVING METHOD FOR LIQUID CRYSTAL DISPLAY PANEL, DRIVING APPARATUS AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A polarity inversion driving method for a liquid crystal display panel, wherein each of frames is divided into M polarity
arrangement units in a same manner, every 2×M×N frames form one inversion driving period, and in each of half inversion driving
periods:
?!x?(0, M×N], between an x-th frame and a (x+1)-th frame, except that polarities of first polarity arrangement units are same,
polarities of all polarity arrangement units are opposite;

?m?[0, M), between a (x+m×N)-th frame and a (x+m×N+1)-th frame, except that polarities of (m+1)-th polarity arrangement units
are same, polarities of all polarity arrangement units are opposite;

wherein a polarity of each of other frames is opposite to that of a frame adjacent thereto;
wherein, each of M, N, x and m is an integer number, and value of M×N is an even number; when (x+1)>M×N, (x+1) represents
the first frame in the half inversion driving period; when (x+m×N)>M×N, (x+m×N) represents the (x+m×N?M×N)-th frame in the
half inversion driving period; when (x+m×N+1)>M×N, (x+m×N+1) represents the (x+m×N?M×N+1)-th frame in the half inversion driving
period; and

in two of half inversion driving periods adjacent to each other, the polarities of corresponding frames are opposite.

US Pat. No. 9,095,031

ORGANIC LIGHT EMITTING DIODE DRIVING CIRCUIT, DISPLAY PANEL, DISPLAY AND DRIVING METHOD

BOE TECHNOLOGY GROUP CO.,...

1. An organic light emitting diode driving circuit comprising an organic light emitting diode, a driving unit controlling
a current of the organic light emitting diode and a threshold compensation unit comprising:
a first electronic switch with a first connection terminal thereof being connected to a cathode of the organic light emitting
diode, a second connection terminal thereof being connected to the driving unit and a switch control terminal thereof being
connected to a second control voltage;

a second electronic switch with a first connection terminal thereof being connected to a high level, a second connection terminal
thereof being connected to a first connection terminal of a third electronic switch, and a switch control terminal thereof
being connected to a first control voltage;

the third electronic switch with a first connection terminal thereof being connected to the second connection terminal of
the second electronic switch, a second connection terminal thereof being connected to a capacitance, and a switch control
terminal thereof being connected to a scan voltage;

a fourth electronic switch, with a first connection terminal thereof being connected to the driving unit, a second connection
terminal thereof being connected to a data voltage, and a switch control terminal thereof being connected to the scan voltage;

a fifth electronic switch with a first connection terminal thereof being connected to ground, a second connection terminal
thereof being connected to the driving unit, and a switch control terminal thereof being connected to the second control voltage;
and

the capacitance with one terminal thereof being connected to ground, and the other terminal thereof being connected to the
second connection terminal of the third electronic switch,

wherein an anode of the organic light emitting diode is connected to the high level, and
the second connection terminal of the second electronic switch is connected to the second connection terminal of the first
electronic switch.

US Pat. No. 9,195,100

ARRAY SUBSTRATE, LIQUID CRYSTAL PANEL AND DISPLAY DEVICE WITH PIXEL ELECTRODE AND COMMON ELECTRODE WHOSE PROJECTIONS ARE OVERLAPPED

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate comprising a pixel electrode layer and a common electrode layer,
wherein the common electrode layer is provided with a plurality of common electrodes, and the pixel electrode layer is provided
with a plurality of pixel electrodes, and

wherein projection of each common electrode, projected in a direction vertical to the pixel electrode layer, overlaps or partially
overlaps with a corresponding pixel electrode; and

wherein the pixel electrode layer comprises a first pixel electrode and a second pixel electrode adjacent to each other, and
the common electrode layer comprises a first common electrode located over a data line, and

wherein projection lines of two opposite edges of the first common electrode, projected in a direction vertical to the pixel
electrode layer, are respectively located on the first pixel electrode and on the second pixel electrode; and

the data line and the pixel electrode layer are disposed in the same layer; the first pixel electrode and the second pixel
electrode of the pixel electrode layer are located respectively at two sides of the data line.

US Pat. No. 9,123,283

SHIFT REGISTER, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A shift register comprising shift register units at N stages in a cascade connection, wherein a frame start signal STV
is input to a first signal input terminal of a shift register unit at a first stage and a second signal input terminal of
a shift register unit at an Nth stage, and a forward scanning signal and a reverse scanning signal are input to a forward
scanning signal input terminal and a reverse scanning signal input terminal of each of the shift register units respectively,
the shift register outputs an output signal of each stage via a signal output terminal of each stage in a forward direction
according to the forward scanning signal and outputs the output signal of each stage via the signal output terminal of each
stage in a reverse direction according to the reverse scanning signal, wherein the shift register units at N stages comprises
odd numbered shift register units which receive a first clock signal and even numbered shift register units which receive
a second clock signal having phase opposite to that of the first clock signal,
wherein each of the shift register units (S/R(n)) comprises:
a forward scanning switch module for turning on a pull-up driving module under the control of the forward scanning signal
to output a first signal to a pull-up node (PU), and outputting a second signal to a second pull-down module under control
of the forward scanning signal; the first signal is the output signal of a shift register unit (S/R(n?1)) at a previous stage
of the shift register unit (S/R(n)) or STV, and the second signal is the output signal of a shift register unit (S/R(n+1))
at a next stage of the shift register unit (S/R(n)) or STV;

a reverse scanning switch module for turning on the pull-up driving module under control of the reverse scanning signal to
output the second signal to the pull-up node (PU), and outputting the first signal to the second pull-down module under the
control of the reverse scanning signal;

the pull-up driving module for inputting a pull-up control signal to the pull-up node (PU) according to an output signal of
the forward scanning switch module or the reverse scanning switch module;

a pull-up module for supplying the first clock signal or the second clock signal to the signal output terminal according to
the pull-up control signal of the pull-up node (PU);

a pull-down driving module for outputting a pull-down control signal to a first pull-down module according to a second supply
voltage (VDD) and the pull-up control signal of the pull-up node (PU);

the first pull-down module for receiving the pull-down control signal of the pull-down driving module and supplying a first
supply voltage (VSS) to the signal output terminal;

a second pull-down module for receiving a reset signal according to the control of the forward scanning switch module or the
reverse scanning switch module, and discharging under control of the reset signal, wherein the reset signal is the first signal
or the second signal.

US Pat. No. 9,113,534

LIGHT-EMITTING CONTROL CIRCUIT, LIGHT-EMITTING CONTROL METHOD AND SHIFT REGISTER

BOE Technology Group Co.,...

1. A light-emitting control circuit for generating a light-emitting control signal which controls an OLED to emit light in
an AMOLED, phases of the light-emitting control signal and a gate driving signal outputted by a gate driving circuit are opposite;
the light-emitting control circuit comprises an inputting terminal, an input sampling unit, an outputting unit, a resetting
unit, an output pulling-down unit and a outputting terminal for the light-emitting control signal, wherein,

the output pulling-down unit is connected with the outputting terminal for the light-emitting control signal;
the input sampling unit is connected with the inputting terminal, a first clock signal inputting terminal and the output pulling-down
unit, respectively, and is used for sampling an input signal under a control of a first clock signal and transmitting the
sampled signal to the outputting terminal for the light-emitting control signal through the output pulling-down unit;

the outputting unit is connected with the input sampling unit, a second clock signal inputting terminal and the outputting
terminal for the light-emitting control signal, respectively, and is used for generating a light-emitting control signal under
a control of a second clock signal after the input sampling unit samples the input signal and transmitting the light-emitting
control signal to the outputting terminal for the light-emitting control signal;

the resetting unit is connected with a third clock signal inputting terminal and the output pulling-down unit, respectively,
and is used for sending a resetting control signal to the output pulling-down unit under a control of a third clock signal;

the output pulling-down unit is used for resetting the light-emitting control signal according to the resetting control signal.

US Pat. No. 9,123,592

ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY APPARATUS

BOE Technology Group Co.,...

1. An array substrate, comprising:
a substrate;
a plurality of common electrodes formed on the substrate;
a plurality of gate signal lines formed above the common electrodes; and
a plurality of common electrode signal line units corresponding to the plurality of common electrodes, respectively, and formed
on the corresponding common electrodes, respectively,

wherein each of the common electrode signal line units comprises a first common electrode signal line perpendicular to the
gate signal line and a second common electrode signal line parallel to the gate signal line;

wherein the first common electrode signal line and the second common electrode signal line both are made of metal;
wherein the first common electrode signal line and the second common electrode signal line of each of the common electrode
signal line units cross with each other and are electrically connected to each other; and

wherein two adjacent common electrode signal line units are electrically connected by a bridge line.

US Pat. No. 9,288,460

METHOD, APPARATUS, AND SYSTEM FOR ADJUSTING WHITE BALANCE DATA

BOE TECHNOLOGY GROUP CO.,...

1. A method for adjusting white balance data, comprising:
reading only a first white balance data of an image of a certain target signal source, without reading white balance data
of other signal sources other than the certain target signal source;

performing a first adjustment operation such that the first white balance data complies with a predetermined target value
and a second white balance data is generated;

sending the second white balance data to signal source channels of the other signal sources except the certain target signal
source; and

performing a second adjustment operation, wherein the second adjustment operation is a second adjustment performed on a third
white balance data of the signal source channels of the other signal sources according to the second white balance data,

wherein the performing of a first adjustment operation comprises:
comparing the predetermined target value with the first white balance data to acquire a comparison result; and
when the comparison result indicates that the first white balance data does not comply with the predetermined target value,
adjusting source data in the first white balance data such that the target data in the first white balance data falls within
a range of the predetermined target value.

US Pat. No. 9,544,981

TOUCH DISPLAY PANEL AND TOUCH DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A touch display panel comprising:
a driving electrode layer arranged with driving electrodes,
a sensing electrode layer arranged with sensing electrodes;
an anti-static layer arranged with conductive anti-static patterns each of which does not overlap spatially overlapped regions
of the driving electrodes and the sensing electrodes; and

a controllable switch through which the anti-static layer is grounded,wherein the anti-static layer is different from the sensing electrode layer and the driving electrode layer, and the driving
electrode layer is different from the sensing electrode layer.

US Pat. No. 9,250,726

TOUCH DISPLAY AND ELECTRONIC APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A touch display, comprises:
a display device;
a touch device, positioned on a display surface side of the display device, and the touch display comprising a touch-sensitive
layer;

a shielding circuit layer, disposed between the touch-sensitive layer and the display device; and
a transparent insulating layer, disposed between the touch-sensitive layer and the shielding circuit layer,
wherein the shielding circuit layer and the touch-sensitive layer are equipotential, and
wherein the shielding circuit layer and the touch-sensitive layer are electrically connected with each other by a via penetrating
the transparent insulating layer.

US Pat. No. 9,285,517

BACK COVER FOR BACKLIGHT SOURCE, BACKLIGHT SOURCE, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A back cover for a backlight source, comprising:
at least one reflection surface arranged on one surface of the back cover, wherein:
the reflection surface includes a first reflection region and a second reflection region;
the first reflection region includes a plurality of concave arc-shaped regions whose curvatures gradually increase in a direction
toward the second reflection region;

the second reflection region includes a plurality of concave arc-shaped regions whose curvatures gradually decrease in a direction
away from the first reflection region; and

the concave arc-shaped region having a maximum curvature in the first reflection region is connected with the concave arc-shaped
region having a maximum curvature in the second reflection region.

US Pat. No. 9,466,624

ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A fabrication method of an array substrate, comprising:
forming a gate metal layer, a gate insulating layer, an active layer and a source-drain metal layer on a base substrate, wherein
the gate metal layer comprises at least a gate electrode and a metal pad;

wherein the forming the gate insulating layer, the active layer and the source-drain metal layer on the base substrate comprises:
forming a gate insulating film, an active layer film, and a source-drain metal film on the base substrate; and
forming the gate insulating layer, the active layer and the source-drain metal layer by a single patterning process,
wherein in a via hole is formed during the single pattern process, with the via hole penetrating the source-drain metal layer,
the active layer and the gate insulating layer and reaching the metal pad.

US Pat. No. 9,261,642

LIGHT GUIDE MEMBER AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A display device comprises:
a plurality of display panels that are connected together,
a frame to connect the plurality of display panels, and
at least one light guide member disposed above the frame between adjacent display panels, the light guide member comprising
a plurality of light guide sheets, each light guide sheet comprising:

a body having a curved shape;
a plurality of scattering particulates dispersed in the body;
a light exiting layer positioned on an outer surface of the body; and
a light reflecting layer positioned on an inner surface of the body,
wherein each light guide sheet further comprises two end surfaces and two side surfaces, and at least one of the two end surfaces
is used to guide light into the light guide sheets;

wherein the light guide member is formed by the plurality of light guide sheet connected side by side through the side surfaces,
and

wherein the two end surfaces of each light guide sheet are positioned at two sides of the frame and contact display areas
of adjacent display panels, respectively.

US Pat. No. 9,569,049

CAPACITIVE TOUCH PANEL AND DISPLAY DEVICE WITH IMPROVED VISUAL EFFECT

BOE Technology Group Co.,...

1. The last limitation should read:
each of the first electrodes comprises a body part and a periphery part, the periphery part is directly connected to the body
part, the body part corresponds to a second electrode to which the first electrode corresponds, and the periphery part corresponds
to the second gap to which the first electrode corresponds, and a ratio of a width of the periphery part to a width of the
second gap is greater than or equal to 1/3and is less than or equal to 1/2.

US Pat. No. 9,743,512

FLEXIBLE DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A flexible display device comprising:
a display screen, wherein a side of the display screen for image display is a display side, and wherein a side opposite to
the display side is a back side;

a plurality of limiting structures arranged at the back side of the display screen, wherein each limiting structure comprises
a bottom end, a head end and a tail end; wherein an end surface of the bottom end of each limiting structure is fixed on the
back side of the display screen; wherein the head end of each limiting structure has a protrusion, the protrusion comprising
a first abutting surface and a second abutting surface adjoined with each other, an opening of an angle between the first
abutting surface and the second abutting surface faces away from the display screen; wherein the tail end of each limiting
structure has a groove, the groove comprising a third abutting surface and a fourth abutting surface adjoined with each other,
an opening of an angle between the third abutting surface and the fourth abutting surface faces away from the display screen,
and the angle between the third abutting surface and the fourth abutting surface is larger than the angle between the first
abutting surface and the second abutting surface;

wherein the plurality of limiting structures are arranged in at least one row, a protrusion of a latter limiting structure
in one row is located in a groove of a previous limiting structure, and the first abutting surface of the latter limiting
structure is opposite to the third abutting surface of the previous limiting structure, and the second abutting surface of
the latter limiting structure is opposite to the fourth abutting surface of the previous limiting structure;

wherein when the flexible display device bends towards the back side to a first curvature, the first abutting surface of the
latter limiting structure and the third abutting surface of the previous limiting structure abut against each other; and wherein
when the flexible display device bends towards the display side to a second curvature, the second abutting surface of the
latter limiting structure and the fourth abutting surface of the previous limiting structure abut against each other.

US Pat. No. 9,622,343

FLEXIBLE DISPLAY AND METHOD FOR PREPARING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A method for preparing a flexible display, comprising the steps of:
providing a first substrate;
forming a bonding agent layer on a first surface of the first substrate;
providing a second substrate;
attaching the surface of the first substrate, on which the bonding agent layer is formed, to the second substrate, wherein
the second substrate is a glass substrate, a metal substrate or a quartz substrate, and the adhesive force between the bonding
agent layer and the second substrate is lower than 5 N/20 mm-wide bonding agent layer;

forming a display device body on a second surface of the first substrate, which is opposite to the first surface of the first
substrate; and

forming a tilt slot on the edge of the first substrate, then peeling off the first substrate, on which the display device
body is formed, from the second substrate using a mechanical force and obtaining the flexible display.

US Pat. No. 9,285,631

DISPLAY DEVICE, TRANSFLECTIVE THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A transflective thin film transistor array substrate, comprising: a gate line, a data line, a common electrode line, a
reflective electrode, a pixel electrode, a common electrode and a thin film transistor formed on a substrate, wherein the
thin film transistor comprises a source electrode and a drain electrode, an area on which the reflective electrode is located
is a reflective area, an area between the reflective electrode and the common electrode line is a transmissive area, wherein
the gate line, the data line, the reflective electrode and the common electrode line are arranged in the same layer, the gate
line and the data line are vertical to each other, the data line is broken when passing through the gate line, a connection
line of the data line is set between the data lines which are broken by the same gate line and located on the same straight
line, the connection line of the data line is used to connect broken data lines, wherein the pixel electrode, the source electrode,
the drain electrode and the connection line of the data line are arranged in the same layer.

US Pat. No. 9,629,293

CHIP REMOVING DEVICE

BOE Technology Group Co.,...

1. A chip removing device, comprising:
a handle;
a heat supply unit mounted at one end of the handle,
a detachable chip heating head provided on one side of the heat supply unit away from the handle;
a temperature controller in signal communication with the heat supply unit for controlling a temperature output by the heat
supply unit; and

a gripping mechanism mounted to the handle for picking up a chip to be removed from a glass panel;
wherein the gripping mechanism comprises:
an operating rod positioned on one side of the handle;
a connecting rod with one end thereof pivotably connected to the operating rod at a first pivoting point and the other end
thereof fixedly connected to the handle;

a first gripping rod and a second gripping rod disposed opposite to each other for gripping the chip to be removed, wherein
the first gripping rod is pivotably connected to one end of the heat supply unit and the second gripping rod is pivotably
connected to the other end of the heat supply unit, and the two ends of the heat supply unit are positioned at the same height;

a first transmission rod with a first end thereof pivotably connected to the operating rod at a second pivoting point and
a second end thereof pivotably connected to a non-gripping end of the first gripping rod, the second pivoting point being
positioned below the first pivoting point; and

a second transmission rod with a first end thereof pivotably connected to the operating rod at a third pivoting point and
a second end thereof pivotably connected to a non-gripping end of the second gripping rod, the third pivoting point being
positioned above the first pivoting point,

wherein, when the operating rod moves towards the handle under a force, a distance between a gripping end of the first gripping
rod and a gripping end of the second gripping rod decreases to grip and pick up the chip to be removed.

US Pat. No. 9,240,424

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND PRODUCING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A manufacturing method of a thin film transistor array substrate, comprising:
forming an active layer thin film and a conductive layer thin film on a substrate;
depositing a source/drain electrode layer thin film on the conductive layer thin film, treating the conductive layer thin
film and the source/drain electrode layer thin film using a gray tone or half tone masking process, to form at least two data
lines, a pixel electrode and source/drain electrodes of a thin film transistor, and the source electrode of the thin film
transistor being connected with one of the data lines;

after depositing an insulating layer thin film covering the active layer thin film, the source/drain electrodes, the data
lines and the pixel electrode, forming a through hole in the insulating layer thin film, forming a gate insulating layer,
and forming an active layer of the thin film transistor, and the through hole being provided at a selected position in the
area corresponding to each of the data lines; and

forming a gate electrode of the thin film transistor and at least two gate scanning lines crossing with the data lines on
the insulating layer, and the gate electrode of the thin film transistor being connected with one of the gate scanning lines,

wherein, forming the through hole in the insulating layer thin film, forming the gate insulating layer of the thin film transistor
and forming the active layer of the thin film transistor comprises:

coating photoresist on the deposited insulating layer thin film, after exposing and developing the photoresist, etching the
insulating layer thin film and the active layer thin film, to obtain the through hole and the gate insulating layer and the
active layer of the thin film transistor; wherein, the active layer of the thin film transistor is located within an area
whose boundaries are defined by the gate scanning lines and the data lines and is distributed within the whole area.

US Pat. No. 9,544,995

FLEXIBLE SUBSTRATE ATTACHING METHOD AND FLEXIBLE SUBSTRATE ATTACHMENT STRUCTURE

Boe Technology Group Co.,...

11. A flexible substrate attachment structure, comprising:
a carrier substrate;
a flexible substrate pre-fixed on the carrier substrate via a first fixation structure; and
a pattern of a thin film on the flexible substrate, the pattern of the thin film contacting at least a part of the flexible
substrate and at least a part of the carrier substrate simultaneously.

US Pat. No. 9,723,690

METHOD AND DEVICE FOR ADJUSTING INDOOR BRIGHTNESS AND SMART HOME CONTROL SYSTEM

BOE TECHNOLOGY GROUP CO.,...

1. A method for adjusting indoor brightness, comprising:
detecting a display device to obtain brightness of the display device;
calculating indoor brightness based on the brightness of the display device; and
adjusting brightness of an indoor lighting device based on the calculated indoor brightness.

US Pat. No. 9,717,143

METHOD FOR FABRICATING FLEXIBLE SUBSTRATE AND FLEXIBLE SUBSTRATE PREFABRICATED COMPONENT

BOE Technology Group Co.,...

11. A flexible substrate prefabricated component, comprising a flexible substrate, wherein the flexible substrate comprises
an electronic device and a flexible layer provided with the electronic device; the flexible substrate prefabricated component
further comprising a support substrate, a double-sided adhesive layer and a single-sided adhesive layer, wherein:
the single-sided adhesive layer is disposed at a central portion of a surface of the support substrate, the double-sided adhesive
layer are disposed at a peripheral region of the support substrate; the flexible layer is disposed on surfaces of the single-sided
adhesive layer and the double-sided adhesive layer, the flexible layer is bonded to the double-sided adhesive layer, and the
electronic device is disposed in a region of the single-sided adhesive layer;

wherein the single-sided adhesive layer is in contact with and shape-match with the double-sided adhesive layer.

US Pat. No. 9,735,182

ARRAY SUBSTRATE, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE

BOE Technology Group Co.,...

1. A method for manufacturing an array substrate including a step of forming data lines, scan lines, and a light shielding
metal layer on a substrate and a step of forming thin film transistors on the substrate, forming the thin film transistor
includes a step of forming a gate electrode, a source electrode, a drain electrode, and an active region, both the thin film
transistors and the light shielding metal layer are formed in a plurality of pixel regions defined by the scan lines and the
data lines, wherein the light shielding metal layer and the data lines are formed along a direction parallel to a surface
of the substrate in a same layer on the substrate in a single step, and are arranged with an interval therebetween on the
substrate, the data lines being arranged under the active region, the light shielding metal layer is formed under the active
region and at least partially overlaps with the active region in a projection direction, the data line is close to the source
electrode and does not overlap with the active region at least partially in the projection direction.

US Pat. No. 9,305,498

GATE DRIVING CIRCUIT, GATE DRIVING METHOD AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A gate driving circuit, comprising a plurality of cascaded shift register units for outputting gate driving signals, each
of the gate driving signals being output by a gate driving signal output terminal of each of the shift register units; the
gate driving circuit further comprises:
a gate driving control unit, connected with the shift register unit and configured to control the gate driving signal to be
transmitted to N rows of pixel circuits time-divisionally, wherein N is a positive integer greater than or equal to 2.

US Pat. No. 9,795,031

WIRING BOARD, FLEXIBLE DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A wiring board which is used to connect a driving chip and a display panel, wherein signal output ends on the driving chip
and signal input ends on the display panel are arranged in pairs; and the wiring board comprises fanout lines each of which
is configured to connect a pair of the signal output end and the signal input end,
wherein the wiring board comprises a substrate;
a plurality of segments of first connection lines having first resistivity is arranged on a first surface of the substrate;
a plurality of segments of second connection lines having second resistivity is arranged on a second surface of the substrate
opposite to the first surface; and

at least parts of the fanout lines are formed by connecting the first connection lines and the second connection lines, wherein
connection lines of one of the fanout lines at least partially overlap connection lines of another one of the fanout lines
at an identical location on the substrate.

US Pat. No. 9,239,485

TOUCH DISPLAY PANEL AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A touch display panel, comprising a color filter substrate, wherein
a first conductive layer is formed on a base substrate of the color filter substrate, and a first insulation layer is formed
on the first conductive layer;

a pattern of the first conductive layer is same as a pattern of a black matrix that is formed on the base substrate; and
a pattern of the first insulation layer in a display region of the touch display panel is same as a pattern of the first conductive
layer in the display region.

US Pat. No. 9,312,793

BRAKE CONTROL CIRCUIT AND MOTOR SYSTEM

BOE TECHNOLOGY GROUP CO.,...

1. A brake control circuit for controlling a motor brake connected to a motor, which comprises a brake control input module
and a brake control main module used to control the motor brake to start or stop under the control of the brake control input
module, wherein the brake control input module includes a control signal input unit and N relays connected in parallel to
an output end of the control signal input unit, the control signal input unit is used to collect a power-off signal or receive
an emergency stop signal, generate a brake control signal according to the collected power-off signal or the input emergency
stop signal, and transmit the generated brake control signal to the relays, the relays are electrically connected to the brake
control main module, and are used to control an output of the brake control main module according to the brake control signal
received from the control signal input unit, and N is an integer greater than or equal to 2.

US Pat. No. 9,439,248

ELECTROLUMINESCENT DISPLAY SCREEN AND METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An electroluminescent display screen, comprising: a back plane; a package substrate; and a luminescent layer and a frit
sealant provided between the back plane and the package substrate, wherein the electroluminescent display screen further comprises
a light-shielding pattern layer for shielding the region other than the frit sealant when a laser irradiates on the frit sealant,
which is formed on one side of the package substrate that faces the back plane,
wherein the light-shielding pattern layer comprises the first annular region and the second annular region, and wherein, the
frit sealant surrounds the first annular region, and the second annular region surrounds the frit sealant,

wherein a distance between an outmost side edge of a first annular region and an inmost side edge of a second annular region
is in a range of 0.6 mm to 1.2 mm,

wherein a distance between an inmost side edge of the first annular region and an outmost side edge of the second annular
region is a sum of a width of a laser beam and a laser alignment precision,

wherein the first annular region is located inside the frit sealant, and the second annular region is located outside the
frit sealant, the first annular region functions as a barrier layer for laser irradiation and as a black frame on the cover
plate of the display screen, and is used for defining a display region.

US Pat. No. 9,423,550

BACKLIGHT MODULE HAVING A LIGHT SCATTERING UNIT FOR SCATTERING LIGHT ENTERING THE LIGHT GUIDE PLATE AND DISPLAY DEVICE HAVING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A backlight module, comprising a light guide plate and a plurality of light sources, the light guide plate comprising a
light incident surface, the plurality of light sources being arranged opposite to the light incident surface of the light
guide plate, wherein
the backlight module further comprises a light scattering unit arranged between the plurality of light sources and the light
incident surface of the light guide plate, and the light scattering unit is used for scattering and irradiating light rays
from the plurality of light sources to the light guide plate;

wherein the backlight module further comprises a light guide unit used for guiding light rays from the light sources into
the light scattering unit;

wherein the light guide unit comprises a plurality of transparent light guide bars, one end of each of the light guide bars
is arranged at light emitting surfaces of the light sources and the other end thereof is connected to the light scattering
unit; and

wherein the front faces of the light sources are in contact with the light scattering unit, and the light guide bars connect
the sides of the light sources to the light scattering unit.

US Pat. No. 9,324,873

FABRICATING METHOD OF THIN FILM TRANSISTOR, THIN FILM TRANSISTOR AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A fabricating method of a thin film transistor, comprising following steps:
M1, depositing an inducing layer on a substrate;

M2, etching a recess in the inducing layer by an etching process, the recess having an edge with a prescribed shape;

M3, depositing an amorphous silicon layer in the recess having an edge with a prescribed shape, and inducing the amorphous silicon
layer to form a polycrystalline silicon layer by crystallization method, polycrystalline silicon grains in the polycrystalline
silicon layer arranging in a direction vertical to the edge of the recess by the limitation of the edge of the recess, and
the polycrystalline silicon layer and the inducing layer together forming a semiconductor layer; and

M4, forming a gate insulating layer, a gate, a passivation layer and a source and a drain connecting with the semiconductor
layer sequentially on the semiconductor layer.

US Pat. No. 9,196,636

TFT AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor, comprising an active layer, wherein,
the active layer comprises a plurality of active semiconductor sub-layers and a plurality of insulation sub-layers, which
are stacked alternately; and

a source and a drain of the thin film transistor are electrically connected to the plurality of active semiconductor sub-layers.

US Pat. No. 9,305,945

TFT ARRAY SUBSTRATE, MANUFACTURING METHOD OF THE SAME AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A TFT array substrate, comprising:
a plurality of gate lines and a plurality of data lines formed on a substrate,
wherein the gate lines and the data lines intersect with each other to define a plurality of pixel units, and each of the
pixel units comprises a TFT and a pixel electrode, and

wherein the TFT comprises:
a gate electrode formed on the substrate;
a gate insulating layer and a passivation layer formed in this order on the substrate and covering the gate electrode;
a drain electrode formed on the passivation layer;
a first ohmic contact layer pattern formed on the drain electrode;
a semiconductor layer formed on both of the first ohmic contact layer pattern and the passivation layer;
a second ohmic contact layer pattern formed on the semiconductor layer and separated from the drain electrode and the first
ohmic contact layer pattern; and

a source electrode formed on the second ohmic contact layer pattern.

US Pat. No. 9,553,477

MOBILE COMMUNICATION TERMINAL

BOE Technology Group Co.,...

1. A mobile communication terminal comprising:
a magnetic field unit for generating magnetic field;
an induction unit comprising at least one coil;
a fixed unit and a motion unit which is movable relative to the fixed unit, wherein one of the magnetic field unit and the
induction unit is arranged on the fixed unit, and the other is arranged on the motion unit; and

an energy storage unit electrically connected to the induction unit and configured to store electrical energy generated by
the induction unit;

wherein the mobile communication terminal further comprises a speaker with a magnet, and the magnet in the speaker is used
as the magnetic field unit for generating the magnetic field.

US Pat. No. 9,424,792

TEST METHOD AND TEST DEVICE FOR LINE DEFECT OF DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A test method for line defect in a display panel comprising a plurality rows of gate lines and a plurality columns of data
lines intersecting each other to thereby define pixel units arranged in an array, each pixel unit comprising a transistor
serving as a switching element, switching state of the transistor being controlled by a corresponding gate line, the method
comprising:
inputting a first ON signal and a first OFF signal into odd rows of gate scanning lines and even rows of gate scanning lines
of the display panel respectively, to turn on transistors controlled by the odd rows of gate scanning lines, and turn off
transistors controlled by the even rows of gate scanning lines, thereby obtaining a first test image of the display panel;

inputting a second OFF signal and a second ON signal into the odd rows of gate scanning lines and the even rows of gate scanning
lines of the display panel respectively, to turn off the transistors controlled by the odd rows of gate scanning lines, and
turn on the transistors controlled by the even rows of gate scanning lines, thereby obtaining a second test image of the display
panel; and

comparing the first test image with the second test image to determine that line display defect appearing in the first test
image or the second test image is true display defect;

wherein the method further comprises:
inputting a third ON signal into both the odd rows of gate scanning lines and the even rows of gate scanning lines of the
display panel to turn on the transistors controlled by both the odd rows and the even rows of gate scanning lines, thereby
obtaining a third test image of the display panel;

comparing the first test image and the second test image with the third test image to determine that line display defects
appearing in the third test image but not in the first test image and the second test image are false display defects.

US Pat. No. 9,391,097

THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor array substrate, comprising: a substrate and a thin film transistor formed on the substrate,
wherein the thin film transistor comprises a gate electrode, a gate insulating layer, a semiconductor active layer, an etch
stop layer, a source electrode and a drain electrode,

wherein, the gate insulating layer is interposed between the gate electrode and the semiconductor active layer,
the etch stop layer covers the semiconductor active layer, and has a first via hole and a second via hole formed therein which
expose a part of the semiconductor active layer,

the source electrode of the thin film transistor contacts with the semiconductor active layer through the first via hole,
and the drain electrode of the thin film transistor contacts with the semiconductor active layer through the second via hole,

wherein, a peripheral edge pattern of the etch stop layer and the pattern of the semiconductor active layer are consistent
with each other,

wherein, the peripheral edge of the etch stop layer is aligned with a peripheral edge of the semiconductor active layer,
wherein, the etch stop layer does not extend beyond the pattern of the semiconductor active layer,
wherein the thin film transistor array substrate further comprises a gate line, a gate line lead wire, a data line and a data
lead wire, the gate line and the gate line lead wire are located on the same layer as the gate electrode; and the data line
and the data lead wire are located on the same layer as the source electrode and the drain electrode,

wherein the thin film transistor array substrate further comprises an assistant gate line lead wire which is located on the
same layer as the data line and above the gate line lead wire, the gate line lead wire contacts with the assistant gate line
lead wire through a third via hole, and

wherein the thin film transistor array substrate comprises a display region and a peripheral wiring region, the thin film
transistor, the gate line and the data line are disposed in the display region, the gate line lead wire, the assistant gate
line lead wire and the third hole are disposed in the peripheral wiring region.

US Pat. No. 9,383,640

MASK PLATE AND METHOD FOR DETECTING EXPOSURE DEFECTS USING THE SAME

BEIJING BOE OPTOELECTRONI...

1. A mask plate, comprising a mask pattern and a plurality of detection-mark mask patterns arranged along a scan direction
of an exposure machine, the detection-mark mask patterns are arranged at an edge of the mask pattern, the detection-mark mask
patterns are used for forming detection marks on a substrate, the detection marks are used for reflecting exposure defects
caused by a beam emitted from the exposure machine scanning and passing through the substrate with a nonuniform velocity.

US Pat. No. 9,383,598

LIQUID CRYSTAL MODULE

BOE TECHNOLOGY GROUP CO.,...

1. A liquid crystal module comprising:
a panel;
a backlight unit arranged at a back side of the panel;
a connection structure that connects the panel with the backlight unit, the connection structure has a supporting surface
that supports the panel, and the connection structure is made of stainless steel and is arranged at the back side of the panel,
and an adhesive layer is arranged between the supporting surface and the panel, the connection structure comprises:

a supporting portion that supports the panel, the supporting surface is arranged on the supporting portion; and
a connection portion that is connected with the backlight unit, wherein a threaded hole is formed in the connection portion,
and a bolt is inserted through the threaded hole so that the connection structure is fixed to a back plate of the backlight
unit; and

a bolt covering portion that covers a head portion of the bolt, the bolt covering portion is arranged between a back shell
and the back plate.

US Pat. No. 9,310,636

LIQUID CRYSTAL CELL, LIQUID CRYSTAL DISPLAY DEVICE AND SURFACE MODIFICATION METHOD FOR INFRARED MATERIAL

BEIJING BOE OPTOELECTRONI...

1. A liquid crystal cell, wherein a component comprising an infrared (IR) material is disposed in the liquid crystal cell,
the liquid crystal cell includes a color filter substrate and an array substrate disposed as opposed to each other, the component
comprising the IR material is disposed on the color filter substrate, and the color filter substrate is divided into a pixel
region and a black matrix region surrounding the pixel region, the component comprising the IR material is only formed on
the black matrix region.

US Pat. No. 9,274,368

COA SUBSTRATE, METHOD FOR FABRICATING THE SAME AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for fabricating a COA substrate, comprising:
forming a TFT on a base substrate;
forming a pattern of a color film layer on the base substrate having the TFT formed thereon;
forming a pattern which comprises a color film via hole on the color film layer through a patterning process, the patterning
process comprising an ashing process;

forming a pattern comprising a pixel electrode on the base substrate, the pixel electrode being electrically connected to
a drain electrode of the TFT by way of the color film via hole,

wherein before forming the pattern comprising the color film via hole on the color film layer through a patterning process,
the method further comprises: forming a transparent protection layer on the color film layer,

wherein forming the pattern comprising the color film via hole on the color film layer through a patterning process comprises:
applying a photoresist on the transparent protection layer, exposing and developing the photoresist to form a photoresist-retained-region
and a photoresist-removed region, the photoresist-removed region comprises a region of the color film via hole:

etching the transparent protection layer in the photoresist-removed region to form a pattern comprising a protection layer
via hole, locations of the protection layer via hole and the color film via hole correspond to each other;

removing the color film layer in the photoresist-removed region by using an ashing process to form the pattern comprising
the color film via hole.

US Pat. No. 9,907,202

ELECTRONIC EQUIPMENT

BOE TECHNOLOGY GROUP CO.,...

1. An electronic equipment, comprising: a housing provided with ventilation holes, and a movable baffle;
wherein where the electronic equipment is not in operation, the movable baffle is in a first state, the ventilation holes
on the housing are shielded by the movable baffle; and where the electronic equipment is in operation, the movable baffle
is moved to a second state to enable the ventilation holes on the housing to ventilate and dissipate heat normally; and

wherein the movable baffle has a structure of shutter; where the movable baffle is in the first state, the movable baffle
corresponds to a closed state of the shutter, and the ventilation holes on the housing are closed; and where the movable baffle
is moved to the second state, the movable baffle corresponds to an open state of the shutter, and the ventilation holes on
the housing are open;

wherein the electronic equipment further comprises a driving mechanism which controls the movable baffle to be switched between
the first state and the second state, wherein the driving mechanism comprises:

a coil;
a control component which controls whether the coil is powered or not;
a magnet provided on one end of the movable baffle adjacent to the coil and rigidly connected with the movable baffle;
a spring, one end of which is fixed and the other end of which is connected with the other end of the movable baffle away
from the magnet; and

a stop post, wherein where the movable baffle is at the position defined by the stop post, the movable baffle is in the second
state, and where the spring is in an initial position, the movable baffle is in the first state.

US Pat. No. 9,384,534

METHOD AND SYSTEM FOR ESTABLISHING MODEL BASED ON VIRTUAL ALGORITHM

BOE Technology Group Co.,...

1. An image processing method based on a virtual algorithm, comprising:
a) simulating a single subpixel of a practical pixel through a lattice composed of a bivariate normal distribution to obtain
a simulation result of the single subpixel including normal distribution parameters;

b) establishing a subpixel array of a single color, which contains a repeating group composed of a left side practical pixel
and a right side practical pixel, dividing a whole plane into a grid area in which each square in the grid area corresponds
to a practical pixel by using the subpixels of the single color as an origin, and selecting the normal distribution parameters
through a limiting condition of the subpixel array of the single color;

c) calculating integral values of the subpixels of the single color in different squares according to the selected normal
distribution parameters to obtain different weight coefficients of the subpixels of the single color at different squares,
stacking the subpixels of the single color in different squares, having an effect on the practical pixel, according to different
weight coefficients to obtain the strength of the single color of the left side practical pixel and the strength of the single
color of the right side practical pixel in the subpixel array of the single color; and

d) placing the strengths of three colors of the left side practical pixel into a pixel to obtain the left side virtual pixel
corresponding to the position of the left side practical pixel, and placing the strengths of three colors of the right side
practical pixel into a pixel to obtain right side virtual pixel corresponding to the position of the right side practical
pixel;

wherein, the aspect ratio of the single subpixel of the practical pixel is 2:3, and three subpixels constitute two practical
pixels.

US Pat. No. 9,299,727

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AS WELL AS DISPLAY PANEL

BOE Technology Group Co.,...

1. A manufacturing method of an array substrate, comprising:
forming a pattern including a scanning line and a spacer base on a same layer of a substrate;
forming a gate insulating layer;
forming another pattern including an active layer, a data line, a source electrode and a drain electrode;
forming a passivation layer; and
sequentially etching the passivation layer and the gate insulating layer through a dry etching method to form a via hole exposing
the spacer base, and inducing materials generated from an etching process in a reaction cavity to deposit on a surface of
the spacer base, through an electric field formed by the spacer base exposed in the via hole and etching gas adopted in the
etching process, to form a spacer.

US Pat. No. 9,281,493

FLEXIBLE SUBSTRATE AND MANUFACTURING METHOD THEREOF, OLED DISPLAY DEVICE

HEFEI BOE OPTOELECTRONICS...

1. A manufacturing method for a flexible substrate comprising a flexible base, wherein the flexible base is provided with
a mesh depression layer in which a mesh current sinking layer is embedded, the method comprises:
providing a current sinking film layer on a film forming substrate;
manufacturing the current sinking film layer into a mesh current sinking layer;
providing a flexible base material on the mesh current sinking layer;
curing the substrate formed with the flexible base material; and
removing the film forming substrate to form the flexible substrate.

US Pat. No. 9,261,744

ARRAY SUBSTRATE, FABRICATING METHOD THEREOF AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. An array substrate, comprising a base substrate, and a pattern of a gate, a pattern of a gate insulating layer, a pattern
of a pixel electrode, a pattern of an ohmic contact layer, a pattern of an active layer, and a pattern of source-drain electrodes
sequentially formed on the base substrate,
wherein the pattern of the pixel electrode is positioned between the pattern of the gate insulating layer and the pattern
of the ohmic contact layer.

US Pat. No. 9,223,168

PDLC FILM STRUCTURE, MANUFACTURING METHOD AND CONTROLLING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A polymer dispersed liquid crystal (PDLC) film structure, comprising:
a first substrate and a second substrate disposed facing each other; and
a PDLC layer filled between the first substrate and the second substrate,
wherein a transparent electrode is provided on a surface of the first substrate which faces the second substrate, and
a plurality of control units are provided on a surface of the second substrate which faces the first substrate, each control
unit comprising a first thin film field effect transistor and a first transparent electrode connected thereto, and a second
thin film field effect transistor and a second transparent electrode connected thereto, wherein

the control units are configured so that, upon the PDLC film structure being turned on, the first transparent electrode and
the second transparent electrode are controlled to have a same polarity, which is opposite to that of the transparent electrode
on the first substrate, by using the first thin film filed effect transistor and the second thin film field effect transistor,
respectively; and upon the PDLC film structure being turned off, the first transparent electrode and the second transparent
electrode are controlled to have different polarities by using the first thin film filed effect transistor and the second
thin film field effect transistor, respectively, causing liquid crystal molecules in the PDLC layer to return to a scattering
state.

US Pat. No. 9,429,802

DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display panel, comprising a GOA circuit, an array substrate and an opposed substrate, wherein a first conducting wire
and a second conducting wire are disposed in a region outside the GOA circuit, an insulating layer is disposed between the
first conducting wire and the second conducting wire, and the first conducting wire, the insulating layer and the second conducting
wire form a first capacitor;
the first capacitor is provided on the array substrate,
a spacer is further disposed outside the GOA circuit on the opposed substrate, a conductive layer is disposed on a surface
and periphery of the spacer, and the conductive layer is disposed opposite to a region where the first capacitor is located
on the array substrate; and

a passivation layer is further disposed on the array substrate, and the conductive layer, the passivation layer and the first
conducting wire at a corresponding position on the array substrate form a second capacitor.

US Pat. No. 9,231,564

GATE ON ARRAY DRIVER UNIT, GATE ON ARRAY DRIVER CIRCUIT, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A row driving unit on array substrate, comprising a first thin film transistor, a second thin film transistor, a third
thin film transistor, a fourth thin film transistor, and a storage capacitor, wherein:
a first end of the storage capacitor is connected with an outputting terminal for a gate driving signal of current stage;
a gate of the first thin film transistor is connected with the outputting terminal for the gate driving signal of a previous
row driving unit stage on the array substrate, a source thereof is connected with a second end of the storage capacitor, and
a drain thereof is connected with a low level outputting terminal of a driving power supply;

a gate of the second thin film transistor is connected with the source of the first thin film transistor, a source thereof
is connected with a drain of the fourth thin film transistor, and a drain thereof is connected with a first clock signal inputting
terminal;

a gate of the third thin film transistor is connected with an outputting terminal for the gate driving signal of a next row
driving unit stage on the array substrate, a drain thereof is connected with the source of the first thin film transistor,
and a source thereof is connected with a high level outputting terminal of the driving power supply;

a gate of the fourth thin film transistor is connected with a second clock signal inputting terminal, and a source thereof
is connected with the high level outputting terminal of the driving power supply;

the first end of the storage capacitor is connected with the source of the second thin film transistor, and the second end
thereof is connected with the gate of the second thin film transistor;

the gate of the first thin film transistor is an inputting terminal, the gate of the third thin film transistor is a resetting
terminal, and the source of the second thin film transistor is the outputting terminal for the gate driving signal of the
current stage;

wherein the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin
film transistor are p-type thin film transistors,

during an input sampling stage, the inputting terminal is at a low level, the resetting terminal is at a high level, the first
clock signal inputting terminal is at a high level and the second clock signal inputting terminal is at a low level, the first
thin film transistor is turned on by the low level signal applied to the gate of the first thin film transistor and the fourth
thin film transistor is turned on by the low level signal applied to the gate of the fourth thin film transistor, the outputting
terminal for the gate driving signal of the current stage outputs a high level;

during an outputting signal stage, the inputting terminal is at a high level, the resetting terminal is at a high level, the
first clock signal inputting terminal is at a low level and the second clock signal inputting terminal is at a high level,
the second thin film transistor is turned on by a low level signal applied to the gate of the second thin film transistor,
the outputting terminal for the gate driving signal of the current stage outputs a low level;

during a resetting stage, the inputting terminal is at a high level, the resetting terminal is at a low level, the first clock
signal inputting terminal is at a high level and the second clock signal inputting terminal is at a low level, the third thin
film transistor is turned on by a low level signal applied to the gate of the third thin film transistor and the fourth thin
film transistor is turned on by a low level signal applied to the gate of the fourth thin film transistor, the outputting
terminal for the gate driving signal of the current stage outputs a high level.

US Pat. No. 9,781,847

POSITIONING FRAME FOR MOUNTING A DISPLAY MODULE, DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A positioning frame for mounting a display module, comprising:
a plurality of side plates enclosing an accommodation zone for receiving the display module;
a support bed provided on at least a pair of side plates arranged opposite to each other, and connected perpendicularly with
the side plate, for supporting a display panel of the display module;

baffles corresponding to the support beds one by one, the baffles provided at a display side of the display panel, perpendicularly
connected with the side plate and arranged to be parallel with the support bed, for limiting in the normal direction of the
display panel;

limiting holes provided in the baffle and the support bed at least at one side; and
a limiting element being plugged in the limiting holes for limiting the display panel in the peripheral directions;
wherein at least at one side on which no limiting hole is provided, a width of the baffle is less than a width of the support
bed.

US Pat. No. 9,383,498

LIGHT-CONDENSING SHEET, BACKLIGHT AND LIQUID CRYSTAL DISPLAY

BEIJING BOE OPTOELECTRONI...

1. A light-condensing sheet, comprising a supporter and a plurality of flat light-condensing films provided on the supporter,
wherein
the plurality of light-condensing films are made of ultraviolet curing adhesive, and
the ultraviolet curing adhesive mainly comprises acrylic and epoxy resin; and
contents of sulfur and aromatic in the epoxy resin of the plurality of light-condensing films are different from each other,
so that refractive indexes of the plurality of light-condensing films gradually increase from bottom to top.

US Pat. No. 9,312,310

DISPLAY PANEL, FABRICATING METHOD THEREOF AND DISPLAY DEVICE

BEIJING BOE DISPLAY TECHN...

1. A display panel, comprising:
a transparent substrate;
a plurality of display pixels, provided on the transparent substrate, wherein each of the plurality of display pixels comprises:
a plurality of first transparent self-luminous sub-pixels, provided on a light exiting surface of the transparent substrate;
and

a plurality of second self-luminous sub-pixels, provided on a surface of the transparent substrate opposite to the light exiting
surface, and a light exiting direction of each of the second sub-pixels comprises a direction towards the light exiting surface
of the transparent substrate.

US Pat. No. 9,303,969

METHOD FOR DETECTING PATTERN OFFSET AMOUNT OF EXPOSED REGIONS AND DETECTING MARK

BOE TECHNOLOGY GROUP CO.,...

1. A method for detecting a pattern offset amount of exposed regions, comprising:
forming at least one pair of conductive detecting marks with a predetermined position relationship by a patterning process
including two exposing processes;

detecting an electrical characteristic of the at least one pair conductive detecting marks, if the detected electrical characteristic
does not meet a predetermined position relationship, it is determined that the pattern offset amount of the exposed regions
in two exposure steps is not qualified; and if the detected electrical characteristic meets the predetermined position relationship,
it is determined that the pattern offset amount of the exposed regions in two exposure steps is qualified,

wherein forming at least one pair conductive detecting marks with a predetermined position relationship by a patterning process
including two exposing processes comprises:

sequentially forming a first conductive thin film and a first photoresist layer on a substrate;
exposing a first region of the first photoresist layer and a periphery region of the first region, and then, developing the
exposed first photoresist layer on the substrate to obtain a first photoresist mask and etching the first conductive thin
film by using the first photoresist mask, and then removing the first photoresist mask, and thus at least one first detecting
mark formed of the first conductive thin film is formed in the periphery region of the first region;

sequentially forming a second conductive thin film and a second photoresist layer in another layer on the substrate; and
exposing a first region of the second photoresist layer and a periphery region of the first region, and then, developing the
exposed second photoresist layer on the substrate to obtain a second photoresist mask and etching the second conductive thin
film by using the second photoresist mask, and then removing the second photoresist mask, and thus at least one second detecting
mark formed of the second conductive thin film is formed in the periphery region of the first region, wherein the second detecting
mark and the first detecting mark are disposed in pair, and an insulating layer is formed between the second detecting mark
and the first detecting mark.

US Pat. No. 9,171,732

THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a thin film transistor, comprising the following steps of:
S1. forming an active layer and a source-drain electrode layer;

S2. coating a photoresist layer on the source-drain electrode layer, exposing and developing a substrate coated with the photoresist
layer to form a photoresist pattern comprising a photoresist-remained area, a photoresist-half-remained area and a photoresist-removed
area;

S3. etching by using the photoresist pattern as a mask, and etching off the source-drain electrode layer within the photoresist-removed
area;

S4. performing a two-step etching on the active layer, wherein the two-step etching comprises a first etching, which makes a
contour of the active layer below the source-drain electrode layer covered by the photoresist layer consistent with that of
the source-drain electrode layer; and a second etching, which etches the active layer within the photoresist-removed area
and ensures a longitudinal etching contour of the active layer, and forms an active layer tail; and

S5. ashing the photoresist layer such that the contour of the photoresist layer becomes consistent with that of the source-drain
electrode layer; etching the source-drain electrode layer by using the photoresist pattern as a mask to form a source-drain
electrode pattern comprising a source electrode and a drain electrode, and etching off a doped semiconductor layer between
the source electrode and the drain electrode, and meanwhile etching off the active layer tail.

US Pat. No. 9,159,448

SHIFT REGISTER UNIT, SHIFT REGISTER AND SCANNING METHOD THEREOF, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A shift register unit, comprising:
a first switch, of which the gate electrode receives a signal inputted through a first input;
a second switch, of which the source electrode is connected with the drain electrode of the first switch, and the gate electrode
receives a signal inputted through a second input;

a third switch, of which the drain electrode is connected with the source electrode of the first switch, the source electrode
receives a high level signal, and the gate electrode receives a first forward DC signal;

a fourth switch, of which the source electrode is connected with the source electrode of the third switch, and the gate electrode
receives a second reverse DC signal;

a fifth switch, of which the drain electrode is connected with the drain electrode of the third switch, the gate electrode
receives a first reverse DC signal, and the source electrode receives a low level signal;

a sixth switch, of which the source electrode is connected with the source electrode of the fifth switch, the drain electrode
is connected both with drains of the second switch and the fourth switch, and the gate electrode receives a second forward
DC signal;

a seventh switch, of which the drain electrode receives the signal inputted through the first input, and the gate electrode
receives the second reverse DC signal;

an eighth switch, of which the gate electrode is connected with the source electrode of the seventh switch, the source electrode
is connected with the source electrode of the first switch, and the drain electrode is connected with an output end;

a ninth switch, of which the drain electrode is connected with the drain electrode of the eighth switch, the gate electrode
is connected with the drain electrode of the first switch, and the source electrode receives a first clock signal;

a tenth switch, of which the source electrode and the gate electrode both receive a second clock signal;
an eleventh switch, of which the source electrode is connected with the drain electrode of the tenth switch, the gate electrode
receives a control signal, and the drain electrode receives the low level signal;

a twelfth switch, of which the gate electrode is connected with the drain electrode of the tenth switch, the drain electrode
is connected with the source electrode of the second switch, and the source electrode receives the low level signal;

a thirteenth switch, of which the gate electrode is connected with the drain electrode of the tenth switch, and the drain
electrode receives the low level signal;

a fourteenth switch, of which the source electrode is connected with the source electrode of the thirteenth switch and the
output end, and the drain electrode is connected with the drain electrode of the sixth switch;

a fifteenth switch, of which the source electrode is connected with the gate electrode of the fourteenth switch, the drain
electrode receives the signal inputted through the second input, and the gate electrode receives the second forward DC signal;
and

a capacitor positioned between a first node and a second node, wherein the first node is connected to the drain of the first
switch, and the second node is connected to the output end.

US Pat. No. 9,445,506

PREPARATION METHOD OF PATTERNED FILM, DISPLAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A preparation method of a patterned film, wherein the method comprises:
forming a preset film layer on a surface of a preset substrate, the material constituting the preset film layer being silver
nanowire;

forming an isolation layer on a surface of the preset film layer;
forming a photoresist layer on a surface of the isolation layer and forming a pattern of the isolation layer with a patterning
process;

removing the preset film layer which is not covered by the pattern of the isolation layer; and
peeling off the photoresist layer, removing the pattern of the isolation layer to form a pattern of the preset film layer.

US Pat. No. 9,196,631

ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing an array substrate comprising:
a step of forming a gate metal layer, wherein the gate metal layer comprises gate lines;
a step of film-forming an active layer and a step of film-forming a signal line metal layer, wherein the signal line metal
layer comprises data lines; and

a step of forming both a pattern of the active layer and a pattern of the signal line metal layer simultaneously using a half-tone
mask process, wherein after the step of film-forming an active layer and before the step of film-forming a signal line metal
layer,

the method further comprises a step of:
hollowing out a first region of the active layer through a patterning process,
wherein the first region is below the data lines in a display area, and the first region excludes portions of the active layer
corresponding to overlapping regions of the data lines and the gate lines.

US Pat. No. 9,196,735

THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor, comprising:
a substrate;
a gate electrode, a source electrode, at least two drain electrodes and a semiconductor layer;
a gate electrode protection layer located between the gate electrode and the semiconductor layer; and
an etch stopping layer located between the semiconductor layer and the source electrode, the drain electrode,
wherein, the source electrode and the drain electrodes are respectively connected with the semiconductor layer by different
via holes, and

wherein the thin film transistor comprises a first drain electrode, a second drain electrode and a third drain electrode,
wherein the first drain electrode, the second drain electrode and the source electrode are arranged in a straight line or
in such a way that the electrodes are taken as three vertices of a isosceles triangle, and the second drain electrode, the
third drain electrode and the source electrode are also arranged in the same way.

US Pat. No. 9,136,088

DETECTION APPARATUS AND OPERATING METHOD

BOE TECHNOLOGY GROUP CO.,...

1. A detection apparatus, comprising
a test chamber provided with a signal wire connection member therein,
an exchange chamber,
a communicating mechanism, which is provided between the test chamber and the exchange chamber and capable of rendering the
test chamber and the exchange chamber separated from or communicated with each other;

a probe frame provided within the test chamber; and
a supporting bracket provided within the test chamber and matching a shape of the probe frame;
wherein transmission devices are positioned within the test chamber and the exchange chamber, respectively, and the transmission
devices are adapted to convey a probe frame from the test chamber to the exchange chamber or from the exchange chamber to
the test chamber,

the probe frame is configured to be detachably mounted on the supporting bracket and detachably connected to the signal wire
connection member provided within the test chamber; and the transmission device within the test chamber comprises a transmission
part configured for conveying the probe frame onto the supporting bracket.

US Pat. No. 9,354,465

COLOR FILTER SUBSTRATE, LIQUID CRYSTAL DISPLAY PANEL AND DISPERSING METHOD OF MONOCOLOR QUANTUM DOTS

BOE TECHNOLOGY GROUP CO.,...

1. A color filter substrate comprising:
a base substrate;
a plurality of pixels provided on the base substrate, each comprised of a plurality of sub-pixels of different colors; and
a layered structure containing monocolor quantum dots disposed in areas corresponding to sub-pixels of at least one color
of pixels, and the layered structure comprising an alternate lamination of flake graphene layers and monocolor quantum dot
layers,

wherein a bottom layer and a top layer of the layered structure are both flake graphene layers; and the monocolor quantum
dots emit monochromatic light corresponding to a color of the sub-pixels after being excited.

US Pat. No. 9,357,637

FLEXIBLE SUBSTRATE, SUPPORT PLATFORM, FLEXIBLE DISPLAY AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A flexible substrate for a flexible LCD display, wherein a plurality of spacers are arranged at intervals on one side of
the flexible substrate opposing a side on which a structure for pixel display is formed, wherein the distance between any
two adjacent ones of the plurality of spacers is from 10 to 500 ?m, and
wherein the spacers are arranged in an array, and each of the spacers has a cuboid structure with a height thereof ranging
from 0.25 to 10 ?m.

US Pat. No. 9,219,082

ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate comprising a thin film transistor, the thin film transistor comprises a source electrode, a gate electrode
and a drain electrode, wherein the gate electrode is located on a first metal layer, and the source electrode and the drain
electrode are located on a second metal layer, wherein:
the shapes of the source electrode and the gate electrode are configured so that when dislocation occurs between the first
metal layer and the second metal layer, the area of the overlapping region between the source electrode and the gate electrode
keeps constant,

wherein the source electrode comprises an overlapping region with the gate electrode, and a first part region and a second
part region located on the two sides of the gate electrode respectively in a direction parallel to a gate line;

when dislocation occurs between the first metal layer and the second metal layer, a bottom area of the first part region is
increased while a bottom area of the second part region is decreased; or a bottom area of the first part region is decreased
while a bottom area of the second part region is increased;

an increased/decreased bottom area of the first part region equals to a decreased/increased bottom area of the second part
region.

US Pat. No. 9,907,204

HEAT DISSIPATION DEVICE AND WORKING METHOD THEREOF, DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A heat dissipation device, applied to a display device, comprising a temperature monitoring unit, a control unit, a movement
unit, and a plurality of heat dissipation fans, wherein:
the temperature monitoring unit monitors an environment temperature of each predetermined region of the display device;
the control unit is connected to the temperature monitoring unit, and determines to-be-cooled regions according to a monitoring
result of the temperature monitoring unit and then send a control instruction to the movement unit, wherein the control unit
determines the to-be-cooled regions by:

comparing the environment temperatures of the predetermined regions detected by the temperature monitoring unit with a predetermined
threshold value, and determine the predetermined regions of which the environment temperatures are higher than the predetermined
threshold value as high-temperature regions;

determining all the high-temperature regions as the to-be-cooled regions when an amount of the high-temperature regions is
not larger than an amount M of the plurality of heat dissipation fans; and

ranking priorities of all the high-temperature regions according to the environment temperatures of the high-temperature regions
and/or importance thereof and determine M high-temperature regions with highest priority as the to-be-cooled regions when
the amount of the high-temperature regions is larger than the amount M of the plurality of heat dissipation fans;

the movement unit is connected to the control unit, and moves the plurality of heat dissipation fans to the to-be-cooled regions
to be cooled in response to the control instruction; and

the plurality of heat dissipation fans are connected to the movement unit.

US Pat. No. 9,459,743

TOUCH SENSING CIRCUIT, TOUCH SENSING METHOD, TOUCH SENSING PANEL AND TOUCH SENSING DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A touch sensing circuit, comprising a first gate line, a second gate line, data lines, a signal transmission line and a
common electrode, the first gate line, the second gate line and the data lines define a plurality of pixel units, each of
the pixel units is provided with a first switch tube and a second switch tube, the first switch tube is connected to the data
lines, the second switch tube is connected to the signal transmission line, and the signal transmission line is connected
to a signal processor which is used for judging whether a touch action is performed according to the change in a signal; wherein
the touch sensitive circuit further comprises a third switch tube, the third switch tube is connected in series between the
first switch tube and the second switch tube; and

a first node is formed at a junction of the first switch tube and the third switch tube, a second node is formed at a junction
of the second switch tube and the third switch tube, a first fixed capacitor is formed between the first node and the common
electrode, and a second variable capacitor is formed between the second node and the common electrode.

US Pat. No. 9,461,489

MOBILE COMMUNICATION TERMINAL

BOE Technology Group Co.,...

1. A mobile communication terminal comprising:
a thermoelectric conversion unit comprising a conversion device for converting heat energy into electric energy; and
an energy storage unit electrically connected to the conversion device and configured to store the electric energy generated
by the conversion device, wherein the conversion device comprises a plurality of superposed carbon nano-tube films, and areas
of the carbon nano-tube films become smaller gradually in a direction perpendicular to surfaces of the carbon nano-tube films.

US Pat. No. 9,425,770

GATE DRIVING CIRCUIT, DISPLAY MODULE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A gate driving circuit for driving gates of Thin Film Transistors TFTs corresponding to gate lines connected thereto, including:
at least two stages of shift registers connected in cascade,
wherein each stage of shift register includes a first output terminal and a second output terminal,
wherein the first output terminal is connected to an enable signal input terminal of a next stage of shift register so as
to output a next stage enable signal to the next stage of shift register, and the second output terminal is connected to a
corresponding gate line so as to apply a gate driving signal on the gates of TFTs through the corresponding gate line,

wherein each stage of shift register includes a pull-up unit connected to a pull-up node, a first clock signal terminal, the
first output terminal and the second output terminal, respectively, for, when a pull-up signal at a high level is detected,
outputting a next stage enable signal to the next stage of shift register through the first output terminal and outputting
the gate driving signal to the corresponding gate line through the second output terminal according to an first clock signal
acquired;

each stage of shift register further includes a pull-down unit connected to the pull-up node, a pull-down node, a second clock
signal terminal and a low voltage maintaining terminal, respectively, for pulling-down a potential of the second output terminal
and the potential of the pull-up node when a pull-down signal at a high level is detected and for pulling-down the potential
of the second output terminal when a second clock signal at a high level is detected, wherein the second clock signal and
the first clock signal are inverted to each other;

each stage of shift register further includes a pull-down driving unit connected to the pull-down node, the pull-up node,
the low voltage maintaining terminal and the second clock signal terminal, respectively, for outputting the pull-down signal
at the high level when the second clock signal at the high level and the pull-up signal at a low level are detected.

US Pat. No. 9,242,266

ALIGNMENT FILM PRINTING DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An alignment film printing device for applying alignment film on a substrate, comprising at least one printing unit, and
the printing unit each comprising:
a cylinder body, with an opening at a bottom and an extract opening provided on a top of the cylinder body;
a vacuum extractor, connected with the extract opening;
a plunger, provided inside the cylinder body and configured to draw an alignment fluid from the opening to the cylinder body;
a vacuum tester, provided at the extract opening and configured to monitor a vacuum degree inside the cylinder body and above
the plunger;

a range finder, provided inside the cylinder body and configured to monitor a distance from the plunger to the top of the
cylinder body; and

a control device, in signal communication with the vacuum extractor, the vacuum tester and the range finder respectively and
configured to control a volume of the alignment fluid drawn into the cylinder body according to test values of the vacuum
tester and the range finder.

US Pat. No. 9,235,058

POLARIZATION-TYPE THREE-DIMENSIONAL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A polarization-type three-dimensional display device, comprising:
a liquid crystal panel, comprising:
an array substrate and a color filter substrate disposed opposite to each other, the color filter substrate comprising a plurality
of black matrix strips disposed on a side of it facing the array substrate; and

a liquid crystal layer, located between the array substrate and the color filter substrate;
a phase difference structure, located on a light-exiting side of the liquid crystal panel, wherein a plurality of patterned
phase difference diaphragms are arranged on the phase difference structure;

a plurality of light-shielding strips, disposed on a side of the array substrate far away from the liquid crystal layer,
wherein, orthographic projections of the plurality of light-shielding strips on the phase difference structure cover boundary
lines of the patterned phase difference diaphragms on the phase difference structure, and orthographic projections of the
plurality of black matrix strips on the phase difference structure cover the boundary lines of the patterned phase difference
diaphragms on the phase difference structure.

US Pat. No. 9,159,867

ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:
a base substrate;
a gate line and a gate electrode formed on the base substrate;
a gate insulating layer formed on the gate line and the gate electrode;
a source electrode, a drain electrode and a pixel electrode formed on the gate insulating layer, wherein the pixel electrode
is directly connected to the drain electrode; and

an active layer formed on the gate insulating layer, the source electrode and the drain electrode;
a passivation layer formed on the source electrode, the drain electrode and the active layer, wherein a through hole is formed
in the passivation layer; and

a data line formed on the passivation layer, wherein the data line extends perpendicular to the gate line and the data line
is connected to the source electrode via the through hole.

US Pat. No. 9,146,344

BACKLIGHT MODULE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A backlight module, comprising a light source and a backplate which comprises a baseplate and a side plate surrounding
edges of the baseplate, wherein the light source is provided on the side plate, and the baseplate is formed by jointing a
plurality of sub-baseplates with different heat conductivities together, so that heat generated by radiation of the light
source is circulated and led out.

US Pat. No. 9,445,033

METHOD FOR DETECTING ROTATION ANGLE OF REMOTE CONTROLLER IN TELEVISION SYSTEM AND TELEVISION SYSTEM

BOE Technology Group Co.,...

1. A method for detecting a rotation angle of a remote controller in a television system including a television and the remote
controller, wherein the method comprises:
collecting, by the remote controller, an image of preset infrared sensors on the television and imaging the collected image
to a preset plane as a standard image, in a case in which the remote controller does not rotate with respect to the television;

collecting, by the remote controller, an image of the infrared sensors on the television and imaging the collected image to
the preset plane again, in a case in which the remote controller rotates with respect to the television; and

calculating a rotation angle in a case in which the remote controller rotates with respect to a screen of the television by
comparing the image with the standard image.

US Pat. No. 9,374,025

CONTROL CIRCUIT AND ELECTRICAL DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A control circuit comprising:
a first power supply comprising a high-level output and a low-level output;
a first circuit comprising two inputs, a driver module and at least two braking switch units, the two inputs being respectively
connected to the high-level output and the low-level output of the first power supply, and the driver module being in series
connected to the at least two braking switch units, wherein the driver module comprises two outputs that which are the outputs
of the control circuit;

braking circuits corresponding to the braking switch units in a one to one manner and configured to control switching states
of the braking switch units; and

a second power supply comprising a high-level output and a low-level output,
wherein each of the braking circuits comprises two inputs that are respectively connected to the high-level output and the
low-level output of the second power supply.

US Pat. No. 9,275,589

GATE DRIVE CIRCUIT, ARRAY SUBSTRATE AND DISPLAY APPARATUS

BOE Technology Group Co.,...

1. A gate drive circuit, comprising:
a plurality of shift register units each having a signal output end, wherein the signal output end of one of the plurality
of shift register units except the last one is connected to the signal input end of the next one;

L arithmetic units each having a plurality of input ends, wherein L is an integer equal to or larger than 2, and one of the
plurality of input ends of each of the L arithmetic units is connected to the signal output end of a respective shift register
unit; and

a clock generation unit having a plurality of clock output ends for outputting different clock signals, wherein at least one
of the plurality of clock output ends is connected to at least one of the other input ends of a respective arithmetic unit
except the one input end connected to the signal output end of the shift register unit, so that the L arithmetic units output
L different drive signals,

wherein the clock generation unit comprising:
a sub clock generation unit configured to generate m different first clock signals and output the m first clock signals through
m first clock output ends of the plurality of clock output ends, wherein m is an integer equal to or larger than 1 and less
than L; and

a sub shift register unit connected to the sub clock generation unit and configured to shift the m first clock signals generated
by the sub clock generation unit so as to generate (L?m) different second clock signals and output the (L?m) different second
clock signals through (L?m) second clock output ends of the plurality of clock output ends,

wherein at least one of the first clock output ends and the second clock output ends is connected to the at least one of the
other input ends of each of the L arithmetic unit, so that L clock output ends of the clock generation unit consist of first
clock output ends of the sub clock generation unit and second clock output ends of the sub shift register unit.

US Pat. No. 9,240,141

PIXEL UNIT DRIVING CIRCUIT, PIXEL UNIT DRIVING METHOD AND PIXEL UNIT

BOE TECHNOLOGY GROUP CO.,...

1. A pixel unit driving circuit for driving OLED, including: a driving thin Film Transistor TFT, a matching TFT, a first switching
element, a storage capacitor and a driving control unit; wherein the driving control unit includes a second switching element
and a third switching element, the first switching element, the second switching element and the third switching element are
different from each other,
the driving TFT has a gate connected to a first terminal of the storage capacitor, a source connected to the OLED and connected
to a second terminal of the storage capacitor through the first switching element, and a drain connected to a driving power
source;

the matching TFT has a gate and a drain connected to the gate of the driving TFT, and a source connected to the source of
the driving TFT through the second switching unit; and

the second terminal of the storage capacitor is also connected to a data line through the third switching unit.

US Pat. No. 9,229,286

ARRAY SUBSTRATE, MANUFACTURING METHOD FOR THE SAME AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising a first data shorting bar formed on a gate metal layer and a second data shorting bar formed
on a data metal layer, wherein the array substrate further comprises:
a first conductive strip, being configured to be coupled to the first data shorting bar, wherein the width of the first conductive
strip is greater than a+c+d; and

a second conductive strip, being configured to be coupled to the second data shorting bar and not overlapped with the first
data shorting bar, wherein the width of the second conductive strip is greater than b;

where a is the width of the first data shorting bar, b is the width of the second data shorting bar, c is the width of the
second conductive strip, and d is the horizontal space between the second conductive strip and the first data shorting bar.

US Pat. No. 9,223,154

DISPLAY DEVICE HAVING A CUBOID BIREFRINGENT CRYSTAL LAYER

BOE TECHNOLOGY GROUP Co.,...

1. A display device, comprising:
a first substrate;
a first polarizer which is disposed below the first substrate and parallel to the first substrate;
a second polarizer, which is disposed above the first substrate and parallel to the first substrate;
a first electrode and a second electrode, which are disposed between the first substrate and the second polarizer;
an electrically controlled birefringence crystal layer, which is disposed between the first electrode and the second electrode,
actualizes display and has a primary electro-optic effect, wherein the crystal is single-axis crystal, the crystal layer has
the shape of a cuboid, and a thickness of the cuboid is larger than a width of the cuboid;

further comprising:
a backlight source, which is disposed below the first polarizer and parallel to the first polarizer, wherein the backlight
source is a RGB light source, and adopts a field sequential control mode to achieve color display;

the first electrode and the second electrode are disposed in accordance with a state where a direction of an electric field
is parallel or perpendicular to the first substrate; and the electric field is an electric field generated between the first
electrode and the second electrode; the electrically controlled birefringence crystal layer actualizes display under the action
of the electric field;

in case of an electric field being parallel to the first substrate, an optical axis of the crystal is parallel to the first
substrate, a size of a driving voltage is in an inversely proportional relationship with a primary electric-optic coefficient
of a crystal material, and is in an inversely proportional relationship with a thickness-to-width ratio (l/d) of the crystal;

in case of an electric field being perpendicular to the first substrate, an optical axis of the crystal is perpendicular to
the first substrate, and a size of a driving voltage is in an inversely proportional relationship with a primary electric-optic
coefficient of the crystal material.

US Pat. No. 9,883,600

DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display device, comprising a display panel, and further comprising a supporting structure for accommodating and fixing
the display panel, and a seat disposed below the supporting structure, wherein the supporting structure is formed as a single
member, and is provided with an opening at a side opposite to the seat, and the display panel is allowed to be inserted into
the supporting structure through the opening, and the seat is configured to lock the display panel into the supporting structure.

US Pat. No. 9,423,902

AMOLED PIXEL CIRCUIT, A DRIVING METHOD THEREOF AND A DISPLAY DEVICE

Chengdu BOE Optoelectroni...

1. An AMOLED pixel circuit, comprising:
a light emitting module,
a touching module,
a controlling module, and
a driving and amplifying module;
the light emitting module is connected with the controlling module and a first voltage terminal and is used for performing
light emitting display under the control of the controlling module;

the touching module is connected with the controlling module and a first signal line and is used for receiving an input touch
signal;

the controlling module is connected with the first signal line, a second signal line, a third signal line and a data line,
and is used for controlling the light emitting module and the touching module under input signals of the signal lines, wherein
the controlling module includes

a first transistor which has a gate connected to the first signal line and a first electrode connected to the light emitting
device;

a second transistor has a gate connected to the second signal line, a first electrode connected to a second electrode of the
first transistor, and a second electrode connected to the data line;

a third transistor which has a gate connected to the third signal line, a first electrode connected to the driving and amplifying
module, and a second electrode connected to the data line; and

a fourth transistor which has a gate connected to the first signal line, a first electrode connected to the second electrode
of the first transistor, and a second electrode connected to the driving and amplifying module; and

the driving and amplifying module is connected with the light emitting module, the touching module, the controlling module
and a second voltage terminal, and is used for driving the light emitting module and amplifying the touch signals received
by the touching module.

US Pat. No. 9,298,330

CAPACITIVE TOUCH PANEL HAVING COMPLEMENTARILY MATCHING ADJACENT ELECTRODE UNITS AND DISPLAY DEVICE INCLUDING THE CAPACITIVE TOUCH PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A capacitive touch panel, comprising at least one column of electrode set, the electrode set comprising a plurality of
electrode units which are sequentially arranged, and adjacent electrode units complementarily matching each other, wherein
each electrode unit comprises a first touch electrode, a second touch electrode and a third touch electrode, the first touch
electrode, the second touch electrode and the third touch electrode complementarily match each other, and the first touch
electrode is used for keeping patterns of the second touch electrode and the third touch electrode included in the same electrode
unit from contacting with each other, the second touch electrode is used for keeping a pattern of the electrode unit from
contacting with a pattern of an immediately previous electrode unit, the third touch electrode is used for keeping the pattern
of the electrode unit from contacting with a pattern of an immediately next electrode unit, and the first touch electrode,
the second touch electrode, and the third touch electrode have the same length in a direction perpendicular to a column direction.

US Pat. No. 9,298,034

LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A liquid crystal display device, comprising: a color filter substrate, an array substrate, an upper polarizing sheet arranged
at a side of the color filter substrate and a lower polarizing sheet arranged at a side of the array substrate; wherein:
the color filter substrate comprises a first graduated scale and a second graduated scale, the array substrate comprises a
third graduated scale and a fourth graduated scale, and the first graduated scale, the second graduated scale, the third graduated
scale and the fourth graduated scale are arranged within a non-display region;

the first graduated scale is configured to measure a distance of at least one first edge of a plurality of first edges, which
are parallel with each other, of the upper polarizing sheet to an edge of the color filter substrate closer to the at least
one first edge; and the second graduated scale is configured to measure a distance of at least one second edge of a plurality
of second edges, which are parallel with each other, of the upper polarizing sheet to an edge of the color filter substrate
closer to the at least one second edge; and

the third graduated scale is configured to measure a distance of at least one third edge of a plurality of third edges, which
are parallel with each other, of the lower polarizing sheet to an edge of the array substrate closer to the at least one third
edge; and, the fourth graduated scale is configured to measure a distance of at least one fourth edge of a plurality of fourth
edges, which are parallel with each other, of the lower polarizing sheet to an edge of the array substrate closer to the at
least one fourth edge.

US Pat. No. 9,285,938

ORGANIC LIGHT-EMITTING DIODE PIXEL CIRCUIT, DRIVING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An organic light emitting dioxide (OLED) pixel circuit, comprising a data writing unit, a driving unit, an OLED, a first
control unit, a second control unit and a touch detecting unit, wherein,
the first control unit, in a touch detecting stage and an OLED light-emitting stage, is used for importing a power supply
voltage signal into the data writing unit under the control of a scanning line, and, in the OLED light-emitting stage, is
used for turning on the OLED and the driving unit;

the data writing unit, in the touch detecting stage and the OLED light-emitting stage, is used for importing the power supply
voltage signal under the control of a first light-emitting control line, and importing a data line signal under the control
of the scanning line and a second light-emitting control line, and meanwhile is used for supplying voltage to the driving
unit;

the touch detecting unit, in the touch detecting stage, is used for sensing touch under the control of a touch signal level
control line, and generating a detecting signal;

the driving unit, in the touch detecting stage, is used for converting the detecting signal into a touch output signal, which
is output to a driving integrated circuit (IC) via the touch detecting unit, under the control of the touch signal level control
line, and in the OLED light-emitting stage, is used for providing driving current for the OLED; and

the second control unit, in the OLED light-emitting stage, is used for connecting the driving unit to a ground level under
the control of a third light-emitting control line.

US Pat. No. 9,222,860

TAPPING HAMMER FOR TAPPING TEST

BOE Technology Group Co.,...

1. A tapping hammer for tapping test, comprising a hammerhead and a handle supporting the hammerhead, the tapping hammer further
comprises an alarm, a power source and a conductor, wherein,
a hollowed-out region is provided in interior of the hammerhead and the hammerhead is elastically deformable, the hammerhead
is electrically connected to a first electrode of the power source;

the conductor is fixed in the interior hollowed-out region of the hammerhead, the conductor is not electrically connected
to the hammerhead while no tapping force is exerted on the hammerhead, and the conductor is electrically connected to the
hammerhead while a tapping force larger than a certain amount is exerted on the hammerhead; and

a first electrode of the alarm is connected to the conductor, a second electrode of the alarm is connected to a second electrode
of the power source.

US Pat. No. 9,217,818

POLARIZER, DISPLAY DEVICE AND MANUFACTURING METHOD OF POLARIZER

BOE TECHNOLOGY GROUP CO.,...

1. A polarizer, comprising:
a transparent substrate, on a main surface of which a plurality of grooves in parallel with each other are provided at an
interval, the grooves being directly formed in the transparent substrate, and a part of the transparent substrate between
the grooves and a part of the transparent substrate below the grooves being integrally formed;

a birefringence crystal layer with a single orientation formed on the main surface of the transparent substrate where the
grooves are provided,

wherein, the birefringence crystal layer is at least filled in the grooves so that linearly polarized light incident on a
location corresponding to the grooves, along a direction perpendicular to the main surface of the transparent substrate, and
passing through the polarizer is converted into first polarized light, and linearly polarized light incident on a location
between the grooves, along the direction perpendicular to the main surface of the transparent substrate, and passing through
the polarizer is converted into second polarized light, and polarization directions of the first polarized light and the second
polarized light are different from each other,

wherein, the birefringence layer is provided at the grooves and on the part of the transparent substrate between the grooves,
a thickness of the birefringence layer at the grooves is equivalent to a thickness of a three-quarter wave plate corresponding
to light to be transmitted, a thickness of the birefringence crystal layer on the part between the grooves is equivalent to
a thickness of a quarter wave plate corresponding to the light to be transmitted; and

the first and second polarized light are circularly polarized light.

US Pat. No. 9,448,445

ELECTRODE STRUCTURE AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate comprising a plurality of electrode structures, wherein each electrode structure comprises an introduction
electrode and a body electrode, and a first isolating layer and a second isolating layer arranged between the introduction
electrode and the body electrode, in which a first via hole is formed in the first isolating layer, a second via hole is formed
in the second isolating layer, and a hole axis of the first via hole and a hole axis of the second via hole are on a same
straight line passing through the body electrode, so that a part of the body electrode is exposed via the first via hole and
the second via hole; and in which the introduction electrode is electrically connected with the body electrode through the
part of the body electrode exposed via the first via hole and the second via hole, wherein a diameter of the first via hole
is smaller than that of the second via hole, and the first isolating layer extends to completely cover the hole wall of the
second via hole,
wherein the array substrate comprises a display area and a non-display area, the electrode structures are arranged in the
non-display area and comprise a first electrode structure and a second electrode structure, and

wherein the introduction electrode in the first electrode structure is used for introducing a gate line test signal, and the
introduction electrode in the second electrode structure is used for introducing a data line test signal.

US Pat. No. 9,434,036

REPLACING MECHANISM FOR RUBBING ROLLERS IN RUBBING EQUIPMENT

BOE Technology Group Co.,...

1. A replacing mechanism for replacing rubbing rollers of rubbing equipment, the rubbing equipment comprising pressing devices
for:
taking down worn rubbing rollers from the rubbing equipment and putting the worn rubbing rollers into vacant placement grooves
of one stage, and/or

taking out new rubbing rollers from placement grooves of the stage, in which the new rubbing rollers are placed, and installing
the new rubbing rollers on the rubbing equipment,

the replacing mechanism further comprising:
the one stage, which has the placement grooves for holding the rubbing rollers, an exchange placement platform for conveying
the stage to a rubbing roller replacing area,

an exchange unit for:
taking out the stage from a transport vehicle and placing the stage onto the exchange placement platform, and/or
taking out the stage from the exchange placement platform and placing the stage onto the transport vehicle, and
the replacing mechanism further comprising a connecting device for releasably connecting the exchange placement platform and
a rubbing platform of the rubbing equipment,

wherein the stage is provided with ones of the placement grooves arranged in parallel, the number of which is larger than
that of the pressing devices of the rubbing equipment.

US Pat. No. 9,368,520

ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:
a base substrate, on which a plurality of gate lines and a plurality of data lines are provided;
shielding electrodes, which are provided above and electrically insulated from the data lines, the shielding electrodes at
least partially covering the data lines;

first electrodes, which are provided in the same layer as the shielding electrodes and are electrically insulated from the
shielding electrodes; and

second electrodes, which are provided above and electrically insulated from the first electrodes, wherein,
the shielding electrodes are applied with a shielding voltage signal, the second electrodes are applied with a stable voltage
signal, and no electric field or weak electric filed is formed between the shielding electrodes and the second electrodes;
and

each data line comprises a plurality of data line bodies and a plurality of connection parts, each connection part is used
for connecting two adjacent data line bodies, the array substrate further comprises a first insulation layer, which is provided
above the gate lines, wherein,

the data line bodies and the gate lines are provided in the same layer, and the connection parts connect every two adjacent
data line bodies in the data lines through via holes penetrating through the first insulation layer.

US Pat. No. 9,252,163

ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. An array substrate, comprising:
a pad area;
signal lines, arranged on the pad area; and
conductive connection lines, arranged at least on the pad area and directly connected to a flexible circuit,
wherein the conductive connection lines are connected to the signal lines through a via hole, and comprise a first wire and
a second wire electrically connected to each other;

wherein the second wire is arranged in such a manner that a contact area between the conductive connection lines and the flexible
circuit is not less than a predetermined threshold when the flexible circuit is displaced in a first direction relative to
the first wire; and

wherein the first direction is substantially perpendicular to an extending direction of the first wire.

US Pat. No. 9,247,613

QUANTUM DOT ELECTROLUMINESCENCE DISPLAY DEVICE AND DISPLAY APPARATUS

BEIJING BOE OPTOELECTRONI...

1. A quantum dot electroluminescence display device provided with a plurality of pixel units provided therein, each of which
comprises a plurality of sub-pixel units for displaying different colors, the display device comprising:
a base substrate;
an electroluminescence structure, disposed on the base substrate and located at the sub-pixel units of each pixel unit;
a monochromatic quantum dot layer, which is disposed in at least one sub-pixel unit of a color of each pixel unit and is located
on a light exiting side of the electroluminescence structure of the at least one sub-pixel unit of a color, for emitting monochromatic
light corresponding to the color of the sub-pixel unit after it is excited by light emitted from the electroluminescence structure,
wherein the quantum dots in the monochromatic quantum dot layer are configured to have a scattering function.

US Pat. No. 9,223,198

MASK PLATE AND MANUFACTURING METHOD THEREOF

HEFEI BOE OPTOELECTRONICS...

1. A mask plate comprising a mask plate body and a transmissive member, wherein the mask plate body has a transmissive part
and a non-transmissive part adjacent to the transmissive part, the transmissive member is disposed corresponding to the transmissive
part of the mask plate body, the absorbance of the transmissive member progressively increases in a direction away from a
center region of the transmissive member to an edge region of the transmissive member which is closer to the non-transmissive
part with regard to the center region of the transmissive member.

US Pat. No. 9,877,372

DRIVING CIRCUIT AND DRIVING METHOD OF ORGANIC LIGHT EMITTING DIODE

BOE TECHNOLOGY GROUP CO.,...

1. A driving circuit of an organic light emitting diode comprising:
an electricity storage unit, the polarity of a first terminal of which is positive, and the polarity of a second terminal
of which is negative;

a signal input unit, a first terminal and a second terminal of which input signals of opposite polarities to the driving circuit
respectively, the signal polarities of the first and second terminals of the signal input unit being changed in accordance
with a preset frequency;

a control unit, which causes the first terminal of the signal input unit to transmit negative charges to the anode of the
organic light emitting diode and causes the second terminal of the signal input unit to transmit positive charges to the cathode
of the organic light emitting diode, when the signal polarity at the first terminal of the signal input unit is negative and
the signal polarity at the second terminal thereof is positive,

and causes the first terminal of the electricity storage unit to transmit positive charges to the anode of the organic light
emitting diode and causes the second terminal of the electricity storage unit to transmit negative charges to the cathode
of the organic light emitting diode, when the signal polarity at the first terminal of the signal input unit is positive and
the signal polarity of the second terminal thereof is negative.

US Pat. No. 9,564,260

METHOD FOR PREPARING A SILICON DIOXIDE SUBSTRATE-BASED GRAPHENE TRANSPARENT CONDUCTIVE FILM

BOE TECHNOLOGY GROUP CO.,...

1. A method for preparing a silicon dioxide substrate-based graphene transparent conductive film, which prepares a silicon
dioxide substrate on a graphene transparent conductive film, and thereby obtains the silicon dioxide substrate-based graphene
transparent conductive film,
wherein the preparing step comprises:
(1) a graphene transparent conductive film preparation step of preparing the graphene transparent conductive film on a metal
substrate to form a first substrate;

(2) a silicon dioxide substrate preparation step of preparing the silicon dioxide substrate on the graphene transparent conductive
film so as to obtain a laminated structure that consists of the metal substrate, the graphene transparent conductive film,
and the silicon dioxide substrate which are sequentially arranged; and

(3) an etching step of etching off the metal substrate, thereby obtaining the silicon dioxide substrate-based graphene transparent
conductive film.

US Pat. No. 9,366,923

ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, including a base substrate and pixel units arranged in a matrix-type manner on the base substrate,
a thin film transistor, a fist electrode and a second electrode being provided in the pixel unit, the thin film transistor
including a gate, a first insulation layer, an active layer, a source and a drain, wherein
the array substrate further includes:
a black matrix provided above the first electrode and covering a non-display region of each pixel unit;
a second insulation layer for allowing the black matrix and the first electrode to be insulated from the thin film transistor,
a covering region of the second insulation layer being overlapped with covering regions of the black matrix and the first
electrode; and

a passivation layer provided above a layer at which the thin film transistor locates and below the second electrode and covering
a region above the thin film transistor.

US Pat. No. 9,323,127

ACTIVE SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An electrophoretic display device, comprising:
an active substrate comprising;
a first substrate;
a pixel exectrode layer formed on the first substrate;
a color filter layer formed on the pixel electrode layer;
a protective layer formed on the color filter layer, wherein:
the color filter layer comprises a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit that are sequentially
arranged;

a material of the red sub-pixel unit is a quantum dot material that emits red light when excited by an ambient light;
a material of the green sub-pixel unit is a quantum dot material that emits green light when excited by the ambient light;
and

a material of the blue sub-pixel unit is a quantum dot material that emits blue light when excited by the ambient light;
an upper substrate arranged opposite to the active substrate;
a control wall formed on the active substrate, wherein the control wall is electrically connected with the pixel electrode
layer and extends to the upper substrate; and

an insulating wall that is formed outside the control wall and surrounds the control wall;
wherein:
the control wall, the upper substrate and the active substrate construct a plurality of cavities,
each of the cavities corresponds to a region that corresponds to one of the red sub-pixel unit, the green sub-pixel unit and
the blue sub-pixel unit,

a microcapsule is provided in each of the cavities, and
the microcapsule is filled with a transparent fluid and electrophoretic particles that are moveable in the transparent fluid.

US Pat. No. 9,318,508

ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME, DISPLAY

BOE Technology Group Co.,...

1. An array substrate, comprising:
a substrate;
a metal pattern formed on the substrate;
an insulation layer formed on the metal pattern and formed with a via therein; and
a transparent conductive pattern formed on the insulation layer and electrically connected to the metal pattern through the
via,

wherein the via has a cross section exhibiting an irregular geometry shape which having a curved side edge,
wherein the metal pattern comprises a first metal pattern and a second metal pattern; and
wherein the via comprises a first via corresponding to the first metal pattern and a second via corresponding to the second
metal pattern.

US Pat. No. 9,293,340

SURFACE PLANARIZATION METHOD OF THIN FILM AND PREPARING METHOD OF ARRAY SUBSTRATE

BEIJING BOE OPTOELECTRONI...

1. A surface planarization method of thin films, comprising:
patterning a non-metallic layer located above a first film layer by dry etching in an apparatus with a dry-etching working
gas configured for the dry etching, wherein the dry etching causes the first film layer to be exposed with a rough surface;
and

planarizing the exposed first film layer to smooth the rough surface of the exposed first film layer to be planar, wherein
planarizing the exposed first film layer comprises:

introducing into the same apparatus configured for the dry etching a chemically reactive gas that is different from the dry-etching
working gas,

wherein the chemically reactive gas reacts with the exposed first film layer to generate volatile substances so that the rough
surface of the exposed first film layer is planarized.

US Pat. No. 9,209,405

COMPOUND WITH BRANCHING ALKYL CHAINS, METHOD FOR PREPARING THE SAME, AND USE THEREOF IN PHOTOELECTRIC DEVICE

PEKING UNIVERSITY, Beiji...

1. A Formula (II) polymer:

wherein Ar1 and Ar2 represent different aromatic compound fragments; n is an integer which represents the polymerization degree of the polymer;
m is an integer of from 3 to 18; R3 and R4 are the same or different, independently selected from alkyl, halogen substituted alkyl, alkoxy, halogen substituted alkoxy,
alkenyl and alkynyl; and R5 is hydrogen, hydroxyl, alkyl, halogen substituted alkyl, alkoxy, halogen substituted alkoxy, alkenyl or alkynyl.

US Pat. No. 9,123,586

ARRAY SUBSTRATE, METHOD FOR FABRICATING THE SAME AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate comprising:
a substrate,
a gate electrode, a gate insulating layer as well as an active layer, and a source/drain metal layer formed on the substrate,
the source/drain metal layer is configured for forming a source electrode, a drain electrode and a channel region, wherein
a region of the S/D metal layer for forming the channel region is at a lower height than other region of the S/D metal layer
for forming the source electrode and the drain electrode.

US Pat. No. 9,888,590

PRINTED CIRCUIT BOARD, DISPLAY PANEL AND WIRING METHOD FOR PRINTED CIRCUIT BOARD

BOE TECHNOLOGY GROUP CO.,...

1. A printed circuit board, comprising:
a first multichannel circuit connecting terminal having a plurality of first channel connecting pins;
a second multichannel circuit connecting terminal having a plurality of second channel connecting pins, the plurality of second
channel connecting pins being arranged to face the plurality of first channel connecting pins, the number of the first channel
connecting pins being larger than the number of the second channel connecting pins and a length of the second multichannel
circuit connecting terminal being larger than a length of the first multichannel circuit connecting terminal; and

a plurality of connecting wires arranged between the first multichannel circuit connecting terminal and the second multichannel
circuit connecting terminal, the plurality of connecting wires connecting the plurality of second channel connecting pins
with a part of the first channel connecting pins in one-to-one correspondence, with the rest of the first channel connecting
pins being spare,

wherein at least one of the plurality of connecting wires has a first portion, which is bent to extend through a spare region,
on the printed circuit board, between the spare first channel connecting pins and the second multichannel circuit connecting
terminal.

US Pat. No. 9,429,811

DISPLAY PANEL AND DISPLAY METHOD THEREOF AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A display panel, comprising:
a first transparent substrate and a second transparent substrate opposed to each other;
a plurality of double sided light emitting pixel units located between the first transparent substrate and the second transparent
substrate and arranged in a matrix;

a plurality of first electrophoresis units located outside of the first transparent substrate and corresponding to odd numbered
rows of the pixel units one by one;

a plurality of second electrophoresis units located outside of the second transparent substrate and corresponding to even
numbered rows of the pixel units one by one,

wherein each of the first electrophoresis units and the second electrophoresis units comprises a plurality of electrophoresis
particles having a first arrangement mode and a second arrangement mode, and

wherein in response to the electrophoresis particles in any first one electrophoresis unit of the first electrophoresis units
and the second electrophoresis units being in the first arrangement mode, the first one electrophoresis unit reflects a light
emitted from the pixel unit corresponding to the first one electrophoresis unit, while in response to the electrophoresis
particles in any second one electrophoresis unit of the first electrophoresis units and the second electrophoresis units being
in the second arrangement mode, the second one electrophoresis unit absorbs an ambient light passing through the pixel unit
corresponding to the second one electrophoresis unit.

US Pat. No. 9,236,022

GATE DRIVING CIRCUIT, SWITCHING CONTROL CIRCUIT AND SHIFT REGISTER OF DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A gate driving circuit of a display device, comprising:
multiple stages of shift register units, being configured to be sequentially coupled, wherein each of the multiple stages
of shift register units is coupled to a row of gate line;

a first switch control circuit, being configured to be respectively coupled to each of the multiple stages of shift register
units, input a pull-up signal to each of the multiple stages of shift register units under the control of a forward signal,
and control each of the multiple stages of shift register units to turn on in a forward sequence;

a second switch control circuit, being configured to be respectively coupled to each of the multiple stages of shift register
units, input a reset signal to each of the multiple stages of shift register units under the control of a backward signal,
and control each of the multiple stages of shift register units to turn on in a backward sequence;

a first thin film transistor (TFT), being configured to input a start signal to a first stage of shift register unit among
the multiple stages of shift register units under the control of the forward signal; and

a second TFT, being configured to input the start signal to the last stage of shift register unit among the multiple stages
of shift register units under the control of the backward signal,

wherein the first TFT and the second TFT are external to each of the multiple stages of shift register units.

US Pat. No. 9,572,270

DETACHABLE DISPLAY MODULE AND DISPLAY DEVICE COMPRISING THE SAME

BOE Technology Group Co.,...

1. A detachable display module, comprising: a front frame, a display screen and a back plate; wherein
a plurality of COFs are provided on each of four sides of the display screen, the plurality of COFs provided on each side
of the display screen are connected to at least one printed circuit board, and the printed circuit board is provided on a
rear surface of the display screen;

the front frame is fixedly connected with the display screen, and the front frame comprises: a first frame and a third frame
disposed opposite to each other, a second frame and a fourth frame disposed opposite to each other, wherein the first frame
is detachably and fixedly connected with the second frame and the fourth frame through bridge connection pieces, the third
frame is detachably and fixedly connected with the back plate, and the first frame, the second frame, the third frame and
the fourth frame each have a recess regions for accommodating the plurality of COFs; and

the back plate is provided on the rear surface of the display screen, and the back plate is provided with a recess portion
corresponding to the printed circuit board provided between the back plate and the display screen.

US Pat. No. 9,470,949

ELECTROPHORETIC DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

CHENGDU BOE OPTOELECTRONI...

1. An electrophoretic display (EPD) device, comprising an electrophoretic substrate and a drive substrate arranged opposite
to each other and a plurality of microcups disposed between the electrophoretic substrate and the drive substrate,
wherein each microcup includes a cup body for defining an accommodating space; a thickness of the cup body on one side of
the microcup closer to the electrophoretic substrate is less than a thickness of the cup body on one side of the microcup
closer to the drive substrate; and a cup surface of the microcup is a cambered surface which is away from a vertical central
axis of the microcup and concave towards the cup body, wherein

the cup body is formed by a plurality of partition walls arranged in an array; upper surfaces and lower surfaces of the partition
walls are parallel to each other; and both the two side-walls of the partition wall are cambered surfaces, and

a height of the partition walls is ranged from 1 to 10 micrometers; and a radius of the cambered surface of the two side-walls
of the partition walls is ranged from 4 to 10 micrometers.

US Pat. No. 9,337,217

DISPLAY DEVICE WITH BARRIER LAYER DISPOSED AT PRE-CUTTING POSITION AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A display device comprising:
an array substrate;
an opposite substrate;
sealant frames between the array substrate and the opposite substrate, wherein a pre-cutting position is disposed between
two adjacent the sealant frames; and

a barrier layer between the array substrate and the opposite substrate and at a position corresponding to the pre-cutting
position,

wherein a material forming the barrier layer has an elongation at fracture smaller than that of a material forming the sealant
frames, and the barrier layer comprises a first sub-barrier layer corresponding to the pre-cutting position and a second sub-barrier
layer corresponding to the pre-cutting position, which are disposed on the opposite substrate and the array substrate respectively.

US Pat. No. 9,324,764

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:
a terminal region; and
an active pixel region, the active pixel region comprising:
a plurality of pixel units;
a plurality of gate lines;
a plurality of data lines; and
a plurality of gate leading wires,
wherein two columns of the plurality of pixel units are provided between two adjacent data lines among the plurality of data
lines, each of the plurality of gate leading wires is disposed between the two columns of the plurality of pixel units, and
each of the plurality of gate lines is connected to respective one of the plurality of gate leading wires,

wherein two of the plurality of gate leading wires are provided between the two columns of the plurality of pixel units,
wherein the array substrate further comprises a dummy line, the dummy line is disposed between the two columns of the pixel
units and is a leading wire not being connected to every gate line of the plurality of gate lines, the number of the dummy
line disposed between the two columns of the pixel units is two,

the dummy line is floated.

US Pat. No. 9,310,948

ARRAY SUBSTRATE, TOUCH SCREEN PANEL AND DISPLAY DEVICE

ORDOS YUANSHENG OPTOELECT...

1. An array substrate comprising a plurality of gate lines, a plurality of data lines, a plurality of touch sensing units,
wherein each of the touch sensing units comprising a touch scanning line and a touch sensing line intersecting each other,
a first transistor and a sensing electrode, the touch scanning line is connected with a gate and a drain electrode of the
first transistor, and the sensing electrode is connected with a source electrode of the first transistor;
the touch sensing line and the sensing electrode are spaced apart by an insulating layer and have an overlapping region.

US Pat. No. 9,269,316

SHIFT REGISTER, GATE DRIVING DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE

BOE Technology Group Co.,...

1. A shift register, comprising a driving module, an output module, a first pull-down module and a second pull-down module;
wherein the driving module is connected to the output module; the first pull-down module is connected to the driving module,
the output module and a second level signal input terminal; the second pull-down module is connected to the driving module,
the output module and the second level signal input terminal;

wherein a connection point of the driving module, the output module, the first pull-down module and the second pull-down module
is a pull-up node, a connection point of the first pull-down module and the driving module is a first pull-down node, a connection
point of the first pull-down module and the output module is a control signal output terminal of the shift register; a connection
point of the second pull-down module and the driving module is a second pull-down node, and a connection point of the second
pull-down module and the output module is the control signal output terminal of the shift register;

wherein the driving module is configured to control the pull-up node to be at a first level and control the first pull-down
node and the second pull-down node to be at a second level when a selection signal received is at the first level or changed
from the first level to the second level, and to control a signal at the first pull-down node to be same as a clock signal
and control a signal at the second pull-down node to be same as a clock block signal when the pull-up node is at the second
level;

the output module is configured to connect the control signal output terminal of the shift register and a clock signal input
terminal under the control of the signal at the pull-up node;

the first pull-down module is configured to connect the pull-up node and the second level signal input terminal and connect
the control signal output terminal of the shift register and the second level signal input terminal when the signal at the
first pull-down node is at the first level;

the second pull-down module is configured to connect the pull-up node and the second level signal input terminal and connect
the control signal output terminal of the shift register and the second level signal input terminal when the signal at the
second pull-down node is at the first level.

US Pat. No. 9,190,427

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising a base substrate, a gate line, a data line, and a pixel region defined by intersection of
the gate line and the data line, which are formed on the base substrate, wherein the pixel region comprises a thin film transistor,
and the thin film transistor comprises a gate, a gate insulation layer, an active layer, a source and a drain, wherein the
pixel region further comprises:
at least one groove, formed on a surface of the base substrate;
a first electrode layer, comprising at least one first electrode bar, wherein the at least one first electrode bar is disposed
in the corresponding groove and electrically connected with each other; and

a second electrode layer, comprising at least one second electrode bar, wherein the second electrode bar is disposed outside
the groove and electrically connected with each other.

US Pat. No. 9,171,519

METHOD AND DEVICE FOR DRIVING LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY

BOE Technology Group Co.,...

1. A driving method for a Liquid Crystal Display (LCD) panel, comprising:
compensating a voltage on a data line according to a pixel value of each of pixels on the LCD panel corresponding to an image
to be displayed; and

inputting the compensated voltage on the data line to the data line, and driving the LCD panel for display;
wherein compensating the voltage on the data line according to the pixel value of each of pixels on the LCD panel corresponding
to the image to be displayed comprises:

acquiring the pixel value of each of pixels corresponding to the image to be displayed and an actual voltage supplied to the
data line from a source driving unit;

performing compensation according to a set of compensating voltages as preset and the actual voltage on the data line, wherein
the set of compensating voltages is a preset set of values of compensating voltages of data lines corresponding to various
pixel values of each of pixels on the LCD panel;

wherein the set of compensating voltages is a set comprising a product of compensating voltage coefficient of each of pixels
multiplied by each of pixel values of each of pixels respectively, wherein the compensating voltage coefficient of each of
pixels represents the quotient obtained from a difference value between a theoretical voltage on the data line and the actual
voltage on the data line corresponding to a specific pixel value of each of pixels divided by a maximum pixel value of each
of pixel.

US Pat. No. 9,366,914

LIQUID CRYSTAL PANEL AND LIQUID CRYSTAL DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A liquid crystal panel comprising a color filter substrate and an array substrate which are bonded, wherein a gate shift
register is provided on a side of the array substrate facing the color filter substrate, a conductive electrode connecting
a gate electrode and source/drain electrodes is provided in a wiring region of the gate shift register, and a common electrode
is provided on a side of the color filter substrate facing the array substrate, and wherein the liquid crystal panel further
includes:
an insulating layer located between the conductive electrode and the common electrode, a projection of the insulating layer
on the side of the array substrate facing the color filter substrate covering a projection of the conductive electrode on
the side of the array substrate facing the color filter substrate, and

wherein a projection of a sealant on the side of the array substrate facing the color filter substrate and the projection
of the insulating layer on the side of the array substrate facing the color filter substrate have overlaying regions.

US Pat. No. 9,054,345

PIXEL DEFINING LAYER, PREPARATION METHOD THEREOF, ORGANIC LIGHT-EMITTING DIODE SUBSTRATE AND DISPLAY

BOE TECHNOLOGY GROUP CO.,...

1. A method for preparing a pixel defining layer (PDL), comprising the following steps:
step 1: forming a mixed solution on a substrate to form a mixed solution film, in which the mixed solution includes a solvent,
and a hydrophilic material and a hydrophobic material dissolved in the solvent;

step 2: performing a heat treatment on the mixed solution film to form a pixel defining material layer in which a content
of the hydrophilic material on an upper portion is less than that of the hydrophilic material on a lower portion and a content
of the hydrophobic material on the upper portion is more than that of the hydrophobic material on the lower portion; and

step 3: forming a pattern of the PDL by a patterning process.

US Pat. No. 10,018,768

LIGHT GUIDE PLATE ASSEMBLY, SIDE-TYPE BACKLIGHT SOURCE MODULE AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A light guide plate assembly, comprising:a first substrate which is transparent and positioned on a light-emitting side of the light guide plate assembly;
a second substrate which is disposed opposite to the first substrate; and
a plurality of light modulation units which are disposed between the first substrate and the second substrate, wherein each of the light modulation units comprises:
a first electrode which is transparent and is disposed adjacent to the first substrate;
a second electrode which is disposed adjacent to the second substrate, wherein the first electrode and the second electrode are configured to generate an electric field therebetween; and
an electrophoretic capsule layer which is disposed between the first electrode and the second electrode and comprises an electrophoretic capsule containing white electrophoretic particles and black electrophoretic particles which are dispersed in transparent dispersing medium and are oppositely charged.

US Pat. No. 9,355,838

OXIDE TFT AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A method of manufacturing an oxide thin film transistor, comprising: forming a conductive film on a substrate and forming
a gate electrode by a patterning process; forming an insulation film on the substrate to cover the gate electrode and function
as a gate insulation layer; forming an oxide film on the gate insulation layer and forming an active layer comprising a source
region, a drain region and a channel by a patterning process,
wherein the method further comprises:
sequentially forming a lower metal film and an upper metal film on the active layer, forming a source electrode and a drain
electrode by performing a patterning process on the upper metal film which is away from the active layer, and remaining the
lower metal film which is adjacent to the active layer, and

wherein the lower metal film functions as an etching barrier layer, the etching barrier layer covering the active layer and
the gate insulation layer;

wherein the etching barrier layer comprises a channel protective layer, the channel protective layer is located on the channel
and corresponds to a position of the channel, and the channel protective layer is formed by performing an oxidation treatment
on the lower metal film;

wherein the etching barrier layer is provided below the source and drain electrodes and covers both upper surface and side
surface of the active layer and further covers a portion of the gate insulation layer on which the active layer is not formed,
and

wherein the oxidation treatment is an oxygen plasma oxidation treatment, and an oxygen plasma employed in the oxygen plasma
oxidation treatment is a mixed gas of O2 and BCl2.

US Pat. No. 9,269,289

SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS

BOE Technology Group Co.,...

1. A shift register unit including an input terminal, an output terminal, a first clock signal input terminal, a second clock
signal input terminal, a low potential connecting terminal and a reset terminal, the shift register unit further consisting
of:
a first Thin Film Transistor TFT having a first electrode connected to the input terminal and a gate connected to the second
clock signal input terminal;

a second TFT having a first electrode connected to the second electrode of the first TFT, a gate connected to the reset terminal,
and a second electrode connected to the low potential connecting terminal;

a third TFT having a second electrode connected to the output terminal, a first electrode connected to the first clock signal
input terminal, and a gate connected to a second electrode of the first TFT;

a fourth TFT having a first electrode connected to the output terminal, a gate connected to the reset terminal, and a second
electrode connected to the low potential connecting terminal;

a fifth TFT having a gate directly connected to the second clock signal input terminal, a first electrode directly connected
to the output terminal, and a second electrode connected to the low potential connecting terminal; and

a capacitor connected between the gate and the second electrode of the third TFT;
wherein a first clock signal input from the first clock signal input terminal and a second clock signal input from the second
clock signal input terminal have a same period and are inverted to each other.

US Pat. No. 9,196,569

BONDING PAD OF ARRAY SUBSTRATE, METHOD FOR PRODUCING THE SAME, ARRAY SUBSTRATE, AND LIQUID CRYSTAL DISPLAY APPARATUS

Boe Technology Group CO.,...

1. An array substrate, comprising:
a gate electrode formed on a substrate;
a first insulation layer formed on the gate electrode;
a first conductive layer formed on the first insulation layer;
a source electrode or drain electrode formed on the first conductive layer;
a second insulation layer formed on the source electrode or drain electrode; and
a second conductive layer formed on the second insulation layer,
wherein the second insulation layer is formed with a bonding pad via through which the second conductive layer is electrically
connected to the first conductive layer,

wherein the second conductive layer is separated from the source electrode or drain electrode by the second insulation layer
and does not contact with the source electrode or drain electrode, and

wherein the source electrode or drain electrode has a longitudinal direction and a lateral direction, and the source electrode
or drain electrode is transversely cut off by the bonding pad via at a position of the source electrode or drain electrode
in the longitudinal direction, such that the source electrode or drain electrode is divided into separate segments.

US Pat. No. 9,449,542

GATE DRIVING CIRCUIT, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A gate driving circuit comprising multi-stage shift registers, and each stage shift register of the multi-stage shift registers
is coupled with both of a first clock signal line and a second clock signal line;
wherein, for any integer N which is not less than 2, an input terminal of an N-th stage shift register is coupled with an
output terminal of an (N?1)-th stage shift register; an output terminal of the N-th stage shift register is coupled with an
input terminal of an (N+1)-th stage shift register; a reset terminal of the N-th stage shift register is coupled with an output
terminal of an (N+2)-th stage shift register;

the gate driving circuit further comprises an output side switch element disposed between the input terminal and the output
terminal of the N-th stage shift register;

the output terminal of the N-th stage shift register is coupled with a second terminal of the output side switch element;
a first terminal of the output side switch element is coupled with the input terminal of the N-th stage shift register; a
control terminal of the output side switch element is coupled with the second clock signal line.

US Pat. No. 9,443,472

PIXEL CIRCUIT AND DISPLAY

BOE TECHNOLOGY GROUP CO.,...

1. A pixel circuit comprising a first pixel sub-circuit and a second pixel sub-circuit different from the first pixel sub-circuit,
and an initialization module and a data voltage writing module connected to the first pixel sub-circuit and the second pixel
sub-circuit, wherein
the initialization module is connected to a reset signal terminal and a low level terminal, and is configured to initialize
the first pixel sub-circuit and the second pixel sub-circuit under the control of a reset signal input at the reset signal
terminal; and

the data voltage writing module is connected to a data voltage terminal and a gate signal terminal, and is configured, under
the control of a signal input at the gate signal terminal, to firstly write a first data voltage to the first pixel sub-circuit,
and then write a second data voltage to the second pixel sub-circuit;

wherein while the first data voltage is written to the first pixel sub-circuit, the first pixel sub-circuit performs compensation
on a first driving module of the first pixel sub-circuit; and while the second data voltage is written to the second pixel
sub-circuit, the second pixel sub-circuit performs compensation on a second driving module of the second pixel sub-circuit;

wherein after the first data voltage is written into the first pixel sub-circuit and the second data voltage is written into
the second pixel sub-circuit, the first pixel sub-circuit and the second pixel sub-circuit emit light concurrently.

US Pat. No. 9,383,488

COLOR FILTER SUBSTRATE, MANUFACTURING METHOD THEREFOR AND 3D DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A color filter substrate comprising
a substrate,
a color filter unit, and
a lenticular lens structure which is disposed between the substrate and the color filter unit, wherein the lenticular lens
structure is a single-layer lenticular lens array, which is composed of a plurality of lenticular lenses arranged in a planar
direction where the color filer unit is located; and

each lenticular lens consists of two kinds of lenses having different refractive indexes,
wherein the two kinds of lenses having different refractive indexes include a first lens and a second lens in order from the
substrate to the color filter unit; the refractive index of the first lens is smaller than that of the second lens and larger
than or equal to that of the substrate,

wherein the first lens is a plane-concave lens, and the second lens is a plane-convex lens, said plane-convex lens is correspondingly
embedded in the plane-concave lens;

wherein a thickness H of the plane-convex lens is obtained by:

where n1 is the refractive index of the plane-convex lens, n2 is the refractive index of the plane-concave lens, and p is the size of the color filter resin, and

wherein a thickness h of the plane-concave lens is obtained by:

where Wp is the interpupillary distance of human eyes, D is the distance between human eyes and the display device, ? is the
incident angle of the light emitted from the side of the plane-concave lens to the interface between the plane-concave lens
and the substrate, and the emergent angle of the light is refraction angle ?.

US Pat. No. 9,311,892

ELECTRONIC PAPER DISPLAY DEVICE AND DRIVING METHOD

BOE TECHNOLOGY GROUP CO.,...

1. A driving method of all electronic paper display device, comprising: with a driving device, obtaining grayscale levels
of each pixel in the electronic paper display device from an input video data signal, and determining a sequence and time
intervals for turning-on of thin film transistors in each pixel according to the number N of the thin film transistors contained
in the pixel and the grayscale levels of the pixel, so as to form a grayscale display scheme, wherein the thin film transistors
in each pixel are connected to a same pixel electrode of the pixel, and the same pixel electrode electrically connects the
at least two thin film transistors together; applying a signal voltage to a data line corresponding to each thin film transistor
of each pixel in accordance with the formed grayscale display scheme while a turning-on voltage is applied to a gate line
corresponding to each thin film transistor of each pixel, so as to drive the pixel electrode of each pixel to present its
grayscale levels, respectfully, wherein the thin film transistors in each pixel are connected to different data lines, and
signal voltages applied to the thin film transistors in each pixel are different while in a same polarity, wherein applying
of the signal voltages to the data line corresponding to each thin film transistor of each pixel in accordance with the formed
grayscale display scheme comprises: applying groups of signal voltages of differently set magnitudes to data lines corresponding
to the thin film transistors of each pixel in accordance with the formed grayscale display scheme, so as to drive each pixel
to present its grayscale levels, separately, wherein the groups of signal voltages of differently set magnitudes are 0V, ±10V,
±15V or ±30V, wherein for a first row of pixels that corresponds to a first gate line and a second gate line and includes
a first group of thin film transistors and a second group of thin film transistors; a first turning-on voltage is applied
to the first group of thin film transistors though the first gate line; and a second turning-on voltage is applied to the
second group of thin film transistors through the second gate line; wherein for a second row of pixels adjacent to the first
row of pixels that corresponds to a third gate line and a fourth gate line and includes a third group of thin film transistors
and a fourth group of thin film transistors: a third turning-on voltage is applied to the third group of thin film transistors
through the third gate line; and a fourth turning-on voltage is applied to the fourth group of thin film transistors through
the fourth gate line, the third gate line and the fourth gate line being different from the first gate line and the second
gate line, wherein: for a first column of pixels that corresponds to a first data line and a second data line and includes
a fifth group of thin film transistors and a sixth group of thin film transistors: a first signal voltage is applied to the
fifth group of thin film transistors through the first data line; and a second signal voltage is applied to the sixth group
of thin film transistors through the second data line; and for a second column of pixels adjacent to the first column of pixels
that corresponds to a third data line and a fourth data line and includes seventh group of thin film transistors and an eighth
group of thin film transistors: a third signal voltage is applied to the seventh group of thin film transistors through the
third data line; and a fourth signal voltage is applied to the eighth group of thin film transistors through the fourth data
line, the third data line and the fourth data line being different from the first data line and the second data line, and
wherein N is a natural number, and N?2.

US Pat. No. 9,490,029

SHIFT REGISTER UNIT, GATE DRIVING APPARATUS AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A shift register unit comprising a capacitor, wherein one terminal of the capacitor is connected with an outputting node
at a present stage, and the other terminal of the capacitor is connected with a pulling-up node, and the shift register unit
further comprises:
a first thin film field effect transistor, a drain thereof connected with a first signal terminal, a source thereof connected
with the outputting node at the present stage, a gate thereof connected with a first node; wherein the first signal terminal
is configured to output a low potential signal when the first thin film field effect transistor is turned on;

a second thin film field effect transistor, a drain thereof connected with the first signal terminal, a source thereof connected
with the pulling-up node, and a gate thereof connected with the first node; wherein the first signal terminal is configured
to output the low potential signal when the second thin film field effect transistor is turned on;

a third thin film field effect transistor, a drain thereof connected with a second signal terminal, a source thereof connected
with the outputting node at the present stage, and a gate thereof connected with a second node; wherein the second signal
terminal is configured to output the low potential signal when the third thin film field effect transistor is turned on;

a fourth thin film field effect transistor, a drain thereof connected with the second signal terminal, a source thereof connected
with the pulling-up node, and a gate thereof connected with the second node; wherein the second signal terminal is configured
to output the low potential signal when the fourth thin film field effect transistor is turned on; and

a node voltage control module, configured to control the first node and the second node to be in a high potential state alternatively
when the shift register unit is in a pulling-down phase; and

a first resetting unit configured to output the low potential signal to the pulling-up node and the outputting node at the
present stage under a control of a reset signal, wherein the first resetting unit comprises:

a first resetting thin film field effect transistor, a source thereof configured to receive a first clock control signal,
a drain thereof connected with the first node, and a gate thereof configured to receive the reset signal; and

a second resetting thin film field effect transistor, a source thereof configured to receive a second clock control signal,
a drain thereof connected with the second node, and a gate thereof configured to receive the reset signal;

wherein the node voltage control module comprises a first node voltage control sub-module, and the first node voltage control
sub-module comprises:

a fifth thin film field effect transistor, a source and a gate thereof configured to receive the first clock control signal,
and a drain thereof connected with the first node; and

a sixth thin film field effect transistor, a drain thereof configured to receive the low potential signal, a source thereof
connected with the second node, and a gate thereof configured to receive the first clock control signal.