US Pat. No. 9,820,401

PACKAGED RF POWER TRANSISTOR DEVICE HAVING NEXT TO EACH OTHER A GROUND AND A VIDEO LEAD FOR CONNECTING A DECOUPLING CAPACITOR, RF POWER AMPLIFIER

Ampleon Netherlands B.V.,...

1. A packaged Radio Frequency power transistor device, in particular for use in a power amplifier operating in the frequency
range from DC up to 3 GHz, the packaged Radio Frequency power transistor device comprising:
a component carrier,
a die comprising a semiconductor transistor having a source, a gate and a drain, wherein the die is mounted at the component
carrier,

a ground lead extending from the component carrier and electrically connected to the source,
an output lead extending from the component carrier and electrically connected to the drain,
a resonance circuit being electrically inserted between the drain and the ground lead,
a video lead extending from the component carrier and electrically connected to the resonance circuit, wherein the video lead
is configured for being connected to a first contact of a decoupling capacitor, wherein

the ground lead is configured for being connected to a second contact of the decoupling capacitor, and wherein the ground
lead and the video lead are spatially arranged next to each other, and

a further ground lead extending from the component carrier, wherein the video lead is arranged in between the ground lead
and the further ground lead.

US Pat. No. 9,406,659

TRANSISTOR ARRANGEMENT

Ampleon Netherlands B.V.,...

1. A transistor arrangement comprising;
an electrically conductive substrate;
a semiconductor body including a transistor structure, the transistor structure including a source terminal connected to said
electrically conductive substrate;

a bond pad providing a connection to the transistor structure configured to receive a bond wire, wherein the semiconductor
body includes an RF-return current path configured to carry a return current associated with said bond wire, said RF-return
current path comprising a strip of metal arranged on said semiconductor body, said RF-return current strip configured such
that it extends beneath said bond pad and is connected to said source terminal of the transistor structure.

US Pat. No. 9,496,836

DOHERTY AMPLIFIER

Ampleon Netherlands B.V.,...

1. A Doherty amplifier comprising:
a main amplifier;
at least one peaking amplifier;
an input network connecting the Doherty amplifier input to the input of the main amplifier and to the input of the at least
one peaking amplifier; and

an output network connecting an output of the main amplifier and an output of the at least one peaking amplifier to an output
of the Doherty amplifier,

wherein the output network comprises at least one first series phase shifting element between the output of the main amplifier
and a combining node, and at least one second series phase shifting element between the output of the peaking amplifier and
the combining node, the output network further comprising an output match arranged in between the combining node and the output
of the Doherty amplifier, and

wherein the peaking amplifier includes a peaking power transistor and the main amplifier includes a main power transistor,
wherein a different drain bias is applied to the peaking power transistor than is applied to the main power transistor;

wherein the first series phase shifting element comprises a transmission line having a predefined characteristic impedance
and configured for introducing a phase shift of 90 degrees at a frequency of interest and the second series phase shifting
element comprises a transmission line having a predefined characteristic impedance and configured for introducing a phase
shift of 180 degrees at the frequency of interest;

wherein an impedance transformation by the second series phase shifting element is essentially independent from input power
supplied to the Doherty amplifier.

US Pat. No. 9,786,640

TRANSISTOR ARRANGEMENT

Ampleon Netherlands B.V.,...

1. A transistor arrangement comprising:
an electrically conductive substrate;
a semiconductor body including a transistor structure, the transistor structure including a source terminal connected to said
electrically conductive substrate; and

a bond pad providing a connection to the transistor structure configured to receive a bond wire, wherein the semiconductor
body includes an RF-return current path configured to carry a return current associated with said bond wire, said RF-return
current path comprising a strip of metal arranged on said semiconductor body, said RF-return current strip configured such
that it is connected to said source terminal of the transistor structure.

US Pat. No. 9,450,283

POWER DEVICE AND A METHOD FOR CONTROLLING A POWER DEVICE

Ampleon Netherlands B.V.,...

1. A power device comprising:
a transistor;
a lumped element capacitance inductive capacitance analog of a transmission line configured to form an output matching circuit
for the transistor, said analog of a transmission line having a first port and a second port, wherein the first port is coupled
to an output of the transistor; and

a directional coupler inductively coupled to said analog of a transmission line configured to form a power sensor for the
transistor, wherein the power sensor comprises a third port and a fourth port;

wherein an inductive element of said analog of a transmission line is formed by plurality of bonding wires, the power device
further comprising a first capacitance between the first port and ground and a second capacitance between the second port
and ground;

wherein the directional coupler is a lumped element inductive capacitance coupler;
wherein an inductive element of the directional coupler is a bonding wiring that is inductively coupled to said plurality
of bonding wires, the power device further comprising a third capacitance between the third port and the second port, a fourth
capacitance between the third port and ground, a fifth capacitance between the first port and the fourth port, and a sixth
capacitance between the fourth port and ground;

wherein the fourth port of the directional coupler is configured to provide an indication of power reflected from a load coupled
to the second port.

US Pat. No. 9,450,545

DUAL-BAND SEMICONDUCTOR RF AMPLIFIER DEVICE

Ampleon Netherlands B.V.,...

1. A dual-band semiconductor RF amplifier device, the device comprising
a transistor having an output capacitance,
a first shunt element arranged in parallel with the output capacitance, the first shunt element comprising a first shunt inductor
connected in series with a first shunt capacitor, and

a second shunt element arranged in parallel with the first shunt capacitor, the second shunt element comprising a second shunt
inductor connected in series with a second shunt capacitor,

wherein the dual-band semiconductor RF amplifier device is configured to be able to operate at a first operating frequency
and a second operating frequency, said second operating frequency being smaller than said first operating frequency,

wherein a capacitance of the second shunt capacitor is such that it forms a short at both the first and second operating frequency,
wherein the first shunt inductor, the second shunt inductor, and the first shunt capacitor are configured to form an inductance
that resonates with the output capacitance at both the first and second operating frequency.

US Pat. No. 9,413,308

RF POWER DEVICE

Ampleon Netherlands B.V.,...

1. A RF power device for amplifying RF signals comprising:
a flange,
an input lead,
an output lead,
an input matching network comprising an input matching die having a first terminal coupled to the input lead by a plurality
of bond-wires and a second terminal coupled to the flange,

an active die mounted on the flange, the active die comprising at least one power transistor, at least one input terminal
and at least one output terminal respectively coupled to the input lead and the output lead by a plurality of bond-wires

an output matching network comprising an output matching die having a first terminal coupled to the at least one output terminal
by a plurality of bond-wires and a second terminal coupled to the flange, and

at least one capacitance element connected to one of the input lead and the output lead and wherein in operation the at least
one capacitance element modifies the impedance of a portion of the respective one of the input lead and the output lead, wherein
the input lead and the output lead at least partially overlap the flange and the at least one capacitance element comprises
a conductive pillar partially spanning a gap between the flange and a surface of one of the input lead and the output lead.

US Pat. No. 9,325,280

MULTI-WAY DOHERTY AMPLIFIER

Ampleon Netherlands B.V.,...

1. An electronic circuit with a multi-way Doherty amplifier, wherein the multi-way Doherty amplifier comprises:
a two-way Doherty amplifier comprising a main stage and a first peak stage that are integrated in a semiconductor device;
at least one further peak stage implemented in a separate semiconductor device,
a first half-wavelength line connecting an output of the Doherty amplifier to an output node, and
a second half-wavelength line connecting an output of the at least one further peak stage to the output node.

US Pat. No. 9,362,871

WIDEBAND AMPLIFIER

AMPLEON NETHERLANDS B.V.,...

1. A Doherty amplifier, comprising:
an RF signal input;
an RF signal output;
a main amplifier portion and a peak amplifier portion,
wherein the main and peak amplifiers portions each include:
a first amplifier;
a second amplifier,
a first phase shifter;
a second phase shifter;
a third phase shifter;
a fourth phase shifter;
wherein the first and second amplifiers each include an input terminal coupled to the RF signal input and an output terminal,
wherein within each of the portions,
the first phase shifter is coupled to the output terminal of the first amplifier
the second phase shifter is coupled to the output terminal of the second amplifier;
the third phase shifter is coupled to the first phase shifter; and
the fourth phase shifter coupled to the second phase shifter;
wherein the Doherty amplifier further comprises a first combining node and a second combining node,
wherein each portion's third phase shifter is coupled to the first combining node;
wherein each portion's fourth phase shifter is coupled to the second combining node, and
wherein the RF signal output is coupled to the first combining node and the second combining node.

US Pat. No. 9,768,736

POWER AMPLIFIER CELL

Ampleon Netherlands B.V.,...

1. A power amplifier cell comprising:
a first input terminal configured to receive a first-balanced-input-signal;
a second input terminal configured to receive a second-balanced-input-signal;
an output terminal;
a reference terminal;
a first power amplifier having:
a first-PA-input-terminal connected to the first input terminal; and
a first-PA-output-terminal;
the first power amplifier having an associated first-PA-output-capacitance;
a second power amplifier having:
a second-PA-input-terminal connected to the second input terminal; and
a second-PA-output-terminal;
the second power amplifier having an associated second-PA-output-capacitance;
a balun comprising:
a first balanced node connected to the first-PA-output-terminal;
a second balanced node connected to the second-PA-output-terminal;
an unbalanced node connected to the output terminal;
a first transmission line with a first end and a second end, the second end of the first transmission line connected to the
unbalanced node;

a second transmission line with a first end and a second end, wherein the second transmission line is capacitively and/or
inductively coupled to the first transmission line, the first end of the second transmission line is connected to the first
balanced node, and the second end of the second transmission line is connected to the reference terminal;

a third transmission line with a first end and a second end, wherein the first end of the third transmission line is connected
to the first end of the first transmission line, and the second end of the third transmission line is connected to the reference
terminal;

a fourth transmission line with a first end and a second end, wherein the first end of the fourth transmission line is connected
to the second balanced node, the fourth transmission line is capacitively and/or inductively coupled to the third transmission
line, and the second end of the fourth transmission line is connected to the reference terminal; and

a tuning component connected between the first balanced node and the second balanced node;
each of the first power amplifier and the second power amplifier being associated with a predefined load parameter (Ropt)
corresponding to a desired substantially resistive load seen at the first-PA-output-terminal and the second-PA-output-terminal,
respectively, at a predefined operational frequency assuming that the first-PA-output-capacitance and the second-PA-output-capacitance
are not present;

the balun and the tuning component being designed such that:
an impedance between the first balanced node and the second balanced node of the balun (Zdiff), when said balun is terminated
by a predefined impedance (Zsingle) connected in between the unbalanced node and the reference terminal, substantially equals
said predefined impedance (Zsingle) at the operational frequency;

said impedance between the first balanced node and the second balanced node of the balun substantially equaling two times
the predefined load parameter (Ropt); and

the balun being designed at substantially two times the predefined load parameter at the operational frequency;
said tuning component at least in large part being formed by the first-PA-output-capacitance and the second-PA-output-capacitance.

US Pat. No. 9,444,421

COMBINER CIRCUIT FOR A CLASS-E OUTPHASING POWER AMPLIFIER

Ampleon Netherlands B.V.,...

1. A combiner circuit for a class-E outphasing power amplifier comprising first and second branch amplifiers, the combiner
circuit comprising:
a first input node, for receiving an output signal of the first branch amplifier;
a second input node, for receiving an output signal of the second branch amplifier;
an output node, for supplying a combined output signal to a load;
a first inductor connected in series at the first input node, the first inductor having an input terminal connected to the
first input node and an output terminal;

a second inductor connected in series at the second input node, the second inductor having an input terminal connected to
the second input node and an output terminal;

a compensation inductor connected in series with the first inductor and directly connected to the output node;
a compensation capacitor connected in series with the second inductor and directly connected to the output node;
a first capacitor, with a first terminal connected to the output terminal of the first inductor and a second terminal connected
to ground; and

a second capacitor, with a first terminal connected the output terminal of the second inductor and a second terminal connected
to ground;

wherein the second capacitor and the compensation capacitor are implemented as Metal-Insulator-Metal capacitors together on
a single die, and wherein each of the capacitors and/or inductors is implemented as a lumped element component.

US Pat. No. 9,324,674

DIE SUBSTRATE ASSEMBLY AND METHOD

Ampleon Netherlands B.V.,...

7. A method of forming a package, comprising the steps of:
receiving a substrate of copper;
receiving a semiconductor body;
applying an interface layer to the semiconductor body, the interface layer comprising a plurality of sub-layers of different
metals,

wherein the step of applying the interface layer comprises:
applying a first sub-layer of gold to the semiconductor body,
applying a second sub-layer of silver to the first sub-layer,
applying a third sub-layer of nickel to the second sub-layer and
applying a fourth sub-layer of gold to the third sub-layer; and
wherein the second sub-layer of silver is thinner than the third sub-layer of nickel; and
die bonding the semiconductor body with the interface layer to the substrate using a solder layer that comprises an alloy
of gold and tin.

US Pat. No. 9,570,323

SEMICONDUCTOR DEVICE LEADFRAME

Ampleon Netherlands B.V.,...

1. A lead frame for a semiconductor device manufactured by film assisted moulding, the lead frame comprising: a base portion;
and a connection lead, and a plurality of connection leads,
wherein the base portion comprises an upper surface arranged for mounting one or more semiconductor device dies, the one or
more semiconductor device dies being configured to be electrically connected to the plurality of connection leads using respective
bond wires;

wherein each connection lead that is to be electrically connected to the one or more semiconductor device dies comprises a
portion arranged horizontally with respect to the upper surface of the base portion for external connection and an angled
tip portion for connection to the semiconductor die, and

wherein the angled tip portion is arranged to be resiliently biased against and to seal against a film during moulding of
the semiconductor device, and

wherein the angled tip portion subtends a positive angle of 3 to 10 degrees with respect to the upper surface of the base
portion.

US Pat. No. 9,509,252

DOHERTY AMPLIFIER

Ampleon Netherlands B.V.,...

1. An integrated Doherty amplifier for amplifying an input signal at an operating frequency, comprising:
a main amplifier;
at least a first and a second peak amplifier, each of the amplifiers comprising a gate for receiving the input signal, a source
and a drain for providing an amplified signal;

a first input phase shifter comprising an integrated lumped inductor between the gate of the main amplifier and the gate of
the first peak amplifier;

a second input phase shifter comprising an integrated lumped inductor between the gate of the first peak amplifier and the
gate of the second peak amplifier, wherein the first input phase shifter and second input phase shifter are each configured
to shift the phase of the input signal by 90 degrees at the operating frequency, wherein the first input phase shifter and/or
second input phase shifter further comprises a DC blocking capacitor;

a first integrated lumped capacitor configured to be coupled between the drain of the first peak amplifier and ground;
a first output phase shifter between the drain of the main amplifier and the drain of the first peak amplifier, wherein the
first output phase shifter in combination with the first integrated lumped capacitor is configured to shift the phase of the
amplified signals from the main amplifier by 90 degrees at the operating frequency; and

a second output phase shifter between the drain of the first peak amplifier and the drain of the second peak amplifier, wherein
the second output phase shifter in combination with the first integrated lumped capacitor is configured to shift the phase
of the amplified signals from the first peak amplifier by 90 degrees at the operating frequency.

US Pat. No. 9,698,750

CIRCUIT

Ampleon Netherlands B.V.,...

1. A circuit comprising:
a first balanced terminal; a second balanced terminal; an unbalanced terminal; a ground terminal; a first substrate; a second
substrate;

a balun portion comprising:
a first balanced node, a second balanced node, an unbalanced node connected to the unbalanced terminal,
a first transmission line with a first end and a second end, the second end of the first transmission line connected to the
unbalanced node,

a second transmission line with a first end and a second end, the second transmission line capacitively and/or inductively
coupled to the first transmission line, the first end of the second transmission line connected to the first balanced node,
wherein the second end of the second transmission line is connected to the ground terminal,

a third transmission line with a first end and a second end, the first end of the third transmission line connected to the
first end of the first transmission line, wherein the second end of the third transmission line is connected to the ground
terminal,

a fourth transmission line with a first end and a second end, the first end of the fourth transmission line connected to the
second balanced node, the fourth transmission line capacitively and/or inductively coupled to the third transmission line,
wherein the second end of the fourth transmission line is connected to the ground terminal, and

at least one matching transmission element configured to present an impedance at one of the first balanced node, second balanced
node or unbalanced node; and

a balanced side impedance transforming element comprising:
a fifth transmission line connected between the first balanced terminal and the first balanced node of the balun portion,
and

a sixth transmission line connected between the second balanced terminal and the second balanced node of the balun portion,
the sixth transmission line capacitively and/or inductively coupled to the fifth transmission line, wherein the first substrate
comprises a planar dielectric layer, wherein each pair of coupled transmission lines are broad-side coupled transmission lines,
wherein the broad-side coupled transmission lines of each pair are disposed on opposing surfaces of the planar dielectric
layer of the first substrate, wherein the unbalanced node is disposed on the second substrate.

US Pat. No. 9,627,301

INTEGRATED CIRCUIT ARRANGEMENT

Ampleon Netherlands B.V.,...

1. An integrated circuit arrangement comprising:
a flange, the flange comprising conducting material;
a transistor die disposed on a surface of the flange;
an elongate capacitor bar disposed on the surface of the flange;
a first conducting element defining a lead, the first conducting element being electrically connected to the transistor die
via connecting elements to allow current flow from the transistor die;

wherein the flange defines return current paths allowing the current flow via the connecting elements and the lead to return
to the transistor die, wherein the flange comprises one or more reduced thickness portions, the one or more reduced thickness
portions being configured to limit the return current paths and therewith to control current flow passing through the flange
to the transistor die, wherein the one or more reduced thickness portions correspond to one or more pits in the flange surface,
wherein the one or more pits comprise an elongate trench, wherein a longitudinal axis of the elongate trench is parallel to
a longitudinal axis of the transistor die, wherein the elongate trench is located between at least one of: i) the elongate
capacitor bar and the first conducting element or ii) the elongate capacitor bar and the transistor die.

US Pat. No. 9,577,585

ULTRA WIDEBAND DOHERTY AMPLIFIER

Ampleon Netherlands B.V.,...

1. A Doherty amplifier for amplifying an input signal to an output signal, the Doherty amplifier comprising:
a main amplifier for receiving a first signal and for amplifying the first signal to generate a first amplified signal, said
main amplifier having an output line and an output capacitance connected to said output line;

a first peak amplifier for receiving a second signal and for generating a second amplified signal, said first peak amplifier
having an output line and an output capacitance connected to said output line, the first peak amplifier only operating when
the second signal has reached a first threshold power, the first and second signal split from the input signal; and

output circuitry to combine the first and second amplified signals to generate an output signal having an operating bandwidth,
the output circuitry comprising inductors arranged in the format of a branch line coupler, wherein the output circuitry comprises:

a first inductor having a first inductance connected on the output line of the first peak amplifier;
a second inductor having the first inductance connected on the output line of the main amplifier,
a third inductor having a second inductance branching between the outputs of the first inductor and second inductor;
a fourth inductor having the second inductance branching between the inputs of the first and second inductors; and
an output load having one terminal thereof connected between the second and third inductors.

US Pat. No. 9,496,837

DOHERTY AMPLIFIER

Ampleon Netherlands B.V.,...

1. A Doherty amplifier for driving a load comprising:
a main amplifier package, comprising a main amplifier and a drain connection connecting a drain of the main amplifier to an
output lead of the main amplifier package;

a peaking amplifier package, comprising a peaking amplifier, a first drain connection connecting a drain of the peaking amplifier
to a first output lead of the peaking amplifier package, and a second drain connection connecting the drain of the peaking
amplifier to a second output lead of the peaking amplifier package different from the first output lead;

an input network connecting an input of the Doherty amplifier to an input lead of the main amplifier package and to an input
lead of the peaking amplifier package; and

an output network connecting the output lead of the main amplifier package and the first output lead of the peaking amplifier
package;

wherein the output network, the drain capacitance of the main amplifier and the peaking amplifier, parasitics associated with
the drain connection and output lead of the main amplifier package, and parasitics associated with the first drain connection
and first output lead of the peaking amplifier package form an impedance inverter; and

wherein, during operation, the second output lead is connected to the load.

US Pat. No. 9,461,005

RF PACKAGE WITH NON-GASEOUS DIELECTRIC MATERIAL

Ampleon Netherlands B.V.,...

1. A package comprising:
an RF circuit;
a non-gaseous dielectric material coupled to the RF circuit, and having a thickness based on a magnetic field in the RF circuit;
and

an encapsulant material coupled to cover the RF circuit and non-gaseous dielectric material on at least one side of the RF
circuit.

US Pat. No. 9,543,914

DOHERTY AMPLIFIER STRUCTURE

Ampleon Netherlands B.V.,...

1. An integrated Doherty amplifier structure comprising;
a main amplifier stage;
a first peak amplifier stage;
an output combination bar configured to receive and combine an output from the main amplifier stage and an output from the
first peak amplifier stage, wherein the main amplifier stage and the first peak amplifier stage are formed on a semiconductor
die and the output combination bar comprises an output lead of a package in which the semiconductor die is mounted;

a main connection configured to connect the output of the main amplifier stage to the output combination bar, the main connection
comprising, at least in part, a bond wire forming a first inductance;

a peak connection configured to connect the output of the first peak amplifier stage to the output combination bar; wherein
the main connection connects to the output combination bar at a first point along the output combination bar, the peak connection
connects to the output combination bar at a second point along the output combination bar spaced from the first point, the
main amplifier stage is located further from the output combination bar than the first peak amplifier stage, and a physical
and electrical length of the main connection is greater than a physical and electrical length of the peak connection.

US Pat. No. 9,621,109

AMPLIFIER STRUCTURE

Ampleon Netherlands B.V.,...

1. An amplifier structure comprising a transistor element having a plurality of sub-sections each having a respective output
terminal and arranged adjacent to one another along a transistor element axis, a bias distribution element comprising a first
part and a second part, the first part configured to receive a bias signal and the second part configured to supply the bias
signal to the respective output terminal of each of the sub-sections of the transistor element, wherein the first part is
configured and arranged to deliver the bias signal to a distribution point and the second part is configured to diverge from
the distribution point to provide the bias signal to each of the sub-sections of the transistor element, the distribution
point arranged substantially facing a center point of the transistor element axis, wherein the first part comprises an elongate
part having a first end, said first part extending at least to the distribution point, wherein the first end is configured
to receive the bias signal, and wherein the first part provides a common current path for the bias signals intended for each
of the sub-sections.

US Pat. No. 10,003,318

CIRCUIT

Ampleon Netherlands B.V.,...

1. A circuit comprising:a first balanced terminal;
a second balanced terminal;
an unbalanced terminal;
a ground terminal;
a balun portion comprising:
a first balanced node, a second balanced node, an unbalanced node connected to the unbalanced terminal,
a first transmission line with a first end and a second end, the second end of the first transmission line connected to the unbalanced node,
a second transmission line with a first end and a second end, the second transmission line capacitively and/or inductively coupled to the first transmission line, the first end of the second transmission line connected to the first balanced node, wherein the second end of the second transmission line is connected to the ground terminal,
a third transmission line with a first end and a second end, the first end of the third transmission line connected to the first end of the first transmission line, wherein the second end of the third transmission line is connected to the ground terminal,
a fourth transmission line with a first end and a second end, the first end of the fourth transmission line connected to the second balanced node, the fourth transmission line capacitively and/or inductively coupled to the third transmission line, wherein the second end of the fourth transmission line is connected to the ground terminal, and
at least one matching transmission element configured to present an impedance at one of the first balanced node, second balanced node or unbalanced node; and
a balanced side impedance transforming element comprising:
a fifth transmission line connected between the first balanced terminal and the first balanced node of the balun portion, and
a sixth transmission line connected between the second balanced terminal and the second balanced node of the balun portion, the sixth transmission line capacitively and/or inductively coupled to the fifth transmission line; and
an unbalanced side impedance transforming element connected between the unbalanced terminal and the unbalanced node of the balun portion, wherein each of the unbalanced side impedance transforming element, the balanced side impedance transforming element, and the balun portion has an electrical length equivalent to ?/4 relative to an operating frequency.

US Pat. No. 10,143,045

RADIO FREQUENCY HEATING APPARATUS

Ampleon Netherlands, B.V....

1. An radio frequency (RF) heating apparatus comprising:a cavity for receiving an object to be heated;
an oscillator for generating a common phase reference signal;
a plurality of channels for generating RF radiation to be introduced into the cavity, wherein each channel comprises:
an RF frequency synthesiser;
a coherent quadrature modulator for modulating a first RF signal outputted by the RF frequency synthesiser;
a controller for outputting control signals to the modulator for controlling at least one of phase and amplitude of the modulated first RF signal;
a power amplifier for amplifying the modulated first RF signal;
an antenna connected to an output of the power amplifier;
a forward signal detection coherent quadrature demodulator;
a reverse signal detection coherent quadrature demodulator; and
a directional coupler connected in between the power amplifier and the antenna, the directional coupler being connected to the forward signal detection coherent quadrature demodulator and to the reverse signal detection coherent quadrature demodulator by a forward signal coupled path and a reverse signal coupled path, respectively,
wherein the forward signal detection coherent quadrature demodulator is configured to monitor an RF signal that is introduced in the cavity by the antenna and wherein the reverse signal detection coherent quadrature demodulator is configured to monitor an RF signal that is reflected back from the cavity,
wherein the forward signal detection and the reverse signal detection coherent quadrature demodulators are configured to provide their respective output to the controller,
wherein the controller is configured to use the output from the forward signal detection and the reverse signal detection coherent quadrature demodulators to alter operation of the channel for modifying the RF radiation that is introduced to the cavity, and
wherein the common phase reference signal is used to synchronise the frequency synthesisers of each channel in terms of at least one of frequency and phase.

US Pat. No. 9,911,628

SEMICONDUCTOR DEVICE LEADFRAME

Ampleon Netherlands B.V.,...

1. A method of manufacturing a semiconductor package by means of film assisted moulding, comprising:
providing a base of a package;
providing a leadframe comprising a plurality of connection leads, wherein each connection lead that is to be electrically
connected to said one or more semiconductor dies comprises a portion that is arranged horizontally with respect to the upper
surface of the base for external connection and an angled tip portion for connection to the semiconductor die;

mounting one or more semiconductor device dies on an upper surface of the base;
placing a first film over a top portion of the base and further arranging the first film to seal against the angled tip portion,
wherein the first film is placed so as to create a first cavity such that the semiconductor device dies are protected, and
further creating mold cavities;

introducing moulding compound in a mold for a moulding process so as to fill the mold cavities, wherein the angled tip portion
is pressed into the film resulting in an improved seal to the connection leads;

removing the resulting moulded base from the mold and removing the first film to expose the first cavity and to expose the
tip portions of the connection leads;

electrically connecting the one or more semiconductor device dies to the tip portions of the connection leads by means of
wirebonding.

US Pat. No. 9,928,954

TRANSFORMER

Ampleon Netherlands B.V.,...

1. A bond-wire transformer for an RF circuit comprising:a substrate being a semiconductor die comprising a plurality of metal layers including a top-level metal layer (N) and a next lowest metal layer (N?1), which substrate has a pair of primary terminals and a pair of secondary terminals, wherein a region of one of the plurality of metal layers is defined as a shield layer, wherein the shield layer is operably coupled to a ground potential,
a primary circuit comprising primary bond-wires electrically coupled in series between the pair of primary terminals, a first of the primary bond-wires having a different maximum spacing from a major surface of the substrate than a second of the primary bondwires, and
a secondary circuit comprising secondary bond-wires electrically coupled in series between the pair of secondary terminals, a first of the secondary bond-wires having a different maximum spacing from a major surface of the substrate than a second of the secondary bond-wires,
wherein the first terminal of said pairs of terminals is defined in the top-level metal layer (N) and the second terminal of said pairs of terminals is defined in the next lowest metal layer (N?1),
wherein the primary circuit comprises at least one primary loop having a pair of primary bond-wires, each pair consisting of a first and a second primary bond-wire, which first primary bond-wire is routed directly over the second primary bond wire without making direct contact,
wherein the secondary circuit comprises at least one secondary loop having a pair of secondary bond-wires, each pair consisting of a first and a second secondary bond-wire, which first secondary bond-wire is routed directly over the second secondary bond wire without making direct contact.

US Pat. No. 10,038,407

INTEGRATED 3-WAY DOHERTY AMPLIFIER

Ampleon Netherlands B.V.,...

1. A die comprising at least one integrated 3-way Doherty amplifier, the integrated 3-way Doherty amplifier comprising:a main stage;
a first peak stage;
a second peak stage;
an input connected to an input network which is connected to the main stage, first peak stage and second peak stage, wherein the input network includes a first impedance connected to an input of the first peak stage and providing a ?90° phase shift and a second impedance connected to an input of the second peak stage and providing a 90° phase shift;
an output connected to an output network which is connected to the main stage, first peak stage and second peak stage, wherein the output network includes a third impedance connected to the output of the first peak stage and providing a 180° phase shift and a fourth impedance connected to the output of the main stage and providing a 90° phase shift;
a first pi-network formed by a parasitic drain-source shunt capacitor to ground of the first peak stage, the at least one first bond wire, and the parasitic drain-source shunt capacitor to ground of the second peak stage, said first pi-network being configured for providing the third phase shifting impedance; and
a second pi-network formed by a parasitic drain-source shunt capacitor to ground of the main stage, the at least one second bond wire, and the parasitic drain-source shunt capacitor to ground of the second peak stage, said second pi-network being configured for providing the fourth phase shifting impedance; and
the die optionally comprising an output capacitance connected in between the output of the die and ground,
wherein the third impedance comprises at least one first bond wire connected between an output of the first peak stage and the output of the second peak stage and the fourth impedance comprises at least one second bond wire connected between an output of the main stage and the output of the second peak stage.

US Pat. No. 9,941,227

IMPEDANCE MATCHING CONFIGURATION

Ampleon Netherlands B.V.,...

1. A package comprising:an integrated circuit die having a first terminal and a second terminal;
a first package lead coupled to the first terminal;
a second package lead coupled to the second terminal; and
an impedance matching network coupled to the second terminal and comprising a first inductor and a first capacitor, wherein the first capacitor is an integrated capacitor arranged on the integrated circuit die;
wherein the first inductor comprises first bond wire connections coupled between the second terminal and a first bond pad on the die, and second bond wire connections coupled between the first bond pad and a second bond pad coupled to the first capacitor;
wherein the first bond wire connections and the second bond wire connections are adjacently arranged;
wherein the first bond pad is arranged on the die in between the first package lead and the second terminal; and
wherein the first capacitor is a DC decoupling capacitor.

US Pat. No. 10,218,313

AMPLIFIER ASSEMBLY

Ampleon Netherlands B.V.,...

1. An amplifier arrangement forming a multi-way Doherty amplifier, comprising:a main amplifier, a first peak amplifier, and a second peak amplifier;
a printed circuit board comprising:
(i) an RF input terminal;
(ii) an RF output terminal;
(iii) a dual path package having a first RF input lead, a second RF input lead, a first RF output lead, and a second RF output lead;
(iv) a splitter element for splitting an RF input signal received at the RF input terminal over the first RF input lead and the second RF input lead;
(v) a combiner element for combining signals from the first RF output lead and the second RF output lead;
(vi) an impedance inverter arranged in between (a) one of the first RF output lead and the second RF output lead and (b) the combiner element, and
(vii) a phase delay element configured to provide a phase offset between the RF input signals received by the first RF input lead and the second RF input lead;
wherein the dual path package comprises:
(i) a first semiconductor die comprising an integrated two-way Doherty amplifier that comprises a first amplifier and a second amplifier, wherein the first amplifier and the second amplifier comprise two amplifiers selected from a group consisting of: the first peak amplifier, the second amplifier, and the main amplifier, and
(ii) a second semiconductor die comprising a third amplifier, wherein the third amplifier comprises a remaining amplifier of the group of the first peak amplifier, the second amplifier, and the main amplifier,
wherein the first semiconductor die comprises:
(i) a Doherty splitter element configured to split the RF input signal received from the first RF input lead to provide an input signal to the first amplifier and the second amplifier;
(ii) a phase shifting element arranged in between the Doherty splitter element and the second amplifier;
(iii) a main connection comprising a bond wire connecting an output of the first amplifier to the first RF output lead, and
(iv) a peak connection comprising a bond wire connecting an output of the second amplifier to the first RF output lead;
wherein different physical and electrical lengths of the main connection compared to the peak connection in combination with output parasitic capacitances of the first amplifier and the second amplifier form an impedance inverter arrangement, and
wherein the impedance inverter arrangement introduces an approximately 90° phase shift in the output of the first amplifier, the phase shifting element being adapted to compensate for the approximately 90° phase shift.

US Pat. No. 10,218,315

DOHERTY AMPLIFIER

Ampleon Netherlands B.V.,...

1. A Doherty amplifier, comprising:a main amplifier and a first peak amplifier, a second peak amplifier, and a third peak amplifier, each amplifier having an input and an output;
a combining network configured for combining signals emerging at outputs of the main amplifier, the first peak amplifier, the second peak amplifier, and the third peak amplifier, wherein the signals are combined at a combining node, and wherein the combining network comprises:
a first impedance inverter arranged in between the output of the main amplifier and the output of the third peak amplifier to combine the output of the main amplifier with the output of the third peak amplifier at the output of the third peak amplifier;
a second impedance inverter arranged in between the output of the first peak amplifier and the output of the second peak amplifier to combine the output of the first peak amplifier with the output of the second peak amplifier at the output of the second peak amplifier;
a first 180 degrees phase shifter arranged in between the output of the second peak amplifier and an intermediate node;
a second 180 degrees phase shifter arranged in between the output of the third peak amplifier and the combining node; and
a third impedance inverter arranged in between the combining node and the intermediate node.