US Pat. No. 9,588,791

FLEXIBLE PHYSICAL FUNCTION AND VIRTUAL FUNCTION MAPPING

Altera Corporation, San ...

1. A method for mapping between physical functions and virtual functions, the method comprising:
receiving, by a virtualization management unit, data indicating virtual machines to be provided access to hardware functionality
implemented in function blocks; and

establishing, by the virtualization management unit, a mapping between the virtual machines and the function blocks to provide
the virtual machines access to the hardware functionality implemented in the function blocks, the mapping indicating each
virtual machine associated with a corresponding virtual function, each virtual function associated with one or more of the
physical functions, and each of the one or more physical functions associated with the one or more function blocks, wherein
the mapping is based on characteristics of the virtual machines, wherein the one or more physical functions includes a first
physical function and a second physical function, the first physical function mapped to a first function block providing a
first hardware functionality, the second physical function mapped to the first function block and a second function block,
the second function block providing a second hardware functionality;

reconfiguring the second function block to provide a third hardware functionality, the third hardware functionality being
different than the second hardware functionality; and

updating, by the virtualization management unit, the mapping based on the reconfiguration of the second function block to
provide the third hardware functionality.

US Pat. No. 9,590,635

PARTIAL RECONFIGURATION OF PROGRAMMABLE DEVICES

Altera Corporation, San ...

1. A bridge circuit of a programmable logic device (PLD) to:
receive a first configuration data from a communications interface, the first configuration data indicating states of configurable
elements of a region of configurable logic of the PLD to implement a first functionality, the bridge circuit to freeze inputs
and outputs of the region of the configurable logic, and the bridge circuit to provide bits of the first configuration data
to a control block of the PLD to configure the configurable elements after freezing the inputs and outputs.

US Pat. No. 9,329,608

PROGRAMMABLE INTEGRATED CIRCUITS WITH DECOUPLING CAPACITOR CIRCUITRY

Altera Corporation, San ...

1. Circuitry, comprising:
first and second adjacent conductive paths;
a first driver circuit that drives the first conductive path to a first power supply voltage level;
a second driver circuit that drives the second conductive path to a second power supply voltage level that is different than
the first power supply voltage level, wherein the first and second different power supply voltage levels are maintained on
the first and second adjacent conductive paths, respectively, during normal operation such that the first and second conductive
paths contribute to a power supply decoupling capacitance; and

a reset circuit that is coupled to the first driver circuit and that drives the first conductive path to the first power supply
voltage level in response to asserting a control signal that controls the reset circuit.

US Pat. No. 9,336,078

MEMORY ERROR DETECTION CIRCUITRY

Altera Corporation, San ...

1. A method of generating a parity check matrix used for error detection, wherein the parity check matrix includes logic high
and logic low bits arranged in rows and columns, the method comprising:
providing a Boolean formula that defines a set of constraints, wherein the set of constraints determines an upper bound on
the number of logic high bits are in each column, whether certain types of errors are detectable, and whether the detectable
errors are correctable; and

generating the parity check matrix by solving the set of constraints using a Boolean equation solver running on computing
equipment.

US Pat. No. 9,331,714

CIRCUIT STRUCTURE AND METHOD FOR HIGH-SPEED FORWARD ERROR CORRECTION

Altera Corporation, San ...

1. A receiver for a multi-lane data link, the receiver comprising:
a plurality of physical media attachment circuits for de-serializing data from a plurality of serial lanes of the multi-lane
data link, each physical media attachment circuit outputting the data at a first bus width;
a plurality of gearbox circuits, each gearbox circuit receiving the data at the first bus width and outputting the data at
a second bus width, wherein the first bus width is different from the second bus width; anda forward error correction (FEC) decoder for receiving and decoding the data at a third bus width, wherein the third bus width
in bits is a product of the second bus width in bits and a number of the serial lanes of the multi-lane data link, and wherein
the data is encoded with an FEC code having a block length,wherein the third bus width in bits is an exact multiple of a number of bits per symbol in the data, andwherein the block length in bits is an exact multiple of the third bus width.

US Pat. No. 9,215,115

APPARATUS AND METHOD FOR IMPROVED INTEGRATION CIRCUITRY IN DECISION FEEDBACK EQUALIZATION

Altera Corporation, San ...

1. A decision feedback equalization circuit, comprising:
a linear feedback shift register configured to count through a predetermined sequence;
a digital integrator controller configured to detect a first predetermined boundary value from the linear feedback shift register,
wherein the digital integrator is configured to output a first digital integrator control signal responsive to the detection
of the first predetermined boundary value;

a digital integrator configured to terminate integration responsive to the first digital integrator control signal.

US Pat. No. 9,504,156

DISTRIBUTION OF RETURN PATHS FOR IMPROVED IMPEDANCE CONTROL AND REDUCED CROSSTALK

Altera Corporation, San ...

1. A method of distributing signal, power and ground connections at an electrical interface comprising the steps of:
(a) determining from a total number of each of signal, power and ground connections to be provided at the electrical interface
a ratio of the total number of each of signal, power and ground connections to be provided at the electrical interface where
the number of signal connections is at least twice the sum of the number of power connections and the number of ground connections;

(b) selecting from a set of repeatable cells of signal, power and ground connections in which each signal connection is no
more than one unit distance from a nearest power or ground connection a cell having the ratio determined in step a;

(c) locating the signal, power and ground connections in one portion of the interface in a pattern specified by the selected
cell; and

(d) repeating step c at least once in other portions of the interface with the same pattern specified by the cell selected
in step b until the interface is filled with signal, power and ground connections where the number of signal connections is
at least twice the sum of the number of power connections and the number of ground connections.

US Pat. No. 9,330,997

HEAT SPREADING STRUCTURES FOR INTEGRATED CIRCUITS

Altera Corporation, San ...

1. An integrated circuit heat spreading structure, comprising:
a planar portion; and
a slanted portion that extends at an angle from an edge of the planar portion, wherein a slot is formed in the slanted portion,
wherein the integrated circuit heat spreading structure forms a part of an integrated circuit package that includes a package
substrate, an integrated circuit mounted on the package substrate, and a passive device mounted on the package substrate adjacent
to the integrated circuit, wherein the integrated circuit is interposed between the package substrate and the integrated circuit
heat spreading structure, and wherein a top portion of the passive device penetrates through the slot in the integrated circuit
heat spreading structure.

US Pat. No. 9,053,232

METHOD AND APPARATUS FOR SUPPORTING A UNIFIED DEBUG ENVIRONMENT

Altera Corporation, San ...

1. A hybrid field programmable gate array (FPGA), comprising
a soft processor and a soft processor debug unit implemented by programmable logic on the FPGA;
a system on a chip (SOC) that includes a hard processor and a hard processor debug unit; and
a bus bridge, coupled to an input output (IO) of the FPGA, that transmits data between the IO and the soft processor debug
unit and the hard processor debug unit.

US Pat. No. 9,479,456

PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP

Altera Corporation, San ...

1. A programmable integrated circuit comprising a plurality of Network-On-Chip (NoC) stations, wherein a first NoC station
in the plurality of NoC stations receives a first clock input and comprises:
a first hard-IP interface comprising:
a first bidirectional connection that communicatively couples the first NoC station to a local logic area of the programmable
integrated circuit; and

a second bidirectional connection that communicatively couples the first NoC station to a second NoC station in the plurality
of NoC stations neighboring the first NoC station; and

a user-programmable first soft-IP interface that supports the first hard-IP interface and comprises Quality-of-Service (QoS)
circuitry that provides functionality to the first NoC station based at least in part on a QoS parameter instantiated in the
first soft-IP interface, wherein, when the QoS parameter comprises a data width of the first NoC station, the functionality
comprises:

segmenting data received at the first NoC station with a width greater than the data width into smaller data units to facilitate
processing by the first NoC station; and

padding data received at the first NoC station with a width less than the data width into a padded data unit to facilitate
processing by the first NoC station.

US Pat. No. 9,059,716

DIGITAL PVT COMPENSATION FOR DELAY CHAIN

Altera Corporation, San ...

1. A circuit for controlling delay in an input signal comprising:
a delay locked loop comprising a first plurality of first delay elements for producing a phase control signal, each first
delay element having a first delay that is controllable by the phase control signal;

a calibration circuit that determines a minimum number of second delay elements required to produce the first delay where
each second delay element produces a second delay that is less than the first delay; and

an output circuit that uses the minimum number to determine how many second delay elements to use to produce a desired delay
in the input signal.

US Pat. No. 9,235,460

METHODS AND APPARATUS FOR AUTOMATIC FAULT DETECTION

ALTERA CORPORATION, San ...

1. An integrated circuit device comprising:
control logic operable to send a signal onto a signal tree included on the integrated circuit device, the signal tree comprising
branches and leaves, wherein the branches and leaves include columns and rows of circuit lines configured to carry signals
from a signal source to signal endpoints, wherein each leaf of the signal tree comprises a signal endpoint;

user logic operable to implement a user design on the integrated circuit device; and
fault detection circuitry on the integrated circuit device operable to monitor, using sensors, a plurality of signal values
at each of the leaves on the signal tree such that the fault detection circuitry can detect faults at any point along the
branches of the signal tree, wherein the fault detection circuitry is operable to generate a fault detect signal having a
first value in response to determining that the first signal value of the plurality of signal values deviates from an expected
signal value, and wherein the control logic implements a fault handling procedure upon receiving the fault detect signal having
the first value.

US Pat. No. 9,424,210

SDRAM MEMORY ORGANIZATION AND EFFICIENT ACCESS

Altera Corporation, San ...

1. A method of organizing data in a memory for a particular application, the memory including a plurality of banks, each bank
including a plurality of rows, the method comprising:
arranging data locations in the memory such that, for access commands generated during normal operation of the particular
application, access commands generated in an order corresponding to a data order requested for the particular application
can be ordered so that consecutive memory accesses do not access different rows in a same bank of the memory by: if consecutively
generated access commands do not require accessing different rows in a same bank of the memory, then leaving the consecutively
generated access commands in their generated order and, if consecutively generated access commands require accessing different
rows in a same bank of the memory, then switching an order of one or more pairs of consecutively generated access commands
and only such switching reorders the access commands during the entirety of normal operation of the particular application
so that consecutive memory accesses do not access different rows in a same bank of the memory.

US Pat. No. 9,094,014

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

Altera Corporation, San ...

1. A programmable logic device, comprising:
a logic element (LE) array;
a base signal routing architecture including a plurality of signal routing lines to route signals among the LE array; and
an interface region for interconnecting an IP function block and the LE array, the interface region comprising interfacing
circuitry for selectively applying a signal provided by the base signal routing architecture to the IP function block, and
the interface region having a granularity substantially similar to a width of a logic array block (LAB) of the LE array.

US Pat. No. 9,471,388

MAPPING NETWORK APPLICATIONS TO A HYBRID PROGRAMMABLE MANY-CORE DEVICE

Altera Corporation, San ...

1. A hybrid programmable logic device, comprising:
transceivers that receive data packets, wherein the data packets comprise header data and payload data;
programmable logic fabric comprising programmable logic elements, wherein a first portion of the programmable logic elements
provide hardware acceleration functions;

processors interleaved with the programmable logic elements, wherein each of the processors process the received header data
using the hardware acceleration functions and processing threads, and a second portion of the programmable logic elements
schedule the distribution of header data to the processing threads, wherein each processing thread of the processors is associated
with a unique address received by each of the processors via an interconnect shared by each of the processors, wherein each
of the processors comprises a memory interface that monitors the received header data for the unique address associated with
each respective processing thread and stores the received header data in a local memory when the received header data is marked
with the unique address.

US Pat. No. 9,190,332

METHOD OF FABRICATING INTEGRATED CIRCUIT TRANSISTORS WITH MULTIPART GATE CONDUCTORS

Altera Corporation, San ...

1. A method for fabricating a transistor comprising:
using a self-aligned gate formation process, depositing a first gate conductor on a gate insulator in the transistor during
a first time period;

depositing a second gate conductor directly on top of the first gate conductor during a second time period that is different
than the first time period; and forming first and second edge conductor portions on the gate insulator by simultaneously removing
a portion of the first and second gate conductors.

US Pat. No. 9,385,717

LEVEL-SENSITIVE TWO-PHASE SINGLE-WIRE LATCH CONTROLLERS WITHOUT CONTENTION

Altera Corporation, San ...

1. A contention-free controller for a data latch, the controller comprising:
first and second bidirectional signal pins;
a decision element;
a first driving transistor coupled between the first bidirectional signal pin and a power rail;
a second driving transistor coupled between the second bidirectional signal pin and the power rail;
a first tri-stateable half-latch coupled to the first bidirectional signal pin; and
a second tri-stateable half-latch coupled to the second bidirectional signal pin,
wherein the decision element is a gate comprising an input for the first bidirectional signal pin and an input for one of
the second bidirectional signal pin and an inverted version of the second bidirectional signal pin.

US Pat. No. 9,462,691

ENHANCED BALL GRID ARRAY

Altera Corporation, San ...

1. A device package comprising:
a substrate having first and second major surfaces and electrical conductors extending across or into the substrate;
a two-dimensional array of pads formed on the first major surface of the substrate, first and second subsets of the pads being
connected to the electrical conductors, each pad of the second subset of the pads having a plurality of isolated electrically
conductive regions that are connected to different conductors;

solder balls or solder bumps formed on the first subset of the pads, said solder balls or solder bumps having a first height;
and

other devices formed on the second subset of the pads that have a height that is no more than that of the first height, wherein
each of the other devices is directly mounted on one of the second subset of the pads, wherein each of the other devices comprises
multiple terminals, and wherein each of the multiple terminals of one of the other devices is electrically connected to a
different one of the plurality of isolated electrically conductive regions of one of the second subset of the pads.

US Pat. No. 9,331,703

SAMPLE RATE CONVERTER

Altera Corporation, San ...

1. A circuit comprising:
a clock period measurement unit to determine a period of a clock signal;
an average clock period calculation unit to determine an average period of the clock signal, the average period of the clock
signal based on a plurality of measurements of the period of the clock signal;

a period adjustment unit to generate an adjusted average period of the clock signal based on the average period of the clock
signal and one or more adjustment values;

a period difference unit to determine a difference of the adjusted average period of the clock signal and the period of the
clock signal; and

an adjustment values unit to generate the one or more adjustment values based on the difference of the adjusted average period
of the clock signal and the period of the clock signal.

US Pat. No. 9,298,865

DEBUGGING AN OPTIMIZED DESIGN IMPLEMENTED IN A DEVICE WITH A PRE-OPTIMIZED DESIGN SIMULATION

Altera Corporation, San ...

1. A method for simulating a design implemented in a semiconductor device, the method comprising:
receiving first interconnect data, the first interconnect data indicating a first interconnect of a first logic design implemented
within a circuit schematic, wherein the first interconnect is associated with a first combinational logic block;

identifying, by a processor, a first node for the first combinational logic block, the first node having an output providing
an input to the first combinational logic block;

identifying, by the processor, a second node in a second logic design physically implemented in the semiconductor device,
the second node having an output providing an input to a second combinational logic block, wherein the second combinational
logic block physically implemented in the semiconductor device is a modified version of the first combinational logic block
implemented within the circuit schematic, and the second node providing an input to the second combinational logic block corresponds
to the first node providing an input to the first combinational logic block;

configuring the semiconductor device such that the second logic design is modified to include a tap associated with the output
of the second node; and

simulating a signal associated with the first interconnect of the first logic design implemented within the circuit schematic
based on data provided by the tap in the second logic design physically implemented in the semiconductor device.

US Pat. No. 9,319,063

ENHANCED MULTI-PROCESSOR WAVEFORM DATA EXCHANGE USING COMPRESSION AND DECOMPRESSION

Altera Corporation, San ...

1. A system for processing waveform data, wherein the waveform data comprise samples represented in an integer data format
or a floating-point data format, comprising:
a plurality of processor cores and a communications fabric for transfer of data packets among the plurality of processor cores;
compression logic integrated with a source processor core of the plurality of processor cores, wherein the compression logic
is operable to compress a plurality of samples from the source processor core in accordance with one or more compression control
parameters to form a plurality of compressed samples, the compression logic further including logic to provide the compressed
samples to a data portion of a compressed packet and the one or more compression control parameters to a header portion of
the compressed packet for transmission on the communication fabric; and

decompression logic integrated with a destination processor core of the plurality of processor cores, wherein the decompression
logic is applied to the compressed packet received from the communication fabric to decompress the compressed samples from
the data portion of the compressed packet in accordance with the one or more compression control parameters from the header
portion of the compressed packet to form a plurality of decompressed samples.

US Pat. No. 9,298,799

METHOD AND APPARATUS FOR UTILIZING PATTERNS IN DATA TO REDUCE FILE SIZE

Altera Corporation, San ...

1. A method for managing records, comprising:
generating modified representations of data in fields of the records by taking an arithmetic difference between data in fields
of a record and data in corresponding fields of a previous instance of the record, wherein a location of the previous instance
of the record and a location of a next instance of the record are identified in the fields of the records; and

compressing the modified representations of the data utilizing similarities between values within the modified representations
of the data, wherein at least one of the generating and the compressing is performed by a processor.

US Pat. No. 9,158,873

CIRCUIT DESIGN TECHNIQUE FOR DQS ENABLE/DISABLE CALIBRATION

Altera Corporation, San ...

1. A system for calibrating timing of a signal, the system comprising:
a first circuit for generating a calibrated signal by calibrating the signal based on a first clock; and
a second circuit for maintaining the timing of the calibrated signal over a plurality of clock cycles based on the first clock
and a second clock.

US Pat. No. 9,130,561

CONFIGURING A PROGRAMMABLE LOGIC DEVICE USING A CONFIGURATION BIT STREAM WITHOUT PHANTOM BITS

Altera Corporation, San ...

1. A circuit including configuration elements comprising:
a bit stream generation circuit to receive a first configuration bit stream including a first header portion and a first configuration
bit portion, and to generate a second configuration bit stream used to configure the configuration elements of the circuit,
the second configuration bit stream including at least one padding bit and at least one bit from the first configuration bit
portion based on the first header portion, the first header portion including data used by the bit stream generation circuit
to determine a distribution of the configuration elements in the circuit, and the bit stream generation circuit including
the at least one padding bit in the second configuration bit stream based on the distribution of configuration elements.

US Pat. No. 9,299,396

PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION CAPABILITY

Altera Corporation, San ...

1. A method of operating an integrated circuit that includes a plurality of memory elements, wherein each memory element in
the plurality of memory elements controls a corresponding pass gate, the method comprising:
performing partial reconfiguration on a first portion of the plurality of memory elements;
with the first portion of the plurality of memory elements, receiving a power supply voltage via a power supply line; and
during the partial reconfiguration, enhancing write margin for the first portion of the plurality of memory elements by temporarily
adjusting the power supply voltage, wherein pass gates associated with a second portion of the plurality of memory elements
that also receive the adjusted power supply voltage from the power supply line exhibit performance that is unaffected by the
temporary adjustment of the power supply voltage.

US Pat. No. 9,293,452

ESD TRANSISTOR AND A METHOD TO DESIGN THE ESD TRANSISTOR

Altera Corporation, San ...

1. An electro static discharge (ESD) protection device comprising:
a transistor that includes a gate of the transistor, a first diffusion area as a source of the transistor and a second diffusion
area as a drain of the transistor, wherein the first diffusion area is adjacent to the second diffusion area, the gate covers
a region between the first diffusion area and the second diffusion area, and the transistor provides protection from electrostatic
discharge;

a first dummy gate that is adjacent to the first diffusion area and is substantially parallel with the gate of the transistor,
the first dummy gate having a first single, unitary body, wherein the first dummy gate provides further protection from electrostatic
discharge;

a routing structure located in a layer different than the gate of the transistor, the routing structure coupled to the first
dummy gate;

a first coupling that couples the first diffusion area to the first dummy gate;
a second coupling that couples the first diffusion area to the first dummy gate, the second coupling in electrical parallel
with the first coupling;

a second dummy gate that is adjacent to the second diffusion area and is substantially parallel with the gate of the transistor,
the second dummy gate having a second single, unitary body, wherein the second dummy gate provides further protection from
electrostatic discharge; and

a third coupling that couples the second diffusion area to the second dummy gate.

US Pat. No. 9,237,001

METHOD AND APPARATUS TO CALIBRATE DUTY CYCLE DISTORTION

Altera Corporation, San ...

1. A method of calibrating duty cycle distortion, the method comprising:
changing a data rate of a physical layer interface from a first rate to a second rate, wherein the first rate is lower than
the second rate;

changing a data rate of one or more transceivers associated with the physical layer interface from the first rate to the second
rate;

maintaining an electrical idle state after changing the data rate of the one or more transceivers;
performing a duty cycle distortion calibration for a first transceiver of said one or more transceivers during the electrical
idle state; and

once there are no more transceivers to calibrate, ending the electrical idle state and resuming operation of the physical
layer interface by asserting a ready signal.

US Pat. No. 9,197,531

METHODS AND APPARATUS OF TIME STAMPING FOR MULTI-LANE PROTOCOLS

Altera Corporation, San ...

1. A method of determining an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane
link, the method comprising:
receiving words of the data packet on the plurality of lanes of the multi-lane link;
determining word arrival times for a subset of the words of the data packet, each word arrival time corresponding to an arrival
time of a word of the data packet at an individual lane of the multi-lane link; and

determining the arrival time of the data packet using the word arrival times for the subset of the words, wherein the subset
of the words consists of a first-to-arrive word and a last-to-arrive word.

US Pat. No. 9,236,864

STACKED INTEGRATED CIRCUIT WITH REDUNDANCY IN DIE-TO-DIE INTERCONNECTS

Altera Corporation, San ...

1. An integrated circuit (IC) comprising:
a first die including a bottom-die redundancy control circuit;
a second die coupled to the first die, the second die including a top-die redundancy control circuit; and
a plurality of die-to-die interconnects coupling the bottom-die redundancy control circuit to the top-die redundancy control
circuit, wherein the plurality of die-to-die interconnects comprises a plurality of pre-designated die-to-die interconnects
and at least one redundancy die-to-die interconnect,

wherein the bottom-die redundancy control circuit comprises:
a plurality of pre-designated signal paths; and
a redundancy signal path, wherein the redundancy signal path includes a selector coupled to the plurality of pre-designated
signal paths,

wherein the selector receives signals received by the plurality of pre-designated signal paths and an additional signal, wherein
the additional signal is not a select signal for the selector, further wherein the selector selects a signal from its received
signals and outputs the signal to a redundancy die-to-die interconnect of the at least one redundancy die-to-die interconnect,

further wherein the top-die redundancy control circuit comprises:
a plurality of selectors; and
a plurality of decoding logic circuits coupled to the plurality of selectors, wherein each decoding logic circuit of the plurality
of decoding logic circuits is coupled to a corresponding selector of the plurality of selectors,

wherein each selector of the plurality of selectors receives a signal from a corresponding pre-designated die-to-die interconnect
and a signal from a redundancy die-to-die interconnect of the at least one redundancy die-to-die interconnect, further wherein
each selector of the plurality of selectors receives a select signal from a corresponding decoding logic circuit of the plurality
of decoding logic circuits.

US Pat. No. 9,229,909

METHOD AND APPARATUS FOR PERFORMING REQUIREMENT-DRIVEN DISCRETE FOURIER TRANSFORMS AND THEIR INVERSES

Altera Corporation, San ...

1. A method for designing a discrete Fourier transform (DFT) unit in a system on a target device, comprising:
identifying a number of DFT engines to implement in the DFT unit in response to a data throughput rate, a clock rate of the
system, a size of a DFT, and radix of each of the DFT engines, wherein the identifying is performed by a processor.

US Pat. No. 9,223,090

BIDIRECTIONAL WAVELENGTH CROSS CONNECT ARCHITECTURES USING WAVELENGTH ROUTING ELEMENTS

Altera Corporation, San ...

1. A K×K bidirectional wavelength cross connect, comprising:
a plurality K of 1:(K?1) optical couplers, each configured to receive one of a plurality of input optical signals, each of
the plurality of input optical signals comprising a plurality of spectral bands; and

a plurality (K(K?1))/2 of wavelength blockers, each wavelength blocker having at least two wavelength blocker ports;
wherein each optical coupler is configured to transmit (K?1) substantial equivalents of one of the plurality of input optical
signals to (K?1) wavelength blockers, to receive an output optical signal from each of the (K?1) wavelength blockers, and
to transmit a composite output signal; and

wherein the wavelength blockers are configured to receive two of the substantial equivalents of the plurality of input optical
signals from two different optical couplers, selectively to block spectral bands from the substantial equivalents of the plurality
of input optical signals, and to transmit output optical signals to the two different optical couplers.

US Pat. No. 9,383,802

INTEGRATED CIRCUIT WITH STATE AND DATA RETENTION

Altera Corporation, San ...

1. A method of operating an integrated circuit, comprising:
receiving a sleep mode request at the integrated circuit, wherein the integrated circuit includes a plurality of registers
that stores state information when the integrated circuit is in a user mode and configuration memory that stores configuration
data in the user mode;

configuring the plurality of registers to operate as a scan chain in response to receiving the sleep mode request;
retrieving integrated circuit state information stored in the plurality of registers by operating the scan chain;
retrieving the configuration data from the configuration memory;
storing the retrieved integrated circuit state information and the retrieved configuration data in a memory module; and
placing the integrated circuit in a sleep mode to reduce power consumption of the integrated circuit.

US Pat. No. 9,275,184

METHOD AND APPARATUS FOR PERFORMING TIMING CLOSURE ANALYSIS WHEN PERFORMING REGISTER RETIMING

Altera Corporation, San ...

1. A method for designing a system on a target device, comprising:
performing register retiming on the system in response to a timing analysis;
detecting a critical chain in the system in response to the register retiming, wherein the critical chain includes a plurality
of register-to-register paths where improving timing on one of the register-to-register paths improves timing on other register-to-register
paths;

reporting properties of the critical chain to a user;
modifying the system in response to input received from the user after reporting the properties of the critical chain to the
user; and

performing another register retiming on the system after modifying the system.

US Pat. No. 9,245,835

INTEGRATED CIRCUIT PACKAGE WITH REDUCED PAD CAPACITANCE

Altera Corporation, San ...

1. An integrated circuit package, comprising:
a package substrate having first and second surfaces;
an integrated circuit mounted on the first surface of the package substrate;
a solder ball pad located on the second surface of the package substrate, wherein a gap in the second surface of the package
substrate surrounds the solder ball pad, wherein the solder ball pad has a diameter, and wherein the package substrate includes
a layer comprising:

a ground plane; and
an opening formed through the ground plane above the solder ball pad, wherein the opening has a diameter that is at least
equal to half the diameter of the solder ball pad.

US Pat. No. 9,118,349

CONTINUOUS PARALLEL CYCLIC BCH DECODING ARCHITECTURE

Altera Corporation, San ...

1. Circuitry for, in p parallel streams, searching a received codeword having n received symbols for roots of a cyclic code
polynomial having a number of terms, where n and p are positive integers greater than 1 that have differing values that are
not integer multiples of one another, said circuitry comprising:
a plurality of multipliers;
a source of constants derived from roots of said polynomial, said source of constants comprising a respective register corresponding
to each respective term of said polynomial; and

at least one counter that supplies an index; wherein for a symbol of said received codeword:
said multipliers multiply respective terms of said polynomial for a previous received symbol by constants from said source
of constants; and

said counter advances to select respective products of said constants and said respective terms for said previous received
symbol by providing an index into each said respective register to select a constant from said source of constants for multiplication
by said respective term of said polynomial.

US Pat. No. 9,323,538

SYSTEMS AND METHODS FOR MEMORY INTERFACE CALIBRATION

Altera Corporation, San ...

1. A method for calibrating memory interface circuitry on an integrated circuit using calibration circuitry on the integrated
circuit, wherein the calibration circuitry includes data storage circuitry and control signal storage circuitry, the method
comprising:
processing an instruction stored in the calibration circuitry by retrieving a data storage address and a control signal storage
address from the instruction;

retrieving test data from the data storage circuitry using the data storage address; and
retrieving control signal data from the control signal storage circuitry using the control signal storage address.

US Pat. No. 9,298,211

TIME DIVISION MULTIPLEXED MULTIPORT MEMORY IMPLEMENTED USING SINGLE-PORT MEMORY ELEMENTS

Altera Corporation, San ...

1. A method of operating memory having first and second ports, comprising:
receiving a first memory access request at the first port;
receiving a second memory access request and an associated clock signal at the second port;
with a control circuit, detecting a clock edge in the clock signal at the second port; and
in response to detecting the clock edge, using the control circuit to generate an additional clock signal.

US Pat. No. 9,275,178

METHOD AND APPARATUS FOR CONSIDERING PATHS INFLUENCED BY DIFFERENT POWER SUPPLY DOMAINS IN TIMING ANALYSIS

Altera Corporation, San ...

1. A method for modeling variation in a system, comprising:
generating timing graph traversal groups which divide a timing analysis problem into smaller sub-problems, wherein each timing
graph traversal group has an associated set of arrival paths and required paths;

identifying delay-impacting parameters associated with path elements in the arrival paths, that include a source clock path
and a data path, and the required paths, that include a destination clock path;

performing a first arrival time traversals for a first subset of the arrival paths and a first required time traversal for
a first subset of the required paths based on a first set of assumptions of values for a first subset of the delay-impacting
parameters associated with the path elements;

performing a second arrival time traversal for a second subset of the arrival paths and a second required time traversal for
a second subset of the required paths based on a second set of assumptions of values for a second subset of the delay-impacting
parameters, wherein assumptions for delay impacting parameters for a first timing graph traversal group are different from
assumptions for delay-impacting parameters for a second timing graph traversal group.

US Pat. No. 9,274,802

DATA COMPRESSION AND DECOMPRESSION USING SIMD INSTRUCTIONS

Altera Corporation, San ...

1. A computer system, comprising:
a data processor and memory accessible by the data processor, the memory storing computer programs executable by the data
processor, including at least one application program and a set of functions to implement operations to perform compression
of data samples from a data set, the at least one application program and the set of functions including single instruction
multiple data (SIMD) instructions for at least a portion of the operations to be executed by the data processor, the data
processor including a set of registers;

a first register of the register set to store a plurality of operands corresponding to an encoding group of data samples;
an exponent register of the register set, the data processor responsive to a SIMD instruction for operations to determine
a maximum exponent value of the plurality of operands in the first register and to store the maximum exponent value in the
exponent register;

interleaver logic to interleave bits of the operands in the first register to produce a plurality of nibbles to store in a
second register of the register set, wherein the interleaver logic maps the bits to a given nibble based on a place value
of the bits in respective operands;

a third register of the register set, the data processor responsive to a SIMD instruction for operations to select a subset
of nibbles from the plurality of nibbles in the second register to store in the third register, wherein a number of nibbles
for the subset is based on the maximum exponent value, wherein the subset of nibbles includes interleaved mantissa bits of
the operands; and

logic to pack the interleaved mantissa bits of the subset of nibbles from the third register to a compressed data packet,
wherein the packed interleaved mantissa bits represent compressed data for the encoding group of data samples.

US Pat. No. 9,154,134

CONFIGURABLE STORAGE ELEMENTS

Altera Corporation, San ...

1. An integrated circuit (“IC”) comprising:
a plurality of configurable logic circuits for configurably performing a plurality of logic operations based on configuration
data;

a configurable routing fabric for configurably routing signals among the configurable logic circuits, the configurable routing
fabric comprising a particular wiring path connecting an output of a source circuit to inputs of a destination circuit;

a first configuration retrieval path for retrieving configuration data for the source circuit; and
a second configuration retrieval path for retrieving configuration data for the destination circuit, wherein the first configuration
retrieval path is slower than the second configuration retrieval path.

US Pat. No. 9,112,519

APPARATUS AND METHODS OF RATE CONTROL FOR A SAMPLE RATE CONVERTER

Altera Corporation, San ...

1. An apparatus for sample rate conversion, the apparatus comprising:
baseband modulator and filter circuitry for receiving a data bitstream and using a sample request signal to generate an input
signal at an input sampling frequency;

a sample rate converter for receiving the input signal and using an interpolation interval to convert the input signal to
an output signal at an output sampling frequency, where the input sampling frequency and the output sampling frequency are
different;

a comparator for selecting a frequency control word from multiple frequency control words; and
a rate controller for using the frequency control word in generating the interpolation interval,
wherein the comparator compares the interpolation interval against a second number when an enable signal indicates that a
counter is at a first number modulo N.

US Pat. No. 9,369,372

METHODS FOR NETWORK FORWARDING DATABASE FLUSHING

Altera Corporation, San ...

1. A method of operating a network switch having ports at which network packets are received, the method comprising:
forming a plurality of port aging groups each associated with at least one respective port of the network switch;
maintaining aging threshold values each associated with a respective port aging group of the plurality of port aging groups;
performing network address learning operations to maintain a packet forwarding database having forwarding database entries
that are each associated with a corresponding port;

identifying expired forwarding database entries based on the aging threshold values;
identifying ports of the network switch that are associated with a network topology change; and
performing network address flushing operations on entries in the packet forwarding database using the aging threshold values,
wherein the network address flushing operations comprise temporarily disabling the network address learning operations on
the identified ports.

US Pat. No. 9,305,992

INTEGRATED CIRCUIT INDUCTORS WITH INTERTWINED CONDUCTORS

Altera Corporation, San ...

1. An inductor, comprising: a first terminal; a second terminal; and a conductive path coupled between the first and second
terminals, wherein the conductive path includes a plurality of intertwined conductive lines in an integrated circuit, wherein
each of the intertwined conductive lines extends for at least a distance in a direction that is parallel to a linear path
between the first and second terminals, wherein one of the plurality of intertwined conductive lines crosses over the remaining
conductive lines in a first crossover region in the conductive path, and wherein another one of the plurality of intertwined
conductive lines crosses under the remaining conductive lines in a second crossover region in the conductive path.

US Pat. No. 9,274,980

APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE DEVICES

Altera Corporation, San ...

1. A memory interface comprising:
a data output signal for providing, from a memory circuit, configuration data to an integrated circuit for configuring the
integrated circuit; and

a data input signal for providing an operation code from the integrated circuit to the memory circuit, wherein:
the integrated circuit includes hard-wired logic,
the hard-wired logic sends the operation code to the memory circuit via the data input signal of the memory interface,
the memory circuit sends the configuration data to the integrated circuit via the data output signal of the memory interface
in response to receiving the operation code, and

the integrated circuit initiates its configuration in response to receiving the configuration data.

US Pat. No. 9,648,728

CORELESS ORGANIC SUBSTRATE

Altera Corporation, San ...

1. Apparatus for mounting electrical components comprising:
a first coreless, organic substrate having first and second major surfaces and four corners;
holes extending through first portions of the first coreless, organic substrate near each corner;
pins that pass through the holes near each corner of the first coreless, organic substrate; and
an electrical circuit on a second portion of the first coreless, organic substrate, wherein the first portions of the first
coreless, organic substrate comprising the holes and the second portion of the first coreless, organic substrate under the
electrical circuit are a single contiguous substrate.

US Pat. No. 9,292,474

CONFIGURABLE HYBRID ADDER CIRCUITRY

Altera Corporation, San ...

1. Hybrid adder circuitry comprising:
a plurality of carry-select adders that produce sum signals from two input words, wherein the carry-select adders each produce
at least one carry signal based on a carry input signal;

a plurality of carry look-ahead units, each carry look-ahead unit receiving propagate and generate signals from a respective
one of the plurality of carry-select adders and each producing output signals; and

a carry computation unit that receives the output signals from each of the carry look-ahead units and that produces a carry
output signal, wherein the sum signals from the carry-select adders and the carry output signal from the carry computation
unit form an arithmetic sum of the two input words.

US Pat. No. 9,276,582

METHOD AND CIRCUIT FOR SCALABLE CROSS POINT SWITCHING USING 3-D DIE STACKING

Altera Corporation, San ...

13. A method of configuring a cross point switch on a first switching die for cross connections between a first plurality
of electronic components and a second plurality of electronic components on a component die, the first switching die including
a plurality of ingress stage switches each having outputs cross connected to inputs of a plurality of multiplexers, the plurality
of multiplexers each having outputs coupled to inputs of a plurality of middle stage switches, the first switching die over
the component die, the method comprising:
selecting a plurality of input ports for the cross point switch, the plurality of input ports coupled to the first plurality
of electronic components;

selecting a plurality of output ports for the cross point switch, the plurality of output ports coupled to the second plurality
of electronic components;

coupling the plurality of input ports to inputs of the ingress switches of the first switching die;
coupling the outputs of the middle stage switches to the plurality of output ports; and
controlling the multiplexers via configuration information to select the input ports or the outputs of the ingress stage switches
for sending signals to the inputs of the middle stage switches.

US Pat. No. 9,196,749

PROGRAMMABLE DEVICE WITH A METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR

Altera Corporation, San ...

1. A programmable device comprising:
a first well having a top surface and a bottom surface, the first well of a first conductivity type;
a transistor having a source region of a second conductivity type within the first well, a drain region of the second conductivity
type within the first well, an insulating layer disposed over the top surface of the first well, and a gate disposed over
the insulating layer;

a substrate region surrounding the first well, having a top surface and a bottom surface, the substrate region of the first
conductivity type;

a junction of the second conductivity type disposed within the substrate region;
a second well surrounding the substrate region, the second well having a top surface and a bottom surface, the second well
of the first conductivity type, wherein the junction, the first well and the second well are included as portions of a junction
field effect transistor (JFET); and

a guard ring surrounding the second well, the guard ring having a top surface and a bottom surface, the guard ring of the
second conductivity type.

US Pat. No. 9,256,266

NEGATIVE BIT LINE DRIVER CIRCUITRY

Altera Corporation, San ...

1. An integrated circuit comprising:
at least one multiport memory element supplied with a first power supply voltage and a second power supply voltage that is
less than the first power supply voltage;

a data line coupled to the at least one multiport memory element; and
a write driver circuit having an output coupled to the data line, wherein the write driver circuit is operable to generate
a signal that is equal to the second power supply voltage during a first time period and less than the second power supply
voltage during a second time period that is different than the first time period at its output.

US Pat. No. 9,223,743

MULTIPLIER OPERABLE TO PERFORM A VARIETY OF OPERATIONS

ALTERA CORPORATION, San ...

1. A programmable chip, comprising:
a plurality of programmable logic elements;
a hard-coded multiplier implemented using only AND gates and adders, the hard-coded multiplier configured to receive a first
operand over a plurality of first operand input lines and a second operand over a plurality of second operand input lines
and to provide a first output over a plurality of first output lines, wherein the plurality of first operand input lines and
the plurality of second operand input lines are all inputs to the hard-coded multiplier,

wherein a subset of the plurality of first operand input lines and a subset of the second plurality of input lines are grounded
such that the hard-coded multiplier provides only two-input logic operations on a subset of the first plurality of output
lines,

wherein the hard-coded multiplier uses hard-coded logic to perform shifting, rotation, and multiplication operations in addition
to hard-coded two-input logic operations, and wherein a subset of the plurality of output lines provides a plurality of XOR
and non-XOR functions.

US Pat. No. 9,100,531

METHOD AND APPARATUS FOR PERFORMING ROBUST CADENCE DETECTION IN A VIDEO DEINTERLACER

Altera Corporation, San ...

1. A method for processing interlaced video, comprising:
combining each field in a plurality of consecutive fields of the interlaced video to be combined with its preceding field
into a frame and with its subsequent field into another frame to obtain a plurality of combined frames;

determining a comb factor of each of the combined frames to obtain a sequence of comb factors of the combined frames by determining
a comb factor value of each pixel in the frame and accumulating the comb factor value over all of the pixels within the frame
to obtain the comb factor of that frame, and declaring the comb factor of a combined frame to be a high value if the accumulated
comb factor value over all the pixels within the combined frame exceeds a pre-determined threshold while declaring the comb
factor of the combined frame to be a low value if the accumulated comb factor value does not exceed the pre-determined threshold;
and

determining if the sequence of comb factors of the combined frames follows a pre-determined repeating pattern.

US Pat. No. 9,270,500

APPARATUS AND METHODS OF DYNAMIC TRANSMIT EQUALIZATION

Altera Corporation, San ...

1. An integrated circuit comprising:
physical coding circuitry for encoding data bytes for transmission and decoding received data bytes;
media access control circuitry for controlling link initialization and training;
an interface between the physical coding and the media access control circuitry;
an equalization control circuit, external to the physical coding circuitry, wherein the equalization control circuit performs
dynamic transmit equalization using said interface to refine receiver coefficients during a phase where the integrated circuit
operates as a slave and refine transmitter coefficients during a phase where the integrated circuit operates as a master;
and

a preset-to-coefficient converter in the media access control circuitry which converts transmitter preset data to transmitter
coefficient data.

US Pat. No. 9,270,274

FPGA CONFIGURATION DATA SCRAMBLING USING INPUT MULTIPLEXERS

Altera Corporation, San ...

1. A method of configuring an integrated circuit, the method comprising:
receiving a first portion of configuration data with a plurality of multiplexers, wherein the configuration data is received
at an input port to the integrated circuit; and

retrieving a first portion of a key from memory;
selecting inputs of the plurality of multiplexers under control of the first portion of the key;
storing the selected inputs of the plurality of multiplexers; and
receiving a second portion of the configuration data with the plurality of multiplexers; and
retrieving a second portion of the key from the memory;
selecting inputs of the plurality of multiplexers under control of the second portion of the key, wherein the selecting of
the inputs multiplexes the first and second portions of the configuration data under control of the first and second portions
of the key retrieved from the memory to descramble the configuration data;

storing the selected inputs of the plurality of multiplexers; and
configuring the integrated circuit using the stored selected inputs of the plurality of multiplexers.

US Pat. No. 9,191,617

USING FPGA PARTIAL RECONFIGURATION FOR CODEC APPLICATIONS

Altera Corporation, San ...

1. An apparatus that communicates data with at least two stations, the apparatus comprising:
at least one communication channel for each respective station, data carried within each communication channel being compressed
in accordance with an associated codec standard, the codec standard being at least partially selected in view of characteristics
of the respective station;

a programmable logic device (PLD), the PLD being partially reconfigurable; and
a control unit that selects between two or more personas to be used within a reconfigurable region of the PLD, wherein the
control unit partially reconfigures the PLD by instantiating a subset of the two or more personas, each persona within the
subset being compatible with at least a portion of the associated codec of at least one communication channel.

US Pat. No. 9,172,505

METHODS AND APPARATUS FOR FRAME DETECTION

Altera Corporation, San ...

1. A frame detection circuit for detecting a frame boundary in a sequence of bits, the circuit comprising:
a first buffer for storing a first received frame of bits, wherein a width of the first buffer is a number of bits in one
word in the sequence of bits;

a second buffer for storing a second received frame of bits, wherein a width of the second buffer is the number of bits in
the one word; and

a staged-parallel structure of syndrome computation circuits that computes a number of syndromes in one cycle, wherein the
number of the syndromes computed in one cycle is a fraction of the number of bits in the one word, and wherein each syndrome
computation circuit in the staged-parallel structure has inputs consisting of a preceding syndrome, a head bit from the first
received frame and a tail bit from the second received frame.

US Pat. No. 9,313,132

STANDALONE OAM ACCELERATION ENGINE

Altera Corporation, San ...

1. A method for implementing an Operation, Administration, and Management (OAM) co-processor that is connected to a switch,
the method comprising:
receiving input data at an ingress engine;
determining whether the input data comprises OAM information;
in response to determining that the input data does not comprise OAM information, transmitting the input data to the switch,
wherein the input data is processed at the switch; and

in response to determining that the input data does comprise OAM information, processing the input data at the ingress engine;
receiving output data at an egress engine from the switch;
determining whether the output data comprises OAM information;
in response to determining that the output data does not comprise OAM information, forwarding the output data to a next hop;
in response to determining that the output data does comprise OAM information, processing the output data at the egress engine;
maintaining a first queue for a first plurality of output data including the output data, wherein the first plurality of output
data is associated with a first traffic control parameter, and wherein the first plurality of output data comprises both OAM
data and non-OAM data;

maintaining a second queue for a second plurality of output data including the output data, wherein the second plurality of
output data is associated with a second traffic control parameter, and wherein the second plurality of output data comprises
both OAM data and non-OAM data; and

selectively scheduling transmission of data in the first queue and the second queue based on the first traffic control parameter
and the second traffic control parameter.

US Pat. No. 9,292,638

METHOD AND APPARATUS FOR PERFORMING TIMING CLOSURE ANALYSIS WHEN PERFORMING REGISTER RETIMING

Altera Corporation, San ...

1. A method for designing a system on a target device, comprising:
performing register retiming on the system;
detecting a critical chain in the system in response to the register retiming, wherein the critical chain includes a plurality
of register-to-register paths and where improving timing on one of the register-to-register paths improves timing on other
register-to-register paths; and

modifying the system in response to properties of the critical chain, wherein the modifying includes removing register retiming
constraints that prohibit movement of a register for register retiming, and wherein at least one of the performing, detecting,
and modifying is performed by a processor.

US Pat. No. 9,279,850

PHYSICALLY UNCLONABLE FUNCTIONS WITH ENHANCED MARGIN TESTING

Altera Corporation, San ...

1. An apparatus for identifying stable physically unclonable function (PUF) cells, the apparatus comprising:
an array of PUF cells;
a bias control circuit having a plurality of bias control lines, wherein the bias control lines apply one or more bias control
signals to each PUF cell in the array of PUF cells; and

a selector circuit that selects a subset of the PUF cells in the array of PUF cells based on whether outputs of the PUF cells
in the array of PUF cells change in response to application of the bias control signals.

US Pat. No. 9,274,951

CACHE MEMORY CONTROLLER FOR ACCELERATED DATA TRANSFER

Altera Corporation, San ...

1. A computer system, comprising:
a central processing unit (CPU) responsive to instructions of a computer program;
a plurality of application accelerator processors in communication with the CPU;
a first memory storing compressed application data and having a plurality of buffers allocated therein;
a memory controller connected to the first memory;
a cache memory; and
a cache memory controller in communication with the CPU, the application accelerator processors, the cache memory, and the
memory controller, the cache memory controller including an encoder to compress application data from the application accelerator
processors for writes to the first memory and a decoder to decompress compressed application data from reads of the first
memory,

wherein the CPU is responsive to instructions to allocate the buffers in the first memory to store the application data provided
by respective application accelerator processors and to provide location parameters representing sets of memory addresses
allocated for the respective buffers to the cache memory controller, and

wherein the cache memory controller monitors memory addresses specified in respective read requests and write requests to
the memory controller.

US Pat. No. 9,264,276

ADAPTATIONS FOR PARTIAL RESPONSE SUMMATION NODE EMBEDDED FPGA TRANSCEIVER

ALTERA CORPORATION, San ...

1. Adaptation circuitry for processing a data signal, the adaptation circuitry comprising:
a data slicing level (dLev) Digital-to-Analog Convertor (DAC) for outputting a predicted dLev value associated with the data
signal;

summation node circuitry, coupled to the dLev DAC, for processing an error value associated with the data signal based on
the predicted dLev value; and

adaptation engine circuitry, coupled to the summation node circuitry, for controlling an operation of the summation node circuitry.

US Pat. No. 9,335,343

CONTACTOR FOR REDUCING ESD IN INTEGRATED CIRCUIT TESTING

Altera Corporation, San ...

1. A test contactor comprising:
a Printed Circuit Board (PCB) configured to transfer electrical signals through a plurality of signal pathways, wherein the
plurality of signal pathways couples a signal source to a signal destination;

a first test contact coupled to a first signal pathway of the plurality of signal pathways, wherein the first test contact
is configured to transfer the electrical signals; and

a second test contact coupled to a second signal pathway of the plurality of signal pathways, wherein the second test contact
is configured to provide a ground voltage, and

wherein the first test contact and the second test contact are pogo pins or spring probes, and a length of the second test
contact is greater than a length of the first test contact and a spring constant of the first test contact is greater than
a spring constant of the second test contact, and wherein the spring constant of the first test contact and the spring contact
of the second test contact are tuned so that, with the Printed Circuit Board pressed to a Device Under Test (DUT), the first
test contact is compressed to a same compressed length as the second test contact and the first test contact presses on the
Device Under Test with a same force as the second test contact.

US Pat. No. 9,252,776

SELF-CONFIGURING COMPONENTS ON A DEVICE

ALTERA CORPORATION, San ...

1. A method of designing an electronic device, comprising:
receiving a specification of a first component on the electronic device having a first component output interface;
receiving a specification of a second component on the electronic device having a second component input interface; and
performing, using a processor, self-configuration of the second component input interface using parameter information obtained
from the first component so that the second component is interoperable with the first component.

US Pat. No. 9,229,888

AREA-EFFICIENT DYNAMICALLY-CONFIGURABLE MEMORY CONTROLLER

Altera Corporation, San ...

1. An integrated circuit comprising a dynamically-reconfigurable memory controller block, wherein:
the dynamically-reconfigurable memory controller block is reconfigurable, at run time, between: a first memory controller
configured to transmit data at a first data rate and a second memory controller configured to transmit data at a second data
rate, the first data rate being different from the second data rate,

the dynamically-reconfigurable memory controller block is reconfigurable in response to dynamic run-time conditions during
operation, and

the dynamically-reconfigurable memory controller block includes a first set of memory controller resources to be used by the
first memory controller, a second set of memory controller resources to be used by the second memory controller, and a third
set of memory controller resources to be shared by the first and second memory controllers, wherein the third set of memory
controller resources includes one or more of a command queue, a first first-in-first-out buffer, an error code checker, bank
tracker, a command interface and a control interface.

US Pat. No. 9,111,121

METHOD AND APPARATUS FOR SECURING A PROGRAMMABLE DEVICE USING A KILL SWITCH

Altera Corporation, San ...

1. A programmable device, comprising:
a control block;
a kill switch coupled to the control block, wherein the control block is configured to blow the kill switch in response to
an occurrence of an event, wherein blowing the kill switch causes data stored within at least a portion of the programmable
device to be changed; and

a plurality of key fuses for storing fuse bits representing a decryption key, wherein at least one of the key fuses is blown
in response to the kill switch being blown.

US Pat. No. 9,461,837

CENTRAL ALIGNMENT CIRCUTRY FOR HIGH-SPEED SERIAL RECEIVER CIRCUITS

Altera Corporation, San ...

1. A method for operating serial receiver circuitry comprising:
receiving serial data over a plurality of serial lanes;
with an alignment circuit that controls the alignment of the plurality of serial lanes, identifying a current order of the
serial lanes; and

with the alignment circuit, configuring a multi-stage switching network to arrange the serial lanes in a desired order based
on the current order.

US Pat. No. 9,300,421

METHODS TO ACHIEVE ACCURATE TIME STAMP IN IEEE 1588 FOR SYSTEM WITH FEC ENCODER

Altera Corporation, San ...

1. A communication system for an integrated circuit, the system comprising:
transmitter circuitry including:
a medium access control (MAC) layer; and
a forward error correction (FEC) layer coupled to the MAC layer by a data link and a feedback link, wherein the MAC layer
is operable to send a message to the FEC layer on the data link, wherein the FEC layer asserts a feedback signal on the feedback
link when the message arrives at the FEC layer, and wherein the MAC layer determines a timestamp value associated with the
message based on the asserted feedback signal.

US Pat. No. 9,100,031

METHOD AND SYSTEM FOR DYNAMIC TABLE LINE ENCODING

Altera Corporation, San ...

1. A system comprising:
a first input for receiving a first data value;
a memory device for providing a second data value based on the first data value, wherein the second data value is a representation
of the first value according to a first scheme; and

a first output for providing the second data value.

US Pat. No. 9,281,974

EQUALIZER CIRCUITRY HAVING DIGITALLY CONTROLLED IMPEDANCES

Altera Corporation, San ...

1. An integrated circuit, comprising:
an equalizer circuit that provides high-frequency signal boosting and that includes adjustable impedance circuitry, wherein
the adjustable impedance circuitry receives digital control signals and comprises:

a first capacitor having first and second terminals;
a second capacitor having first and second terminals; and
a control terminal that is connected to the first terminal of the first capacitor and to the first terminal of the second
capacitor.

US Pat. No. 9,270,279

APPARATUS AND METHODS FOR TIME-MULTIPLEX FIELD-PROGRAMMABLE GATE ARRAYS

Altera Corporation, San ...

1. A time-multiplexed field programmable gate array (TM-FPGA), comprising:
a plurality of programmable logic circuits, each programmable logic circuit comprising at least one context register; and
programmable interconnect circuitry,
wherein a user's circuit can be mapped to the plurality of programmable logic circuit and the programmable interconnect circuitry
without the user's intervention in mapping the circuit to the at least one context register.

US Pat. No. 9,300,958

METHODS AND APPARATUS FOR MOTION SEARCH REFINEMENT IN A SIMD ARRAY PROCESSOR

Altera Corporation, San ...

1. An apparatus for a motion search refinement function, the apparatus comprising:
a processing element (PE) having an execution unit and the PE coupled by a first interconnection path to a local PE data memory,
wherein the PE executes program instructions that output a memory address and control information from the execution unit
to initiate operation of a motion search refinement function of video compression; and

a hardware assist (HA) unit coupled to the execution unit and separately coupled by a second interconnection path to the local
PE data memory, the HA unit responds to the memory address and the control information received from the PE to initiate the
motion search refinement function on the HA unit, to read row data over the second interconnection path from the local PE
data memory that is filtered by a first 2J-tap filter and interleaved to form interpolated row results overlapped with writing
of the interpolated row results to a transpose memory configured to operate in the HA unit, wherein the row data is a row
of pixels from a (J+L+J)×(J+L+J) pixel window, L is a number of the form 2n, n is an integer greater than one, and J is a positive integer, wherein the interpolated row results are read in transpose
order from the transpose memory as transposed output and then filtered by a second 2J-tap filter and interleaved to form interpolated
column results that are stored over the second interconnection path in the local PE data memory to assemble a (2L+3)×(2L+3)
search window for the motion search refinement function of video compression, wherein (2L+3) is greater than (J+L+J).

US Pat. No. 9,298,457

SIMD INSTRUCTIONS FOR DATA COMPRESSION AND DECOMPRESSION

Altera Corporation, San ...

1. A data processor, comprising:
an execution unit configured to execute single instruction multiple data (SIMD) instructions, the execution unit including
logic responsive to a first SIMD instruction (V_EXPMAX) that includes a multiple data identifier that identifies multiple
operands to determine a maximum exponent value of the multiple operands identified by the multiple data identifier, the execution
unit including logic to pack a number of bits from each of the plurality of operands based on the maximum exponent value determined
in response to the first SIMD instruction to form the compressed data group, wherein the compressed data group represents
the plurality of operands.

US Pat. No. 9,251,300

METHODS AND TOOLS FOR DESIGNING INTEGRATED CIRCUITS WITH AUTO-PIPELINING CAPABILITIES

Altera Corporation, San ...

1. A method for using circuit design computing equipment, the method comprising:
with the circuit design computing equipment, receiving a path description for a path that conductively couples a source node
to a destination node in an integrated circuit, wherein the path description includes a plurality of path implementations
for the path, and wherein a predetermined number of pipeline registers is associated with each path implementation in the
plurality of path implementations;

with the circuit design computing equipment, receiving a target criterion for the path, wherein the target criterion for the
path are selected from the group consisting of: performance, area usage, number of registers, power dissipation, clock rate,
throughput, and latency;

with the circuit design computing equipment, receiving a pipeline optimization constraint for the path, wherein the pipeline
optimization constraint specifies at least one allowable number of pipeline registers for the path; and

with the circuit design computing equipment, selecting a target path implementation that satisfies the target criterion, the
target path implementation being selected from the plurality of path implementations, and the predetermined number of pipeline
registers associated with the target path implementation is one of the at least one allowable number of pipeline registers
for the path.

US Pat. No. 9,158,547

METHODS AND APPARATUS FOR SCALABLE ARRAY PROCESSOR INTERRUPT DETECTION AND RESPONSE

Altera Corporation, San ...

1. A method of operating a pipeline, the method comprising:
initiating execution of a first instruction in parallel with a second instruction in a processor, wherein the first instruction
is a one cycle execution instruction and the second instruction is a two cycle execution instruction;

receiving a notification of an interrupt in the processor before completing the execution of the first instruction and before
completing the execution of the second instruction;

completing the execution of the first instruction and saving a first execution result in a target register specified by the
first instruction;

completing the execution of the second instruction and saving a second execution result in an interrupt forwarding register
in response to the notification without saving the second execution result in a target register specified by the second instruction;
and

restoring the second execution result from the interrupt forwarding register to the target register specified by the second
instruction on a return from interrupt.

US Pat. No. 9,250,859

DETERMINISTIC FIFO BUFFER

Altera Corporation, San ...

1. A method for determining an average latency of a first-in-first-out buffer, the method comprising:
applying input-comparison logic to a first input comprising a highest-order read bit from a read counter and a second input
comprising a highest-order write bit from a write counter, wherein the input-comparison logic differentiates between the first
and second inputs having a same logic level and the first and second inputs having different logic levels;

generating an output signal by the input-comparison logic; and
determining an occupancy level of the first-in-first-out buffer based on the output signal from the input-comparison logic,
wherein a delay difference is known between a first signal delay from the read counter to the input-comparison logic and a
second signal delay from the write counter to the input-comparison logic, and wherein said delay difference is used in determining
the occupancy level.

US Pat. No. 9,106,936

RAW FORMAT IMAGE DATA PROCESSING

Altera Corporation, San ...

1. A method, comprising:
receiving a raw format image from an image capture device within an image capture time window, the raw format image including
a plurality of pixel samples representing an image;

compressing the raw format image using only a time domain compression process to form a compressed raw format image during
a time interval that is less than or equal to the image capture time window;

transferring the compressed raw format image across a data channel to a receiving device within a transfer window having a
time duration less than or equal to the image capture time window;

decompressing the compressed raw format image after said transferring to form a recovered raw format image; and
applying digital signal processing to the recovered raw format image.

US Pat. No. 9,251,305

METHOD AND APPARATUS FOR ANALYZING STRUCTURED CELL CANDIDATES FOR STRUCTURED APPLICATION SPECIFIC INTEGRATED CIRCUITS

Altera Corporation, San ...

1. A method for evaluating structured cells on a target device, the method comprising:
identifying logic functions implementable by a candidate structured cell on the target device by connecting one or more components
in the candidate structured cell together to generate a circuit, determining whether the circuit satisfies a set of wiring
rules, determining output values for given input values for the circuit, and deriving a truth table that describes one or
more logic functions implemented by the circuit from the determination, wherein the candidate structured cell comprises a
plurality of gates configurable to be coupled together and the logic functions are implemented by connecting a subset of the
plurality of gates together;

generating a cell library with a subset of the logic functions implementable by the structured cell;
implementing a system on the target device using the subset of logic functions in the cell library; and
evaluating the system on the target device, wherein at least one of the identifying, generating, implementing, and evaluating
is performed using a processor.

US Pat. No. 9,225,335

CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES

ALTERA CORPORATION, San ...

1. Clock distribution circuitry for an integrated circuit, the clock distribution circuitry comprising:
a deterministic clock distribution portion;
a user-configurable clock distribution conductor located within a predetermined area of the integrated circuit; and
configurable logic elements (LEs) on the predetermined area of the integrated circuit, the configurable LEs being custom-configurable
by a user to selectably be configured to:

(a) function as clock distribution buffer circuitry, for routing, through the user-configurable clock distribution conductor,
a clock signal from the deterministic clock distribution portion to clock utilization circuitry within the predetermined area
of the integrated circuit, and

(b) perform logic functions when not functioning as the clock distribution buffer circuitry.

US Pat. No. 9,240,804

TECHNIQUES FOR ALIGNMENT OF PARALLEL SIGNALS

Altera Corporation, San ...

1. A circuit comprising:
a serial-to-parallel converter circuit to convert a serial data signal into first parallel data signals;
phase detection circuitry to generate an indication of a phase shift based on a phase offset between a first periodic signal
and a second periodic signal; and

a clock signal generation circuit to provide an adjustment to a phase of the first periodic signal based on the indication
of the phase shift, the serial-to-parallel converter circuit to adjust a word boundary of the first parallel data signals
by a number of bit positions that is determined by the adjustment to the phase of the first periodic signal.

US Pat. No. 9,224,433

METHOD AND APPARATUS FOR POWER SUPPLY AWARE MEMORY ACCESS OPERATIONS IN AN INTEGRATED CIRCUIT

Altera Corporation, San ...

1. An integrated circuit comprising:
a power supply rail that conveys a power supply voltage;
a storage circuit that performs memory access operations using the power supply voltage from the power supply rail;
a control circuit that controls the memory access operations performed by the storage circuit based at least in part on a
comparison between the power supply voltage conveyed by the power supply rail and a nominal voltage; and

a reference voltage generator coupled to the control circuit that generates the nominal voltage and provides the nominal voltage
to the control circuit, wherein the nominal voltage is the targeted operating voltage of the power supply rail.

US Pat. No. 9,222,972

ON-DIE JITTER GENERATOR

Altera Corporation, San ...

1. An integrated circuit (IC) comprising:
a jitter generator, wherein the jitter generator is integral with the IC and generates non-intrinsic jitter, wherein the jitter
generator comprises:

a low frequency jitter generator (LFJG); and
a high frequency jitter generator (HFJG) coupled to the LFJG;
a multiplexer coupled to the LFJG and HFJG, wherein the multiplexer includes a first input terminal coupled to an output terminal
of the LFJG, a second input terminal coupled to an output terminal of the HFJG, and a third input terminal coupled to a normal
transmit data signal input.

US Pat. No. 9,086,434

METHODS AND SYSTEMS FOR VOLTAGE REFERENCE POWER DETECTION

ALTERA CORPORATION, San ...

1. A method for determining a value of a reset signal, the method comprising:
setting a first signal to be proportional to a power supply voltage in response to a determination from control circuitry
that an output voltage of bandgap voltage reference circuitry is less than a first threshold voltage;

setting the first signal to a logic low level in response to a determination from the control circuitry that the output voltage
of the bandgap voltage reference circuit is greater than the first threshold voltage, wherein:

the first threshold voltage is less than a bandgap reference voltage; and
determining the value of the reset signal based at least in part on the first signal.

US Pat. No. 10,031,846

TRANSPOSITION OF TWO-DIMENSIONAL ARRAYS USING SINGLE-BUFFERING

Altera Corporation, San ...

1. An address generator circuit for addressing a storage circuit, comprising:a status flag generation circuit that generates a plurality of status flag signals;
a modulo adder circuit that receives first and second signals and computes a modulo adder output signal based on the first and second signals; and
an address processing circuit that receives the modulo adder output signal from the modulo adder circuit and the plurality of status flag signals from the status flag generation circuit, wherein the address processing circuit provides the first and second signals to the modulo adder circuit and generates address signals for read and write access operations of the storage circuit, wherein the write access operation stores a two-dimensional array in the storage circuit and the read access operation retrieves a transpose of the two-dimensional array from the storage circuit.

US Pat. No. 9,201,097

METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUIT DIE WITH A PARTIALLY COMPLETED AND VALIDATED MODULE

Altera Corporation, San ...

1. An apparatus for electrically testing an IC die, comprising:
a partially completed and validated module including:
an IC package substrate,
one or more known good IC dice attached on a first surface of the IC package substrate at first regions, and
package pads on the first surface of the IC package substrate at a second region;
a pick and place tool for positioning a test subject IC die on the second region of the IC package substrate such that interconnection
bumps of the test subject IC die are facing and aligned with the package pads of the module, the positioned test subject IC
die and the module forming a multi-die flip-chip test assembly; and

test circuitry electrically connected with the module for electrically testing the multi-die flip-chip test assembly without
the test subject IC die being attached to the module.

US Pat. No. 9,673,173

INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED PASSIVE STRUCTURES

Altera Corporation, San ...

1. A method of manufacturing an integrated circuit package, comprising:
encapsulating first and second integrated circuit dies with a molding compound;
forming a passive component over the molding compound;
encapsulating the passive component in additional molding compound, wherein the additional molding compound directly contacts
the molding compound; and

mounting the encapsulated first and second integrated circuit dies on a redistribution wafer, wherein the first integrated
circuit die is interposed between the passive component and the redistribution wafer.

US Pat. No. 9,203,408

RECONFIGURABLE LOGIC ANALYZER CIRCUITRY

Altera Corporation, San ...

1. Logic analyzer circuitry, comprising:
storage circuitry that stores incoming data;
logic analyzer control circuitry that controls the storage circuitry; and
partial-reconfiguration controller circuitry that reconfigures the logic analyzer control circuitry.

US Pat. No. 9,195,793

METHOD AND APPARATUS FOR RELOCATING DESIGN MODULES WHILE PRESERVING TIMING CLOSURE

Altera Corporation, San ...

1. A method for designing a system on a target device, comprising:
generating a solution for the system;
preserving a solution for a module of the system identified by a user; and
implementing the preserved solution for the module at a location on the target device identified by the user which is a different
location than which the preserved solution is based on.

US Pat. No. 9,508,785

SEMICONDUCTOR DEVICE INCLUDING A RESISTOR METALLIC LAYER AND METHOD OF FORMING THE SAME

Altera Corporation, San ...

1. A semiconductor device, comprising:
a source region and a drain region of a semiconductor switch on a substrate; and
a resistor metallic layer over said source region and said drain region of said semiconductor switch, said resistor metallic
layer comprising a first resistor including a first resistor metallic strip coupled between a first cross member and a second
cross member.

US Pat. No. 9,490,814

CONFIGURABLE IC HAVING A ROUTING FABRIC WITH STORAGE ELEMENTS

Altera Corporation, San ...

1. A method for routing signals in an integrated circuit (IC) that comprises a plurality of configurable circuit interconnected
by a routing fabric, the method comprising:
transmitting a first signal from a first configurable circuit of the IC to a second configurable circuit of the IC by using
a particular path of the routing fabric that connects the first circuit to the second circuit without an intervening signal
storage element;

storing the first signal along the particular path; and
while storing said first signal along the particular path, passing a second signal from the first circuit to the second circuit
along the particular path.

US Pat. No. 9,473,112

CLOCK GRID FOR INTEGRATED CIRCUIT

Altera Corporation, San ...

1. A switch box for interconnecting clock-type signals in an integrated circuit, the switch box comprising:
a dedicated clock-type signal line, connected to a clock distribution spine on said integrated circuit, said dedicated clock-type
signal line for conducting a selectable one of a first clock-type signal in a first direction and a second clock-type signal
in a second direction;

a selection circuitry for selecting as a selection output, one of the first clock signal in the first direction and the second
clock signal in the second direction; and

a distributed deskewing object having a first input corresponding to the selection output of the selection circuitry and a
second input corresponding to a clocking signal from the clock distribution spine, and an output coupled to the clock distribution
spine.

US Pat. No. 9,412,436

MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY

Altera Corporation, San ...

1. A memory element comprising:
first, second, third, fourth, and fifth transistor pairs each of which forms an inverter-type circuit and that collectively
form a bistable cell, wherein each of the transistor pairs receives at least two distinct logic signal inputs, wherein the
at least two distinct logic signal inputs comprise a first logic signal input from one of the transistor pairs of the first,
second, third, fourth, and fifth transistor pairs, wherein the at least two distinct logic signal inputs further comprise
a second logic signal input from another one of the transistor pairs of the first, second, third, fourth, and fifth transistor
pairs, and wherein each of the first, second, third, fourth, and fifth transistor pairs comprises:

first and second transistors that are connected together in series; and
a common node between the first and second transistors, wherein the first transistor in the first transistor pair has a first
source-drain terminal connected to the common node of the first transistor pair and has a second source-drain terminal connected
to the common node of the second transistor pair.

US Pat. No. 9,053,045

COMPUTING FLOATING-POINT POLYNOMIALS IN AN INTEGRATED CIRCUIT DEVICE

Altera Corporation, San ...

1. Polynomial circuitry for calculating a polynomial having terms including powers of an input variable, said input variable
represented by a mantissa and an exponent, said circuitry comprising:
at least one respective coefficient table corresponding to a respective one of said terms of said polynomial; wherein:
for each respective one of said terms of said polynomial, each respective coefficient table is loaded with a plurality of
respective instances of a respective coefficient for said respective one of said terms of said polynomial, and

respective instances of said respective coefficient for said respective one of said terms of said polynomial are multiple
versions of said respective coefficient, each version being shifted by a different number of bits; and

respective decoder circuitry associated with each respective one of said coefficient tables, said respective decoder circuitry
selecting one of said instances of said respective coefficient for said respective one of said terms of said polynomial based
on said exponent and on a range, from among a plurality of ranges, of input values into which said input variable falls.

US Pat. No. 9,342,402

MEMORY INTERFACE WITH HYBRID ERROR DETECTION CIRCUITRY FOR MODULAR DESIGNS

Altera Corporation, San ...

1. An integrated circuit, comprising:
user logic circuitry configured to implement a custom function;
non-programmable memory interface logic that communicates with external memory; and
programmable memory interface logic interposed between the non-programmable memory interface logic and the user logic circuitry.

US Pat. No. 9,240,912

TRANSCEIVER CIRCUITRY WITH SUMMATION NODE COMMON MODE DROOP REDUCTION

Altera Corporation, San ...

1. An integrated circuit, comprising:
a differential amplifier having a power supply terminal and an output;
an operational amplifier having an input that receives a common mode sensing voltage from the output of the differential amplifier
and an output that is connected to the power supply terminal of the differential amplifier;

a digital sampler that receives signals from the output of the differential amplifier and that has an output;
a digital flip-flop that receives signals from the output of the digital sampler and that has an output; and
a summation node circuit that is coupled to the output of the differential amplifier and that has a first input that is coupled
to the output of the digital sampler, a second input that is coupled to the output of the digital flip-flop, and an output
that is coupled to an input of the digital sampler.

US Pat. No. 9,123,437

SCALEABLE LOOK-UP TABLE BASED MEMORY

Altera Corporation, San ...

1. An integrated circuit (IC) having configurable memory elements, comprising;
data paths having dedicated multiplexers; and
a control block generating control signals for each of the dedicated multiplexers, the control signals determining whether
the configurable memory elements are utilized as one of a configuration random access memory or a static random access memory.

US Pat. No. 9,048,823

DUTY CYCLE DISTORTION CORRECTION CIRCUITRY

Altera Corporation, San ...

1. A circuit, comprising:
an input that receives a control signal having a duty cycle;
an output on which an output clock signal is generated, wherein the output clock signal has an adjustable duty cycle that
is different than the duty cycle of the control signal; and

an additional input that receives an additional control signal, wherein the control signal is a delayed version of the additional
control signal, and wherein the control signal is delayed by an amount with respect to the additional control signal that
sets the adjustable duty cycle of the output clock signal.

US Pat. No. 9,438,272

DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS

Altera Corporation, San ...

1. Apparatus for converting parallel data to serial data, the apparatus comprising:
serializer circuitry for:
receiving, at a first clock rate, the parallel data; and
outputting, at a second clock rate, each bit of the parallel data, one bit after another in succession; and
circuitry for replicating each bit that is output by the serializer onto a number of parallel leads, wherein the number is
based on a ratio of the first clock rate and the second clock rate.

US Pat. No. 9,424,088

MULTI-LEVEL DEFICIT WEIGHTED ROUND ROBIN SCHEDULER ACTING AS A FLAT SINGLE SCHEDULER

Altera Corporation, San ...

9. A multi-level scheduler, implemented using a plurality of sub schedulers, the plurality of sub schedulers together performing
functions of a single conventional scheduler, the multi-level scheduler comprising:
one or more first level sub schedulers from the plurality of sub schedulers;
one or more second level sub schedulers from the plurality of sub schedulers;
memory; and
a processor configured to:
create subgroups from a group of entities desiring access to a shared resource;
assign each subgroup of entities from the group of entities to a sub scheduler of the plurality of sub schedulers at the first
level of the multi-level scheduler,

wherein each first level sub scheduler from the plurality of sub schedulers determines a first level result entity from among
its assigned subgroup to access the shared resource;

send outputs of the first level sub schedulers as inputs to a second level sub scheduler, the second level sub scheduler selecting
from among the inputs it receives from the first level sub schedulers to determine a second level result entity to access
the shared resource, wherein selecting among the inputs includes:

monitoring a volume of traffic associated with each of the entities from the group of entities assigned to the plurality of
sub schedulers at the first level of the multi-level scheduler;

calculating weights to assign to each input of the second level sub scheduler based at least in part on the monitored traffic
load associated with each entity from the group of entities assigned to the plurality of sub schedulers at the first level
of the multi-level scheduler;

selecting the input to the second level scheduler to be provided access to the shared resource based on the weights assigned
to each input of the second level sub scheduler;

providing an indication to a First-In First-Out (FIFO) associated with one of the first level sub schedulers to provide a
first packet to be provided to the second level sub scheduler;

providing the first packet to the shared resource;
providing an indication of a capacity of the FIFO to the first level sub scheduler associated with the FIFO following the
providing of the first packet to the second level sub scheduler; and

storing a second packet received from the first level sub scheduler associated with the FIFO in the FIFO based on the indication
of the capacity of the FIFO.

US Pat. No. 9,110,128

IC PACKAGE FOR PIN COUNTS LESS THAN TEST REQUIREMENTS

Altera Corporation, San ...

1. An integrated circuit (IC) package, comprising: a surface of said IC having a plurality of contact leads disposed thereon,
wherein the plurality of contact leads comprises solder balls affixed to the surface of the IC package; and a plurality of
contact pads disposed on the surface of the IC package, wherein the plurality of contact pads is adjacent to the plurality
of contact leads, wherein the plurality of contact pads comprises a substantially flat outer surface extending from the surface
of the IC package, wherein the outer surface of each contact pad of the plurality of contact pads extends from the surface
of the IC package by a first elevation and a surface of each of the solder balls of the plurality of contact leads extends
from the surface of the IC package by a second elevation; a socket body having a plurality of test pins, wherein a first portion
of the plurality of test pins is configured to contact the plurality of contact pads when engaged with the IC package and
a second portion of the plurality of test pins is configured to contact the plurality of contact leads when engaged with the
IC package, wherein each test pin of the first portion of the plurality of test pins and each test pin of the second portion
of the plurality of test pins are adjustable in height to accommodate the first elevation and the second elevation, respectively,
when engaged with the IC package, and wherein a first portion of the plurality of contact leads forming a first ring of contact
leads is arranged in an inner perimeter area of the surface of the IC package, the first ring of contact leads is exclusive
of any contact pads, and a first portion of the plurality of contact pads forming a first ring of contact pads along an outermost
perimeter area and the first ring of contact pads is exclusive of any contact leads, and wherein the first ring of contact
pads is arranged adjacent to the first ring of contact leads, wherein at least a second portion of the plurality of contact
leads forming a second ring of contact leads is arranged adjacent to first ring of contact pads on the surface of the IC package,
the second ring of contact leads exclusive of any contact pads, wherein at least a third portion of the plurality of contact
leads is arranged in a grid pattern on the surface of the IC package and is located in a center area of the surface of the
IC package, wherein at least a second portion of the plurality of contact pads forming a second ring of contact pads is arranged
between the second ring of contact leads and the third portion of the plurality of contact leads on the surface of the IC
package.

US Pat. No. 9,348,557

FUSED FLOATING POINT DATAPATH WITH CORRECT ROUNDING

ALTERA CORPORATION, San ...

1. Floating point datapath circuitry, said datapath circuitry comprising:
solely a single adder stage for computing a rounded absolute value of a mantissa of a floating point number based on at least
two bits of an unrounded mantissa of the floating point number.

US Pat. No. 9,319,186

RECEIVER EYE-MONITOR CIRCUIT AND METHOD

Altera Corporation, San ...

1. An integrated circuit with on-die instrumentation for obtaining bit error data for an eye-opening diagram, the integrated
circuit comprising:
a voltage multiplexer for selecting a reference voltage from a high reference voltage and a low reference voltage;
a clock multiplexer for selecting a clock signal from an even clock signal and an odd clock signal;
a first sense amplifier circuit for slicing an input data signal using a first slicing voltage at times indicated by said
clock signal to generate a speculative-high error signal, wherein said first slicing voltage comprises said reference voltage
increased by a speculative voltage; and

a second sense amplifier circuit that slices the input data signal using a second slicing voltage at times indicated by said
clock signal to generate a speculative-low error signal, wherein said second slicing voltage comprises said reference voltage
reduced by the speculative voltage.

US Pat. No. 9,473,145

PROGRAMMABLE HIGH-SPEED I/O INTERFACE

Altera Corporation, San ...

1. An integrated circuit comprising:
a differential input buffer having a first input coupled to a first pad and a second input coupled to a second pad;
a single-ended input buffer having an input coupled to the first pad; anda serial-to-parallel converter having:
a data input selectably coupled to an output of the single-ended input buffer or an output of the differential input buffer;
and

a clock input selectably coupled to a low-speed clock signal or a high-speed clock signal.

US Pat. No. 9,368,485

ELECTROSTATIC DISCHARGE CIRCUITRY WITH SEPARATE POWER RAILS

Altera Corporation, San ...

1. An integrated circuit, comprising:
an input-output circuit having an input node that is coupled to an input-output pad via a resistor;
first and second power clamp circuits;
first and second power rails and a ground power rail, wherein the first power clamp circuit is coupled between the first power
rail and the ground power rail, and wherein the second power clamp circuit is coupled between the second power rail and the
ground power rail;

a first electrostatic discharge (ESD) diode connected between the input-output pad and the first power rail;
a second electrostatic discharge (ESD) diode connected between the input-output pad and the ground power rail;
a third electrostatic discharge (ESD) diode connected between the input node and the second power rail; and
a fourth electrostatic discharge (ESD) diode connected between the input node and the ground power rail.

US Pat. No. 9,276,572

CONFIGURATION CONTEXT SWITCHER WITH A LATCH

Altera Corporation, San ...

1. An integrated circuit (“IC”) comprising:
a configurable circuit for configurably performing one of a plurality of operations based on configuration data;
a plurality of storage circuits for storing a plurality of configuration data sets for the configurable circuit; and
an interconnect circuit for switchably connecting the configurable circuit to different subsets of the plurality of storage
circuits to receive different subsets of the plurality of configuration data sets, said interconnect circuit comprising a
set of latches for temporarily storing configuration data sets.

US Pat. No. 9,246,715

PRE-EMPHASIS CIRCUITRY INCLUDING A PRE-EMPHASIS VOLTAGE VARIATION COMPENSATION ENGINE

Altera Corporation, San ...

1. A pre-emphasis circuitry comprising:
a pre-emphasis voltage variation compensation (PVVC) engine including (a) a transition detection circuit, (b) a digital finite
impulse response (FIR) filter coupled to the transition detection circuit, and (c) an FIR delay circuit coupled to the digital
FIR filter, wherein the FIR delay circuit introduces latency to match delay produced by the transition detection circuit;
and

a compensation driver coupled to the PVVC engine.

US Pat. No. 9,432,023

ROUTING AND PROGRAMMING FOR RESISTIVE SWITCH ARRAYS

Altera Corporation, San ...

1. A method of programming a column of resistive switches in a power constraint sharing region of a resistive switch array,
the method comprising:
during a first programming cycle, programming one or more resistive switches to be on-programmed if a power cost of on-programming
the one or more resistive switches does not exceed a power constraint for on-programming switches during a programming cycle;
and

if, after the first programming cycle, any resistive switches are remaining to be on-programmed (“remaining switches”), programming
the remaining switches during one or more subsequent programming cycles.

US Pat. No. 9,385,718

INPUT-OUTPUT BUFFER CIRCUIT WITH A GATE BIAS GENERATOR

Altera Corporation, San ...

12. A method of operating an input-output buffer circuit that includes first, second, third, and fourth transistors coupled
in series, comprising:
receiving a first input signal on a gate terminal of the first transistor;
in response to detecting a transition in the first input signal, receiving a first pulsed control signal on a gate terminal
of the second transistor;

receiving a second input signal that is different than the first input signal at a gate terminal of the third transistor;
and

in response to detecting a transition in the second input signal, receiving a second pulsed control signal on a gate terminal
of the fourth transistor, wherein the first pulsed control signal includes a voltage peak that temporarily exceeds a given
voltage level, wherein the second pulsed control signal includes a voltage dip that temporarily dips below the given voltage
level, and wherein the first and second pulsed control signals otherwise remain at the given voltage level.

US Pat. No. 9,164,952

ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS

Altera Corporation, San ...

1. An adaptive computing engine comprising:
a first configurable computational unit including a first plurality of heterogeneous computational elements, the first plurality
of heterogeneous computational elements including an adder, a register, and a function generator, the first plurality of heterogeneous
computational elements coupled to each other via a first interconnection network to configure interconnections between the
computational elements in response to configuration information to perform a first function;

a second configurable computational unit for performing digital signal processing functions, the second computational unit
including a second plurality of heterogeneous computational elements, the second plurality of heterogeneous computational
elements including at least one multiplier computational element and at least one adder computational element, the second
plurality of heterogeneous computational elements coupled to each other via a second interconnection network to configure
the interconnections between the second plurality of heterogeneous computational elements in response to configuration information
to perform a digital signal processing function; and

a third interconnection network coupled between the first and second configurable computational units.

US Pat. No. 9,166,591

HIGH SPEED IO BUFFER

Altera Corporation, San ...

1. An input buffer, comprising:
a first PMOS transistor coupled to a pre-driver voltage source and an input terminal;
a first NMOS transistor coupled to the input terminal and a ground terminal;
a second NMOS transistor, wherein the source of the second NMOS transistor is coupled to the gates of the first NMOS transistor
and the first PMOS transistor, wherein the drain of the second NMOS transistor is coupled to a pad terminal, and wherein the
gate of the second NMOS transistor is coupled to a pre-driver voltage source; and

a second PMOS transistor, wherein a gate of the second PMOS transistor is coupled to the pre-driver voltage source, a drain
of the second PMOS transistor is coupled to the ground terminal and a source of the second PMOS transistor is coupled to the
source of the second NMOS transistor.

US Pat. No. 9,166,596

MEMORY INTERFACE CIRCUITRY WITH IMPROVED TIMING MARGINS

Altera Corporation, San ...

1. Circuitry, comprising:
latch circuitry that receives a data strobe signal and a data strobe enable signal and latches the data strobe enable signal
based on the data strobe signal;

logic circuitry that receives the data strobe signal and the latched data strobe enable signal and produces a corresponding
gated data strobe signal based on the latched data strobe enable signal; and

control circuitry that generates a control signal by monitoring the gated data strobe signal, wherein the logic circuitry
receives the control signal and produces the gated data strobe signal based at least partly on the control signal.

US Pat. No. 9,064,068

DEBUGGABLE OPAQUE IP

Altera Corporation, San ...

1. A method comprising:
receiving, at a processor, instructions for implementing, on a hardware device, an intellectual property (IP) block, the IP
block including source code and a plurality of internal circuit nodes, the IP block being encrypted or otherwise opaque such
that at least a portion of the plurality of internal nodes are not normally visible, the source code including embedded attributes
of at least one internal circuit node of the portion of internal circuit nodes, wherein the attributes enable providing a
visualization of the at least one internal circuit node to a user performing simulation or debugging of the hardware device;
and

implementing, by using a processor, the IP block on the hardware device, wherein one or both of the instructions and the attributes
are encrypted.

US Pat. No. 9,496,268

INTEGRATED CIRCUITS WITH ASYMMETRIC AND STACKED TRANSISTORS

Altera Corporation, San ...

1. An integrated circuit, comprising:
an array of memory cells loaded with respective data bits, each memory cell having an output at which a static output signal
is produced based on the data bit loaded into that memory cell; and

programmable circuitry including a plurality of programmable transistors, each programmable transistor having a gate that
is electrically connected to a respective one of the outputs to receive a respective one of the static output signals, wherein
the memory cells each include a first asymmetric transistor that exhibits a strong mode of operation and a weak mode of operation
and a second asymmetric transistor with first and second source-drains, wherein the first source-drain of the second asymmetric
transistor is directly connected to the output of that memory cell, and wherein the second asymmetric transistor has an energy-barrier-inducing
implant at its second source-drain.

US Pat. No. 9,076,230

CIRCUITRY AND TECHNIQUES FOR IMAGE PROCESSING

Altera Corporation, San ...

1. A method of interpolating an image field with image processing circuitry, the method comprising:
with the image processing circuitry, identifying a pixel to be interpolated from a first row of the image field;
with the image processing circuitry, determining a plurality of edge direction vectors from the identified pixel and a plurality
of neighboring pixels in a second row of the image field;

with the image processing circuitry, combining the plurality of edge direction vectors to produce an interpolated pixel; and
assigning a score to each pixel of the plurality of neighboring pixels in the second row based on an angle of a corresponding
edge direction vector of that pixel with respect to a horizontal axis of the image field.

US Pat. No. 9,436,565

NON-INTRUSIVE MONITORING AND CONTROL OF INTEGRATED CIRCUITS

Altera Corporation, San ...

10. A non-transitory machine readable medium storing a program for monitoring operations of an integrated circuit (IC), the
IC comprising a set of configurable circuits for configurably performing a set of operations based on configuration data,
the program comprising sets of instructions for:
loading a first set of configuration data into the IC to configure a plurality of configurable circuits in the set of configurable
circuits to perform operations of a user design;

receiving a definition of (i) an event based on values of a set of signals in the user design and (ii) a set of corresponding
actions to take when the event occurs;

generating an incremental second set of configuration data based on the definition of the event and the set of corresponding
actions; and

loading, while the IC is performing the operations of the user design, the incremental second set of configuration data into
the IC to monitor for the event and to take the set of actions when the event occurs.

US Pat. No. 9,231,631

CIRCUITS AND METHODS FOR ADJUSTING THE VOLTAGE SWING OF A SIGNAL

Altera Corporation, San ...

1. A driver circuit comprising:
a first subset of unit slice circuits that generate an output data signal based on an input data signal; and
a second subset of unit slice circuits that generate constant current affecting a voltage swing of the output data signal
based on a fixed voltage, wherein the driver circuit reduces the voltage swing of the output data signal without changing
a termination resistance of the driver circuit in response to decreasing a number of the unit slice circuits in the first
subset that generate the output data signal based on the input data signal and in response to increasing a number of the unit
slice circuits in the second subset.

US Pat. No. 9,189,200

MULTIPLE-PRECISION PROCESSING BLOCK IN A PROGRAMMABLE INTEGRATED CIRCUIT DEVICE

Altera Corporation, San ...

1. A specialized processing block for performing floating-point arithmetic operations at selectable different precisions in
a programmable integrated circuit device, said specialized processing block comprising:
a plurality of different respective types of floating-point arithmetic operator circuit structures, each respective type of
floating-point arithmetic operator circuit structure performing a different type of operation than each other type of floating-point
arithmetic operator circuit structure; and

for each respective type of floating-point arithmetic operator circuit structure, respective control circuitry within said
floating-point arithmetic circuit structure for partitioning said respective type of floating-point arithmetic operator circuit
structure to select between a first precision for which said respective type of floating-point arithmetic operator structure
is not partitioned, and at least a second precision, less than said first precision, for which said respective type of floating-point
arithmetic operator structure is partitioned into at least two smaller ones of said respective type of floating-point arithmetic
operator circuit structure.

US Pat. No. 9,177,087

METHODS AND APPARATUS FOR GENERATING SHORT LENGTH PATTERNS THAT INDUCE INTER-SYMBOL INTERFERENCE

Altera Corporation, San ...

1. A method of measuring a performance of a communication link that comprises a transmitter circuit, a receiver circuit, and
a communication channel therebetween, the method comprising:
generating, by a pattern generator circuit, an inter-symbol interference inducing short pattern comprising:
a binary clock sequence comprising a plurality of bits of alternating values;
a first inter-symbol interference inducing binary sequence to follow the binary clock sequence in order within the inter-symbol
interference inducing short pattern, wherein the first inter-symbol interference inducing binary sequence comprises repeating
a first series of consecutive identical bits of a first value followed in order by one bit of a second value a plurality of
times, wherein the first and second values are inverses of each other; and

a second inter-symbol interference inducing binary sequence that follows the complement of the binary clock sequence in order
within the inter-symbol interference inducing short pattern, wherein the second inter-symbol interference inducing binary
sequence comprises repeating a second series of consecutive identical bits of the second value followed in order by one bit
of the first value a plurality of times;

transmitting, by the transmitter circuit, the inter-symbol interference inducing short pattern to the communication channel;
receiving, by the receiver circuit, the inter-symbol interference inducing short pattern from the communication channel; and
measuring the performance of the communication link to obtain measured performance data.

US Pat. No. 9,170,775

FLEXIBLE ACCUMULATOR IN DIGITAL SIGNAL PROCESSING CIRCUITRY

Altera Corporation, San ...

1. A multiplier-accumulator block operative to zero or initialize an accumulator output value comprising:
a first multiplier having a first input operative to receive a first input signal, a second input operative to receive a second
input signal, and a first output, wherein the first input signal and the second input signal are concatenated in a predetermined
order and sent to the first output;

a second multiplier having a first input operative to receive a third input signal, a second input operative to receive a
fourth input signal, and a second output, wherein the first multiplier is separate and distinct from the second multiplier,
and wherein the first multiplier operates in parallel with the second multiplier;

an accumulator having a first input operative to receive the first output, a second input operative to receive the second
output, a third input operative to receive a feedback output, and an accumulator output, wherein the feedback output is set
to zero; and

a register block having an input operative to receive the accumulator output and a register block output, wherein the first
input signal and the second input signal are both set to zero, and wherein the feedback output is concatenated to the first
output.

US Pat. No. 9,172,384

LOW-NOISE VOLTAGE REGULATOR FOR VOLTAGE-CONTROLLED OSCILLATOR

Altera Corporation, San ...

1. An apparatus for regulating a voltage-controlled oscillator, the apparatus comprising:
a digital-to-analog converter that has an input that receives a digital input signal and an output that outputs an analog
control signal;

a transistor having an input that receives the analog control signal so as to control an output voltage of the voltage-controlled
oscillator; and

control circuitry that receives the output voltage and generates the digital input signal, wherein the control circuitry comprises
a plurality of comparators and calibration control logic.

US Pat. No. 9,171,185

PROGRAMMABLE LOGIC DEVICE WITH IMPROVED SECURITY

Altera Corporation, San ...

1. A logic device comprising:
at least one logic block driven by a first clock signal; and
a decryption core configured to process encrypted input data, the decryption core driven by a second clock signal, the second
clock signal being one or both of decoupled from the first clock signal and asynchronous to the first clock signal; wherein:

the decryption core generates plaintext output data to configure the at least one logic block.

US Pat. No. 9,158,686

PROCESSING SYSTEM AND METHOD INCLUDING DATA COMPRESSION API

Altera Corporation, San ...

1. A computer system, comprising:
a data processor and memory accessible by the data processor, the memory storing computer programs executable by the data
processor, including at least one application program and a set of functions that use parameters and implement operations
of an application program interface (API) for processes that move a data set between elements of the memory, and perform compression
and decompression of data in the data set, the at least one application program including:

a process to move a data set between a first element of the memory to a second element of the memory, the application program
being responsive on execution by the data processor to call the API, the call including parameters and identifying operations
of the API, the parameters including a location of the data set to be moved, an identifier of a data type for the data set
to be moved, and an identifier of a characteristic of a data compression procedure to be applied, to perform data compression
according to the identified characteristic of the data compression procedure on the data set in the first element of the memory
to form a compressed data set, and to store the compressed data set in the second element of the memory.

US Pat. No. 9,147,023

METHOD AND APPARATUS FOR PERFORMING FAST INCREMENTAL RESYNTHESIS

Altera Corporation, San ...

1. A method for designing a system on a target device, comprising:
generating a first netlist with a first set of functionally invariant boundaries (FIBs) for a first version of the system
in a first compilation;

invalidating one or more of the FIBs from the first set after performing optimizations during synthesis resulting in a second
netlist with a second set of FIBs;

generating a third netlist with a third set of FIBs of a second version of the system having a changed portion in a second
compilation; and

replacing a region in the third netlist with an optimized synthesized region from the second netlist identified as being identical,
wherein at least one of the generating, invalidating, and replacing is performed by a processor.

US Pat. No. 9,104,473

CONVERSION AND COMPRESSION OF FLOATING-POINT AND INTEGER DATA

Altera Corporation, San ...

1. A method for transfer of floating-point data across a data transfer interface connecting components of a computer system,
comprising:
scaling a plurality of floating-point samples by a scale factor that is inversely proportional to a maximum floating-point
value for a set of input floating-point samples, wherein each floating-point sample comprises an original number of bits in
accordance with a floating-point format used in the computer system, the floating-point format defining a sign bit to represent
a sign, a plurality of exponent bits to represent an exponent and a plurality of mantissa bits to represent a mantissa;

converting the plurality of scaled samples to a plurality of integer samples having an integer format used in the computer
system, the integer format comprising an integer sign bit and a plurality of integer mantissa bits;

compressing the plurality of integer samples to form a plurality of compressed integer samples in accordance with one or more
parameters; and

encoding the plurality of compressed integer samples to form compressed data for a compressed data packet to provide to the
data transfer interface.

US Pat. No. 9,443,054

METHOD AND APPARATUS FOR UTILIZING CONSTRAINTS FOR THE ROUTING OF A DESIGN ON A PROGRAMMABLE LOGIC DEVICE

Altera Corporation, San ...

1. A method for designing a system on a target device, comprising:
selecting routing resources for a user specified segment on a target device in response to user specified routing constraints
specifying one of a specific wire and a category of wires on the target device; and

selecting routing resources for a non-user specified segment on the target device without utilizing the user specified routing
constraints, wherein at least one of the selecting is performed by a processor.

US Pat. No. 9,369,363

APPARATUS AND METHODS FOR DETERMINING LATENCY OF A NETWORK PORT

Altera Corporation, San ...

1. A method for determining a latency of a network port, the method comprising:
generating a sampling clock at a sampling frequency;
sampling a read pointer for a first-in-first-out (FIFO) buffer using an edge of the sampling clock;
sampling a write pointer for the FIFO buffer using the edge of the sampling clock; and
determining an average difference between the read and write pointers.

US Pat. No. 9,348,795

PROGRAMMABLE DEVICE USING FIXED AND CONFIGURABLE LOGIC TO IMPLEMENT FLOATING-POINT ROUNDING

ALTERA CORPORATION, San ...

1. A configurable specialized processing block on an integrated circuit device, said configurable specialized processing block
comprising:
a first floating-point arithmetic operator stage;
a second floating-point arithmetic operator stage;
configurable interconnect within said configurable specialized processing block for routing signals into and out of each of
said first and second floating-point arithmetic operator stages; and

fixed rounding circuitry for performing a partial rounding operation on output of said second floating-point arithmetic operator
stage, said fixed rounding circuitry comprising a rounding condition detector and an overflow detector, said overflow detector
comprising:

a first AND-gate combining output mantissa bits of said second floating-point arithmetic operator stage, and
a second AND-gate combining output of said first AND-gate and output of said rounding condition detector.

US Pat. No. 9,331,848

DIFFERENTIAL POWER ANALYSIS RESISTANT ENCRYPTION AND DECRYPTION FUNCTIONS

Altera Corporation, San ...

20. A method of using a processor to configure a programmable integrated circuit device as an encryption system, said method
comprising:
configuring, using the processor, logic of said programmable integrated circuit device as whitening circuitry for obfuscating
a first and second block of plaintext to generate a respective first and second block of obfuscated plaintext;

configuring logic of said programmable integrated circuit device as first combining circuitry for processing the first block
of obfuscated plaintext to generate a first block of further obfuscated plaintext;

configuring logic of said programmable integrated circuit device as a first encryption block to encrypt the first block of
further obfuscated plaintext to output a first block of ciphertext after the first combining circuitry generates the first
block of further obfuscated plaintext;

configuring logic of said programmable integrated circuit device as second combining circuitry for combining the first block
of ciphertext with a first block of mask values to output a first block of obfuscated ciphertext;

configuring logic of said programmable integrated circuit device as third combining circuitry for combining the first block
of ciphertext with the second block of obfuscated plaintext to output a second block of further obfuscated plaintext;

configuring logic of said programmable integrated circuit device as a second encryption block for encrypting the second block
of further obfuscated plaintext to output a second block of ciphertext; and

configuring logic of said programmable integrated circuit device as fourth combining circuitry for combining one of the first
block of further obfuscated plaintext or the first block of obfuscated plaintext to output a second block of obfuscated ciphertext.

US Pat. No. 9,153,572

INTEGRATED CIRCUIT SYSTEM WITH DYNAMIC DECOUPLING AND METHOD OF MANUFACTURE THEREOF

Altera Corporation, San ...

1. A method of manufacture of an integrated circuit system comprising:
providing a supply grid connected to an active component of an integrated circuit die;
connecting a high voltage capacitor to the supply grid;
connecting a low voltage decoupling capacitor to the supply grid;
gating the low voltage decoupling capacitor with a pass gate; and
configuring a pass gate control for controlling the pass gate to cause the high voltage capacitor and the low voltage decoupling
capacitor to stabilize voltage of the supply grid during activity of the active component.

US Pat. No. 9,141,747

SYSTEM LEVEL TOOLS TO SUPPORT FPGA PARTIAL RECONFIGURATION

Altera Corporation, San ...

1. An apparatus for designing a reconfigurable programmable logic device (PLD), the apparatus comprising:
a processor configured to run a system level design tool, the processor accepting, as inputs from a user, an identification
of at least two personas to be used within a partitioned reconfigurable region of the PLD, wherein:

the design tool (i) captures a list of the at least two personas, the list defining a superset of boundary interfaces that
includes subsets of interfaces, each of the subsets of interfaces being associated with a respective one of the at least two
personas; (ii) ensures that each persona in the list has a compatible subset of interfaces; and (iii) defines, as high-level
interface descriptions, one or more boundaries of a partial reconfig (PR) domain inside the partitioned reconfigurable region
of the PLD such that the PR domain is selectably reconfigurable as any of the at least two personas while at least one other
portion of the PLD outside the partitioned reconfigurable region is still operating.

US Pat. No. 9,099,999

ADJUSTABLE DRIVE STRENGTH INPUT-OUTPUT BUFFER CIRCUITRY

Altera Corporation, San ...

1. An integrated circuit within a multi-die package comprising:
a microbump pad that is coupled to another integrated circuit in the multi-die package;
a flip-chip bump pad;
a microbump output buffer circuit that is coupled to the microbump pad, wherein the microbump output buffer circuit has an
adjustable drive strength and wherein the microbump output buffer circuit drives output signals to the another integrated
circuit;

a flip-chip bump output buffer circuit that is coupled to the flip-chip bump pad; and
a control circuit that generates control signals that control the adjustable drive strength of the microbump output buffer
circuit.

US Pat. No. 9,081,062

MEMORY ERROR DETECTION AND CORRECTION CIRCUITRY

Altera Corporation, San ...

1. A method of detecting soft errors in memory elements on an integrated circuit, comprising:
obtaining data bits from the memory elements;
obtaining predetermined data bits;
with comparator circuitry on the integrated circuit, comparing each of the data bits with a corresponding one of the predetermined
data bits to identify correctable erroneous data bits; and

correcting a subset of the identified correctable erroneous data bits; and
loading mask bits into a mask register, wherein comparing each of the data bits comprises latching an error signal with the
comparator circuitry in response to detection of a correctable soft error in the data bits when the mask bits enable latching
and not latching the error signal with the comparator circuitry in response to detection of the correctable soft error when
the mask bits disable latching.

US Pat. No. 9,063,722

METHODS AND APPARATUS FOR INDEPENDENT PROCESSOR NODE OPERATIONS IN A SIMD ARRAY PROCESSOR

Altera Corporation, San ...

1. A method for executing very long instruction words (VLIWs) separately on individual processing elements (PEs), the method
comprising:
receiving a thread start (Tstart) instruction from a first instruction path in each PE of a plurality of PEs;
switching in each PE from the first instruction path to a second instruction path in response to the Tstart instruction, wherein
the first instruction path is used to receive single instruction multiple data (SIMD) instructions distributed to each PE
and the second instruction path is used to receive instructions from a local PE instruction memory (PE Imem);

fetching a PE execute VLIW (PEXV) instruction from the local PE Imem in each PE;
selecting a VLIW having a plurality of slot instruction from a VLIW memory located in each PE in response to the PEXV instruction,
to decode and execute the plurality of slot instructions in parallel in each PE;

executing a Tstop instruction fetched from the local PE Imem that is specified to execute a PE instruction in the shadow of
the Tstop instruction; and

executing the PE instruction in the shadow of the Tstop instruction.

US Pat. No. 9,812,216

CIRCUITS AND METHODS FOR GENERATING A CLOCK ENABLE SIGNAL USING A SHIFT REGISTER

Altera Corporation, San ...

1. A method comprising:
generating multiple pulses in a clock enable signal using a shift register circuit in response to a single transition in a
start signal and in response to control signals; and

generating an output signal for testing an electronic circuit using a first multiplexer circuit by selecting from an input
signal and a first clock signal, wherein selection of the first multiplexer circuit is controlled by the multiple pulses in
the clock enable signal.

US Pat. No. 9,450,402

ELECTROSTATIC DISCHARGE PROTECTION CIRCUITRY WITH REDUCED CAPACITANCE

Altera Corporation, San ...

16. A method of forming an integrated circuit, comprising:
forming processing circuitry that includes transistors formed in a first well having a first dopant concentration of a first
type of dopants; and

forming electrostatic discharge protection circuitry by:
forming isolation structures in a substrate;
forming a second well between the isolation structures in the substrate, wherein the second well exhibits a second dopant
concentration of a second type of dopants that is different from the first type of dopants;

forming a third well in the substrate, wherein the third well exhibits a third concentration of the first type of dopants;
reducing the second dopant concentration of the second well by implanting dopants of the first type in the second well;
reducing the third concentration of the third well by implanting dopants of the second type in the third well; and
forming contact regions within the second well.

US Pat. No. 9,432,051

METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN MEMORY CELLS

Altera Corporation, San ...

13. A method for processing configuration data that implements a circuit design on an integrated circuit, comprising:
receiving the configuration data;
identifying a set of don't care bits in the configuration data, wherein a polarity change in any one of the don't care bits
preserves the functionality of the circuit design;

computing a parity bit for a subset of the configuration data;
generating updated configuration data by replacing a bit in the set of don't care bits with the parity bit; and
programming configuration memory cells on the integrated circuit with the updated configuration data.

US Pat. No. 9,390,057

COMMUNICATON ACROSS SHARED MUTUALLY EXCLUSIVE DIRECTION PATHS BETWEEN CLUSTERED PROCESSING ELEMENTS

Altera Corporation, San ...

1. A method of operating an array processor, the method comprising:
organizing an N-row by M-column torus array processor into M clusters of N processing elements (PEs), where M and N are positive
integers both greater than 1, said organizing including, for each value of y, where y ? {0,1} for M=2 and y ? {0, 1, . . .
, M?1} for M>2, establishing a cluster y of N PEs with a unique PE0, y, the remaining PEs of cluster y selected by PEa,(y+M-a)Mod M for each a, where a=1 for N=2, a ? {1, 2} for N=3, and a ? {1, 2, . . . , N?1} for N>3;

receiving a communication instruction in each PE, the M clusters interconnected by cluster switches, wherein the communication
instruction provides software accessible control of the cluster switches, wherein each PE in a first cluster of N PEs controls
an associated switching element (SE) of an associated cluster switch coupled to the first cluster of N PEs to select a signal
path in response to the received communication instruction, wherein the selected signal path begins from each PE that controls
the associated SE, continues through the associated cluster switch, and then continues through an adjacent cluster switch
to a torus nearest neighbor adjacent PE in an adjacent cluster of N PEs, and wherein N signal paths are selected by the N
PEs in the first cluster of N PEs; and

transmitting N source values, a different source value transmitted from each PE in the first duster of N PEs, in parallel
across the selected N signal paths to N torus nearest neighbor adjacent PEs in response to the communication instruction,
wherein the associated cluster switch and the adjacent cluster switch each provide N shared mutually exclusive direction paths
between the first cluster of N PEs and the adjacent cluster of N PEs.

US Pat. No. 9,331,370

MULTILAYER INTEGRATED CIRCUIT PACKAGES WITH LOCALIZED AIR STRUCTURES

Altera Corporation, San ...

1. An integrated circuit package substrate, comprising:
a top surface of the integrated circuit package substrate on which an integrated circuit die is mounted;
a bottom surface of the integrated circuit package substrate;
a dielectric layer formed between the top and bottom surfaces of the integrated circuit package substrate;
signal routing conductors formed on the dielectric layer; and
a localized air region that is formed on the dielectric layer over the signal routing conductors and that is formed between
the top and bottom surfaces of the integrated circuit package substrate.

US Pat. No. 9,323,285

METASTABILITY PREDICTION AND AVOIDANCE IN MEMORY ARBITRATION CIRCUITRY

Altera Corporation, San ...

1. Circuitry comprising:
a first input that receives a first periodic signal having a first period;
a second input that receives a second periodic signal having a second period;
hazard prediction circuitry that predicts a future hazard condition between the first and second periodic signals, wherein
the hazard prediction circuitry predicts the future hazard condition at a first instant of time, and the future hazard condition
is predicted to occur at a second instant of time that is after the first instant of time; and

hazard prevention circuitry that selectively delays at least one of the first and second periodic signals by a first predetermined
duration during at least one clock cycle of the respective periodic signal prior to the second instant of time.

US Pat. No. 9,311,106

MULTIPLE RECONFIGURATION PROFILES FOR DYNAMICALLY RECONFIGURABLE INTELLECTUAL PROPERTY CORES

Altera Corporation, San ...

1. A non-transitory computer readable medium having instructions stored thereon, the instructions executable by a processor
to:
receive a first configuration profile, the first configuration profile providing a first configuration of a set of configuration
elements of an Intellectual Property (IP) core to implement a first functionality of the IP core;

receive a second configuration profile, the second configuration profile providing a second configuration of the set of configuration
elements of the IP core to implement a second functionality of the IP core;

determine a subset of the set of configuration elements that are in opposite states between the first configuration and the
second configuration of the IP core;

generate a first configuration data associated with the first configuration profile, the first configuration data indicating
settings for the subset of the set of configuration elements to implement the first functionality; and

generate a second configuration data associated with the second configuration profile, the second configuration data indicating
settings for the subset of the set of configuration elements to implement the second functionality.

US Pat. No. 9,275,694

FPGA EQUIVALENT INPUT AND OUTPUT GRID MUXING ON STRUCTURAL ASIC MEMORY

Altera Corporation, San ...

1. A method for operating a device having a configurable bus width, the method comprising:
receiving data comprising a plurality of bits;
coupling a first set of data lines corresponding to a first portion of the plurality of bits to a first one bit wide output
of the device through a first set of vias associated with the first set of data lines, wherein a first data ling of the first
set of data lines is coupled to the first one bit wide output through a first via of the first set of vias and a second data
line of the first set of data lines is coupled to the first one bit wide output through a second via of the first set of vias;
and

selectively controlling which bit of the first portion is coupled to the first set of data lines based on a placement of the
first via or the second via.

US Pat. No. 9,166,590

INTEGRATED CIRCUITS WITH IMPROVED MEMORY INTERFACE CALIBRATION CAPABILITIES

Altera Corporation, San ...

1. An integrated circuit, comprising:
memory interface circuitry that interfaces with external memory;
storage circuitry; and
calibration circuitry having a first configuration in which the calibration circuitry includes calibration data generation
circuitry that generates and stores calibration data at the storage circuitry and a second configuration in which the calibration
circuitry does not include the calibration data generation circuitry and in which the calibration circuitry loads the calibration
data from the storage circuitry.

US Pat. No. 9,154,151

ANALOG-TO-DIGITAL CONVERTER CIRCUITS AND METHODS

Altera Corporation, San ...

1. An analog-to-digital converter circuit comprising:
a digital-to-analog converter circuit to generate a first analog signal based on digital signals and a reference voltage;
a voltage stabilization circuit to reduce variations in the reference voltage in response to at least one of the digital signals;
and

a comparator circuit to generate a comparison output based on the first analog signal, wherein the digital signals are generated
based on the comparison output.

US Pat. No. 9,069,624

SYSTEMS AND METHODS FOR DSP BLOCK ENHANCEMENT

Altera Corporation, San ...

1. A system comprising:
a plurality of multiplier circuitries; and
control circuitry configured to multiply a number AB and a number CD, wherein:
the number AB comprises a component A and a component B, and the component A comprises a subcomponent AH and a subcomponent AL, and

the number CD comprises a component C and a component D, and the component C comprises a subcomponent CH and a subcomponent CL, and

the control circuitry is configured to:
compute a partial product AD based on multiplying the component D and the subcomponent AL using a first multiplier circuitry of the plurality of multiplier circuitries and based on multiplying the component D and
the subcomponent AH using a first multiplier module of a second multiplier circuitry of the plurality of multiplier circuitries; and

compute a partial product CB based on multiplying the component B and the subcomponent CL using a third multiplier circuitry of the plurality of multiplier circuitries and based on multiplying the component B and
the subcomponent CH using a second multiplier module of the second multiplier circuitry of the plurality of multiplier circuitries.

US Pat. No. 9,065,399

PROGRAMMABLE HIGH-SPEED VOLTAGE-MODE DIFFERENTIAL DRIVER

Altera Corporation, San ...

1. A differential driver for driving a differential signal, the differential driver comprising:
a first driver arm comprising a first variable-impedance driver for driving a first single-ended output signal of the differential
signal; and

a second driver arm comprising a second variable-impedance driver for driving a second single-ended output signal of the differential
signal;

a first re-timing block providing a first plurality of re-timed signals to the first variable-impedance driver; and
a second re-timing block providing a second plurality of re-timed signals to the second variable-impedance driver,
wherein each said variable-impedance driver comprises multiple driver slices, each driver slice including a pre-driver circuit
and a driver circuit.

US Pat. No. 9,485,129

MULTI-STANDARD PEAK CANCELING CIRCUITRY

Altera Corporation, San ...

6. A method of operating peak cancelation circuitry, comprising:
receiving a first carrier waveform at a first input;
receiving a second carrier waveform at a second input;
with a summing circuit, combining the first and second carrier waveforms into an aggregated waveform;
with a peak detector, performing peak detection on the aggregated waveform and outputting a result;
with a first canceling pulse generator circuit, receiving the first carrier waveform, a first canceling pulse, and a first
weighting factor that is computed from the result, and performing a first adjustable amount of peak canceling on the first
carrier waveform based on the first canceling pulse and the first weighting factor to generate a corresponding first output
waveform; and

with a second canceling pulse generator circuit, receiving the second carrier waveform, a second canceling pulse, and a second
weighting factor that is computed from the result, and performing a second adjustable amount of peak canceling on the second
carrier waveform based on the second canceling pulse and the second weighting factor to generate a corresponding second output
waveform.

US Pat. No. 9,471,737

SEMICONDUCTOR DEVICE WITH DUMMY CELLS OF DIFFERENT DATA TYPES

Altera Corporation, San ...

8. A method of designing a floorplan layout of a semiconductor device, comprising:
defining a dummy structure region on the floorplan layout of the semiconductor device;
adding a plurality of dummy cells to the dummy structure region, wherein each dummy cell in the plurality of dummy cells is
associated with a respective different data type;

identifying a subset of the plurality of dummy cells, wherein dummy cells in the subset of the plurality of dummy cells are
associated with a first data type;

determining whether a sub-region within the floorplan layout has a manufacturing design density that is within a predefined
manufacturing design density range; and

removing dummy cells of the plurality of dummy cells from the sub-region that are associated with the first data type in response
to determining that the manufacturing design density is greater than the predefined manufacturing design density range.

US Pat. No. 9,471,537

HYBRID PROGRAMMABLE MANY-CORE DEVICE WITH ON-CHIP INTERCONNECT

Altera Corporation, San ...

1. A hybrid programmable logic device, comprising:
programmable logic elements, at least some of which provide at least one hardware acceleration function;
processors interleaved with the programmable logic elements and physically sized such that one physical dimension of each
of the processors is equal to a multiple of a same physical dimension of the programmable logic elements; and

first intersecting horizontal and vertical connectors that provide data to and from the programmable logic elements, the processors
or any combination therein;

wherein the vertical pitch of the intersecting horizontal and vertical connectors is a multiple of a vertical pitch of at
least one of the programmable logic elements of the processors.

US Pat. No. 9,400,652

METHODS AND APPARATUS FOR ADDRESS TRANSLATION FUNCTIONS

Altera Corporation, San ...

1. A processor system vector address translation apparatus comprising:
an instruction register receiving, in a processor from a program memory coupled to the processor, a first vector instruction
that is identified to specify a vector register file indexing (RFI) operation, the first received vector RFI instruction encoded
to identify a first memory address and control information that includes a specification for a sequence of memory addresses;

a vector update unit enabled to generate on a vector update unit output a sequence of memory addresses following the first
memory address based on the specification for the sequence of memory addresses, wherein a plurality of vector RFI instructions
are subsequently received sequentially from the instruction register for which the processor vector update unit generates,
for each subsequently received vector RFI instruction, a subsequent memory address in the sequence of memory addresses;

a processor multiplexer enabled to select the first memory address for the first received vector RFI instruction from a first
input of the processor multiplexer coupled to the instruction register and enabled to select the sequence of memory addresses
for the plurality of subsequently received vector RFI instructions from a second input of the processor multiplexer coupled
to the vector update unit output, an output of the processor multiplexer producing a sequence of vector addresses beginning
with the first memory address; and

a data memory device coupled to the processor for read operations by a k-bit read address port coupled to the output of the
processor multiplexer, a load translation parameter port, and a read data port, the data memory device having an internal
translation parameter storage element previously loaded by the processor with a first translation parameter, the data memory
device comprising:

a memory array for storing data in the data memory device; and
an address translation unit receiving the sequence of vector addresses from the processor external to the data memory device,
translating the sequence of vector addresses beginning with the first memory address to form a sequence of translated vector
addresses in a translation pattern according to the first translation parameter stored in the data memory device, and accessing
a sequence of data values from the memory array according to the sequence of translated vector addresses for output on the
read data port for input to the processor, wherein for vector operations that are operable in conjunction with indirect very
long instruction word (iVLIW) operations, each received vector RFI instruction identities a VLIW having plurality of processor
instructions, each processor instruction having a specification of the translation pattern to be selected.

US Pat. No. 9,379,687

PIPELINED SYSTOLIC FINITE IMPULSE RESPONSE FILTER

ALTERA CORPORATION, San ...

1. A systolic FIR filter circuit comprising:
a plurality of multipliers, each respective one of said multipliers having a respective coefficient input, a respective sample
input, and a respective multiplier output;

a plurality of sample pre-adders, each respective one of said sample pre-adders connected to a sample input of a respective
one of said multipliers;

an output cascade adder chain comprising a respective output adder connected to a respective multiplier output of each respective
one of said multipliers, each respective output adder having a first input receiving said respective multiplier output, and,
except for a first output adder in said output cascade adder chain, having a second input receiving an output of a previous
one of said output adders, said output cascade adder chain further comprising a selectable number of output delays between
adjacent ones of said output adders; and

an input sample chain having a first leg and a second leg; wherein:
each respective one of said sample pre-adders receives a respective input from a respective sample point in said first leg
and a respective input from a respective sample point said second leg;

said input sample chain has, between adjacent sample points in at least one of said legs, a selectable number of sample delays
related to said selectable number of output delays; and

connections of inputs from said input sample chain to said sample pre-adders are adjusted to account for said selectable number.

US Pat. No. 9,344,113

LEMPEL ZIV COMPRESSION ARCHITECTURE

Altera Corporation, San ...

1. A data compression architecture, comprising:
means for receiving input data characters;
means for receiving a data flush enable input signal, wherein said data flush input signal is asserted in response to said
means for receiving input data characters beginning to receive said input data characters from a new source;

means for storing a plurality of previously received data characters, wherein the plurality of previously received data characters
are cleared within a clock cycle in response to the data flush enable input signal;

means for comparing each received input data character with said plurality of stored data characters;
means for detecting a match in response to determining that a sequence of two or more of the received input data characters
is equal to a sequence of the stored data characters;

means for determining that a match criterion is met; and
means for supplying a match output in response to said detecting a match and in response to said determining that a match
criterion is met.

US Pat. No. 9,246,497

INTEGRATED CIRCUIT (IC) CLOCKING TECHNIQUES

Altera Corporation, San ...

1. An integrated circuit (IC) comprising:
a divider circuit coupled to receive a preamble signal, wherein the divider circuit outputs a first clock signal based on
the preamble signal;

a recovery circuit coupled to the divider circuit, wherein the recovery circuit determines a phase of the first clock signal
and outputs a second clock signal based on the first clock signal;

a comparator circuit having a first input coupled to the divider circuit, wherein the comparator circuit outputs a phase difference
between the first clock signal and a delayed version of the second clock signal; and

a delay circuit having an input coupled to the recovery circuit and an output coupled to a second input of the comparator
circuit, and further coupled to receive the phase difference, wherein the delay circuit outputs the delayed version of the
second clock signal based on the phase difference and outputs a recovered clock signal based on the delayed version of the
second clock signal in response to a receipt of a lock signal.

US Pat. No. 9,244,867

MEMORY CONTROLLER INTERFACE WITH ADJUSTABLE PORT WIDTHS

Altera Corporation, San ...

1. An integrated circuit configured to access memory, comprising:
circuitry that generates memory access requests;
a programmable memory interface that receives the memory access requests from the circuitry through a memory interface port
having a port width and is configurable to vary the port width used in receiving the memory access requests from the circuitry;
and

a memory controller having a plurality of data ports each of which has an associated port width, wherein the memory controller
fulfills the memory access requests by accessing the memory, wherein the programmable memory interface uses a selected number
of the data ports in providing the memory access requests to the memory controller, wherein a sum of the port widths of the
selected number of data ports is at least equal to the port width of the memory interface port, wherein the programmable memory
interface is interposed between the memory controller and the circuitry that generates memory access requests.

US Pat. No. 9,196,575

INTEGRATED CIRCUIT PACKAGE WITH CAVITY IN SUBSTRATE

Altera Corporation, San ...

1. An integrated circuit package comprising:
a package substrate having a topmost surface and a cavity formed in the topmost surface, wherein the package substrate further
includes a plurality of thermally conductive vias;

a first die;
a second die, wherein the second die includes opposing top and bottom surfaces, wherein the first die is attached to the top
surface of the second die, and wherein the second die is formed above the topmost surface of the package substrate; and

a thermally conductive block in the cavity over the thermally conductive vias, wherein the thermally conductive block is coupled
to the bottom surface of the second die.

US Pat. No. 9,184,123

PACKAGE SUBSTRATE WITH CURRENT FLOW SHAPING FEATURES

Altera Corporation, San ...

1. A package substrate for use with a die, the package substrate comprising:
a plurality of layers, wherein:
each of the layers in the plurality of layers includes a pattern of electrically-conductive material, and
the plurality of layers includes:
a) a die-interface layer including one or more die contact pads configured to interface with solder bumps of the die,
b) a ball-grid-array-interface (BGA-interface) layer including one or more BGA contact pads configured to interface with solder
balls, and

c) one or more additional layers interposed between the die-interface layer and the BGA-interface layer; and
a plurality of power rails, each power rail:
conductively connecting one or more of the BGA contact pads with one or more of the die contact pads, and
including interlayer vias conductively connecting one or more areas of each of two or more of the layers, wherein:
at least one of the additional layers includes one or more electrically-nonconductive regions arranged to produce an electrical
current density that is more evenly distributed within a given power rail when i) the die is installed and ii) power is applied
to the die through the package substrate as compared with the electrical current density that is produced within the given
power rail when i) the one or more electrically-nonconductive regions is instead electrically-conductive, ii) the die is installed,
and iii) power is applied to the die through the package substrate.

US Pat. No. 9,172,537

ARRAY ENCRYPTION CORE

Altera Corporation, San ...

1. Circuitry for encrypting data using a cryptographic algorithm, the circuitry comprising:
a plurality of encryption cores, each encryption core having at least a respective data input for receiving respective data
blocks and a respective control input for receiving a respective load signal;

input arbitration logic circuitry to:
receive a plurality of timeslot availability signals from each encryption core, and
provide an enable load signal to the control input of an encryption core of the plurality of encryption cores based on the
plurality of timeslot availability signals, wherein the data blocks are loaded into the data input of the encryption core
of the plurality of encryption cores based on the enable load signal.

US Pat. No. 9,166,597

INTEGRATED CIRCUIT PROCESSING VIA OFFLOAD PROCESSOR

Altera Corporation, San ...

1. A method, comprising:
determining whether one or more basic blocks of a kernel implementable on programmable logic on an integrated circuit is to
be implemented on one or more offload processors separate from the programmable logic;

assigning offload logic corresponding to the one or more basic blocks to the one or more offload processors when the one or
more basic blocks is to be implemented on the one or more offload processors; and

assigning the one or more basic blocks on the programmable logic on the integrated circuit when the one or more basic blocks
is not to be implemented on the one or more offload processors.

US Pat. No. 9,135,087

WORKGROUP HANDLING IN PIPELINED CIRCUITS

Altera Corporation, San ...

1. A method for limiting a number of workgroups that may simultaneously access a kernel of an integrated circuit (IC), the
method comprising:
tracking a plurality of threads that currently access the kernel and workgroup information associated with the plurality of
threads;

determining a threshold number of workgroups that may access the kernel simultaneously, wherein the threshold is based on
an allotment of additional workgroups that are expected not to cause overuse, depletion or both of hardware resources of the
integrated circuit;

receiving a first thread of execution and workgroup information associated with the first thread;
determining, based on the workgroup information associated with the first thread and workgroup information associated with
the plurality of threads that currently access the kernel, if allowing the first thread access to the kernel will result in
an additional workgroup accessing the kernel;

allowing the first thread to access the kernel when it is determined the first thread would not result in an additional workgroup
accessing the kernel;

allowing the first thread to access the kernel when it is determined the first thread would not exceed the threshold; and
disallowing the first thread to access the kernel when doing so would exceed the threshold number of workgroups.

US Pat. No. 9,111,603

SYSTEMS AND METHODS FOR MEMORY CONTROLLER REFERENCE VOLTAGE CALIBRATION

Altera Corporation, San ...

1. An integrated circuit die that communicates with a memory that is external to the integrated circuit die, the integrated
circuit die comprising:
a port that receives a signal from the memory;
detection circuitry coupled to the port, wherein the detection circuitry produces a target reference voltage signal based
at least partly on the signal received at the port from the memory;

reference circuitry that produces a reference voltage signal based on the target reference voltage signal; and
a comparator that receives the signal from the memory through the port and the reference voltage signal and produces a corresponding
output signal by comparing the signal from the memory to the reference voltage signal.

US Pat. No. 9,628,095

PARAMETERIZABLE METHOD FOR SIMULATING PLL BEHAVIOR

Altera Corporation, San ...

1. A non-transitory computer-readable storage medium for simulating circuitry using a simulation time scale, wherein the simulated
circuitry operates based on at least one clock signal having a clock frequency, the non-transitory computer-readable storage
medium comprising instructions for:
calculating an inverse of the clock frequency to determine an exact clock period;
rounding down the exact clock period using the simulation time scale to determine a first clock period;
rounding up the exact clock period using the simulation time scale to determine a second clock period; and
simulating the circuitry using the first and second clock periods by toggling between simulating the circuitry using the first
clock period and simulating the circuitry using the second clock period.

US Pat. No. 9,570,134

REDUCING TRANSACTIONAL LATENCY IN ADDRESS DECODING

Altera Corporation, San ...

14. A processing system, comprising:
an encoded address partitioning component that partitions a set of encoded addresses into a first and a second subset of encoded
addresses;

a controller component that sends a first encoded address of the range of encoded addresses to access a first target component
through an interconnection component; and

a decode component that receives the first encoded address, wherein the decode component:
asserts a halt signal to the controller component in response to identifying that the first encoded address belongs to the
second subset of encoded addresses, decodes the first encoded address, de-asserts a halt signal to the controller component
in response to decoding the first encoded address, and receives a second encoded address from the controller component in
response to de-asserting the halt signal.

US Pat. No. 9,490,836

APPARATUS FOR IMPROVED ENCODING AND ASSOCIATED METHODS

Altera Corporation, San ...

1. An apparatus, comprising:
an encoder circuit adapted to encode data bits for transmission via a communication link, wherein the data bits have a run-length,
the encoder circuit comprising:

a logic circuit that selectively performs a logic operation on a pattern of bits and the data bits based on an approximation
of the run-length of the data bits in order to reduce the run-length of the data bits; and

a bit order scrambling circuit that selectively performs a bit scrambling operation on the data bits based on the approximation
of the run-length of the data bits to scramble an order of the data bits, that is connected in series with the logic circuit,
and that receives an output of the logic circuit.

US Pat. No. 9,396,358

INTEGRATED CIRCUIT WITH A SELF-DESTRUCTION MECHANISM

Altera Corporation, San ...

1. A method for securing an integrated circuit (IC), comprising:
detecting a tamper condition via a circuit in the IC;
placing the IC in a configurable state;
switching a multiplexer internal to the IC from selecting settings for scan pins from one or more pins of the integrated circuit
to selecting settings for scan pins from a controller circuit internal to the IC, thus disabling a scan chain interface in
the IC while in the configurable state, wherein the disabling prevents external input to the scan chain interface and external
output from the scan chain interface and enables sending an internal instruction from the controller circuit via the multiplexer
and the scan chain interface;

sending, from the controller circuit internal to the integrated circuit, the internal instruction via the scan chain interface,
with the external input prevented, wherein the internal instruction directs erasing a specified sector of a memory module;

initiating a power down operation in the IC; and
powering down the IC.

US Pat. No. 9,337,782

METHODS AND APPARATUS FOR ADJUSTING TRANSMIT SIGNAL CLIPPING THRESHOLDS

Altera Corporation, San ...

1. Circuitry, comprising:
peak canceling circuitry that receives signals and that clips peaks in the signals that exceed a magnitude threshold value
to generate peak-canceled signals;

predistortion circuitry that performs predistortion operations on the peak-canceled signals to generate predistorted signals;
signal conditioning circuitry that adjusts the magnitude threshold value based on a power transfer characteristic of the predistortion
circuitry;

an amplifier having an input and an output, wherein the input of the amplifier receives the predistorted signals from the
predistortion circuitry;

a delay path coupled between the signal conditioning circuitry and the input of the amplifier; and
delay circuitry interposed on the delay path.

US Pat. No. 9,255,968

INTEGRATED CIRCUIT WITH A HIGH-SPEED DEBUG ACCESS PORT

Altera Corporation, San ...

1. An integrated circuit comprising:
high speed serial interface circuitry having a function circuit block that receives a data packet from external circuitry;
and

a dedicated debug port in the high speed serial interface circuitry coupled to the function circuit block that transmits the
received data packet to debug circuitry on the integrated circuit.

US Pat. No. 9,166,052

MULTIPLE GATE SEMICONDUCTOR DEVICES AND THEIR APPLICATIONS

Altera Corporation, San ...

1. A semiconductor structure comprising:
a thin segment of a semiconductor having first and second major surfaces,
a first gate on the first major surface of the segment,
a second gate on the second major surface of the segment opposite the first gate, and
first and second differential inputs coupled, respectively, to the first and second gates for applying to the gates signals
of opposite polarity.

US Pat. No. 9,111,641

MEMORY CIRCUIT INCLUDING MEMORY DEVICES, A FREEZE CIRCUIT AND A TEST SWITCH

Altera Corporation, San ...

1. A memory circuit comprising:
a first memory device;
a second memory device coupled to the first memory device;
a freeze circuit coupled to a first output terminal and a second output terminal, wherein the first output terminal is an
output terminal of the first memory device and the second output terminal is an output terminal of the second memory device;
and

a test switch coupled to the first output terminal and the second output terminal.

US Pat. No. 9,076,776

INTEGRATED CIRCUIT PACKAGE WITH STAND-OFF LEGS

Altera Corporation, San ...

1. An integrated circuit (IC) package comprising:
a package substrate including a die attach pad (DAP) and a plurality of lead fingers arranged around the DAP;
a die mounted on the DAP;
a plurality of stand-off legs connected to the DAP; and
a mold compound covering the die, at least a portion of the package substrate, and at least a portion of the plurality of
stand-off legs,

wherein portions of the DAP directly above the plurality of stand-off legs have flat surfaces, further wherein the mold compound
covers bottom surfaces of the plurality of stand-off legs,

wherein each stand-off leg is coupled at one end to a bottom surface of the DAP and at the other end to a floor of the mold
compound, further wherein a vertical height of each stand-off leg is substantially equal to a vertical height between the
DAP and the floor of the mold compound, and further wherein the bottom surfaces of the plurality of stand-off legs are flat,
and

wherein the plurality of stand-off legs includes at least two stand-off legs connected to a first side of the DAP and at least
two stand-off legs connected to a second side of the DAP.

US Pat. No. 9,064,298

SEGMENT-BASED ENCODING SYSTEM USING RESIDUE CODING BY BASIS FUNCTION COEFFICIENTS

Altera Corporation, San ...

1. An encoding system for encoding uncompressed video data to form compressed video data, wherein the video data comprises
a sequence of a plurality of image frames comprising key frames and nonkey frames, the encoding system comprising:
an encoder comprising
a segmenter that generates a segmentation of a key frame, wherein the key frame is an image frame having content that is used
in encoding a nonkey frame, and wherein the segmentation is an assignment of some or all pixels of the key frame to segments
based on at least pixel color values and pixel locations,

a kinetic information generator that generates kinetic information that relates segments of a nonkey frame to segments of
the key frame that is used in encoding a nonkey frame, wherein the kinetic information includes a z-order for said segments,

a residue coder that codes residue data, wherein the residue data comprises differences between a frame representing differences
between content of the nonkey frame and a frame resulting from an application of the kinetic information of the reference
frame, and

a compressed video data outputter that outputs compressed video data including at least compressed key frames, the kinetic
information and residue data; and

a decoder that regenerates the nonkey frame from the compressed video data using kinetic information about the nonkey frame
from the compressed video data and residue data about the nonkey frame, and wherein the decoder fills an exposed area by examining
pixels color values of adjacent segments to the exposed area and continues a color value of an adjacent segment that has a
higher z-order than other adjacent segments of said adjacent segments so as to reconstruct the exposed area where one object
in a scene is partially obscuring another object in the scene,

wherein the residue is coded as coefficients of basis functions.

US Pat. No. 9,659,124

TRANSPORT NETWORK

Altera Corporation, San ...

1. A method for monitoring a programmable integrated circuit (IC), the method comprising:
with a debug system, monitoring a plurality of data bits from a plurality of configurable circuits configurably performing
a plurality of operations in the programmable IC; and

with a subset of the plurality of configurable circuits, providing the monitored plurality of data bits to a transport network
in the programmable IC, wherein the transport network operates a plurality of slots, each slot for transporting one data bit
to a set of destination circuits, wherein each data bit of the monitored plurality of data bits is provided to the transport
network by delaying each data bit from entering the transport network until a slot becomes available for transporting that
monitored data bit, wherein the plurality of configurable circuits are implemented on the programmable IC.

US Pat. No. 9,432,025

TECHNIQUES FOR REDUCING SKEW BETWEEN CLOCK SIGNALS

Altera Corporation, San ...

1. A circuit comprising:
a clock signal generation circuit to generate a first clock signal based on second and third clock signals, wherein the clock
signal generation circuit generates an indication of a phase difference between the second and the third clock signals; and

a skew reduction circuit to reduce skew between the second and the third clock signals in response to the indication of the
phase difference between the second and the third clock signals indicating that the second and the third clock signals are
aligned in phase within at least an error margin of the clock signal generation circuit.

US Pat. No. 9,384,312

METHOD AND APPARATUS FOR IMPLEMENTING PERIPHERY DEVICES ON A PROGRAMMABLE CIRCUIT USING PARTIAL RECONFIGURATION

Altera Corporation, San ...

1. A method for designing a system on a target device, the method comprising:
identifying a sequencer unit and a controller unit in a periphery device that operate at a different time, wherein the sequencer
unit configures a physical interface and the controller unit translates commands to the physical interface; and

partitioning the sequencer unit and the controller unit on the periphery device such that the sequencer unit is implemented
by a first instance of a partial reconfigurable (PR) module and the controller unit is implemented by a second instance of
the PR module.

US Pat. No. 9,368,451

MULTICHIP MODULE WITH REROUTABLE INTER-DIE COMMUNICATION

Altera Corporation, San ...

1. A module, comprising:
a substrate;
at least two cores coupled to the substrate wherein each of the at least two cores comprises a test processor that communicates
via test signals with the test processor in the other of the at least two cores wherein the test signals are communicable
via at least one connection that is dedicated to testing;

a plurality of Input/output (I/O) connections between said at least two cores, wherein the plurality of I/O connections includes
at least one redundant I/O connection; and

circuitry configured to reroute a signal from an I/O connection of the plurality of I/O connections to the at least one redundant
I/O connection based on a determination that said I/O connection is defective.

US Pat. No. 9,342,640

METHOD AND APPARATUS FOR PROTECTING, OPTIMIZING, AND REPORTING SYNCHRONIZERS

Altera Corporation, San ...

1. A method for designing a system on a target device using an electronic design automation (EDA) tool, comprising:
identifying a desirable mean-time-between-failure (MTBF) for a synchronizer chain to be implemented with programmable resources
on the target device;

computing a desirable chain slack for the synchronizer chain from the desirable MTBF for the synchronizer chain; and
computing slacks on all the hops of the synchronizer chain based on a current slack and the desirable chain slack, wherein
at least one of the identifying and computing is performed by a processor.

US Pat. No. 9,330,218

INTEGRATED CIRCUITS HAVING INPUT-OUTPUT CIRCUITS WITH DEDICATED MEMORY CONTROLLER CIRCUITRY

Altera Corporation, San ...

1. An integrated circuit comprising:
first and second input-output circuits each including respective memory controller circuitry; and
a backbone path that electrically couples the memory controller circuitry of the first and second input-output circuits, wherein
the first and second input-output circuits each include a multiplexing circuit interposed in the backbone path.

US Pat. No. 9,202,772

HEAT PIPE IN OVERMOLDED FLIP CHIP PACKAGE

Altera Corporation, San ...

1. A structure comprising:
a substrate,
a semiconductor die mounted on the substrate;
a molding material encircling the semiconductor die;
a lid on the molding material,
a heat pipe extending between the semiconductor die and the lid in a channel in the molding material; and
wherein the channel encircles the semiconductor die and the heat pipe contacts the lid and encircles and contacts an upper
part of all sides of the semiconductor die.

US Pat. No. 9,465,769

METHODS AND APPARATUS FOR HIGH-SPEED SERIAL INTERFACE LINK ASSIST

Altera Corporation, San ...

1. An apparatus for serial interface link assist, the apparatus comprising:
a physical coding sublayer (PCS) encoder that encodes an outgoing data signal to generate a first encoded outgoing data signal;
a link assist engine that obtains an encoded incoming data signal and outputs a second encoded outgoing data signal;
a multiplexor selector that selects one of the first and second encoded outgoing data signals and outputs the selected encoded
outgoing signal; and

a transmitter, including a serializer, that serializes and transmits the selected encoded outgoing signal to an outbound serial
data channel.