US Pat. No. 10,154,443

CROSS RADIO ACCESS TECHNOLOGY HANDOFF USING CACHING

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1. A User Equipment (UE), comprising:an antenna configured to receive data from a first access point;
a cache that stores the data; and
a controller configured to predict if the UE will undergo a connection handoff from the first access point to a second access point, and to request, responsive to predicting that the UE will undergo the connection handoff, a burst of data from the first access point to supplement the data in the cache in preparation for the connection handoff,
wherein the antenna is further configured to transmit a request for the burst of data to the first access point, and to receive the burst of data from the first access point in response to transmitting the request.

US Pat. No. 10,129,972

FRAME ELEMENTS FOR PACKAGE STRUCTURES COMPRISING PRINTED CIRCUIT BOARDS (PCBS)

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1. An apparatus, comprising:a substrate having an upper surface and a lower surface;
an electronic component disposed over the substrate;
an upper metallization disposed over the upper surface;
a frame element disposed directly on the upper metallization, the frame element comprising an outer wall disposed along a perimeter of the substrate, and a plurality of compartments disposed within a perimeter of the frame element, the frame element being configured to provide structural rigidity to the apparatus;
an encapsulating material disposed over an upper surface of the substrate, the electronic component and the frame element, the encapsulating material having upper surface and sides; and
an electrically conductive layer disposed over the upper surface and the sides of the encapsulating material.

US Pat. No. 10,136,449

WIRELESS LOCAL AREA NETWORK WITH ZERO-WAIT DYNAMIC FREQUENCY SELECTION

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8. A wireless local area network (WLAN) modem, comprising:a plurality of radio frequency (RF) transceivers, each configured to receive a WLAN signal operating at an RF frequency determined by a local oscillator (LO) frequency of a corresponding LO signal;
a plurality of WLAN baseband processor circuits, each coupled to a corresponding RF transceiver and configured to perform baseband processing associated with the WLAN signal; and
a controller configured to tune the RF frequency of a first RF transceiver of the plurality of RF transceivers from a first RF frequency to a second RF frequency to scan for radar signals operating on the second RF frequency;
wherein a remainder of the plurality of RF transceivers are tuned to the first RF frequency to communicate WLAN data simultaneously with the scan for radar signals operating on the second RF frequency,
wherein the corresponding LO signal for each transceiver in the remainder of the plurality of RF transceivers is tuned to the first RF frequency to communicate the WLAN data simultaneously with the scan for radar signals operating on the second RF frequency, and
wherein the remainder of the plurality of RF transceivers and a corresponding number of LU signals are greater than or equal to two.

US Pat. No. 10,134,686

SYSTEMS AND METHODS FOR PROVIDING ELECTROMAGNETIC INTERFERENCE (EMI) COMPARTMENT SHIELDING FOR COMPONENTS DISPOSED INSIDE OF SYSTEM ELECTRONIC PACKAGES

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1. A system module package comprising:a substrate;
a first compartment having a first set of electrical components disposed on a top surface of the substrate, the first set of electrical components including at least a first electrical component;
a second set of electrical components disposed on the top surface of the substrate external to the first compartment, the second set of electrical components including at least a second electrical component; and
a compartment electromagnetic interference (EMI) shield comprising a fence that extends substantially laterally along a compartment boundary at least in between the first and second sets of electrical components of the system module package, the fence comprising a plurality of substantially vertical conductive structures arranged along the compartment boundary and forming the fence, adjacent substantially vertical conductive structures being spaced apart from one another by a pitch that is preselected to ensure that the compartment EMI shield attenuates EMI of a frequency of interest, the fence extending substantially vertically relative to the top surface of the substrate, the fence being configured to attenuate EMI of a frequency of interest traveling in at least one of a first direction and a second direction, the first direction being from the first set of electrical components toward the second set of electrical components, the second direction being from the second set of electrical components toward the first set of electrical components, wherein each of the substantially vertical conductive structures has at least a first end that is mechanically coupled to the top surface of the substrate and has a highest point that is at a height, H, from the top surface of the substrate in a direction substantially normal to the top surface of the substrate, the height H being at least twice as great as a lateral distance, DL, of the highest point from a center of the first end of the respective substantially vertical conductive structure in a direction substantially parallel to the top surface of the substrate.

US Pat. No. 10,128,813

BULK ACOUSTIC WAVE (BAW) RESONATOR STRUCTURE

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1. A bulk acoustic wave (BAW) resonator, comprising:a first electrode;
a second electrode comprising a plurality of sides, wherein at least one of the sides is a connection side;
a piezoelectric layer disposed between the first and second electrodes, and
an acoustic reflective element disposed beneath the first electrode, the second electrode and the piezoelectric layer, wherein a contacting overlap of the acoustic reflective element, the first electrode, the second electrode, and the piezoelectric layer defines an active area of the BAW resonator;
a bridge adjacent to a termination of the active area of the BAW resonator;
a layer at least a part of which is disposed over a gap, and between the piezoelectric layer and the second electrode, the layer comprising a frame element, the frame element being disposed immediately adjacent to the termination of the active area; and
a discontinuity, which exists in the bridge.

US Pat. No. 10,134,682

CIRCUIT PACKAGE WITH SEGMENTED EXTERNAL SHIELD TO PROVIDE INTERNAL SHIELDING BETWEEN ELECTRONIC COMPONENTS

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1. A module, comprising:a circuit package, comprising:
a plurality of electronic components on a substrate; and
a molded compound disposed over the substrate and the plurality of electronic components; and
an external shield disposed on at least one outer surface of the circuit package, the external shield being segmented into a plurality of external shield partitions that are grounded, respectively, adjacent external shield partitions of the plurality of external shield partitions being separated by a corresponding gap located between adjacent electronic components of the plurality of electronic components,
wherein the external shield is configured to protect the circuit package from external electromagnetic radiation and environmental stress, and
wherein each corresponding gap separating the adjacent external shield partitions is configured to provide internal shielding of at least one of the electronic components, between which the corresponding gap is located, from internal electromagnetic radiation generated by the other of the adjacent electronic components.

US Pat. No. 10,128,812

ELECTRICAL RESONATOR

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1. An acoustic resonator, comprising:a substrate;
a cavity in the substrate; and
a resonator stack suspended over the cavity and comprising:
a first electrode; a second electrode; a piezoelectric layer; and a temperature compensation layer comprising borosilicate glass (BSG) wherein a concentration of boron in the temperature compensation layer is in a range of approximately 0.1% to approximately 5.0% by weight percent, or by atomic percent.

US Pat. No. 10,153,910

LOW POWER TWISTED PAIR CODING SCHEME

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1. A communication transceiver comprising:an analog front end configured to communicate, without a hybrid circuit, over at least one twisted pair that is only for transmitting data streams, and communicate, without the hybrid circuit, over at least one twisted pair that is only for receiving data streams; and
circuitry configured to
encode an input data stream to generate a first number of data streams,
multiplex the generated first number of data streams having a first transmission rate into a second number of data streams having a second transmission rate higher than the first transmission rate,
pre-code the multiplexed second number of data streams to be communicated via the at least one twisted pair that is only for transmitting data streams by the analog front end,
convert the pre-coded multiplexed second number of data streams into analog transmission signals,
transmit the analog transmission signals via the at least one twisted pair that is only for transmitting data streams,
convert a plurality of received signals received via the at least one twisted pair that is only for receiving data streams into digital data streams, and
control a sampling phase of the conversion of pre-coded multiplexed second number of data streams into the analog transmission signals and a sampling phase of the conversion of the plurality of received signals received via the at least one twisted pair that is only for receiving data streams into the digital data streams.

US Pat. No. 10,148,907

SYSTEM AND METHOD OF LUMINANCE PROCESSING IN HIGH DYNAMIC RANGE AND STANDARD DYNAMIC RANGE CONVERSION

AVAGO TECHNOLOGIES INTERN...

1. A method for converting between standard dynamic range (SDR) media and high dynamic range (HDR) media, comprising:receiving, by a media processor, an input media item in a first format;
determining, by the media processor, a luminance mapping ratio between a pixel of the input media item in the first format and a corresponding pixel of the media item in a second format;
determining, by the media processor, a peak luminance scaling factor;
for each pixel of the media item in the first format:
for each color component value of the pixel:
calculating, by the media processor, an output value based on a product of the color component value of the pixel, the luminance mapping ratio, and the peak luminance scaling factor, and
replacing, by the media processor, the color component value of the pixel with the calculated output value in the second format; and
providing, by the media processor, the media item in the second format.

US Pat. No. 10,152,433

INLINE PCI-IOV ADAPTER

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1. A Soft Register Unit for facilitating register access in a network device, the Soft Register Unit comprising:a Soft Register Engine having an external connection via a PCIe link;
a Soft Register CPU connected to the Soft Register Engine;
a first memory including an address decode table; the first memory accessible to the Soft Register Engine and the Soft Register CPU; and
a plurality of registers implemented in a second memory, the second memory accessible to the Soft Register Engine,
wherein, the Soft Register Unit facilitates register access by performing the steps of:
receiving a raw address by the Soft Register Engine via the PCIe link;
decoding the raw address by using the address decode table to locate a corresponding register;
obtaining the characteristics of the register; and
accessing the register in response to the characteristics of the register.

US Pat. No. 10,153,815

MIXED MODE OPERATIONS WITHIN MULTIPLE USER, MULTIPLE ACCESS, AND/OR MIMO WIRELESS COMMUNICATIONS

AVAGO TECHNOLOGIES INTERN...

1. A wireless communication device comprising:a communication interface; and
processing circuitry that is coupled to the communication interface, wherein at least one of the communication interface or the processing circuitry configured to:
generate a first orthogonal frequency division multiple access (OFDMA) frame that includes information that specifies a first time period during which a first other wireless communication device is to transmit first information via a first subset of OFDMA sub-carriers of a communication channel to the wireless communication device, wherein the first other wireless communication device has a first capability based on a first communication protocol;
transmit the first OFDMA frame to the first other wireless communication device;
receive the first information from the first other wireless communication device via the first subset of OFDMA sub-carriers of the communication channel during the first time period specified within the first OFDMA frame;
generate a second OFDMA frame that includes information that specifies a second time period during which a second other wireless communication device is to transmit second information via a second subset of OFDMA sub-carriers of the communication channel to the wireless communication device and also during which a third other wireless communication device is to transmit third information via a third subset of OFDMA sub-carriers of the communication channel to the wireless communication device, wherein both the second other wireless communication device and the third other wireless communication device have a second capability based on a second communication protocol that is different than the first capability based on the first communication protocol;
transmit the second OFDMA frame to the second other wireless communication device and the third other wireless communication device; and
receive the second information from the second other wireless communication device via the second subset of OFDMA sub-carriers of the communication channel and the third information from the third other wireless communication device via the third subset of OFDMA sub-carriers of the communication channel via another OFDMA frame during the second time period specified within the second OFDMA frame.

US Pat. No. 10,129,656

ACTIVE TEMPERATURE CONTROL OF PIEZOELECTRIC MEMBRANE-BASED MICRO-ELECTROMECHANICAL DEVICES

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1. An apparatus, comprising:a substrate;
a microelectronic ultrasonic transducer (MUT) disposed over the substrate; and
a thermoelectric device proximate to the MUT and configured to provide heat to, and remove heat from the MUT.

US Pat. No. 10,153,932

RESOURCE UNIT (RU) ALLOCATION WITHIN WIRELESS COMMUNICATIONS

AVAGO TECHNOLOGIES INTERN...

1. A wireless communication device comprising:a communication interface; and
processing circuitry that is coupled to the communication interface, wherein at least one of the communication interface or the processing circuitry configured to:
generate an orthogonal frequency division multiple access (OFDMA) frame that includes a preamble that specifies allocation of a first at least one resource unit (RU) for a communication channel and non-allocation of a second at least one RU for the communication channel, wherein:
a multi-bit index of the preamble is set to a first value to specify a first size and a first location of the first at least one RU that is allocated for the communication channel and a second size and a second location of the second at least one RU that is not allocated for the communication channel; and
the multi-bit index of the preamble is set to a second value to specify a third size and a third location of the first at least one RU that is allocated for the communication channel and a fourth size and a fourth location of the second at least one RU that is not allocated for the communication channel; and
transmit, via the communication channel, the OFDMA frame to at least one other wireless communication device to be processed by the at least one other wireless communication device to determine at least one of the allocation of the first at least one RU for the communication channel or the non-allocation of the second at least one RU for the communication channel.

US Pat. No. 10,141,268

CIRCUIT PACKAGE WITH INTERNAL AND EXTERNAL SHIELDING

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1. A module, comprising:a circuit package, comprising:
a first electronic component on a substrate, the first electronic component comprising a first die substrate with first electronic circuitry that generates electromagnetic radiation internally within the circuit package;
a second electronic component on the substrate, the second electronic component comprising a second die substrate with second electronic circuitry;
an internal shield electrically connected to ground and covering only a surface of the second die substrate facing away from the substrate, the internal shield being configured to shield the second electronic circuitry from the internally generated electromagnetic radiation from the first electronic circuitry; and
a molded compound disposed over the substrate and the first and second electronic components; and
an external shield disposed on at least one outer surface of the circuit package and electrically connected to ground, the external shield being configured to protect the circuit package from external electromagnetic radiation and environmental stress.

US Pat. No. 10,128,037

EMBEDDED SUBSTRATE CORE SPIRAL INDUCTOR

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1. An inductor comprising:a first conductive segment fabricated in a first core metal layer of a semiconductor package;
a second conductive segment fabricated in a second core metal layer of the semiconductor package;
a third conductive segment fabricated in the second core metal layer of the semiconductor package;
a first conductive core via through a core dielectric layer of the semiconductor package, the first conductive core via in contact with a first end of the first conductive segment and a first end of the second conductive segment;
a second conductive core via through the core dielectric layer of the semiconductor package, the second conductive core via in contact with a second end of the second conductive segment and a first end of the third conductive segment; and
an inductor terminal via connecting the first conductive segment to a fourth conductive segment within a build-up layer of the semiconductor package, wherein the first, the second, and the third conductive segments are fabricated with thicknesses that are greater than a thickness of the fourth conductive segment within the build-up layer.

US Pat. No. 10,129,587

FAST SWITCHING OF SYNCHRONIZED MEDIA USING TIME-STAMP MANAGEMENT

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1. A system, comprising:processing circuitry configured to:
obtain a video stream associated with a plurality of audio streams, the audio streams being time synchronized to the video stream;
decode the video stream; and
while the video stream is being continuously decoded:
concurrently perform time-stamp management on each of the audio streams;
decode portions of a selected subset of the audio streams having a first presentation time stamp, with portions of at least one of the audio streams having the first presentation time stamp being excluded from the selected subset and remaining undecoded; and
discard, from a buffer, the portions having the first presentation time stamp of the at least one of the audio streams that remain undecoded;
obtain a selection of a second subset of the audio streams; and
switch decoding from the selected subset to the second subset by:
decoding a first portion of the selected subset of the audio streams having a second presentation time stamp, and discarding without decoding a first portion of the second subset of the audio streams having the second presentation time stamp, each of the first portion of the selected subset of the audio streams and the first portion of the second subset of the audio streams synchronized to a first portion of the video stream, and
decoding a second portion of the second subset of the audio streams having a third presentation time stamp subsequent to the second presentation time stamp, and discarding without decoding a second portion of the selected subset of the audio streams having the second presentation time stamp, each of the second portion of the selected subset of the audio streams and the second portion of the second subset of the audio streams synchronized to a second portion of the video stream.

US Pat. No. 10,152,999

SYSTEMS AND METHODS FOR CORRELATION BASED DATA ALIGNMENT

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1. A data processing system comprising:a data detector operable to apply a data detection algorithm to generate detected values for user data in a data sector;
a data decoder operable to apply a data decode algorithm to a decoder input derived from the detected values to yield decoded values; and
an alignment detector operable to calculate an offset between multiple versions of the same user data in the data sector by correlating the multiple versions.

US Pat. No. 10,149,051

SYSTEM AND METHOD FOR LOUDSPEAKER PROTECTION

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1. A loudspeaker protection system comprising:an upstream loudspeaker model estimation component that includes:
an impedance model fitter configured to:
receive voltage sense data and current sense data over a frequency range of a loudspeaker;
estimate a plurality of impedance parameters associated with a plurality of impedance components of a model of the loudspeaker based on the voltage sense data and the current sense data; and
fit, as a function of frequency, each of the plurality of impedance components to an estimated impedance based on the voltage sense data and the current sense data to generate an estimated impedance model of the loudspeaker by combining the plurality of fitted impedance components;
wherein the plurality of impedance components include a voice coil resistivity component, a voice coil inductance component, a primary resonance component of the loudspeaker, and a secondary resonance component associated with an enclosure of the loudspeaker; and
an excursion model converter configured to:
receive the plurality of fitted impedance components that comprise the estimated impedance model from the impedance model fitter; and
convert the estimated impedance model to an excursion model of the loudspeaker.

US Pat. No. 10,141,960

SYSTEM FOR AND METHOD OF REDUCING TRANSMIT SIGNAL DISTORTION

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1. A transmitter circuit, comprising:a main pre-equalizer configured to pre-distort a burst signal;
a main power amplifier configured to receive the pre-distorted burst signal and generate an amplified burst signal using the pre-distorted burst signal;
a replica pre-equalizer configured to pre-distort a non-burst signal; and
a replica power amplifier, the replica power amplifier configured to receive the pre-distorted non-burst signal from the replica pre-equalizer and generate an amplified non-burst signal using the pre-distorted non-burst signal, wherein control signals are provided to the main pre-equalizer to pre-distort the burst signal, the control signals being provided using the amplified non-burst signal of the replica power amplifier.

US Pat. No. 10,177,736

BULK ACOUSTIC WAVE RESONATOR COMPRISING MULTIPLE ACOUSTIC REFLECTORS

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1. A bulk acoustic wave (BAW) resonator, comprising: a plurality of separate acoustic reflectors disposed in a substrate; a single lower electrode disposed over the plurality of separate acoustic reflectors; a piezoelectric layer disposed over the lower electrode and a plurality of upper electrodes being provided over a respective one of the plurality of separate acoustic reflectors.

US Pat. No. 10,175,739

WEARABLE DEVICE-AWARE SUPERVISED POWER MANAGEMENT FOR MOBILE PLATFORMS

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1. A power management system on a primary platform, comprising:a memory;
a processor coupled to the memory, the processor being configured, based on instructions stored in the memory, to:
establish communication between the primary platform and a secondary platform;
capture an application running on the secondary platform;
collect an input feature of the application and an output measure of the application reflecting a characteristic of the application as a training set for the application, wherein the input feature includes a utilization rate, wherein the utilization rate is a ratio of an active period over a total period, and wherein the total period is a sum of the active period and an idle period, and wherein the input feature and the output measure are categorized into a low, medium, or high category;
predict power consumption of the secondary platform with an expected performance level for a second application running on the secondary platform based on the training set; and
adjust a power management policy with a clock frequency of the secondary platform that reduces a total power consumption of the primary platform and the secondary platform.

US Pat. No. 10,148,284

APPARATUS AND METHOD FOR WIRED DATA COMMUNICATION

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1. A wired communication device, comprising:media access control (MAC) circuitry configured to:
frame a plurality of data packets to provide a plurality of framed data packets, each data packet of the plurality of data packets being separated from an adjacent data packet of the plurality of data packets by a corresponding interpacket gap (IPG) of a plurality of IPGs,
determine a first IPG duration from among a plurality of IPG durations corresponding to a first IPG of the plurality of IPGs, and
selectively choose a second IPG duration of the plurality of IPG durations corresponding to a second IPG of the plurality of IPGs to be greater than the first IPG duration when the first IPG duration is less than an average IPG duration or to be less than the first IPG duration when the first IPG duration is greater than the average IPG duration to maintain the average IPG duration over the plurality of framed data packets; and
physical layer (PHY) circuitry, coupled to the MAC circuitry, configured to encode the plurality of framed data packets in accordance with a line coding scheme to provide a plurality of encoded data packets.

US Pat. No. 10,148,670

MOVEMENT-BASED EVENT DETECTION IN A MOBILE DEVICE

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1. A user device for detecting an occurrence of an event comprising:a memory coupled to a processor, the memory configured to store a movement pattern signature of the user device indicative of a predefined movement pattern of the user device during the occurrence of the event; and
a movement sensing module comprising sensor hardware, the movement sensing module configured to:
capture a motion of the user device generated by a user of the user device, the captured motion including a change in rotation of the user device, a change in position of the user device, and a change in velocity of the user device;
convert the captured motion into the movement pattern signature;
store the movement pattern signature in the memory;
monitor the user device for movement that matches the stored movement pattern signature; and
in response to detecting that the monitored movement matches the stored movement pattern signature, wirelessly transmit a message to an external device indicating that the event has been detected and trigger a responsive action.

US Pat. No. 10,182,014

DATA COMMUNICATION IN A PEER-TO-PEER NETWORK

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1. A device, comprising:at least one processor circuit configured to:
initiate, in a discovery time window of a plurality of discovery time windows, a data connection setup with a second device;
in response to the data connection setup not being completed within the discovery time window:
randomly select, in a next discovery time window, a time window from among a subset of available time slots identified in at least one of an advertised availability of the device or an advertised availability of the second device; and
resume, in the time window, the data connection setup; and
receive information associated with one or more data transfer time windows from the second device upon completion of the data connection setup, wherein the one or more data transfer time windows are selected based at least on the data connection setup.

US Pat. No. 10,163,808

MODULE WITH EMBEDDED SIDE SHIELD STRUCTURES AND METHOD OF FABRICATING THE SAME

Avago Technologies Intern...

1. A module, comprising:a circuit package, comprising:
a plurality of electronic components on a substrate;
at least one side shield structure located at a corresponding at least one side edge region of the circuit package and electrically connected to ground, the at least one side shield structure being positioned on the substrate or on a pad on the substrate; and
a molded compound disposed over the substrate, the plurality of electronic components, and the at least one side shield structure, such that each of the at least one side shield structure is partially embedded in the molded compound and has an exposed end uncovered by the molded compound at a side edge of the corresponding at least one side edge region of the circuit package; and
a top external shield layer disposed on a top outer surface of the circuit package and electrically connected to ground,
wherein the at least one side shield structure and the top external shield layer provide an external shield configured to protect the circuit package from external electromagnetic radiation and environmental stress, and
wherein the at least one side shield structure extends partially through the molded compound without contacting the top external shield layer.

US Pat. No. 10,147,455

SENSOR CIRCUIT SUPPORTING MULTIPLE TRANSDUCERS WITH DEDICATED AND SHARED TERMINALS

AVAGO TECHNOLOGIES INTERN...

1. A memory system, comprising:a first transducer configured to output a first electrical signal indicative of a first operating parameter of the memory system, wherein the first transducer has a first DC bias applied thereto;
a second transducer configured to output a second electrical signal indicative of a laser output, wherein the second transducer has a second DC bias applied thereto, and wherein the second transducer shares a node with the first transducer; and
a sense amplifier that receives the first electrical signal and the second electrical signal and provides an output responsive to both the first electrical signal and the second electrical signal to a preamplifier Integrated Circuit (IC).

US Pat. No. 10,148,798

PHY/MAC INTERFACE (PMI) FOR COMMUNICATION SYSTEMS

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1. A communication device comprising:a communication interface; and
a processor, the processor and the communication interface configured to:
receive, from a first other communication device, a media access control (MAC) message for a second other communication device, wherein the MAC message is based on a physical layer (PHY)/MAC interface (PMI) protocol;
generate, based on the MAC message, a physical layer (PHY) message for the second other communication device, wherein the PHY message is based on the PMI protocol; and
transmit the PHY message to the second other communication device for use by the second other communication device to configure at least one PHY operational parameter within the second other communication device, wherein the second other communication device is located remotely with respect to the communication device.

US Pat. No. 10,148,460

PACKET EXTENSION FOR WIRELESS COMMUNICATION

Avago Technologies Intern...

1. A wireless communication device, comprising:one or more processors and/or circuits configured to:
identify a final symbol of an outgoing data packet that includes a data payload;
segment the final symbol into a plurality of short symbol segments;
determine a last short symbol segment of the plurality of short symbol segments that includes a portion of the data payload;
add a first padding and a second padding to the outgoing data packet based on the last short symbol segment and the portion of the data payload; and
a transmitter configured to transmit the outgoing data packet to a receiver.

US Pat. No. 10,178,757

SYSTEMS AND METHODS FOR PROVIDING ELECTROMAGNETIC INTERFERENCE (EMI) COMPARTMENT SHIELDING FOR COMPONENTS DISPOSED INSIDE OF SYSTEM ELECTRONIC PACKAGES

Avago Technologies Intern...

1. A system module package comprising:a substrate;
a first compartment having a first set of electrical components disposed on a top surface of the substrate, the first set of electrical components including at least a first electrical component;
a second set of electrical components disposed on the top surface of the substrate in a second compartment that is external to the first compartment, the second set of electrical components including at least a second electrical component; and
a compartment electromagnetic interference (EMI) shield comprising a conductive fence and a substantially horizontal conductive structure, the substantially horizontal conductive structure being electrically coupled to the conductive fence, the conductive fence extending along a compartment boundary at least in between the first and second sets of electrical components and extending substantially normal to the top surface of the substrate, the substantially horizontal conductive structure being substantially parallel to the top surface of the substrate and being disposed above the top surface of the substrate, and wherein the compartment EMI shield is configured to attenuate EMI of a frequency of interest traveling in at least one of a first direction from the first set of electrical components toward the second set of electrical components and a second direction from the second set of electrical components toward the first set of electrical components.

US Pat. No. 10,177,735

SURFACE ACOUSTIC WAVE (SAW) RESONATOR

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1. An apparatus, comprising:a silicon (Si) substrate having a first surface and a second surface, the silicon substrate having a resistivity at room temperature greater than approximately 1000 ?-cm, and less than approximately 15000 ?-cm; and
a piezoelectric layer disposed over the silicon substrate and having a first surface and a second surface, wherein the piezoelectric layer has an optical absorptivity of greater than approximately 0.1 cm?1 to less than approximately 1.0 cm?1 at an optical wavelength of approximately 500 nm.

US Pat. No. 10,164,605

BULK ACOUSTIC WAVE RESONATOR WITH PIEZOELECTRIC LAYER COMPRISING LITHIUM NIOBATE OR LITHIUM TANTALATE

Avago Technologies Intern...

1. A bulk acoustic wave (BAW) resonator, comprising:a substrate defining a cavity;
a bottom electrode disposed over the substrate and the cavity;
a piezoelectric layer disposed over the bottom electrode, the piezoelectric layer comprising polycrystalline lithium niobate (LN) material;
a top electrode disposed over the piezoelectric layer; and
an encapsulant layer formed over side and top surfaces of the piezoelectric layer, the encapsulant layer being configured to protect the LN material from a release solvent previously applied to sacrificial material within the cavity in the substrate.

US Pat. No. 10,185,535

INTERMEDIARY DEVICE FOR ESTABLISHING WIRELESS SERVICES

Avago Technologies Intern...

1. A device comprising:at least one processor circuit configured to:
identify a first wireless device configured to broadcast a wireless service over a wireless personal area network;
receive information for connecting to the first wireless device to access the wireless service; and
transmit, to a second wireless device, the information for connecting to the first wireless device to access the wireless service, wherein a transmission corresponding to the wireless service that is received by the second wireless device bypasses the device and the second wireless device is not a member of the wireless personal area network prior to connecting to the first wireless device to access the service.

US Pat. No. 10,181,835

BULK ACOUSTIC RESONATOR DEVICES AND PROCESSES FOR FABRICATING BULK ACOUSTIC RESONATOR DEVICES

Avago Technologies Intern...

1. A bulk acoustic wave (BAW) resonator device comprising:a substrate having a bottom surface and a top surface;
a bottom metal electrode disposed on the top surface of the substrate;
a piezoelectric material layer disposed on the top surface of the substrate and covering the bottom metal electrode, the piezoelectric material layer having at least a first opening formed therein;
a top metal electrode disposed on a top surface of the piezoelectric material layer;
a first additional metal feature disposed on a top surface of the bottom metal electrode beneath the first opening at least at a first location on the top surface of the bottom metal electrode, the first additional metal feature having a preselected width and thickness; and
a metal bottom electrode electrical contact disposed in the first opening and in contact with at least the first additional metal feature to allow an electrical connection to be established with the bottom metal electrode.

US Pat. No. 10,181,968

SYSTEM AND METHOD FOR BACKCHANNEL CLOSED LOOP FEEDBACK FOR CHANNEL EQUALIZATION OVER ETHERNET

AVAGO TECHNOLOGIES INTERN...

1. A method, comprising:configuring a network link for active data communication between a first network device and a second network device via a physical communication medium;
after the network link is configured for active data communication, communicating data between a first physical layer device in the first network device and a second physical layer device in the second network device;
analyzing, by the first network device during the active data communication, a frequency response of a communication channel that includes the physical communication medium, corresponding to a change in heat generation in the first network device over a time duration in the order of minutes during the active data communication;
determine, by the first network device during the active data communication responsive to the change in heat generation in the first network device over the time duration, an equalization adjustment based on the analyzed frequency response; and
transmitting, by the first network device, equalization information to the second network device in an amplitude, frequency or phase modulated signal using a packet that is interspersed with packets carrying live traffic of data communicated between the first and second physical layer devices, for adjustment of a transmit equalizer in the second physical layer device, the equalization information based on the determined equalization adjustment.

US Pat. No. 10,177,734

SURFACE ACOUSTIC WAVE (SAW) RESONATOR

Avago Technologies Intern...

1. A surface acoustic wave (SAW) resonator structure, comprising:a substrate having a first surface and a second surface, the first surface having a plurality of features;
a piezoelectric layer disposed over the substrate, the piezoelectric layer having a first surface and a second surface;
a plurality of electrodes disposed over the first surface of the piezoelectric layer, the plurality of electrodes configured to generate surface acoustic waves in the piezoelectric layer; and
an acoustic wave suppression layer having a first surface and a second surface, the acoustic wave suppression layer being disposed between the first surface of the substrate and the second surface of the piezoelectric layer, the acoustic wave suppression layer having a thickness in a range of approximately 300 ? to approximately one third of a wavelength (?/3) of a resonance mode of the SAW resonator structure, the first surface of the acoustic wave suppression layer having a smoothness sufficient to foster atomic bonding between the first surface of the acoustic wave suppression layer and the second surface of the piezoelectric layer, wherein the plurality of features reflect acoustic waves and reduce an incidence of spurious modes in the piezoelectric layer.

US Pat. No. 10,178,616

ENHANCED DISCOVERY CHANNEL FOR INTERWORKING BETWEEN A CELLULAR WIDE-AREA COMMUNICATION SYSTEM AND A WIRELESS LOCAL-AREA COMMUNICATION SYSTEM

Avago Technologies Intern...

1. A method comprising:inserting, in a discovery channel, interworking capability information of a small cell base station of a small cell of a cellular wide-area communication network; and
transmitting, by the small cell base station, the discovery channel including the interworking capability information of the small cell base station to a user equipment located in the small cell,
wherein the interworking capability information of the small cell base station indicates a capability of the small cell base station to operate between a cellular wide-area communication system of the cellular wide-area communication network and a wireless local-area communication system of a wireless local-area communication network and includes discovery assistant information comprising at least one of a beacon interval, a working channel, a load indication, or neighbor access information of the wireless local-area communication system.

US Pat. No. 10,165,361

SYSTEM AND METHOD FOR LOUDSPEAKER PROTECTION

Avago Technologies Intern...

1. A loudspeaker protection system, comprising:an upstream loudspeaker model estimation component including:
an impedance model fitter configured to receive at least current data of a loudspeaker during audio playback, to estimate an impedance of the loudspeaker based on the at least received current data, and to estimate a plurality of impedance model parameters of an impedance model of the loudspeaker based on the estimated impedance of the loudspeaker, and
an excursion model converter configured to compare the estimated impedance model to the estimated impedance of the loudspeaker to estimate one or more first impedance model parameters of the plurality of impedance model parameters as being non-negligible and one or more second impedance model parameters of the plurality of impedance model parameters as being negligible, to convert the one or more first impedance model parameters to a plurality of parameters of an excursion model of the loudspeaker and to exclude the one or more second impedance model parameters from the excursion model of the loudspeaker; and
a downstream audio signal processing component including:
first audio signal processing circuitry configured to receive an audio signal and the plurality of parameters of the excursion model of the loudspeaker and to generate a processed version of the audio signal corresponding to a constrained predicted excursion based on the excursion model, and
distortion suppression circuitry configured to suppress unwanted distortion in the processed version of the audio signal to generate an output audio signal for playback by the loudspeaker.

US Pat. No. 10,164,883

SYSTEM AND METHOD FOR FLOW MANAGEMENT IN SOFTWARE-DEFINED NETWORKS

AVAGO TECHNOLOGIES INTERN...

1. A switch, comprising:one or more ports capable of processing data flows based on a flow rule;
flow circuitry configured to allocate a flow identifier to a generic flow definition, which indicates a flow that is not specific to any input port of the switch;
lookup circuitry configured to:
store, in a first data structure, one or more port-specific flow rules generated based on the generic flow definition, wherein each port-specific flow rule corresponds to a port of the one or more ports; and
store the flow identifier in a respective entry of a second data structure, wherein each entry of the second data structure corresponds to a port of the one or more ports; and
forwarding circuitry configured to determine an egress port for a packet based on one of the one or more port-specific flow rules.

US Pat. No. 10,164,744

FLEXIBLE OFDMA PACKET STRUCTURE FOR WIRELESS COMMUNICATIONS

AVAGO TECHNOLOGIES INTERN...

14. A method for execution by a wireless communication device, the method comprising:generating an orthogonal frequency division multiple access (OFDMA) packet that includes first one or more fields based on a first communication protocol and for a plurality of other wireless communication devices modulated across all of OFDMA sub-carriers of the OFDMA packet followed by second one or more fields based on a second communication protocol and for the plurality of other wireless communication devices modulated across all of the OFDMA sub-carriers of the OFDMA packet, wherein the second one or more fields is followed by third one or more fields for a first of the plurality of other wireless communication devices modulated across a first subset of the OFDMA sub-carriers and fourth one or more fields for a second of the plurality of other wireless communication devices modulated across a second subset of the OFDMA sub-carriers; and
transmitting, via a communication interface of the wireless communication device, the OFDMA packet, via the communication interface and via at least one wireless communication channel that includes the OFDMA sub-carriers of the OFDMA packet, to the plurality of other wireless communication devices.

US Pat. No. 10,164,796

FLEXIBLE FLOW TABLE WITH PROGRAMMABLE STATE MACHINE

AVAGO TECHNOLOGIES INTERN...

1. A network switch for network communications, the network switch comprises:a first data bus, the first data bus supporting receiving first data;
a second data bus, the second data bus supporting transmitting second data;
a data flow analyzer, the data flow analyzer coupled between the first data bus and the second data bus and including at least:
a first table configured to detect selectable data packet fields within a data flow;
a second table including a programmable state machine, the second table coupled to an output of the first table and configured to retain selectable states of one or more instances of the detected selectable data packet fields;
programmable switch logic configured to output one or more potential actions to be taken based on a selectable computation of the detected selectable data packet fields;
a third table coupled to the programmable switch logic and including encoding for a current state of the selectable states and next state transitions; and
wherein the data flow analyzer communicates with the first data bus to receive and analyze the selectable data packet fields, compute a programmable state and potential actions, and communicate the one or more potential actions to the second data bus.

US Pat. No. 10,209,992

SYSTEM AND METHOD FOR BRANCH PREDICTION USING TWO BRANCH HISTORY TABLES AND PRESETTING A GLOBAL BRANCH HISTORY REGISTER

Avago Technologies Intern...

1. A method, comprising:providing a program to be executed in accordance with a speculative address;
executing the program, the program comprising a procedure;
setting bits in a taken branch history register to indicate whether a branch is taken or not taken during execution of instructions in the program;
calling the procedure in the program; and
overwriting, responsive to calling the procedure, contents of the taken branch history register to a start address for the procedure;
accessing, using a hash block, a first branch history table based on contents of the taken branch history register for a first prediction of whether a current branch will be taken or not taken;
accessing, using the hash block, a second branch history table based on the contents of the taken branch history register for a second prediction of whether the current branch will be taken or not taken; and
determining whether the first prediction or the second prediction is used based on whether a selection value in a selection entry of a selector table is equal to or greater than a threshold value.

US Pat. No. 10,180,542

CONTROL DEVICE AND METHOD FOR CONTROLLING BIASING OF MULTIPLE LIGHT SOURCES OF MULTIPLE CHANNELS OF A MULTI-CHANNEL OPTICAL COMMUNICATIONS MODULE

AVAGO TECHNOLOGIES INTERN...

1. A control device for controlling an optical transmitter of an optical transceiver transmitting a first transmission through a medium, and an optical receiver of the optical transceiver receiving a second transmission through a medium, the control device comprising:a transmitter interface circuit having a first biasing generator and a second biasing generator, wherein the first and second biasing generators are adapted to control the optical transmitter so as to generate the first transmission, the first and second biasing generators operating in first and second supply voltage domains, respectively, that are substantially non-overlapping;
a receiver interface circuit configured to at least receive an electrical connection from the receiver;
a control circuit coupled to the transmitter interface circuit and to the receiver interface circuit, the control circuit being configured to control operations of the first and second biasing generators, wherein the control circuit operates in the first supply voltage domain; and
a level shift circuit configured to convert a first signal operating within the first supply voltage domain into a first converted signal operating within the second supply voltage domain.

US Pat. No. 10,181,932

METHOD TO COORDINATE RESOURCE ALLOCATION TO ADDRESS INTER-CELL INTERFERENCE

AVAGO TECHNOLOGIES INTERN...

1. A method to coordinate resource allocation to address inter-cell interference, comprising:sending a first message by a first pico eNB to a macro eNB, the first message specifying a target cell identifier of a second pico eNB and an expected number of Almost Blank Subframes (ABS) to service user equipment in an overlap region between the first pico eNB and the second pico eNB;
receiving, by the second pico eNB, a second message sent by the macro eNB, the second message specifying an ABS resource allocation and the target cell identifier of the second pico eNB; and
the second pico eNB operating according to the ABS resource allocation specified in the second message.

US Pat. No. 10,171,303

IP-BASED INTERCONNECTION OF SWITCHES WITH A LOGICAL CHASSIS

AVAGO TECHNOLOGIES INTERN...

1. A switch, comprising:one or more ports;
chassis management circuitry configured to assign a virtual Internet Protocol (IP) address to the switch, wherein the virtual IP address is associated with a logical unit comprising the switch and a second switch in a network of interconnected switches, wherein the network of interconnected switches further includes a third switch and is identified by a fabric identifier distinct from the virtual IP address, and wherein the fabric identifier is assigned to a respective switch of the network of interconnected switches; and
tunnel circuitry configured to:
encapsulate a packet with a tunnel header associated with a tunnel between the logical unit and the third switch, wherein the tunnel header includes the virtual IP address as a source address and a second IP address of the third switch as a destination address; and
determine a port from the one or more ports as an egress port for the encapsulated packet based on the second IP address.

US Pat. No. 10,164,870

RELAXED ORDERING NETWORK

Avago Technologies Intern...

1. A network interface controller for processing packets arranged in a sequential packet order before transmission over an ordered multi-path network, the network interface controller comprising:a negotiation module configured to negotiate, with a data flow source, packets that are to be transmitted in a data flow through the ordered multi-path network using a relaxed order that differs from the sequential packet order; and
a packet reassembly module configured to:
receive the packets transmitted in the data flow through the ordered multi-path network in the relaxed order; and
reassemble the packets received in the relaxed order into the sequential packet order prior to delivering the packets having the sequential packet order for sequential processing;
wherein the negotiation module is configured to determine during the negotiation whether the data flow source has an Internet Protocol (IP) address on a list of IP addresses that are predetermined to communicate packets using the relaxed order, and
wherein the IP address on the list of IP addresses indicates that the data flow source operates according to a TCP/IP protocol that can be negotiated to communicate packets using the relaxed order.

US Pat. No. 10,165,489

NETWORK SELECTION

AVAGO TECHNOLOGIES INTERN...

1. A method for use in access network selection in a telecommunications system comprising at least a mobile telephony radio access network, the method comprising:monitoring, by circuitry of a network node of the mobile telephony radio access network, a traffic volume within the mobile telephony radio access network;
determining, by the circuitry, whether the traffic volume exceeds a predetermined threshold;
identifying, by the circuitry and based on the determining, a preference to offload specific internet protocol (IP) flows of data communication in the mobile telephony radio access network to an available local area network;
transmitting, by the circuitry to a user equipment via the mobile telephony radio access network, an indication of the identified preference, the indication including at least one condition that, when satisfied, the user equipment is to offload the data communication; and
offloading, by the user equipment when the at least one condition is satisfied, the specific IP flows of the data communication without offloading other IP flows of the data communication.

US Pat. No. 10,165,285

VIDEO CODING TREE SUB-BLOCK SPLITTING

AVAGO TECHNOLOGIES INTERN...

1. An apparatus comprising:an input configured to receive a bitstream, corresponding to a video signal, and including a plurality of treeblocks;
a parser and treeblock splitter configured to:
partition adaptively the plurality of treeblocks (TBs) into a plurality of sub-treeblocks (STBs) such that each of the plurality of TBs corresponding to a respective plurality of STBs; and
output the plurality of STBs, in parallel, via a first pathway and a second pathway of a plurality of pathways;
a video decoder including:
a first decoding engine configured to receive the plurality of STBs via the first pathway and to perform a first at least one video decoding operation to generate a first at least one intermediate decoded resultant; and
a second decoding engine configured to receive the plurality of STBs via the second pathway and to perform a second at least one video decoding operation that is different than and is independent from the first at least one video decoding operation, in parallel with the first decoding engine performing the first at least one video decoding operation, to generate a second at least one intermediate decoded resultant; and
a combiner configured to combine the first at least one intermediate decoded resultant and the second at least one intermediate decoded resultant to generate at least one decoded resultant; and wherein:
the first decoding engine configured to partition adaptively the plurality of STBs further into a plurality of sub-STBs and to perform the first at least one video decoding operation on the plurality of sub-STBs to generate the first at least one intermediate decoded resultant;
the parser and treeblock splitter configured to partition adaptively the plurality of TBs into a plurality of STBs based on at least of at least one characteristic associated with at least one local processing condition of the apparatus and at least one characteristic associated with at least one source device to provide the bitstream via at least one communication network; and
each of the plurality of STBs having a size of 32 pixels by 32 pixels.

US Pat. No. 10,257,523

ADAPTIVE DECODING SYSTEM

Avago Technologies Intern...

1. An adaptive decoding system, comprising:a bitstream extractor configured to extract data including one or more of temporal sub-layers, reference frames, non-reference frames, or Random Access Point (RAP) pictures from a video bitstream;
a decoder coupled to the bitstream extractor and configured to decode the data extracted by the bitstream extractor;
a decoding speed monitor configured to determine a decoding rate at which the decoder decodes the data extracted by the bitstream extractor; and
a quality of experience (QoE) selector coupled to the decoding speed monitor and the bitstream extractor and configured to adjust an extraction quality level of the bitstream extractor based on a comparison of the decoding rate and a rate at which the bitstream extractor sends the data to the decoder.

US Pat. No. 10,211,881

SYSTEMS AND METHODS FOR IMPLEMENTING ENERGY-EFFICIENT ETHERNET COMMUNICATIONS

Avago Technologies Intern...

1. A method for implementing an Energy-Efficient Ethernet (EEE) communication, the method comprising:receiving, from a media access control (MAC) layer, a plurality of data streams at an input of a first physical layer of a first electronic device via a first set of wires;
identifying, at the first physical layer, an EEE signal in the plurality of data streams received via the first set of wires, the EEE signal being associated with one of a first EEE signal type or a second EEE signal type;
combining, at the first physical layer, the plurality of data streams into a combined data stream for transmission via a second set of wires, the second set of wires comprising a single twisted pair of wires, the first set of wires comprising more wires than the second set of wires;
encoding, at the first physical layer, the combined data stream to include a first indication of the EEE signal when the EEE signal is associated with the first EEE signal type and encoding the combined data stream to include a second indication of the EEE signal when the EEE signal is associated with the second EEE signal type, the first indication and the second indication identifying different low power idle signals; and
communicating the encoded combined data stream at an output of the first physical layer of the first electronic device via the second set of wires, the encoded combined data stream being communicated in a full-duplex mode from the first physical layer of the first electronic device to a second physical layer of a second electronic device over the single twisted pair of wires.

US Pat. No. 10,199,082

AUTOMATIC DELAY-LINE CALIBRATION USING A REPLICA ARRAY

AVAGO TECHNOLOGIES INTERN...

1. A computer memory system, comprising:a memory array comprising a plurality of memory cells; and
a delay calibration circuit comprising a delay-line that is used to measure a chip-specific delay between when a bitline is discharged by a bitcell and when a sense amplifier is used to detect a memory value from the memory array, wherein the delay calibration circuit triggers the delay-line to begin measuring the chip-specific delay in response to a timing trigger, wherein the delay calibration circuit further comprises a first counter, a second counter, and a clock signal, wherein the first counter is connected to the delay-line, wherein the second counter is connected to the clock signal, and wherein the timing trigger corresponds to a time where the clock signal is started and the first and second counters both begin counting at substantially the same time.

US Pat. No. 10,198,316

SYSTEMS AND METHODS FOR EFFICIENT FLASH MEMORY ACCESS

AVAGO TECHNOLOGIES INTERN...

1. A system for accessing a flash memory device, the system comprising:a first encoder circuit operable to apply a first encoding algorithm to a user data set to yield a first number of first algorithm codewords, wherein each of the first number of the first algorithm codewords includes a second number of elements;
a second encoder circuit operable to apply a second encoding algorithm to a combination of the first number of the first algorithm codewords to yield a second number of sets of a third number of voltage values; wherein each of the sets of the third number of voltage values represents corresponding elements of each of the first number of the first algorithm codewords; and
a write circuit operable to apply voltages indicated by each of the third number of voltage values to respective flash memory cells.

US Pat. No. 10,193,852

CANONICAL NAME (CNAME) HANDLING FOR GLOBAL SERVER LOAD BALANCING

AVAGO TECHNOLOGIES INTERN...

1. A method of providing load balancing in a network, the method comprising:receiving, by a processor, a domain name system (DNS) reply to a DNS request to resolve an alias host name that is an alias for a primary domain, wherein the DNS reply includes
a canonical name (CNAME) record identifying the primary domain, and
network addresses that correspond with the primary domain;
detecting, by said processor, the CNAME record identifying the primary domain in said DNS reply;
applying, by said processor a load balancing algorithm configured to be applied to DNS requests for the primary domain to the network addresses received in response to the DNS request to resolve the alias host name; and
sending, by said processor, to a client program that originated the DNS request to resolve the alias host name, a response to the DNS request that includes a list of the network addresses associated with the primary domain that has been ordered according to the load balancing algorithm configured to be applied to DNS requests for the primary domain.

US Pat. No. 10,211,281

ISOLATION DEVICE

AVAGO TECHNOLOGIES INTERN...

1. An isolation capacitor, comprising:a first capacitive element in electrical communication with a first circuit and having a first area;
a second capacitive element in electrical communication with a second circuit that operates at a different voltage than the first circuit, wherein the second capacitive element comprises a second area that is different from the first area, wherein the second capacitive element comprises a conductive element formed on or near a top surface of a substrate, wherein the substrate further comprises at least one metal layer that is included in the second circuit, and wherein the second capacitive element is electrically connected to the at least one metal layer through at least one via; and
at least one isolation layer disposed on the substrate and positioned between the first capacitive element and the second capacitive element, wherein the at least one isolation layer substantially prohibits electrical current from flowing between the first capacitive element and the second capacitive element, thereby maintaining an electrical isolation between the first circuit and second circuit, and wherein the at least one isolation layer allows a capacitively coupled signal to travel between the first capacitive element and the second capacitive element thereby enabling communication between the first circuit and second circuit even though the first circuit and second circuit are electrically isolated from one another;
wherein a trench isolation layer is provided between the second capacitive element and the first capacitive element, wherein the trench isolation layer comprises a top surface that is substantially parallel with the top surface of the substrate, and wherein at least a portion of the second capacitive element that is aligned with the first capacitive element is buried in the substrate and covered by the trench isolation layer.

US Pat. No. 10,210,105

INLINE PCI-IOV ADAPTER

AVAGO TECHNOLOGIES INTERN...

1. A soft register unit for facilitating register access in a network device, the soft register unit comprising:soft register engine having an external connection via a link;
a soft register microprocessor connected to the soft register engine;
a first memory including an address decode table, the first memory accessible to the soft register engine and the soft register microprocessor; and
a plurality of registers implemented in a second memory, the second memory accessible to the soft register engine,
wherein, the soft register unit facilitates register access by performing the steps of:
receiving a raw address by the soft register engine via the link;
decoding the raw address by using the address decode table to locate a corresponding register;
obtaining characteristics of the register; and
accessing the register in response to the characteristics of the register.

US Pat. No. 10,206,084

POWER-EFFICIENT, BALANCED, AND RELIABLE TRUE WIRELESS BLUETOOTH STEREO AUDIO SOLUTION

Avago Technologies Intern...

1. A system for wirelessly communicating audio content, comprising:a first audio sink device;
a second audio sink device, wherein the first and second audio sink devices are wirelessly connected via a hybrid link, and are each configured to render a different audio channel of stereo audio content wirelessly received from an audio source; and
a link manager residing on at least one of the first audio sink device and the second audio sink device, the link manager configured to:
select the second audio sink device to bidirectionally communicate with the audio source, by:
enabling the first audio sink device to wirelessly receive the stereo audio content from the audio source via a first wireless link between the first audio sink device and the audio source, and disabling the first audio sink device from wirelessly transmitting messages to the audio source via the first wireless link, and
enabling the second audio sink device to wirelessly receive the stereo audio content from the audio source via a second wireless link between the second audio sink device and the audio source, and enabling the second audio sink device to wirelessly transmit messages to the audio source via the second wireless link;
compare a first link quality of the first wireless link, with a second link quality of the second wireless link; and
in response to the first link quality being better than the second link quality, select the first audio sink device to bidirectionally communicate with the audio source, by:
enabling the first audio sink device to wirelessly receive the stereo audio content from the audio source via the first wireless link, and enabling the first audio sink device to wirelessly transmit messages to the audio source via the first wireless link, and
enabling the second audio sink device to wirelessly receive the stereo audio content from the audio source via the second wireless link, and disabling the second audio sink device from wirelessly transmitting messages to the audio source via the second wireless link.

US Pat. No. 10,205,660

APPARATUS AND METHOD FOR PACKET HEADER COMPRESSION

Avago Technologies Intern...

5. A method for operating a network, the method comprising:receiving, by the network, a first frame including a first header that is formatted in accordance with a first communication protocol or layer and a second header that is formatted in accordance with a second communication protocol or layer, wherein one or more second fields from the second header are compressed as conveying similar information as one or more first fields of the first header;
determining, by the network whether the one or more second fields from the second header should be compressed or uncompressed,
decompressing, by the network, the one or more second fields from the second header that convey the similar information as the one or more first fields of the first header when the one or more second fields from the second header should be uncompressed to provide a decompressed first frame; and
providing, by the network, the first frame as a second frame from among a second plurality of frames when the one or more second fields from the second header should be compressed or the decompressed first frame as the second frame from among the second plurality of frames when the one or more second fields from the second header should be uncompressed.

US Pat. No. 10,205,438

ADJUSTABLE LOW-PASS FILTER IN A COMPACT LOW-POWER RECEIVER

AVAGO TECHNOLOGIES INTERN...

1. An adjustable low-pass filter (LPF) in a compact low-power receiver, the adjustable LPF comprising:a resistance input block; and
a plurality of operational amplifiers, wherein
an input of at least one of the plurality of operational amplifiers is coupled to an output of the at least one of the plurality of operational amplifiers by at least one capacitor;
a number of the plurality of operational amplifiers does not exceed a number of poles characterizing the adjustable LPF, and
an output stage of least one of the plurality of operational amplifiers includes two transistors connected in a cascode configuration, and two cross-coupling transistors that connect opposite terminals of the two transistors in cascode configuration,
wherein the resistance input block includes a network of switchable unit resistors arranged in series and a parallel array of switchable resistors situated between an input of the adjustable LPF and the network, and
the parallel array and the network include native devices for controlling the switchable resistors and the switchable unit resistors.

US Pat. No. 10,203,400

OPTICAL MEASUREMENT SYSTEM INCORPORATING AMBIENT LIGHT COMPONENT NULLIFICATION

AVAGO TECHNOLOGIES INTERN...

1. An optical measurement system comprising:a first detector circuit comprising a combination of a photodetector and at least one gain element, the photodetector comprising an avalanche photodetector (APD) that converts optical signals incident thereon into electrical signals, the gain element amplifying the electrical signals to produce amplified electrical signals; and
first correlator and ambient light suppression circuitry electrically coupled with the first detector circuit and configured to receive a first amplified electrical signal from the first detector circuit relating to an amount of ambient light that is incident on the photodetector and to receive a second amplified electrical signal from the first detector circuit relating to the amount of ambient light that is incident on the photodetector and an amount of desired light reflected from a target object that is incident on the photodetector, the first correlator and ambient light suppression circuitry processing the first and second amplified electrical signals to produce a compensated electrical signal from which an effect of ambient light has been removed, the first correlator and ambient light suppression circuitry correlating the compensated signal with a reference signal to determine a distance of the optical measurement system from the target object.

US Pat. No. 10,205,975

TRICK MODE OPERATION WITH MULTIPLE VIDEO STREAMS

Avago Technologies Intern...

1. A method, comprising:decoding a first video stream having a first level of a video characteristic at a first rate and a second video stream having a second level of the video characteristic at the first rate, the first video stream and the second video stream directed to a same video content;
presenting the first video stream for display;
in response to receiving a first command, changing to decode the second video stream from the first rate to a second rate based at least in part on a determination determined using the first level of the video characteristic and the second level of the video characteristic, wherein the second rate is higher than the first rate, and wherein the second level of the video characteristic is different from the first level of the video characteristic; and
presenting the second video stream directed to the same video content as the first video stream for display while stopping displaying the first video stream.

US Pat. No. 10,203,966

APPLICATION LAUNCHER AND MANAGEMENT FRAMEWORK FOR A NETWORK DEVICE

AVAGO TECHNOLOGIES INTERN...

1. A network device comprising:a set of one or more processors;
a set of ports for receiving or forwarding packets;
wherein a first processor from the set of processors is configured to execute, as part of a network operating system (NOS) of the network device, an application launcher and management framework (ALM);
wherein the ALM is configured to:
receive information identifying an application to be executed by the network device, the application being a third-party application;
receive configuration information for the application, the configuration information identifying a condition for launching the application, the condition related to a state of a command line interface (CLI) of the network device or a state of the set of ports of the network device;
monitor the network device to determine a current state;
determine, based at least on the current state of the network device, if the condition is satisfied; and
cause the application to be executed by the network device upon determining that the condition is satisfied, wherein
a second processor from the set of processors is configured to
determine a first state associated with the network device upon determining that a failover has occurred; and
cause the application to be re-launched in response to determining that the first state is associated with the network device.

US Pat. No. 10,205,539

MAGNETIC CIRCUIT FOR HIGH SPEED AUTOMOTIVE ETHERNET OVER UTP CHANNELS

Avago Technologies Intern...

1. A transceiver, comprising:a physical layer device (PHY) configured to send and receive differential data signals via a media dependent interface (MDI) over an unshielded twisted pair (UTP) cable;
a common mode choke (CMC), coupled between an input/output port of the PHY and the MDI, and configured to provide a low impedance to the differential data signals and a high impedance to common mode noise;
a common mode termination (CMT) configured to provide a matched termination for the common mode noise; and
a differential mode choke (DMC), coupled between the UTP cable and the CMT, configured to provide a low impedance for the common mode noise and a high impedance for the differential data signals,
wherein the CMT includes an input node connected to an output of the DMC and includes another node connected to ground.

US Pat. No. 10,204,006

SYSTEMS AND METHODS FOR SIDE DATA BASED SOFT DATA FLASH MEMORY ACCESS

AVAGO TECHNOLOGIES INTERN...

1. A method, comprising:accessing a first set of memory cells having a series of voltages written to the first set of memory cells, each cell having a voltage value representing codewords stored to the cell;
receiving the voltage value of the each cell;
comparing the voltage value of the each cell to a first threshold to determine a first binary set of the each cell, the first binary set including a first group of binary values;
comparing the voltage value of the each cell to a second threshold to determine a second binary set of the each cell, the second binary set including a second group of binary values and a third group of binary values;
generating a soft data representation of the codewords using a combination of the second group of binary values and at least one side data value;
decoding the soft data representation to obtain recovered read data; and
storing the recovered read data.

US Pat. No. 10,187,653

MOTOR VECTOR PREDICTION USING CO-LOCATED PREDICTION UNITS

Avago Technologies Intern...

1. A device comprising:buffer circuitry configured to store:
a current picture comprising a current pixel group comprising a pixel subgroup;
a target reference picture comprising a co-located pixel group that includes a spatial position in the target reference picture occupied by the current pixel group in the current picture; and
a reference vector picture;
candidate selection circuitry in data communication with the buffer circuitry, the candidate selection circuitry configured to:
without first shifting the current pixel group in accord with an offset vector, determine the co-located pixel group has an assigned candidate motion vector;
determine a default motion vector from the assigned candidate motion vector of the co-located pixel group; and
subgroup vector selection circuitry in data communication with the buffer circuitry and the candidate selection circuitry, the subgroup vector selection circuitry configured to:
determine that a spatiotemporal neighbor pixel group has an assigned reference vector that indicates a predictive relationship that points to the reference vector picture;
determine a ratio of a first duration between the current picture and the reference vector picture to a second duration between the current picture and the target reference picture;
scale the reference vector in accord with the ratio to determine the offset vector;
shift the current pixel group in accord with the offset vector, and then determine whether a pre-determined pixel of the pixel subgroup occupies a spatial position that is occupied by a predictor pixel group that is assigned a predictor motion vector;
when the pre-determined pixel of the pixel subgroup occupies the spatial position that is occupied by the predictor pixel group that is assigned a predictor motion vector, processing the predictor motion vector to generate a subgroup motion vector for the pixel subgroup; and
when the pre-determined pixel of the pixel subgroup does not occupy the spatial position that is occupied by the predictor pixel group that is assigned the predictor motion vector, assigning the default motion vector to the pixel subgroup irrespective of whether other predictor pixel groups are assigned predictor motion vectors.

US Pat. No. 10,187,080

APPARATUS AND SYSTEM FOR HIGH SPEED KEEPER BASED SWITCH DRIVER

AVAGO TECHNOLOGIES INTERN...

1. A keeper based switch driver, comprising:circuitry configured to
generate overlapping differential signals,
increase a crossing point of the overlapping differential signals a first predetermined amount,
further increase the crossing point of the overlapping differential signals a second predetermined amount, and
limit signal swing to an absolute value of a drain source voltage.

US Pat. No. 10,257,117

DISTRIBUTED SWITCH ARCHITECTURE

AVAGO TECHNOLOGIES INTERN...

1. A method comprising:establishing a distributed buffering architecture comprising:
an input packet buffer in an ingress tile;
an output packet buffer in an egress tile, the input packet buffer and the output packet buffer not being located on shared memory; and
at least one buffer in a switching fabric, the at least one buffer in the switching fabric being separate from the input packet buffer and the output packet buffer and being located between an ingress and an egress of the switching fabric;
connecting the ingress tile and the egress tile with the switching fabric; and
executing a distributed bandwidth grant mechanism between the ingress tile and the egress tile, through the switching fabric,
wherein:
the distributed bandwidth grant mechanism comprises a store-and-forward bandwidth credit grant mechanism,
the method further comprises tracking, with an ingress queue scheduler, active virtual output queues (VoQs) defined in the input packet buffer,
the distributed bandwidth grant mechanism further comprises a cut through grant mechanism in which packet cells immediately begin to flow through the switching fabric to the egress tile, and
the method further comprises:
receiving a packet cell in a staging buffer in the ingress tile; and
making an ingress-side decision on whether the packet cell is ingress-side eligible for cut through to the egress tile.

US Pat. No. 10,200,187

METHODS AND SYSTEMS FOR DISSIPATING HEAT IN OPTICAL COMMUNICATIONS MODULES

AVAGO TECHNOLOGIES INTERN...

1. An optical communications system comprising:a first surface-mount structure having first and second arrays of electrical contacts disposed on top and bottom surfaces thereof, respectively;
clock and data recovery (CDR) circuitry mounted on a first mounting region of the top surface of the first surface-mount structure and having electrical contacts that are in contact with respective electrical contacts of the first array of electrical contacts;
a parallel optical communications module mounted on a second mounting region of the first surface-mount structure, the module including a module surface-mount structure having third and fourth arrays of electrical contacts disposed on top and bottom surfaces thereof, respectively, wherein electrical contacts of the fourth array of electrical contacts are in contact with respective electrical contacts of the first array of electrical contacts; and
a baffle mechanically coupled with the optical communications system, the baffle having walls that define first and second convective air pathways that are thermally decoupled from one another.

US Pat. No. 10,200,001

METHODS AND DEVICES FOR AUTOMATIC GAIN CONTROL

AVAGO TECHNOLOGIES INTERN...

1. A controller operable to:check control bits;
sample a first signal at a frequency that is indicated by the checked control bits, the first signal indicating an initial amplitude of an output signal of an oscillator circuit;
select a step amount based on the sampled first signal and a target amplitude of the output signal; and
generate a control signal for the oscillator circuit based on the selected step amount, the control signal indicating a change in gain for the oscillator circuit according to the selected step amount.

US Pat. No. 10,193,714

CONTINUOUS TIME PRE-CURSOR AND POST-CURSOR COMPENSATION CIRCUITS

Avago Technologies Intern...

1. A pre-cursor compensation circuit for performing pre-cursor compensation on a differential input signal, the pre-cursor compensation circuit comprising:a first differential pair of transistors comprising first gate terminals coupled to the differential input signal, first source terminals coupled across a degeneration resistor, and first drain terminals coupled to a pre-cursor compensated version of the differential input signal; and
a second differential pair of transistors comprising second gate terminals coupled to the differential input signal, second source terminals coupled across a degeneration capacitor, and second drain terminals coupled to the pre-cursor compensated version of the differential input signal.

US Pat. No. 10,194,241

SYSTEM AND METHOD FOR LOUDSPEAKER PROTECTION

Avago Technologies Intern...

1. A loudspeaker protection system comprising an audio signal processing component that includes:first audio signal processing circuitry comprising a non-linear constraint filter that is configured to:
receive an audio signal;
receive one or more parameters of an excursion model of a loudspeaker from a model estimation component; and
generate a processed version of the audio signal corresponding to a constrained predicted excursion based on the one or more parameters of the excursion model; and
second audio signal processing circuitry configured to apply a gain change parameter to the audio signal prior the audio signal being received by the first audio signal processing circuitry, the gain change parameter being based on a temperature of a component of the loudspeaker.

US Pat. No. 10,193,509

POWER AMPLIFIER HARMONIC MATCHING NETWORK

Avago Technologies Intern...

1. An output network connected to an output of a nonlinear unmatched power amplifier that provides an amplified voltage signal at a fundamental frequency, the output network comprising:a harmonic matching network comprising a plurality of acoustic resonators configured to match a plurality of harmonic frequencies of the amplified voltage signal to one of substantially zero impedance, appearing as a short at the output of the nonlinear unmatched power amplifier, or substantially infinite impedance, appearing as an open at the output of the nonlinear unmatched power amplifier, resulting in zero voltage or zero current at higher harmonic frequencies, respectively, to avoid power distribution at the higher harmonic frequencies,
wherein each higher harmonic frequency of the plurality of matched harmonic frequencies is higher than a first harmonic frequency, which is the fundamental frequency.

US Pat. No. 10,200,080

SELF-INTERFERENCE CANCELLATION FOR FULL-DUPLEX COMMUNICATION USING A PHASE AND GAIN ADJUSTED TRANSMIT SIGNAL

Avago Technologies Intern...

1. An apparatus configured to cancel interference, from an outbound signal provided at an output of a power amplifier (PA), in an inbound signal at an input of a low-noise amplifier (LNA), the apparatus comprising:a first resistor controllably coupled between a first differential end of the output of the PA and the input of the LNA;
a first capacitor controllably coupled between the first differential end of the output of the PA and the input of the LNA;
a second resistor controllably coupled between a second differential end of the output of the PA and the input of the LNA; and
a second capacitor controllably coupled between the second differential end of the output of the PA and the input of the LNA.

US Pat. No. 10,198,063

AVERAGE POWER SAVING MODES AND POWER ARCHITECTURE FOR READ CHANNEL PRODUCT

AVAGO TECHNOLOGIES INTERN...

1. A power regulation system for a read channel assembly, the read channel assembly having at least one front-end component and at least one back end codec having at least one sampling frequency, the system comprising:at least one first voltage regulator connected to a power source and to the at least one front-end component, and to use the power source to supply a first voltage to the at least one front-end component; and
at least one second voltage regulator connected to the power source and to the at least one back-end codec, and to use the power source to (a) supply a second voltage to the at least one back-end codec, and (b) decrease from the second voltage to a third voltage lower than the second voltage in response to at least one first prompt from the at least one back-end codec,
wherein the at least one first prompt includes the at least one back-end codec reducing the at least one sampling frequency at which a data signal is being sampled by the at least one back-end codec from a first sampling frequency to a second sampling frequency,
wherein the reducing of the at least one sampling frequency occurs in response to an activity condition in which circuits of the at least one back-end codec are running in parallel, and
wherein the at least one first voltage regulator holds the first voltage constant while the at least one second voltage regulator decreases from the second voltage to the third voltage.

US Pat. No. 10,190,889

COUNTING SENSOR FOR COUNTING THE NUMBER OF REVOLUTIONS OR OF LINEAR DISPLACEMENTS OF AN OBJECT

AVAGO TECHNOLOGIES INTERN...

1. Counting sensor for counting the number of revolutions or of linear displacements of an object, wherein the counting sensor comprises:one single Wiegand module, which is composed of a Wiegand wire having a coil which encloses the Wiegand wire;
at least one sensor element;
a processing electronics, which is connected to the sensor element and configured to evaluate an output signal that is output from the sensor element; and
a permanent magnet arrangement, which is movable relative to the Wiegand module in one direction as well as in a direction that is opposite to said one direction, wherein the permanent magnet arrangement is configured to be arranged at the object such that the permanent magnet arrangement performs the revolutions or the linear displacements together with the object; wherein:
upon movement of the permanent magnet arrangement in said one direction, the coil of the Wiegand module generates a voltage impulse, if a north pole or a south pole of the permanent magnet arrangement is located at a first position, and, upon movement of the permanent magnet arrangement in said opposite direction, the coil of the Wiegand module generates the voltage impulse, if the north pole or the south pole of the permanent magnet arrangement is located at a second position that is different from the first position,
in an autonomous mode, in which the counting sensor is not supplied with outside energy, the processing electronics is supplied with energy that is provided by the Wiegand module,
the processing electronics is configured, after detecting the voltage impulse that is output from the Wiegand module, to
(i) obtain, by an evaluation of the output signal of the sensor elements, direction information indicating whether the permanent magnet arrangement moves in said one direction or in said opposite direction, and (ii) to obtain, by an evaluation of the output signal of the sensor element or by a determination of the polarity of the voltage impulse that is generated by the coil of the Wiegand module, magnetic pole information indicating whether the north pole or the south pole of the permanent magnet arrangement is located at said first or said second position; and
a data storage for storing a value, which indicates the number of the revolutions or of the linear displacements; wherein
the processing electronics is configured (i) to incorporate both the direction information and the magnetic pole information in a sequence, to determine the number of the revolutions or of the linear displacements of the object on the basis of the direction information and the magnetic pole information, and to store the corresponding value in the data storage, (ii) to perform, on the basis of the sequence of the direction information and the magnetic pole information, an error detection indicating whether one of the revolutions or one of the linear displacements of the object has not been detected partially or completely, and (iii) upon detection of the error, to determine a corresponding correction of said number and to correct said value.

US Pat. No. 10,256,788

ACOUSTIC RESONATOR INCLUDING EXTENDED CAVITY

Avago Technologies Intern...

1. A bulk acoustic wave (BAW) resonator, comprising:a substrate defining a cavity, the substrate being formed of a nonlinear material;
an acoustic stack over the substrate and the cavity, the acoustic stack comprising:
a bottom electrode;
a piezoelectric layer over the bottom electrode; and
a top electrode over the piezoelectric layer, wherein an active region of the acoustic stack comprises overlapping portions of the cavity, the bottom electrode, the piezoelectric layer and the top electrode; and
a connecting strip extending from a portion of the top electrode for providing electrical excitation of the acoustic stack, wherein an electric field (E-field) is generated in the BAW resonator, the E-field beginning at the top electrode and terminating at the bottom electrode, in response to the electrical excitation, a portion of the E-field outside the active region of the acoustic stack being a parasitic E-field,
wherein the cavity includes an inner portion in the active region of the acoustic stack and a first extended portion extending from an outer perimeter of the active region underneath the connecting strip, and
wherein a length of the first extended portion of the cavity is sufficient to substantially prevent the parasitic E-field from passing through the substrate, resulting in a negligible amount of the parasitic E-field passing through the substrate, such that a nonlinear response to the parasitic E-field by the substrate is improved and electrical loss generated in the substrate is reduced.

US Pat. No. 10,200,706

PIPELINED VIDEO DECODER SYSTEM

Avago Technologies Intern...

1. A device comprising:at least one circuit configured to:
decode a current block within a frame of video data, the frame comprised of a plurality of blocks;
identify an intra-block copy request (IBC request) for the current block, wherein the IBC request comprises copying content from a source block to the current block of the frame, wherein the source block is within the frame and has been decoded; and
copy the content of the source block to the current block.

US Pat. No. 10,254,312

TRANSMISSION LINE COUPLER FOR TESTING OF INTEGRATED CIRCUITS

Avago Technologies Intern...

1. A transmission line coupling circuit, comprising:a flexible substrate; and
a plurality of transmission line coupling blocks formed onto the flexible substrate in a circular manner around a central point of the flexible substrate, the plurality of transmission line coupling blocks comprising:
a plurality of first coupled transmission lines implemented on a top side of the flexible substrate and connected to the central point,
a plurality of first conductive traces implemented on the top side of the flexible substrate and connected between the plurality of first coupled transmission lines and a plurality of ports,
a plurality of second coupled transmission lines implemented on a bottom side of the flexible substrate and connected to a plurality of vias, and
a plurality of second conductive traces implemented on the top side of the flexible substrate and connected between the plurality of vias and a plurality of load resistors.

US Pat. No. 10,250,200

LOW POWER SPECTRALLY PURE OFFSET LOCAL OSCILLATOR SYSTEM

Avago Technologies Intern...

1. A transmitter back-end comprising:a frequency synthesizer configured to generate an offset local oscillator (LO) signal;
an LO offset circuit configured to adjust a frequency of the offset LO signal to provide a desired LO signal;
a back-end mixer configured to mix a baseband signal and the desired LO signal to provide an up-converted signal; and
a power amplifier (PA) configured to amplify the up-converted signal output by the back-end mixer;
wherein the LO offset circuit comprises:
an offset mixer configured to frequency shift the offset LO signal to provide a frequency shifted offset LO signal; and
a filter configured to filter an unwanted portion of the frequency shifted offset LO signal.

US Pat. No. 10,218,332

BROADBAND MATCHING CIRCUIT FOR CAPACITIVE DEVICE

Avago Technologies Intern...

5. A switched power amplifier duplexer (S-PAD) device having a composite broadband frequency range, the S-PAD device comprising:a solid state switch configured to selectively connect a circuit device to one of a plurality of acoustic filters having a corresponding plurality of different frequency bands within the composite broadband frequency range;
a first matching circuit configured to match an impedance of the solid state switch and an impedance of the circuit device, the first matching circuit comprising:
a first series resonance circuit comprising a first inductor and a first capacitor connected between the solid state switch and the circuit device, the first series resonance circuit having a predetermined first resonance frequency within a middle portion of the composite broadband frequency range; and
a second matching circuit configured to match impedances of the solid state switch and one acoustic filter of the plurality of acoustic filters, the second matching circuit comprising:
a second series resonance circuit comprising a second inductor and a second capacitor connected between the solid state switch and the one acoustic filter, the second series resonance circuit having a predetermined second resonance frequency within the middle portion of the composite broadband frequency range;
wherein one of the first matching circuit and the second matching circuit further comprises a first shunt inductor, connected at one end between the solid state switch and one of the first series resonance circuit or the second series resonance circuit, respectively, and connected at an opposite end to reference ground, the first shunt inductor being configured to transform the impedance of the solid state switch to a matching impedance for a matching resonance frequency, the matching resonance frequency being within the middle portion of the composite broadband frequency range, and
wherein each of the first series resonance circuit and the second series resonance circuit is configured to further transform the matching impedance of the solid state switch and the first shunt inductor to a design matching impedance within the composite broadband frequency range.

US Pat. No. 10,191,855

CACHING SYSTEMS AND METHODS FOR PAGE RECLAMATION WITH SIMULATED NVDRAM IN HOST BUS ADAPTERS

AVAGO TECHNOLOGIES INTERN...

1. A system, comprising:a host processor operable to generate Input/Output (I/O) requests;
a host memory communicatively coupled to the host processor and sectioned into pages;
a host bus adapter (HBA) communicatively coupled to the host processor to process the I/O requests, wherein the HBA comprises a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD); and
an HBA driver operable on the host processor wherein the DRAM is sectioned into pages mapped to pages of the host memory, and the SSD is sectioned into pages mapped to pages of the DRAM, and
wherein the HBA driver is operable to detect a rate at which the pages of the DRAM are accessed for both of read requests and write requests of the I/O requests, to determine a rate of page reclamation based on the detection, and to reclaim pages of data in the DRAM by moving pages of data from the DRAM into the pages of the SSD based on the determined rate of page reclamation.

US Pat. No. 10,256,865

BIDIRECTIONAL TRANSCEIVER CIRCUITS

Avago Technologies Intern...

1. A bidirectional time-division duplexing transceiver circuit, the transceiver circuit comprising:a first and a second bidirectional phase-shift circuit; and
a bidirectional amplifier circuit including a first amplifier circuit and a second amplifier circuit, wherein the first amplifier circuit and the second amplifier circuit are connected to double-pole-double-throw (DPDT) switches, wherein a first DPDT switch is configured to connect the first amplifier circuit to a first radio-frequency (RF) antenna and a second DPDT switch is configured to connect the second amplifier circuit to a second RF antenna, and wherein the first and the second bidirectional phase-shift circuit and the DPDT switches are configured to enable the first amplifier circuit and the second amplifier circuit to be operable simultaneously as transmit (TX) path amplifiers in a first time slot and as a receive (RX) path amplifiers in a second time slot.

US Pat. No. 10,270,221

OPTICAL DEVICE AND SYSTEM HAVING AN ARRAY OF ADDRESSABLE APERTURES

Avago Technologies Intern...

1. An optical device, comprising:a semiconductor layer having a first surface and a second surface opposing the first surface, the semiconductor layer comprising a plurality of active regions;
a plurality of first metal strips positioned adjacent to the first surface, each of the plurality of first metal strips being in a substantially parallel arrangement and oriented in a first direction;
a plurality of apertures positioned on the plurality of first metal strips; and
a plurality of second metal strips positioned adjacent to the second surface, each of the plurality of second metal strips being in a substantially parallel arrangement and oriented in a second direction that forms an angle relative to the first direction,
wherein each of the plurality of active regions are positioned at an intersection residing between a metal strip in the plurality of first metal strips and a metal strip in the plurality of second metal strips, and
wherein the plurality of active regions are positioned in correspondence with the plurality of apertures, respectively, such that the plurality of active regions are adaptable to emit light independently through a corresponding aperture.

US Pat. No. 10,237,004

INTER-RADIO COMMUNICATIONS FOR SCHEDULING OR ALLOCATING TIME-VARYING FREQUENCY RESOURCES

AVAGO TECHNOLOGIES INTERN...

1. A device comprising:two radios, each corresponding to a different communication protocol;
a generalized coexistence interface (GCI) that interconnects the two radios, wherein at least one of the radios includes circuitry configured to
determine characteristics of jammer signals associated with a first wireless protocol of another of the two radios based, at least in part, on information received via the GCI,
determine an amount of interference between the jammer signals and a first received signal at the device associated with a second wireless protocol, and
filter the jammer signals from the first received signal in a case that the amount of interference between the jammer signals and the first received signal is greater than a first predetermined threshold,
wherein the circuitry filters the jammer signals from the first received signal using a notch filter in a case that a bandwidth of the jammer signals is less than a second predetermined threshold, and filters the jammer signals from the first received signal using a whitening filter in a case that the bandwidth of the jammer signals is greater than the second predetermined threshold.

US Pat. No. 10,236,239

APPARATUS AND SEMICONDUCTOR STRUCTURE INCLUDING A MULTILAYER PACKAGE SUBSTRATE

Avago Technologies Intern...

1. An apparatus, comprising:a first heat sink comprising: a first side and a second side, the entire first side being disposed over an upper surface of a multilayer package substrate, and the second side comprising a plurality of electrically conductive pedestals disposed thereon, the first heat sink being configured to connect to a plurality of semiconductor devices and to provide an electrical ground for the semiconductor devices, wherein each of the electrically conductive pedestals is configured to connect to one of the semiconductor devices, the multilayer package substrate comprising: at least one dielectric layer having the upper surface; a second heat sink comprising a first electrically conductive layer disposed in a first layer; a second electrically conductive layer disposed in a third layer; and a via disposed in a second layer, the via electrically connecting the first electrically conductive layer and the second electrically conductive layer.

US Pat. No. 10,236,247

ISOLATION DEVICE

AVAGO TECHNOLOGIES INTERN...

1. An isolation system comprising:a plurality of metal layers comprising a top most metal layer, a second top most metal layer and at least one additional metal layer;
a first isolation layer having a first thickness sandwiched between the top most metal layer and the second top most metal layer;
a second isolation layer having a second thickness sandwiched between the second top most metal layer and the at least one additional metal layer, wherein the first thickness is substantially larger than the second thickness;
a first circuit electrically connected to the top most metal layer; and
a second circuit electrically connected to the second top most metal layer and the at least one additional metal layer, wherein the first circuit and the top most metal layer are electrically isolated from the second circuit, the second top most metal layer and the at least one additional metal layer through the first isolation layer.

US Pat. No. 10,237,026

BEAMFORMING FEEDBACK TONE/SUB-CARRIER LOCATION WITHIN WIRELESS COMMUNICATIONS

AVAGO TECHNOLOGIES INTERN...

1. A wireless communication device comprising:a communication interface; and
processing circuitry that is coupled to the communication interface, wherein at least one of the communication interface or the processing circuitry configured to:
receive, via a communication channel and from another wireless communication device, a null data packet (NDP) sounding frame that includes a plurality of long training fields (LTFs) and a plurality of pilots at predetermined locations;
identify a set of feedback sub-carrier locations based on a sub-carrier or tone grouping factor and a communication channel bandwidth of a plurality of communication channel bandwidths specified within a NDP announcement frame that is received before the NDP sounding frame;
process the NDP sounding frame to generate beamforming feedback by estimating the communication channel for each sub-carrier location within the set of feedback sub-carrier locations; and
transmit, via the communication channel, a beamforming feedback frame to the another wireless communication device that includes estimates of the communication channel for each sub-carrier location within the set of feedback sub-carrier locations.

US Pat. No. 10,237,824

POWER EFFICIENT NETWORKING

Avago Technologies Intern...

1. A device comprising:at least one processor circuit configured to:
identify a time to enter a low power state;
transmit, prior to the identified time, transmission parameters to a network coordinator device for a network of devices, the transmission parameters being associated with a transmission from at least one of the devices to the device;
enter the low power state at the identified time; and
upon exiting the low power state, receive the transmission from the at least one of the devices based at least in part on the transmission parameters.

US Pat. No. 10,270,348

SYNCHRONOUS SWITCHING REGULATOR CIRCUIT

Avago Technologies Intern...

1. A synchronous switching regulator circuit, the circuit comprising:a pass transistor configured to couple a switching circuit to a supply voltage; and
a switch operable to synchronously turn off a flow of a supply current through the pass transistor,
wherein:
the switching circuit is configured to be controlled by a switching signal, and
the switch is configured to be controlled by the switching signal to operate in synchronization with the switching circuit.

US Pat. No. 10,268,592

SYSTEM, METHOD AND COMPUTER-READABLE MEDIUM FOR DYNAMICALLY MAPPING A NON-VOLATILE MEMORY STORE

Avago Technologies Intern...

1. A method for dynamically managing a virtual address space disposed in a host, the virtual address space corresponding to data accessible to a host bus adapter for the host, the method comprising:initializing a paging table which is disposed in the host to correspond to a first portion of available storage capacity of a volatile memory element coupled to the host bus adapter, the first portion of the volatile memory element containing first information stored in a non-volatile memory element, wherein the method further includes:
when an application executing in the host triggers a fault by requesting access to a page that is not present in the volatile memory element;
instructing the host bus adapter to transfer second information from a region of the non-volatile memory element to a second portion of the volatile memory element, the second information defining a most recently transferred region and including the page that is not present in the volatile memory element as defined by the fault;
modifying the paging table to include a reference to the most recently transferred region; and
updating the virtual address space to reflect the reference in the paging table.

US Pat. No. 10,271,421

SYSTEMS AND METHODS FOR PROVIDING ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING BETWEEN INDUCTORS OF A RADIO FREQUENCY (RF) MODULE

Avago Technologies Intern...

1. A radio frequency (RF) module comprising:a multi-layer substrate having a plurality of layers and a top surface, the plurality of layers including at least N layers of metal, where N is a positive integer that is greater than or equal to 1;
at least first and second inductors disposed in the multi-layer substrate, each of the first and second inductors having at least N coils, the first and second inductors having first and second axes, respectively, that are substantially perpendicular to the top surface of the multi-layer substrate, each coil being disposed in a respective layer of metal of the N layers of metal; and
at least a first electromagnetic interference (EMI) shield at least partially surrounding and extending over the first inductor, the first EMI shield being electrically coupled to an electrical ground structure of the multi-layer substrate, the first EMI shielding reducing EMI crosstalk between the first and second inductors, the first EMI shield comprising at least a first set of electrically-conductive wires, each electrically-conductive wire comprising: a first wire portion; a second wire portion; a third wire portion; and first and second bends where the first and second wire portions, respectively, transition into the third wire portion, wherein the third wire portion is substantially parallel to a top surface of the multilayer substrate.

US Pat. No. 10,270,660

FUNCTION VIRTUALIZATION FOR MULTIMEDIA NETWORK TOPOLOGY ADAPTATION

AVAGO TECHNOLOGIES INTERN...

1. A system comprising: a service provider network interface; anda cable interface to a multimedia over coax alliance (MoCA) network of MoCA nodes, the MoCA network of MoCA nodes organized in a physical tree network topology; and
network controller circuitry in communication with the service provider network interface, the network controller circuitry configured to:
execute as a MoCA network controller (NC) for the MoCA nodes in the MoCA network;
implement bandwidth scheduling for the MoCA nodes as the MoCA network controller, including asymmetric provisioning of bandwidth to provide gateway to MoCA node downlink bandwidth for broadband program content that is greater than MoCA node to gateway uplink bandwidth;
receive the broadband program content through the service provider network interface; and
communicate the broadband program content received from the service provider network interface to the MoCA nodes using the downlink bandwidth, according to a logical star network topology over the physical tree network topology.

US Pat. No. 10,270,696

TRANSMISSION OF DATA PACKETS OF DIFFERENT PRIORITY LEVELS USING PRE-EMPTION

Avago Technologies Intern...

1. A method for transmitting frames of at least two different priority levels via one or more bearer channels, comprising:buffering, by a plurality of service queues, a plurality of low priority frames and a plurality of high priority frames, each service queue from among the plurality of service queues corresponding to different priority levels;
fragmenting a low priority frame from among the plurality of low priority frames into a plurality of low priority code words, each low priority code word in the plurality of low priority code words comprising a sync code from among a plurality of sync codes, the sync code being configured to indicate a priority level of the low priority frame;
mapping a priority bit of the low priority frame to at least one of the plurality of sync codes;
transmitting the plurality of low priority code words via the one or more bearer channels after the fragmenting and prior to transmitting a high priority code word;
wherein in case the high priority code word corresponding to a high priority frame from among the plurality of high priority frames arrives during transmission of the plurality of low priority code words, the following is performed:
interrupting the transmission of the plurality of low priority code words,
transmitting the high priority code word corresponding to the high priority frame, and
resuming the transmission of the plurality of low priority code words via the one or more bearer channels after the transmission of the high priority code word.

US Pat. No. 10,270,717

UNIFIED MEDIA ACCESS CONTROL (MAC) FOR MULTIPLE PHYSICAL LAYER DEVICES

AVAGO TECHNOLOGIES INTERN...

1. A device comprising:a media access control (MAC) circuit communicatively coupled to first and second physical layer circuits, wherein the first physical layer circuit is configured to communicate with another device over a first physical wireless channel, the second physical layer circuit is configured to communicate with the another device over a second physical wireless channel, and the MAC circuit is configured to:
receive one or more data items to be transmitted to the another device;
select at least one of the first or second physical layer circuits for transmission of the one or more data items to the another device based at least in part on a first wireless link quality of the first physical wireless channel and a second wireless link quality of the second physical wireless channel; and
provide the one or more data items to the selected at least one of the first or second physical layer circuits for transmission to the another device.

US Pat. No. 10,250,338

TRANSMITTER DRIVE WITH IMPROVED TRANSMITTER PERFORMANCE AND RELIABILITY

Avago Technologies Intern...

1. An apparatus comprising:A transmitter circuit coupled to a termination resistor, the transmitter circuit configured to generate a plurality of link pulses;
a driver circuit coupled to the transmitter circuit and configured to control a dynamic range of the link pulses; and
a transformer configured to couple the termination resistor via a transmission medium to a far-end transceiver,
wherein the driver circuit is configured to control the dynamic range of the link pulses by providing complementary digital input signals to the transmitter circuit, and wherein the complementary digital input signals include ramp sections.

US Pat. No. 10,250,904

APPARATUS AND METHOD FOR OVERLAPPED MOTION COMPENSATION FOR VIDEO CODING

Avago Technologies Intern...

1. A method of video processing, comprising:receiving, by a processor, a current prediction block and a plurality of adjacent prediction blocks including an above prediction block, a below prediction block, a left prediction block, and a right prediction block; and
blending, by the processor, the current prediction block and the plurality of adjacent prediction blocks, including:
combining first weighted samples from a top subset of rows of the current prediction block with corresponding second weighted samples from a top subset of rows of the above prediction block to form a first portion of an intermediate prediction block;
combining third weighted samples from a bottom subset of rows of the current prediction block with corresponding fourth weighted samples from a bottom subset of rows of the below prediction block to form a second portion of the intermediate prediction block;
combining fifth weighted samples from a left subset of columns of the intermediate prediction block with corresponding sixth weighted samples from a left subset of columns of the left prediction block to form a first portion of a blended prediction block; and
combining seventh weighted samples from a right subset of columns of the intermediate prediction block with corresponding eighth weighted samples from a right subset of columns of the right prediction block to form a second portion of the blended prediction block,
wherein the combining the first weighted samples with the second weighted samples is performed simultaneously with the combining the third weighted samples with the fourth weighted samples, and
wherein the combining the fifth weighted samples with the sixth weighted samples is performed simultaneously with the combining the seventh weighted samples with the eighth weighted samples.

US Pat. No. 10,236,354

THREE DIMENSIONAL MONOLITHIC LDMOS TRANSISTOR

AVAGO TECHNOLOGIES INTERN...

1. A transistor comprising:a first level comprising:
a first source/drain structure;
a second source/drain structure;
a gate structure at least partially disposed in a space defined between inner ends of the first source/drain structure and the second source/drain structure;
a first shallow trench isolation structure disposed below an outer end of the first source/drain structure; and
a second shallow trench isolation structure disposed at least partially below an outer end of the second source/drain structure;
a second level vertically above the first level, comprising a voltage attenuation structure;
a first conductive connection connected to the first source/drain structure and being at least partially above the first shallow trench isolation structure, the first conductive connection extending through the first level and the second level; and
a second conductive connection connected to the second source/drain structure and being at least partially above the second shallow trench isolation structure, the second conductive connection extending through the first level and the second level;
wherein the voltage attenuation structure is located entirely between the first conductive connection and the second conductive connection in a cross sectional view.

US Pat. No. 10,229,072

SYSTEM AND METHOD FOR DESPREADER MEMORY MANAGEMENT

AVAGO TECHNOLOGIES INTERN...

1. A communication channel, comprising:a despreader memory block configured to de-interleave incoming memory slices associated with a plurality of data sectors;
a buffer configured to receive the de-interleaved memory slices and further configured to transfer the de-interleaved memory slices of the plurality of data sectors sequentially to a decoder for further processing; and
a resource management controller configured to monitor a memory availability of the despreader memory block and a memory availability of the buffer and further configured to prevent the despreader memory block from transferring the de-interleaved memory slices of a data sector to the buffer when the memory availability of the buffer is below a threshold buffer availability and the memory availability of the despreader memory block is above a threshold despreader availability.

US Pat. No. 10,218,498

EFFICIENT HASH TABLE KEY STORAGE

Avago Technologies Intern...

1. A system, comprising:a hash function processor implemented using a hardware device, the hash function processor configured to process a key-data item pair for storage by:
performing a hash function to map an input key to a hash value, wherein the hash function includes a division function that results in a quotient value and a remainder value having a first portion and a second portion, and the hash value is equal to the first portion of the remainder value that results from the division function, and
generating a compressed key that includes information for mapping the hash value to the input key, wherein the information includes the quotient value and the second portion of the remainder value, and does not include the first portion of the remainder value; and
a hash table, implemented in memory, configured to store the compressed key and a data item associated with the input key in a bucket of the hash table identified by the hash value,
wherein the stored compressed key and data item are used in a packet forwarding application or a packet routing application.

US Pat. No. 10,305,708

METHODS, SYSTEMS, AND APPARATUS FOR THE IMPROVEMENT OF SIGNAL INTEGRITY OVER AN UNBALANCED DIFFERENTIAL CHANNEL

Avago Technologies Intern...

1. A driver circuit for improving signal integrity for a differential pair of signals having a first signal and a second signal, the driver circuit comprising:a signal level detector configured to detect a change in signal level of the first signal or the second signal;
pulse shaping logic configured to:
generate a delayed and scaled version of the first signal based on the detected change in signal level; and
combine the first signal and the delayed and scaled version of the first signal to generate a first shaped signal; and
an edge-rate control filter configured to adjust at least one of a rise time or a fall time of the first shaped signal to generate a first adjusted signal, wherein the first adjusted signal provides a portion of a balanced differential pair of signals.

US Pat. No. 10,305,515

SYSTEM AND METHOD FOR ENCODING USING MULTIPLE LINEAR FEEDBACK SHIFT REGISTERS

Avago Technologies Intern...

1. A method for encoding a first stream of bits, comprising:splitting with one or more switches, a first input stream of bits to multiple second streams;
encoding, in parallel and by using multiple linear feedback shift register (LSFR) circuits, the multiple second streams to provide third streams, wherein each second stream of the multiple second streams is encoded using an LFSR circuit of the multiple LFSR circuits; wherein the encoding comprises feeding the multiple second streams to the multiple LFSR circuits;
merging, with memory cells, the third streams to provide a fourth stream; wherein the fourth stream is stored in the multiple LFSR circuits; and
encoding the fourth stream to provide a fifth stream; wherein the encoding of the fourth stream comprises concatenating the multiple LFSR circuits while bypassing feedback circuits of some of the multiple LFSR circuits; and
shifting the fourth stream through the multiple LFSR circuits.

US Pat. No. 10,305,821

FACILITATING HOT-SWAPPABLE SWITCH FABRIC CARDS

AVAGO TECHNOLOGIES INTERN...

1. A switching system, comprising:a processor;
a plurality of line cards, wherein a respective line card includes one or more ports;
one or more switch fabric cards configured to facilitate switching among the line cards; and
a memory storing instructions that when executed by the processor cause the switching system to perform a method, the method comprising:
identifying a hot-swapping event of a first switch fabric card based on a data structure indicating the one or more switch fabric cards, wherein the hot-swapping event indicates insertion or removal of the first switch fabric card while the switching system remains in an operational state;
determining an event type associated with the hot-swapping event;
managing the first switch fabric card based on the determined event type; and
in response to the event type indicating the first switch fabric card being inaccessible, the managing the first switch fabric card further includes disabling the first switch fabric card, thereby ensuring that the first switch fabric card does not participate in an internal switching of the switching system, and determining whether the first switch fabric card becomes accessible within a predetermined number of attempts.

US Pat. No. 10,282,116

METHOD AND SYSTEM FOR HARDWARE ACCELERATED CACHE FLUSH

Avago Technologies Intern...

1. A method for performing a cache flush, the method comprising:allocating one or more Internal Scatter Gather Lists (ISGLs) for the cache flush;
populating the one or more ISGLs with Cache Segment Identifiers (CSIDs) and corresponding Buffer Segment Identifiers (BSIDs) of each strip that is identified as dirty, of a skip-type Internal Scatter Gather Element (ISGE), or of a missing arm-type ISGE;
allocating a flush Local Message Identifier (LMID) as a message to be used in connection with processing the cache flush;
populating the flush LMID with an identifier of the one or more ISGLs; and
transferring the flush LMID to a cache manager module to enable the cache manager module to execute the cache flush based on information contained in the flush LMID.

US Pat. No. 10,284,168

BULK ACOUSTIC WAVE RESONATOR

Avago Technologies Intern...

1. A bulk acoustic wave (BAW) resonator, comprising:an acoustic reflector disposed in a substrate;
a lower electrode disposed over the acoustic reflector;
a piezoelectric layer disposed over the lower electrode; and
an upper electrode disposed over the piezoelectric layer, a contacting overlap of the lower electrode, the piezoelectric layer, and the upper electrode over the acoustic reflector comprising an active area of the BAW resonator, wherein an opening exists in and extends completely through the upper electrode in a region of the BAW resonator susceptible to unacceptable overheating, the region being located where self-heating is the greatest, and having an areal dimension, wherein the opening is located in the region, and has the areal dimension.

US Pat. No. 10,284,173

ACOUSTIC RESONATOR DEVICE WITH AT LEAST ONE AIR-RING AND FRAME

Avago Technologies Intern...

1. An acoustic resonator device, comprising:a bottom electrode disposed on a substrate over an air cavity, the bottom electrode having a central region and a peripheral region;
a piezoelectric layer disposed on the bottom electrode;
a top electrode disposed on the piezoelectric layer, an overlap between the top electrode, the piezoelectric layer and the bottom electrode over the air cavity defining a main membrane region;
a first metal frame disposed on a bottom surface of the bottom electrode, the first metal frame having a first side and a second side, the first side being opposite the second side, the first metal frame having a thickness that ranges from about 10% to about 75% of a thickness of the bottom electrode in the central region of the bottom electrode, wherein the first side of the first metal frame extends laterally from a location that is outside of the main membrane region to a location that is within the main membrane region; and
at least one air-bridge disposed between the top electrode and the piezoelectric layer.

US Pat. No. 10,285,227

PROGRAMMABLE AND ADAPTABLE INTERFACE FOR DIMMING LIGHT EMITTING DIODES

AVAGO TECHNOLOGIES INTERN...

1. A device comprising:circuitry configured to
receive and decode an input signal, the decoded input signal having a first modulation format,
generate a light emitting diode (LED) dimming signal by converting the first modulation format to a second modulation format,
add a dither signal to the decoded input signal to form a dithered input signal;
modulate the dithered input signal to have the first modulation format, and
over-sample the dithered input signal at an over-sampling ratio that is programmable with respect to the input signal, the input signal being a digital signal corresponding to an intensity level of an LED.

US Pat. No. 10,283,699

HALL-EFFECT SENSOR ISOLATOR

Avago Technologies Intern...

1. A coupler, comprising:a first conductor configured to induce a magnetic field as electrical current flows through the first conductor;
a second conductor that is electrically isolated from the first conductor;
a semiconductor connected to a first surface of the second conductor, wherein the semiconductor comprises a top surface with a magnetic sensor provided thereon;
an isolation material sandwiched between the top surface of the semiconductor and the first conductor, the isolation material providing an electrical isolation between the first conductor and both the semiconductor as well as the second conductor;
an encapsulant that substantially encapsulates the semiconductor, a piece of the first conductor, a piece of the second conductor, and the isolation material; and
one or more bondwires connected between one or more bond pads of the semiconductor and the second conductor.

US Pat. No. 10,284,469

PROGRESSIVE MAC ADDRESS LEARNING

AVAGO TECHNOLOGIES INTERN...

1. A switch, comprising:a storage device configured to store one or more forwarding entries;
a content-addressable memory, which is separate from the storage device, configured to store a forwarding data structure; and
management circuitry configured to:
in response to determining that a destination MAC address of a data frame is not present in the forwarding data structure, identify the destination MAC address and a corresponding egress port in the storage device;
create a forwarding entry comprising the destination MAC address in the forwarding data structure; and
determine an egress port for the data frame based on the forwarding entry in the forwarding data structure.

US Pat. No. 10,284,991

METHODS FOR DETERMINING RELATIVE LOCATIONS OF WIRELESS LOUDSPEAKERS

Avago Technologies Intern...

9. A method comprising:receiving a responsive wireless timing transmission signal that includes timing information from each of a plurality of wireless loudspeakers arranged in an acoustic space;
determining a location in the acoustic space of one or more of the plurality of wireless loudspeakers based on the timing information;
generating and providing a location indication, the location indication being indicative of whether a loudspeaker of the plurality of wireless loudspeakers is properly located based on the location; and
providing wireless audio transmission signals to the plurality of wireless loudspeakers.

US Pat. No. 10,285,258

SYSTEMS AND METHODS FOR PROVIDING ELECTROMAGNETIC INTERFERENCE (EMI) COMPARTMENT SHIELDING FOR COMPONENTS DISPOSED INSIDE OF SYSTEM ELECTRONIC PACKAGES

Avago Technologies Intern...

1. A system module package comprising:a substrate;
circuitry comprising at least one electrical component mounted over a surface of the substrate;
a common electrical ground structure disposed on the surface of the substrate, the common electrical ground structure comprising at least first and second portions, wherein the first portion and the second portion of the common electrical ground structure provide a unitary elongated conductive strip; and
a compartment electromagnetic interference (EMI) shield, the compartment EMI shield surrounding and extending over at least one portion of the circuitry, the compartment EMI shield comprising at least a first set of bond wires, each wire having a first length that extends over and is spaced apart from said at least one electrical component and having second and third lengths that extend from opposite ends of the respective first length and connect to the common electrical ground structure, the first lengths being substantially parallel to one another and being substantially parallel to a plane in which the surface of the substrate lies, the compartment EMI shield attenuating a frequency or frequency range of interest.

US Pat. No. 10,282,211

OPERATING SYSTEM SOFTWARE INSTALL AND BOOT UP FROM A STORAGE AREA NETWORK DEVICE

Avago Technologies Intern...

1. A method for a computer network including a storage area network (SAN) device, the method comprising:mapping at least one boot logical unit (LUN) of the SAN device to a communication port of at least one converged network adapter (CNA) belonging to at least one computer server;
sending one or more operating system (OS) images from a provisioning server to a converged network switch, the converge network switch supporting a plurality of computer communication protocols through a plurality of communication ports;
sending the one or more operating system images from the converged network switch to the communication port of the at least one converged network adapter using a first network communication protocol;
downloading at least one of the one or more operating system software images through the converged network switch to the communication port of the at least one converged network adapter using the first network communication protocol;
writing the at least one operating system image into the at least one boot logical unit of the SAN device through the communication port of the at least one CNA using a second communication protocol; and
booting the at least one computer server with the at least one operating system image stored in the at least one boot logical unit of the SAN device.

US Pat. No. 10,282,301

METHOD AND SYSTEM FOR HARDWARE ACCELERATED READ-AHEAD CACHING

Avago Technologies Intern...

1. A method for read-ahead caching, the method comprising:determining that a read-ahead operation is to be performed in response to receiving a host Input/Output (I/O) command;
in response to determining that the read-ahead operation is to be performed, allocating a new Local Message Identifier (LMID) for the read-ahead operation;
sending a buffer allocation request to a buffer manager module, the buffer allocation request containing parameters associated with the read-ahead operation;
causing the buffer manager module to allocate at least one Internal Scatter Gather List (ISGL) and Buffer Section Identifier (BSID) in accordance with the parameters contained in the buffer allocation request;
enabling the allocated ISGL and BSID to be used in connection with the read-ahead operation;
transferring information describing the new LMID to a cache manager module; and
enabling the cache manager module to perform a hash search using a row or strip number and identification information available in the new LMID.

US Pat. No. 10,276,490

ISOLATION DEVICES WITH FARADAY SHIELDS

AVAGO TECHNOLOGIES INTERN...

1. An isolation device comprising:a first integrated circuit in electrical communication with first circuitry, wherein the first integrated circuit includes a first light emitter portion configured to emit a first optical signal based on first electrical signals received at the first integrated circuit from the first circuitry;
a second integrated circuit in electrical communication with second circuitry, wherein the second integrated circuit includes a first light-sensitive area configured to convert the first optical signal into second electrical signals for communication to the second circuitry;
an isolation material between the first integrated circuit and the second integrated circuit to electrically isolate the first integrated circuit from the second integrated circuit and to pass the first optical signal from the first light emitter portion to the first light-sensitive area; and
a first shield to shield the first light emitter portion from electromagnetic radiation.

US Pat. No. 10,264,666

METHOD OF PROVIDING COMPARTMENT EMI SHIELDS ON PRINTED CIRCUIT BOARD USING A VACUUM

Avago Technologies Intern...

1. A method of forming an internal electromagnetic interference (EMI) shield in a mold cap formed over a printed circuit board (PCB), the method comprising:forming a trench in the mold cap, the trench extending continuously from a first edge of the mold cap to a second edge of the mold cap, wherein the trench defines a trench pattern corresponding to desired locations of the internal EMI shield;
sealing an elastomeric pad on a top surface of the mold cap to form a channel, the channel comprising at least the trench formed in the mold cap; and
filling the channel with a conductive epoxy using a pressure differential to draw the conductive epoxy from a dispenser, connected to the first edge of the mold cap, through the channel to the second edge of the mold cap.

US Pat. No. 10,263,649

FULLY INTEGRATED POWER AMPLIFIER EMPLOYING TRANSFORMER COMBINER WITH ENHANCED BACK-OFF EFFICIENCY

Avago Technologies Intern...

1. A power amplifier (PA) circuit, the circuit comprising:a first PA configured to amplify a first radio frequency (RF) signal, wherein the first PA is a fixed-bias PA;
a second PA configured to amplify a second RF signal, wherein the second PA is a variable-bias PA;
a first variable capacitor coupled between differential output nodes of the first PA; and
a second variable capacitor coupled between differential output nodes of the second PA,
wherein the first and the second RF signals are differential signals that are created by splitting a differential input RF signal, and wherein the differential output nodes of the first PA and the second PA are coupled via respective first and second transformers to a load, and capacitance values associated with the first and second variable capacitors are configured to be dynamically adjustable based on an amplitude of the RF signal to achieve a desired power efficiency at an output power level.

US Pat. No. 10,263,652

MULTI-CHIP MILLIMETER-WAVE INTERFACE

Avago Technologies Intern...

1. A millimeter-wave (MMW) transceiver system, the system comprising:a transceiver chip configured to generate and to receive and/or transmit signals; and
an interface configured to communicate the signals including modulated MMW signals, a control signal and a DC supply voltage between the transceiver chip and one or more active antenna modules to avoid local oscillator (LO) generation,
wherein:
the transceiver chip comprises baseband circuitry, up and down conversion mixers, and
RF front-end circuitry, and
an active antenna module of the one or more active antenna modules is configured to receive a first modulated MMW signal from the interface for transmission via a plurality of antennas and to receive a second modulated MMW signal from the plurality of antennas for transmission through the interface to the transceiver chip, and wherein the active antenna module comprises a master millimeter-wave integrated circuit (MMIC) followed by a plurality of slave antenna modules directly in parallel to each other, the MMIC is configured to provide control signals for at least some of the plurality of slave antenna modules, and wherein the interface is scalable and allows the master MMIC to be used in multiple hierarchical tiled modes.

US Pat. No. 10,262,992

THREE DIMENSIONAL LVDMOS TRANSISTOR STRUCTURES

AVAGO TECHNOLOGIES INTERN...

1. A semiconductor device comprising:a first stack of device components comprising
a transistor switching element having a channel, a source in contact with the channel, a drain in contact with the channel; and a gate structure at least partially disposed in a space defined between and separating the source and the drain;
a source connection to the source, and
a drain connection to the drain; and
a second stack of device components disposed underneath the first stack at a lower level than the first stack, and comprising:
a semiconductor substrate of a doping type the same as the drain; and
a pair of electrical contacts spaced apart on the semiconductor substrate and contacting a conduction path in the semiconductor substrate extending between the pair of electrical contacts,
wherein said drain connection is connected to one of the pair of electrical contacts.

US Pat. No. 10,262,994

FINFET LDMOS DEVICES WITH ADDITIONAL DYNAMIC CONTROL

Avago Technologies Intern...

1. A FinFET semiconductor device comprising:a semiconductor body including a source region of a first type, and a drain region of a second type, and a drain-region shallow trench isolation (STI) disposed in the drain region;
a plurality of fins attached to the semiconductor body and extending across the semiconductor body;
a channel gate structure disposed over a section of said plurality of fins;
a supplemental gate disposed on the drain-region STI.

US Pat. No. 10,263,601

TUNABLE BULK ACOUSTIC RESONATOR DEVICE WITH IMPROVED INSERTION LOSS

Avago Technologies Intern...

1. A tunable bulk acoustic wave (BAW) filter device for filtering a radio frequency (RF) signal having a carrier frequency in an allocated channel of a predetermined frequency band having a plurality of predetermined channels, the BAW filter device comprising:a first voltage source that selectively provides a non-zero direct current (DC) bias voltage based on a location of the allocated channel within the predetermined frequency band; and
a plurality of BAW resonators configured to provide a passband of the BAW filter device, each BAW resonator having a corresponding resonance frequency and comprising:
a bottom electrode disposed over a substrate and an acoustic reflector;
a piezoelectric layer disposed over the bottom electrode and having a corresponding resonance frequency; and
a top electrode disposed over the piezoelectric layer, the top electrode being electrically connected to the first voltage source via a first resistor,
wherein the first voltage source is controlled to apply the non-zero DC bias voltage to the top electrode of each BAW resonator, when the location of the allocated channel is near an upper corner or a lower corner of the predetermined frequency band, the upper corner corresponding to a high frequency edge of the predetermined frequency band and the lower corner corresponding to a low frequency edge of the predetermined frequency band, and
wherein the resonance frequency of each BAW resonator is shifted in response to the non-zero DC bias voltage toward a center of the predetermined frequency band, shifting a minimum insertion loss portion of the passband of the BAW filter device toward the allocated channel.

US Pat. No. 10,244,414

SIGNAL FIELD (SIG) DESIGN WITHIN OFDM/OFDMA WIRELESS COMMUNICATIONS

AVAGO TECHNOLOGIES INTERN...

1. A wireless communication device comprising:a communication interface; and
processing circuitry that is coupled to the communication interface, wherein at least one of the communication interface or the processing circuitry configured to:
generate a first signal that includes a field that specifies an acceptable interference level for concurrent communication for use by a first other wireless communication device to determine whether a transmission from the first other wireless communication device to a second other wireless communication device acceptably or unacceptably interferes with another transmission from the wireless communication device, wherein the field specifies a first acceptable interference level for first concurrent communication within a first sub-band of a communication channel and a second acceptable interference level for second concurrent communication within a second sub-band of the communication channel;
transmit the first signal to a third other wireless communication device via the communication channel, wherein a second signal is transmitted from the first other wireless communication device to the second other wireless communication device via the communication channel and during transmission of at least a portion of the first signal from the wireless communication device when the first other wireless communication device determines that interference from the second signal is less than or equal to the acceptable interference level for concurrent communication; and
transmit the first signal to the third other wireless communication device, wherein the first other wireless communication device is permitted to transmit the second signal to the second other wireless communication device within the first sub-band of the communication channel during the transmission of the at least a portion of the first signal from the wireless communication device when the first other wireless communication device determines that interference from the second signal is less than or equal to the acceptable interference level for concurrent communication, and wherein a fourth other wireless communication device is permitted to transmit a third signal to a fifth other wireless communication device within the second sub-band of the communication channel during the transmission of the at least a portion of the first signal from the wireless communication device when the fourth other wireless communication device determines that interference from the second signal is less than or equal to the acceptable interference level for concurrent communication.

US Pat. No. 10,243,407

SYSTEM, DEVICE, AND METHOD FOR CONTROLLING A POWER INVERTER

AVAGO TECHNOLOGIES INTERN...

1. A device comprising:circuitry configured to
determine a load impedance for at least one power conversion device,
control a dead-time of one or more switching stages of the at least one power conversion device based on the load impedance,
control a tunable matching network based on the load impedance and the dead-time of the one or more switching stages, and
modify the dead-time of the one or more switching stages including a plurality of switches based on a comparator output indicating an amount of body diode conduction of the plurality of switches.

US Pat. No. 10,244,469

POWER MANAGEMENT FOR PERSONAL BSS CONTROL POINT (PCP)

AVAGO TECHNOLOGIES INTERN...

1. A wireless communication device comprising:a communication interface; and
processing circuitry that is coupled to the communication interface, wherein at least one of the communication interface or the processing circuitry configured to:
generate an announcement frame that includes information specifying a start time and a periodicity corresponding to a low power or sleep mode of the wireless communication device;
transmit the announcement frame to a plurality of other wireless communication devices;
enter into the low power or sleep mode after receiving a plurality of responses respectively from the plurality of other wireless communication devices within a predetermined period of time, wherein the plurality of responses includes one respective response from each of the plurality of other wireless communication devices, are in response to the announcement frame, and are received by the wireless communication device within the predetermined period of time, wherein the start time is delayed by an extended time period when fewer than the plurality of responses are received respectively from the plurality of other wireless communication devices within the predetermined period of time; and
enter into the low power or sleep mode after receiving the plurality of responses respectively from the plurality of other wireless communication devices within another predetermined period of time that includes the predetermined period of time and the extended time period, wherein the plurality of responses includes one respective response from each of the plurality of other wireless communication devices.

US Pat. No. 10,243,518

SINGLE INPUT, DUAL OUTPUT PATH LOW-NOISE AMPLIFIER

Avago Technologies Intern...

1. A front-end receiver comprising:a low-noise amplifier (LNA) configured to provide an amplified signal;
a first output path of the LNA comprising a first isolation circuit and a first impedance circuit;
a second output path of the LNA comprising a second isolation circuit and a second impedance circuit; and
a circuit component coupled to both the first output path of the LNA and the second output path of the LNA and configured to receive the amplified signal from the LNA through one of the first output path of the LNA and the second output path of the LNA based on a current power mode of the front-end receiver,
wherein the second impedance circuit provides a larger voltage gain for the LNA than the first impedance circuit, and
wherein the second impedance circuit has a higher impedance than the first impedance circuit.

US Pat. No. 10,243,822

SYSTEM AND METHOD FOR END-TO-END BEACONING

AVAGO TECHNOLOGIES INTERN...

1. A method comprising:receiving, at a receipt port of a first device, a beacon command to activate a light generating device physically located at and associated with the receipt port of the first device, the light generating device emitting light that is visible to a user;
issuing, from the receipt port by the first device, an acceptance reply accepting the beacon command; and
activating, by the first device, a light generating device physically located at and associated with the receipt port of the first device in response to receiving the beacon command.

US Pat. No. 10,241,788

METHOD AND SYSTEM FOR DETERMINING INSTRUCTION CONFLICT STATES FOR ISSUANCE OF MEMORY INSTRUCTIONS IN A VLIW PROCESSOR

Avago Technologies Intern...

1. A method, comprising:receiving, by a first queue, and storing therein, an instruction of a first plurality of instructions that updates a first physical resource of a plurality of physical resources, the instruction being not ready to execute;
transferring the instruction from the first queue to a second queue in response to the instruction becoming ready to execute;
comparing, by a state-selection circuit, the instruction against an older instruction of a second plurality of instructions, the second plurality of instructions being stored in the second queue and the older instruction requiring a second physical resource of the plurality of physical resources;
setting a status in the second queue, by the state-selection circuit, to indicate whether (i) the instruction can be issued independent of the older instruction; or (ii) the instruction must be issued, if at all, after the older instruction is issued;
issuing one of the instruction and the older instruction from the second queue;
identifying resource-independent instructions from instructions stored in the second queue; and
in response to the identifying, issuing resource-independent instructions that update more of the plurality of physical resources before resource-independent instructions that update fewer of the plurality of physical resources.

US Pat. No. 10,237,090

RULE-BASED NETWORK IDENTIFIER MAPPING

AVAGO TECHNOLOGIES INTERN...

1. A switch, comprising:a storage device;
rule management circuitry configured to store, in the storage device, a first mapping that maps a virtual network identifier of a tunnel to a rule for classifying traffic, wherein the virtual network identifier identifies a virtualized network associated with the tunnel;
network identifier circuitry configured to:
generate, for a virtualization manager of a virtual machine, a control packet comprising a representation of the first mapping for a respective local end device; and
obtain, from a notification packet from the virtualization manger, a second mapping that maps the virtual network identifier to an identifier of the virtual machine and an identifier of the tunnel.

US Pat. No. 10,229,888

SYSTEMS AND METHODS FOR PROVIDING ELECTROMAGNETIC INTERFERENCE (EMI) COMPARTMENT SHIELDING FOR COMPONENTS DISPOSED INSIDE OF SYSTEM ELECTRONIC PACKAGES

Avago Technologies Intern...

1. A system module package comprising:a substrate;
a first compartment having a first set of electrical components disposed on the substrate;
a second compartment having a second set of electrical components disposed on the substrate; and
a plurality of substantially vertical conductive structures, each of the plurality of substantially vertical conductive structures is arranged within a separating pitch so as to attenuate an electromagnetic interference of a frequency range of interest, wherein the plurality of substantially vertical conductive structures are arranged along a boundary forming a fence separating the second compartment from the first compartment, and substantially attenuate the electromagnetic interference of the frequency range of interest generated from the first compartment traveling through the plurality of substantially vertical conductive structures to the second compartment and vice versa, wherein each of the plurality of substantially vertical conductive structures comprises a wire bond having a first end electrical connected to the substrate, and a second end having a tail portion substantially thinner than other portions of the wire bond.

US Pat. No. 10,218,990

VIDEO ENCODING FOR SOCIAL MEDIA

Avago Technologies Intern...

1. A device for encoding and sharing media for social networks, comprising:a sharing engine comprising a buffer, and a network interface installed within a housing of the device;
wherein the sharing engine is configured to:
receive a first portion of a media stream, and
write a subset of the received first portion of the media stream to the buffer; and
wherein the network interface is configured to, responsive to receipt of a capture command:
retrieve a second portion of the media stream from the buffer of the sharing engine,
trim the beginning and end of the retrieved second portion of the media stream to independently decodable frames, and
transmit the retrieved second portion of the media stream via a network to a second device.

US Pat. No. 10,216,688

SYSTEMS AND METHODS FOR ACCURATE TRANSFER MARGIN COMMUNICATION

AVAGO TECHNOLOGIES INTERN...

1. A data processing system, the system comprising:a sampling latch operable to sample a received serial data input and provide a corresponding serial data output;
a first duration margin determination circuit operable to: define a first contour of a data signal eye corresponding to the serial data output over a first number of bit periods, and determine a first margin characteristic based upon the first contour;
a second duration margin determination circuit operable to: define a second contour of the data signal eye corresponding to the serial data output over a second number of bit periods, and determine a second margin characteristic based upon the second contour;
a margin normalization circuit operable to calculate a normalized value based upon a combination of the first margin characteristic and the second margin characteristic; and
a transmission circuit operable to transmit an output to a requesting device, wherein the output transmitted by the transmission circuit is indicative of the normalized value.

US Pat. No. 10,216,567

DIRECT PARITY ENCODER

Avago Technologies Intern...

1. An encoder for wireless local area networking (WLAN) communication, comprising:a processor configured to divide a generator matrix into a first portion and a second portion, the second portion of the generator matrix including an array of sub-blocks, the array of sub-blocks arranged in rows and columns, each row including M number of sub-blocks and each column including J number of sub-blocks, wherein M and J are integers, each sub-block including Z number of rows and Z number of columns, wherein Z is an integer, a sub-block of the array of sub-blocks including (i) a first set of elements circularly shifted from an identity matrix by a first amount, and (ii) a second set of elements circularly shifted from the identity matrix by a second amount; and
parity bit generation circuitry coupled to the processor, the parity bit generation circuitry configured to generate parity bits according to the array of sub-blocks, the parity bit generation circuitry including:
bit permutation circuitry,
Z number of XOR devices coupled to the bit permutation circuitry,
M sets of storage registers, each set of the M sets of storage registers including Z number of storage registers, each of the Z number of storage registers coupled to a corresponding XOR device of the Z number of XOR devices, and
control circuitry coupled to the bit permutation circuitry and the M sets of storage registers, the control circuitry configured to:
cause the bit permutation circuitry to generate Z number of first bits according to Z number of input bits and the first amount, the Z number of first bits equal to the Z number of input bits when circularly shifted according to the first amount, each of the Z number of first bits provided as input to a corresponding XOR device of the Z number of XOR devices,
cause each storage register of a first set of the M sets of storage registers to store an output of the corresponding XOR device of the Z number of XOR devices,
cause the bit permutation circuitry to generate Z number of second bits according to the Z number of input bits and the second amount, the Z number of second bits equal to the Z number of input bits when circularly shifted according to the second amount, and
cause the Z number of XOR devices to perform bit-wise XOR operations on the stored Z number of outputs from the first set of the M sets of storage registers and the generated Z number of second bits from the bit permutation circuitry, to provide a portion of the parity bits.

US Pat. No. 10,299,155

INFORMATION EXCHANGE FOR CELLULAR NON-CELLULAR INTERWORKING

AVAGO TECHNOLOGIES INTERN...

1. A method comprising:establishing an X3 connection with an access point of a non-cellular local-area communication system;
obtaining, via the X3 connection at a radio access network level of a cellular wide-area communication system, access point information about at the access point in at least one of an interface setup operation or an interface reset operation for the X3 interface triggered by an event at the access point, the triggering event includes at least a change of a working channel of the access point, a change in a working bandwidth of the access point, and a change in a working system version of the access point; and
performing, at the radio access network level of the cellular wide-area communication system, traffic offloading management for a terminal being served in the cellular wide-area communication system to enable offloading of terminal-related traffic from the cellular wide-area communication system to the non-cellular local-area communication system on the basis of the obtained access point information.

US Pat. No. 10,291,434

MULTI-DESTINATION PACKET FORWARDING FOR A MULTI-HOMED DEVICE IN A VIRTUAL NETWORK

AVAGO TECHNOLOGIES INTERN...

1. A switch, comprising:network-virtualization circuitry configured to establish a forwarding segment for an end device, wherein the end device is multi-homed with the switch and a second switch participating in the forwarding segment, and wherein the forwarding segment is identified by a segment identifier persistent in the switch and the second switch;
update circuitry configured to construct, for the second switch, a first route update message comprising an indicator value for the forwarding segment;
acknowledgment circuitry configured to determine the indictor value in a second route update message from the second switch as an acknowledgment for the first route update message; and
election circuitry configured to, in response to determining the acknowledgment from a respective switch participating in the forwarding segment, initiate a designated forwarder election for the forwarding segment, wherein the designated forwarder is responsible for forwarding multi-destination traffic in the forwarding segment, wherein
the election circuitry initiates the designated forwarder election for the forwarding segment as a result of a new forwarding segment being deployed or an occurrence of a recovery event of the switch or second switch, and the end device transmits data on the forwarding segment after the designated forwarder election is completed.

US Pat. No. 10,291,754

APPARATUS, SYSTEM, AND METHOD FOR AUTO-NEGOTIATION

Avago Technologies Intern...

1. An active cable that comprises:a first connection component;
first electrical circuitry;
second electrical circuitry;
the first electrical circuitry being communicatively coupled to the first connection component, and configured to:
receive auto-negotiation information according to an auto-negotiation protocol standard encoded in first physical layer signaling from an initiating device;
generate a data packet that includes the auto-negotiation information in a format that is not in accordance with the auto-negotiation protocol standard; and
transmit the data packet via the first connection component;
the second electrical circuitry being communicatively coupled to the first connection component, and configured to:
receive the data packet from the first electrical circuitry via the first connection component;
encode the auto-negotiation information included in the data packet according to the auto-negotiation protocol standard for second physical layer signaling; and
transmit the second physical layer signaling to a receiving device;
a second connection component communicatively coupled to the initiating device and communicatively coupled to the first electrical circuitry; and
a third connection component communicatively coupled to the second electrical circuitry and communicatively coupled to the receiving device;
wherein the second connection component and the third connection component comprise M and N connection components, respectively, where N is different from M,
wherein the first electrical circuitry is configured to transmit the data packet at a first rate that is at least M-times a second rate for transmission of the first physical layer signaling, and
wherein the second electrical circuitry is configured to transmit the second physical layer signaling at a third rate that is equal to the first rate divided by N.

US Pat. No. 10,263,678

PREAMBLE DESIGN WITHIN WIRELESS COMMUNICATIONS

AVAGO TECHNOLOGIES INTERN...

1. A wireless communication device comprising:a communication interface; and
processing circuitry that is coupled to the communication interface, wherein at least one of the communication interface or the processing circuitry configured to:
receive an orthogonal frequency division multiplexing (OFDM) packet from another wireless communication device, wherein the OFDM packet includes a preamble that includes a first signal field (SIG) followed by a second SIG that is followed by a third SIG;
process the OFDM packet to classify a packet format of the OFDM packet among a plurality of OFDM packet formats including a first OFDM packet format, a second OFDM packet format, and a third OFDM packet format, wherein, based on:
the first OFDM packet format, the first SIG includes first content;
the second OFDM packet format, the second SIG has a first phase that is 90 degrees phase shifted from a second phase of the third SIG; and
the second OFDM packet format and the third OFDM packet format, the first SIG includes second content; and
process the OFDM packet based on the packet format that is classified.

US Pat. No. 10,263,587

PACKAGED RESONATOR WITH POLYMERIC AIR CAVITY PACKAGE

Avago Technologies Intern...

1. A packaged resonator, comprising:a substrate;
an acoustic stack disposed over the substrate;
a first polymer layer disposed over the substrate, surrounding the acoustic stack, and providing a first air gap above the acoustic stack;
a second polymer layer disposed over the acoustic stack and above the first air gap; and
at least three release holes disposed between an air cavity under the acoustic stack, and the first polymer layer, wherein the first polymer layer covers each of the at least three release holes.

US Pat. No. 10,313,091

ROBUST ELECTROMAGNETIC COMPATIBILITY PERFORMANCE FOR IN-VEHICLE ETHERNET PHYS UTILIZING TIME DIVISION DUPLEXING

Avago Technologies Intern...

1. An Ethernet transceiver within a first electronic domain of an in-vehicle network, comprising:a media access control (MAC) controller; and
a physical layer (PHY) device comprising:
a transmit buffer configured to buffer a plurality of frames of first media independent interface (MII) data received from the MAC controller over a first path and to cause the MAC controller to pause transmission of the plurality of frames of first MII data to the transmit buffer before being filled;
a receive buffer configured to buffer a plurality of frames of second MII data for transmission to the MAC controller over a second path;
a transmitter configured to convert a first frame from among the plurality of frames of first MII data buffered by the transmit buffer from a first-bit packet stream to a second-bit packet stream, the second-bit packet stream having fewer bits than the first-bit packet stream, to map the second-bit packet stream to a plurality of first bit streams, and to multiplex the plurality of first bit streams into a first single stream to form a transmit signal for transmission over a single pair of cables to a second Ethernet transceiver within a second electronic domain of the in-vehicle network during a first transmit time of a time-division duplex (TDD) frame;
a receiver configured to receive a receive signal received over the single pair of cables from the second Ethernet transceiver during a second transmit time of the TDD frame, to demultiplex the receive signal from a second single stream to a plurality of second bit streams, to map the plurality of second bit streams to a third-bit packet stream, and to convert the third-bit packet stream to a fourth-bit packet stream, the third-bit packet stream having fewer bits than the fourth-bit packet stream, to provide a second frame from among the second plurality of frames of MII data to the receive buffer for buffering; and
a time-division duplex (TDD) controller configured to control when the transmitter starts transmitting the transmit signal during the first transmit time of the TDD frame over the single pair of cables to the second Ethernet transceiver and to adapt a duration of the first transmit time of the TDD frame in which the transmitter transmits the transmit signal over the single pair of cables to the second Ethernet transceiver.

US Pat. No. 10,313,104

SYSTEM AND METHOD FOR CONTROLLING THE IMPACT OF PERIODIC JITTER CAUSED BY NON-IDEAL PHASE INTERPOLATORS

Avago Technologies Intern...

15. A system for controlling periodic jitter arising from a phase interpolator (PI), comprising:a receiver configured to receive incoming data;
a fractional-N phase-locked loop (PLL) configured to receive a reference clock, wherein N is an integer; and
measurement circuitry configured to measure a parts per million (PPM) offset between the incoming data and the reference clock, of a first PI,
wherein the fractional-N PLL is further configured to restrict jitter arising from the first PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the first PI, wherein the jitter arising from the first PI comprises jitter arising from non-linear phases of the first PI.

US Pat. No. 10,312,365

LATERALLY DIFFUSED MOSFET ON FULLY DEPLETED SOI HAVING LOW ON-RESISTANCE

Avago Technologies Intern...

1. A semiconductor device, comprising:a substrate;
a first semiconductor layer disposed on the substrate;
a buried oxide layer disposed on the first semiconductor layer,
a second semiconductor layer disposed on the buried oxide layer, wherein the second semiconductor layer comprises a first gate region, a drain region, and a source region, and wherein the first gate region is positioned between the source and the drain regions;
a first shallow trench isolation disposed between the drain region at a first end of the second semiconductor layer and the first semiconductor layer, wherein the first shallow trench isolation is extended from the second semiconductor layer to the first semiconductor layer;
a second gate region disposed on the first semiconductor layer away from the second semiconductor layer and between the first shallow trench isolation and a second shallow trench isolation; and
a gate node coupled to the first gate region and the second gate region and configured to apply a gate voltage to the first gate region and the second gate region.

US Pat. No. 10,313,932

MECHANISM TO UPDATE THE CSG CELL ACCESS CHECK UPON PLMN CHANGE AT HANDOVER

Avago Technologies Intern...

1. A method comprising:performing a location or registration area update, by a user equipment, triggered in response to receiving an indication of a network change in signaling of a handover received from a second device, and
during the location or registration area update procedure,
comparing a received public land mobile network (PLMN) of a target cell or a list of equivalent PLMNs (EPLMNs) of the target cell to a PLMN of a serving cell or a list of EPLMNs of the serving cell, and
based on the comparison, determining whether a private cell is allowed for the user equipment,
wherein the user equipment refrains from reporting private cells after the handover until the location or registration area update procedure is complete.

US Pat. No. 10,313,054

LOW DENSITY PARITY CHECK (LDPC) CODES FOR COMMUNICATION DEVICES AND SYSTEMS

AVAGO TECHNOLOGIES INTERN...

1. A communication device comprising:a communication interface; and
processing circuitry that is coupled to the communication interface, wherein at least one of the communication interface or the processing circuitry configured to:
puncture a sub-matrix column of a preliminary low density parity check (LDPC) matrix that has a variable node degree that is greater than other sub-matrix columns of the preliminary LDPC matrix to generate an LDPC matrix that includes a plurality of sub-matrices that are 81×81 size sub-matrices arranged as a left hand side matrix and a right hand side matrix, wherein the right hand side matrix includes all-zero-valued sub-matrices except for a plurality of CSI (Cyclic Shifted Identity) sub-matrices located on a main diagonal of the right hand side matrix and another diagonal that is adjacently located to right of the main diagonal of the right hand side matrix and two other CSI sub-matrices located on a left hand most column of the right hand side matrix, and wherein variable node degree of columns of the left hand side matrix is 3;
encode information using an LDPC code that is a rate 7/8 LDPC code to generate an LDPC coded signal, wherein the LDPC code is characterized by the LDPC matrix; and
transmit the LDPC coded signal to another communication device via a communication channel to be processed by the another communication device to decode the LDPC coded signal to generate estimates of the information encoded therein.

US Pat. No. 10,295,373

MAGNETIC ABSOLUTE POSITION SENSOR HAVING A WIEGAND MODULE

Avago Technologies Intern...

1. Position sensor for determining the number of repeating courses of movement of an object and the precise position of the object in relation to a reference position, wherein the position sensor comprises:a Wiegand module, which is composed of a Wiegand wire having a coil, which surrounds the Wiegand wire;
a magnetic temporary storage, which is in addition to the Wiegand module;
a first sensor element;
a processing electronics circuit, which is configured to evaluate or to determine an output signal that is output from the first sensor element and an information that is stored in the magnetic temporary storage; and
a permanent magnet arrangement, which is movable relatively to the Wiegand module in one direction and in a direction that is opposite to said one direction, wherein the permanent magnet arrangement is configured to be arranged at the object such that the permanent magnet arrangement performs the repeating courses of movement together with the object; wherein:
upon movement of the permanent magnet arrangement in said one direction, the coil of the Wiegand module produces a voltage impulse, if a north pole or a south pole of the permanent magnet arrangement is located at a first position, and upon movement of the permanent magnet arrangement in said opposite direction, the coil of the Wiegand module produces the voltage impulse, if the north pole or the south pole of the permanent magnet arrangement is located at a second position that is different from the first position;
upon movement of the permanent magnet arrangement, the magnetic poles of the permanent magnet arrangement come to pass the magnetic temporary storage such that the magnetic temporary storage stores information, which indicates whether the north pole or the south pole of the permanent magnet arrangement has lastly passed the magnetic temporary storage;
in an autonomous mode, in which the position sensor is not supplied with outside energy, the processing electronic circuit is supplied with energy, which is provided by the Wiegand module;
the processing electronic circuit is configured to, after the determining of the voltage impulse, which is output by the Wiegand module, determine a value, which corresponds to the number of repeating courses of movement of the permanent magnet arrangement, by the evaluation of the output signal of the first sensor element;
in a non-autonomous mode, in which the position sensor is supplied with outside energy, the processing electronic circuit is further configured to continuously receive position information about the precise position of the permanent magnet arrangement in relation to the reference position, to combine the position information with the determined value, and to output the combined information, by the evaluation of the output signal of either the first sensor element or of a second sensor element that is different from the first sensor element; and
if the outside energy supply is re-established again after a discontinuation, the combining of the position information with the determined value takes into consideration the information, which is stored in the magnetic temporary storage.

US Pat. No. 10,318,765

PROTECTING CRITICAL DATA STRUCTURES IN AN EMBEDDED HYPERVISOR SYSTEM

Avago Technologies Intern...

1. A system on a chip, comprising:a security processor configured to receive access rights associated with an operating system from an off-chip memory;
a hypervisor configured to:
install the access rights associated with the operating system on a processor executing on the chip, wherein the access rights associated with the operating system determine access of the operating system to at least one resource, and
execute hypervisor specific code as the operating system executes on the processor, the hypervisor specific code including configuring access rights within a hypervisor page table of the off-chip memory according to the access rights of the operating system;
an on-chip memory configured to store the hypervisor, the hypervisor being associated with a digital signature when stored in the on-chip memory;
a transaction filter configured to prevent, using the access rights of the operating system, unauthorized access of the operating system to the least one resource in real-time as the operating system executes on the processor;
a write blocker configured to utilize the digital signature to differentiate between the hypervisor and other components executing on the chip to ensure only the hypervisor modifies the hypervisor page table as the operating system executes on the processor;
a background hardware checker configured to verify a code digest value associated with the hypervisor specific code matches the digital signature associated with the hypervisor as the operating system executes on the processor to verify the hypervisor is executing the hypervisor specific code; and
an instruction checker configured to verify the hypervisor executes the hypervisor specific code from a specific range of addresses in the on-chip memory.

US Pat. No. 10,320,678

MAPPING CONTROL PROTOCOL TIME ONTO A PHYSICAL LAYER

AVAGO TECHNOLOGIES INTERN...

1. A method comprising:in a communication device comprising a Media Access Control (MAC) layer and a Physical (PHY) layer:
determining a MAC layer data rate of the MAC layer;
determining a PHY layer data rate at which communication will occur over a physical communication medium; and
at the MAC layer:
determining a rate difference between the MAC layer data rate and the PHY layer data rate;
communicating a data flow from the MAC layer to the PHY layer, the data flow comprising data for communication over the physical communication medium, including inserting IDLE characters into the data flow responsive to the rate difference; and
in the PHY layer, replacing, prior to forward error correction encoding, selected IDLE characters among those inserted into the data flow at the MAC layer with data bytes of the data flow received from the MAC layer to adapt to the rate difference between the MAC layer and the PHY layer.