US Pat. No. 9,318,457

METHODS OF FABRICATING SEMICONDUCTOR CHIP SOLDER STRUCTURES

ATI Technologies ULC, Ma...

1. An apparatus, comprising:
a semiconductor chip including a layer of copper, the copper layer having a first preselected volume; and
a layer of a metallic material on the copper layer, the layer of metallic material having a second preselected volume, the
first and second metallic materials operable to convert into a solder bump upon reflow with a desired ratio of copper to the
layer of metallic material, the desired ratio being based on the first preselected volume and the second preselected volume.

US Pat. No. 9,385,055

STACKED SEMICONDUCTOR CHIPS WITH THERMAL MANAGEMENT

ATI Technologies ULC, Ma...

1. A method of assembling a semiconductor chip device, comprising:
placing an interposer on a first semiconductor chip, the interposer including a lower surface seated on the first semiconductor
chip and an upper surface adapted to thermally contact a heat spreader, the upper surface including a first aperture defining
a seating surface facing away from the lower surface; and

placing a second semiconductor chip in the first aperture.

US Pat. No. 9,430,391

MANAGING COHERENT MEMORY BETWEEN AN ACCELERATED PROCESSING DEVICE AND A CENTRAL PROCESSING UNIT

Advanced Micro Devices, I...

1. A method of managing a coherent memory between a first processor and a second processor comprising:
monitoring a flag register to determine whether data stored in a system coherent memory is available for processing, wherein
the flag register notifies the second processor that data is available for processing in the system coherent memory;

monitoring and recording the addresses of cache lines used by a first processor using a probe filter;
receiving an address for a data that is available to be processed using the second processor;
comparing the address for the data to the addresses recorded with the probe filter to determine whether the data has been
exported by the first processor;

in response to determining that data was not exported by the first processor, partitioning a second processor memory into
a local memory and a coherent memory, wherein a portion of the coherent memory containing the recorded cache lines is stored
in the local memory; and

in response to determining that data was exported by the first processor, sending a probe to the first processor to retrieve
the data exported by the first processor.

US Pat. No. 9,304,772

ORDERING THREAD WAVEFRONTS INSTRUCTION OPERATIONS BASED ON WAVEFRONT PRIORITY, OPERATION COUNTER, AND ORDERING SCHEME

Advanced Micro Devices, I...

1. An apparatus for the ordered execution in computer parallel processing, comprising:
a scoreboard structure configured to store a plurality of wavefronts each including a plurality of ordered operations in response
to ordered operation requests from one or more processing units; and

a controller configured to control an order of operations in the plurality of wavefronts supporting an ordering scheme including
operations from more than one of the wavefronts, wherein the controller comprises multiple counters such that a counter is
associated with a wavefront and identifies the priority of the wavefront and a counter is associated with each operation in
a wavefront and identifies the priority of each operation in a wavefront and the order of operations in the plurality of wavefronts
is based on the multiple counters and the ordering scheme.

US Pat. No. 9,135,017

CONFIGURABLE SHADER ALU UNITS

ATI Technologies ULC, Ma...

1. A shader unit to process an input data stream, the shader unit comprising:
a sequencer associated with the shader unit to provide control instructions based on an amount of ALU bandwidth desired for
a number of groups of ALUs; and

a plurality of processing integrated circuit chips coupled to the sequencer, each processing integrated circuit chip includes
a plurality of arithmetic logic units, wherein each processing integrated circuit chip includes at least one defective arithmetic
logic unit, further wherein each of the plurality of arithmetic logic units of each of the plurality of processing circuit
chips is dynamically configurable to be enabled or disabled according to the control instructions provided by the sequencer
instructions based on an amount of ALU bandwidth desired, thereby increasing a yield for processing integrated circuit chips
wherein the sequencer dynamically configures a number of enabled arithmetic logic units and provides a same sized ALU instruction
to each of the enabled ALUs.

US Pat. No. 9,270,969

3D VIDEO PROCESSING

ATI TECHNOLOGIES ULC, Ma...

1. A method for performing 2D image to 3D image conversion, comprising:
extracting a 2D image input data source into a left 3D image and right 3D image;
calculating a motion vector for each of the left 3D image and right 3D image;
performing frame rate conversion on the left 3D image and the right 3D image, using the respective calculated motion vectors,
to produce motion compensated left and right 3D images; and

reordering the left and right 3D images and the motion compensated left and right 3D images for display by a display device.

US Pat. No. 9,263,364

THERMAL INTERFACE MATERIAL WITH SUPPORT STRUCTURE

Advanced Micro Devices, I...

1. An apparatus, comprising:
a first semiconductor chip having a first footprint;
a second semiconductor chip mounted on the first semiconductor chip and having a second footprint smaller than the first footprint
and a side facing away from the first semiconductor chip; and

a thermal interface material layer on the side of the second semiconductor chip, the thermal interface material layer containing
a support structure having a third footprint larger than the second footprint.

US Pat. No. 9,116,809

MEMORY HEAPS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM

ATI Technologies ULC, Ma...

1. A method of allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor
configured for unified operation with a second processor, comprising:
receiving a memory operation from a processor;
mapping the memory operation to one of a plurality of memory heaps,
wherein the memory operation references a shared memory address (SMA) in a shared memory, and
wherein the mapping includes mapping the memory operation to one of a plurality of memory heaps based on the SMA, wherein
the mapping produces a mapping result; and

providing the mapping result to the processor.

US Pat. No. 9,176,795

GRAPHICS PROCESSING DISPATCH FROM USER MODE

Advanced Micro Devices, I...

1. A method comprising:
selecting a user mode application for scheduling by a scheduler; and
dispatching commands, in a user mode, directly to an accelerated processing device from a work queue allocated to the user
mode application by a kernel mode driver, the work queue being accessible to the user mode application and the accelerated
processing device without transitioning to a kernel mode.

US Pat. No. 9,209,106

THERMAL MANAGEMENT CIRCUIT BOARD FOR STACKED SEMICONDUCTOR CHIP DEVICE

ATI Technologies ULC, Ma...

20. An apparatus, comprising:
a first circuit board having a plurality of thermally conductive vias;
a second circuit board mounted on the first circuit board over and in thermal contact with the thermally conductive vias,
the second circuit board including first side facing the first circuit board and a second and opposite side; and

a first semiconductor chip coupled on the first side of the second circuit board over and in thermal contact with the thermally
conductive vias, at least a portion of the first semiconductor chip extending beyond the first side of the second circuit
board.

US Pat. No. 9,213,381

VOLTAGE REGULATOR DYNAMICALLY DETERMINING WHETHER REQUESTED POWER TRANSITION CAN BE SUPPORTED

ATI Technologies ULC, Ma...

1. A method of controlling circuit voltage comprising:
requesting, by an electrical component, permission for an electrical component block to enter a state that requires a different
current draw relative to a current state of the electrical component block;

receiving permission to enter the requested state, the permission coming from a voltage regulator for the electrical component,
wherein the voltage regulator dynamically determines whether the requested state can be supported;

transmitting a permission signal to the electrical component when the requested state can be supported; and
entering, by the electrical component block, the state that requires a different current draw responsive to receiving the
requested permission.

US Pat. No. 9,317,082

CONTROLLING OPERATION OF TEMPERATURE SENSORS

Advanced Micro Devices, I...

1. An integrated circuit, comprising:
a first temperature sensor configured to determine a first temperature of the integrated circuit and a subsequent, second
temperature of the integrated circuit; and

wherein the integrated circuit is configured to reduce power consumption of the first temperature sensor based, at least in
part, on a decrease in temperature indicated by the second temperature being less than the first temperature, and wherein
the integrated circuit is configured to reduce the power consumption of the first temperature sensor without varying power
consumption of at least a portion of the integrated circuit, wherein the integrated circuit is configured to reduce the power
consumption of the first temperature sensor by disabling the first temperature sensor for an interval selected based on the
second temperature.

US Pat. No. 9,286,046

METHOD AND APPARATUS FOR DISTRIBUTED OPERATING SYSTEM IMAGE DEPLOYMENT

Advanced Micro Devices, I...

1. A method for distributing an operating system, comprising:
partitioning a storage device of a device into a first partition and a second partition;
installing a first operating system into the first partition of the storage device, wherein the device transmits registration
information to a central repository of images connected to the device with one or more networks after the first operating
system is installed onto the first partition to obtain an image of a second operating system;

obtaining the image of the second operating system, the image including at least a second operating system pre-configured
for operation with the device; and

installing, using the first operating system, the image of the second operating system to the second partition of the storage
device.

US Pat. No. 9,071,787

DISPLAY INFORMATION FEEDBACK

Advanced Micro Devices, I...

1. A multimedia entertainment system comprising:
a communication link;
a video source coupled to the communication link and configured to produce a video signal and provide the video signal to
the communication link; and

a video display coupled to the communication link and configured to receive the video signal from the video source via the
communication link, to provide dynamic display characteristic information indicative of a display capability of the video
display to the video source via the communication link, and to automatically provide updated dynamic display characteristic
information to the video source in response to a change in the dynamic display characteristic information;

wherein the dynamic display characteristic information includes an indication of a color gamut of the video display;
wherein the video source is configured to receive the dynamic display characteristic information, determine whether to adapt
processing of the video signal according to the dynamic display characteristic information including a mapping of colors outside
the color gamut of the video display to colors within the color gamut of the display in response to receiving the color gamut
information, and to produce the video signal as a function of the dynamic display characteristic information; and

wherein the video display is configured to display a video image in accordance with the video signal provided by the video
source.

US Pat. No. 9,176,794

GRAPHICS COMPUTE PROCESS SCHEDULING

Advanced Micro Devices, I...

1. A method comprising:
allocating a work queue by a kernel mode driver to a user mode application in response to a request by the application, wherein
the work queue is directly accessible by an accelerated processing device;

selecting the application for scheduling in the accelerated processing device by an accelerated processing device scheduler,
wherein at least non-dependent instructions are processed autonomously from a processor scheduler; and

allocating non-pageable memory allocations upon access by the accelerated processing device to support at least page fault
handling by the accelerated processing device.

US Pat. No. 9,153,198

METHOD AND DEVICE FOR LINK OVER-TRAINING

ATI Technologies ULC, Ma...

1. A method of training a data link including:
obtaining signal noise by one of changing clock distribution methods associated with the data link; removing a first noise
filter from cascaded phase-locked loops associated with the data link, increasing a level of a spread spectrum setting associated
with the data link, and other noise sources related to routing, isolation, and tying to a power or ground rail;

selectively and intentionally adding the obtained noise to a signal; and
using the signal with the noise added thereto to train a data link.

US Pat. No. 9,310,863

MULTI-PURPOSE POWER CONTROLLER AND METHOD

ATI Technologies ULC, Ma...

1. A device for implementing internal and external power management and logic management, the device comprising:
an embedded system power controller;
an application specific standard product (ASSP) initializing block coupled to the controller via a chip;
a template that sets designs for the power management and logic management of the controller and initializing block, wherein
at least one power template balances block resources between internal and external power management.

US Pat. No. 9,088,276

PRE-EMPHASIS CONTROL CIRCUIT FOR ADJUSTING THE MAGNITUDE OF A SIGNAL OVER A PERIOD ACCORDING TO A FRACTION OF A BIT-TIME

ATI TECHNOLOGIES ULC, Ma...

1. A circuit comprising:
a re-timing circuit configured to retime a first signal by a predetermined amount to produce a second signal; and
a summing circuit configured to add the second signal to the first signal to produce a third signal, wherein the third signal
is logically equivalent to the first signal, and wherein the third signal is pre-emphasized to a first magnitude for a duration
equal to a first portion of a bit-time of the first signal, and wherein the third signal is not pre-emphasized and has a second
magnitude for a duration equal to a second portion of the bit-time of the first signal, wherein the bit-time of the first
signal comprises a duration of approximately one full period of a first clock signal, and wherein the first and second portions
of the bit-time of the first signal are each less than one full period of the clock signal, and wherein a sum of the first
and second portions of the bit-time is equal to one full period of the clock signal.

US Pat. No. 9,055,306

PARALLEL DECODING METHOD AND SYSTEM FOR HIGHLY COMPRESSED DATA

ATI Technologies ULC, Ma...

1. A video data decoding method comprising:
pre-processing control maps generated from encoded video data that was encoded according to a pre-defined format, wherein
pre-processing comprises generating a plurality of intermediate control maps for a respective plurality of frame processing
operations containing control information, the control information including an indication of which macro blocks or portions
of macro blocks of a frame may be processed in parallel in respective frame processing operations; and

decoding the encoded video data on a frame basis using an interprediction algorithm, intraprediction algorithm or both interprediction
and intraprediction algorithms, wherein decoding comprises parallel processing of macro blocks or portions of macro blocks
in respective frame processing operations using the intermediate control maps to improve the performance of a plurality of
processing pipelines whereby one intermediate control map can control frame processing for an interprediction algorithm where
one set of macro blocks of a frame are identified for parallel processing and another intermediate control map can control
frame processing for an intraprediction algorithm where an entirely different set of macro blocks of the frame are identified
for parallel processing, wherein the plurality of intermediate control maps and at least one buffer are generated by running
a pre-shader on the control maps based on at least one predetermined value that is set to indicate whether particular macro
blocks are interprediction, intraprediction or both interprediction and intraprediction, the at least on buffer containing
a subset of control information indicating which of the macro blocks are interprediction, intraprediction or both interprediction
and intraprediction.

US Pat. No. 10,104,758

HEAT SINK WITH CONFIGURABLE GROUNDING

ATI Technologies ULC, Ma...

1. An apparatus, comprising:a heat sink;
plural contact pins coupled to the heat sink;
at least one fastener to secure the heat sink to a circuit board, the circuit board having plural ground conductors; and
whereby each of the contact pins is selectively movable relative to the heat sink independently of the at least one fastener to contact or not contact one of the ground conductors without forcing the heat sink toward the circuit board to control a number and location of ground points of the heat sink.

US Pat. No. 9,437,561

SEMICONDUCTOR CHIP WITH REDUNDANT THRU-SILICON-VIAS

Advanced Micro Devices, I...

1. A method of manufacturing, comprising:
forming a first plurality of conductive vias in a layer of a first semiconductor chip, the first plurality of conductive vias
including first ends and second ends;

forming conductive via extensions on each of the first ends of the first conductive vias; and
forming a first conductor pad in ohmic contact with the conductive via extensions.

US Pat. No. 9,152,571

ALL INVALIDATE APPROACH FOR MEMORY MANAGEMENT UNITS

ATI Technologies ULC, Ma...

1. A method comprising:
caching information in a cache for a memory management unit of a computer system, wherein the management unit comprises a
cache and non-cached registers;

detecting an abnormal event;
storing control and configuration information of the memory management unit in the non-cached registers; and
in response to a single command generated in response to the abnormal event, clearing at least a subset of the information
in the cache in response to the detecting the abnormal event, and preserving the control and configuration information in
the non-cached registers,

wherein the caching, storing, detecting and clearing are performed by one or more digital devices.

US Pat. No. 9,076,265

SYSTEM AND METHOD FOR PERFORMING DEPTH TESTING AT TOP AND BOTTOM OF GRAPHICS PIPELINE

ATI TECHNOLOGIES ULC, Ma...

1. A computer implemented graphics processing method for processing graphics data to produce electronic data for use in generating
an electronic image, the method comprising:
performing an initial depth test on a pixel sample without updating a depth value of the pixel sample on a condition that
the initial depth test is satisfied;

processing the pixel sample using shader hardware and software of a graphics processing pipeline if the initial depth test
is determined to be satisfied;

performing a subsequent depth test on the processed pixel sample after performing the initial depth test and the processing;
and

writing the depth value of the pixel sample to storage after performing the subsequent depth test if the subsequent depth
test is determined to be satisfied.

US Pat. No. 9,372,635

METHODS AND APPARATUS FOR DIVIDING SECONDARY STORAGE

ATI Technologies ULC, Ma...

12. An apparatus for restricting access by one or more processors to a storage area of a secondary storage unit, comprising:
an independent programmable storage controller logic, interposed between the one or more processors and the secondary storage
unit, operative to:

divide the storage area of the secondary storage unit into at least a first area and a second area; and
control usage of at least the first area and the second area as at least two virtual secondary storage units such that the
one or more processors access the at least two virtual secondary storage units as if accessing at least two physical secondary
storage units, each area containing at least one region of which an access permission setting is modifiable, by selecting
one of the at least two virtual secondary storage units as an active virtual secondary storage unit to provide the one or
more processors access to the active virtual secondary storage unit based on a secondary storage unit configuration.

US Pat. No. 9,244,872

CONFIGURABLE COMMUNICATIONS CONTROLLER

ATI TECHNOLOGIES ULC, Ma...

1. A communications controller comprising:
a physical interface having a port for connection to a communication medium, and an output, and operating according to a protocol
to provide a sequence of data bits with a first number of data bits to said output;

a deserializer having an input coupled to said output of said physical interface, and an output for providing, in response
to said sequence of data bits, a first plurality of data bits at a first rate in a low frequency mode until said first number
of data bits is provided and a second plurality of data bits at a second rate in a low latency mode until said first number
of data bits is provided, wherein said first plurality is greater in number than said second plurality, and said second rate
is higher than said first rate; and

a receive block having an input coupled to said output of said deserializer, and an output.

US Pat. No. 9,152,201

METHOD AND SYSTEM FOR DISPLAY OUTPUT STUTTER

ATI Technologies ULC, Ma...

1. A method of reducing power consumption for transferring video frames of a video stream over a data transfer interface between
a first device and a second device, the method comprising:
determining, by the second device, whether (a) the video stream is completed or terminated or (b) the data transfer interface
is disabled after a notification included in a video frame of the video stream;

receiving, over the data transfer interface, the notification from the first device that the data transfer interface will
be temporarily disabled upon completion or termination of a first video frame of the video stream; and

in response to the second device determining that the data transfer interface is disabled after the notification, (a) freezing
a display while displaying a second video frame and (b) enabling the data transfer interface before transferring a third video
frame.

US Pat. No. 9,142,520

METHODS OF FABRICATING SEMICONDUCTOR CHIP SOLDER STRUCTURES

ATI Technologies ULC, Ma...

1. A method of manufacturing, comprising: depositing a layer of copper on a semiconductor chip, the copper layer having a
first preselected volume; depositing a layer of a metallic material on the copper layer, the layer of metallic material having
a second preselected volume; and reflowing the copper layer and the layer of metallic material to convert them into a solder
bump with a desired ratio of copper to the layer of metallic material, the desired ratio being based on the first preselected
volume and the second preselected volume.

US Pat. No. 9,064,468

DISPLAYING COMPRESSED SUPERTILE IMAGES

ATI Technologies ULC, Ma...

1. A method for use in a system for displaying an image frame from a plurality of compressed supertile frames, comprising:
creating, using a control processor, one or more compressed supertile frames from a plurality of tiles read from a system
memory, wherein the tile frames correspond to an image to be generated;

processing, using a plurality of graphics processing units, the one or more compressed supertile frames, wherein each graphics
processing unit processes the one or more compressed supertile frames allocated to the graphics processing unit;

reading, using a supertile frame combiner, the compressed supertile frames and expanding each of the compressed supertile
frames to generate an expanded supertile frame, wherein the expanded supertile frame is generated at each graphics processing
unit and the expanded supertile frame is created for each compressed supertile frame and contains blank tiles for one or more
tiles for each tile not allocated to the graphics processing unit;

combining, using the supertile frame combiner, the expanded supertile frames to generate an image frame; and
displaying the generated image frame on a display.

US Pat. No. 9,239,793

MECHANISM FOR USING A GPU CONTROLLER FOR PRELOADING CACHES

ATI TECHNOLOGIES ULC, Ma...

1. A system including an accelerated processing device electrically coupled to a cache, the system comprising:
a controller configured to:
receive a command message, the command message including instructions to be accessed during processing by the accelerated
processing device, the instructions comprising data related to a portion of a plurality of portions of memory;

interpret the command message by determining whether or not the command message includes a preloading instruction to preload,
to the cache, the portion of the memory to be accessed;

on the condition that the command message is determined to include the preloading instruction, determine to preload, to the
cache, at least the portion of the memory;

on the condition that command message is determined to not include the preloading instruction, compare the instructions of
the command message to cache access history and determine to preload, to the cache, at least the portion of the memory based
on a comparison of the command message to the cache access history;

determine which of the plurality of portions of the memory to preload to the cache based on at least one of: (i) locality
reference information and (ii) policy information of the cache;

create a fetch message including data related to contents of the portion; and
output the fetch message to the cache.

US Pat. No. 9,118,928

METHOD AND SYSTEM FOR PROVIDING SINGLE VIEW VIDEO SIGNAL BASED ON A MULTIVIEW VIDEO CODING (MVC) SIGNAL STREAM

ATI Technologies ULC, Ma...

1. A method, carried out by a video system for providing a single view video signal based on a multiview video coding (MVC)
signal stream, comprising:
processing a MVC signal stream using image information from more than one of a plurality of decoded video signals that represent
a plurality of spatially related views; and

providing a processed video signal representing one of said plurality of spatially related views based on said processing
said MVC signal stream using said image information from said more than one of said plurality of decoded video signals that
represent said plurality of spatially related views.

US Pat. No. 9,060,162

PROVIDING MULTIPLE VIEWER PREFERENCES ON A DISPLAY DEVICE

ATI Technologies ULC, Ma...

1. A system for providing viewer preferences on a display device, the system comprising:
a storage medium for storing preset viewer preferences, each preference being categorized based on one of a plurality of viewers;
a processor that accesses the storage medium and acquires the stored preset viewer preferences for a given one of the plurality
of viewers;

comparing the given one's viewer preferences against at least another one's viewer preferences; and
a display device that provides content to the given one viewer in accordance with the given one viewer's preferences using
at least one optical element, wherein the display device toggles between standard and multiview modes based on the comparison.

US Pat. No. 9,414,078

METHOD FOR RATE CONTROL FOR CONSTANT-BIT-RATE-FINITE-BUFFER-SIZE VIDEO ENCODER

ATI Technologies ULC, Ma...

1. A method for rate control for a constant-bit-rate finite-buffer-size video encoder comprising:
calculating a group-of-pictures-level prediction for a number of bits encoded for a group of pictures;
calculating a picture-level prediction for a number of bits encoded for a picture;
calculating a pixel-block-level prediction for a number of bits encoded for a pixel block; and
using the group-of-pictures-level prediction, the picture-level prediction, and the pixel-block-level prediction to adjust
a quantizer scale factor to provide the rate control for the video encoder.

US Pat. No. 9,201,682

VIRTUALIZED DEVICE RESET

ATI Technologies ULC, Ma...

1. A method for resetting a function in a hardware-based virtualization system, comprising:
switching out of a first function into a second function, wherein the first function is one of a physical function and a virtual
function and the second function is one of a physical function and virtual function;

detecting a malfunction in the first function during the switching; and
resetting the first function without resetting the second function,
wherein the switching, detecting and the resetting are performed by a hypervisor.

US Pat. No. 9,418,450

TEXTURE COMPRESSION TECHNIQUES

ATI Technologies ULC, Ma...

1. A texture compression method, comprising:
(a) splitting an original texture having a plurality of pixels into original blocks of pixels;
for each of the original blocks of pixels:
(b) identifying a partition from a predefined set of partitions, the partitions having one or more disjoint and variably shaped
subsets of pixels whose union is the original block of pixels;

(c) subdividing the original block of pixels into one or more subsets according to the identified partition;
(d) independently compressing each subset to form a compressed texture block; and
(e) decompressing the compressed texture block to obtain an approximation of the original block of pixels;
(f) comparing the original block of pixels to the approximation of the original block of pixels to obtain a quality parameter
for the identified partition;

(g) repeating steps (b) through (f) for each partition in the predefined set of partitions to obtain the quality parameter
for each partition;

(h) choosing a final partition for the original block of pixels that yields an optimal quality parameter;
(i) subdividing the original block of pixels into one or more final subsets according to the final partition; and
(j) independently compressing each final subset to form a compressed texture block.

US Pat. No. 9,286,904

ADJUSTING A DATA RATE OF A DIGITAL AUDIO STREAM BASED ON DYNAMICALLY DETERMINED AUDIO PLAYBACK SYSTEM CAPABILITIES

ATI Technologies ULC, Ma...

1. A method of adjusting a data rate of a digital audio stream, the method comprising:
sampling sound generated, from a digital audio stream, by an audio playback system;
ascertaining, from the sampled sound, a sound quality of the generated sound; and
based at least in part on the ascertained sound quality of the generated sound, reducing the data rate of the digital audio
stream by performing either one or both of:

reducing a sampling rate of the digital audio stream to a reduced sampling rate; and
reducing a number of bits per sample of the digital audio stream to a reduced number of bits per sample.

US Pat. No. 9,497,439

APPARATUS AND METHOD FOR FAST MULTIVIEW VIDEO CODING

ATI Technologies ULC, Ma...

1. A method for multiview video coding, the method comprising:
downscaling two views of a multiview video;
determining a shift between the two downscaled views;
encoding one of the two views using the shift;
upscaling the shift; identifying co-located areas of the two views using the upscaled shift; comparing pixels of the co-located
areas in a first comparison, shifting one of the co-located areas by a predetermined shift amount; comparing pixels of the
other of the co-located areas to pixels of the shifted co-located area in a second comparison; and refining the upscaled shift
with the predetermined shift amount if the second comparison results in less residue than the first comparison.

US Pat. No. 9,344,671

SYSTEM AND METHOD FOR ARTIFACT REMOVAL

ATI Technologies ULC, Ma...

1. A method of providing signal improvement including:
receiving a first media signal in a first format, the first format resulting from having undergone at least one permutation
from an original format, the first format being different than the original format;

obtaining a second signal indicative of error within the first media signal, the second signal being in a second format, the
second format being different than the first format;

applying a second permutation to the second signal to place the second signal in the first format; and
combining the first media signal in the first format and the second signal in the first format to produce an error-corrected
first signal in the first format.

US Pat. No. 10,114,761

SHARING TRANSLATION LOOKASIDE BUFFER RESOURCES FOR DIFFERENT TRAFFIC CLASSES

ATI TECHNOLOGIES ULC., M...

1. A method for accessing data stored in memory, the method comprising:selecting a translation request specifying a virtual memory address and having, out of a plurality of translation requests ready for translation, a highest quality-of-service level for which an available finite state machine (“FSM”) exists in a translation lookaside buffer (“TLB”) work queue;
storing the selected translation request with the available FSM;
processing the translation request to obtain a physical memory address; and
outputting the physical memory address to access the data stored in the memory.

US Pat. No. 9,124,855

METHOD AND APPARATUS FOR VIDEO STREAM PROCESSING

ATI Technologies ULC, Ma...

1. A method for video stream processing, implemented in a monitor scaler chip (MSC), the method comprising:
receiving the video stream from an external source via a capture port;
determining whether the video stream includes copy protected content; and
routing the video stream to either a first location or a second location based upon the external source supporting copy protection
and the determination of the presence of copy protected content;

wherein the video stream is routed directly and exclusively to the first location if the external source supports copy protection
and the video stream is determined to include copy protected content;

wherein the video stream is routed directly and exclusively to the first location if the external source does not support
copy protection and the video stream is determined to include copy protected content;

wherein the video stream is routed to the second location if the external source supports copy protection and the video stream
is determined to not include copy protected content;

wherein the video stream is routed to the second location if the external source does not support copy protection and the
video stream is determined to not include copy protected content; and

wherein the first location is a display and the second location includes a graphics processing unit (GPU).

US Pat. No. 9,105,081

PROTECTION FILTER FOR IMAGE AND VIDEO PROCESSING

ATI Technologies ULC, Ma...

1. A noise reduction filter comprising:
a temporal noise reduction filtering block receiving an input value for a pixel location in a current image frame from an
input signal and computing a filtered value based on said input value and values for said pixel location in previous image
frames; and

a protection block comprising:
an input for receiving said filtered value, and a group of values for pixels proximate said pixel location in said current
image frame; and

control logic for computing a minimum bounding value and a maximum bounding value from said group of values, excluding said
filtered value and for clipping said filtered value to form an output value that is range bounded within the range of said
minimum bounding value and said maximum bounding value.

US Pat. No. 9,117,036

FAST EXIT FROM LOW-POWER STATE FOR BUS PROTOCOL COMPATIBLE DEVICE

ATI TECHNOLOGIES ULC, Ma...

1. A bus protocol compatible device, comprising:
a transmitter having a first mode for providing a reference clock signal to an output, and a second mode for providing a training
sequence to said output; and

a power state controller for placing said transmitter in said first mode for a first period of time in response to a change
in a link state, and in said second mode after an expiration of said first period of time.

US Pat. No. 9,473,678

METHOD, APPARATUS AND MACHINE-READABLE MEDIUM FOR APPORTIONING VIDEO PROCESSING BETWEEN A VIDEO SOURCE DEVICE AND A VIDEO SINK DEVICE

ATI Technologies ULC, Ma...

22. A non-transitory machine-readable medium storing instructions that, when processed, cause the creation of a circuit capable
of:
based upon an indication of video processing algorithms of which a video sink device is capable and an indication of video
processing algorithms of which a video source device is capable:

identifying a set of video processing algorithms for achieving desired video processing; and
classifying the video processing algorithms of said set into a first subset of video processing algorithms for performance
by said video sink device and a second subset of video processing algorithms for performance by said video source device;
and

sending at least one command to said video sink device, said at least one command identifying the first subset of video processing
algorithms to be effected at said video sink,

wherein said circuit comprises said video source device.

US Pat. No. 9,432,690

APPARATUS AND METHOD FOR VIDEO PROCESSING

ATI Technologies ULC, Ma...

1. A method of video processing comprising:
determining, for a search block within a first frame, a relative location of a corresponding block in a second frame with
respect to the search block based on comparative searching at a predetermined granularity to produce a motion vector for the
search block with a first precision;

determining correlation values with respect to the search block for the corresponding block and for at least one block defined
at a relative location of less than the predetermined granularity with respect to the corresponding block; and

determining a refined motion vector for the search block with a second higher precision based on the relative location of
the block having a selected correlation value that is selected from among the correlation values with respect to the corresponding
block and the at least one block,

wherein the at least one block is produced by up-sampling the corresponding block at less than the predetermined granularity
in different directions relative to the corresponding block to generate an alternating pattern of corresponding block pixels
and oversampled pixels.

US Pat. No. 9,098,932

GRAPHICS PROCESSING LOGIC WITH VARIABLE ARITHMETIC LOGIC UNIT CONTROL AND METHOD THEREFOR

ATI Technologies ULC, Ma...

1. Graphics data processing logic comprising:
a plurality of rows of parallel arithmetic logic units that operate as an array of arithmetic logic units on both pixel data
and vertex data, wherein the array of ALUs include a plurality of sets of parallel ALUs, each set of said sets comprising
at least two parallel ALUs, and including an ALU load arbiter operatively coupled to each of the sets of parallel ALUs and
operative to determine the order in which each set of parallel ALUs gets loaded with pixel data or vertex data;

a programmable storage element containing first data to adapt at last one of an ALU of the ALUs in the plurality of rows of
parallel ALUs to perform either pixel data processing or vertex data processing; and

parallel ALU pixel data and vertex data packing logic operatively coupled to the array of arithmetic logic units and to the
programmable storage element and operative to pack pixel and vertex data only for specified arithmetic logic units of the
array of arithmetic logic units based on the first data.

US Pat. No. 9,070,198

METHODS AND SYSTEMS TO REDUCE DISPLAY ARTIFACTS WHEN CHANGING DISPLAY CLOCK RATE

ATI Technologies ULC, Ma...

1. A method, comprising:
changing a rate of a display clock;
adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output
rate from the display data processing pipeline based upon the changing, wherein a delay in the display data processing pipeline
remains constant by adjusting a number of compensation pipeline stages; and,

writing an output data from the display data processing pipeline into a buffer at the pixel output rate.

US Pat. No. 9,049,461

METHOD AND SYSTEM FOR INTER-PREDICTION IN DECODING OF VIDEO DATA

ATI Technologies ULC, Ma...

1. A video data decoding method comprising:
pre-processing control maps generated from encoded video data that was encoded according to a pre-defined format, wherein
pre-processing comprises generating a plurality of intermediate control maps for a respective plurality of frame processing
operations containing control information, the control information including an indication of which macro blocks or portions
of macro blocks of a frame may be processed in parallel in respective frame processing operations such that one intermediate
control map can control frame processing for an inter-prediction algorithm where one set of macro blocks of a frame are identified
for parallel processing and another intermediate control map can control frame processing for an intra-prediction algorithm
where an entirely different set of macro blocks of the frame are identified for parallel processing; and wherein the pre-defined
format comprises a compression scheme according to which the video data may be encoded using one of a plurality of prediction
operations for various units of video data in a frame, the plurality of prediction operations comprising inter-prediction,
wherein the plurality of intermediate control maps and at least one buffer are generated by running a pre-shader on the control
maps based on at least one predetermined value that is set to indicate whether particular macro blocks are interprediction,
intraprediction or both interprediction and intraprediction, the at least on buffer containing a subset of control information
indicating which of the macro blocks are interprediction, intraprediction or both interprediction and intraprediction;

determining from an intermediate control map indicated units of video data that are to be decoded using inter-prediction;
and

performing inter-prediction on all of the indicated units of video data in the frame in parallel in a respective frame processing
operation.

US Pat. No. 9,347,836

DYNAMIC VOLTAGE REFERENCE FOR SAMPLING DELTA BASED TEMPERATURE SENSOR

ATI Technologies ULC, Ma...

1. A temperature measurement circuit comprising:
circuitry configured to:
generate a temperature dependent first reference voltage, responsive to a reference current flowing through a reference diode
at a first point-in-time;

generate a temperature dependent second reference voltage, responsive to a reference current flowing through the reference
diode at a second point-in-time after the first point-in-time;

generate a temperature dependent first thermal voltage, responsive to a first thermal current flowing through a thermal diode
at the first point-in-time;

generate a temperature dependent second thermal voltage, responsive to a second thermal current flowing through the thermal
diode at the second point-in-time, wherein the second thermal current is different from the first thermal current;

determine a first difference between the first thermal voltage and the first reference voltage at the first point-in-time
using a differential amplifier;

determine a second difference between the second thermal voltage and the second reference voltage at the second point-in-time
using the differential amplifier;

determine an indication of a temperature based at least in part on the first difference and the second difference; and
output the indication of the temperature.

US Pat. No. 9,348,355

DISPLAY LINK CLOCKING METHOD AND APPARATUS

ATI Technologies ULC, Ma...

1. An apparatus comprising:
a clock circuit that is operative to provide a common clock signal synthesized from a reference clock signal; and
a plurality of display interface circuits that are operative to provide a plurality of respective display link clock signals
in response to the common clock signal, wherein a first of the plurality of display link clock signals is at a different clock
speed than the common clock signal while a second of the plurality of display link clock signals is simultaneously at a different
clock speed than both the first of the plurality of display link clock signals and the common clock signal,

wherein the clock speeds of the first and second of the plurality of display link clock signals are adjusted in response to
display configuration information from each of a first and a second of a plurality of displays respectively for simultaneously
driving the first and the second of the plurality of displays respectively.

US Pat. No. 9,099,051

GPU DISPLAY ABSTRACTION AND EMULATION IN A VIRTUALIZATION SYSTEM

ATI Technologies ULC, Ma...

1. A computer-based system comprising:
a first virtual function module including a first virtual timing generator, a first emulated surface register, and a first
emulated flip register;

a second virtual function module including a second virtual timing generator, a second emulated surface register, and a second
emulated flip register, wherein the first emulated surface register and the first emulated flip register are configured to
provide a first hardware interrupt signal indicating that a first new surface has been rendered and is ready for consumption
according to the first virtual timing generator, wherein the second emulated surface register and the second emulated flip
register are configured to provide a second hardware interrupt signal indicating that a second new surface has been rendered
and is ready for consumption according to the second virtual timing generator, and wherein a hypervisor is configured to assign
the first virtual function module to the first virtual machine and the second virtual function module to the second virtual
machine; and

a physical function module comprising a physical timing generator configured to match a monitor's timing, wherein the physical
function module is configured to consume the new surface according to the first hardware interrupt signal and the second hardware
interrupt signal from the first and the second virtual function modules, wherein the physical timing generator, the first
virtual timing generator and the second virtual timing generator are independent of each other.

US Pat. No. 9,424,622

METHODS AND APPARATUS FOR PROCESSING GRAPHICS DATA USING MULTIPLE PROCESSING CIRCUITS

ATI Technologies ULC, Ma...

1. An apparatus comprising:
an integrated graphics processing circuit configured to process graphics jobs from an application run on a processor;
a discrete graphics processing circuit;
an interface operable to interface with the discrete graphics processing circuit;
a system memory operably coupled to the integrated graphics processing circuit and the discrete graphics processing circuit;
and

a controller operably coupled to the system memory and configured to detect when the discrete graphics processing circuit
is coupled to the interface and to cause the integrated graphics processing circuit to process at least one task of a graphics
job at the same time as the discrete graphics processing circuit operates to process at least another task of the same graphics
job, wherein the graphics job includes a series of graphics calculation processing tasks for manipulating data so as to produce
an image for display, wherein the integrated graphics processing circuit is configured to process the at least one task of
the graphics job by performing at least a first number of the series of graphics calculation processing tasks for manipulating
data so as to produce the image at the same time as the discrete graphics processing circuit operates to process the at least
another task of the same graphics job by performing at least a second number of the series of graphics calculation processing
tasks for manipulating data so as to produce the image, wherein the controller establishes separate data paths for the integrated
graphics processing circuit and the discrete graphics processing circuit for each to independently access the system memory
to manipulate the data.

US Pat. No. 10,142,607

SINGLE DISPLAY PIPE MULTI-VIEW FRAME COMPOSER METHOD AND APPARATUS

ATI Technologies ULC, Ma...

1. A method for providing multi-view video comprising:generating stereoscopic multi-view composed frames using a single display pipe that employs multiple viewports wherein each of the stereoscopic multi-view composed frames includes both left eye and right eye data;
providing the stereoscopic multi-view composed frames for display as stereoscopic multi-view video;
generating viewport read requests for at least two viewports of the multiple viewports of the single display pipe based on viewport configuration data;
receiving fetched frame data associated with each of the viewport read requests for the at least two viewports wherein the fetched frame data represents more than one view of a multi-view frame; and
wherein the generating of the stereoscopic multi-view composed frames is based on the received fetched frame data.

US Pat. No. 9,344,727

METHOD OF USING A REDUCED NUMBER OF MACROBLOCK CODING MODES IN A FIRST VIEW BASED ON TOTAL CODING MODE COMPLEXITY VALUES OF MACROBLOCKS IN SECOND VIEW

ATI TECHNOLOGIES ULC, Ma...

1. A method for determining a macroblock (MB) coding mode for a current MB in a dependent view, comprising:
determining a window around a co-located MB and neighboring MBs in a base view, wherein the co-located MB is a MB in the base
view having a same location as the current MB in the dependent view;

determining a coding mode complexity value for the co-located MB and each neighboring MB in the window, wherein the coding
mode complexity value is based on one of a plurality of coding modes;

comparing a total coding mode complexity value of the co-located MB and each neighboring MB in the window to a threshold value,
wherein the total coding mode complexity value is calculated using more than one of the plurality of coding modes;

performing rate distortion optimization (RDO) for the current MB using a first number of coding modes when the total coding
mode complexity value of the co-located MB and each neighboring MB in the window is less than the threshold value;

performing RDO for the current MB using a second number of coding modes greater than the first number of coding modes when
the total coding mode complexity value of the co-located MB and each neighboring MB in the window is greater than or equal
to the threshold value; and

determining a coding mode for the current MB based on the RDO results.

US Pat. No. 9,081,618

METHOD AND APPARATUS FOR THE SCHEDULING OF COMPUTING TASKS

ATI Technologies ULC, Ma...

1. A method for selecting a computing resource to execute a computing task, the method comprising:
accessing information that describes a plurality of computing resources,
wherein the information that describes the computing resources is organized as a multidimensional coordinate system that includes
a plurality of coordinate points,

wherein each of the coordinate points corresponds to a computing resource from the plurality of computing resources,
wherein each of the coordinate points corresponds to a combination of attributes of the computing resource to which the coordinate
point corresponds, and

wherein each of the coordinate points is associated with a weight;
accessing information that defines a computing task, wherein the information that defines the computing task includes constraint
information that defines constraints on computing resources on which the computing task can be executed;

selecting, at a processor, a computing resource from the plurality of computing resources based on the information that describes
the plurality of computing resources and the constraint information;

the processor executing the computing task at the selected computing resource and;
upon completion of the computing task, updating the weights with which the coordinate points are associated to indicate whether
execution of the computing task was successful or unsuccessful.

US Pat. No. 9,351,004

MULTIVIEW VIDEO CODING REFERENCE PICTURE SELECTION UNDER A ONE REFERENCE PICTURE CONSTRAINT

ATI TECHNOLOGIES ULC, Ma...

1. A method for coding a dependent view picture based on a reference picture, comprising:
coding a base view picture;
evaluating the coded base view picture by determining (i) a metric of intra macroblocks used during the coding of the base
view picture and (ii) a metric of skipped macroblocks omitted during the coding of the base view picture;

selecting, as the reference picture to code the dependent view picture, the evaluated coded base view picture when the determined
metric of intra macroblocks in the evaluated coded base view picture is greater than a first threshold;

selecting, as the reference picture to code the dependent view picture, a dependent view reference picture when the determined
metric of skipped macroblocks in the evaluated coded base view picture is greater than a second threshold; and

coding the dependent view picture using the selected reference picture.

US Pat. No. 9,984,664

METHOD AND APPARATUS FOR COMPENSATING FOR VARIABLE REFRESH RATE DISPLAY RANGE LIMITATIONS

ATI Technologies ULC, Ma...

1. A method of providing display content for a display that supports a variable refresh rate range that includes a minimum supported display refresh rate and a maximum supported display refresh rate, the method comprising:determining that a new frame is to be displayed at an expected new frame display rate that is within either a first frame reinsertion range that includes the minimum supported display refresh rate of the display or a second frame reinsertion range that includes the maximum supported display refresh rate of the display;
based on the expected new frame display rate, re-providing a current frame for display prior to providing the new frame for display; and
varying a new frame presentation duration based on a time difference between when a previous frame is presented for display and when the new frame is ready to be displayed.

US Pat. No. 9,947,114

MODIFYING GRADATION IN AN IMAGE FRAME INCLUDING APPLYING A WEIGHTING TO A PREVIOUSLY PROCESSED PORTION OF THE IMAGE FRAME

ATI Technologies ULC, Ma...

1. A method for modifying gradation in an image frame, the method comprising:determining, by blend factor adjustment logic of an image processing apparatus, a blend factor indicating a first weighting associated with a previously modified portion of the image frame;
modifying, by image gradation modifying logic of the image processing apparatus, the gradation in a current region of the image frame by:
generating a weighted value for the current region of the image frame comprising:
applying the first weighting to the previously modified portion of the image frame to generate weighted previously modified portion data;
applying a second weighting to the current region of the image frame to generate weighted current region data; and
combining the weighted previously modified portion data and the weighted current region data to generate the weighted value; and
modifying the gradation in the current region of the image frame by applying the weighted value to the current region of the image frame;
storing the modified image frame in a memory; and
displaying the modified image frame on a display.

US Pat. No. 9,164,646

METHOD AND APPARATUS FOR ACCOMMODATING DISPLAY MIGRATION AMONG A PLURALITY OF PHYSICAL DISPLAYS

ATI Technologies ULC, Ma...

1. A method for accommodating display migration among a plurality of physical displays, the method comprising:
detecting a display migration condition from at least a second physical display to a first physical display; and
controlling compositing of a plurality of desktop surfaces by combining the plurality of desktop surfaces into a display object
that includes the plurality of desktop surfaces on different surfaces of the display object in response to detecting the display
migration condition from the at least the second physical display to the first physical display, so as to enable access to
each one of the plurality of desktop surfaces of the display object on the first physical display, wherein the plurality of
desktop surfaces comprise at least a desktop surface associated with the second physical display.

US Pat. No. 10,074,600

METHOD OF MANUFACTURING INTERPOSER-BASED DAMPING RESISTOR

ATI Technologies ULC, Ma...

1. A method of manufacturing, comprising:forming a resistor onboard an interposer, the interposer adapted to have a first semiconductor chip mounted thereon, the resistor adapted to dampen a capacitive network, the capacitive network having at least one capacitor positioned off the interposer and the first semiconductor chip.

US Pat. No. 9,922,395

MULTI-THREAD GRAPHICS PROCESSING SYSTEM

ATI TECHNOLOGIES ULC, (C...

1. In a graphics processing system, a method for selecting a command thread for processing, the method comprising:
providing a plurality of pixel command threads to a first reservation station and a plurality of vertex command threads to
a second reservation station;

implementing a priority scheme to select, by an arbiter circuit, a first command thread from among both (1) the plurality
of pixel command threads and (2) the plurality of vertex command threads;

providing, by the arbiter circuit, the first command thread to an arithmetic logic unit (ALU) operatively connected to the
arbiter circuit; and

implementing the priority scheme to select, by the arbiter circuit, a second command thread from among both (1) the plurality
of pixel command threads and (2) the plurality of vertex command threads,

wherein the priority scheme is configured to intermix, in an order determined based on a command of the first command thread
and a command of the second command thread, an execution of commands of the first command thread with commands of the second
command thread.

US Pat. No. 9,400,540

EVENT BASED DYNAMIC POWER MANAGEMENT

ATI Technologies ULC, Ma...

1. A method of event based dynamic power management, the method comprising:
receiving, at a processor having a plurality of hardware block engines each configured to perform a function, an indication
of an occurrence of an event external to the plurality of hardware block engines;

in response to receiving the indication of the occurrence of the event external to the plurality of hardware block engines,
determining whether or not the occurrence of the event indicates adjusting an amount of power used by one of the plurality
of hardware block engines; and

adjusting the amount of power used by the one hardware block engine without monitoring an activity of the one hardware block
engine while an amount of power used by one or more other hardware block engines of the plurality of hardware block engines
is maintained when it is determined that the received event indicates adjusting the amount of power used by the one hardware
block engine.

US Pat. No. 9,760,333

PIXEL CLOCKING METHOD AND APPARATUS

ATI Technologies ULC, Ma...

1. An apparatus comprising:
a clock circuit that is operative to provide a common clock signal synthesized from a reference clock signal; and
a virtual pixel clock circuit that is operative to provide a plurality of virtual pixel clock signals in response to the common
clock signal, wherein a first of the plurality of virtual pixel clock signals is at a different clock speed than the common
clock signal while a second of the plurality of virtual pixel clock signals is simultaneously at a different clock speed than
both the first of the plurality of virtual pixel clock signals and the common clock signal, and

wherein the clock speeds of the first and second of the plurality of virtual pixel clock signals are adjusted in response
to display configuration information from each of a first and a second of a plurality of displays respectively for simultaneously
driving the first of the plurality of displays that operates using the first of the plurality of virtual pixel clock signals
and the second of the plurality of displays that operates using the second of the plurality of virtual pixel clock signals,
respectively, wherein the display configuration information from the first of the plurality of displays describes operating
characteristics of the first of the plurality of displays and the display configuration information from the second of the
plurality of displays describes operating characteristics of second of the plurality of displays.

US Pat. No. 9,449,359

RENDERING SETTINGS IN A MULTI-GRAPHICS PROCESSING UNIT SYSTEM

ATI Technologies ULC, Ma...

1. A method for adjusting graphics rendering settings in a computer system, comprising:
monitoring an activity level on the bus, the monitoring comprising measuring a latency on the bus by:
determining whether a request made for a data chunk is the first request for the data chunk;
on the condition that it is determined that the request for the data chunk is the first request for the data chunk, (i) increasing
a latency counter when the requested data chunk has not been received and a clock cycle has occurred and (ii) repeating (i)
after the latency counter is increased; and

resetting the latency counter and updating a trigger value when the requested data chunk has been received;
adjusting the graphics rendering settings of the system from a first level to a second level when the activity level on the
bus meets the trigger value; and

returning the graphics rendering settings of the system from the second level to the first level when the bus activity level
drops below a threshold.

US Pat. No. 9,281,701

WIRELESS POWER TRANSFER DEVICE FOR CHARGING MOBILE/PORTABLE DEVICES

ATI Technologies ULC, On...

1. A wireless mobile/portable device charging system, comprising:
a charging device having a housing with a groove for receiving the mobile/portable device for charging, a magnetic core located
in the housing, the magnetic core has a base and two legs that are located around the groove, and a coil wrapped around the
base, and a driver circuit is connected to the coil and to an external power source;

a power receiver adapted to be located on a mobile/portable device in an area that is engagable in the groove of the charging
device, the power receiver including a receiver magnetic core, a receiving coil wrapped around the receiving magnetic core
for receiving an inductive current, and a charging circuit connected to the receiving coil and adapted to be connected to
a battery of the mobile/portable device.

US Pat. No. 10,134,106

METHOD AND DEVICE FOR SELECTIVE DISPLAY REFRESH

ATI Technologies ULC, Ma...

1. A method of providing image frames including:using a memory having a swap buffer chain comprising at least three buffers, including a present buffer, a first back buffer, and a second back buffer;
determining when a rendering engine has written to a first portion of a first frame in the first back buffer since a last time the present buffer was read by a display controller;
determining when the rendering engine has written to a first portion of a second frame in the second back buffer since the last time the present buffer was read by the display controller;
determining that a first portion of a present frame in the present buffer has changed by tracking which portion of the present frame in the present buffer, the first frame in the first back buffer, and the second frame in the second back buffer has changed since the last time the present buffer was read by the display controller;
responsive to determining that the first portion of the present frame in the present buffer has changed, outputting the first portion of the present frame that has changed along with any other portions of the present frame that have changed relative to the first and second frames without outputting portions of the first and second frames that have not changed,
wherein the tracking includes detecting an interim change caused by a copying operation from at least one of the first back buffer and the second back buffer, and detecting a current change in the present buffer caused by a writing operation performed by the rendering engine to the present buffer.

US Pat. No. 10,045,003

EFFICIENT MODE DECISION METHOD FOR MULTIVIEW VIDEO CODING BASED ON MOTION VECTORS

ATI TECHNOLOGIES ULC, Ma...

1. A method for determining a macroblock (MB) coding mode for a current MB in a dependent view, comprising: determining a window around a co-located MB and neighboring MBs in a base view, wherein the co-located MB is a MB in the base view having a same location as the current MB in the dependent view;selecting, for at least each neighboring MB sharing a portion of a border with the co-located MB in the window, a motion vector (MV) as a candidate MV;
calculating an average MV from each of the candidate MVs in the window;
performing rate distortion optimization (RDO) for the current MB using a first number of coding modes when a difference between the MV of the co-located MB and the average MV is less than or equal to a threshold;
performing RDO for the current MB using a second number of coding modes greater than the first number of coding modes when the difference between the MV of the co-located MB and the average MV is greater than or equal to the threshold; and
determining a coding mode for the current MB based on the RDO results.

US Pat. No. 9,455,722

METHOD AND APPARATUS FOR FAST LOCKING OF A CLOCK GENERATING CIRCUIT

ATI Technologies ULC, Ma...

1. An integrated circuit having a clock generating circuit with a feedback loop and a variable clock signal generator comprising:
open feedback loop switch logic responsive to a controlled change in power supply voltage indication signal, and operative
to selectively open the feedback loop; and

a dynamic fast lock control signal generator operative to selectively apply a stabilizing control signal to the variable clock
signal generator in response to opening the feedback loop.

US Pat. No. 9,406,098

MULTI-THREAD GRAPHICS PROCESSING SYSTEM

ATI Technologies ULC, Ma...

1. In a graphics processing system, a method for selecting a command thread for processing, the method comprising:
providing, by an input arbiter implemented by the graphics processing system, a plurality of pixel and vertex command threads
to each of a first and second reservation station;

selecting, by an arbiter implemented by the graphics processing system, a pixel command thread from the plurality of pixel
command threads;

selecting, by the arbiter, a vertex command thread from the plurality of vertex command threads;
selecting, by the arbiter as the command thread, either of the pixel command thread and the vertex command thread; and
maintaining a state of a selected pixel command thread or vertex command thread.

US Pat. No. 9,323,274

SELF-CALIBRATING DIGITAL BANDGAP VOLTAGE AND CURRENT REFERENCE

ATI Technologies ULC, Ma...

1. A reference voltage generator, comprising:
a temperature-dependent device;
a processing device comprising circuitry configured to process a reference voltage and digital representations of first and
second voltages, the first and second voltages being derived from the temperature dependent device, and to output a value;

a digital to analog converter (DAC) comprising circuitry configured to generate the reference voltage based on the value;
wherein the first voltage is proportional to absolute temperature (PTAT) and the second voltage is complementary to absolute
temperature (CTAT), and

wherein the reference voltage is substantially independent of absolute temperature in an operating temperature range of the
reference voltage generator; and

wherein the reference voltage is fed back from the DAC to the processing device.

US Pat. No. 9,609,358

PERFORMING VIDEO ENCODING MODE DECISIONS BASED ON DOWN-SCALED MACROBLOCK TEXTURE COMPLEXITY

ATI Technologies ULC, Ma...

1. A method of performing video encoding mode decisions, the method comprising:
receiving a down-scaled frame including at least one macroblock, wherein the down-scaled frame is associated with a full-scale
frame having a plurality of macroblocks that have been downsampled;

determining a weighting factor for each of the macroblocks in the full-scale frame from stored predetermined information comprising
a plurality of different weighting factors each corresponding to a different mode used to encode each of the macroblocks in
the full-scale frame;

determining, for each of the plurality of macroblocks, a distance measure factor corresponding to a location of each of the
plurality of macroblocks in the full-scale frame relative to a selected point adjacent to at least one of the plurality of
macroblocks and excluded from each of the plurality of macroblocks; and

predicting an encoding mode to encode the at least one macroblock in the down-scaled frame based on the weighting and the
distance measure factors.

US Pat. No. 9,143,751

METHOD AND APPARATUS FOR AUTOMATIC TIME-SHIFTING FOR A CONTENT RECORDER

ATI Technologies ULC, Ma...

1. A method for controlling the time shifting of content comprising:
receiving content by a digital video recording system;
detecting by a digital video recording system, a non-viewer initiated event that is not embedded in the content; and
in response to detecting the non-viewer initiated event;
pausing by a digital video recording system, the content to a presentation device;
in response to the same detected non-viewer initiated event, spooling by a digital video recording system, the content onto
a mass storage device; and

unpausing from the event to resume presentation of the content.

US Pat. No. 9,078,028

METHOD AND DEVICE FOR CREATING AND MAINTAINING SYNCHRONIZATION BETWEEN VIDEO SIGNALS

ATI TECHNOLOGIES ULC, Ma...

1. A method of providing data output including:
generating a first data stream and a second data stream, the streams being generated by a first device having a processor
and first and second rate generators, the first data stream following a first protocol and being governed by the first rate
generator and the second data stream following a second protocol that is different from the first protocol, the second data
stream being governed by the second rate generator;

outputting said first and second streams; and
subsequent to the outputting, writing to a pixel rate register to adjust a setting of one of the first and second rate generators
to adjust a rate at which pixels are generated thereby to cause a reduction in any temporal offset between first data in the
first stream and the first data in the second stream.

US Pat. No. 9,164,564

METHOD AND APPARATUS FOR OPTIMIZING POWER CONSUMPTION IN A MULTIPROCESSOR ENVIRONMENT

ATI Technologies ULC, Ma...

1. A computer system comprising:
a load balancer that is operative to identify a plurality of processing states each operable to execute a task, wherein each
processing state indicates how the task is to be distributed among a plurality of processing elements; and

a current selector operative to select a processing state and select a battery characteristic, from a plurality of differing
battery characteristics, that is most power efficient for execution of the task and executing the task using the selected
processing state and selected battery characteristic.

US Pat. No. 9,959,593

MEMORY CONTROLLER HAVING PLURALITY OF CHANNELS THAT PROVIDES SIMULTANEOUS ACCESS TO DATA WHEN ACCESSING UNIFIED GRAPHICS MEMORY

ATI Technologies ULC, Ma...

1. A method, carried out by a memory controller, the method comprising:receiving client data access requests associated with one or more clients and a central processing unit (CPU) data access request associated with a CPU, to a plurality of memory channels for accessing unified system/graphics memory, wherein the plurality of memory channels is accessible, simultaneously, by the CPU and at least one client of the one or more clients through the memory controller;
prioritizing the CPU data access request to the unified memory over the client data access requests to the unified memory; and
controlling the plurality of memory channels to access, simultaneously, data for the CPU and data for the at least one client based on a request of the client data access requests and the CPU data access request.

US Pat. No. 9,300,966

ADAPTIVE FREQUENCY DOMAIN FILTERING FOR PHASE PLANE CORRELATION

ATI Technologies ULC, Ma...

1. A method for producing a phase plane correlated surface comprising:
Fourier transforming by a digital device first and second time domain images to create a first and second phase plane images,
respectively;

prefiltering the first and second phase plane images, said prefiltering based on certain predetermined criteria;
correlating by the digital device the first and second phase plane images to form a frequency domain correlated phase plane
surface; and

inverse Fourier transforming the frequency domain correlated phase plane surface to provide a phase plane correlated surface.

US Pat. No. 9,230,484

ADAPTIVE BACKLIGHT CONTROL AND CONTRAST ENHANCEMENT

ATI TECHNOLOGIES ULC, Ma...

1. A method comprising:
determining n points that define n?1 regions of a first transform function based at least in part on a first set of values
associated with a first display frame and a maximum average contrast function, n being an integer greater than 2;

converting the first set of values to a corresponding second set of values based on the first transform function; and
generating a backlight control signal based on an average contrast of the second set of values, the backlight control signal
configured to control an intensity of a backlight of a display.

US Pat. No. 9,508,282

VIRTUALIZED DISPLAY OUTPUT PORTS CONFIGURATION

ATI Technologies ULC, Ma...

1. A multi-stream transport (MST) sink device comprising:
a receiver communicatively coupled to a source device by a Source Display Port, wherein the receiver receives packetized data;
an Output Display Port communicatively coupled to a first display via a physical link;
a logical port communicatively coupled to a second display via a logical link;
a memory, wherein the memory stores DisplayPort Configuration Data (DPCD) associated with the Output Display Port and stores
Virtual DPCD (VDPCD) associated with the logical port; and

a transmitter, wherein the transmitter:
selectively transmits the packetized data to the first display via the physical link based on the DPCD, and
selectively transmits the packetized data to the second display via the logical link based on the VDPCD, wherein the VDPCD
comprises information for configuring the second display to display the packetized data.

US Pat. No. 9,565,433

SYSTEM FOR PARALLEL INTRA-PREDICTION DECODING OF VIDEO DATA

ATI TECHNOLOGIES ULC, Ma...

1. A system for decoding video data, the system comprising:
a plurality of processing pipelines;
a z-buffer; and
a driver, coupled to the z-buffer, the driver comprising a decoder, the decoder being configured to:
receive a plurality of control maps that were generated from encoded video data encoded according to a pre-defined format,
write, to the z-buffer, values indicating whether macro blocks of the encoded video data are to be decoded using intra-prediction
or inter-prediction, the values being based on the plurality of control maps,

preprocess the plurality of received control maps to generate a plurality of intermediate control maps containing control
information including an indication of which macro blocks or portions of macro blocks may be processed in parallel in the
plurality of processing pipelines, and

performing Z-testing on the Z-buffer to determine whether to perform intra-prediction or inter-prediction on the encoded video
data.

US Pat. No. 9,190,012

METHOD AND SYSTEM FOR IMPROVING DISPLAY UNDERFLOW USING VARIABLE HBLANK

ATI Technologies ULC, Ma...

1. A method of displaying data, comprising:
detecting, at a timing generator, an assertion of a data ready signal in a display pipeline, the display pipeline having access
to a shared system resource that is accessed by a plurality of devices, wherein the data ready signal indicates the availability
of the shared system resource and the readiness of a line of display data for transmission from the display pipeline; and

generating, by the timing generator, a line-transmit signal based upon a clock signal and the asserted data ready signal,
wherein the line-transmit signal is provided to the display pipeline and indicates that the display pipeline should transmit
the line of display data.

US Pat. No. 10,002,028

DYNAMIC FEEDBACK LOAD BALANCING

ATI Technologies ULC, Ma...

1. A computing system, comprising:a unified command buffer, wherein the unified command buffer is found in system memory and enables each of the processors to similarly view system memory thereby permitting the processors to share the same system memory; and
a plurality of processors configured to access one or more instructions stored in the unified buffer, wherein each processor is coupled to the unified command buffer, wherein the one or more instructions stored in the unified command buffer contain an indication that designates each instruction for a particular processor;
wherein each processor of the plurality of processors is further configured to read each instruction stored in the unified command buffer having an indication for the processor;
wherein each processor of the plurality of processors is further configured to implement virtual memory (VM) such that the underlying physical resources of the unified command buffer are located in different physical locations.

US Pat. No. 9,904,970

MULTI-THREAD GRAPHICS PROCESSING SYSTEM

ATI Technologies ULC, Ma...

1. In a graphics processing system, a method for selecting command threads for processing, the method comprising:
selecting, by an arbiter circuit implemented by the graphics processing system, command threads from among a plurality of
pixel command threads and a plurality of vertex command threads, wherein the arbiter circuit selects a pixel command thread
as a selected command thread and a vertex command thread as another selected command thread;

intermixing, in an order determined based on a command of the selected pixel command thread and a command of the selected
vertex command thread, an execution, in an arithmetic logic unit, of commands of the selected pixel command thread with commands
of the selected vertex command thread;

maintaining a first status of the selected pixel command thread, wherein the first status is used by the arbiter circuit to
perform the selecting of the selected pixel command thread; and

maintaining, concurrently with the first status, a second status of the selected vertex command thread, wherein the second
status is used by the arbiter circuit to perform the selecting of the selected vertex command thread.

US Pat. No. 10,108,439

SHADER PIPELINES AND HIERARCHICAL SHADER RESOURCES

Advanced Micro Devices, ...

1. A method for inputting a shader resource to a shader or a pipeline in a computing device, comprising:creating, in a computer memory, by a processing device, a data structure having at least one slot which contains a pointer to a shader resource stored in a graphics processing unit (GPU) memory;
binding the data structure to a GPU register;
referencing the at least one slot by an offset to input the shader resource to the shader or pipeline;
determining a GPU overhead associated with inputting a different shader resource to the shader or pipeline by referencing a different slot of the data structure;
determining a CPU overhead associated with inputting the different shader resource to the shader or pipeline by binding a different data structure to the GPU register; and
inputting a different shader resource to the shader or pipeline by conditionally either referencing a different slot of the data structure or binding a different data structure to the GPU register, wherein the condition is based on the GPU overhead and the CPU overhead.

US Pat. No. 9,769,494

ADAPTIVE SEARCH WINDOW POSITIONING FOR VIDEO ENCODING

ATI Technologies ULC, Ma...

1. A method comprising:
receiving a motion hint that is generated based on motion information associated with a plurality of video frames, the plurality
of video frames including a reference video frame and a current video frame, wherein the motion hint is associated with one
or more motion vectors associated with one or more regions of the current video frame;

partitioning a region of the current video frame into sub-regions, each sub-region having an anchor block;
searching for matching blocks of pixels in the plurality of video frames using a search window in the reference video frame,
wherein the motion hint and the anchor block in the sub-region are used to determine a position for the search window in the
reference video frame to use to encode a block of pixels in a sub-region of the current video frame and the search window
captures the motion of the matching blocks of pixels; and

encoding the current video frame using the motion hint and the search window.

US Pat. No. 9,059,159

ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE

ATI Technologies ULC, Ma...

1. A semiconductor die comprising:
i) an integrated circuit formed on one surface of a piece of semiconductor wafer;
ii) a plurality of input-output (I/O) pads interconnected to said integrated circuit;
iii) a routing layer comprising: a dielectric layer formed on said one surface; and a plurality of conductive traces extending
from respective ones of said I/O pads;

iv) a plurality of under-bump metallizations (UBMs), each comprising a top surface for attaching a respective one of a plurality
of solder bumps; and a bottom contact surface smaller than said top surface, in electrical contact with a respective one of
said plurality of conductive traces;

wherein said routing layer comprises one or more stress-buffering areas, each circumscribing a UBM and larger than a bump
pad in contact with said UBM and containing at least one conductive trace passing under said UBM without electrically contacting
said UBM, wherein at least one of said one or more stress-buffering areas is between 30% and 100% occupied by said conductive
traces.

US Pat. No. 10,546,365

SINGLE PASS FLEXIBLE SCREEN/SCALE RASTERIZATION

Advanced Micro Devices, I...

1. A method comprising:rendering, in a graphics pipeline, pixels in window space with a non-uniform pixel spacing;
sampling, with a scan converter, the pixels in window space through a distortion function that maps the non-uniformly spaced pixels in window space to uniformly spaced pixels in raster space;
rendering, at the scan converter, display pixels based on the uniformly spaced pixels in raster space; and
generating an image for display to a user using the display pixels.

US Pat. No. 10,043,481

METHOD AND DEVICE FOR LINK OVER-TRAINING

ATI Technologies ULC, Ma...

1. A method of training a data link using a link controller, the method including:supplying, using the link controller, a signal having noise deliberately added thereto for processing by a link training operation that is training a data link between a display data source and a display data sink;
removing, using the link controller, the noise from the signal upon reaching a predetermined amount of time without achieving successful training;
removing, using the link controller, the noise from the signal once the data link is trained.

US Pat. No. 9,867,282

CIRCUIT BOARD WITH CORNER HOLLOWS

ATI Technologies ULC, Ma...

1. An apparatus, comprising:
a circuit board having a first side configured to have a semiconductor chip mounted thereon and four corner hollows, the circuit
board having a perimeter partially defined by the four corner hollows; and

wherein the circuit board includes an interconnect layer having plural conductor traces to conduct current and that track
the perimeter.

US Pat. No. 9,832,479

MOTION ESTIMATION APPARATUS AND METHOD FOR MULTIVIEW VIDEO

ATI Technologies ULC, Ma...

1. A method for encoding multiview video comprising:
estimating motion vector information for a group of pixels in a dependent eye view using motion vector information from a
co-located group of pixels in a base eye view and motion vector information from neighboring pixels to the co-located group
of pixels in the base eye view wherein the base eye view and dependent eye views are temporally the same;

encoding the group of pixels in the dependent eye view based on the estimated motion vector information; and
wherein estimating the motion vector information for the group of pixels in a dependent eye view is done based on a median
value calculation of motion vectors for the co-located group of pixels in a base eye view and motion vectors for the neighboring
pixels to the co-located group of pixels in the base eye view.

US Pat. No. 9,607,935

SEMICONDUCTOR CHIP PACKAGE WITH UNDERMOUNT PASSIVE DEVICES

ATI Technologies ULC, Ma...

8. An apparatus, comprising:
a printed circuit board;
a carrier substrate having a first side and a second side opposite the first side, the second side including plural solder
structures coupled to the printed circuit board so as to leave a gap between the second side of the carrier substrate and
the printed circuit board;

a semiconductor chip coupled to the first side of the carrier substrate;
a mechanically joined group of discrete passive devices positioned in the gap, the group including at least terminal coupled
to the second side of the carrier substrate and at least one terminal coupled to the printed circuit board; and

at least one passive device coupled to the first side of the carrier substrate.

US Pat. No. 9,583,072

SPATIAL DITHERING FOR A DISPLAY PANEL

ATI Technologies ULC, Ma...

1. A method, comprising:
receiving an image with an L bit long pixel input data;
generating an M bit long random data, wherein M is a number of least significant bits of the input data;
adding an M bit long frame counter value to the random data;
rounding up the pixel input data to L-M most significant bits when the M least significant bits of the pixel input data is
greater than the sum of the frame counter value and the random data;

truncating the pixel input data to the L-M most significant bits when the M least significant bits of the pixel input data
is less than or equal to the sum of the frame counter value and the random data and

dithering the image by replacing the L bit long pixel input data with the L-M bit long most significant bits of the rounded
UP pixel input data and the L-M bit long most significant bits of the truncated pixel input data.

US Pat. No. 9,569,349

METHOD AND APPARATUS FOR REALLOCATING MEMORY CONTENT

ATI Technologies ULC, Ma...

1. A method for reallocating memory content comprising:
copying data from a source memory region to a pending data queue;
writing the data from the pending data queue to a destination memory region;
executing a first write request to a source memory region;
duplicating the first write request to produce a duplicated write request; and
executing a second write request to copy content that is the subject of the duplicated write request from the source memory
region to the destination memory region.

US Pat. No. 10,063,834

METHOD AND APPARATUS FOR PROVIDING VIDEO ENHANCEMENTS FOR DISPLAY IMAGES

ATI Technologies ULC, Ma...

1. A method for processing video comprising:analyzing, by each of a plurality of processors, respective portions of a display image or respective frames of a group of multi-view frames and producing respective image enhancement statistic information based on the analysis, the image enhancement statistic information being information describing image enhancements available to be applied to the given display image portion or frame to produce a difference in the appearance of said display image portion or frame; and
generating, by another processor separate from the plurality of processors, global image enhancement control information for application to at least two analyzed portions of the display image or at least two of the plurality of multi-view frames of interest based on the image enhancement statistic information from at least two of the plurality of processors,
wherein generating global image enhancement control information comprises sharing respective image enhancement statistic information among the plurality of processors and wherein each of the plurality of processors generates image enhancement control information based on image enhancement statistics obtained from another of the plurality of processors.

US Pat. No. 9,325,929

POWER MANAGEMENT IN MULTI-STREAM AUDIO/VIDEO DEVICES

ATI Technologies ULC, Ma...

1. A method of processing audio/video data from a multi-stream audio/video source at an audio/video device to output audio/video
in one of at least two power consumption modes, said audio/video data comprising a first digital audio/video stream and a
second digital audio/video stream, said method comprising:
(i) in a first normal power consumption mode, compositing images of a first sequence of decoded images with images of a second
sequence of decoded images to produce output audio/video frames, wherein said first sequence of decoded images is formed by
digitally processing said first digital stream and said second sequence of decoded images is formed by digitally processing
said second digital stream to output audio/video;

(ii) detecting a desired reduced power consumption mode for operating said device; and
(iii) in response to said detecting:
continuing decoding and digitally processing said first digital stream as in the first normal power consumption mode to produce
said first sequence of decoded images;

producing a third sequence of decoded images by digitally processing and decoding said second stream in a computationally
simpler manner than in the first normal power consumption mode to reduce power consumption,

said digitally processing and decoding in said computationally simpler manner comprising at least one of:
decoding only a subset of overlay images from said second stream;
performing lower order filtering on said second stream than in the first normal power consumption mode;
performing lower quality interpolation on said second stream than in the first normal power consumption mode;
performing nearest neighbor interpolation on said second stream;
inhibiting inverse telecine operations on said second stream; and
performing one of: de-noising, scaling, frame rate conversion, gamma correction, and de-interlacing operations on said second
stream in a computationally simpler manner than in the first normal power consumption mode; and

transitioning said device to composite images of said first sequence of decoded images, produced as in the first normal power
consumption mode, with images of the third sequence of decoded images, produced in the computationally simpler manner, to
produce output audio/video frames, wherein said third sequence of decoded images differs from said second sequence of decoded
images.

US Pat. No. 9,865,030

METHODS AND APPARATUS FOR PROCESSING GRAPHICS DATA USING MULTIPLE PROCESSING CIRCUITS

ATI Technologies ULC, Ma...

1. An apparatus comprising:
an integrated graphics processing circuit configured to process graphics jobs;
an interface operable to interface with a discrete graphics processing circuit;
a processor operably coupled to the integrated graphics processing circuit and the discrete graphics processing circuit; and
a controller operably coupled to the processor and configured to detect when the discrete graphics processing circuit is coupled
to the interface and to cause the integrated graphics processing circuit to process at least one task of a graphics job at
the same time as the discrete graphics processing circuit operates to process at least another task of the same graphics job,
wherein the integrated graphics processing circuit is configured to process the at least one task of the graphics job by performing
at least a first number of a series of graphics calculation processing tasks for manipulating data so as to produce an image
at the same time as the discrete graphics processing circuit operates to process the at least another task of the same graphics
job by performing at least a second number of the series of graphics calculation processing tasks for manipulating data so
as to produce the image, wherein the controller establishes separate data paths for the integrated graphics processing circuit
and the discrete graphics processing circuit for each to independently access the processor to receive the data for manipulation.

US Pat. No. 9,594,536

METHOD AND APPARATUS FOR ELECTRONIC DEVICE COMMUNICATION

ATI Technologies ULC, Ma...

1. A method carried out by an electronic device comprising:
translating monitor control commands to a network protocol format to produce network protocol formatted monitor control commands;
and

communicating the network protocol formatted monitor control commands to a network protocol port dedicated for communicating
network protocol formatted monitor control commands, wherein translating the monitor control commands to a network protocol
format to produce network protocol formatted monitor control commands comprises:

generating a high level messaging transaction structure from a plurality of low level messaging transaction requests or replies;
and

converting the high level messaging transaction structure into network protocol packets.

US Pat. No. 10,334,276

METHOD AND APPARATUS FOR DETERMINING THE SEVERITY OF CORRUPTION IN A PICTURE

ATI Technologies ULC, Ma...

8. A method comprising:receiving, at a decoder, a first packet including encoded pixels representative of a picture in a multimedia stream;
receiving, at the decoder, a first approximate signature generated based on approximate values of pixels in a reconstructed copy of the picture;
decoding the encoded pixels at the decoder;
transmitting, from the decoder, a first signal in response to comparing the first approximate signature and a second approximate signature generated based on approximate values of the decoded pixels,
wherein transmitting the first signal comprises transmitting a first signal that indicates whether the first approximate signature is equal to the second approximate signature;
replicating a second packet to replace a corrupted third packet, wherein the first packet was encoded based on the third packet, and wherein decoding the encoded pixels in the first packet comprises decoding the encoded pixels in the first packet based on encoded pixels in the second packet
receiving, at the decoder, a second signal in response to transmitting the first signal and in response to detecting corruption of the third packet; and
wherein receiving the second signal comprises receiving instructions to request an intra-coded picture in response to the first approximate signature differing from the second approximate signature.

US Pat. No. 10,025,721

INPUT/OUTPUT MEMORY MAP UNIT AND NORTHBRIDGE

Advanced Micro Devices, I...

1. A method for managing page tables in a computer system including the handling of dirty bits, the method comprising:accessing one or more table entries in the page tables providing a mapping of at least one virtual memory address to its corresponding physical address, the accessing according to an access flag, the accessing occurring via hardware in order to be performed in one atomic update, the accessing causing at least one access bit in the access flag to be modified, wherein the access flag is used to indicate secure and non-secure table entries for address translations, wherein the atomic update is a single atomic operation;
modifying a memory address identified in the one or more accessed page tables based on the memory address and one or more memory operations performed on the memory address, wherein the modifying includes setting and clearing the memory address using the one or more memory operations; and
modifying a dirty bit in the page table that indicates whether the page is clean or dirty in response to the modified memory address in the atomic update,
wherein the at least one access bit in the access flag and the dirty bit are updated for the accessed one or more tables entries during the atomic update.

US Pat. No. 9,910,788

CACHE ACCESS STATISTICS ACCUMULATION FOR CACHE LINE REPLACEMENT SELECTION

Advanced Micro Devices, I...

1. A system comprising:
a processor device comprising:
a cache;
a set of counters, each counter of the set associated with a corresponding block of a plurality of blocks of the cache;
a cache access monitor coupled to the cache and the set of counters, the cache access monitor to, for each time quantum for
a series of one or more time quanta, adjust counter values of the set of counters based on accesses to the corresponding blocks
of the cache; and

a transfer engine to, after completion of each time quantum, transfer the counter values of the set of counters for the time
quantum to a corresponding location in a system memory.

US Pat. No. 9,720,486

METHOD AND DEVICE FOR NOISE REDUCTION IN MULTI-FREQUENCY CLOCKING ENVIRONMENT

Advanced Micro Devices, I...

1. A method of operating a synchronous frequency processing environment served by a common power source and common clock source
including:
operating the processing environment to have a first power consumption;
determining a first synchronous frequency processing domain within the processing environment where it is desired to implement
a first clock frequency alteration in a clock signal for the first synchronous frequency processing domain; the first clock
frequency alteration generating an associated first alteration in a power consumption from the first synchronous frequency
processing domain; and

determining a second clock frequency alteration to a clock signal for a second synchronous frequency processing domain of
the processing environment, the second clock frequency alteration being determined so as to reduce a change in the first power
consumption caused by the first alteration in power consumption.

US Pat. No. 9,696,784

DIRECT HARDWARE ACCESS MEDIA PLAYER

Advanced Micro Devices, I...

1. A method for use in an electronic device, comprising:
activating an operating system on the electronic device in a normal mode using a central processing unit (CPU) and a graphics
processing unit (GPU);

activating a standalone media player (SMP) to process media content in response to selecting media content for playback, wherein
the SMP is electronically activated and the SMP is software that has direct access to computer hardware on the electronic
device;

placing the activated operating system on the electronic device into a stand-by mode in response to activating the SMP, wherein
the SMP causes the operating system to be placed in the stand-by mode;

dedicating, by the SMP, a hardware pipeline of the electronic device to process media content, wherein the hardware pipeline
of the electronic device is powered on and accessible when the operating system on the device is in the normal mode or the
stand-by mode, wherein the dedicating further includes the SMP initializing the hardware pipeline of the electronic device
for processing the media content;

wherein the dedicating further comprises: allocating a memory buffer in the hardware pipeline for storing the media content
during processing; and initializing hardware blocks and registers in the hardware pipeline for processing the media content;

processing, by the SMP, the media content on the GPU using the dedicated hardware pipeline while the operating system is in
the stand-by mode; and

in response to determining that the hardware pipeline completed processing the media content and that the operating system
is in the stand-by mode, restoring the operating system on the electronic device.

US Pat. No. 9,569,395

FAST EXIT FROM LOW-POWER STATE FOR BUS PROTOCOL COMPATIBLE DEVICE

ATI TECHNOLOGIES ULC, Ma...

1. A bus protocol compatible device, comprising:
an encoder having an input for receiving a local clock signal, and an output;
a multiplexer having a first input for receiving a reference clock signal, a second input coupled to said output of said encoder,
a control input for receiving a select signal, and an output, wherein said multiplexer is responsive to said select signal
to select said reference clock signal in a first mode, and to select said output of said encoder in a second mode; and

a driver having an input coupled to said output of said multiplexer, and an output for coupling to a bus protocol link.

US Pat. No. 9,544,523

WIRELESS DISPLAY APPARATUS AND METHOD

ATI Technologies ULC, Ma...

1. A method for providing image data for a wireless monitor comprising:
in a device:
processing graphics drawing commands to render graphics data using a first processor to produce rendered graphics image data
and storing the rendered graphics image data to a frame buffer;

retrieving the rendered graphics image data from the frame buffer over a local bus using a second processor;
determining whether a wireless display mode has been selected;
in response to selection of the wireless display mode, encoding, by the second processor, the retrieved rendered graphics
image data to produce encoded graphics image data;

sending the encoded graphics image data to a wireless monitor using a short range wireless transmitter in response to selection
of the wireless display mode; and

wherein if a wireless display mode has been selected, controlling the rendered graphics image data to be restored to the frame
buffer.

US Pat. No. 9,837,398

METAL TRACK CUTTING IN STANDARD CELL LAYOUTS

Advanced Micro Devices, I...

1. An integrated circuit layout, comprising:
a standard cell;
a metal layer in the standard cell, the metal layer comprising a plurality of substantially parallel metal tracks placed in
the standard cell, wherein the metal tracks extend a width of the standard cell;

one or more active sections defined in the metal tracks;
one or more inactive sections defined in the metal tracks, wherein the inactive sections of the metal tracks are defined as
sections of the metal tracks outside of the active sections; and

at least one cut placed in at least one inactive region on at least one metal track, wherein the at least one cut is placed
to electrically isolate a portion of the at least one metal track in the at least one inactive region from an adjacent portion
of the at least one metal track.

US Pat. No. 9,627,281

SEMICONDUCTOR CHIP WITH THERMAL INTERFACE TAPE

Advanced Micro Device, In...

1. A method of manufacturing, comprising:
applying a thermal interface tape to a side of a semiconductor wafer including at least one semiconductor chip, the at least
one semiconductor chip having plural front side interconnects and plural backside interconnects, the thermal interface tape
being positioned on the at least one semiconductor chip over the backside interconnects; and

singulating the at least one semiconductor chip from the semiconductor wafer with at least a portion of the thermal interface
tape still attached to the semiconductor chip.

US Pat. No. 9,612,884

MEMORY MANAGEMENT IN GRAPHICS AND COMPUTE APPLICATION PROGRAMMING INTERFACES

Advanced Micro Devices, I...

1. A method for cloning a data object based on an original data object comprising:
creating a destination data object;
specifying data of the destination data object based on the original data object;
specifying a state of the data of the destination data object to an application programming interface (API); and
writing the data of the destination data object having the specified state to a memory.

US Pat. No. 9,563,211

MULTIPLE OUTPUT CHARGE PUMP WITH PEAK VOLTAGE FOLLOWING FREQUENCY DIVIDER CONTROL

ATI Technologies ULC, Ma...

1. An electronic device comprising:
a charge pump comprising a plurality of outputs to concurrently provide a plurality of different voltage levels;
a switch coupled to the plurality of outputs and comprising an output to provide a supply voltage that is selected from one
of the plurality of different voltage levels;

a controller to control the switch based on an analog input signal; and
a peak following frequency divider to limit a switching frequency of the plurality of different voltage levels to a threshold
frequency.

US Pat. No. 10,304,506

DYNAMIC CLOCK CONTROL TO INCREASE STUTTER EFFICIENCY IN THE MEMORY SUBSYSTEM

Advanced Micro Devices, I...

1. A system comprising:one or more processing units;
one or more memory devices;
a communication fabric comprising a plurality of domains that are configured to be power-gated;
a first clock circuit configured to provide a first clock signal to the communication fabric; and
a first bypass clock circuit, different from the first clock circuit, configured to provide a first bypass clock signal to the communication fabric;
wherein the system is configured to:
during an idle state, power down a subset of the plurality of domains of the communication fabric and disable the first clock signal to the subset of the plurality of domains; and
enter an active state responsive to determining a processing unit requests access to a first domain of the subset of the plurality of domains, and in response to entering the active state:
power up the first domain; and
supply one or more components of the first domain with the first bypass clock signal without re-enabling the first clock signal.

US Pat. No. 10,243,727

METHOD AND SYSTEM FOR CONSTANT TIME CRYPTOGRAPHY USING A CO-PROCESSOR

ATI Technologies ULC, Ma...

1. A method for secure communication, comprising:receiving encrypted data at a receiving device;
obtaining a random number by the receiving device, for at least one bit of the encrypted data;
modifying, by the receiving device, an execution of an Rivest-Shamir-Adleman (RSA) cryptographic algorithm on the at least one bit to obtain a randomized cryptographic algorithm based on the obtained random number wherein modifying the execution of a cryptographic algorithm further comprises:
determining a number of leading zeros of the encrypted data;
inserting a number of dummy cycles equal to the number of leading zeros into the execution of the cryptographic algorithm;
decrypting the encrypted data by executing the randomized cryptographic algorithm on the at least one bit of encrypted data to recover original data associated with the encrypted data, comprising:
subtracting the random number from an RSA exponent value to obtain a first exponent; and
multiplying a first exponential value having the first exponent by a second exponential value having a second exponent equal to the random number.

US Pat. No. 9,606,936

GENERALIZED CONTROL REGISTERS

Advanced Micro Devices, I...

1. A method, comprising:
maintaining at least one table, the at least one table including a plurality of concurrently available pointers, each being
associated with a corresponding one of a plurality of input/output (I/O) devices;

creating for each pointer a first translation from a virtual address to a first type physical address associated with a first
physical address space, and a second translation from the first type physical address to a second type physical address associated
with a second physical address space, wherein the second type physical address is different from the first type physical address;

receiving a first translation transaction from a first I/O device from the plurality of I/O devices, wherein the first translation
transaction includes a first concurrent context and a first guest virtual address to be translated;

isolating the first concurrent context residing in a shared memory based on the first translation transaction to form a first
isolated context;

receiving a second translation transaction from a second I/O device from the plurality of I/O devices, wherein the second
translation transaction includes a second concurrent context and a second guest virtual address to be translated;

isolating the second concurrent context residing in the shared memory based on the second translation transaction to form
a second isolated context;

performing the first translation, in response to the first translation transaction, of the first guest virtual address to
the first physical address based on the at least one table and the first isolated context to generate a first translation
result;

performing the first translation of the second guest virtual address to the first physical address based on the table and
the second isolated context to generate a second translation result;

performing the second translation of the first translation result and the second translation result to create a respective
third translation result and a fourth translation result; and

concurrently performing direct memory access of the second physical address space using the third translation result and the
fourth translation result by the first I/O device and the second I/O device.

US Pat. No. 9,588,734

TRANSLATION LAYER FOR CONTROLLING BUS ACCESS

ATI Technologies ULC, Ma...

1. An apparatus comprising:
a plurality of components;
a bus; and
a translation layer between the plurality of components and the bus, wherein the translation layer comprises:
a plurality of first buffers; and
a controller to assert at least one ready signal corresponding to at least one of the plurality of first buffers in response
to the at least one of the plurality of first buffers being less than full, wherein the at least one of the plurality of first
buffers receives data or control information from at least one corresponding component in response to the ready signal being
asserted concurrently with at least one valid signal asserted by the at least one corresponding component.

US Pat. No. 9,319,254

METHODS AND SYSTEMS FOR PROCESSING NETWORK MESSAGES IN AN ACCELERATED PROCESSING DEVICE

ATI Technologies ULC, Ma...

1. A method of processing network messages in an accelerated processing device (APD), comprising:
receiving a radio frequency (RF) signal;
assigning the received RF signal to a single instruction multiple data (SIMD) module in the APD for processing, wherein the
APD includes a plurality of SIMD modules;

extracting at least one physical layer message from the RF signal in an assigned SIMD module, wherein each SIMD module is
assigned to process a different type of physical layer message; and

processing the extracted at least one physical layer message in the assigned SIMD module to obtain data transmitted via the
RF signal, wherein any delayed physical layer messages are combined before processing to improve signal quality and each of
the SIMD modules perform parallel processing of the extracted at least one physical layer messages.

US Pat. No. 10,324,732

MULTI-PURPOSE POWER CONTROLLER AND METHOD

ATI TECHNOLOGIES ULC., M...

1. A method of performing power sequencing and boot strapping for internal and external blocks on a chipset, the method comprising:performing, by a system power controller and initializing block (SPCIB), power sequencing and boot strapping for the internal and external blocks of the chipset to generate a power-up template, wherein the internal and external blocks of the chipset include an application specific standard product (ASSP) block and a remainder of blocks that are required to be awake in a time frame after the ASSP block;
storing, by the SPCIB, the power-up template in a non-volatile wake-up table;
waking-up, by the SPCIB, the ASSP block according to the power-up template stored in the non-volatile wake-up table, wherein the ASSP block is required to be awake within a predetermined time frame; and
providing, by the ASSP block, power to the remainder of blocks after the ASSP block is awoken according to the power-up template.

US Pat. No. 10,169,843

TEMPORAL FOVEATED RENDERING USING MOTION ESTIMATION

Advanced Micro Devices, I...

1. A method comprising:estimating, at a motion estimator engine, a motion vector for each of a plurality of units of a first image, each unit comprising one or more pixels, by comparing corresponding units of a second image and a third image, wherein the second image comprises an image rendered immediately prior to the first image and the third image comprises an image rendered immediately prior to the second image;
identifying, at a rendering processor, for each of the plurality of units, a probability that pixels comprising the unit will be unrendered based on a magnitude of the motion vector for the unit; and
selectively rendering, at the rendering processor, the pixels of each unit of the plurality of units for a resulting rendered image based on the identified probabilities.

US Pat. No. 9,648,357

METHOD AND DEVICE FOR PROVIDING A VIDEO STREAM FOR AN OBJECT OF INTEREST

ATI Technologies ULC, Ma...

1. A method of ranking a video feed including:
obtaining one or more video feeds by a computing device, the video feeds depicting a first event;
comparing the one or more video feeds to each other; and
ranking the video feeds by the computing device, the ranking based, at least in part, upon input from a viewer indicating
an object of interest that is part of the event, the ranking providing a top ranked video feed, wherein ranking a video feed
as the top ranked video feed reflects the top ranked video feed's ability to depict the object of interest identified by the
viewer.

US Pat. No. 9,628,740

METHOD, APPARATUS AND MACHINE-READABLE MEDIUM FOR DESCRIBING VIDEO PROCESSING

ATI Technologies ULC, Ma...

1. A method comprising, at an intermediate video processor:
receiving video data;
receiving metadata describing video processing that has been earlier performed upon said video data by an upstream video processor;
determining at the intermediate video processor, from said received metadata describing video processing that has been earlier
performed upon said video data by said upstream video processor, additional video processing to be performed upon said video
data that has not yet been performed upon said video data;

performing said determined additional video processing to create processed video data at the intermediate video processor;
and

forming composite metadata that describes the processed video data from said received metadata and new metadata describing
the performed additional processing,

passing said processed video data and composite metadata to a downstream video processor;
wherein the composite metadata identifies, for each type of video processing indicated by the composite metadata, a video
processing component that performed the type of video processing.

US Pat. No. 9,582,846

GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER

ATI TECHNOLOGIES ULC, On...

1. A graphics processor, comprising:
a unified shader; and
an arbiter circuit operative to carry out an arbitration scheme to determine which of a plurality of inputs to provide to
the unified shader;

wherein the unified shader is operatively coupled to the arbiter circuit and comprises:
a processor unit configured to simultaneously perform vertex manipulation operations and pixel manipulation operations based
on the provided inputs to the unified shader.

US Pat. No. 10,021,413

APPARATUS AND METHOD FOR VIDEO DATA PROCESSING

ATI Technologies ULC, Ma...

1. An apparatus for facilitating processing image data of video frames comprising:a processing component configured to process a reference frame to produce an output frame by:
producing comparison metrics for a reference frame pel of a reference frame block of the reference frame, the comparison metrics being based on correlations between the reference frame block, a block of a prior output frame, a motion compensated output block of a motion compensated prior output frame, and a motion compensated input block of a motion compensated prior input frame, the comparison metrics including a first comparison metric based on a comparison of a block of pels of the reference frame with corresponding pels of the prior output frame, a second comparison metric based on a comparison of the block of pels of the reference frame with corresponding pels of the motion compensated prior output frame, and a third comparison metric based on a comparison of a pel of the block of pels of the reference frame and a plurality of neighboring reference frame pels;
compare the comparison metrics to noise value thresholds;
determine gain values based on the comparisons and based on one or more piecewise linear relationships between gain and comparison metric values; and
determine a pel of the output frame that corresponds to the reference frame pel based on the gain values, the gain values indicating the relative contributions, to the pel of the output frame, of the block from the prior output frame and the motion compensated block from the motion compensated prior output frame, the determining of the pel of the output frame also including determining whether the third comparison metric is used in determining a current noise level based on whether the second comparison metric is below a threshold, and determining the pel of the output frame based on the current noise level.

US Pat. No. 9,972,275

CONTENT PRESENTATION SYSTEM AND METHOD

ATI Technologies ULC, Ma...

1. A method of content presentation by a computer system, the method comprising:transferring, by a main processor of the computer system, content to at least one of: a graphics processor and storage accessible by the graphics processor in response to a request for presentation of the content in a main processor shutoff mode, the content being stored in the storage accessible by the graphics processor for presentation by the graphics processor in the main processor shutoff mode, the content comprising at least one of: multimedia data, text data, and image data;
shutting off the main processor in response to the transferring of content such that the main processor is disabled while the graphics processor presents the content stored in the storage; and
executing, in response to the request, a configuration program operative to configure settings for the presentation of the content by the graphics processor based on at least one user selection received via a user interface that selects a target storage location, the settings including an identification of the target storage location accessible by the graphics processor for storing the content.

US Pat. No. 9,924,134

DYNAMIC FRAME RATE ADJUSTMENT

ATI Technologies ULC, Ma...

1. In a device comprising an image rendering unit for communication with a display, a method for dynamically adjusting a frame
rate of the display by the image rendering unit, the method comprising:
determining dynamic frame rate capabilities of the display and an indication of a preferred method of how to dynamically adjust
the frame rate of the display as stored and communicated from the display;

determining an image frame rate of content to be provided to the display based on a rate at which a content source provides
frames for the display; and

providing the content to the display at an updated image frame rate based on the determined image frame rate, based on the
determined dynamic frame rate capabilities of the display and based on the determined indication of the preferred method of
how to dynamically adjust the display frame rate of the display.

US Pat. No. 9,911,397

EXTENDING THE RANGE OF VARIABLE REFRESH RATE DISPLAYS

ATI Technologies ULC, Ma...

1. A method of providing display content for a variable refresh rate display, the method comprising:
responsive to a new frame being rendered at a render rate outside of a display refresh rate range of the display while the
display is refreshing with a previous frame, providing content from the new frame corresponding to a location on the display
where the display is refreshing with the previous frame, wherein the display continues refreshing with the provided content
from the new frame from the location on the display where the display is refreshing with the previous frame;

determining that the new frame has been rendered at the render rate outside of the display refresh rate range of the display
while the display is refreshing with the previous frame; and

providing content from the new frame for the location on the display corresponding to the first scan line of the display when
it is determined that the new frame has not been rendered at the render rate outside of the display refresh rate range of
the display while the display is refreshing with the previous frame.

US Pat. No. 10,210,845

METHOD AND APPARATUS FOR COMPENSATING FOR VARIABLE REFRESH RATE DISPLAY RANGE LIMITATIONS

ATI Technologies ULC, Ma...

1. A method of providing display content for a variable refresh rate display, the method comprising:providing first content of a first frame on the display during a refresh safe period ranging between a minimum refresh period and a maximum refresh period;
determining a trigger event indicating that a second frame has been rendered during the refresh safe period;
providing, after the trigger event, second content of the second frame on the display during an intermediate refresh safe period that is greater than the minimum refresh period and less than the maximum refresh period, the intermediate refresh safe period variably set based on a time difference between when the first frame is presented for display and when the second frame is ready to be displayed.

US Pat. No. 10,085,017

BANDWIDTH SAVING ARCHITECTURE FOR SCALABLE VIDEO CODING SPATIAL MODE

Advanced Micro Devices, I...

1. A system for scalable video coding comprising:a base layer encoder configured to encode a frame to a base layer;
the base layer encoder further configured to generate and transmit inter-layer data to an enhanced layer encoder, wherein the inter-layer data includes any one or a combination of residual data, reconstruction data, or motion data and a bit indicating whether the inter-layer data includes residual data; and
the enhanced layer encoder configured to receive the inter-layer data from the base layer encoder and upsample the received inter-layer data, wherein the residual data or reconstruction data included in the inter-layer data is received from the base layer encoder in the same number of data channels;
the enhanced layer encoder further configured to encode the frame to an enhanced layer using the upsampled inter-layer data based on a micro-block (MB) type of the base layer, wherein the MB type of the base layer indicates whether the inter-layer data includes either residual data or reconstruction data, wherein the resolution of the enhanced layer is greater than the resolution of the base layer.

US Pat. No. 10,055,857

EXTENSION OF THE MPEG/SC3DMC STANDARD TO POLYGON MESHES

ATI Technologies ULC, Ma...

1. A polygon mesh compression system comprising:a processor configured to perform operations comprising:
traversing vertices of a plurality of polygons in a polygon mesh, in an order of traversal, the plurality of polygons comprising a plurality of non-triangle polygons;
partitioning the polygon mesh comprising the plurality of non-triangle polygons into an ordered set of polygon fans in the order of traversal, at least one of the polygon fans having a plurality of polygons, each polygon fan being defined by corresponding vertices of one or more polygons in the polygon fan in the order of traversal and, for the at least one polygon fan having the plurality of polygons, the order of traversal starts from a common vertex of the plurality of polygons in the at least one polygon fan;
converting the polygon mesh comprising the plurality of non-triangle polygons to a triangle mesh by:
tessellating each non-triangle polygon in the ordered set of polygon fans into triangles from the common vertex to corresponding vertices of each non-triangle polygon in the order of traversal; and
generating an ordered set of triangle fans in the order of traversal; and
an encoder configured to receive the triangle mesh and the ordered set of triangle fans and compress the polygon mesh using the triangle mesh and the ordered set of triangle fans.

US Pat. No. 9,906,239

GPU PARALLEL HUFFMAN DECODING

ATI Technologies ULC, Ma...

1. A system comprising:
a plurality of execution units; and
a memory;
wherein the system is configured to:
partition an encoded bitstream into a plurality of chunks;
assign a separate chunk of the encoded bitstream and an extra portion of an adjacent chunk to each execution unit of the plurality
of execution units;

decode, by each execution unit, the chunk and the extra portion of the adjacent chunk assigned to the execution unit, wherein
decoding is performed in parallel by the plurality of execution units;

determine, from each decoded extra portion, where incorrectly decoded data ends and where correctly decoded data begins in
a corresponding chunk; and

retain correctly decoded data in the memory and discard incorrectly decoded data.

US Pat. No. 9,819,962

EFFICIENT LOW-COMPLEXITY VIDEO COMPRESSION

ATI TECHNOLOGIES ULC, Ma...

1. A method of compressing motion estimation information in video processing, the method comprising:
determining and storing a distortion value for each trial motion vector in a plurality of trial motion vectors, wherein each
trial motion vector specifies a position of a search region relative to a reference frame; and

compressing each of the distortion values as a fixed number of bits based upon a minimum distortion value amongst the stored
distortion values, and re-storing each compressed distortion value in place of its uncompressed value,

wherein compressing each of the distortion values comprises determining and storing binary integers p and q, both having user-defined
bit lengths, the binary integer p including a series of bits, and the binary integer q determining, along with a fixed compression
shift value s, the degree to which the binary integer p is shifted; and

wherein the compressed distortion value exceeds the minimum distortion value by the value of p shifted based on q and s.

US Pat. No. 9,785,218

PERFORMANCE STATE SELECTION FOR LOW ACTIVITY SCENARIOS

Advanced Micro Devices, I...

1. A method comprising:
tracking an idle state of a hardware component and generating a tracked level of idleness;
comparing the tracked level of idleness with a first threshold;
causing a power state of the hardware component to be limited to a low power state if the tracked level of idleness is above
the first threshold, to thereby prevent the low power state of the hardware component from being increased in response to
detected activity; and

comparing the tracked level of idleness with a second threshold and removing a power state limit if the tracked level of idleness
is below the second threshold.

US Pat. No. 9,576,923

SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION AND POLYMER FILM

ATI Technologies ULC, Ma...

10. A method of coupling a semiconductor chip to a circuit board, the semiconductor chip having a first underbump metallization
layer on a semiconductor chip, the first underbump metallization layer having a hub, a first portion extending laterally from
the hub, and a spoke connecting the hub to the first portion, and a polymer layer on the first underbump metallization layer,
the polymer layer including a first opening in alignment with the hub and a second opening in alignment with the spoke, and
a second underbump metallization layer in the first opening, comprising:
removing via the second opening a portion of the spoke to sever the connection between the hub and the first portion;
coupling a solder structure to the second underbump metallization layer; and
coupling the solder structure to the circuit board.

US Pat. No. 10,310,985

SYSTEMS AND METHODS FOR ACCESSING AND MANAGING A COMPUTING SYSTEM MEMORY

ATI Technologies ULC, Ma...

1. A system comprising:a first processor and a second processor; and
a first memory and a second memory;
wherein the first processor is configured to:
maintain a request log of entries identifying requests that have been made to pages stored in the second memory;
generate an indication for the second processor to process the request log when the number of entries in the request log reaches a first threshold;
wherein the second processor is configured to:
increase the first threshold responsive to determining a rate of indication generation is greater than a given range; and
decrease the first threshold responsive to determining the rate of indication generation is less than the given range;
process the request log responsive to detecting the indication; and
determine whether to migrate physical pages from the second memory to the first memory.

US Pat. No. 10,198,219

METHOD AND APPARATUS FOR EN ROUTE TRANSLATION IN SOLID STATE GRAPHICS SYSTEMS

ATI Technologies ULC, Ma...

1. A solid state graphics (SSG) device, comprising:at least one first memory architecture and an associated first memory architecture controller;
at least one graphics processing unit (GPU);
a second memory architecture associated with each GPU;
a data translator; and
an expansion bus interface connected to each associated first memory architecture controller, the at least one GPU, and the data translator,
wherein the data translator:
en route detects a data form of data read from the at least one first memory architecture in response to a data transfer command and received at the data translator via the associated first memory architecture controller and expansion bus interface;
en route determines if read data is in clear form for a target device;
en route applies data processing to the read data to generate clear data with respect to the target device when the read data is not in clear form; and
transfers the clear data to a target memory associated with the target device.

US Pat. No. 10,095,295

METHOD AND APPARATUS FOR POWER MANAGEMENT OF A GRAPHICS PROCESSING CORE IN A VIRTUAL ENVIRONMENT

Advanced Micro Devices, I...

1. A method comprising:processing a plurality of virtual machine power control setting requests including a first virtual machine power control setting request and a second virtual machine power control setting request by blending the plurality of virtual machine power control setting requests together to determine a power control request for a power management unit of a graphics processing core, wherein each of the first and second virtual machine power control setting requests is associated with a respective virtual machine requirement defined by a minimum frequency and a maximum frequency and wherein blending includes determining an overlap of the minimum and maximum frequencies of the first virtual machine power control setting request and the second virtual machine power control setting request; and
controlling power levels of the graphics processing core with the power management unit based on the determined overlap of the minimum and maximum frequencies between the first and second virtual machine power control setting requests.

US Pat. No. 9,977,854

INTEGRATED CIRCUIT IMPLEMENTING STANDARD CELLS WITH METAL LAYER SEGMENTS EXTENDING OUT OF CELL BOUNDARY

ATI Technologies ULC, Ma...

1. An integrated circuit structure comprising:a first cell extending along orthogonal first and second directions of a semiconductor substrate and having a cell boundary, the first cell comprising:
a first metal segment at a first metal track of an M1 metal layer, the first metal segment extending along the first direction and terminating a specified first distance beyond a first edge of the cell boundary; and
a pin extending outside of the cell boundary of the first cell and coupled to the first metal segment.

US Pat. No. 9,888,256

TECHNIQUE TO CONSTRAIN A VIDEO SLICE SIZE WITH REDUCED PERFORMANCE PENALTY ON PIPELINED ENCODER ARCHITECTURES

ATI Technologies ULC, Ma...

1. A method of encoding video data, comprising:
encoding macroblocks in a data pipeline to form a first video slice of a plurality of video slices associated with a frame
of video;

responsive to a macroblock overshoot condition indicating that the first video slice has reached a maximum number of macroblocks,
forming a second video slice that comprises at least one of: an overshooting macroblock that caused the macroblock overshoot
condition; and the encoded macroblocks, without re-encoding the at least one of: the overshooting macroblock and the encoded
macroblocks.

US Pat. No. 9,798,353

COMMAND PROTOCOL FOR ADJUSTMENT OF WRITE TIMING DELAY

Advanced Micro Devices, I...

1. An apparatus for adjusting write timing, the apparatus comprising:
an address/control bus port comprising circuitry configured to transmit a signal to concurrently enable a write clock data
recovery (WCDR) mode of operation and an active mode of operation in a memory device;

a data bus port comprising circuitry configured to transmit a data signal to the memory device during the active mode of operation;
and

a WCDR signal bus port comprising circuitry configured to transmit WCDR data to the memory device during the WCDR mode of
operation;

wherein the WCDR data includes information indicating a phase difference between the data signal and a clock signal;
the WCDR signal bus port further comprising circuitry configured to receive a phase error signal in response to the WCDR data.

US Pat. No. 9,734,549

MEMORY DEVICE FOR PROVIDING DATA IN A GRAPHICS SYSTEM AND METHOD AND APPARATUS THEREOF

ATI Technologies ULC, Ma...

1. A method, carried out by a memory controller, the method comprising: arbitrating access to at least a portion of unified
memory among a plurality of client data access requests from a plurality of clients to a plurality of memory channels, wherein
the plurality of memory channels are accessible bypassing arbitration of the plurality of client data access requests to said
at least a portion of the unified memory in response to a CPU data access request to said at least same portion of the unified
memory; and controlling the plurality of memory channels to access client data address space and CPU data address space of
the same unified memory simultaneously.

US Pat. No. 9,530,175

GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER

ATI Technologies ULC, On...

1. A graphics processor, comprising:
an arbiter operative to carry out an arbitration scheme to determine one of a plurality of inputs; and
a unified shader, operatively coupled to the arbiter, comprising:
a processor unit configured to simultaneously perform vertex manipulation operations and pixel manipulation operations based
on a plurality of inputs.

US Pat. No. 10,659,796

BANDWIDTH SAVING ARCHITECTURE FOR SCALABLE VIDEO CODING SPATIAL MODE

Advanced Micro Devices, I...

1. A system configured to perform scalable video encoding comprising:a memory; and
a processing unit, wherein the processing unit is configured to:
receive video data, wherein the video data includes one or more frames;
encode at least one frame to a base layer;
generate inter-layer data based on the at least one frame, wherein the inter-layer data includes any one or a combination of residual data, reconstruction data, and motion data, wherein the inter-layer data includes a bit indicating whether the inter-layer data includes residual data;
upsample the inter-layer data; and
encode the at least one frame to an enhanced layer using the upsampled inter-layer data based on a block type of the base layer, wherein the block type of the base layer indicates whether the inter-layer data includes either residual data or reconstruction data, wherein the resolution of the enhanced layer is greater than the resolution of the base layer.

US Pat. No. 10,535,178

SHADER WRITES TO COMPRESSED RESOURCES

Advanced Micro Devices, I...

1. A processor comprising:a cache; and
one or more shader units coupled to the cache;
wherein responsive to a write request targeting a compressed surface, a shader unit of the one or more shader units is configured to:
identify a first block of the compressed surface targeted by the write request;
responsive to detecting all data of the first block is set to a single value:
prevent logic for fetching and decompressing the first block from being activated;
compress data of the write request to form a second block; and
write the second block to the cache without fetching or decompressing the first block.

US Pat. No. 10,242,647

THREE DIMENSIONAL (3-D) LOOK UP TABLE (LUT) USED FOR GAMUT MAPPING IN FLOATING POINT FORMAT

ATI Technologies ULC, Ma...

1. A method comprising:determining, at a data segmenter of an electronic device, indices using numbers of most significant bits (MSBs) of fractional values of floating-point representations of component values of an input color that are selected based on exponent values of the floating-point representations, wherein the component values are defined according to a source gamut;
determining, at the data segmenter, offsets associated with the indices using subsets of the fractional values; and
mapping the input color to an output color defined according to a destination gamut based on a location in a three-dimensional (3-D) look up table (LUT) indicated by the indices and offsets.

US Pat. No. 10,209,991

INSTRUCTION SET AND MICRO-ARCHITECTURE SUPPORTING ASYNCHRONOUS MEMORY ACCESS

Advanced Micro Devices, I...

1. A computing system comprising:a memory; and
a processing unit;
wherein the processing unit is configured to:
detect a non-blocking load instruction that includes an address of data stored in the memory and an identification of one or more instructions configured to operate on the data;
convey a request to the memory for the data;
process instructions that follow the non-blocking load instruction in program order, prior to fetching the one or more instructions configured to operate on the data;
fetch the one or more instructions for execution using the identification, responsive to detecting the data has returned from the memory; and
retire the non-blocking load instruction after a successful commit, wherein the successful commit comprises verifying address translations are available for the data and the one or more instructions.

US Pat. No. 10,176,122

DIRECT MEMORY ACCESS AUTHORIZATION IN A PROCESSING SYSTEM

Advanced Micro Devices, I...

1. A method, comprising:receiving, at an input/output memory management unit (IOMMU) of a processor, a direct memory access request from an input/output (IO) device to access a memory space within memory, wherein the direct memory access request comprises a memory address value and a requestor ID, wherein the IOMMU provides an interface between the IO device and a memory controller implemented using at least one hardware processor;
in response to the direct memory access request determining, at the IOMMU, an identification tag value associated with the requestor ID and providing the identification tag value to the memory controller; and
accessing, at the memory controller, data at the memory address value of the memory space using a security key corresponding to the identification tag value.

US Pat. No. 10,162,765

ROUTING DIRECT MEMORY ACCESS REQUESTS IN A VIRTUALIZED COMPUTING ENVIRONMENT

Advanced Micro Devices, I...

1. A method for calculating a physical address based on a received virtual address, comprising:calculating, by a device, an offset value based on the received virtual address,
the offset value being equal to the received virtual address minus a base address;
determining, by the device and when the offset value is negative, that the received virtual address is outside a predetermined range;
comparing, by the device and when the offset value is zero or positive, the offset value to a length value,
the received virtual address being outside the predetermined range when the offset value is greater than the length value, and
the received virtual address being within the predetermined range when the offset value equals zero or when the offset value is less than the length value;
determining, by the device and when the received virtual address is within the predetermined range, whether an access type associated with the received virtual address is permitted;
calculating, by the device, the physical address via a first processing path when the access type is not permitted or when the received virtual address is outside the predetermined range; and
calculating, by the device, the physical address, via a second processing path and based on the offset value and a relocation value, when the access type is permitted,
the second processing path being faster than the first processing path.

US Pat. No. 10,103,837

ASYNCHRONOUS FEEDBACK TRAINING

Advanced Micro Devices, I...

1. A system comprising:a transmitter; and
a receiver coupled to the transmitter via a communication channel including one or more data lanes;
wherein the transmitter is configured to:
initiate an asynchronous feedback training sequence by transmitting a training sequence indication as a plurality of bits during a supercycle comprising a first multi-bit sequence followed by a second multi-bit sequence, where the first multi-bit sequence and the second multi-bit sequence are of opposite polarity and a transition from the first multi-bit sequence to the second multi-bit sequence occurs at a midpoint of the supercycle; and
transmit a test pattern on a first lane of the channel at the end of the supercycle; and
wherein the receiver is configured to:
receive the training sequence indication;
sample a state of the first lane at an end of each supercycle;
responsive to determining that a transition occurs on the first lane between two successive tests:
sample the state of the first lane at an end of each supercycle;
if the state of the first lane does not change for a predetermined number of samples, determine the training sequence indication has been detected; and
if the state of the first lane does change during the predetermined number of samples, determine the training sequence indication has not been detected;
capture the test pattern responsive to detecting the training sequence indication; and
convey an error indication to the transmitter via the first lane that indicates whether any errors were detected in the test pattern;
wherein each of the transmitter and the receiver includes a supercycle counter for counting supercycles, with a single supercycle corresponding to N clock cycles of a system clock, where N is an integer greater than 1.

US Pat. No. 10,097,835

CONTENT-ADAPTIVE B-PICTURE PATTERN VIDEO ENCODING

Advanced Micro Devices, I...

1. A method for content adaptive video encoding, the method comprising:selecting a set of successive pictures;
forming a plurality of distinct group of pictures (GOP) decompositions of the set of successive pictures, at least one of the GOP decompositions including a plurality of GOPs;
determining, for each GOP decomposition in the plurality of distinct GOP decompositions, a GOP decomposition rate-distortion (RD) cost by determining a GOP RD cost for each GOP in that GOP decomposition, the RD cost for each GOP being based on a bit rate at which the GOP is encoded, and a measure of distortion associated with the GOP, the measure of distortion being based on a difference between an original version of at least one picture in the GOP and an encoded version of the picture; and
selecting a GOP decomposition from the plurality of distinct GOP decompositions for use in encoding the successive pictures, wherein the GOP decomposition is selected based on having a lowest GOP decomposition cost in the plurality of distinct GOP decompositions.

US Pat. No. 10,056,027

VIRTUALIZED DISPLAY OUTPUT PORTS CONFIGURATION

ATI Technologies ULC, Ma...

1. A monitor, comprising:an internal display;
a source display port communicatively coupled to a source device;
an output display port communicatively coupled to an external display via a physical link;
a memory, wherein the memory stores DisplayPort Configuration Data (DPCD) associated with the output display port and stores Virtual DPCD (VDPCD) associated with the internal display; and
a processor communicatively coupled to the source display port, the output display port and the memory, wherein the processor:
receives packetized data from the source device via the source display port,
selectively transmits the packetized data to the external display via the physical link based on the DPCD, and
selectively transmits the packetized data to the internal display based on the VDPCD, wherein the VDPCD comprises information for configuring the internal display to display the packetized data.

US Pat. No. 9,965,392

MANAGING COHERENT MEMORY BETWEEN AN ACCELERATED PROCESSING DEVICE AND A CENTRAL PROCESSING UNIT

Advanced Micro Devices, I...

9. A non-transitory computer-readable storage medium having instructions for execution by a computing device cause the computing device to perform operations that cause an accelerated processing device (APD) to manage a coherent memory between a central processing unit (CPU)—and the APD, the APD performing the method comprising:monitoring a flag register to determine whether data stored in a coherent memory is available for processing, wherein the flag register notifies the APD that data is available for processing in the coherent memory;
acquiring an address pointer for the data in the coherent memory from an address processing device in response to determining data stored in the coherent memory is available for processing;
fencing outstanding read requests associated with the data stored in the coherent memory in response to the determining that data stored in the coherent memory is available for processing by the APD;
processing the data stored in the coherent memory using the APD;
executing a store release instruction for the data stored in the coherent memory that has been processed by the APD;
flushing processed data that is stored in an APD cache and storing the flushed data to the coherent memory; and
setting a synchronization variable by the APD to confirm that the data stored in the coherent memory is valid, wherein the synchronization variable is associated with the flag register.

US Pat. No. 9,736,477

PERFORMING VIDEO ENCODING MODE DECISION BASED ON MOTION ACTIVITY

ATI TECHNOLOGIES ULC, Ma...

1. A method of performing video encoding mode decisions, the method comprising:
receiving a down-scaled frame that includes a macroblock corresponding to a first subset of macroblocks in a full-scale frame;
determining a first motion vector for each macroblock of the first subset of macroblocks in the full-scale frame;
determining a second motion vector for each macroblock of a second subset of macroblocks in the full-scale frame, the second
subset being adjacent to and sharing a common border with the first subset of macroblocks in the full-scale frame;

calculating a first average motion vector of the first subset of macroblocks based on the first motion vectors of the macroblocks
of the first subset of macroblocks;

calculating a second average motion vector of the second subset of macroblocks based on the second motion vectors of the macroblocks
of the second subset of macroblocks;

determining whether a boundary region, indicating a level of motion for the macroblock in the down-scaled frame, exists between
the first subset of macroblocks and the second subset of macroblocks based on a difference between the first average motion
vector and the second average motion vector; and

generating a predicted macroblock for the macroblock in the down-scaled frame by: (i) selecting, when the boundary region
is determined, an encoding mode from a first number of selectable encoding modes, and performing a rate distortion assessment
on each of the first number of selectable encoding modes; and (ii) selecting, when the boundary region is not determined,
the encoding mode from a second number of selectable encoding modes and performing a rate distortion assessment on each of
the second number selectable encoding modes, the second number of selectable encoding modes being less than the first number
of selectable encoding modes.

US Pat. No. 9,728,518

INTERCONNECT ETCH WITH POLYMER LAYER EDGE PROTECTION

ATI Technologies ULC, Ma...

8. A method of manufacturing, comprising:
applying a polyimide layer to a passivation structure of a silicon wafer, the silicon wafer having first and second semiconductor
chips separated by a dicing street;

patterning a first opening in the polyimide layer with opposing edges pulled back from the dicing street and second opening
exposing a first portion of the passivation structure;

applying a mask over the first opening; and
etching the first portion of the passivation structure to expose an underlying portion of the silicon wafer while using the
polyimide layer as an etch mask.

US Pat. No. 10,659,724

METHOD AND APPARATUS FOR PROVIDING DROPPED PICTURE IMAGE PROCESSING

ATI Technologies ULC, Ma...

1. An apparatus comprising:a frame rate converter operative to generate a corrupted picture indication information indicating a corrupted or repeated source frame, and to adaptively create a plurality of frame rate converted frames by using a plurality of alternate source frames output from a decoder instead of using a replacement source frame, the plurality of alternate source frames used to create a frame rate converted frame in the plurality of frame rate converted frames affected by the corrupted or repeated source frame including at least a neighboring previous source frame and a non-neighboring future source frame with respect to the frame rate converted frame, as well as a previous source frame prior to the neighboring previous source frame and a future source frame subsequent to the non-neighboring future source frame, wherein the neighboring previous source frame and the non-neighboring future source frame with respect to the frame rate converted frame are non-sequential, the neighboring previous source frame and the previous source frame prior to the neighboring previous source frame are sequential, and the non-neighboring future source frame and the future source frame subsequent to the non-neighboring future source frame are sequential; and
wherein the frame rate converter is operative to create the plurality of frame rate converted frames by generating motion vector information using the plurality of alternate source frames, and wherein the frame rate converter is operative to output the plurality of frame rate converted frames to a display.

US Pat. No. 10,545,800

DIRECT DOORBELL RING IN VIRTUALIZED PROCESSING DEVICE

ATI Technologies ULC, Ma...

1. A method for sending a notification, by a first processing engine, to a second processing engine, that work is ready to be performed in a virtualized environment, the method comprising:issuing a first write request of a first doorbell value to a first address specified in a guest physical address space;
comparing the first address to one or more doorbell base addresses to determine that the first address refers to a first doorbell of the second processing engine;
determining that a first offset of the first address matches in a set of allowed offsets for doorbells specified by guest physical addresses; and
responsive to the determining, causing the first write request to occur, resulting in the first doorbell value being written to a doorbell memory for the second processing engine, wherein the doorbell memory is identified by the first address specified in the guest physical address space, without translation into a system physical address space.

US Pat. No. 10,545,887

MULTIPLE LINKED LIST DATA STRUCTURE

ATI Technologies ULC, Ma...

1. A buffer comprising:a memory comprising a plurality of storage locations configured to store entries of one or more data structures;
a first plurality of pointers configured to store at least two head pointers and two tail pointers corresponding to at least two linked lists in the memory, wherein the first plurality of pointers correspond to a first single requestor, wherein the at least two linked lists correspond to a single logical data structure in the memory, wherein each entry of the single logical data structure is configured to store a requestor identifier of the first single requestor; and
control logic configured to alternate between the at least two linked lists when accessing the single logical queue in the memory.

US Pat. No. 10,534,730

STORING MICROCODE FOR A VIRTUAL FUNCTION IN A TRUSTED MEMORY REGION

ATI Technologies ULC, Ma...

15. An apparatus comprising:a first processor that has a trusted relationship with a trusted memory region (TMR) comprising a first region for storing microcode used to execute a microcontroller on a second processor and a second region for storing data associated with the microcontroller and configured to be modifiable by the microcode, wherein the microcontroller supports a virtual function; and
an access controller configured by the first processor to selectively provide the microcontroller with access to the TMR in response to a request from the microcontroller based on whether the request is to write in the first region.

US Pat. No. 10,424,269

FLEXIBLE ADDRESSING FOR A THREE DIMENSIONAL (3-D) LOOK UP TABLE (LUT) USED FOR GAMUT MAPPING

ATI Technologies ULC, Ma...

1. A method comprising:identifying a plurality of vertices in a three-dimensional (3-D) look up table (LUT) based on a number (m) of most significant bits (MSBs) of three coordinate values representative of an input color and a non-zero integer (p), wherein the three coordinate values are determined by a source gamut;
retrieving component values representative of a plurality of second colors determined by a destination gamut, wherein the component values are stored at memory locations associated with the plurality of vertices;
scaling the component values in the source gamut by a factor determined by the non-zero integer (p); and
mapping the input color to an output color in the destination gamut based on the component values, wherein a number of vertices along each dimension of the 3-D LUT is equal to (2m+1+4p).

US Pat. No. 10,218,273

ON DIE VOLTAGE REGULATION WITH DISTRIBUTED SWITCHES

Advanced Micro Devices, I...

1. A distributed voltage regulator comprising:a plurality of switches distributed in an area receiving a regulated voltage, each of the switches have one of N resistance values, N being an integer, the switches coupled to receive an unregulated voltage;
a plurality of switch control lines coupled to selectively enable selected ones of the plurality of switches according to values of respective ones of the switch control lines, each of the plurality of switches being coupled to receive one of the switch control lines, the selected ones of the switches to collectively convert the unregulated voltage to the regulated voltage; and
a selector circuit coupled to receive a first group of control lines and a second group of control lines and to supply a selected one of the first group and the second group of control lines as the switch control lines.

US Pat. No. 10,198,358

SYSTEM AND METHOD OF TESTING PROCESSOR UNITS USING CACHE RESIDENT TESTING

ADVANCED MICRO DEVICES, I...

1. An integrated circuit (IC) for processor unit testing using cache resident testing, the integrated circuit comprising:a plurality of portions of memory, including a cache configured to store a test program including a plurality of different types of instructions configured to cause one or more components of the IC to implement one or more functions by executing a plurality of memory access requests to access the plurality of portions of memory;
one or more processing units configured to execute the test program and generate one or more results indicative of whether the test program executes correctly; and
an electronic circuit configured to, in response to a determination that one of the plurality of memory access requests is a request to access a memory location not resident in the cache:
redirect said one memory access request to the cache, by redirecting the one memory access request from the memory location not resident in the cache to a memory location that is resident in the cache on a condition that said one memory access request is a request to access one of the plurality of portions of memory of the IC different from the cache; and
not redirect said one memory access request to the cache on a condition that said one memory access request is a request to access an outside component, in communication with the IC and remote from the IC, being used to implement the test program.

US Pat. No. 10,120,430

DYNAMIC RELIABILITY QUALITY MONITORING

Advanced Micro Devices, I...

1. A semiconductor chip comprising:a functional unit;
a monitor comprising circuitry configured to:
monitor an actual usage of the functional unit;
compare the actual usage of the functional unit to an expected usage of the functional unit, wherein the expected usage is based at least in part on an age of the functional unit; and
provide information corresponding to said compare;
a power manager comprising circuitry configured to:
update operating parameters of the functional unit to change power consumption for the functional unit responsive to the information; and
send the updated operating parameters to the functional unit;
wherein in response to determining the actual usage is less than the expected usage, the updated operating parameters include maximum values for the operating parameters that are greater than current maximum values for the operating parameters.

US Pat. No. 9,793,199

CIRCUIT BOARD WITH VIA TRACE CONNECTION AND METHOD OF MAKING THE SAME

ATI Technologies ULC, Ma...

1. A method of manufacturing, comprising:
forming a first interconnect layer of a circuit board by forming a first conductor trace with a first segment that does not
include a via land, a second conductor trace with a second segment that does not include a via land, third and fourth conductor
traces in spaced apart relation and in between the first and second segments and an insulating layer over the first, second,
third and fourth conductor traces; and

forming a first via on the first segment and a second via on the second segment but without forming a third via between the
first and second vias wherein the first via is formed with a groove to engage the first segment.

US Pat. No. 10,656,696

REDUCING CHIPLET WAKEUP LATENCY

Advanced Micro Devices, I...

1. A system comprising:one or more processing nodes, wherein each processing node of the one or more processing nodes comprises one or more processor cores;
a communication fabric coupled to the one or more processing nodes via one or more link interfaces; and
a power management unit;
wherein the power management unit is configured to:
detect a request to wake up a processor core of a processing node;
determine that a link interface that connects the communication fabric to the processing node is in a non-operational state; and
send an out-of-band signal over the link interface to wake up the processor core prior to the link interface returning to an operational state.

US Pat. No. 10,602,158

METHOD FOR MAXIMIZING VIDEO SLICE SIZE CONSTRAINT

ATI Technologies ULC, Ma...

1. A method for encoding, comprising:dividing a received video frame into a plurality of slices including a first slice, wherein each of the plurality of slices includes a plurality of macroblocks;
predicting a first number of bits that are required to encode a first macroblock based on a quantization parameter, wherein the first macroblock is from the plurality of macroblocks of the first slice;
on a condition that the number of bits predicted to encode the first macroblock is less than a maximum slice size, predicting, using the quantization parameter, a total number of bits required to encode each of an additional predetermined number of macroblocks subsequent to the first macroblock in the plurality of macroblocks of the first slice;
on a condition that the total number predicted is greater than the maximum slice size:
decreasing the additional predetermined number of macroblocks to a decreased number of macroblocks,
recalculating the total number of bits for the decreased number of macroblocks, and
reevaluating the quantization parameter based on the recalculated total number of bits; and
on a condition that the total number predicted is less than the maximum slice size, encoding the first macroblock using the quantization parameter.

US Pat. No. 10,268,620

APPARATUS FOR CONNECTING NON-VOLATILE MEMORY LOCALLY TO A GPU THROUGH A LOCAL SWITCH

ATI Technologies ULC, Ma...

1. A solid state graphics (SSG) card, comprising:a plurality of first memory architecture units;
at least one graphics processing unit (GPU);
a second memory architecture associated with each GPU;
a local switch coupled to each of the first memory architecture units and the at least one GPU; and
a redundant array of independent drives (RAID) assist unit connected to each of the plurality of first memory architecture units and the local switch, the RAID assist unit segmenting and distributing a data transaction amongst the plurality of first memory architecture units,
wherein the first memory architecture units and the local switch directly process data transactions between a second memory architecture and the first memory architecture units in response to a data transfer command.

US Pat. No. 10,241,925

SELECTING A DEFAULT PAGE SIZE IN A VARIABLE PAGE SIZE TLB

ATI Technologies ULC, Ma...

1. A system comprising:at least one processor;
a memory subsystem which stores a plurality of page sizes; and
a first translation lookaside buffer (TLB) comprising a plurality of entries;
wherein the first TLB is configured to:
allocate a first entry of the TLB responsive to detecting a miss for a first address translation request, wherein the first address translation request is generated by a first processor;
prior to determining a page size targeted by the first address translation request, specify, in the first entry, that the first request targets a page of a first page size in the memory subsystem; and
responsive to determining that the first address translation request targets a second page size different from the first page size, reissue the first address translation request to the first TLB with an indication that the first address translation request targets the second page size.

US Pat. No. 10,230,370

DATA TRANSMISSION WITH POWER SUPPLY NOISE COMPENSATION

ATI TECHNOLOGIES ULC, Ma...

1. A data transmission system comprising:a transmission circuit comprising:
a first driver having an input for receiving a first transmit data signal, an output, a positive power supply terminal for receiving an input/output (I/O) power supply voltage, and a negative terminal for receiving an I/O ground voltage;
a second driver having an input for receiving said I/O power supply voltage, an output, and a positive power supply terminal for receiving said I/O power supply voltage, wherein said transmission circuit does not use said second driver during transmission of data; and
a third driver having an input for receiving said I/O ground voltage, an output, and a negative power supply terminal coupled to said I/O ground voltage, wherein said transmission circuit does not use said third driver during transmission of data, and
a reception circuit coupled to said output of said first driver, said output of said second driver, and said output of said third driver, wherein said reception circuit forms a reference voltage based an average of signal content below a predetermined frequency of outputs of said second and third drivers, and receives a signal from said output of said first driver using said reference voltage.

US Pat. No. 10,176,548

GRAPHICS CONTEXT SCHEDULING BASED ON FLIP QUEUE MANAGEMENT

ATI TECHNOLOGIES ULC, Ma...

1. A method comprising:receiving, from a first graphics context in execution, a request to modify contents of a first frame buffer;
determining whether the first frame buffer is in use;
when the first frame buffer is determined to be in use, suspending execution of the first graphics context;
while the execution of the first graphics context is suspended, executing a second graphics context at a processor until the second graphics context is stalled when attempting to execute a change to contents of a second frame buffer that is in use; and
when the second graphics context stalls, resuming execution of the first graphics context at the processor based on determining that the first frame buffer is no longer in use.

US Pat. No. 10,121,477

VIDEO ASSISTED DIGITAL AUDIO WATERMARKING

ATI Technologies ULC, Ma...

1. An audio watermarking embedder comprising: an interface configured to receive an identification of video content represented by data in a video frame; and control logic configured to: select a watermark embedding parameter used for embedding an audio watermark in an audio frame based at least in part on the identification of video content; embed the audio watermark in an audio frame corresponding to the video frame based at least in part on the selected watermark embedding parameter; embed a first amount of data of the audio watermark in the audio frame based at least in part on detecting the identification of video content represents a first scene; and embed a second amount of data different from the first amount of data of the audio watermark in the audio frame based at least in part on detecting the indication of video content represents a second scene different from the first scene.

US Pat. No. 10,714,056

EXTENDING THE RANGE OF VARIABLE REFRESH RATE DISPLAYS

ATI Technologies ULC, Ma...

1. A method of providing display content for a variable refresh rate display, the method comprising:providing a first content of a first frame on the display during an active refresh cycle where the display is refreshing with the first content of the first frame;
determining whether a second frame has been rendered at a render rate within a display refresh rate range of the display during the active refresh cycle, the second frame being after the first frame; and
when the second frame has been rendered at the render rate within the display refresh rate range of the display during the active refresh cycle, providing a second content of the second frame during a next refresh cycle of the display at a location on the display where the first content of the first frame is displayed such that the display is continuously refreshing with the second content of the second frame, thereby preventing an image tear on the display.

US Pat. No. 10,324,860

MEMORY HEAPS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM

Advanced Micro Devices, I...

1. A method for allocating memory in a processing system having at least two processors, the method comprising:receiving a memory access request for a shared memory address from one processor of the at least two processors; and
mapping the shared memory address to at least two virtual memory pools of a plurality of virtual memory pools, wherein each virtual memory pool is associated with at least one memory resource; and
providing a mapping result to the one processor of the at least two processors.

US Pat. No. 10,291,931

DETERMINING VARIANCE OF A BLOCK OF AN IMAGE BASED ON A MOTION VECTOR FOR THE BLOCK

ATI TECHNOLOGIES ULC, Ma...

1. A method for determining a variance for a pixel block, the method comprising:identifying a motion vector for the pixel block, the motion vector being associated with a second pixel block of a reference frame;
obtaining a cost for the pixel block, the cost being previously determined by the identifying of the motion vector, the cost indicating a degree of similarity between the pixel block and the second pixel block; and
determining the variance for the pixel block based on the cost, wherein determining the variance for the pixel block based on the cost comprises:
determining that the cost is above a first threshold but below a second threshold; and
responsive to determining that the cost is above the first threshold but below the second threshold, determining the variance for the pixel block as being equal to a variance of the second pixel block of the reference frame multiplied by a correlation factor.

US Pat. No. 10,198,283

EXCLUSIVE ACCESS TO SHARED REGISTERS IN VIRTUALIZED SYSTEMS

ATI Technologies ULC, Ma...

1. A method, comprising:establishing a communications channel between a new virtual function (VF) of a guest virtual machine (VM) and a physical function (PF) on a graphics processing unit (GPU);
granting the VF exclusive access to a set of shared GPU registers during initialization of the new VF;
performing a world switch, after initialization of the new VF, from the new VF to a previously initialized VF executing at the GPU prior to initialization of the new VF; and
allocating cycles of GPU processing time to the previously initialized VF to process accumulated commands.

US Pat. No. 9,596,481

APPARATUS AND METHOD FOR VIDEO DATA PROCESSING

ATI Technologies ULC, On...

1. An apparatus for facilitating processing image data of video frames comprising:
a processing component configured to process a reference frame to produce an output frame including:
a first input configured to receive motion vector data for a block of pels of the reference frame that estimates the displacement
of the reference frame pels from corresponding pels in a prior input frame; and

a second input configured to receive pel data for pels of a prior output frame corresponding to the prior input frame as previously
processed;

the processing component configured to produce comparison metrics for a reference frame pel of the reference frame block based
on a comparison of the reference frame pel and a plurality of neighboring reference frame pels with pels of the prior output
frame including:

a first comparison metric based on a comparison with corresponding pels of the prior output frame; and
a second comparison metric based on a comparison with corresponding pels of a motion compensated prior output frame derived
from applying the motion vector data for the reference frame block to the pels of the prior output frame; and

the processing component configured to determine a pel of the output frame that corresponds to the reference frame pel using
the first and second comparison metrics;

wherein the processing component is configured to use the first comparison metric to determine a first gain for use in blending
the reference frame pel with a corresponding pel of the prior output frame to produce a first blended pel and to use the second
comparison metric to determine a second gain for use in blending the reference frame pel with a corresponding pel of the motion
compensated prior output frame to produce a second blended pel; and

wherein the processing component is configured to produce the first and second blended pels and to use the first and second
comparison metrics, a motion vector variance value, and a motion vector metric to determine a third gain for use in blending
the first and second blended pels to produce a third blended pel upon which the output frame pel corresponding to the reference
frame pel is based.

US Pat. No. 10,664,403

PER-GROUP PREFETCH STATUS TO REDUCE DUPLICATE PREFETCH REQUESTS

ATI Technologies ULC, Ma...

1. A method for prefetching data into a cache, the method comprising:detecting access by a cache client to a data block;
identifying proposed data blocks for prefetching based on a prefetch method and the data block;
examining prefetch tracking data to determine whether a prefetch group containing the proposed data blocks is marked as having already been prefetched;
determining whether to prefetch the proposed data blocks based on the prefetch tracking data; and
either prefetching or not prefetching the proposed data blocks based on the determining.

US Pat. No. 10,664,223

METHODS AND APPARATUS FOR MAPPING VIRTUAL SURFACE TO PHYSICAL SURFACE ON CURVED DISPLAY

ATI Technologies ULC, Ma...

1. A method, by a computing device, for providing pixel information for display, the method comprising:mapping, using the computing device, pixel information of a virtual rendering surface to a physical curved display screen based on field-of-view point reference data and display curvature data of one or more curved displays using a scaled ratio, wherein using the scaled ratio comprises applying virtual pixels in the virtual rendering surface to a plurality of differing physical pixels in at least one row of a portion of the physical curved display screen, wherein the scaled ratio is a non-constant value that defines more than one virtual pixel to a single physical pixel and varies the number of virtual pixels to be applied to the plurality of differing physical pixels in the at least one row of the portion of the physical curved display screen based on the field-of-view point reference data and the display curvature data; and
outputting, using the computing device, display data based on the mapped pixel information for display to the one or more curved displays.

US Pat. No. 10,594,901

GAME ENGINE APPLICATION DIRECT TO VIDEO ENCODER RENDERING

ATI Technologies ULC, Ma...

1. A system comprising:a game engine comprising a rendering unit configured to render images for display; and
a video encoder configured to encode rendered images that have been rendered in a first color space;
wherein the rendering unit is configured to:
render each image in the first color space;
generate attributes associated with, and distinct from, each image rendered in the first color space;
convey each image rendered in the first color space to the encoder; and
convey the attributes associated with each image to the encoder;
wherein the encoder is configured to encode each rendered image based on the plurality of attributes provided by the rendering unit.

US Pat. No. 10,511,858

BIT PACKING FOR DELTA COLOR COMPRESSION

ATI Technologies ULC, Ma...

1. A method comprising:determining delta values for a plurality of pixels in a block, wherein each delta value represents a difference between a color of one of the plurality of pixels and a reference color of a reference pixel selected from the plurality of pixels;
subdividing the plurality of pixels into a plurality of groups, wherein different minimum numbers of bits are used to represent the delta values in the plurality of groups;
generating a compressed bitstream representative of the delta values, wherein the compressed bitstream includes:
bits representative of a block header that indicates a range of the minimum numbers of bits that are used to represent the delta values in the plurality of groups;
a plurality of group headers, each group header indicating a group minimum number of bits that is used to represent the delta values in a corresponding one of the plurality of groups; and
the delta values encoded using the group minimum number of bits for the group that includes the delta values; and
transmitting the compressed bitstream.

US Pat. No. 10,304,155

DELTA COLOR COMPRESSION APPLICATION TO VIDEO

Advanced Micro Devices, I...

1. A system comprising:a memory subsystem;
a processor coupled to the memory subsystem;
wherein the processor is configured to:
receive a plurality of M-bit pixel components comprising pixel data which are most significant bit (MSB) aligned in N-bit containers, wherein N and M are integers, N is greater than M, and only the M most significant bits of the N-bit containers store pixel data;
shift the M-bit pixel components down into least significant bits (LSB) locations of the N-bit containers;
convert the plurality of N-bit containers into a plurality of M-bit containers;
compress the plurality of M-bit containers to create a compressed block of pixel data; and
store the compressed block of pixel data in the memory subsystem.

US Pat. No. 10,572,246

LIVE UPDATE OF A KERNEL DEVICE MODULE

ATI Technologies ULC, Ma...

8. A method comprising:executing program instructions of a first version of a device driver to register the first version of the device driver with a proxy module, wherein the first version of the device driver is configured to manage interactions between a device and one or more software applications;
wherein subsequent to registering the first version of the device driver with the proxy module:
executing program instructions of the proxy module to provide an indication from the proxy module to the first version of the device driver that specifies whether another version of the device driver is already loaded on the system and managing the device; and
registering with the OS as the first version of the device driver and emulating the first version of the device driver to the OS, responsive to determining no other versions of the device driver are loaded on the system and managing the device.

US Pat. No. 10,542,268

SYSTEM FOR VIDEO COMPRESSION

ADVANCED MICRO DEVICES, I...

1. A method for encoding video data having a luma-chroma format (“YUV format”), the method comprising:encoding a U value, by a U-compression core, for a macro block based on data for the macro block to generate U-color output;
encoding a V value, by a V-compression core, for the macro block based on data for the macro block to generate V-color output;
encoding a Y value, by a Y-compression core, for the macro block based on data for the macro block to generate Y output;
for a separate-color-plane stream, patching, by the Y-compression core, the Y output, the U-color output, and the V-color output together at the end of a frame, to generate encoded YUV data; and
for a non-separate-color-plane stream, patching, by the Y-compression core, a second Y output encoded by the Y-compression core, a second U-color output encoded by the U-compression core, and a second V-color output encoded at the V-compression core at the end of a macroblock, to generate second encoded YUV data;
wherein encoding the U value, encoding the V value, and encoding the Y value occur simultaneously.

US Pat. No. 10,424,274

METHOD AND APPARATUS FOR PROVIDING TEMPORAL IMAGE PROCESSING USING MULTI-STREAM FIELD INFORMATION

ATI Technologies ULC, Ma...

1. A method, carried out by an encoder, for providing temporal image processing comprising:producing, by the encoder, for output on a single link, packet based multi-stream information by producing a sequence of temporally related frames and generating the packet based multi-stream information from the sequence, the packet based multi-stream information comprising a first stream that provides at least entire frame N information together with a second stream that provides at least entire frame N?1 information for temporal image processing by a same display, wherein N and N?1 information include entire frame information of temporally different frames from a same two-dimensional image sequence; and
outputting, by the encoder, the packet based multi-stream information comprising the first stream that provides the at least entire frame N information together with the second stream that provides the at least entire frame N?1 information for temporal image processing by the same display.