US Pat. No. 9,620,200

RETENTION VOLTAGES FOR INTEGRATED CIRCUITS

ARM Limited, Cambridge (...

1. An integrated circuit, comprising:
functional circuitry configured to store one or more data bits; and
retention mode circuitry coupled to the functional circuitry and configured to provide a plurality of retention voltages to
the functional circuitry, wherein the retention mode circuitry comprises:

a first circuitry configured to provide a first retention voltage to the functional circuitry, wherein the first circuitry
comprises:

a first diode device; and
a first transistor device, a second diode device, or combinations thereof; and
a second circuitry configured to provide a second retention voltage to the functional circuitry, wherein the second circuitry
comprises a plurality of second transistor devices;

wherein the functional circuitry is configured to be held in a data retention mode when the first retention voltage or the
second retention voltage is provided to the functional circuitry.

US Pat. No. 9,125,804

PHARMACEUTICAL COMPOSITION COMPRISING BOTULINUM, A NON IONIC SURFACTANT, SODIUM CHLORIDE AND SUCROSE

IPSEN BIOPHARM LIMITED, ...

1. A liquid pharmaceutical composition consisting of
(a) botulinum toxin complex type A,
(b) 0.01% (v/v) POLYSORBATE 80 (polyoxyethylene (20) sorbitan monooleate),
(c) 0.15 M sodium chloride,
(d) 10 mM histidine to maintain the pH at 6.5,
(e) 11.7 mM sucrose, and
(f) sterile water.

US Pat. No. 9,223,701

DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING LOAD-EXCLUSIVE AND STORE-EXCLUSIVE OPERATIONS

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
a processor configured to perform data processing operations by executing instructions, said data processing operations comprising
accessing data values stored in a memory;

a cache configured to store local copies of a subset of said data values, wherein said cache is configured to maintain a status
value for each local copy stored in said cache; and

an exclusive use monitor configured to monitor a selected memory location for accesses,
wherein said processor is configured to execute a load-exclusive operation, said load-exclusive operation comprising loading
a first data value from a specified memory location and causing said exclusive use monitor to begin monitoring said specified
memory location,

wherein said processor is configured to execute a store-exclusive operation, said store-exclusive operation comprising storing
a second data value to said specified memory location if said exclusive use monitor indicates that said first data value at
said specified memory location has not been modified since said load-exclusive operation was executed,

and wherein, when a local copy of said first data value is stored in said cache and said status value for said local copy
of said first data value indicates that said processor has exclusive usage of said first data value, said data processing
apparatus is configured to prevent modification of said status value for a predetermined time period after said processor
has executed said load-exclusive operation,

a pending instruction queue populated by pending instructions which have been decoded but not yet executed, wherein said data
processing apparatus is configured to prevent modification of said status value with reference to said pending instructions,

wherein said data processing apparatus is configured to identify a first set of pending instructions in said pending instruction
queue when an instruction configured to cause execution of at least part of said load-exclusive operation is in said pending
instruction queue,

wherein execution of said first set of pending instructions must be completed before execution of said store-exclusive operation
completes, and said data processing apparatus is configured to prioritize execution of said first set of pending instructions.

US Pat. No. 9,552,665

HIDDEN SURFACE REMOVAL IN GRAPHICS PROCESSING SYSTEMS

ARM LIMITED, Cambridge (...

1. A method of operating a graphics processing pipeline that includes rasteriser processing circuitry that rasterises input
primitives to generate graphics fragments to be processed, each graphics fragment having one or more sampling points associated
with it, and renderer processing circuitry that processes fragments generated by the rasteriser processing circuitry to generate
output fragment data, the method comprising:
when the graphics processing pipeline is processing a set of graphics primitives, depth sorting primitives of successive sub-sets
of the primitives in the set of graphics primitives prior to the rasteriser processing circuitry generating graphics fragments
for processing the primitives;

wherein the step of depth sorting primitives of successive sub-sets of the primitives in the set of graphics primitives prior
to the rasteriser processing circuitry generating graphics fragments for processing the primitives comprises: once a sub-set
of primitives has been sorted into a sorted sub-set of primitives, passing a primitive in the sorted sub-set of primitives
onwards for processing, and adding a next primitive in the set of primitives to the remaining primitives of the sorted sub-set
of primitives to generate a new sub-set of primitives for sorting.

US Pat. No. 9,477,623

BARRIER TRANSACTIONS IN INTERCONNECTS

ARM Limited, Cambridge (...

1. Interconnect circuitry for a data processing apparatus, said interconnect circuitry being configured to provide data routes
via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising:
at least one input for receiving transaction requests from said at least one initiator device;
at least one output for outputting transaction requests to said at least one recipient device;
at least one path for transmitting said transaction requests between said at least one input and said at least one output;
control circuitry for routing said received transaction requests from said at least one input to said at least one output;
wherein:

said control circuitry, in response to a barrier transaction request to maintain an ordering of at least some transaction
requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said
at least one paths, is configured to not allow reordering of at least some transaction requests that occur before said barrier
transaction request in said stream of transaction requests with respect to at least some transaction requests that occur after
said barrier transaction request in said stream of transaction requests and to delay transmission along said at least one
path of said at least some transaction requests while allowing other transaction requests to proceed,

said barrier transaction request comprises an indicator indicating which of said transaction requests within said stream of
transaction requests comprise said at least some transaction requests whose ordering is to be maintained,

said indicator is indicative of a property of said transaction requests, and said at least some transaction requests comprise
transaction requests having said property, and

said indicator indicates a function of said transaction request.

US Pat. No. 9,448,875

ERROR RECOVERY WITHIN INTEGRATED CIRCUIT

ARM Limited, Cambridge (...

1. An integrated circuit for performing data processing, said integrated circuit comprising:
an error detector configured to detect errors in operation of said integrated circuit;
error-repair circuitry configured to repair errors in operation of said integrated circuit; and
a power supply configured to apply a power supply voltage to at least one portion of said integrated circuit, wherein:
said power supply is configured to vary an error rate within said at least one portion by varying said power supply voltage
to said at least one portion;

said power supply voltage to said at least one portion is provided via one or more power gates configured to vary said power
supply voltage to said at least one portion; and

said power supply is controlled to produce a finite non-zero error rate within said at least one portion.

US Pat. No. 9,057,761

SENSING SUPPLY VOLTAGE SWINGS WITHIN AN INTEGRATED CIRCUIT

ARM Limited, Cambridge (...

1. An integrated circuit comprising a plurality of sensors configured to sense variations in supply voltage levels at points
within said integrated circuit, said plurality of sensors being distributed across said integrated circuit;
said plurality of sensors comprising transistor devices such that local process variations in said transistor devices within
said sensors are such that a sensing result will have a random voltage offset that has a predetermined probability of lying
within a pre-defined voltage offset range; wherein

said integrated circuit is configured to transmit results from multiple ones of said plurality of sensors to processing circuitry.

US Pat. No. 9,164,842

ERROR RECOVERY WITHIN INTEGRATED CIRCUIT

ARM Limited, Cambridge (...

1. An integrated circuit for performing data processing, said integrated circuit comprising:
a latch configured to receive and to store a signal value;
an error detector configured to detect errors in operation of said integrated circuit by detecting a late arriving transition
in said signal value received by said latch;

error-repair circuitry configured to repair errors in operation of said integrated circuit
a plurality of processing stages, a processing stage output signal from at least one processing stage being supplied as a
processing stage input signal to a following processing stage, wherein said at least one processing stage comprises:

processing logic configured to perform a processing operation upon at least one processing stage input value to generate a
processing logic output signal;

a non-delayed latch configured to capture a non-delayed value of said processing logic output signal at a non-delayed capture
time, said non-delayed value being supplied to said following processing stage as said processing stage output signal following
said non-delayed capture time; and

a delayed latch configured to capture a delayed value of said processing logic output signal at a delayed capture time later
than said non-delayed capture time;

wherein said error detector comprises a comparator configured to compare said non-delayed value and said delayed value to
detect a change in said processing logic output signal following said non-delayed capture time indicative of said processing
logic not having finished said processing operation at said non-delayed capture time; and said error-repair logic is configured,
when said comparator detects said change, to perform an error-repair operation suppressing use of said non-delayed value by
said following processing stage.

US Pat. No. 9,374,072

POST FABRICATION TUNING OF AN INTEGRATED CIRCUIT

ARM Limited, Cambridge (...

1. An integrated circuit comprising:
at least one transistor having a plurality of electrical connections and a normal performance characteristic controlled by
one or more physical properties of said transistor, said normal performance characteristic arising during normal operations
of said transistor that apply normal electrical signals within respective normal ranges to at least some of said plurality
of electrical connections of said transistor, said normal performance characteristic having a value resulting in incorrect
operation of said integrated circuit upon normal switching of said transistor; and

a tuner configured to apply during a tuning operation a tuning stimulus to a gate of said transistor to permanently change
at least one of said one or more physical properties of said transistor that control said normal performance characteristic
such that upon resuming modified normal operations with said normal electrical signals said transistor operates with a changed
normal performance characteristic, said changed normal performance characteristic having a value resulting in correct operation
of said integrated circuit upon normal switching of said transistor.

US Pat. No. 9,383,999

CONDITIONAL COMPARE INSTRUCTION

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
processing circuitry for processing data;
an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry
to process said data;

a status store for storing a current condition state of said processing circuitry, said current condition state being modifiable
during processing of said data;

wherein said program instructions include a conditional compare instruction, and said instruction decoder is responsive to
said conditional compare instruction to generate control signals for controlling said processing circuitry to perform a conditional
compare operation comprising:

(i) if said current condition state passes a test condition, then performing a compare operation on a first operand and a
second operand and setting said current condition state to a result condition state generated during said compare operation;
and

(ii) if said current condition state fails said test condition, then setting said current condition state to a fail condition
state specified by said conditional compare instruction.

US Pat. No. 9,104,400

CRYPTOGRAPHIC SUPPORT INSTRUCTIONS

ARM Limited, Cambridge (...

1. Data processing apparatus comprising:
a single instruction multiple data register file; and
single instruction multiple data processing circuitry coupled to said single instruction multiple data register file and configured
to be controlled by a single instruction multiple data program instruction to perform a processing operation independently
upon separate data elements stored within separate lanes within an input operand register of said single instruction multiple
data register file; wherein

said single instruction multiple data processing circuitry is configured to be controlled by a further program instruction
to perform a further processing operation upon a vector data value comprising a sequence of data elements held within an input
operand register of said single instruction multiple data register file to produce an output operand stored within an output
operand register of said single instruction multiple data register file, said output operand having a first portion with a
value dependent upon all data elements within said sequence of data elements; and

wherein said single instruction multiple data processing circuitry is configured to be controlled by a rotate instruction
having an input operand and generating an output operand with a value the same as given by a right rotation of said input
operand by two bit positions.

US Pat. No. 9,171,634

MEMORY DEVICE AND METHOD OF CONTROLLING LEAKAGE CURRENT WITHIN SUCH A MEMORY DEVICE

ARM Limited, Cambridge (...

1. A memory device comprising:
an array of memory cells arranged as a plurality of rows and columns, each row of memory cells being coupled to an associated
read word line, each column of memory cells forming at least one column group, and the memory cells of each column group being
coupled to an associated read bit line, each column group having an active mode of operation where a read operation is able
to be performed on an activated memory cell within that column group, and a non-active mode of operation where said read operation
is not able to be performed;

precharge circuitry configured, for each column group, to precharge a voltage on the associated read bit line to a first voltage
level prior to said read operation;

each memory cell comprising coupling circuitry connected between the associated read bit line and a reference line associated
with the column group containing that memory cell;

reference line control circuitry configured, for each reference line having an associated column group in said active mode
of operation, to connect that reference line to a second voltage level different to said first voltage level, and configured
for each reference line not having an associated column group in said active mode of operation to disconnect that reference
line from said second voltage level; and

word line boosting circuitry configured to generate an asserted word line signal at a boosted voltage level on the read word
line associated with the row of memory cells to be activated during said read operation;

during said read operation the coupling circuitry associated with each activated memory cell is configured to be activated
by the asserted word line signal and to selectively discharge the associated read bit line towards the second voltage level
present on said associated reference line dependent on a data value stored within that activated memory cell; and

for each reference line not having an associated column group in said active mode of operation, the action of the reference
line control circuitry disconnecting that reference line from the second voltage level serving to remove a leakage current
path through the coupling circuitry of each memory cell of that associated column group.

US Pat. No. 9,052,909

RECOVERING FROM EXCEPTIONS AND TIMING ERRORS

ARM Limited, Cambridge (...

1. A data processing apparatus comprising a processing pipeline for processing a stream of instructions from an instruction
set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions
that may generate an exception and non-exception instructions being instructions that execute in a statically determinable
way, said processing pipeline comprising:
exception control circuitry;
error detection circuitry configured to detect errors within said processing pipeline by detecting changes in a signal value
within a time window occurring after said signal has been sampled in said processing pipeline in response to a clock signal
and being configured to signal detection of an error to an exception storage unit; wherein

said exception storage unit is configured to maintain an age-ordered list of entries corresponding to instructions issued
to said processing pipeline for execution;

said exception storage unit is configured to store in association with each entry an exception indicator indicating whether
said instruction is an exception instruction and whether it has generated an exception and an error indicator indicating whether
said instruction has generated an error;

said data processing apparatus is configured to indicate to said exception storage unit that an instruction is resolved when
processing of said instruction has reached a stage such that it is known whether said instruction will generate an error and
whether said instruction will generate an exception; and

said exception control circuitry is configured to sequentially retire oldest resolved entries from said list in said exception
storage unit.

US Pat. No. 9,483,438

APPARATUS AND METHOD FOR CONTROLLING THE NUMBER OF VECTOR ELEMENTS WRITTEN TO A DATA STORE WHILE PERFORMING SPECULATIVE VECTOR WRITE OPERATIONS

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
a vector register bank configured to store vector operands for access by processing circuitry, each vector operand comprising
a plurality of vector elements;

vector data access circuitry for performing vector access operations in order to move vector operands between the vector register
bank and a data store;

a reconfigurable buffer accessible to the vector data access circuitry and comprising a storage array for storing up to M
vectors of N vector elements, where the values of M and N are reconfigurable;

the vector data access circuitry being configured to perform speculative data write operations in order to cause vector elements
from selected vector operands in the vector register bank to be stored into said reconfigurable buffer, on occurrence of a
commit condition, the vector data access circuitry further being configured to cause the vector elements currently stored
in the reconfigurable buffer to be written to the data store;

speculation control circuitry configured to maintain a speculation width indication indicating the number of vector elements
of each selected vector operand stored in the reconfigurable buffer, the speculation width indication being initialised to
an initial value, and on detection of an overflow condition within the reconfigurable buffer the speculation width indication
being modified to reduce the number of vector elements of each selected vector operand stored in the reconfigurable buffer;
and

the reconfigurable buffer being responsive to a change in the speculation width indication to reconfigure the storage array
to increase the number of vectors M and reduce the number of vector elements N per vector.

US Pat. No. 9,223,677

GENERATION OF TRACE DATA IN A MULTI-PROCESSOR SYSTEM

ARM Limited, Cambridge (...

1. Apparatus for processing data for performing one or more processing tasks by executing sequences of program instructions,
said apparatus comprising:
a plurality of processing circuits each having access to a memory;
tracing circuitry configured to generate a stream of trace data indicative of processing operations being performed by at
least one of said plurality of processing circuits, said tracing circuitry is separate from and shared between said plurality
of processing circuits;

selection circuitry configured to selectively switch, during execution of said program instructions, said tracing circuitry
from generating a first stream of trace data corresponding to one of said plurality of processing circuits to generating a
second different stream of trace data corresponding to a different one of said plurality of processing circuits in dependence
upon processing state information provided by at least one of said plurality of processing circuits.

US Pat. No. 9,064,559

MEMORY DEVICE AND METHOD OF PERFORMING ACCESS OPERATIONS WITHIN SUCH A MEMORY DEVICE

ARM Limited, Cambridge (...

1. A memory device comprising:
an array of memory cells arranged as a plurality of rows and columns, the array operating in an array voltage domain with
an array voltage supply;

a plurality of word lines, each word line being coupled to an associated row of memory cells;
a plurality of bit lines, each bit line being coupled to an associated column of memory cells;
access circuitry coupled to the plurality of word lines and the plurality of bit lines in order to perform access operations
in respect of selected memory cells within the array, at least a part of the access circuitry operating in a peripheral voltage
domain with a peripheral voltage supply;

control circuitry configure to control operation of the access circuitry, the control circuitry including self-timed path
(STP) delay circuitry configured to generate a delay indication indicative of an access timing delay associated with accessing
the memory cells, the control circuitry employing said delay indication when controlling the access circuitry to perform said
access operations; and

voltage supply control circuitry associated with at least one portion of the STP delay circuitry and configured to switch
the voltage supply to said at least one portion of the STP delay circuitry between said peripheral voltage supply and said
array voltage supply dependent on a control signal set having regard to the voltage levels of said array voltage supply and
said peripheral voltage supply.

US Pat. No. 9,473,114

POWER-ON-RESET DETECTOR

ARM Limited, Cambridge (...

1. An integrated circuit, comprising:
a first stage having a resistor and a capacitor arranged to receive an input voltage signal and provide a triggering signal
during ramp of the input voltage signal; and

a second stage having at least one transistor arranged to receive the triggering signal from the first stage and provide an
output voltage signal during ramp of the input voltage signal via gate leakage through the at least one transistor,

wherein the at least one transistor is intercoupled to function as a capacitor having high gate input resistance.

US Pat. No. 9,304,926

COHERENCY CONTROL MESSAGE FLOW

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
a plurality of agents each configured to store one or more lines of data;
coherency control circuitry configured to control coherency between said lines of data stored within said plurality of agents;
and

interconnect circuitry configured to provided communication between said plurality of agents and said coherency control circuitry,
said interconnect circuitry providing a plurality of communication channels between each one of said plurality of agents and
said coherency control circuitry; wherein

at least one of said plurality of agents is configured:
(i) to send an evict message to said coherency control circuitry when performing an eviction operation for a line of data
via a given one of said plurality of communication channels; and

(ii) to send a read message to said coherency control circuitry when performing a subsequent read operation for said line
of data via said given one of said plurality of communication channels;

said interconnect circuitry is configured always to communicate said evict message and said read message to said coherency
control circuitry via said given one of said plurality of communication channels such that said evict message is received
by said coherency control circuitry before said read message; and

said coherency control circuitry is configured always to process said evict message ahead of said read message.

US Pat. No. 9,286,714

APPARATUS AND METHOD FOR PROCESSING GRAPHICS PRIMITIVES

ARM Limited, Cambridge (...

1. An apparatus for processing graphics primitives for display, comprising:
primitive setup circuitry configured to determine a plurality of functions for an input graphics primitive, including an edge
function associated with each edge of the input graphics primitive and a depth function associated with the input graphics
primitive;

rasterization circuitry configured to perform a rasterization operation using the edge function associated with each edge
of the input graphics primitive in order to calculate position data for a plurality of graphics fragments to be used to represent
the input graphics primitive;

depth bound clipping circuitry configured in a default mode of operation to perform a depth bound clipping operation by determining,
for each graphics fragment in said plurality of graphics fragments, a depth value for said graphics fragment using the depth
function, and determining whether said depth value resides within a valid depth range of a view frustum, the graphics fragment
being discarded from further processing if its depth value does not reside within said valid depth range; and

control circuitry configured to be responsive to detection of a predetermined condition to modify the operation of the primitive
setup circuitry and the rasterization circuitry for one or more input graphics primitives in order to incorporate depth bound
clipping within the rasterization operation performed by the rasterization circuitry for said one or more input graphics primitives,
the control circuitry further being configured on detection of said predetermined condition to disable the default mode of
operation in order to disable the depth bound clipping circuitry from performing said depth bound clipping operation;

wherein:
the control circuitry is configured to modify the operation of the primitive setup circuitry by causing the primitive setup
circuitry to additionally determine at least one depth plane edge function for the input graphics primitive; and

the control circuitry is configured to modify the operation of the rasterization circuitry by causing the rasterization circuitry
to incorporate said at least one depth plane edge function in said rasterization operation.

US Pat. No. 9,269,418

APPARATUS AND METHOD FOR CONTROLLING REFRESHING OF DATA IN A DRAM

ARM Limited, Cambridge (...

20. An apparatus comprising:
dynamic random access memory (DRAM) means for storing data;
refresh control means for controlling said DRAM means to periodically perform a refresh cycle for refreshing the data stored
in each memory location of said DRAM means; and

refresh address sequence generating means for generating a refresh address sequence of addresses identifying the order in
which memory locations of said DRAM means are refreshed during said refresh cycle;

wherein said refresh address sequence generating means generates said refresh address sequence with the addresses for at least
a portion of said memory locations in a random order which varies from refresh cycle to refresh cycle; and

wherein said refresh address sequence generating means has a normal mode in which said refresh address sequence is generated
with said addresses of said at least a portion of said memory means in a sequential order, and a random mode in which said
refresh address sequence is generated with said addresses of said at least a portion of said memory locations in said random
order; and

said refresh address sequence generator means is configured to operate in said normal mode when processing means for performing
data processing is operating in a normal mode, and to operate in said random mode when said processing means is operating
in a power saving mode; or

said refresh control means is configured to detect accesses to said DRAM means by said processing means, and said refresh
address sequence generating means is configured to operate in said normal mode when a detected volume of accesses is greater
than a predetermined threshold, and to operate in said random mode when said detected volume of accesses is less than said
predetermined threshold.

US Pat. No. 9,170,282

CONTROLLING VOLTAGE GENERATION AND VOLTAGE COMPARISON

ARM Limited, Cambridge (...

1. An integrated circuit comprising:
voltage generating circuitry configured to receive a supply voltage and to generate an on-chip voltage from the supply voltage
in response to clock pulses of a voltage generation clock signal;

a circuit block configured to receive the on-chip voltage from the voltage generating circuitry; and
clock control circuitry configured to control transmission of the clock pulses of the voltage generation clock signal to the
voltage generating circuitry;

wherein the clock control circuitry is configured to receive a reference voltage and a digital offset value comprising a binary
numeric value identifying an offset; and

the clock control circuitry is configured to suppress transmission of the clock pulses of the voltage generation clock signal
to the voltage generating circuitry if the on-chip voltage is greater than the sum of the reference voltage and the offset
identified by the digital offset value.

US Pat. No. 9,098,265

CONTROLLING AN ORDER FOR PROCESSING DATA ELEMENTS DURING VECTOR PROCESSING

ARM Limited, Cambridge (...

1. A data processing apparatus for processing a stream of vector instructions for performing operations on vectors, said vectors
each comprising a plurality of data elements, said data processing apparatus comprising:
a register bank comprising a plurality of registers for storing said vectors being processed;
a pipelined processor for processing said stream of vector instructions;
said pipelined processor comprising circuitry configured to detect data dependencies for said vectors processed by said stream
of vector instructions and stored in said plurality of registers and to determine constraints on timing of execution for said
vector instructions such that no register data hazards arise, said register data hazards arising where two accesses to a same
register, at least one of said accesses being a write, occur in an order different to an order of said instruction stream
such that an access occurring later in said instruction stream starts before an access occurring earlier in said instruction
stream has completed;

said pipelined processor comprising data element hazard determination circuitry configured to determine for at least some
of said data elements within vectors where data dependencies have been identified, whether said data dependencies identified
for said vectors exist for each of said at least some of said data elements, and if not to relax said determined constraints
on timing of execution for an instruction processing said data element.

US Pat. No. 9,311,244

ENFORCING ORDERING OF SNOOP TRANSACTIONS IN AN INTERCONNECT FOR AN INTEGRATED CIRCUIT

ARM Limited, Cambridge (...

1. An interconnect for connecting devices in an integrated circuit, the interconnect comprising:
transaction tracking circuitry capable of tracking data access transactions received by the interconnect from one or more
master devices, and for at least one set of data access transactions, controlling issuing of the data access transactions
within the same set of data access transactions to one or more slave devices in a selected order; and

a snoop filter capable of identifying, in response to a data access transaction specifying a target address, which master
devices have cached data for the target address;

wherein the transaction tracking circuitry is capable of controlling issuing of at least one snoop transaction to at least
one master device identified by the snoop filter as having cached data for the target address; and

for a set of snoop transactions issued in response to data access transactions within the same set of data access transactions,
the transaction tracking circuitry is capable of controlling issuing of the set of snoop transactions to the at least one
master device in an order corresponding to the selected order of the corresponding set of data access transactions.

US Pat. No. 9,130,433

ELECTRONICALLY CONTROLLED UNIVERSAL MOTOR

ARM Limited, Cambridge (...

1. An electric motor apparatus comprising:
a stator component and a rotor component rotationally mounted coaxially with and within said stator component;
said stator component and said rotor component each comprising windings configured to generate an electromagnetic field from
an electric current;

said electric motor further comprising an intermediate screening component rotationally mounted between said stator component
and said rotor component and configured to provide at least some magnetic screening between said rotor component and said
stator component;

said intermediate screening component comprising at least some magnetically active sections configured such that changing
magnetic fields generated by changing electric currents in said windings on either said rotor component or said stator component
generate a force on said magnetically active sections causing said intermediate screening component to rotate; and

control circuitry for independently controlling power supplied to said windings on said rotor component and said stator component
in dependence upon a desired output rotational speed.

US Pat. No. 9,128,531

OPERAND SPECIAL CASE HANDLING FOR MULTI-LANE PROCESSING

ARM Limited, Cambridge (...

1. Apparatus for processing data having data processing pipeline hardware, said data processing pipeline hardware comprising:
a plurality of lanes of processing circuitry configured to perform data processing operations in parallel upon operands within
respective ones of said plurality of lanes of processing circuitry;

a plurality of special case detecting circuits, each coupled to a respective one of said plurality of lanes of processing
circuitry and configured to detect in parallel a respective special case condition if one or more of said operands processed
by said lane of processing circuitry matches any of one or more predetermined conditions; and

one or more shared special case handling circuits each coupled to a plurality of said plurality of special case detecting
circuits and configured to perform in series a respective special case processing operation for a special case condition detected
within any of a plurality of said plurality of lanes of processing circuitry, wherein said data processing pipeline hardware
comprises permutation circuitry configured to swap operands between said plurality of processing lanes, each of said one or
more shared special case handling circuits disposed within a respective one of said plurality of processing lanes and said
permutation circuitry configured to swap operands for a processing lane in which a special case condition has been detected
into one of said plurality of processing lanes having one of said one or more said shared special case handling circuits for
special case processing.

US Pat. No. 9,304,923

DATA COHERENCY MANAGEMENT

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
a plurality of main cache memories each having a plurality of main cache lines;
an inclusive snoop directory memory having a plurality of directory lines, each of said directory lines respectively storing:
(i) a given directory tag value indicative of a contiguous range of memory address values with a given span corresponding
in size to N main cache lines, where N is an integer greater than one; and

(ii) N snoop vectors, each of said N snoop vectors indicating at least that, for a respective one of N memory address sub-regions
within said given span, one or more of said plurality of main cache memories is logged as storing data corresponding to said
respective one of N memory address sub-regions,

wherein:
said inclusive snoop directory memory comprises A directory lines, where A is a positive integer;
said plurality of main cache memories comprise X cache memories, where X is an integer greater than one;
each of said plurality of main cache memories comprises B main cache lines, where B is a positive integer; and
N*A is greater than X*B.

US Pat. No. 9,294,301

SELECTING BETWEEN CONTENDING DATA PACKETS TO LIMIT LATENCY DIFFERENCES BETWEEN SOURCES

ARM Limited, Cambridge (...

1. An interconnect configured to route data packets between a plurality of initiators and at least one recipient along a plurality
of paths, said data packets comprising an identifier identifying said initiator and data, said interconnect comprising:
a plurality of routers, said routers comprising at least two inputs for receiving said data packets from at least two different
paths and an output for outputting said received data packets;

at least one of said routers comprising an arbiter configured to select between contending data packets input to said at least
one router from said different paths to be output at said output;

said arbiter comprising a history buffer for storing said identifiers identifying said initiators of a plurality of recently
output data packets;

said arbiter comprising selection circuitry configured to select one of said contending data packets to be output in dependence
upon said initiators of said contending data packets and said initiators identified in said history buffer, such that a probability
of a data packet being selected increases with the number of data packets selected since a data packet from the same initiator
was selected;

wherein said arbiter is configured to access weighting indicators indicative of a weighting of at least some of said plurality
of initiators, said selection circuitry being configured to select data packets from initiators with a higher weighting disproportionately
more frequently than said selection circuitry selects data packets from initiators with a lower weighting;

wherein said arbiter further comprises a low priority store for storing identifiers identifying initiators currently having
a low priority, said arbiter comprising a device for updating a value indicative of a number of data packets selected from
each of said initiators, said arbiter being configured to add said initiator to said low priority store in response to said
value for said initiator reaching a predetermined value, said arbiter being configured to preferentially select data packets
from initiators not in said low priority store over data packets from sources in said low priority store;

wherein in response to all of said initiators being added to said low priority store, said low priority store and said values
are cleared; and

wherein said predetermined value is dependent on said weighting of said initiator.

US Pat. No. 9,280,675

ENCRYPTING AND STORING CONFIDENTIAL DATA

ARM LIMITED, Cambridge (...

1. Data storage circuitry comprising:
a data store comprising a plurality of data storage locations for storing data;
an input configured to receive requests to access said data store;
renaming circuitry configured to map architectural data storage locations specified in said access requests to physical data
storage locations within said data store;

encryption circuitry configured to encrypt data prior to storing said data in said data store, said encryption circuitry being
configured to generate an encryption key in dependence upon a physical data storage location said data is to be stored in;
and

decryption circuitry configured to decrypt data read from said data store, said decryption circuitry being configured to generate
a decryption key in dependence upon said physical data storage location said data is read from,

wherein said renaming circuitry is configured to determine which of said plurality of physical data storage locations are
available to store data specified in an access request and to perform said mapping by selecting one of said available physical
data storage locations to map said architectural data storage location to according to a random or pseudo random process and
to store mappings for physical data storage locations currently storing valid data; and

wherein said available physical data storage locations comprise all of the physical data storage locations within said data
store,

wherein said renaming circuitry is configured, when said renaming circuitry selects a physical data storage location from
among said available physical data storage locations which is currently mapped, to select another one of said available physical
data storage locations according to said random or pseudo random process, to write data stored in said currently mapped physical
data storage location to another physical data storage location, to store a mapping for said another physical data storage
location, and to store said data specified in said access request to said selected physical data storage location.

US Pat. No. 9,407,265

INTEGRATED CIRCUIT WITH SIGNAL ASSIST CIRCUITRY AND METHOD OF OPERATING THE CIRCUIT

ARM Limited, Cambridge (...

1. A circuit, comprising: signal assist circuitry configured to assist with pulling a signal on a signal line towards a logical
low signal level and to assist with pulling the signal on the signal line towards a logical high signal level, wherein the
signal on the signal line has one of the logical low signal level and the logical high signal level depending on an output
of predetermined circuitry, wherein the signal assist circuitry comprises:
a first assist circuit configured to couple a first node of the signal line to a first supply node for supplying the logical
high signal level following a pullup transition of the signal from the logical low signal level towards the logical high signal
level, and configured to provide a floating signal level to the first node following a pulldown transition of the signal from
the logical high signal level towards the logical low signal level; and

a second assist circuit configured to couple a second node of the signal line to a second supply node for supplying the logical
low signal level following the pulldown transition, and configured to provide a floating signal level to the second node following
the pullup transition;

wherein the second assist circuit comprises a transistor having a plurality of terminals and a gate, wherein one of the plurality
of terminals directly couples to the second node of the signal line.

US Pat. No. 9,256,975

GRAPHICS PROCESSING SYSTEMS

ARM LIMITED, Cambridge (...

1. A method of providing the accumulated results of several rendering passes for at least one tile of a frame into an output
frame in a tile-based graphics processing system, the method comprising:
performing a set of several rendering passes for a tile that is a division of the output frame,
wherein said tile is represented by a set of sampling positions and each rendering pass determines and writes a set of one
or more values to each sampling position of the tile, each sampling position having a final value at the end of each rendering
pass;

accumulating the results of the set of rendering passes for the tile in an accumulation buffer, so as to generate for the
tile an output tile that comprises the accumulated results of the set of rendering passes for the tile,

wherein the accumulation buffer stores, for each sampling position, an accumulated value for the set of several rendering
passes, and once all of the rendering passes and the accumulation of the results of those rendering passes is completed for
the tile, the accumulated value for a sampling position is an accumulation of the final values for the sampling position from
each of the rendering passes; and

outputting the so-generated output tile to the output frame; and
said method further comprising:
for each rendering pass for the tile, accumulating the rendering results for the rendering pass for the tile in the accumulation
buffer as the rendering pass proceeds by:

when a new value is to be written to a sampling position of the tile during the rendering pass, updating the accumulated value
for the set of rendering passes for that sampling position in the accumulation buffer using the new value for that sampling
position, without waiting for the final value for that sampling position for the rendering pass to be determined.

US Pat. No. 9,122,613

PREFETCHING OF DATA AND INSTRUCTIONS IN A DATA PROCESSING APPARATUS

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
at least one processor for processing data in response to instructions said instructions indicating storage locations for
said data and for said instructions by virtual addresses;

a hierarchical data storage system for storing said data and said instructions in storage locations identified by physical
addresses, said hierarchical data storage system comprising a memory and at least one cache;

address translation circuitry for mapping said virtual addresses to said physical addresses;
load store circuitry configured to receive access requests from said at least one processor, said access requests indicating
storage locations to be accessed as virtual addresses, said load store circuitry being configured to access said address translation
circuitry to identify said physical addresses that correspond to said virtual addresses of said received access requests,
and to access said corresponding physical addresses in said hierarchical data storage system;

preload circuitry configured to receive preload requests from said processor indicating by virtual addresses storage locations
that are to be preloaded into at least one of said at least one caches, said preload circuitry having access to said address
translation circuitry such that said corresponding physical addresses can be identified; and

prefetch circuitry configured to monitor at least some of said accesses performed by said load store circuitry and to predict
addresses to be accessed subsequently, said prefetch circuitry being configured to transmit said predicted addresses to said
preload circuitry as preload requests; wherein

said preload circuitry is configured to respond to said preload requests from said processor and from said prefetch circuitry
to preload at least one of said at least one caches with said requested storage locations,

wherein said prefetch circuitry is configured to transmit predicted physical addresses within a predetermined range to said
preload circuitry such that they are located within in a same page table as said monitored access requests and on a predicted
address being outside of said page table to stop sending said predicted addresses, until said monitored addresses move to
a new page table.

US Pat. No. 9,430,381

PROCESSING ORDER WITH INTEGER INPUTS AND FLOATING POINT INPUTS

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
processing circuitry configured to compute one or more result values as a function of a plurality of input values;
a memory configured to store said plurality of input values;
load circuitry configured to issue one or more memory access requests to said memory to
retrieve said plurality of input values from said memory and to supply said plurality of input values to said processing circuitry;
wherein

said plurality of input values are retrieved in a variable order from said memory; and
said processing circuitry is configured to determine a format type for said plurality of input values for which said function
is associative or non-associative, and wherein:

(i) when said plurality of input values have a format type for which said function is associative, said processing circuitry
performs processing upon said plurality of input values to compute said one or more result values in a variable order that
is dependent upon said variable order in which said plurality of input values are retrieved from said memory; and

(ii) when said plurality of input values have a format type for which said function is non-associative, said processing circuitry
performs processing upon said plurality of input values to compute said one or more result values in a fixed order that is
independent of said variable order in which said plurality of input values are retrieved from said memory.

US Pat. No. 9,424,045

DATA PROCESSING APPARATUS AND METHOD FOR CONTROLLING USE OF AN ISSUE QUEUE TO REPRESENT AN INSTRUCTION SUITABLE FOR EXECUTION BY A WIDE OPERAND EXECUTION UNIT

ARM Limited, Cambridge (...

1. A data processing apparatus, comprising:
execution circuitry comprising a number of execution units, including a first operand execution unit configured to allow up
to N bits of operand data to be processed during execution of a single instruction, where N is an integer greater than 0;

decoder circuitry configured to decode each instruction to be executed by the execution circuitry in order to generate for
each instruction at least one control data block identifying an operation to be performed by the execution circuitry in order
to execute said instruction;

issue queue circuitry providing an issue queue having a plurality of slots, each slot configured to store one control data
block generated by the decoder circuitry along with up to M bits of operand data associated with that control data block,
where M is less than N and is an integer greater than 0;

the issue queue circuitry configured to issue control data blocks and associated operand data from the issue queue to the
execution circuitry for processing;

the decoder circuitry being responsive to receiving an instruction suitable for execution by said first operand execution
unit and requiring more than M bits, but no more than N bits, of operand data to be processed during execution, to generate
at least two re-combineable control data blocks for said instruction suitable for execution by said first operand execution
unit;

the issue queue circuitry configured to allocate a slot in the issue queue for each of said at least two re-combineable control
data blocks and up to M bits of associated operand data, and to mark those allocated slots to identify that they contain re-combineable
control data blocks;

the issue queue circuitry being configured, responsive to a determination that said at least two re-combineable control data
blocks are to be issued to said first operand execution unit, to re-combine said at least two re-combineable control data
blocks into a combined control data block, and to issue the combined control data block to said first operand execution unit
along with the operand data contained in each of the allocated slots for said at least two re-combineable control data blocks.

US Pat. No. 9,361,204

GENERATING TRACE DATA INCLUDING A LOCKUP IDENTIFIER INDICATING OCCURRENCE OF A LOCKUP STATE

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
processing circuitry configured to execute program instructions; and
trace circuitry configured to generate trace data indicative of processing activities of the processing circuitry;
wherein the trace circuitry is configured to detect a lockup state of the processing circuitry in which the processing circuitry
does not make forward progress of execution of any program instructions; and

in response to detecting the lockup state of the processing circuitry, the trace circuitry is configured to include in the
trace data a lockup identifier indicating that the lockup state has occurred;

wherein the trace circuitry is configured to detect the processing circuitry exiting the lockup state; and
in response to detecting the processing circuitry exiting the lockup state, the trace circuitry is configured to include in
the trace data a lockup exit identifier or trace data indicating that forward progress of program execution is once more being
made.

US Pat. No. 9,251,378

SECURITY PROTECTION OF SOFTWARE LIBRARIES IN A DATA PROCESSING APPARATUS

ARM Limited, Cambridge (...

23. A method of data processing for an apparatus comprising
processing circuitry having a plurality of domains of operation including a secure domain and a less secure domain, wherein
at least some data accessible to the instructions when operating in the secure domain is inaccessible when operating in the
less secure domain, and a data store storing a plurality of software libraries and library management software for execution
by the processing circuitry; the method comprising:

under control of the library management software, the processing circuitry setting at least one of the plurality of software
libraries as an active software library which is executable by the processing circuitry and setting at least one other software
library as an inactive software library which is not executable by the processing circuitry;

in response to the processing circuitry calling between the less secure domain and the secure domain, security protection
hardware performing a first security protection operation; and

in response to the processing circuitry calling a target inactive software library, the library management software performing
active library switching to control the processing circuitry to set the target inactive software library as the active software
library and to set a previously active software library as the inactive software library.

US Pat. No. 9,454,313

DYNAMIC SELECTION OF MEMORY MANAGEMENT ALGORITHM

ARM Limited, Cambridge (...

16. A memory controller configured to manage conflicting memory accesses to a memory within a data processing apparatus using
a selected management algorithm dynamically selected from among a plurality of candidate management algorithms in dependence
upon one or more current state parameters of said data processing apparatus;
wherein said one or more current state parameters comprise one or more conflict level parameters indicative of an amount of
conflicting memory accesses detected;

comprising one or more conflict counters configured to store respective conflict count values indicative of a number of conflicting
memory accesses detected,

wherein said one or more conflict counters comprise one or more saturating counters; and
said memory controller changes a corresponding one of said conflict count values by a second amount and in accordance with
a conflict-decrease-noting algorithm when one or more of:

a predetermined number of accesses without a conflict tracked by said corresponding one of said conflict count values are
detected; and

a predetermined interval of time has passed since a last change by said second amount.

US Pat. No. 9,449,717

MEMORY BUILT-IN SELF-TEST FOR A DATA PROCESSING APPARATUS

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
at least one memory configured to store data;
processing circuitry configured to issue memory transactions for accessing data in the at least one memory;
a memory built-in self-test (MBIST) interface configured to receive a MBIST request indicating that a test procedure is to
be performed for testing at least one target memory location of the at least one memory; and

control circuitry configured to detect the MBIST request received by the MBIST interface, and in response to detecting the
MBIST request, to reserve for testing at least one reserved memory location including said at least one target memory location;

wherein during the test procedure, the at least one memory is configured to continue servicing memory transactions issued
by the processing circuitry which target a memory location other than the at least one reserved memory location reserved by
the control circuitry; and

wherein the MBIST interface is configured to receive a plurality of MBIST requests, each MBIST request corresponding to a
burst of test transactions for testing a different subset of memory locations of said at least one memory.

US Pat. No. 9,355,014

DEBUG INSTRUCTION SET ALLOCATION ACCORDING TO PROCESSOR OPERATING STATE

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
data processing circuitry for performing data processing operations in response to execution of program instructions, said
data processing circuitry being configured to operate in at least an operational mode and a debug mode;

debug circuitry configured to provide an interface between said data processing circuitry and a debugger unit external to
said data processing circuitry, said debug circuitry being configured to control operation of said data processing circuitry
using debug instructions of a debug instruction set when said data processing circuitry is operating in said debug mode;

wherein said data processing circuitry has a plurality of operating states including a first operating state and a second
operating state, wherein in said first operating state the data processing circuitry uses virtual addresses having a greater
number of bits than virtual addresses used in said second operating state, and in said first operating state said data processing
circuitry is configured to execute instructions from a first instruction set, and in said second operating state said data
processing circuitry is configured to support execution of instructions from a second instruction set and a third instruction
set; and

wherein said data processing circuitry is configured to determine, upon entry of said data processing circuitry into said
debug mode, a current operating state of said data processing apparatus and to allocate said debug instruction set depending
upon said current operating state, wherein said data processing circuitry is configured to allocate said first instruction
set as said debug instruction set if said current operating state is said first operating state, and to allocate said second
instruction set as said debug instruction set if said current operating state is said second operating state regardless of
whether said data processing circuitry executed instructions from said second instruction set or said third instruction set
prior to said entry into said debug mode.

US Pat. No. 9,354,765

TEXT INPUT MODE SELECTION METHOD

Gold Charm Limited, Apia...

1. A text input mode selection method executable by an electronic device, comprising:
displaying a first virtual keyboard area, wherein the first virtual keyboard area comprises a plurality of alphabet keys;
utilizing the first virtual keyboard area as a base for one or more touch operations detectable by a touch detection function,
wherein the first virtual keyboard area is operable to be switched to and retain activation of one of a plurality of character
input methods, activation and deactivation of each of the plurality of character input methods is controlled by an input mode
switching key separated from the plurality of alphabet keys, each of the plurality of character input methods defines a keyboard
layout and a keyboard function such that the plurality of character input methods define a plurality of keyboard layouts and
a plurality of keyboard functions, each of the plurality of keyboard layouts defines association which maps each character
in an alphabet of a language to one of the plurality of alphabet keys such that each key of the plurality of alphabet keys
is operable as a toggle key and is associated with one or more characters for text input, each of the plurality of keyboard
functions defines input patterns for each of the plurality of alphabet keys such that each of the plurality of alphabet keys
is operable to output one character in response to a key operation conforming to one of the input patterns;

receiving activation of the input mode switching key, wherein the input mode switching key is associated with key options,
each of key options is associated with one of the plurality of character input methods, and the input mode switching key is
operable as a toggle key;

selecting a target key option among the key options through switching among the key options from a first key option to a second
key option according to a preset arrangement of the key options in response to the activation of the input mode switching
key conforming to a first input pattern;

displaying the key options associated with the input mode switching key in a graphical user interface (GUI) component in response
to the activation of the input mode switching key conforming to a second input pattern, wherein each of the key options is
selectable through the graphical user interface component;

selecting one of the key options as the target key option in response to a selecting operation based on the graphical user
interface component through switching among the key options from the first key option to a user selected key option according
to a user selected arrangement of the key options; and

allowing activation of the input mode switching key according to the target key option;
wherein activation of the input mode switching key according to a currently selected one of the key options activates a switching
among the plurality of character input methods from a first character input method to a second character input method, the
switching among the plurality of character input methods comprises deactivation of the first character input method and activation
of the second character input method, the first character input method of the plurality of character input methods is associated
with a previously selected one of the key options and represents a first one of the plurality of keyboard layouts and a first
one of the plurality of keyboard functions, and the second character input method of the plurality of character input methods
is associated with the currently selected one of the key options and represents a second one of the plurality of keyboard
layouts and a second one of the plurality of keyboard functions.

US Pat. No. 9,189,646

PROTECTION CIRCUITY AND METHOD FOR CONTROLLING ACCESS BY PLURAL PROCESSES TO A MEMORY

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
plural data processors configured to execute plural processes;
a memory configured to store data required for said plural processes; and
a protection circuitry configured to control access by said plural processes to said memory, wherein said protection circuitry
is configured to define an allocated access region of said memory for each process of said plural processes, wherein said
protection circuitry is configured to deny access for each said process outside said allocated access region and wherein allocated
access regions are defined to be non-overlapping,

wherein said protection circuitry is configured to define each said allocated access region as a contiguous portion of said
memory between a lower region limit and an upper region limit,

and wherein said protection circuitry is configured to prevent said lower region limit from being decreased when said lower
region limit is modified, and to prevent said upper region limit from being decreased when said upper region limit is modified.

US Pat. No. 9,450,571

DATA AND CLOCK SIGNAL VOLTAGES WITHIN AN INTEGRATED CIRCUIT

ARM Limited, Cambridge (...

1. An integrated circuit comprising:
data processing circuitry configured to process a data signal passing along a data path within said data processing circuitry;
clocked circuitry coupled to said data processing circuitry and configured to regulate passage of said data signal along said
data path under control of a clock signal;

data power supply circuitry coupled to said data processing circuitry and configured to supply power to said data processing
circuitry; and

clock power supply circuitry coupled to said clocked circuitry and configured to supply power to said clocked circuitry;
wherein said data power supply circuitry and said clock power supply circuitry are configured such that, at least when said
data processing circuitry is actively processing said data signal passing along said data path, said data signal has a data
signal voltage amplitude and said clock signal has a clock signal voltage amplitude that is different from said data signal
voltage amplitude,

wherein said data power supply circuitry is configured to operate in a plurality of modes having different associated data
signal voltage amplitudes, and

wherein said clock power supply circuitry is configured to operate in a plurality of modes having different associated clock
signal voltage amplitudes.

US Pat. No. 9,306,545

MASTER-SLAVE FLIP-FLOP CIRCUIT AND METHOD OF OPERATING THE MASTER-SLAVE FLIP-FLOP CIRCUIT

ARM Limited, Cambridge (...

1. A master-slave flip-flop circuit for generating an output signal in response to an input signal and a clock signal, the
master-slave flip-flop circuit comprising:
a master latch configured to capture a master signal dependent on the input signal during a first phase of the clock signal
and to retain the master signal during a second phase of the clock signal;

a slave latch configured to capture a slave signal dependent on the master signal during the second phase of the clock signal
and to retain the slave signal during the first phase of the clock signal, wherein the output signal is dependent on the slave
signal; and

clock generating circuitry configured to:
invert the clock signal to generate an inverted clock signal; and
generate a gated clock signal based on the clock signal and a gating control signal,
wherein the clock generating circuitry comprises a logic gate configured to receive the inverted clock signal and the gating
control signal as inputs and to output the gated clock signal;

at least one clocked component controlled by the gated clock signal; and
at least one clocked component controlled by the inverted clock signal,
wherein the clock generating circuitry is further configured to generate the gated clock signal with a value dependent on
the clock signal when the gating control signal has a first value, and to generate the gated clock signal with a fixed value
independent of the clock signal when the gating control signal has a second value, and

wherein the gating control signal is dependent on the input signal or a signal at a signal node of the master latch, and is
independent of the slave signal and the output signal.

US Pat. No. 9,214,006

HIDDEN SURFACE REMOVAL IN GRAPHICS PROCESSING SYSTEMS

ARM LIMITED, Cambridge (...

1. A method of operating a graphics processing pipeline that includes a plurality of processing stages including a rasteriser
that rasterises input primitives to generate graphic fragments to be processed, each graphics fragment having one or more
sampling points associated with it, and a renderer that processes fragments generated by the rasteriser to generate output
fragment data, the method comprising:
performing an early culling test in respect of at least one sampling point associated with a fragment generated by the rasteriser
before the fragment is sent to the renderer for processing; and

if the at least one sampling point passes the early culling test, sending the fragment onwards for processing and in response
to the at least one sampling point passing the early culling test, determining if the processing of another sampling point
that is in the graphics processing pipeline should be slowed down.

US Pat. No. 9,430,419

SYNCHRONIZING EXCEPTION CONTROL IN A MULTIPROCESSOR SYSTEM USING PROCESSING UNIT EXCEPTION STATES AND GROUP EXCEPTION STATES

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
a plurality of processing units, each processing unit executing a stream of program instructions corresponding to a processing
thread;

a plurality of groups comprising the plurality of processing units, wherein each processing unit is in one of said plurality
of groups; and

exception control circuitry configured to control exception processing of a group of said plurality of groups in response
to an exception triggering event that corresponds with only said group out of said plurality of groups, wherein said exception
control circuitry is configured to control each processing unit of said processing units within said group to respond to said
exception triggering event by in sequence interrupting execution of said stream of program instructions associated with that
processing unit, executing a stream of exception handling program instructions to perform exception processing, and resuming
execution of said stream of program instructions associated with that processing unit,

wherein for each processing unit of said processing units within said group said exception control circuitry is configured
to control traversal only once for said exception triggering event of a sequence of processing unit exception states,

wherein said sequence of processing unit exception states are in turn:
(i) normal corresponding to processing of said stream of program instructions associated with that processing unit;
(ii) in-exception corresponding to processing of said exception handling program instructions; and
(iii) done-exception corresponding to resumed processing of said stream of program instructions associated with that processing
unit; and

wherein said exception control circuitry is configured to move all of said processing units within said group from said done-exception
state to said normal state upon starting of exception processing by all of said processing units within said group.

US Pat. No. 9,256,466

DATA PROCESSING SYSTEMS

ARM LIMITED, Cambridge (...

1. A method of operating a data processing system which includes an execution pipeline that includes one or more programmable
execution stages which execute instructions to perform data processing operations, and in which execution threads may be grouped
together into thread groups in which the threads of the group are executed in lockstep, one instruction at a time, the method
comprising:
for an atomic operation to be executed for a thread group by an execution stage of the execution pipeline, the atomic operation
having an associated arithmetic operation:

issuing to the execution stage an instruction or instructions to determine whether there is a set of threads in the thread
group for which the atomic operation for the threads accesses the same memory location; and to, if such a set of threads is
identified, perform the atomic operation for the set of threads by:

providing to the second thread in the set of threads, the first thread's register value for the atomic operation, performing
for the second thread in the set of threads the arithmetic operation for the atomic operation using the second thread's register
value for the atomic operation and the first thread's register value for the atomic operation, and performing for each thread
in the set of threads other than the first and second threads, if any, the arithmetic operation for the atomic operation using
the thread's register value for the atomic operation and the result of the arithmetic operation for the preceding thread in
the set of threads, to thereby generate for the final thread in the identified set of threads a combined result of the arithmetic
operation for the set of threads; and

then executing, for the identified set of threads, a single atomic memory operation to the memory location for the atomic
operation for the set of threads using the combined result of the arithmetic operation for the set of threads as its register
argument; and

the execution stage of the execution pipeline in response to the instructions:
determining whether there is a set of threads in the thread group for which the atomic operation for the threads accesses
the same memory location; and, if such a set of threads is identified, performing the atomic operation for the set of threads
by:

providing to the second thread in the set of threads, the first thread's register value for the atomic operation;
performing for the second thread in the set of threads the arithmetic operation for the atomic operation using the second
thread's register value for the atomic operation and the first thread's register value for the atomic operation; and

performing for each thread in the set of threads other than the first and second threads, if any, the arithmetic operation
for the atomic operation using the thread's register value for the atomic operation and the result of the arithmetic operation
for the preceding thread in the set of threads,

to thereby generate for the final thread in the identified set of threads a combined result of the arithmetic operation for
the set of threads; and

then executing for the identified set of threads a single atomic memory operation to the memory location for the atomic operation
for the set of threads using the combined result of the arithmetic operation for the set of threads as its register argument.

US Pat. No. 9,454,451

APPARATUS AND METHOD FOR PERFORMING DATA SCRUBBING ON A MEMORY DEVICE

ARM Limited, Cambridge (...

1. An apparatus for accessing a memory device in response to access requests issued by at least one requesting device, said
apparatus comprising:
interface circuitry configured to access said memory device in response to said access requests;
activity monitoring circuitry configured to generate memory access activity data resulting from memory access activity between
said interface circuitry and said memory device; and

scrubbing circuitry comprising:
a plurality of scrubbing handlers configured to perform an associated scrubbing operation in response to said memory access
activity indicating a trigger condition; each scrubbing operation being defined by configuration data associated with each
scrubbing handler and defining said associated scrubbing operation,

wherein said scrubbing circuitry is configured to issue at least one scrubbing access request for processing by the interface
circuitry in dependence on said configuration data.

US Pat. No. 9,317,948

METHOD OF AND APPARATUS FOR PROCESSING GRAPHICS

ARM LIMITED, Cambridge (...

1. A method of sorting graphics primitives for rendering into lists representing different areas of a render target to be
generated in a tile-based graphics processing system, the method comprising:
dividing by processing circuitry a render target into plural rendering tiles for rendering purposes;
preparing by processing circuitry primitive lists indicating primitives to be processed for at least two different sets of
sub-regions of the render target area, at least one of the two different sets of sub-regions of the render target area comprising
sub-regions of the render target area that are bigger than a single rendering tile;

the method further comprising:
for a primitive to be rendered:
determining by processing circuitry sub-regions of at least two of the at least two different sets of sub-regions of the render
target area that the primitive could need to be listed for in order to render the primitive;

using a cost function by the processing circuitry to determine plural cost values representing the cost of listing the primitive
in the primitive lists for the render target area sub-regions that it has been determined that the primitive could need to
be listed for; and

selecting by the processing circuitry which of the render target area sub-regions that it has been determined that the primitive
could need to be listed for in order to render the primitive to list the primitive for based on the determined plural cost
values, and including the primitive in the primitive lists of those selected sub-regions by the processing circuitry.

US Pat. No. 9,299,126

IMAGE PROCESSING APPARATUS AND A METHOD OF STORING ENCODED DATA BLOCKS GENERATED BY SUCH AN IMAGE PROCESSING APPARATUS

ARM Limited, Cambridge (...

1. An image processing apparatus, comprising:
encoder circuitry configured to perform an encoding operation on input data blocks in order to generate encoded data blocks,
an image being formed by a plurality of said input data blocks, and each of said input data blocks comprising a plurality
of data values;

write circuitry configured to perform a write operation in order to store the encoded data blocks to a memory for subsequent
access by decoding circuitry;

identifier generation circuitry configured, for each input data block, to generate an identifier value that is dependent on
the plurality of data values of the input data block;

a lookup storage configured to store predetermined information relating to at least one encoded data block, said predetermined
information being stored within the lookup storage in association with the identifier value for the corresponding input data
block; and

lookup circuitry configured, for a current input data block, to determine whether a match exists between the identifier value
generated for said current input data block and an identifier value stored in the lookup storage;

the write circuitry being configured, in the presence of said match, to use the predetermined information stored in the lookup
storage in association with the matching identifier value, when performing the write operation associated with the current
input data block.

US Pat. No. 9,391,614

CLOCK STATE CONTROL FOR POWER SAVING IN AN INTEGRATED CIRCUIT

ARM Limited, Cambridge (...

1. An integrated circuit comprising:
at least one sequential logic element; and
clock supply circuitry configured to supply a clock signal to the at least one sequential logic element, wherein the clock
supply circuitry comprises at least one clock gate configured to:

receive an enable signal; and
receive an input clock signal, wherein the input clock signal is in a first state of the input clock signal for a greater
fraction of each clock cycle than a second state of the input clock signal;

wherein in response to a first state of the clock signal, the at least one sequential logic element is configured to consume
less static power than in response to a second state of the clock signal; and

wherein the clock supply circuitry is configured to supply the first state of the clock signal to the at least one sequential
logic element for a greater amount of time than the second state of the clock signal.

US Pat. No. 9,201,651

DATA PROCESSING APPARATUS AND METHOD HAVING INTEGER STATE PRESERVATION FUNCTION AND FLOATING POINT STATE PRESERVATION FUNCTION

ARM Limited, Cambridge (...

1. A data processing apparatus, comprising:
a first set of integer registers;
a second set of floating point registers; and
processing circuitry responsive to data processing instructions and configured to execute integer data processing operations
using the first set of integer registers and floating point data processing operations using the second set of integer registers;

wherein:
said processing circuitry is responsive to an interrupt request to perform one of an integer state preservation function in
which at least a subset of said integer registers are copied to a stack memory without copying said floating point registers
to the stack memory, and a floating point state preservation function in which at least a subset of both said integer registers
and said floating point registers are copied to said stack memory, said one of said integer state preservation function and
said floating point state preservation function being selected by said processing circuitry in dependence on state information,
said state information comprises first state information indicative of whether a current data processing context being executed
by said processing circuitry when the interrupt request is received is a floating point data processing context which includes
one or more floating point data processing operations or an integer data processing context which does not include any floating
point data processing operations;

said first state information is set in response to a data processing instruction which causes the processing circuitry to
execute floating point data processing operations;

said processing circuitry is responsive to said interrupt request to perform said integer state preservation function if said
first state information indicates that the current data processing context is an integer data processing context, and to perform,
if said first state information indicates that the current data processing context is a floating point data processing context,
a first part of said floating point state preservation function in which the subset of integer registers are copied to the
stack memory and a second part of said floating point state preservation function including allocating space on the stack
memory for the subset of floating point registers without copying the subset of floating point registers to the stack memory;
and

said processing circuitry is configured to perform a third part of said floating point state preservation function in which
the subset of floating point registers are copied to the allocated portion of the stack memory, responsive to a determination
that a data processing instruction is to be executed following the allocation of space on the stack memory, which causes the
processing circuitry to execute floating point data processing operations.

US Pat. No. 9,384,091

ERROR CODE MANAGEMENT IN SYSTEMS PERMITTING PARTIAL WRITES

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
error code generating circuitry configured to generate an error code for a data block comprising a plurality of data values,
said error code having a value dependent upon said plurality of data values;

a memory configured to store one or more data values of said data block and said error code; and
memory scrubbing circuitry coupled to said memory and configured to perform a periodic memory scrub operation in which data
values of said data block are checked with said error code and, if said data block has an invalid error code, then all data
values for said data block are written to said memory and said error code is updated;

wherein said error code generating circuitry is configured such that:
(i) when one or more data values within said data block are written to said memory and all data values within said data block
are stored within said memory, said error code generating circuitry generates an updated value of said error code for said
data block; and

(ii) when one or more data values within said data block are written to said memory and a proper subset of said data values
within said data block are stored within said memory, said error code generating circuitry marks as invalid said error code
for said data block, and

wherein said memory is part of a memory hierarchy including at least one higher order memory and said memory scrubbing circuitry
is configured to read any data values of said data block not present within said memory from said higher order memory.

US Pat. No. 9,142,037

METHODS OF AND APPARATUS FOR ENCODING AND DECODING DATA

ARM LIMITED, Cambridge (...

1. A method of determining for a set of texture data elements to be encoded for use in a graphics processing system, a direction
in the data space of the texture data elements to be used when determining a base data value or values to be used for the
set of texture data elements when encoding the set of texture data elements, the method comprising:
determining by processing circuitry, for at least one plane that divides the set of texture data elements to be encoded into
two groups in the data space, the direction of a vector in the data space from a point in the data space that is based on
the values of texture data elements of the set of texture data elements to be encoded whose values lie on one side of the
plane in the data space to a point in the data space that is based on the values of texture data elements of the set of texture
data elements to be encoded whose values lie on the other side of the plane in the data space; and

using, by the processing circuitry, the direction determined in the data space of the texture data elements for at least one
of the at least one planes that divide the set of texture data elements into two groups in the data space to determine a direction
in the data space to be used when determining a base data value or values to be used for the set of texture data elements
when encoding the set of texture data elements.

US Pat. No. 9,419,105

METHOD FOR PROCESSING SUBSTRATE AND METHOD FOR FABRICATING APPARATUS

Gold Charm Limited, Apia...

1. A method for processing a substrate, the substrate comprising an organic film pattern, the method comprising:
a fusion/deformation step of fusing said organic film pattern to deform the fused organic film pattern; and
a third removal step of removing at least a part of the fused and deformed organic film pattern;
wherein the substrate further comprises a semiconductor film and a metal film, said metal film is formed on said semiconductor
film, said organic film pattern is formed on the metal film, the organic film pattern is a resist pattern, and the method
further comprises:

a first etching step of etching said metal film with said resist pattern being used as a mask;said first etching step being carried out before said fusion/deformation step;
wherein said etched metal film and said fused and deformed organic film pattern form a joint resist mask, the method further
comprises:

a second etching step of etching said semiconductor film with said joint resist mask, said second etching step being carried
out after said fusion/deformation step before said third removal step;

wherein said metal film is turned into a source electrode and a drain electrode of a thin film transistor (TFT) by said first
etching step;

wherein the method further comprising:
a third etching step of etching said semiconductor film to form a channel of the said TFT, the third etching step being carried
out after said third removal step.

US Pat. No. 9,411,774

MEMORY ACCESS CONTROL

ARM Limited, Cambridge (...

1. Memory access circuitry for controlling access to a memory comprising multiple memory units arranged in parallel with each
other, said memory access circuitry comprising:
two access units each configured to select one of said multiple memory units in response to a received memory access request
and to control and track subsequent accesses to said selected memory unit, said multiple memory units comprising at least
three memory units;

arbitration circuitry configured to receive said memory access requests from a system and to select and forward said memory
access requests to one of said two access units, said arbitration circuitry being configured to forward a plurality of memory
access requests for accessing one memory unit to a first of said two access units, and to forward a plurality of memory access
requests for accessing a further memory unit to a second of said two access units and to subsequently forward a plurality
of memory access requests for accessing a yet further memory unit to one of said first or second access units;

said two access units comprising:
storing circuitry to store requests in a queue prior to transmitting said requests to said respective memory unit; and
tracking circuitry to track said requests sent to said respective memory units and to determine when to transmit subsequent
requests from said queue; and

control circuitry configured to set a state of each of said two access units, said state being one of active, prepare and
dormant, said access unit in said active state being operable to transmit both access and activate requests to said respective
memory unit, said activate request preparing said access in said respective memory unit and said access request accessing
said data, said access unit in said prepare state being operable to transmit said activate requests and not said access requests,
said access unit in said dormant state being operable not to transmit either said access or said activate requests, said control
circuitry being configured to switch states of said two access units periodically and to set not more than one of said access
units to said active state at a same time.

US Pat. No. 9,372,811

RETENTION PRIORITY BASED CACHE REPLACEMENT POLICY

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
a plurality of sources of memory access requests;
a cache memory coupled to said plurality of sources; and
cache control circuitry coupled to said cache memory and configured to control insertion of cache lines into said cache memory
and eviction of cache lines from said cache memory, wherein

said cache control circuitry is configured to store respective retention priority values associated with each cache line inserted
into said cache memory;

said cache control circuitry is configured to select a cache line for eviction from said cache memory in dependence upon said
retention priority values; and

said cache control circuitry is configured to set a retention priority value associated with a cache line inserted into said
cache memory in dependence upon at least one of:

(i) which of instruction fetch circuitry of a processor to fetch program instructions for execution and load store unit circuitry
of said processor to access data values under control of said program instructions issued a memory access request that resulted
in insertion of said cache line into said cache memory; and

(ii) a privilege level of program execution resulting in said memory access request.

US Pat. No. 9,300,716

MODELLING DEPENDENCIES IN DATA TRAFFIC

ARM Limited, Cambridge (...

1. A method of modifying timings of data traffic in a test system by introducing dependencies that would arise in response
to data requiring access to a resource, wherein said test system comprises a model of a system comprising said resource receiving
said data traffic from at least one initiator and being connected via an interconnect to at least one recipient, said resource
comprising a buffer for storing pending data related to an access to said resource that cannot currently complete; said method
comprising the steps of:
storing for said test system a maximum value of a counter which represents said buffer, to a value representative of a buffer
size of said buffer;

inputting data representative of modeled data traffic;
updating said counter in response to said data requiring said resource and being stored in said buffer and in response to
said data traffic indicating a buffer entry has become available;

determining for said test system where said data requires said buffer and said counter is at the maximum value indicating
said buffer is full;

modifying a timing of said data access requiring said buffer indicating that said data is stalled until said buffer has capacity
again;

updating said data traffic with said modified timing for said test system,
wherein said resource comprises a cache, said dependencies being dependencies that would arise in response to data accesses
to said cache, said at least one recipient comprising at least one higher memory level, and said cache comprising said buffer
for storing data related to a data access to said cache that cannot complete before an access to said higher memory level
is made;

said method comprising the further steps of:
determining from said data traffic and from characteristics of said cache whether data accesses within said data traffic will
hit or miss in said cache and if data is to be written to or evicted from said cache;

updating said counter in response to said data accesses requiring said buffer and in response to said data traffic indicating
a buffer entry has become available.

US Pat. No. 9,292,298

DATA PROCESSING APPARATUS HAVING SIMD PROCESSING CIRCUITRY

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
single instruction multiple data (SIMD) processing circuitry configured to perform a SIMD operation on first and second SIMD
operands comprising a plurality of data elements, the SIMD processing circuitry having a plurality of parallel processing
lanes for processing corresponding data elements of the first and second SIMD operands;

permutation circuitry configured to perform a permutation operation on at least one source operand comprising a plurality
of source data elements to generate said first and second SIMD operands, said permutation operation generating at least one
of said first and second SIMD operands with at least one of a different data element size and a different data element positioning
to said at least one source operand; and

an instruction decoder configured to decode SIMD instructions requiring the SIMD operation to be performed by the SIMD processing
circuitry;

wherein in response to a first SIMD instruction requiring the permutation operation and identifying the at least one source
operand, the instruction decoder is configured to control the permutation circuitry to perform the permutation operation on
the at least one source operand to generate the first and second SIMD operands, and to control the SIMD processing circuitry
to perform the SIMD operation using the first and second SIMD operands generated by the permutation circuitry; and

in response to a second SIMD instruction not requiring the permutation operation and identifying the first and second SIMD
operands, the instruction decoder is configured to control the SIMD processing circuitry to perform the SIMD operation using
the first and second SIMD operands identified by the second SIMD instruction, without passing the first and second SIMD operands
via the permutation circuitry.

US Pat. No. 9,281,027

TEST TECHNIQUES IN MEMORY DEVICES

ARM Limited, Cambridge (...

1. A memory device comprising:
latching circuitry to receive a latching value and to provide said latching value as an output;
a path to receive said latching value and to pass said latching value to said latching circuitry;
first storage circuitry to provide a first stored value when said memory device is in a read mode of operation;
a bit line connected to said first storage circuitry;
first control circuitry to selectively connect said bit line to said path;
sensing circuitry to, when an enable signal is active, detect a voltage change on said path as a result of connecting said
bit line to said first storage circuitry and said path, and to output said latching value on said path, wherein said latching
value is dependent on said voltage change;

second storage circuitry to provide a second stored value when said memory device is in a test mode of operation; and
second control circuitry to receive said second stored value and to selectively output said second stored value as said latching
value on said path,

wherein said latching circuitry is to output said latching value as said output in dependence on said enable signal, such
that said enable signal controls both said latching circuitry and said sense circuitry.

US Pat. No. 9,286,069

DYNAMIC WRITE PORT RE-ARBITRATION

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
a register bank configured to store input operands and output operands of data processing operations performed under control
of program instructions, said register bank having one or more write ports;

processing pipeline circuitry having a plurality of pipeline stages, said processing pipeline circuitry coupled to said register
bank via at least said one or more write ports and configured to perform a data processing operation under control of a program
instruction and a processing clock signal over a plurality of clock cycles of said processing clock signal to generate one
or more output operands; and

issue control circuitry configured to issue of said program instruction during a starting clock cycle into said processing
pipeline circuitry to commence said data processing operation; wherein

said issue control circuitry is configured to select said starting clock cycle such that, at a first predetermined number
of clock cycles following said starting clock cycle, at least a minimum number of said one or more write ports will be available
to permit said one or more output operands to be written to said register bank; and

said processing pipeline circuitry includes bypass circuitry configured:
to detect, after said program instruction has been issued into said processing pipeline circuitry, a predetermined state generated
by partial completion of said processing operation and indicative of permitted early generation of said one or more output
operands; and

if (i) said predetermined state is detected, and (ii) said one or more previously issued program instructions indicate that
at least said minimum number of said one or more write ports will be available to permit said one or more output operands
to be written to said register bank at a second predetermined number of clock cycles following said starting clock cycle,
said second predetermined number being fewer than said first predetermined number, then to bypass one or more of said pipeline
stages such that said one or more output operands are written to said register bank during a clock cycle following said starting
clock cycle by said second predetermined number.

US Pat. No. 9,379,710

LEVEL CONVERSION CIRCUIT AND METHOD

ARM Limited, Cambridge (...

1. A level conversion circuit for generating an output signal on an output line in response to one or more input signals having
one of a higher input level and a lower input level, and the output signal having one of a higher output level and a lower
output level, the level conversion circuit comprising:
input circuitry coupled to a first supply node for supplying the higher input level and having a first input for receiving
a first input signal, a second input for receiving a second input signal, and an output coupled to the output line, wherein:

the input circuitry is configured to output a temporary output signal on the output line having one of the higher input level
and the lower input level,

the input circuitry is configured to output a rising transition of the temporary output signal towards the higher input level
in response to a first transition of the first input signal between the higher input level and the lower input level, and

following a second transition of the first input signal in an opposite direction to the first transition, the input circuitry
is configured to output the rising transition of the temporary output signal in response to a predetermined transition of
the second input signal between the higher input level and the lower input level; and

output control circuitry coupled to the output line and a second supply node for supplying the higher output level, and configured
to detect the rising transition of the temporary output signal on the output line and, in response to detecting the rising
transition of the temporary output signal, to pull the output signal on the output line to the higher output level.

US Pat. No. 9,213,359

INTERFACE FOR CONTROLLING THE PHASE ALIGNMENT OF CLOCK SIGNALS FOR A RECIPIENT DEVICE

ARM Limited, Cambridge (...

1. Interface circuitry for transmitting transactions between an initiator and a recipient, said interface circuitry comprising:
a clock input for receiving a clock signal;
at least one transaction input for receiving transactions;
at least one clock output for outputting said clock signal;
a first clock path for transmitting said clock signal from said clock input to said clock output;
at least one transaction output for outputting said transactions to said recipient;
at least one synchronising circuit clocked by said clock signal configured to transmit said transactions to said at least
one transaction output in response to said clock signal;

a second clock path for transmitting said clock signal from said clock input to said at least one synchronising circuit;
a controllable delay circuit arranged on one of said first or said second clock paths and configured to provide said clock
signal with a delay;

a further synchronising circuit configured to provide a similar delay as said at least one synchronising circuit and arranged
in parallel with said at least one synchronising circuit such that a clock signal travelling to said further synchronising
circuit travels along substantially a same path as a signal travelling to said at least one synchronising circuit;

phase detection circuitry configured to receive a clock signal output by said further synchronising circuit and a clock signal
from a location on said first clock path close to said at least one clock output and to detect alignment of said received
clock signals; and

calibration control circuitry configured to adjust a delay of said controllable delay circuit during calibration until said
phase detection circuitry detects said alignment of said clock signals;

said calibration control circuitry being configured to control said controllable delay circuit to generate a delay to said
clock signal in dependence upon said delay that generated said alignment detected during calibration during operation of said
interface circuitry.

US Pat. No. 9,092,215

MAPPING BETWEEN REGISTERS USED BY MULTIPLE INSTRUCTION SETS

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
a plurality of registers configured to store data values to be processed;
processing circuitry coupled to said plurality of registers and configured to perform data processing operations upon data
values stored in said plurality of registers;

an instruction decoder coupled to said processing circuitry and responsive to a stream of program instructions to control
said processing circuitry to perform said data processing operations; wherein

said instruction decoder is responsive to program instructions of a first instruction set to control said processing circuitry
to perform said data processing operations using N-bit architectural registers provided by said plurality of registers, where
N is a positive integer value;

said instruction decoder is responsive to program instructions of a second instruction set to control said processing circuitry
to perform said data processing operations using M-bit architectural registers provided by said plurality of registers, where
M is a positive integer value different from N and at least some of said plurality of registers are shared by program instructions
of said first instruction set and program instructions of said second instruction set;

said instruction decoder is configured to decode a register specifying field within a program instruction of said first instruction
set when determining which of said plurality of registers to access as part of a first set of N-bit architectural registers
presented for use by program instructions of said first instruction set;

said instruction decoder is configured to decode a register specifying field within a program instruction of said second instruction
set when determining which of said plurality of registers to access as part of a second set of M-bit architectural registers
presented for use by program instructions of said second instruction set; and

said instruction decoder is configured to provide a first mapping between values of said register specifying field within
program instructions of said first instruction set and said plurality of registers and a second mapping between values of
said register specifying field within program instructions of said second instruction set and said plurality of registers,
said first mapping is different from said second mapping and said first mapping and said second mapping are configured so
each register of said first set has a predetermined one-to-one mapping to a register of said second set, shares with said
register of said second set a shared part of a common register within said plurality of registers, an unshared part of said
common register being unaccessible using instructions of said first instruction set, and stores a value that is accessible
using a register of said second set, wherein said apparatus when executing program instructions of said first instruction
set is configured to operate in a plurality of exception states and said instruction decoder is configured to decode said
register specifying field within a program instruction of said first instruction set together with a current exception state
of said plurality of exception states when determining which of said plurality of registers to access and a group of registers
within said first set corresponding to a common value of said register specifying field within said program instruction of
said first instruction set and different exception states are a banked group of registers,

wherein within said banked group of registers a value of a least significant bit of said register specifying field within
said program instruction of said first instruction set is common with a value of a least significant bit of said register
specifying field within said program instruction of said second instruction set,

wherein said instruction decoder is configured to provide said first mapping and said second mapping wherein, for a portion
of said registers of said second set corresponding to a sequence of incrementing values of said register specifying field
within said program instruction of said second instruction set, corresponding values of said register specifying field within
said program instruction of said first instruction set alternate between two values.

US Pat. No. 9,757,329

PHARMACEUTICAL COMPOSITION COMPRISING BOTULINUM, A NON IONIC SURFACTANT, SODIUM CHLORIDE AND SUCROSE

Ipsen Biopharm Limited, ...

1. A solid or liquid pharmaceutical composition consisting of:
(a) botulinum neurotoxin complex of type A, B, C, D, E, F or G, or a high purity botulinum neurotoxin of type A, B, C, D,
E, F or G;

(b) a non-ionic surfactant;
(c) sodium chloride;
(d) a buffer capable of maintaining an aqueous solution at a pH of 5.5 to 7.5;
(e) a disaccharide; and
(f) when the composition is liquid, water,
wherein the composition does not contain albumin or polysaccharides.

US Pat. No. 9,367,953

GRAPHICS PROCESSING SYSTEMS

ARM Limited, Cambridge (...

1. A method of processing a scene for display in a graphics processing system, the method comprising:
identifying an object in the scene;
generating a first bounding volume representing the object in the scene;
processing some or all of the scene by performing a depth-only rendering pass in respect of the generated first bounding volume
for the object to assess whether the first bounding volume representing the object is at least partially occluded by one or
more other objects in the scene as it will be displayed; and

determining whether or not to process the object for display on the basis of the assessment;
wherein the graphics processing system is configured to operate in a plurality of rendering states, one of said rendering
states being a depth-only rendering state, the method further comprising:

tagging the first bounding volume and/or its corresponding primitive or primitives with a rendering state index or predefined
fragment program address such that the graphics processing system, on recognizing said rendering state index or predefined
fragment program address, will operate in said depth-only rendering state when processing the first bounding volume;

the method further comprising, if it is determined by the depth-only rendering pass that at least part of the first bounding
volume is present in the scene as it will be displayed, then:

generating two or more second bounding volumes each representing different parts of the first bounding volume;
processing some or all of the scene by performing a depth-test in respect of the generated two or more second bounding volumes
for the object to assess whether the two or more second bounding volumes are at least partially occluded by one or more other
objects in the scene as it will be displayed; and

determining whether or not to process one or more parts of the object for display on the basis of the assessment.

US Pat. No. 9,213,828

DATA PROCESSING APPARATUS AND METHOD FOR PROTECTING SECURE DATA AND PROGRAM CODE FROM NON-SECURE ACCESS WHEN SWITCHING BETWEEN SECURE AND LESS SECURE DOMAINS

ARM Limited, Cambridge (...

1. A data processing apparatus, said data processing apparatus comprising:
processing circuitry configured to perform data processing operations in response to program code;
a data store configured to store data, said data store comprising a plurality of regions including a secure region and a less
secure region, the secure region configured to store sensitive data accessible by said processing circuitry when operating
in a secure domain and not accessible by said processing circuitry when operating in a less secure domain;

said data store comprising a plurality of stacks, including a secure stack in said secure region;
the processing circuitry including stack access circuitry configured in response to an event requiring a transition from the
secure domain to the less secure domain, to store predetermined processing state to the secure stack;

if said event is a first event type, the predetermined processing state stored by the stack access circuitry comprising at
least a return address which is stored at a predetermined relative location on the secure stack;

if the event is a second event type, the predetermined processing state stored by the stack access circuitry comprising at
least a first value which is stored at said predetermined relative location, where said first value is not a valid address
for program code; and

the processing circuitry further comprising fault checking circuitry configured on receipt of a first event type return from
the less secure domain to the secure domain to identify a first fault condition if the data stored in said predetermined relative
location is said first value,

wherein said first event type is a function call and said second event type is an exception or said first event type is an
exception and said second event type is a function call.

US Pat. No. 9,349,156

ADAPTIVE FRAME BUFFER COMPRESSION

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
image data generating circuitry configured to generate image data for forming a sequence of image frames to be displayed;
a frame buffer;
compression circuitry configured to compress said image data in accordance with one or more compression control parameters
to form frame-buffer image data and to write said frame-buffer image data to said frame buffer;

decompression circuitry configured to read said frame-buffer image data from said frame buffer and to decompress said frame-buffer
image data in accordance with said one or more compression control parameters to provide said image data;

display driver circuitry configured to drive a display device using said image data provided by said decompression circuitry
to display said sequence of image frames;

compression control circuitry configured:
(a) to determine if at least a portion of an image frame in successive image frames of said sequence of image frames is subject
to less than a threshold amount of change for greater than a threshold time; and

(b) if said portion is subject to less than said threshold amount of change for greater than said threshold time, then to
change said one or more compression control parameters used for said portion:

(i) to decrease energy consumed by said decompression circuitry while reading said portion from said frame buffer;
(ii) to hold a degree of lossiness for said portion due substantially constant; and
(iii) to increase energy consumed by said compression circuitry while compressing said portion and writing said portion to
said frame buffer.

US Pat. No. 9,170,979

CONVERGING INTERCONNECT NODE CONTROLLING OPERATION RELATED TO ASSOCIATED FUTURE ITEM IN DEPENDENCE UPON DATA PREDICTED BASED ON CURRENT TRANSACTION DATA ITEM PASSING THROUGH

ARM Limited, Cambridge (...

1. An integrated circuit comprising:
one or more transactions data sources;
one or more transaction data destinations; and
interconnect circuitry coupled to said one or more transactions data sources and said one or more transaction data destinations
and configured to transfer transaction data between said one or transaction data sources and said one or more transaction
data destinations; wherein

said interconnect circuitry comprises a plurality of interconnect nodes and said interconnect circuitry is configured to transfer
transaction data between said interconnect nodes along a plurality of data paths between said one or more transaction data
sources and said one or more transaction data destinations; and

at least one of said plurality of interconnect nodes is a converging interconnect node disposed at a point of convergence
between two or more of said plurality of data paths, said converging interconnect node comprising:

prediction data generation circuitry configured to generate prediction data based upon a current item of transaction data
passing through said converging interconnect node, said prediction data including at least data indicative of a prediction
of a time when a future item of transaction data associated with said current item of transaction data will arrive at said
converging interconnect node;

prediction data storage circuitry coupled to said prediction data generation circuitry and configured to store said prediction
data; and

prediction data evaluation circuitry coupled to said prediction data storage circuitry and configured to control operation
of said converging interconnect node in dependence upon said prediction data with respect to the future item.

US Pat. No. 9,311,088

APPARATUS AND METHOD FOR MAPPING ARCHITECTURAL REGISTERS TO PHYSICAL REGISTERS

ARM Limited, Cambridge (...

1. Apparatus for processing data, comprising:
a set of physical registers for storing data;
processing circuitry configured to execute instructions of an instruction set, the processing circuitry requiring access to
said data when executing said instructions;

register renaming circuitry configured to map from architectural registers of a set of architectural registers to physical
registers of said set of physical registers, said set of architectural registers being registers as specified by said instructions
and said set of physical registers being physical registers for use when executing said instructions;

available register identifying circuitry, responsive to a current state of said apparatus, configured to identify which physical
registers of said set of physical registers form a pool of physical registers available to be mapped by said register renaming
circuitry to an architectural register specified by an instruction to be executed; and

configuration storage configured to store configuration data whose value is modified during operation of the processing circuitry
to identify a view of the set of architectural registers applicable to a current software execution level of the processing
circuitry, such that when said configuration data has a first value, the configuration data identifies at least one architectural
register of said set of architectural registers which is not present in said view of the set of architectural registers applicable
to the current software execution level of the processing circuitry and does not require mapping to a physical register by
the register renaming circuitry;

the available register identifying circuitry configured to reference said configuration storage, such that when said configuration
data has said first value, the number of physical registers in said pool is increased due to the reduction in the number of
architectural registers which require mapping to physical registers.

US Pat. No. 9,454,397

DATA PROCESSING SYSTEMS

ARM LIMITED, Cambridge (...

1. A method of initialising an a hypervisor interface for the control of an accelerator that acts as a shared resource in
a data processing system, wherein the data processing system comprises:
one or more processors that each execute one or more operating systems, each operating system including one or more applications;
an accelerator that provides a shared resource for a plurality of the applications;
a storage area accessible by at least the one or more processors and the accelerator;
one or more input/output interfaces for the control of the accelerator, wherein the one or more input/output interfaces comprise
one or more hypervisor interfaces; and

a hypervisor that manages the allocation of input/output interfaces to the one or more processors;
the method comprising, to initialise one of the a hypervisor interfaces:
one of the one or more processors sending a first signal to the accelerator;
the accelerator, in response to receiving the first signal, writing one or more selected pieces of information representative
of one or more capabilities of the accelerator to the storage area, and sending a second signal to the processor;

the processor, in response to receiving the second signal, reading the one or more selected pieces of information from the
storage area;

the processor sending a third signal to the accelerator; and
the accelerator configuring the a hypervisor interface in response to the third signal from the processor.

US Pat. No. 9,349,209

GRAPHICS PROCESSING SYSTEMS

ARM LIMITED, Cambridge (...

1. A method of operating a graphics processing system in which, following fragment shading operations to generate fragment
shading output data, blending may be performed selectively either using fixed-function blending hardware or by performing
a blending software routine, the method comprising:
performing fragment shading operations to generate fragment shading output data;
selecting to blend fragment shading output data by either using fixed-function blending hardware or by performing a blending
software routine;

if said selecting to perform blending is by performing the blending software routine,
performing blending using a blending software routine to blend fragment shading output data from the graphics fragment shading
operations with previously stored graphics data to generate modified graphics fragment output data;

providing at least some output data generated by the fragment shading operation to dedicated function hardware of the graphics
processing system; and

processing the at least some output data generated by the fragment shading operation by the dedicated function hardware to
generate hardware generated result data from the at least some output data generated by the fragment shading operation, wherein

the at least some output data generated by the fragment shading operation that is provided to the dedicated function hardware
when performing blending using the blending software routine comprises graphics alpha values generated by the fragment shading
operation;

the dedicated function hardware performs at least one of alpha test and alpha-to-coverage operations on the alpha values to
generate at least one of hardware generated alpha test result data and hardware generated alpha-to-coverage result data from
the alpha values generated by the fragment shading operation; and

if said selecting to blend fragment shading output data is by using fixed-function blending hardware, generating modified
graphics fragment output data by said fixed-function blending hardware based on the fragment shading output data.

US Pat. No. 9,355,061

DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING SCAN OPERATIONS

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
a vector register store configured to store vector operands;
processing circuitry configured to perform operations on vector operands retrieved from said vector register store;
control circuitry configured to control the processing circuitry to perform the operations required by one or more instructions,
said one or more instructions including a vector scan instruction specifying a vector operand comprising N vector elements
and defining a scan operation to be performed on a sequence of vector elements within the vector operand;

the control circuitry being responsive to the vector scan instruction to partition the N vector elements of the specified
vector operand into P groups of adjacent vector elements, where P is between 2 and N/2, and to control the processing circuitry
to perform a partitioned scan operation yielding the same result as the defined scan operation, the processing circuitry being
configured to perform the partitioned scan operation by performing separate scan operations on those vector elements of the
sequence contained within each group to produce intermediate results for each group, and to perform a computation operation
to combine the intermediate results into a final result vector operand containing a sequence of result vector elements.

US Pat. No. 9,442,878

PARALLEL SNOOP AND HAZARD CHECKING WITH INTERCONNECT CIRCUITRY

ARM Limited, Cambridge (...

1. Interconnect circuitry for communicating access transactions between one or more transaction sources and one or more transaction
destinations, said interconnect circuitry comprising:
buffer circuitry configured to buffer a plurality of access transactions received from said one or more transaction sources
before said plurality of access transactions are sent to respective ones of said one or more transaction destinations;

hazard checking circuitry coupled to said buffer circuitry and configured to perform one or more hazard checks upon said plurality
of access transactions buffered within said buffer circuitry such that at least some of said plurality of access transactions
are constrained to issue from said buffer circuitry in accordance with a predetermined order within said at least some of
said plurality of access transactions; and

snoop circuitry configured to perform snoop operations to manage coherence between data values stored within a plurality of
cache memories coupled to said interconnect circuitry, said snoop circuitry being configured to issue at least some snoop
requests in a given order and operate such that corresponding snoop responses are returned from said snoop circuitry in said
given order;

wherein said snoop circuitry includes snoop reordering circuitry configured to permit reordering of snoop responses received
from one or more of said cache memories to match said given order;

said snoop circuitry is configured to issue a snoop request for a given access transaction in parallel with said hazard checking
circuitry at least performing said one or more hazard checks for said given access transaction; and

if said hazard checking circuitry determines that said given access transaction is not ready to be issued from said buffer
circuitry in accordance with said predetermined order, then said snoop circuitry is configured to stall within said snoop
circuitry said corresponding snoop response to be returned from said snoop circuitry for said given access transaction.

US Pat. No. 9,361,111

TRACKING SPECULATIVE EXECUTION OF INSTRUCTIONS FOR A REGISTER RENAMING DATA STORE

ARM Limited, Cambridge (...

24. A data processing apparatus for processing a stream of program instructions, comprising first processing circuitry configured
to process at least some of the program instructions, the first processing circuitry comprising:
a plurality of registers for storing data;
register renaming circuitry configured to map architectural register specifiers identified by the program instructions to
physical register specifiers identifying the plurality of registers; and

a renaming data store configured to store a plurality of renaming entries, each renaming entry for identifying a register
mapping between at least one of the architectural register specifiers and at least one of the physical register specifiers;
wherein:

at least some renaming entries have a corresponding count value, the count value indicating a number of speculation points
occurring between generation of a previous count value for a previous renaming entry and generation of the count value, the
speculation points comprising branch operations or load/store operations; and

the count value comprises an N-bit value, where N is an integer and N>1.

US Pat. No. 9,507,737

ARBITRATION CIRCUITRY AND METHOD

ARM Limited, Cambridge (...

1. Arbitration circuitry for arbitrating between N inputs each having an associated priority value to select an output, where
N is an integer value of two or more, said arbitration circuitry comprising:
tie-break value generating circuitry configured to generate an M-bit tie-break value, where M is a lowest integer value satisfying
a condition M?log2N;

priority value modifying circuitry configured to extend respective priority values of two or more inputs by appending respective
one or more tie-break bits as one or more least significant bits to said priority values to form two or more extended priority
values, said one or more tie-break bits forming said one or more least significant bits of at least one of said extended priority
values being dependent upon said tie-break value; and

comparator circuitry configured to compare said extended priority values of said two or more inputs to select whichever of
said two or more inputs has a highest priority such that, if respective priority values within extended priority values of
any pair of inputs are the same, then a selection between said pair is made in dependence upon said respective one or more
tie-break bits within said extended priority values, the comparator circuitry including a plurality of comparator circuits
connected in accordance a binary tree having a root node and M levels, each comparator circuit corresponding to a node within
said binary tree and configured to select one of two inputs in accordance with an arbitration operation such that said root
node generates an arbitration result identifying said output,

wherein each said comparator circuit within a level of said binary tree is configured to compare respective extended priority
values of a pair of said inputs to select whichever of said pair has a higher priority, and

wherein said one or more tie-break bits include an Xth bit of said M-bit tie-break value and the value of X is constant within
each level of said binary tree and differs between each level of said binary tree.

US Pat. No. 9,324,392

MEMORY DEVICE AND METHOD OF PERFORMING A WRITE OPERATION IN A MEMORY DEVICE

ARM Limited, Cambridge (...

1. A memory device comprising:
an array of memory cells;
wordline driver circuitry to assert a wordline signal to activate an addressed memory cell in the array;
write driver circuitry to perform a write operation to write a data value into the addressed memory cell, the write driver
circuitry being responsive to assertion of a write enable signal to initiate performance of the write operation and being
responsive to later assertion of a write assist enable signal during the write operation to implement a write assist circuitry;
and

control circuitry to control timing of assertion of the wordline signal in dependence on timing of the assertion of the write
assist enable signal.

US Pat. No. 9,105,315

CONTROLLING THE VOLTAGE LEVEL ON THE WORD LINE TO MAINTAIN PERFORMANCE AND REDUCE ACCESS DISTURBS

ARM Limited, Cambridge (...

1. A semiconductor memory storage device for storing data comprising:
a plurality of storage cells for storing said data each storage cell comprising an access control device configured to provide
said storage cell with access to or isolation from a data access port in response to an access control signal;

access control circuitry configured to transmit said access control signal along one of a plurality of access control lines
to control a plurality of said access control devices connected to said one of said plurality of access control lines;

said access control circuitry comprising:
access switching circuitry configured to connect a selected access control line to a voltage source for supplying a predetermined
access voltage level;

feedback circuitry configured to feedback a change in voltage on said access control line to said access switching circuitry;
wherein

said access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected
to a corresponding selected access control line to:

control said access switching circuitry to provide a low impedance connection between said voltage source and said access
control line such that a voltage level on said access control line changes towards said predetermined access voltage level
at a first rate; and

in response to said feedback circuitry providing a feedback signal indicating that said access control line voltage has attained
a predetermined value to control said access control switching circuitry to provide a higher impedance connection between
said voltage source and said access control line such that a voltage level on said access control line changes towards said
predetermined access voltage level at a second rate said second rate being slower than said first rate;

wherein said feedback circuitry comprises a switching device for generating said feedback signal, said switching device being
of a same type as said access control devices and having substantially a same threshold voltage, said switching device switching
an output value in response to said voltage level on said access control line exceeding said threshold voltage of said switching
device, said switch in the output value indicating to said access control switching circuitry to provide the higher impedance
connection between said voltage source and said access control line.

US Pat. No. 9,454,633

VIA PLACEMENT WITHIN AN INTEGRATED CIRCUIT

ARM Limited, Cambridge (...

1. A method of forming a layout of an integrated circuit having:
a plurality of standard cells connected to draw power from standard-cell power conductors in a standard-cell conductor layer;
and

a plurality of power grid conductors disposed overlapping at least portions of said plurality standard-cell power conductors
in a further layer separate from said standard-cell conductor layer, said method comprising the steps of:

forming a power grid layout placing said plurality of power grid conductors in said integrated circuit;
subsequent to said forming a power grid layout step, a routing step forming a routing layout of routing conductors and routing
connection vias to connect different portions of said plurality of standard cells; and

subsequent to said routing step, a power grid connection step forming a power connection via layout of power connection vias
to connect said plurality of power grid conductors to said plurality of standard-cell power conductors, wherein

said power grid connection step is responsive to positions of said routing connection vias determined in said routing step
to position said power grid connection vias at positions meeting a minimum via spacing requirement from said routing connection
vias.

US Pat. No. 9,202,071

EXCEPTION HANDLING IN A DATA PROCESSING APPARATUS HAVING A SECURE DOMAIN AND A LESS SECURE DOMAIN

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
processing circuitry configured to perform data processing operations in response to program code, the processing circuitry
comprising exception control circuitry for controlling exception processing;

a data store configured to store data, the data store comprising a plurality of regions including a secure region and a less
secure region, wherein the secure region is for storing data which is accessible by the processing circuitry when operating
in a secure domain and not accessible by the processing circuitry when operating in a less secure domain; and

a plurality of registers configured to store data, the registers including a first subset of registers and a second subset
of registers, the registers being accessible to said program code executing on the processing circuitry, wherein, in response
to an exception, state saving of data from the registers to the data store is required in order to allow later restoring of
that data to the registers when the exception has been handled;

wherein:
in response to an initial exception from background processing performed by the processing circuitry, the exception control
circuitry is configured to perform state saving of data from the first subset of registers to the data store before triggering
the processing circuitry to perform an exception handling routine corresponding to the exception, wherein the exception handling
routine has responsibility for performing state saving of data from the second subset of registers to the data store; and

in response to a first exception causing a transition from the secure domain to the less secure domain, where the background
processing was performed by the processing circuitry in the secure domain, the exception control circuitry is configured to
perform additional state saving of the data from the second subset of registers to the data store before triggering the processing
circuitry to perform the exception handling routine in the less secure domain.

US Pat. No. 9,189,881

GRAPHICS PROCESSING

ARM LIMITED, Cambridge (...

1. A method of operating a graphics processing system which includes a graphics processing pipeline that includes one or more
programmable shading stages which execute graphics shader programs to perform graphics processing operations, the method comprising:
identifying in an original shader program to be executed on the graphics processing pipeline program expressions that operate
on run time constant inputs;

creating a new shader program containing instructions for executing the identified program expressions;
creating a modified version of the original shader program, the creating the modified version of the original shader program
including removing the instructions for executing the identified program expressions from the original shader program and
replacing the instructions for executing the identified program expressions with load instructions pointing to output values
generated and stored for the identified program expressions by executing the new shader program;

executing the new shader program containing the instructions for executing the identified program expressions on the graphics
processing pipeline, the executing the new shader program including generating and storing the output values for the identified
program expressions; and

subsequently executing the modified version of the original shader program on the graphics processing pipeline, the subsequently
executing the modified version of the original shader program including, in response to the load instructions of the modified
version of the original shader program, loading the output values generated and stored by executing the new shader program
for processing by the modified version of the original shader program.

US Pat. No. 9,436,473

SCHEDULING PROGRAM INSTRUCTIONS WITH A RUNNER-UP EXECUTION POSITION

ARM Limited, Cambridge (...

17. A method of processing data comprising the steps of:
executing a common program as a respective plurality of threads of program execution with a plurality of execution circuits;
and

scheduling including determining a next scheduled execution position within said common program corresponding to a next program
instruction to be executed by at least one of said plurality of execution circuits while any of said plurality of execution
circuits at a current execution position in an execution path through said common program not followed by said next scheduled
position do not execute said next program instruction; wherein said step of scheduling includes:

calculating a runner up execution position that would have been determined as said next scheduled execution position if said
next program instruction was excluded from serving as said next scheduled execution position;

determining said next scheduled execution position so as to follow an execution path corresponding to consecutive instructions
in program counter order unless a point of full determination is detected by said scheduling circuitry whereupon said a full
determination of said next scheduled execution position is performed that provides for one or more possible execution paths
not corresponding to consecutive instructions in program counter order;

calculating said runner up execution position upon said detection of a current point of full determination; and
detecting a further point of full determination if said execution path reaches said runner up execution position.

US Pat. No. 9,405,939

DATA PROCESSING ON A NON-VOLATILE MASS STORAGE DEVICE

ARM LIMITED, Cambridge (...

1. A non-volatile mass storage device comprising:
memory circuitry remotely accessible by a host file system of a host data processing device via a communication link;
processing circuitry in said non-volatile mass storage device, the processing circuitry being configured to locally access
said memory circuitry in said non-volatile mass storage device as a local file system and to generate a file for storage on
said memory circuitry;

wherein said processing circuitry in said non-volatile mass storage device is configured to be triggered to locally access
state information stored on said non-volatile mass storage device, and to dynamically generate said file comprising data derived
from said state information, by connection of said non-volatile mass storage device to said host data processing device independent
of said host file system of said host data processing device and without any interaction with software executed on said host
data processing device, and

wherein said state information comprises a combination of a serial number of said non-volatile mass storage device and a secret
key generated using a hash function.

US Pat. No. 9,404,966

PERFORMANCE CHARACTERISTIC MONITORING CIRCUIT AND METHOD

ARM Limited, Cambridge (...

1. Monitoring circuitry for provision within a device to generate an output signal indicative of a performance characteristic
of components of said device, the performance characteristic being dependent on one or more physical properties of said components,
the monitoring circuitry comprising:
first delay circuitry providing a first delay path, transmission of a data value over said first delay path incurring a first
delay that varies in dependence on said performance characteristic;

reference delay circuitry providing a reference delay path, transmission of said data value over said reference delay path
incurring a reference delay, the reference delay circuitry comprising components configured to adjust the reference delay
to be less sensitive than said first delay to variation in said performance characteristic, wherein adjusting the reference
delay is self-compensating and includes providing capacitive loading on the reference delay path; and

comparison circuitry configured to generate said output signal in dependence on a comparison of the first delay and the reference
delay,

wherein the components of reference delay circuitry comprise a plurality of resistor-capacitor blocks for providing said capacitive
loading, each resistor-capacitor block comprising a resistor element within the reference delay path and an associated capacitor
element coupled between the resistor element and a reference voltage.

US Pat. No. 9,407,931

MOTION VECTOR ESTIMATOR

ARM Limited, Cambridge (...

1. A data processing apparatus configured to receive a down-sampled source block generated from a source frame and to receive
a down-sampled reference frame portion generated from a reference frame, said reference frame and said source frame being
taken from a sequence of video frames, said data processing apparatus comprising:
interpolation circuitry configured to interpolate between pixels of said down-sampled reference frame portion to generate
a set of interpolated down-sampled reference frame blocks;

cost function calculation circuitry configured to calculate a cost function value indicative of a difference between said
down-sampled source block and each of said set of interpolated down-sampled reference frame blocks;

minimisation circuitry configured to select an interpolated down-sampled reference frame block which corresponds to a minimum
of said cost function value; and

estimate motion vector generation circuitry configured to generate an estimate motion vector in dependence on said interpolated
down-sampled reference frame block selected by said minimisation circuitry,

wherein said cost function calculation circuitry and said minimisation circuitry are configured to iteratively select said
set of interpolated down-sampled reference frame blocks to find a local minimum of said cost function value.

US Pat. No. 9,058,179

RETIREMENT SERIALISATION OF STATUS REGISTER ACCESS OPERATIONS

ARM Limited, Cambridge (...

1. Apparatus for executing a stream of program instructions, said apparatus comprising:
a plurality of processing pipelines including a special register pipeline configured to respond to a status access instruction
to perform a status register access operation to a status register configured to store at least one state variable;

dispatch queue circuitry configured to store a dispatch queue of undispatched program instructions awaiting dispatch to one
of said plurality of pipelines and to dispatch said status access instruction to said special register pipeline;

commit queue circuitry configured to store a commit queue of uncommitted program instructions awaiting a determination to
be permitted to complete processing;

result queue circuitry configured to store a result queue of unretired program instructions yet to update architectural state
variables; and

access timing control circuitry coupled to said special register pipeline, said commit queue circuitry and said result queue
circuitry, said access timing control circuitry being configured such that, when said status access instruction is issued
to said special register pipeline and while program instructions continue to be dispatched from said dispatch queue, said
access timing control circuitry:

(i) controls said commit queue circuitry such that no program instruction succeeding in program order said status access instruction
within said stream of program instructions is permitted to complete processing;

(ii) detects from said result queue circuitry a trigger state when all program instructions preceding in program order said
status access instruction within said stream of program instructions have performed any updates to architectural state variables
of said apparatus; and

(iii) upon detection of said trigger state, triggers said special register pipeline to perform said status register access
operation, comprising special register issue queue circuitry, each entry within said special register issue queue circuitry
including an issue policy field for storing an issue policy value specifying one of a plurality of issue politics to be applied
to issuing of a program instruction corresponding to said entry to said special register pipeline.

US Pat. No. 9,471,493

INVALIDATION OF INDEX ITEMS FOR A TEMPORARY DATA STORE

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
a temporary data store configured to store data items retrieved from a memory, wherein the temporary data store has plural
data storage locations configured to store the data items and the temporary data store is configured to select a storage location
of the plural data storage locations in which to store a newly retrieved data item according to a predetermined circular sequence
of the plural data storage locations;

an index data store configured to store index items corresponding to the data items stored in the temporary data store, wherein
presence of a valid index item in the index data store is indicative of a corresponding data item in the temporary data store;
and

invalidation control circuitry configured to perform a rolling invalidation process with respect to the index items stored
in the index data store, wherein the rolling invalidation process comprises sequentially processing the index items stored
in the index data store and selectively marking the index items as invalid according to a predetermined criterion,

wherein the invalidation control circuitry is configured, when performing the rolling invalidation process, such that the
predetermined criterion is fulfilled if a duration for which a selected index item has been stored in the index data store
exceeds a predetermined period, and

wherein the invalidation control circuitry is configured to determine the duration for which the selected index item has been
stored in the index data store with reference to a count of a number of index items which have been stored in the index data
store since the selected index item was stored in the index data store.

US Pat. No. 9,454,844

EARLY DEPTH TESTING IN GRAPHICS PROCESSING

ARM Limited, Cambridge (...

1. An apparatus for processing graphics primitives for display, comprising, in sequence: rasterization circuitry, depth testing
circuitry and rendering circuitry,
the rasterization circuitry configured to perform rasterization operations on the graphics primitives to generate graphics
fragments;

the depth testing circuitry configured to perform depth testing with respect to a selected graphics fragment of the graphics
fragments to determine if the selected graphics fragment would be obscured by at least one other graphics fragment when displayed
by comparing a depth comparison function and a depth value associated with the selected graphics fragment with a stored depth
value associated with a display location for the selected graphics fragment; and

the rendering circuitry configured to receive the graphics fragments and to perform rendering operations on the graphics fragments,
wherein the depth testing circuitry is configured to suppress the rendering operations with respect to the selected graphics
fragment if the depth testing indicates that the selected graphics fragment would be obscured,

wherein the rendering operations performed by the rendering circuitry cause updating of stored depth values associated with
display locations for at least some graphics fragments,

wherein the depth testing circuitry is configured to store an update indication in dependence on a received depth comparison
function, wherein the update indication shows a possible change direction due to the updating for a stored depth value which
depends on that received depth comparison function, and

wherein the depth testing circuitry is configured to perform the depth testing with respect to the selected graphics fragment
using the possible change direction shown by the update indication to modify the depth comparison function to allow for the
updating of the stored depth value by the rendering operations.

US Pat. No. 9,059,726

APPARATUS AND METHOD FOR PERFORMING A CONVERT-TO-INTEGER OPERATION

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
processing circuitry configured to perform a convert-to-integer operation for converting a floating-point value to a rounded
two's complement integer value, said floating-point value having a significand and an exponent;

wherein said convert-to-integer operation uses round-to-nearest, ties away from zero, rounding in which a fractional floating-point
value lying between two adjacent integer values is rounded to the nearest adjacent integer value, with a fractional floating-point
value lying halfway between two adjacent integer values being rounded to the one of the two adjacent integer values lying
furthest away from zero;

said processing circuitry comprises intermediate value generating circuitry configured to generate an intermediate value based
on said floating-point value, and adding circuitry configured to add a rounding value to the intermediate value to generate
a sum value;

said processing circuitry is configured to output the integer-valued bits of the sum value as the rounded two's complement
integer value; and

if said floating-point value has a negative value, then said intermediate value generating circuitry is configured to generate
said intermediate value by inverting the bits of the significand of said floating-point value without adding a bit value of
1 to a least significant bit of the inverted value, wherein the rounding value has the same value irrespective of whether
the floating-point value has a positive value or a negative value.

US Pat. No. 9,477,479

INSTRUCTION PREFETCH THROTTLING USING INSTRUCTION COUNT AND BRANCH PREDICTION

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
fetch circuitry configured to retrieve instructions from an instruction cache into a temporary buffer;
execution circuitry configured to execute a sequence of said instructions retrieved from the temporary buffer, said sequence
of instructions including branch instructions;

branch prediction circuitry coupled between the fetch circuitry and the execution circuitry and configured to predict, for
each identified branch instruction in said sequence, if that branch instruction will result in a taken branch when that branch
instruction is subsequently executed by the execution circuitry;

the operation of the fetch circuitry and the branch prediction circuitry being such that in a normal operating mode the fetch
circuitry is configured to retrieve one or more speculative instructions from the instruction cache between a source branch
instruction being retrieved from the instruction cache and the branch prediction circuitry predicting if said source branch
instruction will result in said taken branch, when said taken branch is predicted for said source branch instruction, said
one or more speculative instructions being discarded;

throttle prediction circuitry configured to maintain, when said taken branch is predicted for said source branch instruction,
a count value indicative of a number of instructions appearing in said sequence between said source branch instruction and
a subsequent branch instruction in said sequence that the branch prediction circuitry also predicts will result in said taken
branch; and

the throttle prediction circuitry being configured, responsive to a subsequent occurrence of said source branch instruction
in said sequence that the branch prediction circuitry predicts will result in said taken branch, to operate said fetch circuitry
in a throttled mode where the number of instructions subsequently retrieved by the fetch circuitry from the instruction cache
is limited dependent on said count value, and then said fetch circuitry is prevented from retrieving any further instructions
from the instruction cache for a predetermined number of clock cycles.

US Pat. No. 9,330,035

METHOD AND APPARATUS FOR INTERRUPT HANDLING

ARM Limited, Cambridge (...

18. A device for routing an incoming interrupt to processing circuitry, said processing circuitry being configured to execute
software at a plurality of execution levels, said device comprising:
processor mode detection circuitry configured to detect a current execution mode of said processing circuitry; and
input circuitry configured to receive said incoming interrupt intended for an interrupt handler configured to run at an intended
execution mode and at an intended execution level;

routing circuitry configured to route said incoming interrupt to interrupt handling software configured to run at a target
execution level, said routing circuitry being configured to:

respond to said received incoming interrupt having an intended execution mode that corresponds with said current execution
mode of said processing circuitry to route said incoming interrupt to interrupt handling software configured to run at said
intended execution level; and

respond to said received incoming interrupt having an intended execution mode that does not correspond with said current execution
mode of said processing circuitry, to route said incoming interrupt to interrupt handling software configured to run at a
predetermined execution level that is more privileged than said intended execution level.

US Pat. No. 9,218,793

INTERMEDIATE VALUE STORAGE WITHIN A GRAPHICS PROCESSING APPARATUS

ARM Limited, Cambridge (...

1. Apparatus for generating graphics values forming a frame of graphics data from a plurality of graphics primitives, said
apparatus comprising:
dividing circuitry configured to divide said frame into a plurality of tiles, each of said plurality of tiles comprising an
array of adjacent pixel locations;

binning circuitry configured to identify as overlapping graphics primitives for a given tile of said plurality of tiles those
graphics primitives upon which output values depend for pixel locations to be generated for said given tile; and

tile processing circuitry configured to execute for some or all overlapping graphics primitive for said given tile a sequence
of programmable instructions for some or every pixel location overlapped by a given graphics primitive, said tile processing
circuitry including a tile buffer to store output values and a per-pixel general purpose data store to store intermediate
values separate from said output values; wherein

said tile processing circuitry is configured to execute said programmable instructions at pixel locations overlapped by primitives
to perform write accesses and read accesses to said per-pixel general purpose data store for storing said intermediate values
during rendering said given tile to generate said output values.

US Pat. No. 9,116,711

EXCEPTION HANDLING IN A DATA PROCESSING APPARATUS HAVING A SECURE DOMAIN AND A LESS SECURE DOMAIN

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
processing circuitry for performing data processing operations in response to program code, the processing circuitry comprising
exception control circuitry for controlling exception processing;

a plurality of registers for storing data, the registers including a first subset of registers and a second subset of registers;
and

a data store for storing data, the data store comprising a plurality of regions including a secure region and a less secure
region, wherein the secure region is for storing data which is accessible by the processing circuitry when operating in a
secure domain and not accessible by the processing circuitry when operating in a less secure domain; wherein:

in response to an initial exception from background processing performed by the processing circuitry, the exception control
circuitry is configured to perform state saving of data from the first subset of registers before triggering the processing
circuitry to perform an exception handling routine corresponding to the exception, wherein the exception handling routine
has responsibility for performing state saving of data from the second subset of registers;

in response to a first exception causing a transition from the secure domain to the less secure domain, where the background
processing was performed by the processing circuitry in the secure domain, the exception control circuitry is configured to
perform additional state saving of the data from the second subset of registers before triggering the processing circuitry
to perform the exception handling routine in the less secure domain; and
in response to a tail-chained exception causing a transition from the secure domain to the less secure domain, the exception
control circuitry is configured to trigger the processing circuitry to perform the exception handling routine without performing
the additional state saving, the tail-chained exception being processed after said first exception has been processed and
before returning to the background processing,
wherein on entry to a new exception causing a transition from the secure domain to the less secure domain, the exception control
circuity is configured to determine, in dependence on a state saving status value ,whether to perform the additional state
saving before triggering the exception handling routine, and

wherein the state saving status value indicates whether at least one exception has been processed in the less secure domain
between halting the background processing and entering the new exception.

US Pat. No. 9,817,661

FLOATING POINT NUMBER ROUNDING

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
processing circuitry to perform processing operations under control of program instructions; and
decoding circuitry to decode program instructions to generate control signals to control said processing circuitry to perform
said processing operations; wherein

said decoding circuitry is responsive to a given program instruction and a rounding position input operand to generate control
signals to: control said processing circuitry to process a floating point input operand having a significand value, and to
control said processing circuitry to generate an output result dependent upon a value from rounding said floating point input
operand using a variable rounding point within said significand of said floating point input operand specified by said rounding
position input operand.

US Pat. No. 9,417,877

SWITCHING BETWEEN DEDICATED FUNCTION HARDWARE AND USE OF A SOFTWARE ROUTINE TO GENERATE RESULT DATA

ARM Limited, Cambridge (...

1. A method of processing data comprising the steps of:
performing data processing operations using processing circuitry;
decoding a stream of program instructions to generate control signals to control said processing circuitry to perform said
data processing operations; and

receiving output data from said processing circuitry and for performing a dedicated processing operation upon said output
data to generate hardware generated result data using dedicated function hardware; wherein

said decoding step is responsive to an end instruction and a software processing flag to generate control signals to control
said processing circuitry to end a current software routine, to generate said output data and:

(i) if said software processing flag has a first value, then to trigger said dedicated function hardware to receive said output
data from said processing circuitry and to perform said dedicated processing operation to generate said hardware generated
result data; or

(ii) if said software processing flag has a second value, then to trigger said processing circuitry to perform a further software
routine upon said output data to generate software generated result data instead of said hardware generated result data.

US Pat. No. 9,411,362

STORAGE CIRCUITRY AND METHOD FOR PROPAGATING DATA VALUES ACROSS A CLOCK BOUNDARY

ARM Limited, Cambridge (...

1. Storage circuitry for propagating data values across a clock boundary between a first clock domain and a second clock domain,
comprising:
a storage structure having at least one entry;
write circuitry configured to perform write operations in the first clock domain, each write operation writing a data value
into an entry of the storage structure identified by a write pointer, and the write circuitry being configured to alter the
write pointer between each write operation;

write pointer synchronisation circuitry configured to receive a write pointer indication and to synchronise the write pointer
indication to the second clock domain over a predetermined number of clock cycles of the second clock domain;

read circuitry configured to perform read operations in the second clock domain, each read operation reading a data value
from an entry of the storage structure identified by a read pointer, under a condition that the synchronised write pointer
indication indicates that there is a data value written into the storage structure that is available to be read; and

early update circuitry configured, for a write operation, to alter the write pointer indication provided to the write pointer
synchronisation circuitry a number of clock cycles of the first clock domain before the write operation is performed, where
said number of clock cycles is chosen dependent on a difference in clock speed between the first clock domain and the second
clock domain and the predetermined number of clock cycles of the second clock domain over which the write pointer indication
is synchronised to the second clock domain.

US Pat. No. 9,378,162

HANDLING AND ROUTING INTERRUPTS TO VIRTUAL PROCESSORS

ARM Limited, Cambridge (...

1. An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus,
said data processing apparatus comprising at least one physical processing unit, said at least one physical processing unit
being configured to run at least one of a plurality of virtual processors, and a memory configured to store a plurality of
virtual pending tables, each virtual pending table for storing pending virtual interrupts for a corresponding one of said
plurality of virtual processors, said interrupt controller comprising:
redistribution circuitry comprising at least one data store corresponding to said at least one physical processing unit, said
at least one data store being configured to store, for each virtual processor currently running on said corresponding physical
processing unit, a pointer to a virtual pending table configured to store currently pending virtual interrupts for said virtual
processor, and to store a pointer to a pending table configured to store currently pending physical interrupts for said corresponding
physical processing unit;

an input configured to receive a virtual interrupt for interrupting a virtual processor;
control circuitry configured to:
respond to receipt of said virtual interrupt to access said at least one data store in said redistribution circuitry corresponding
to said at least one physical processing unit with which said virtual processor is currently associated, and

to determine from said data store whether said virtual processor of said virtual interrupt is currently running on said physical
processing unit; and

if it is, to add said virtual interrupt to said virtual pending table pointed to by said redistribution circuitry; and
if it is not, to store said virtual interrupt in said virtual pending table for said virtual processor that is stored in said
memory;

wherein said control circuitry is configured in response to determining from said data store that said virtual processor is
not currently running on said physical processing unit to generate a physical interrupt and store said physical interrupt
in said pending table pointed to by said accessed data store in said redistribution circuitry, said physical interrupt indicating
that there is a pending interrupt for a virtual processor not currently running.

US Pat. No. 9,323,536

IDENTIFICATION OF MISSING CALL AND RETURN INSTRUCTIONS FOR MANAGEMENT OF A RETURN ADDRESS STACK

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
a fetch unit configured to retrieve program instructions from memory, wherein said program instructions comprise call instructions
and return instructions; and

an execution unit configured to carry out data processing operations by executing said program instructions,
wherein said fetch unit comprises:
a branch prediction unit configured to generate a return address prediction for an identified return instruction in said program
instructions with reference to a return address stack, wherein said branch prediction unit is configured to perform a return
address push onto said return address stack when said execution unit executes a call instruction and is configured to perform
a return address pop from said return address stack when said execution unit executes a return instruction; and

an error detection unit configured to identify a missing call instruction in said program instructions, and configured to
identify a missing return instruction in said program instructions, by reference to:

said return address prediction;
a resolved return address indicated by said execution unit when said execution unit executes said return instruction; and
content of said return address stack.

US Pat. No. 9,218,302

PAGE TABLE MANAGEMENT

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
processing circuitry configured to manage page table data, said page table data specifying access management parameters associated
with pages of memory within a memory address space; wherein

for each page of memory, said access management parameters include:
a write permission flag indicating whether or not write access is permitted to said page; and
a dirty-bit-modifier flag indicating whether or not, if said write permission flag indicates write access is not permitted
to said page, then action of said write permission flag is permitted to be overridden to permit a write access to said page
and changing of said write permission flag to indicate write access is permitted to said page.

US Pat. No. 9,213,650

MEMORY MANAGEMENT UNIT

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
a memory management unit configured to receive one or more memory access requests and to translate a virtual address included
in a memory access request from a requesting master device into a physical address indicating a storage location in memory,
said memory management unit having an internal storage unit having a plurality of entries wherein indications of corresponding
virtual address portions and physical address portions are stored, said memory management unit being configured to select
a selected entry of said internal storage unit in dependence on said virtual address,

said memory management unit further comprising an index generation unit configured to generate an index into said internal
storage unit to select said selected entry in dependence on said virtual address and an identifier of said requesting master
device,

wherein said index generation unit is configured to generate said index into said internal storage unit using a hash function
and to generate the same index for a plurality of different inputs, and

wherein said index generation unit is configured to generate said index such that said hash function uses a different number
of bits of said virtual address depending on said requesting master device.

US Pat. No. 9,177,415

METHODS OF AND APPARATUS FOR ENCODING AND DECODING DATA

ARM LIMITED, Cambridge (...

1. A method of encoding an array of texture data elements to be used in a graphics processing system, the method comprising:
encoding the array of texture data elements as a plurality of encoded texture data blocks, each encoded texture data block
representing a sub-set of the texture data elements of the array of texture data elements to be encoded and containing data
to allow decoded data values for the sub-set of the texture data elements that the block represents to be determined; and
wherein:

at least two of the encoded texture data blocks represent respective non-rectangular sub-sets of texture data elements from
the array of texture data elements to be encoded, the non-rectangular sub-sets of texture data elements are in the form of
rectangles, the edges of which have been modified so that they are not straight lines and so that they interlock with the
edges of adjacent non-rectangular sub-sets of texture data elements in the array of texture data elements.

US Pat. No. 9,164,910

MANAGING THE STORAGE OF DATA IN COHERENT DATA STORES

ARM Limited, Cambridge (...

13. A method of handling a write request in a data processing apparatus, said data processing apparatus comprising at least
one processor, at least one dedicated data store for storing only data processed by said at least one processor, said data
being stored in said at least one dedicated data store in conjunction with an indicator indicating if said stored data is
consistent with data stored in a corresponding address in a further data store, a shared data store for storing data processed
by said at least one processor and at least one further device, said method comprising the steps of:
receiving a write request from said further device;
determining that data related to an address targeted by said write request is stored in said at least one dedicated data store
and then, in response to said write request from said at least one further device, forcing an eviction of said data stored
in said at least one dedicated data store and writing said evicted data into said shared data store prior to performing said
write request from said at least one further device to said shared data store regardless of whether said data stored in said
at least one dedicated data store is indicated as being consistent or inconsistent.

US Pat. No. 9,141,338

STORAGE CIRCUIT WITH RANDOM NUMBER GENERATION MODE

ARM Limited, Cambridge (...

1. A storage circuit having a normal mode for receiving and storing an external bit value and a random number generation mode,
said storage circuit comprising:
a bit value storage circuit having an input node for receiving an input bit value from outside said bit value storage circuit
and an output node for outputting an output bit value;

wherein said bit value storage circuit is configured such that:
(i) when said storage circuit is operating in said normal mode, said bit value storage circuit generates at said output node
as said output bit value a stable output bit value corresponding to said external bit value; and

(ii) when said storage circuit is operating in said random number generation mode, said bit value storage circuit generates
at said output node an oscillating output bit value and a change from said random number generation mode to said normal mode
leaves said output bit value as a stable pseudo random bit value.

US Pat. No. 9,116,844

DATA PROCESSING APPARATUS AND METHOD FOR ANALYSING TRANSIENT FAULTS OCCURRING WITHIN STORAGE ELEMENTS OF THE DATA PROCESSING APPARATUS

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
a plurality of storage elements, wherein at least some of said storage elements reside at different physical locations within
the data processing apparatus;

fault history circuitry configured to detect local transient faults occurring in each storage element, and to maintain global
transient fault history data based on the detected local transient faults, wherein the global transient fault history data
indicates both spatial and temporal transient fault behaviour within the data processing apparatus,

wherein the fault history circuitry comprises local fault detection circuitry associated with each storage element of said
plurality of storage elements and fault history maintenance circuitry configured to maintain said global transient fault history
data based on local transient fault data received from each local fault detection circuitry.

US Pat. No. 9,087,017

CONTROLLING LATENCY AND POWER CONSUMPTION IN A MEMORY

ARM Limited, Cambridge (...

1. Memory circuitry for storing data comprising:
a memory for storing said data; and
control circuitry configured to control power consumption of said memory by controlling a rate of access to said memory such
that an average access delay between adjacent accesses is maintained at or above a predetermined value; wherein

said control circuitry is configured to determine a priority of an access request to said memory and to maintain said average
access delay at or above said predetermined value by delaying at least some accesses from access requests having a lower priority
for longer than at least some accesses from access requests having a higher priority.

US Pat. No. 9,070,200

GRAPHICS PROCESSING SYSTEMS

ARM LIMITED, Cambridge (...

1. A tile-based graphics processing system comprising:
a graphics processing pipeline comprising:
a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments
to be processed, each graphics fragment having one or more sampling points associated with it, and a renderer that processes
fragments generated by the rasteriser to generate rendered fragment data;

a tile buffer configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being
written out to an external memory, the tile buffer comprising an allocated amount of memory for use as the tile buffer;

write out stage circuitry configured to write data stored in the tile buffer to an external memory; andwherein the graphics processing system further comprises:
a memory allocator configured to determine the tile data storage requirements for each render target to be generated for a
render output to be generated by the graphics processing system and operable to allocate portions of the memory allocated
for use as the tile buffer to respective ones of the render targets based on the determination;

wherein each render target to be stored in the tile buffer has state information associated with it that indicates the tile
buffer region that data for the render target in question should be written to; and

wherein the state information for each render target also indicates one or more of: the format that the data for the render
target is to be stored in whether write out of the render target to external memory is enabled; where the render target data
should be written to in external memory; and how the data should be written out to external memory.

US Pat. No. 9,483,243

INTERLEAVING DATA ACCESSES ISSUED IN RESPONSE TO VECTOR ACCESS INSTRUCTIONS

ARM Limited, Cambridge (...

1. A method of compiling a computer program, comprising:
analysing said computer program and identifying loops within said computer program and converting scalar instructions within
said loops to vector instructions, said vector instructions comprising vector data access instructions, each of said vector
data access instructions specifying a plurality of elements, each of said elements indicating a data access to be performed;

identifying a first vector data access instruction and a second vector data access instruction within said computer program
where interleaving of data accesses from said first and second vector data access instructions, subject to a limited interleaving
constraint, would not cause a data error;

inserting a start limited interleaving instruction into said computer program prior to said first vector data access instruction,
said start limited interleaving instruction providing an indication to a vector data access unit that data accesses from said
first and second vector data access instructions can be interleaved subject to said limited interleaving constraint;

said limited interleaving constraint being that a next data access indicated by an element from said second vector data access
instruction is issued when a numerical position of said element within said plurality of elements of said second vector data
access instruction subtracted from a numerical position of an element indicating a next data access of said first vector data
access instruction is less than a predetermined value, and when it is not less than said predetermined value, a data access
from said first vector data access instruction is issued; and

transforming said computer program into code suitable for execution on a data processing system.

US Pat. No. 9,372,798

DATA PROCESSING APPARATUS HAVING FIRST AND SECOND PROTOCOL DOMAINS, AND METHOD FOR THE DATA PROCESSING APPARATUS

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
a first protocol domain and a second protocol domain each comprising at least one device configured to issue write requests
for requesting that a local version of data associated with a write target address is written to another location and to receive
snoop requests for requesting access to a local version of data associated with a snoop target address; and

a bridge configured to transfer said write requests and said snoop requests between said first protocol domain and said second
protocol domain;

wherein said first protocol domain is configured to operate under a write progress protocol in which, if said write target
address for a pending write request is the same as said snoop target address for a pending snoop request, said pending snoop
request is blocked until said pending write request has been serviced;

said second protocol domain is configured to operate under a snoop progress protocol in which, if said write target address
for a pending write request is the same as said snoop target address for a pending snoop request, said pending write request
is blocked until said pending snoop request has been serviced;

said bridge is configured to detect a deadlock condition in which said write target address for a pending write request issued
from said first protocol domain to said second protocol domain is the same as said snoop target address for a pending snoop
request issued from said second protocol domain to said first protocol domain; and

said bridge is configured to issue, on detecting said deadlock condition, an early response to a selected request without
waiting for said selected request to be serviced, said selected request comprising said pending write request or said pending
snoop request, said early response indicating to the issuing protocol domain that issued said selected request that said selected
request has been serviced.

US Pat. No. 9,348,688

CORRELATING TRACE DATA STREAMS

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
processing circuitry configured to perform processing operations in response to a stream of program instructions; and
tracing circuitry coupled to said processing circuitry and configured to generate trace data indicative of said processing
operations performed by said processing circuitry;

wherein said trace data comprises a plurality of separate trace streams including at least one first trace stream and at least
one second trace stream and said trace circuitry is configured to insert a synchronisation marker in one of said at least
one second trace stream to mark a synchronisation point which matches a known point in one of said at least one first trace
stream;

wherein, in addition to insertion of said synchronisation marker, said trace circuitry is configured to mark individual elements
within said plurality of separate trace streams with respective key values.

US Pat. No. 9,288,258

COMMUNICATION USING INTEGRATED CIRCUIT INTERCONNECT CIRCUITRY

ARM Limited, Cambridge (...

1. An integrated circuit comprising:
a plurality of master units configured to generate communication transactions;
interconnect circuitry coupled to said plurality of master units and configured to carry said communication transactions;
and

one or more slave units coupled to said interconnect circuitry and configured to respond to said communication transactions;
wherein

said interconnect circuitry is configured to provide a plurality of virtual networks, each virtual network connecting at least
one of said plurality of master units to at least one of said one or more slave units and including a plurality of network
nodes, at least two of said plurality of virtual networks being overlapping virtual networks having an overlapped portion
that shares a physical communication link between at least two of said plurality of network nodes; and

at least network nodes within said overlapped portion perform node-to-node token based communication flow management whereby:
(i) before asserting communication signals corresponding to a communication transaction with a target slave unit via one of
said overlapping virtual networks, at least network nodes within said overlapped portion are configured to assert a token
request upon said overlapping virtual network to request a token signal for said overlapping virtual network from a next network
node downstream within said overlapping virtual network toward said target slave unit and not to assert said communication
signals upon said physical communication link shared with another overlapping virtual network until said token signal is received;
and

(ii) said next network node receiving said token request blocks return of said token signal until said next network node is
ready to receive said communication signals.

US Pat. No. 9,176,737

CONTROLLING THE EXECUTION OF ADJACENT INSTRUCTIONS THAT ARE DEPENDENT UPON A SAME DATA CONDITION

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
an instruction decoder configured to decode a stream of instructions;
a data processor configured to process said decoded stream of instructions; wherein
said data processor is configured to analyse said stream of instructions and to identify a plurality of adjacent instructions
within said stream of instructions execution of which is dependent upon a data condition being met and whose execution when
said data condition is not met does not change a value stored in any data register, and in response to identifying said plurality
of adjacent instructions said data processor is configured to:

commence determining whether said data condition is met or not; and
commence processing said plurality of adjacent instructions without waiting for a determination of whether said data condition
is met or not; and

in response to determining that said data condition is not met, skip to a next instruction to be executed after said plurality
of adjacent instructions without executing any intermediate ones of said plurality of adjacent instructions not yet executed
and without restoring state to data registers, and continue execution at said next instruction.

US Pat. No. 9,153,070

HIDDEN SURFACE REMOVAL IN GRAPHICS PROCESSING SYSTEMS

ARM LIMITED, Cambridge (...

1. A method of operating a graphics processing pipeline that includes a plurality of processing stages including a rasteriser
that rasterises input primitives to generate graphic fragments to be processed, each graphics fragment having one or more
sampling points associated with it, and a renderer that processes fragments generated by the rasteriser to generate output
fragment data, the method comprising:
performing an early culling test in respect of at least one sampling point associated with a fragment generated by the rasteriser
before the fragment is sent to the renderer for processing; and

if the at least one sampling point passes the early culling test, sending the fragment onwards for processing, broadcasting
information related to a position of the at least one sampling point or the fragment that passed the test to at least one
processing stage of the graphics processing pipeline and determining if the processing of another sampling point that is in
the graphics processing pipeline can be stopped as a consequence of the at least one sampling point passing the early culling
test using the broadcast position information to assess whether any of the sampling points or fragments that it is currently
processing can have their processing stopped.

US Pat. No. 9,047,184

PROCESSING ERROR DETECTION WITHIN PIPELINE CIRCUITRY

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
processing pipeline circuitry having a plurality of pipeline stages with respective signal value storage circuits interposed
therebetween, said signal value storage circuits configured to be transparent to received signal values during a transparent
phase of a clock signal controlling said signal value storage circuits;

timing detection circuitry coupled to said processing pipeline circuitry and configured to detect as timing violations if
signal transitions arrive at said signal value storage circuits outside respective nominal timing windows; and

error detection circuitry coupled to said timing detection circuitry and configured to trigger an error correcting response
if said timing detection circuitry indicates a predetermined pattern comprising a plurality of timing violations spread over
a plurality of cycles of said clock signal.

US Pat. No. 9,495,163

ADDRESS GENERATION IN A DATA PROCESSING APPARATUS

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
processing circuitry for processing data;
an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry
to perform said data processing;

wherein said program instructions comprise an address calculating instruction having an instruction size, said processing
circuitry being responsive to said address calculating instruction to perform an address calculating operation for calculating
a partial address result by adding a non-fixed reference address and a partial offset value, said partial address result specifying
a portion of a full address specifying a memory location of an information entity, wherein said partial offset value has a
bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address
calculating instruction.

US Pat. No. 9,483,232

DATA PROCESSING APPARATUS AND METHOD FOR MULTIPLYING FLOATING POINT OPERANDS

ARM Limited, Cambridge (...

1. A data processing apparatus for multiplying first and second normalized floating point operands to generate a result, each
normalized floating point operand comprising a significand and an exponent, the data processing apparatus comprising:
exponent determination circuitry configured to compute a result exponent for a normalized version of the result;
rounding value generation circuitry configured to generate a rounding value by shifting a rounding constant in a first direction
by a shift amount that is dependent on the result exponent;

partial product generation circuitry configured to multiply the significands of the first and second normalized floating point
operands to generate first and second partial products;

adder circuitry configured to add the first and second partial products and the rounding value to generate a normalized result
significand; and

shifting circuitry configured to shift the normalized result significand in a second direction opposite to said first direction,
by said shift amount in order to generate a rounded result significand.

US Pat. No. 9,054,698

METHOD FOR SETTING TRANSISTOR OPERATING POINT AND CIRCUIT THEREFOR, METHOD FOR CHANGING SIGNAL COMPONENT VALUE AND ACTIVE-MATRIX LIQUID CRYSTAL DISPLAY DEVICE

Gold Charm Limited, Apia...

1. A method for setting the operating point of a unipolar first transistor, wherein the unipolar first transistor having a
multi-gate structure is equivalently achieved by commonly connecting respective gates of plural unipolar second transistors
each having a single gate structure and connecting the plural unipolar second transistors to one another in series, an operating
point of each single unipolar second transistor having the single gate structure is set at an operating point that the dependence
of source-drain current on source-drain voltage is within a permissible range.

US Pat. No. 9,479,147

SYNCHRONISER FLIP-FLOP

ARM Limited, Cambridge (...

1. A synchroniser flip-flop comprising:
a latch comprising:
inverter circuitry to produce a first signal and a second signal in dependence on a value of an input signal at a node; and
a clocked inverter comprising:
a first switch connected between a first reference voltage supply and an intermediate node; and
a second switch connected between the intermediate node and a second reference voltage supply, wherein the first switch is
controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the
intermediate node; and

a further latch connected in series with the latch, the further latch comprising:
further inverter circuitry to produce a further first signal and a further second signal in dependence on a value of a further
input signal at a further node; and

a further clocked inverter comprising:
a further first switch connected between the first reference voltage supply and a further intermediate node; and
a further second switch connected between the further intermediate node and the second reference voltage supply, wherein the
further first switch is controlled by the further first signal and the further second switch is controlled by the further
second signal to produce a further output signal at the further intermediate node, and wherein the further input signal at
the further node is dependent on the further output signal at the further intermediate node.

US Pat. No. 9,472,008

GRAPHICS TILE COMPOSITING CONTROL

ARM Limited, Cambridge (...

24. A method of processing graphics data to generate a plurality of output graphics tiles that together form an output graphics
frame, said method comprising the steps of:
compositing one or more input graphics tiles for a common tile area to form an output graphics tile for said common tile area;
wherein each one of said one or more input graphics tiles has associated tile flag data; and
reading said tile flag data for said one or more input graphics tiles for said common tile area; and
controlling handling of said one or more input graphics tiles in dependence upon tile flag data; and wherein
said associated tile flag data is indicative of one or more of:
(i) said input graphics tile makes less than a first threshold level of contribution to said output graphics tile; and
(ii) said input graphics tile makes more than a second threshold level of contribution to said output graphics tile.

US Pat. No. 9,262,123

DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A NARROWING-AND-ROUNDING ARITHMETIC OPERATION

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
processing circuitry configured to process data; and
control circuitry configured to control said processing circuitry to perform a narrowing-and-rounding arithmetic operation
in response to a narrowing-and-rounding arithmetic instruction identifying two operands each comprising at least one W-bit
data element, said narrowing-and-rounding arithmetic operation generating a result value comprising at least one X-bit result
data element, each X-bit result data element representing a sum or difference of corresponding W-bit data elements of said
two operands rounded to an X-bit value, where W and X are integers and W>X;

wherein said control circuitry is configured to control said processing circuitry to generate each X-bit result data element
of said result value by:

(a) performing a plurality of N-bit first stage additions to generate respective N-bit intermediate values by adding or subtracting
N-bit portions of said corresponding W-bit data elements, where W=J*N and J>1 and N and J are integers;

(b) performing one or more N-bit second stage additions, each second stage addition for converting the N-bit intermediate
value generated by a corresponding first stage addition into an N-bit rounded result portion of said X-bit result data element
by adding a rounding value and a carry value representing a carry output of a preceding first stage addition for adding less
significant N-bit portions of said corresponding W-bit data elements than said corresponding first stage addition; and

(c) forming said X-bit result data element from the N-bit result portion generated by at least one of said one or more N-bit
second stage additions.

US Pat. No. 9,226,127

METHOD FOR PROVISIONING OF A NETWORK ACCESS FOR A MOBILE COMMUNICATION DEVICE USING THE MOBILE COMMUNICATION DEVICE

ARM LIMITED, Cambridge (...

1. A method for provisioning network access for a mobile communication device having at least one communication interface,
comprising:
providing a mobile communication device comprising a secure environment having a secure operating system and an unsecure environment
having an unsecure operating system, wherein said secure environment comprises a secure payment application;

requesting communication network access from a network operator with the mobile communication device for the mobile communication
device;

processing a payment to the network operator for the requested communication network access by the mobile communication device
using the secure payment application executed in the secure environment by the secure operating system of the mobile communication
device;

downloading a communication network access application from the network operator and storing the communication network access
application in the secure environment of the mobile communication device and using the communication network access application
executed in the secure environment by the secure operating system for an authentication of the mobile communication device
to a mobile communication network,

wherein separate communication network access applications are downloaded for different communication networks so that the
mobile communication device is able to switch between the different communication networks,

wherein downloading the communication network access application comprises downloading an authentication key and/or an authentication
algorithm of the communication network to be accessed,

wherein the authentication key and/or the authentication algorithm in the secure environment of the mobile communication device
are invalidated or deleted after having reached an invalidation time and/or date, and

wherein the communication networks are cellular networks.

US Pat. No. 9,201,816

DATA PROCESSING APPARATUS AND A METHOD FOR SETTING PRIORITY LEVELS FOR TRANSACTIONS

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
a shared resource for processing transactions;
at least one master device configured to issue said transactions to said shared resource, the at least one master device providing
a plurality of sources of said transactions, and each of said transactions having a priority level associated therewith;

arbitration circuitry configured to apply an arbitration policy to select a transaction from amongst multiple transactions
issued to said shared resource, the arbitration policy using the priority level associated with each of said multiple transactions
when performing the selection; and

adaptive priority circuitry associated with at least one of said plurality of sources, the adaptive priority circuitry configured
to monitor throughput indication data for previously issued transactions from the associated source, and, for each new transaction
from the associated source, to set the priority level to one of a plurality of predetermined priority levels dependent on
said throughput indication data, so as to set the lowest priority level from amongst said plurality of predetermined priority
levels that will enable a specified target throughput to be achieved,

wherein the adaptive priority circuitry comprises:
active transaction count circuitry configured to determine from the throughput indication data an indication of the number
of transactions in progress; and

accumulator circuitry configured to maintain a priority level control value, the accumulator circuitry increasing the priority
level control value dependent on the indication of the number of transactions in progress,

wherein the adaptive priority circuitry is configured to detect from the throughput indication data when a transaction in
progress has reached a predetermined point, and responsive thereto the accumulator circuitry is arranged to decrease the priority
level control value.

US Pat. No. 9,081,685

DATA PROCESSING APPARATUS AND METHOD FOR HANDLING PERFORMANCE OF A CACHE MAINTENANCE OPERATION

ARM Limited, Cambridge (...

1. A data processing apparatus, said data processing apparatus comprising:
data processing circuitry configured to perform data processing operations on data;
a hierarchical cache structure configured to store at least a subset of said data for access by the data processing circuitry,
said hierarchical cache structure having a first level cache and a second level cache, the hierarchical cache structure being
responsive to an access request issued by the data processing circuitry and specifying an address, to access in the first
level cache the data identified by the address if that data is stored in the first level cache, and to seek to access in the
second level cache the data identified by the address if that data is not stored in the first level cache, and any data evicted
from the first level cache being routed to the second level cache;

access control circuitry associated with the second level cache and configured, in response to data evicted from the first
level cache, to perform an eviction handling operation requiring access to the second level cache;

cache maintenance circuitry configured to perform a cache maintenance operation requiring cache maintenance to be performed
in both the first level cache and the second level cache;

if the cache maintenance required in respect of the first level cache during performance of the cache maintenance operation
causes data to be evicted from the first level cache, the cache maintenance circuitry being configured to cause maintenance
indication data to be passed to the second level cache in association with the evicted data;

the access control circuitry being responsive to the maintenance indication data to modify the eviction handling operation
performed in response to the evicted data in order to cause the required cache maintenance for the second level cache to be
incorporated within the eviction handling operation.

US Pat. No. 9,047,092

RESOURCE MANAGEMENT WITHIN A LOAD STORE UNIT

ARM Limited, Cambridge (...

1. Apparatus for processing data in response program instructions having a program execution order, said apparatus comprising:
issue queue circuitry configured to store a queue of program instructions to be issued for execution; and
load store circuitry configured to perform data access operations in response to data access instructions issued from said
issue queue circuitry; wherein

said load store circuitry comprises a plurality of access slot circuits, each access slot circuit configured to perform an
access operation corresponding to a data access instruction issued from said issue queue circuitry;

said issue queue circuitry is configured to permit issue of data access instructions to said load store circuitry to be performed
by respective different ones of said plurality of access slot circuits in an order different from said program execution order
such that a bypassing data access instruction is issued to said load store circuitry before a bypassed data access instruction
is issued to said load store circuitry, said bypassed data access instruction having a position before said bypassing data
access instruction within said program execution order and said bypassing data access instruction having a potential dependency
upon said bypassed data access instruction;

said load store circuitry is configured to manage hazards due to potential dependency between a bypassing data access instruction
and a bypassed data access instruction; and further comprising

dependency tracking circuitry configured to track a freeable number of said plurality of access slot circuits including access
slot circuits that are not performing access operations for bypassing data access instructions having a potential dependency
upon one or more bypassed data access instructions and already free access slot circuits; wherein

said issue control circuitry is coupled to said dependency tracking circuitry and is configured to prevent issue of any further
bypassing data access instruction to said load store circuitry unless said freeable number is equal to or exceeds a minimum
number, wherein said freeable number is a sum of any access slot circuits not performing access operations and any access
slot circuits that are performing access operations for data access instruction that are not bypassing data access instructions.

US Pat. No. 9,507,728

BRIDGE CIRCUITRY FOR TRANSLATING BETWEEN MEMORY TRANSACTIONS OF FIRST TYPE AND MEMORY TRANSACTIONS OF A SECOND TYPE

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
bridge circuitry having a first port configured to transmit memory transactions of a first type, a second port configured
to receive memory transactions of a second type and translation circuitry configured to translate between memory transactions
of said first type and memory transactions of said second type; wherein

said memory transactions of said first type specify X significant bits of address and A bits of attribute data, where X and
A are both positive integer values;

said memory transactions of said second type specify Y significant bits of address, where Y is a positive integer value and
Y is greater than X; and

said translation circuitry is configured to map at least some of said A bits of attribute data of a memory transaction of
said first type to unused bits within said Y significant bit of address of a second type unused to represent said X significant
bits of address of said memory transaction of said first type.

US Pat. No. 9,483,664

ADDRESS DEPENDENT DATA ENCRYPTION

ARM Limited, Cambridge (...

1. A method of manufacturing a plurality of devices, comprising:
manufacturing, in each of the devices,
key generation circuitry to generate a key as a function of an address of a storage location of a memory, and
encryption circuitry to encrypt unencrypted data to form encrypted data as a function of said key;
wherein the key generation circuitry comprises physically unclonable function circuitry to receive said address as a challenge
input to said physically unclonable function circuitry, and to output said key as a response output from said physically unclonable
function circuitry, the method further comprising:

manufacturing the devices with device-to-device variation of the physically unclonable function circuitry such that the key
generation circuitry of a first device is configured to generate a different key to the key generation circuitry of a second
device even when the same input data is supplied to the key generation circuitry of the first device and the second device.

US Pat. No. 9,411,662

CONTROLLING PRIORITY LEVELS OF PENDING THREADS AWAITING PROCESSING

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
processing circuitry configured to process processing threads using resources accessible to said processing circuitry;
a pipeline for handling at least two pending threads awaiting processing by said processing circuitry, said pipeline comprising
at least one pipeline stage including at least one resource-requesting pipeline stage for requesting access to said resources
for said pending threads;

a pipeline controller configured to determine whether requested resources are available for a pending thread in a final pipeline
stage of said pipeline, to return said pending thread to a first pipeline stage of said pipeline if said requested resources
are not yet available for said pending thread, and to forward said pending thread from said pipeline if said requested resources
are available for said pending thread;

a priority controller for controlling priority levels of said pending threads, said priority levels defining a priority with
which respective pending threads are granted access to resources, pending threads being assigned a base priority level when
entering said pipeline for the first time;

wherein said priority controller is configured to selectively raise the current priority level of a pending thread in said
final pipeline stage if said pipeline controller returns said pending thread to said first pipeline stage.

US Pat. No. 9,400,655

TECHNIQUE FOR FREEING RENAMED REGISTERS

ARM Limited, Cambridge (...

1. Register renaming apparatus for a processing system having a physical set of registers to store data values being processed
and in which a stream of instructions from an instruction set is processed, said instructions specifying registers from an
architectural set of registers, said register renaming apparatus comprising:
first circuitry configured to receive a stream of operations from an instruction decoder within said processing apparatus
and to map registers that are to be written to by said stream of operations to physical registers within said physical set
of registers that are currently available and to identify additional registers that are registers that are to be written to
by said operations that are not from said architectural set of registers; and

second circuitry configured to release physical registers that have been mapped such that they are available for register
renaming and to release said physical registers that have been mapped to said registers from said set of architectural registers
when a first set of conditions have been met, and to release said physical registers that have been mapped to said additional
registers when a second set of conditions have been met, at least some of said conditions within said first set of conditions
being different to said conditions within said second set of conditions.

US Pat. No. 9,348,598

DATA PROCESSING APPARATUS AND METHOD FOR PRE-DECODING INSTRUCTIONS TO BE EXECUTED BY PROCESSING CIRCUITRY

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
processing circuitry configured to execute instructions fetched from memory in order to perform processing operations on data
values;

a hierarchical cache structure configured to store the instructions fetched from said memory for access by the processing
circuitry, the hierarchical cache structure comprising at least a unified cache configured to store both instructions and
data values and a further cache coupled between the processing circuitry and the unified cache;

the unified cache having a plurality of cache lines, each cache line being identified as an instruction cache line or a data
cache line and each cache line having an associated information portion;

each data cache line being configured to store at least one data value and the associated information portion being configured
to store error correction code (ECC) data used for error detection and correction within that data cache line's stored content;

pre-decode circuitry configured, for each instruction cache line of the unified cache, to perform a first pre-decode operation
on at least one received instruction for that instruction cache line in order to generate at least one partially pre-decoded
instruction for storing in that instruction cache line, each at least one partially pre-decoded instruction having more bits
than the corresponding received instruction and the unified cache being configured to use the instruction cache line in combination
with its associated information portion to store said at least one partially pre-decoded instruction generated by the pre-decode
circuitry; and

further pre-decode circuitry configured when the at least one partially pre-decoded instruction stored in one of said instruction
cache lines is routed to the further cache for storage within at least one cache line of the further cache, to perform a further
pre-decode operation on the at least one partially pre-decoded instruction in order to generate a corresponding at least one
pre-decoded instruction for storage in the further cache.

US Pat. No. 9,286,222

DATA PROCESSING APPARATUS AND METHOD FOR TRANSFERRING WORKLOAD BETWEEN SOURCE AND DESTINATION PROCESSING CIRCUITRY

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
first processing circuitry and second processing circuitry, where both circuitries are configured to perform a processing
workload such that the processing workload is performed by one of the first processing circuitry and the second processing
circuitry at a time;

power control circuitry for independently controlling power supply to the first processing circuitry and the second processing
circuitry;

a workload transfer controller configured to be responsive to a transfer stimulus to initiate a transfer of performance of
the processing workload from a source processing circuitry to a destination processing circuitry prior to the source processing
circuitry being placed in a power saving condition by the power control circuitry, the source processing circuitry being one
of the first and second processing circuitry and the destination processing circuitry being the other of the first and second
processing circuitry; wherein:

at least the source processing circuitry has a cache;
the power control circuitry is configured, following said transfer, to maintain at least the cache of the source processing
circuitry in a powered condition during a snooping period following the start of performance of the transferred processing
workload by the destination processing circuitry;

cache snooping circuitry is configured, during the snooping period, to snoop data values in the cache of the source processing
circuitry and to retrieve the snooped data values for the destination processing circuitry; and

the power control circuitry is configured to place said at least the cache of the source processing circuitry in the power
saving condition following the end of the snooping period, the power saving condition is a condition in which the cache of
the source processing circuitry is not accessed by the cache snooping circuitry,

wherein the snooping period ends on the occurrence of any one of a plurality of predefined snoop stop events, and
wherein the any one of the plurality of predefined snoop stop events is based on at least one of: (i) a number of snoops performed
by the cache snooping circuitry, (ii) a predetermined number of processing transactions of a predetermined type following
said transfer, (iii) a predetermined number of processing cycles after the destination processing circuitry starts performing
the transferred processing workload, (iv) a particular memory region of a shared memory is accessed for the first time by
the destination processing circuitry after starting performance of the transferred processing workload, (v) a particular memory
region of the shared memory, which was accessed by the destination processing circuitry for an initial period after starting
performance of the transferred processing workload, is not accessed by the destination processing circuitry for a predetermined
period, and (vi) the destination processing circuitry writing to a predetermined memory location of the shared memory for
the first time after starting performance of the transferred processing workload.

US Pat. No. 9,229,908

IDENTIFIER SELECTION

ARM Limited, Cambridge (...

1. A data processing apparatus configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M?N, said data processing apparatus comprising:
storage circuitry configured to store at least N+1 identifier selection bits, wherein a position of at least a first marker
bit in said at least N+1 identifier selection bits determines M; and

selection circuitry configured to determine said 2M selected identifiers,

wherein said 2M selected identifiers fall within a range defined by an associated base identifier and a ceiling identifier,

wherein N-M bits of said at least N+1 identifier selection bits form N-M bits of said associated base identifier, and M zeroes
form a further M bits of said associated base identifier,

wherein said ceiling identifier corresponds to said associated base identifier with said M zeros that form M bits of said
associated base identifier replaced with ones.

US Pat. No. 9,105,327

MEMORY CONTROLLER USING A DATA STROBE SIGNAL AND METHOD OF CALIBRATING DATA STROBE SIGNAL IN A MEMORY CONTROLLER

ARM Limited, Cambridge (...

1. A memory controller comprising:
input circuitry configured to receive a differential pair of data strobe signals from a memory, said input circuitry configured
to generate a logical data strobe signal in dependence on a voltage difference between said differential pair of data strobe
signals;

hysteresis circuitry configured, when switched to an active state, to increase by a predetermined offset a threshold voltage
difference at which said input circuitry is configured to change a logical state of said logical data strobe signal; and

gate signal generation circuitry configured to generate a data strobe gating signal, wherein said memory controller is configured
to interpret said logical data strobe signal as valid when said data strobe gating signal is asserted,

wherein said memory controller is configured to perform a training process to determine a timing offset for said data strobe
gating signal with respect to said logical data strobe signal,

wherein said training process comprises a first phase in which said hysteresis circuitry is in said active state and a second
phase in which said hysteresis circuitry is not in said active state.

US Pat. No. 9,081,581

SIZE MIS-MATCH HAZARD DETECTION

ARM Limited, Cambridge (...

1. Apparatus for executing a stream of program instructions, said apparatus comprising:
processing circuitry configured to perform within one or more processing pipelines operations as specified by said stream
of program instructions;

instruction group forming circuitry configured to divide said stream of program instructions into a plurality of groups of
program instructions, each of said plurality of groups comprising one or more program instructions committed together for
completion; and

hazard detection circuitry configured to identify one or more processing hazards preventing proper processing of a group of
program instructions by said processing circuitry; wherein

said hazard detection circuitry detects as a size mismatch hazard a consumer program instruction specifying a source operand
register with a source operand value formed from a concatenation of a plurality of destination operand values produced by
one or more producer program instructions, said one or more producer program instructions being uncompleted and preceding
said consumer program instruction in program order within said stream of program instructions; and

said processing circuitry, upon detection of a group of program instructions including one or more program instructions detected
as subject to a size mismatch hazard and at a commit point within said one or more processing pipelines beyond which said
group of program instructions is committed to complete processing, is configured to:

(i) flush from said one or more processing pipelines for re-dispatch thereto said group of program instructions and any program
instructions succeeding said group of program instructions in program order within said stream of program instructions; and

(ii) control said instruction group forming circuitry to divide said group of program instructions to form at least two groups
of program instructions, said at least two groups of program instructions are separately re-dispatched to said one or more
processing pipelines.

US Pat. No. 9,069,652

INTEGRATED LEVEL SHIFTING LATCH CIRCUIT AND METHOD OF OPERATION OF SUCH A LATCH CIRCUIT

ARM Limited, Cambridge (...

1. An integrated level shifting latch circuit for receiving an input signal in a first voltage domain and generating an output
signal in a second voltage domain, said first voltage domain operating with a first voltage supply providing a first voltage
level and a common voltage level and said second voltage domain operating with a second voltage supply providing a second
voltage level and said common voltage level, said integrated level shifting latch circuit comprising:
data retention circuitry operating in said second voltage domain and configured to operate in a transparent phase where a
data value is subjected to a level shifting function and written into the data retention circuitry dependent on the input
signal, and a latching phase where the data value written into the data retention circuitry during the transparent phase is
retained irrespective of any change in the input signal during the latching phase, and that retained data value forms said
output signal;

control circuitry configured to receive a clock signal and to control the data retention circuitry to operate in said transparent
phase during a first phase of the clock signal and to operate in said latching phase during a second phase of the clock signal;

writing circuitry configured during the transparent phase to write said data value into said data retention circuitry by controlling
a voltage of at least one internal node of the data retention circuitry dependent on the input signal; and

contention mitigation circuitry configured to receive said input signal and, during said transparent phase, to reduce a voltage
drop across at least one component within the data retention circuitry, thereby assisting said writing circuitry in altering
the voltage of said at least one internal node during the transparent phase.

US Pat. No. 9,582,419

DATA PROCESSING DEVICE AND METHOD FOR INTERLEAVED STORAGE OF DATA ELEMENTS

ARM Limited, Cambridge (...

1. A data processing device comprising:
a plurality of storage circuits configured to store a plurality of data elements of b bits in an interleaved manner; and
first instruction execution circuitry including a plurality of lanes, configured to be able to individually access each of
said plurality of storage circuits and to receive into said plurality of lanes one of the set of (a) and (b):

(a) a subset of said plurality of data elements, and
(b) y bits of each of said plurality of data elements, and
wherein the first instruction execution circuitry is further configured to execute a common instruction on each of said plurality
of lanes;

wherein b is greater than y and is an integer multiple of y;
wherein each of said plurality of storage circuits is configured to store a group of bits from each of said data elements,
the group of bits comprising at most y bits, wherein the respective groups of bits stored in the same one of said storage
circuits comprise at least one group of bits corresponding to a first subset of bit positions of a corresponding data element
and at least one group of bits corresponding to a second subset of bit positions of a different corresponding data element,
wherein the second subset of bit positions is different than the first subset of bit positions;

wherein each of said plurality of storage circuits is configured to store at most y/b of said plurality of data elements;
and

wherein said plurality of storage circuits comprise no more than b/y storage circuits.

US Pat. No. 9,465,690

CUMULATIVE ERROR DETECTION IN DATA TRANSMISSION

ARM Limited, Cambridge (...

1. Circuitry for providing error check values for indicating errors in data portions within a data stream comprising:
error detecting code generation circuitry configured to apply an error detecting code algorithm to said data stream and to
thereby generate and periodically update a multi-bit check value as said data stream is processed, each update of said multi-bit
check value being indicative of said error detecting code generation circuitry receiving a further item of said data stream;

an output for periodically outputting a fragment of said multi-bit check value from said error detecting code generation circuitry
during said processing of said data stream, said fragments output each corresponding to a data portion of said data stream;
wherein:

each of said fragments of said multi-bit check value provides a value indicative of an error occurring either in said corresponding
portion of said data stream or in an earlier portion of said data stream;

said data stream comprises a burst of data; and
said error detecting code generation circuitry is configured to output said complete multi-bit check value having processed
said burst of data.

US Pat. No. 9,349,210

METHODS OF AND APPARATUS FOR USING TEXTURES IN GRAPHICS PROCESSING SYSTEMS

ARM LIMITED, Cambridge (...

1. A method of generating texturing output data using a texture in a graphics processing system in which textures to be used
by the graphics processing system can be stored externally to the graphics processing system and pages of the textures then
loaded into a local memory of the graphics processing system for use by the graphics processing system to generate texturing
output data, the method comprising:
when the texturing operation of the graphics processing system is to use a texture that is stored externally to the graphics
processing system at a particular mipmap level to generate texturing output data, the graphics processing system:

determining if the page of the texture at the particular mipmap level and encompassing the region of the texture to be used
to generate the texturing output data is available in the local memory of the graphics processing system; and

when the required page of the texture at the particular mipmap level is not available in the local memory of the graphics
processing system, determining if a page of the texture at a less detailed mipmap level than the particular mipmap level and
that encompasses the required region of the texture to be used to generate the texturing output data is available in the local
memory of the graphics processing system, and, when a page of the texture that encompasses the required region of the texture
to be used to generate the texturing output data at a less detailed mipmap level than the particular mipmap level is available
in the local memory of the graphics processing system, using the available page of the texture that is at a less detailed
mipmap level than the particular mipmap level to generate the texturing output data the method further comprising:

storing entries in a page table corresponding to each page of the texture; and
associating metadata indicating a next lower detail mipmap level to try with texture pages that are not present in the local
memory of the graphics processing system, and storing said metadata using data fields in the page table that are used for
another purpose for pages that are present in the local memory and when a required page of a texture at a given mipmap level
is found not to be available in the local memory of the graphics processing system, using the metadata indicating the next
lower detail mipmap level to try associated with the page of the texture that is not present in the local memory to determine
the next lower detailed mipmap level for which it should be determined whether a page that encompasses the required region
of the texture to be used to generate the texturing output data is available in the local memory of the graphics processing
system.

US Pat. No. 9,311,087

STICKY BIT UPDATE WITHIN A SPECULATIVE EXECUTION PROCESSING ENVIRONMENT

ARM Limited, Cambridge (...

1. Apparatus for processing data in response to program instructions having a program execution order, said apparatus comprising:
processing circuitry configured to perform processing operation in response to said program instructions;
sticky bit storage circuitry configured to store one or more sticky bits, each sticky bit having either an initial value or
a sticky value and being subject to:

(i) a first outcome of an event that leaves said sticky bit unchanged independent of whether said sticky bit has said initial
value or said sticky value; and

(ii) a second outcome of said event that leaves said sticky bit with said sticky value independent of whether said sticky
bit has said initial value or said sticky value; and

speculative execution control circuitry configured to control speculative execution of program instructions by said processing
circuitry to follow a speculative sequence of program instructions including a plurality of segments of program instructions,
each of said plurality of segments separated from one or more adjacent segments by a respective speculation node corresponding
to a program instruction following which a plurality of alternative instructions may serve as a next program instruction to
be executed, said speculative execution control circuitry controlling said speculative sequence of program instructions to
use one of said alternative instructions as said next program instruction; wherein

said sticky bit storage circuitry is configured to store separate versions of said sticky bit, each version corresponding
to a value of said sticky bit associated one of said plurality of segments, and

said speculative execution control circuitry is configured to respond to resolution of speculation associated with a speculation
node corresponding to a condition that a correct one of said plurality of alternative program instruction was selected as
said next program instruction to merge segments separated by said speculation node to form a merged segment; and

said sticky bit storage circuitry is configured to respond to any merging of segments to merge respective versions of said
sticky bit to form a merged sticky bit such that:

(i) if both versions of said sticky bit have said initial value, then said merged sticky bit has said initial value; and
(ii) if either or both of said versions of said sticky bit have said sticky value, then said merged version has said sticky
value.

US Pat. No. 9,170,819

FORWARDING CONDITION INFORMATION FROM FIRST PROCESSING CIRCUITRY TO SECOND PROCESSING CIRCUITRY

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
first processing circuitry configured to execute program instructions and to maintain a plurality of sets of condition information
for indicating characteristics of the outcomes of the program instructions;

second processing circuitry comprising a processing pipeline having a plurality of pipeline stages, wherein the second processing
circuitry is configured to execute at least one conditional instruction having an outcome dependent on one of the plurality
of sets of condition information maintained by the first processing circuitry;

a first forwarding path configured to forward sets of condition information from the first processing circuitry to a predetermined
pipeline stage of the processing pipeline of the second processing circuitry;

a request path configured to transmit a request signal from the second processing circuitry to the first processing circuitry,
the request signal for indicating a requested set of condition information which was not yet valid when a conditional instruction
dependent on the requested set of condition information was at the predetermined pipeline stage; and

a second forwarding path, wherein in response to the requested set of condition information becoming valid, the first processing
circuitry is configured to forward the requested set of condition information via the second forwarding path to a subsequent
pipeline stage of the processing pipeline of the second processing circuitry.

US Pat. No. 9,146,901

VECTOR FLOATING POINT ARGUMENT REDUCTION

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
processing circuitry configured to perform processing operations upon data values; and
decoder circuitry coupled to said processing circuitry and configured to decode program instructions to generate control signals
for controlling said processing circuitry to perform processing operations specified by said program instructions;

wherein said decoder circuitry is responsive to an argument reduction instruction to generate control signals to control said
processing circuitry to perform a processing operation upon a vector floating point value having a plurality of components,
each of said plurality of components including an integer exponent value and a mantissa value, said processing operation including
generating a plurality of result components, the processing operation comprising:

for each of said plurality of components, forming a high order exponent portion Eho being an uppermost P bits of said integer exponent value, where P is less than a total number of bits within said integer
exponent value, and

selecting a highest value Ehomax from among said high order exponent portions Eho,

wherein Ehomax identifies a highest integer exponent value B of said plurality of components;

selecting an exponent shift value C such that (B+C) is less than a first predetermined value Edotmax and (B+C) is greater than a second predetermined value Edotmin, where said exponent shift value C is an integer value; and

for each of said plurality of components, if said exponent shift value C is non-zero, then adding a value of (2(P?1)?Ehomax) to said high order exponent portion Eho to generate one of said plurality of result components.

US Pat. No. 9,142,266

MEMORY CIRCUITRY USING WRITE ASSIST VOLTAGE BOOST

ARM Limited, Cambridge (...

1. Memory circuitry comprising:
an array of bit cells;
a plurality of bit lines, each of said plurality of bit lines coupled to a column of bit cells within said array;
write driver circuitry selectively coupled to each of said bit lines through a respective column select transistor controlled
by a column select signal, said write driver circuitry supplying write signal with a write voltage level outside of a voltage
range between a first voltage level and a second voltage level in order to perform a write operation within said array;

column select circuitry coupled to a power supply via a first power supply rail at said first voltage level and a second power
supply rail at said second voltage level, said first voltage level being higher than said second voltage level, said column
select circuitry being configured to select one or more target columns of bit cells within to which a write operation is to
be performed by:

(i) supplying a column select signal with a selected signal level to respective column select transistors for said one or
more target columns, said selected signal level holding said respective column select transistor for said one or more target
columns in a low impedance state; and

(ii) supplying a column select signal with an unselected signal level to respective column select transistors for one or more
unselected columns within said array other than said one or more target columns, said unselected signal level holding said
respective column select transistor for said one or more other columns in a high impedance state;

wherein at least one of said selected signal level and said unselected signal level is outside of said voltage range between
said first voltage level and said second voltage level.

US Pat. No. 9,070,431

MEMORY CIRCUITRY WITH WRITE ASSIST

ARM Limited, Cambridge (...

1. Memory circuitry comprising:
a plurality of bit cells configured to store respective data bits;
write circuitry configured to write data bits to target bit cells of said plurality of bit cells during a write operation;
and

write assist circuitry configured to lower a power supply signal supplied to said target bit cells during said write operation;
wherein

said write assist circuitry comprises:
a plurality of switches connected in series between a first power supply rail having a first power supply signal level and
a second power supply rail having a second power supply signal level, said plurality of switches including a header switch
having a header gate input and a footer switch having a footer gate input;

header bias circuitry configured to generate a header bias signal supplied to said header gate input during said write operation;
and

footer bias circuitry configured to generate a footer bias signal supplied to said footer gate input during said write operation;
said header bias signal is an analog signal with a signal level intermediate between said first power supply signal level
and said second power supply signal level;

said footer bias signal is an analog signal with a signal level intermediate between said first power supply signal level
and said second power supply signal level; and

during said write operation said target bit cells are supplied with power via a current path through said header switch such
that said power supply signal supplied to said target bit cells during said write operation is controlled by both said header
bias signal and said footer bias signal.

US Pat. No. 10,030,238

RECOMBINANT CLOSTRIDIUM BOTULINUM NEUROTOXINS

IPSEN BIOINNOVATION LIMIT...

1. A nucleic acid sequence having at least 90% sequence identity to SEQ ID NO: 1, wherein the sequence encodes a single-chain BoNT/E1 polypeptide.

US Pat. No. 9,985,613

FLIP-FLOP

ARM Limited, Cambridge (...

1. A single-phase flip-flop comprising:a master latch comprising:
a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal;
a slave latch comprising:
a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal;
wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal; and
wherein one or both of the first master logic operation and first slave logic operation comprise an AND and OR operation and wherein the second master logic operation comprises an OR operation.

US Pat. No. 9,501,667

SECURITY DOMAIN PREDICTION

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
processing circuitry configured to perform data processing operations in response to program instructions, said processing
circuitry having a plurality of domains of operation including a secure domain and a less secure domain, wherein when operating
in said secure domain said processing circuitry has access to data that is not accessible when operating in said less secure
domain; and

prediction circuitry coupled to said processing circuitry and configured to generate a domain prediction predicting whether
a given processing action to be performed by said processing circuitry should be performed associated with said secure domain
or associated with said less secure domain, wherein

said processing circuitry performs said given processing action based upon said domain prediction.

US Pat. No. 9,378,175

DATA TRANSFER BETWEEN A MASTER AND SLAVE

ARM Limited, Cambridge (...

1. A data processing apparatus comprising at least one initiator configured to communicate with at least one recipient via
a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving
data from said bus; said data processing apparatus further comprising:
an initiator clock signal generator for generating an initiator clock signal,
an initiator output enable signal generator for generating an initiator output-enable signal, and
an initiator input enable signal generator for generating an initiator input enable signal, said initiator being clocked by
said initiator clock signal;

said output port being clocked by said initiator output enable signal such that said output port is configured to assert data
to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said
input port is configured to latch data received on a read channel on said bus in response to said initiator input enable signal
having a second predetermined level; wherein

said initiator output enable signal generator and initiator input enable signal generator are configured to output signals
that are different from each other, said at least one recipient is clocked by a recipient clock signal that is slower than
said initiator clock signal by a half integer ratio; said initiator output enable signal generator is configured to generate
said initiator output enable signal that has said first predetermined level during a triggering transition of said recipient
clock signal and retains said first predetermined level for a clock cycle of said initiator clock; and said initiator output
enable signal is configured to retain said first predetermined level for two initiator clock cycles where a second triggering
transition of said recipient clock signal occurs during the second of the two initiator clock cycles and to only retain said
first predetermined level for a single initiator clock cycle where a second triggering transition of said recipient clock
signal does not occur during said second of the two initiator clock cycles.

US Pat. No. 9,208,839

PREDICTING SATURATION IN A SHIFT OPERATION

ARM Limited, Cambridge (...

1. Apparatus for data processing, comprising:
shift circuitry configured to perform a shift operation in response to a shift instruction, wherein the shift operation is
performed on an input data value and comprises shifting bits of the input data value in a direction specified by the shift
instruction to generate a shifted data value;

bit location indicator generation circuitry configured to generate a bit location indicator, wherein the bit location indicator
indicates at least one bit location in the input data value which must not have a bit set if the shifted data value is not
to saturate; and

comparison circuitry configured to compare the bit location indicator with the input data value and to indicate a saturation
condition if any bits are indicated by the bit location indicator for bit locations which hold set bits in the input data
value,

wherein the bit location indicator generation circuitry and comparison circuitry are configured to operate in parallel with
the shift circuitry;

wherein the bit location indicator generation circuitry comprises mask generation circuitry configured to generate a mask
data value as the bit location indicator, wherein the mask data value has bits set at bit locations corresponding to bit locations
in the input data value which must not have bits set if the shifted data value is not to saturate;

wherein the mask data value comprises a sequence of set bits concatenated with a sequence of unset bits, wherein the relative
lengths of the sequence of set bits and the sequence of unset bits is determined in dependence on a shift distance specified
by the shift instruction.

US Pat. No. 9,201,656

DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING REGISTER RENAMING FOR CERTAIN DATA PROCESSING OPERATIONS WITHOUT ADDITIONAL REGISTERS

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
processing circuitry configured to perform data processing operations in response to data processing instructions, said data
processing instructions referencing logical registers;

a set of physical registers configured to store data values for access by the processing circuitry when performing said data
processing operations;

register renaming storage configured to store a one-to-one mapping between said logical registers and said set of physical
registers, the register renaming storage being accessed by the processing circuitry when performing said data processing operations
in order to map the referenced logical registers to corresponding physical registers in said set of physical registers;

update circuitry, responsive to a current data processing operation performed by the processing circuitry requiring data to
be written in respect of multiple of said logical registers, to identify physical registers corresponding to said multiple
of said logical registers in the register renaming storage, and to alter within the register renaming storage the one-to-one
mapping between said multiple of said logical registers and those identified physical registers, such that the altered one-to-one
mapping is employed when performing said current data processing operation; and

in all instances, when said current data processing operation requires data to be written in respect of only one of said logical
registers, the one-to-one mapping within the register renaming storage is retained unaltered such that the unaltered one-to-one
mapping is employed when mapping each referenced logical register to the corresponding physical register during performance
of said current data processing operation.

US Pat. No. 9,189,432

APPARATUS AND METHOD FOR PREDICTING TARGET STORAGE UNIT

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
processing circuitry configured to execute program instructions to process data;
a plurality of storage units comprising storage locations addressable by storage addresses;
a storage controller configured to control access to said plurality of storage units and when said processing circuitry executes
a data access instruction to access a target storage location addressed by a target storage address, to identify, based on
said target storage address, which of said plurality of storage units is a target storage unit that includes said target storage
location; and

prediction circuitry configured to detect whether said processing circuitry is executing a data access instruction of a predetermined
type, and, upon detecting said processing circuitry executing said data access instruction of said predetermined type, to
determine, based on the type of data access instruction, a predicted storage unit predicted to include said target storage
location, wherein

said storage controller is configured to initiate a data access to said predicted storage unit before said storage controller
has identified said target storage unit, wherein said predetermined type of data access instruction is distinguished from
at least one other type of data access instruction by at least one of a different opcode, a different addressing mode, and
a different register referenced by the instruction.

US Pat. No. 9,171,594

HANDLING COLLISIONS BETWEEN ACCESSES IN MULTIPORT MEMORIES

ARM Limited, Cambridge (...

1. A multiport memory comprising:
an array of storage cells for storing data, each storage cell comprising storage circuitry and a plurality of access control
devices for isolating said storage circuitry from or connecting said storage circuitry to a data line, said memory comprising
a plurality of sets of access control lines and corresponding data lines, each set of access control lines controlling one
of said plurality of access control devices for each of said storage cells, said data lines each being coupled to a column
of said storage cells and said access control lines each being coupled to a row of said storage cells;

a plurality of data access ports;
access control circuitry configured to assign each data access port to one of said sets of access control lines and corresponding
data lines;

said access control circuitry comprising collision detection circuitry configured to detect a colliding data access request
received at a second data access port that requests access to a row of storage cells currently being accessed by a data access
request received at a first data access port;

said access control circuitry being configured to respond to said detected collision to assign said set of access control
lines and corresponding data lines currently assigned to said first data access port to said second data access port and following
completion of said data access request received at said first data access port to subsequently assign said first data access
port to said set of access control lines and corresponding data lines previously assigned to said second data access port.

US Pat. No. 9,122,646

GRAPHICS PROCESSING SYSTEMS

ARM LIMITED, Cambridge (...

1. A method of generating an output array of data comprising a plurality of blocks of data in a data processing system that
comprises plural data block generating processors, the method comprising:
initially allocating a different data block of the plurality of data blocks to be generated to each data block generating
processor; and

when each processor completes the data block it is currently processing, allocating another data block that is still to be
processed to that processor, and so on, until all the data blocks to be generated have been allocated to processors;

wherein the next data block to be allocated to a given processor for processing is selected as being the next data block along
a path defined for that given processor that starts at the data block initially allocated to that processor and that will
traverse every data block to be generated if followed to its end, and which path is configured such that, at least for the
initial data blocks along the path, adjacent data blocks in the path are spatially adjacent in the output array of data, unless
the next data block in the path for the given processor has already been allocated to another processor, in which case the
next data block to be allocated to the given processor is selected to be a data block further on in the data block traversal
path for that given processor that is still to be allocated to a processor for processing.

US Pat. No. 9,111,596

MEMORY ACCESS CONTROL IN A MEMORY DEVICE

ARM Limited, Cambridge (...

1. A memory device comprising:
an array of bitcells, each bitcell configured to store a data bit, wherein said array comprises a plurality of rows of bitcells
and a plurality of columns of bitcells;

a plurality of wordlines, wherein each row of bitcells has an associated wordline;
a plurality of readout channels, wherein each column of bitcells has an associated readout channel; and
control circuitry configured to control access to said array of bitcells, wherein in response to a memory access request which
specifies a memory address said control circuitry is configured to activate a selected wordline and to activate said plurality
of readout channels, and to access a row of bitcells in said array storing a data word and addressed by said memory address,
wherein said data word includes a number of data bits given by a number of bitcells in each row of bitcells,

wherein said control circuitry is further configured to be responsive to a masking signal and, when said masking signal is
asserted when said memory access request is received, said control circuitry is configured to activate only a portion of said
selected wordline and a portion of said plurality of readout channels, such that only a portion of said data word is accessed.

US Pat. No. 9,104,479

APPARATUS AND METHOD FOR ROUNDING A FLOATING-POINT VALUE TO AN INTEGRAL FLOATING-POINT VALUE

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
processing circuitry configured to perform a round to integral floating-point operation for rounding a floating-point value
to an integral floating-point value, said floating-point value having a significand and an exponent; and

control circuitry configured to control said processing circuitry to perform said round to integral floating-point operation
in response to execution of a floating-point round to integral floating-point instruction;

said processing circuitry comprising:
shifting circuitry configured to generate a rounding value by shifting a base value by a shift amount dependent on said exponent
of said floating-point value;

adding circuitry configured to add said rounding value to said significand of said floating-point value to generate a sum
value;

mask generating circuitry configured to generate a mask for clearing bits of said sum value having bit positions corresponding
to fractional-valued bit positions of said significand; and

masking circuitry configured to apply said mask to said sum value to generate said integral floating-point value,
wherein said processing circuitry has at least one rounding mode for selecting, when said floating-point value lying between
two integral floating-point values, which of said two integral floating-point values to round said floating-point value to
during said round to integral floating-point operation, and

wherein said processing circuitry has a round to nearest, ties to even, (RNE) rounding mode for rounding said floating-point
value to the nearest of said two integral floating-point values, with floating-point values lying halfway between said two
integral floating-point values being rounded to the one of said two integral floating-point value that is an even value, and

wherein said RNE rounding mode, if said floating-point value lies halfway between said two integral floating-point values,
and a least significant integral-valued bit of said significand has a zero bit value, then said mask generating circuitry
is configured to correct said mask, and said masking circuitry is configured to apply said corrected mask to said sum value
to clear a bit of said sum value having a bit position corresponding to said least significant integral-valued bit of said
significand.

US Pat. No. 9,075,621

ERROR RECOVERY UPON REACHING OLDEST INSTRUCTION MARKED WITH ERROR OR UPON TIMED EXPIRATION BY FLUSHING INSTRUCTIONS IN PIPELINE PENDING QUEUE AND RESTARTING EXECUTION

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
an execution pipeline configured to execute instructions in a sequence of pipelined execution stages;
an error detection unit configured to generate a first sample of a signal associated with execution of an instruction in said
execution pipeline, configured to generate a second sample of said signal after a delay period, and configured to generate
an error signal associated with said instruction if said first sample and said second sample differ;

an exception storage unit configured to maintain an age-ordered list of entries corresponding to instructions issued to said
execution pipeline for execution, each entry initially defined as pending,

said exception storage unit configured to store in association with each entry an error marker if said error signal has been
generated in association with the instruction corresponding to that entry,

said exception storage unit configured to mark an entry as non-pending when said execution pipeline indicates that an instruction
associated with said entry has completed execution without said error signal being generated in association therewith,

and said exception storage unit configured to sequentially retire oldest non-pending entries from said list;
a timer unit configured to be responsive to generation of said error signal to initiate timing of a predetermined time period;
an error recovery unit configured to cause a soft flush procedure to be carried out if an oldest pending entry in said list
has said error marker stored in association therewith, said soft flush procedure comprising removing all pending entries from
said list, cancelling execution in said pipelined execution stages of instructions corresponding to said pending entries,
cancelling said timing of said predetermined time period and restarting execution of said instructions at an instruction corresponding
to said oldest pending entry; and

said error recovery unit configured to cause a hard flush procedure to be carried out if said predetermined time period elapses,
said hard flush procedure comprising removing all entries from said list, resetting said pipeline to a predetermined state
and restarting execution of said instructions at an instruction corresponding to an oldest entry in said list.

US Pat. No. 9,836,279

APPARATUS AND METHOD FOR FLOATING-POINT MULTIPLICATION

ARM Limited, Cambridge (...

1. Apparatus for floating-point multiplication comprising:
partial product generation circuitry to multiply significands of a first floating-point operand and a second floating-point
operand to generate first and second partial products;

adder circuitry to add the first and second partial products to generate a product significand;
exponent calculation circuitry to calculate a value of an unbiased exponent of a result of the multiplication in dependence
on exponent values and leading zero counts of the first and second floating-point operands and to determine a shift amount
and a shift direction for the product significand in dependence on a predetermined minimum exponent value of a predetermined
canonical format;

shift circuitry to shift the product significand by the shift amount in the shift direction in order to generate a formatted
significand in the predetermined canonical format;

mask generation circuitry to generate an overflow mask identifying an overflow bit position of the product significand, wherein
the mask generation circuitry is arranged to generate the overflow mask by right shifting a predetermined mask pattern by
the shift amount; and

comparison circuitry to apply the overflow mask to the product significand to extract an overflow value at the overflow bit
position, wherein the comparison circuitry is arranged to extract the overflow value before the shift circuitry shifts the
product significand.

US Pat. No. 9,432,009

CIRCUIT DELAY MONITORING APPARATUS AND METHOD

ARM Limited, Cambridge (...

1. A circuit delay monitoring apparatus comprising:
a ring oscillator comprising a plurality of delay elements, a signal transition being propagated through the delay elements
of the ring oscillator;

a plurality N of sampling points distributed around the ring oscillator;
fine sampling circuitry configured to sample signal values at each of the plurality of sampling points under control of a
reference clock signal, in order to generate an indication of a current location of the signal transition within the ring
oscillator;

coarse sampling circuitry comprising M transition counter circuits, where M is at least 2 and less than N, each transition
counter circuit being connected to an associated location within the ring oscillator and configured to increment a count value
each time the signal transition passes the associated location, the coarse sampling circuitry being configured to sample the
count value under control of the reference clock signal, the M transition counter circuits being connected to the ring oscillator
so that, at any point in time, the separation between the current location of the signal transition and the associated location
of at least one of said M transition counter circuits will be greater than a predetermined amount;

selection circuitry configured to select, in dependence on the indication of the current location of the signal transition
generated by the fine sampling circuitry, one of said M transition counter circuits whose associated location is greater than
said predetermined amount from the current location of the signal transition; and

output generation circuitry configured to generate a count indication for a reference time period dependent on a sampled count
value of the transition counter circuit selected by the selection circuitry, the indication of the current location of the
signal transition within the ring oscillator, and reference count data relating to the start of the reference time period.

US Pat. No. 9,378,186

DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A TRANSFORM BETWEEN SPATIAL AND FREQUENCY DOMAINS WHEN PROCESSING VIDEO DATA

ARM Limited, Cambridge (...

1. A data processing apparatus for performing a transform between spatial and frequency domains when processing video data,
the data processing apparatus comprising:
transform circuitry configured to receive N input values and to perform a sequence of operations to generate N output values
representing the transform of said N input values between the spatial and frequency domains;

a base circuitry configured to receive M internal input values generated by the transform circuitry, where M is greater than
or equal to 4, and to perform a base operation equivalent to matrix multiplication of said M internal input values by a matrix
comprising an array of coefficients c and having the form


in order to generate M internal output values for returning to the transform circuitry; and
the transform circuitry being arranged during performance of said sequence of operations to generate from the N input values
multiple sets of said M internal input values, to provide each set of M internal input values to the base circuitry in order
to cause multiple sets of said M internal output values to be produced, and to derive the N output values from said multiple
sets of M internal output values.

US Pat. No. 9,324,163

METHODS OF AND APPARATUS FOR COMPRESSING DEPTH DATA

ARM LIMITED, Cambridge (...

1. A method of compressing depth data in a tile-based graphics processing system that comprises:
a graphics processing pipeline comprising:
a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments
to be processed, each graphics fragment having one or more sampling points associated with it, and a renderer that processes
fragments generated by the rasteriser to generate rendered fragment data;

a tile buffer configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being
written out to an external memory, the tile buffer comprising an allocated amount of memory for use as a depth buffer that
stores an array of depth values and an allocated amount of memory for use as a colour buffer that stores an array of colour
datasets, each colour dataset comprising plural colour values that correspond respectively to plural colour data channels;
and

a write out stage configured to write data stored in the tile buffer to external memory;
wherein the method comprises the write out stage when writing depth data from the tile buffer to memory:
dividing each depth value to be compressed into plural parts;
forming plural depth data channels, wherein each depth data channel is formed by associating corresponding ones of the plural
parts of different depth values with each other;

applying a data compression scheme separately to each depth data channel to be compressed in order to produce compressed representations
of the depth data channels; and

writing the compressed representations of the depth data channels to memory; and
wherein the step of dividing each depth value stored in the depth buffer to be compressed into plural parts comprises storing
the parts of each depth value to be compressed in respective colour channels of a colour dataset in the colour buffer; and

the step of applying the data compression scheme separately to each depth data channel is performed by the write out unit
on the depth data that is stored in the colour buffer.

US Pat. No. 9,213,660

RECEIVER BASED COMMUNICATION PERMISSION TOKEN ALLOCATION

ARM Limited, Cambridge (...

1. Apparatus for processing data, said apparatus comprising:
a master device configured to initiate messages;
a slave device configured to respond to messages received from said master device; and
communication circuitry configured to provide communication of messages between said master device and said slave device;
wherein

said slave device is associated with a predetermined number permission tokens, said predetermined number of permission tokens
being equal to a maximum number of concurrently pending messages that can be accepted for processing from said communication
circuitry by said slave device under control of said permission tokens;

said slave device is configured to transmit said permission tokens to said master device via said communication circuitry;
said master device is configured to take exclusive temporary possession of a permission token received via said communication
circuitry such that said permission token is no longer available for possession by any other master device;

said master device is configured to initiate a message to said slave device only when said master device has said exclusive
temporary possession of said permission token; and

said master device is configured to relinquish said exclusive temporary possession of said permission token after said message
has been completed.

US Pat. No. 9,201,749

DIAGNOSING CODE USING SINGLE STEP EXECUTION

ARM LIMITED, Cambridge (...

1. A method for diagnosing a processor processing a stream of instructions comprising:
(i) controlling said processor to execute in a single step mode such that a single instruction from said instruction stream
is executed, said processor determines if said single instruction is one of at least one predetermined type of instruction
and stores a type indicator in a data storage location and a diagnostic exception is taken after said processor has processed
said single instruction;

(ii) performing diagnostic operations following said diagnostic exception including: accessing said type indicator stored
in said data storage location; and

(iiia) in response to said type indicator indicating said single instruction was not one of said predetermined type controlling
said processor to continue executing instructions in said single step mode such that a next single instruction is executed
on return from said diagnostic exception;

(iiib) in response to said type indicator indicating said single instruction was one of said at least one predetermined type
controlling said processor to exit said single step mode and not execute said next instruction within said instruction stream
as a single instruction followed by a diagnostic exception.

US Pat. No. 9,158,574

HANDLING INTERRUPTS IN DATA PROCESSING

ARM Limited, Cambridge (...

1. A method of processing data comprising:
processing a function using a processor operable to perform a plurality of functions;
receiving an interrupt during processing of said function at a point during said processing at which a portion of said function
has been processed;

accessing a control parameter, said control parameter indicating whether said function has idempotence or not;
in response to said control parameter having a value indicating that said function has idempotence, stopping processing of
said function without processing said function further, and discarding information on progress of said function such that
following completion of said interrupt said portion of said function that has already been processed is processed again; and

in response to said control parameter having a value indicating that said function does not have idempotence, suspending processing
of said function without discarding information on progress of said function that has already been processed such that following
completion of said interrupt said processing resumes from a point that it reached when it was suspended.

US Pat. No. 9,570,157

DYNAMIC CAPACITANCE BALANCING

ARM Limited, Cambridge (...

1. A device, comprising:
a sense amplifier coupled to complimentary bitlines, wherein the sense amplifier is configured to receive complimentary data
signals from the complimentary bitlines and provide first and second sensed data signals based on the received complimentary
data signals, and wherein the second sensed data signal is a compliment of the first sensed data signal;

a balance coupler coupled to the sense amplifier and configured to receive the second sensed data signal from the sense amplifier
and provide a modified second sensed data signal having capacitance similar to the first sensed data signal; and

a latch coupled to the sense amplifier and the balance coupler, wherein the latch is configured to receive the first sensed
data signal from the sense amplifier, receive the modified second sensed data signal from the balance coupler, and provide
a latched data signal based on the first and modified second sensed data signals.

US Pat. No. 9,519,538

ERROR RECOVERY FOLLOWING SPECULATIVE EXECUTION WITH AN INSTRUCTION PROCESSING PIPELINE

ARM Limited, Cambridge (...

1. Apparatus for processing data comprising:
an instruction processing pipeline having a plurality of pipeline stages;
at least one error detector, coupled to a pipeline stage of said instruction processing pipeline and responsive to at least
one signal value within said pipeline stage, configured to detect a processing error associated with an erring program instruction
within said pipeline stage;

error recovery circuitry, coupled to said at least one error detector and responsive to detection of a processing error by
said error detector, configured to initiate an error recovery operation, wherein said pipeline stage, includes a first main
storage element and a second main storage element, configured to sample a signal for respective program instructions at respective
operational sampling points in an alternating sequence, and said error recovery operation includes replacing an incorrect
signal value stored in one of said first main storage element and said second main storage element with a correct value subsequent
to said operational sampling point while a signal value for a following program instruction remains stored in the other of
said first main storage element and said second main storage element; and

thread control circuitry, coupled to said instruction processing pipeline and responsive to program instructions from a plurality
of different program threads to control supply of an interleaved stream of program instructions from different program threads,
configured to store signal values from a first program thread in said first main storage element, and signal values from a
second different program thread in said second main storage element,

wherein a thread identifying signal accompanies a program instruction passing along said instruction processing pipeline and
is coupled to said first main storage element and said second main storage element to gate sampling thereby of said signal
at said operational sampling point.

US Pat. No. 9,472,018

GRAPHICS PROCESSING SYSTEMS

ARM LIMITED, Cambridge (...

1. A method of operating a graphics processing system when an overlay image is to be overlaid on an existing image for which
data is already stored in an output array of data in an output buffer, the method comprising:
reading data for the existing image from the output array of data in the output buffer;
using data for the overlay image to modify data for the existing image to generate an overlaid image showing the overlay image
overlaid on the existing image; and

writing data for the overlaid image back to the output array of data in the output buffer, wherein:
the step of writing data for the overlaid image back to the output array of data in the output buffer comprises:
determining whether there are any regions of the existing image that have not been modified when modifying the data for the
existing image to generate the overlaid image; and

for any regions of the existing image that have been determined to have not been modified when modifying the data for the
existing image to generate the overlaid image, not writing data for the overlaid image for those unmodified regions of the
existing image back to the output array of data in the output buffer, and using the data for those regions of the existing
image that is already stored in the output data array in the output buffer for the overlaid image; and

the method further comprises:
as the overlaid image is rendered, loading any existing image data in the output data array that is needed for the overlay
rendering process back into a local memory of the graphics processing system from the output buffer for modification using
data for the overlay image to show the overlay image overlaid on the existing image;

wherein:
the step of loading existing image data in the output data array that is needed for the overlay rendering process back into
a local memory of the graphics processing system from the output buffer for modification using data for the overlay image
to show the overlay image overlaid on the existing image comprises:

identifying regions of the existing image that will be modified using data for the overlay image as the overlaid image is
rendered; and

when a region of the image has been identified as a region of the existing image that will be modified using data for the
overlay image as the overlaid image is rendered, determining whether the existing image data is needed for the modification
process, and then only loading the existing image data in that event.

US Pat. No. 9,378,113

TRACING OF A DATA PROCESSING APPARATUS

ARM Limited, Cambridge (...

1. A trace unit configured to generate items of trace data indicative of processing activities of a data processing apparatus,
said trace unit comprising:
a trace input interface for receiving from said data processing apparatus at least one instruction observed indicator indicating
execution of a conditional instruction and at least one result output indicator indicating output by said data processing
apparatus of a result of executing said at least one conditional instruction; and

tracing circuitry for processing said at least one instruction observed indicator and said at least one result output indicator
and configured to generate from said at least one instruction observed indicator and said at least one result output indicator
corresponding conditional instruction trace data items indicating execution of said conditional instruction and conditional
result trace data items indicating said result of executing said conditional instruction and to independently output said
conditional instruction trace data items and said conditional result trace data items enabling separate trace analysis of
conditional instructions and corresponding conditional results by a diagnostic apparatus.

US Pat. No. 9,292,036

DATA PROCESSING APPARATUS AND METHOD FOR COMMUNICATING BETWEEN A MASTER DEVICE AND AN ASYNCHRONOUS SLAVE DEVICE VIA AN INTERFACE

ARM Limited, Cambridge (...

1. A data processing apparatus comprising:
a master device configured to operate from a master clock signal;
an interface between said master device and a slave device configured to operate from a slave clock signal asynchronous to
said master clock signal, the interface providing a communication path for the transfer of packets between the master device
and the slave device, each packet comprising a plurality of bits;

the master device being configured to initiate transactions, each transaction comprising a plurality of transfers including
a master transfer to transmit a packet from the master device to the slave device and a slave transfer to transmit a packet
from the slave device to the master device;

the master device including a slave clock replica generator configured to generate a slave clock replica used to control timing
of transmission of packets by the master device over the interface, and to control timing of reception by the master device
of packets sent by the slave device over the interface;

the master device including control circuitry configured in response to a predetermined trigger condition to cause a sync
request transfer to be issued over said interface from the master device to the slave device, the sync request transfer having
a property identifiable by the slave device irrespective of whether the sync request transfer is synchronised with the slave
clock signal;

the slave clock replica generator being configured to determine at least the frequency of the slave clock replica from a sync
response transfer received over the interface from the slave device, the sync response transfer being issued in response to
detection of said sync request transfer by the slave device, and being indicative of at least a frequency of the slave clock
signal; and

the slave clock replica generator further being configured to reference at least a portion of the packet of selected slave
transfers to determine a phase of the slave clock replica, said at least a portion of the packet containing at least one transition
between a first value and a second value different to said first value;

whereby the determination of the phase of the slave clock replica is decoupled from the determination of the frequency of
the slave clock replica.

US Pat. No. 9,286,196

PROGRAM EXECUTION OPTIMIZATION USING UNIFORM VARIABLE IDENTIFICATION

ARM Limited, Cambridge (...

1. A processor-executed method of optimizing execution of a computer program, the method comprising the steps of:
identifying basic blocks of instructions within the computer program, wherein each basic block has only one entry point and
only one exit point;

performing a topology-based control flow analysis of the basic blocks to associate at least one tag ID with each basic block,
wherein a tag ID identifies at least one run-time thread having a given run-time instruction sequence;

performing a data flow analysis of instructions within the basic blocks and their associated tag IDs to determine whether
each instruction of said computer program is uniform or non-uniform, wherein a uniform instruction has a same value for all
tag IDs associated with the basic block containing the uniform instruction,

wherein, in the data flow analysis, for each immediate successor basic block of an analysed basic block, when the analysed
basic block ends with a non-uniform conditional branch instruction, a dummy block is generated on each edge from the analysed
basic block to the immediate successor basic block and a new tag ID is generated for association with each dummy block,

wherein, in the topology-based control flow analysis, when the analysed basic block immediately post-dominates a second basic
block and the second basic block ends with a non-uniform conditional branch instruction, any tag IDs associated with the second
basic block are associated with the analysed basic block,

wherein, in the topology-based control flow analysis, when the analysed basic block immediately post-dominates a third basic
block, and the third basic block ends with a non-uniform conditional branch instruction, tag IDs of successors of the third
basic block are dissociated from the analysed basic block, and

wherein a phi instruction is determined to be non-uniform, wherein the phi instruction merges two or more variable definitions
into a single variable definition from plural predecessor basic blocks of the analysed basic block, when operands of the phi
instruction originate in basic blocks which are associated with more than one tag ID; and

suppressing storage, when the computer program is executed, of a copy of a variable dependent on a uniform instruction.

US Pat. No. 9,214,204

WORDLINE PULSE DURATION ADAPTATION IN A DATA STORAGE APPARATUS

ARM Limited, Cambridge (...

1. Apparatus for storing data, comprising:
an array of bitcells, the array comprising a plurality of rows of bitcells, wherein access to a selected bitcell in the array
of bitcells requires assertion of a wordline pulse on a wordline associated with a row in which the selected bitcell is to
be found;

wordline pulse circuitry configured to generate the wordline pulse;
sensor circuitry comprising a calibrated bitcell and a test wordline, wherein the calibrated bitcell is calibrated in a prior
calibration process to use, in writing to the calibrated bitcell, a calibrated duration of wordline pulse on the test wordline
which matches a longest wordline pulse required by any bitcell in the array of bitcells for a successful write operation to
be carried out,

wherein the sensor circuitry is configured to signal a wordline pulse duration to the wordline pulse circuitry based on the
calibrated duration and wherein the wordline pulse circuitry is configured to generate the wordline pulse with the wordline
pulse duration signalled by the sensor circuitry,

and wherein the sensor circuitry is configured to adapt the wordline pulse duration in dependence on current local conditions
in which the apparatus operates to compensate for influence of the current local conditions on the longest wordline pulse
required by any bitcell in the array of bitcells.

US Pat. No. 9,214,837

ELECTRIC MOTOR WITH PLURAL STATOR COMPONENTS

ARM Limited, Cambridge (...

1. An electric motor apparatus comprising:
a rotor; and
a stator formed of at least two stator components, each of said at least two stator components having a substantially hollow
cylindrical form;

said rotor being mounted within said at least two stator components on a rotational mounting such that said rotor can rotate
about a longitudinal central axis with respect to said stator;

each of said at least two stator components comprising at least two protrusions arranged at different circumferential points
on an inner surface of said at least two stator components, each of said at least two protrusions having a winding mounted
thereon; and

control circuitry configured to generate control signals to control power supplied to said windings on each of said at least
two stator components, such that power can be controlled to each of said at least two stator components independently of each
other; wherein

said at least two stator components are mounted adjacent to each other along said longitudinal central axis and rotationally
offset with respect to each other, such that said at least two protrusions on one of said at least two stator components are
offset with respect to said at least two protrusions on an adjacently mounted one of said at least two stator components,
such that a portion of each of said windings that extends beyond a longitudinal end of said protrusions on said one of said
at least two stator components fits within a gap between windings mounted on said adjacently mounted stator component.

US Pat. No. 9,146,870

PERFORMANCE OF ACCESSES FROM MULTIPLE PROCESSORS TO A SAME MEMORY LOCATION

ARM Limited, Cambridge (...

1. A processing apparatus comprising:
a plurality of processors for processing data;
a hierarchical memory system comprising a plurality of data stores for storing said data, said hierarchical memory system
comprising a memory accessible to all of said plurality of processors, and a plurality of caches corresponding to each of
said plurality of processors, each of said caches being accessible to said corresponding processor and comprising a plurality
of storage locations and a corresponding plurality of indicators, said memory having a lower hierarchy than said plurality
of caches;

cache coherency control circuitry for maintaining coherency of data stored in said hierarchical memory system;
each of said plurality of processors being configured to respond to receipt of a predefined request to perform an operation
on a data item, to determine if said cache corresponding to said processor receiving said request comprises a storage location
allocated to said data item;

and if not, said processing apparatus is configured to:
allocate a storage location within said cache to said data item,
set said indicator corresponding to said storage location to indicate that said storage location is storing a delta value,
set data in said allocated storage location to an initial value, and
said processor is configured in response to said predefined request to perform said operation on data within said storage
location allocated to said data item.

US Pat. No. 9,583,209

HIGH DENSITY MEMORY ARCHITECTURE

ARM Limited, Cambridge (...

1. An integrated circuit, comprising:
a plurality of bank arrays having multiple segments of bitcells configured to share local control; and
a plurality of control lines coupling the local control to each of the multiple segments of bitcells;
wherein, during activation of a segment of bitcells by the local control via one of the control lines, another segment of
bitcells is deactivated by the local control via another of the control lines,

wherein the multiple segments of bitcells are separated by an isolation cell,
wherein the plurality of control lines comprise a first control line coupling the local control to the segment of bitcells
as a first segment of bitcells and a second control line coupling the local control to the another segment of bitcells as
a second segment of bitcells,

during activation of the first segment of bitcells by the local control via the first control line, the second control line
is deactivated by the local control,

during activation of the second segment of bitcells by the local control via the second control line, the first control line
is deactivated by the local control, and

wherein the first control line comprises a first bitline, wherein the second control line comprises a second bitline, and
wherein activating and deactivating the first and second bitlines increases performance of the integrated circuit.

US Pat. No. 9,564,187

PREDICTING SATURATION IN A SHIFT OPERATION

ARM Limited, Cambridge (...

1. Apparatus for data processing, comprising:
shift circuitry configured to perform a shift operation in response to a shift instruction, wherein the shift operation is
performed on an input data value and comprises shifting bits of the input data value in a direction specified by the shift
instruction to generate a shifted data value;

bit location indicator generation circuitry configured to generate a bit location indicator, wherein the bit location indicator
indicates at least one bit location in the input data value which must not have a bit set if the shifted data value is not
to saturate; and

comparison circuitry configured to compare the bit location indicator with the input data value and to indicate a saturation
condition if any bits are indicated by the bit location indicator for bit locations which hold set bits in the input data
value,

wherein the bit location indicator generation circuitry and comparison circuitry are configured to operate in parallel with
the shift circuitry.

US Pat. No. 9,519,456

DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A SHIFT FUNCTION ON A BINARY NUMBER

ARM Limited, Cambridge (...

13. A data processing apparatus for performing a shift function on a binary number, comprising:
count determination circuitry configured to determine a number of contiguous bit positions in the binary number having a predetermined
bit value, and to output a count value indicative of said number of contiguous bit positions;

coarse shifting circuitry configured to determine, for at least one predetermined number of contiguous bit positions, whether
said predetermined number of contiguous bit positions within the binary number has said predetermined bit value, and to perform
an initial shift operation on the binary number based on said determination in order to produce an intermediate binary number,
said coarse shifting circuitry operating in parallel with said count determination circuitry;

fine shifting circuitry configured to perform a further shift operation on the intermediate binary number, based on the count
value output by the count determination circuitry, in order to produce a result binary number; and

an input configured to receive a floating point number comprising a fraction and an exponent, the binary number being determined
from said fraction, and said shift function being performed as part of a normalization operation applied to said floating
point number;

wherein said shift function is performed if said floating point number is subnormal;
wherein the floating point number is determined to be subnormal if the exponent has a predetermined exponent value, and the
coarse shifting circuitry is configured to receive the exponent and to cause the initial shift operation to perform no shift
on the binary number if the exponent does not have said predetermined exponent value;

wherein the exponent has said predetermined exponent value if each bit position of said exponent has said predetermined bit
value;

wherein the coarse shifting circuitry is configured to receive as an input value the fraction prepended with the exponent,
and the coarse shifting circuitry is configured to evaluate said input value, starting from a first end comprising said exponent,
in order to determine, for said at least one predetermined number of contiguous bit positions, whether said predetermined
number of contiguous bit positions within the binary number has said predetermined bit value.

US Pat. No. 9,462,469

SYSTEMS AND METHODS FOR SHORT RANGE WIRELESS DATA TRANSFER

ARM LIMITED, Cambridge (...

1. A method for authenticated data transfer between a low energy short range wireless device and an accessory associated with
a user of the accessory, the method comprising:
establishing a network connection between the low energy short range wireless device and a server;
accessing account information associated with the user, where the account information is stored in a database accessible by
the server, the account information including accessory credentials;

receiving, by the low energy short range wireless device, the accessory credentials from the server via the network connection;
establishing a short range wireless low energy connection between the low energy short range wireless device and the accessory;
authenticating with the accessory using the accessory credentials of the user account information;
transferring data from the low energy short range wireless device to the accessory after authenticating with the accessory;
and

the low energy short range wireless device:
requesting the accessory to verify the transferred data; and
sending a message to the accessory to disconnect from the low energy short range wireless device and reset,where the accessory credentials comprise a device identifier of the accessory and an authentication key.

US Pat. No. 9,268,942

PROVIDING A TRUSTWORTHY INDICATION OF THE CURRENT STATE OF A MULTI-PROCESSOR DATA PROCESSING APPARATUS

ARM Limited, Cambridge (...

1. A data processing apparatus formed on an integrated circuit comprising:
a plurality of processors;
power control circuitry configured to control power up and power down of said plurality of processors;
a read only memory for storing boot up software for booting up each of said plurality of processors, for execution by a processor
in response to power up of that processor; wherein

said power control circuitry is configured to respond to receipt of a check state request from one of said plurality of processors,
to control another one of said plurality of processors that is currently powered down to power up and to access said boot
up software, said boot up software accessed in response to said check state request controlling said another processor to
perform a measurement indicative of a current state of said data processing apparatus and to output a value indicative of
said measurement to said processor from which said check state request was received.

US Pat. No. 9,213,547

PROCESSOR AND METHOD FOR PROCESSING INSTRUCTIONS USING AT LEAST ONE PROCESSING PIPELINE

ARM Limited, Cambridge (...

1. A processor comprising:
at least one processing pipeline configured to process instructions, the at least one processing pipeline comprising a first
pipeline stage, a second pipeline stage and a third pipeline stage; wherein:

an instruction at the first pipeline stage requires fewer processing cycles to reach the second pipeline stage than to reach
the third pipeline stage;

the second pipeline stage and the third pipeline stage each comprise a duplicated processing resource;
the first pipeline stage is configured to determine, for a pending instruction which requires the duplicated processing resource
and can be processed using the duplicated processing resource in any of the second pipeline stage and the third pipeline stage,
whether an operand required for said pending instruction would be available at a time when the pending instruction would reach
the second pipeline stage;

if the operand for said pending instruction would be available at said time, then the first pipeline stage is configured to
control the at least one processing pipeline to process said pending instruction using the duplicated processing resource
in the second pipeline stage; and

if the operand for said pending instruction would not be available at said time, then the first pipeline stage is configured
to control the at least one processing pipeline to process said pending instruction using the duplicated processing resource
in the third pipeline stage.

US Pat. No. 9,058,637

METHOD OF AND APPARATUS FOR ENCODING AND DECODING DATA

ARM LIMITED, Cambridge (...

1. A method of encoding a set of texture data elements to be used in a graphics processing system, comprising:
encoding by processing circuitry the set of texture data elements as a block of texture data representing the texture data
elements;

storing by the processing circuitry in the texture data block:
data indicating how to generate a set of data values used to generate data values for a set of the texture data elements that
the block represents,

data indicating a set of integer values used to generate the set of data values used to generate data values for a set of
the texture data elements that the block represents,

data indicating a set of index values indicating how to use the generated set of data values to generate data values for texture
data elements of the set of texture data elements that the generated set of data values is used for, and

data indicating the indexing scheme that has been used for the block.

US Pat. No. 9,406,155

GRAPHICS PROCESSING SYSTEMS

ARM Limited, Cambridge (...

1. A method of operating a data processing system in which data generated by the data processing system is used to form an
output array of data in an output buffer, the method comprising:
storing the output array of data in the output buffer by writing blocks of data representing particular regions of the output
array of data to the output buffer; and

when a block of data representing a first region of the output data array has been generated, comparing said block of data
representing the first region of the output data array to at least one other block of data representing a different region
of the same output data array by comparing signatures representative of the content of the respective data blocks, and determining
whether or not to write said block of data representing the first region of the output data array to the output buffer on
the basis of the comparison; and

where it is determined to not write said block of data representing the first region of the output data array to the output
buffer on the basis of the comparison, storing metadata that indicates which other data block of the same data array should
be processed in place of the data block that was not written to the output buffer.