US Pat. No. 9,294,383

BASELINE WANDER COMPENSATING METHOD, BASELINE CALIBRATION MODULE AND ETHERNET TRANSCEIVER USING THE SAME

ALI CORPORATION, Hsinchu...

1. A baseline wander compensating method, adapted for compensating baseline wander induced in an Ethernet transceiver, the
baseline wander compensating method comprising:
detecting an output packet;
comparing a detection result of the output packet and a predetermined value, and generating a control signal correspondingly;
based on the control signal, selecting a first calibration signal or a second calibration signal, and executing a calibrating
calculation for the selected one of the first calibration signal and the second calibration signal; and

compensating an input signal according to a baseline calibration value generated from the calibrating calculation.

US Pat. No. 9,344,758

VIDEO STREAM PROCESSING APPARATUS, METHOD FOR DISPLAYING MIRROR VIDEO, AND DISPLAY DEVICE

ALi Corporation, Hsinchu...

1. A video stream processing apparatus, comprising:
a processor; and
a non-transitory storage medium, coupled to the processor, and configured to store a plurality of program modules, wherein
the plurality of program modules are executed by the processor, and the plurality of program modules comprises:

a connection establishing module, configured to establish a first wireless connection with a first source device, and establish
a second wireless connection with a second source device;

a mirror video receiving module, configured to receive a first mirror video from the first source device through the first
wireless connection, and receive a second mirror video from the second source device through the second wireless connection;
and

a mirror video display module, configured to control a screen to separately display the first mirror video or the second mirror
video, or simultaneously display the first mirror video and the second mirror video.

US Pat. No. 9,185,322

DIGITAL VIDEO BROADCAST RECEIVER

ALi Corporation, Hsinchu...

1. A digital video broadcast receiver, comprising:
a frequency synthesizer, synthesizing a first frequency signal;
a plurality of frequency dividing-phase shifting circuits, coupled to the frequency synthesizer, individually performing a
frequency dividing-phase shifting operation on the first frequency signal to generate a plurality of first signals having
different frequencies and a plurality of second signals corresponding to the first signals, wherein one of the plurality of
first signals is orthogonal to one of the plurality of second signals corresponding to the one of the plurality of first signals;

an antenna, receiving a radio frequency signal;
a plurality of signal processing modules, coupled to the antenna and the frequency dividing-phase shifting circuits, and respectively
obtaining a plurality of signal components belonging to different sub-bands from the radio frequency signal according to the
plurality of first signals and the plurality of second signals,

wherein the first frequency signal is a first differential signal, and each of the frequency dividing-phase shifting circuits
comprises:

a first frequency divider, coupled to the frequency synthesizer, and dividing a frequency of the first differential signal
by a first factor to generate a second differential signal;

a second frequency divider, coupled to the first frequency divider, and dividing a frequency of the second differential signal
by a second factor to generate a third differential signal;

a first D-type flip-flop, coupled to the first frequency divider and the second frequency divider, and outputting a first
differential oscillation signal according to the second differential signal and the third differential signal, wherein the
first differential oscillation signal is one of the first signals; and

a second D-type flip-flop, coupled to the first frequency divider and the second frequency divider, and outputting a second
differential oscillation signal according to the second differential signal and the third differential signal, wherein the
second differential oscillation signal is one of the second signals,

wherein the first differential oscillation signal and the second differential oscillation signal are orthogonal to each other.

US Pat. No. 9,396,155

ENVELOPE DETECTION DEVICE AND RELATED COMMUNICATION DEVICE

ALI Corporation, Hsinchu...

1. An envelope detection device for detecting a transmission signal in a high speed serial communication, comprising:
an operation circuit, for receiving the transmission signal and generating a set of operation outputs according to a difference
between the transmission signal and at least one reference signal;

a reference signal generation circuit, coupled to the operation circuit, for providing the reference signal to the operation
circuit, wherein the reference signal generation circuit is operable to provide the reference signal with different levels;
and

a comparison circuit, coupled to the operation circuit, for comparing the set of the operation outputs to generate a comparison
result;

wherein the envelope detection device detects a transmission state and a disconnect state of the high speed serial communication
according to the comparison results that are generated based on the reference signal at different levels.

US Pat. No. 9,710,007

INTEGRATED CIRCUIT CAPABLE OF PROVIDING A STABLE REFERENCE CURRENT AND AN ELECTRONIC DEVICE WITH THE SAME

ALi Corporation, Hsinchu...

1. An integrated circuit, comprising:
a voltage generator, generating a reference voltage proportional to an absolute temperature based on a predetermined value;
and

a current generator with a negative temperature coefficient, receiving the reference voltage and comprising an impedance element
with a positive temperature coefficient, the current generator generating a reference current, which is independent of temperature,
based on the impedance element and the reference voltage between two ends of the impedance element, wherein a data transmission
interface is connected to the current generator and generates an output voltage by using the reference current from the current
generator, the integrated circuit receives the output voltage and adjusts trimming data according to the output voltage, and
the voltage generator adjusts the reference voltage according to the trimming data to calibrate the reference current.

US Pat. No. 9,686,115

METHOD AND CIRCUIT FOR DETECTING TMCC SIGNAL

ALI CORPORATION, Hsinchu...

1. A method for detecting a Transmission and Multiplexing Configuration Control (TMCC) signal, adapted for a receiving device
of an Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) system, the receiving device receiving an ISDB-T signal
comprising a plurality of symbols, and sequentially extracting a plurality of TMCC pilots from each of the symbols to obtain
a reference bit of each symbol, the method comprising:
sequentially comparing the reference bits of the symbols with two synchronizing signals in the TMCC signal, and when the reference
bits of the Kth to the (K+15)th symbols are equal to one of the synchronizing signals, updating the reference bits of the Kth to the (K+15)th symbols as a first word-synchronous serial data, wherein K is a positive integer;

collecting the reference bits of the (K+16)th to the (K+202)th symbols and executing a parity check for the reference bits of the (K+19)th to the (K+120)th symbols by the reference bits of the (K+121)th to the (K+202)th symbols to generate a first parity checking result; and

determining whether the TMCC signal in the ISDB-T signal is detected according to the first parity checking result.

US Pat. No. 9,543,237

SEMICONDUCTOR PACKAGE STRUCTURE

ALI CORPORATION, Hsinchu...

1. A semiconductor package structure connected to a circuit board, comprising:
a lead frame, comprising:
a tray; and
a plurality of leads, wherein each lead has an inner lead, and two of the inner leads are different in height position;
a chip disposed on the tray and electrically connected to the circuit board through a plurality of bonding wires and the plurality
of leads; and

a molding compound encapsulating the chip and the inner lead of each lead.

US Pat. No. 10,027,468

ETHERNET PHYSICAL LAYER CIRCUIT AND CLOCK RECOVERY METHOD THEREOF

ALi Corporation, Hsinchu...

1. An Ethernet physical layer circuit, comprising:an analog-to-digital converter, sampling an analog input signal by using a sampling clock to generate a digital input signal;
a clock generator, coupled to the analog-to-digital converter, outputting the sampling clock to the analog-to-digital converter, and adjusting a phase of the sampling clock according to a phase control signal; and
a clock recovery circuit, coupled to the analog-to-digital converter and the clock generator, detecting a timing error of the digital input signal at a plurality of refresh stages of a low power idle mode to obtain phase adjustment information, and generating the phase control signal based on the phase adjustment information at a plurality of quiet stages of the low power idle mode, such that the clock generator adjusts the phase of the sampling clock in response to receiving the phase control signal in the quiet stages.

US Pat. No. 9,825,732

SIGNAL PROCESSING METHOD AND CIRCUIT FOR SUPPRESSING CO-CHANNEL INTERFERENCE

ALI CORPORATION, Hsinchu...

1. A signal processing method for suppressing co-channel interference, adapted to a receiver in an Orthogonal Frequency-Division
Multiplexing (OFDM) system, the signal processing method comprising:
receiving an OFDM signal comprising a plurality of symbols by the receiver, wherein each symbol comprises K subcarriers and
each of the K subcarriers is a non-data subcarrier or a data subcarrier;

processing each non-data subcarrier and each data subcarrier related to each of the plurality of the symbols to obtain a first
comparison result corresponding to each subcarrier;

generating a N×K error matrix according to the first comparison results, and respectively executing a summation operation
for N elements in each column of the N×K error matrix to obtain a sum related to the N elements in each column of the N×K
error matrix; and

respectively comparing the sum related to the N elements in each column of the N×K error matrix with M first threshold values
to obtain a second comparison result corresponding to each column of the N×K error matrix, and determining whether the subcarriers
are affected by co-channel interference according to each second comparison result;

wherein K and M are both positive integers, and N is a variable and varies with different settings of the receiver.

US Pat. No. 9,639,651

ROUTING METHOD FOR INTEGRATED CIRCUIT AND RELATED INTEGRATED CIRCUIT

ALI Corporation, Hsinchu...

1. A routing method for an integrated circuit, comprising:
determining a signal path between a signal source and a corresponding receiving terminal according to a routing structure
of a system power/ground mesh;

placing at least one buffer along the signal path for buffering a signal generated by the signal source;
disposing a deep well region corresponding to the at least one buffer in a substrate of the integrated circuit;
determining a routing structure of an independent power/ground mesh that is independent from the system power/ground mesh
according to the signal path; and

performing a routing process according to the determined routing structure of the independent power/ground mesh and the signal
path;

wherein the system power/ground mesh and the independent power/ground mesh are respectively coupled to different voltage sources;
and at least one portion of the routing structure of the independent power/ground mesh is aligned with the signal path.

US Pat. No. 9,852,038

DEBUGGING SYSTEM AND DEBUGGING METHOD OF MULTI-CORE PROCESSOR

ALi Corporation, Hsinchu...

1. A debugging system of a multi-core processor, comprising:
a debugging host comprising a debugger executed by a processor of the debugging host;
a target processor comprising a plurality of cores; and
a mapping and protocol conversion device being connected between the debugging host and the target processor, identifying
a core architecture of each of the cores, and mapping each of the cores respectively to at least one thread of at least one
process of the debugger according to the core architecture to which each of the cores belongs, wherein the mapping and protocol
conversion device comprises:

a control server being connected to the debugger through a network interface, controlling the cores being mapped to the threads
of the processes; and

a protocol conversion interface device being connected to the control server through a first transmission interface, and being
connected to the target processor through a second transmission interface,

wherein the protocol conversion interface device converts data received from the control server into a signal conforming to
a protocol standard of the second transmission interface,

wherein the debugger executes a debugging procedure for the target processor to debug the cores of the target processor synchronously
through executing the process and the thread corresponded to each of the cores by the processor.

US Pat. No. 9,806,877

CALIBRATION METHOD AND CALIBRATION CIRCUIT

ALI CORPORATION, Hsinchu...

1. A calibration method, used to calibrating mismatches between a first signal path and a second signal path of a transmitter,
wherein a delay chain is configured in the first signal path to delay a signal transmitted through the first signal path,
and a finite impulse response filter is configured in the second signal path to compensate the mismatches between the first
signal path and the second signal path, the calibration method comprising:
inputting a multiple-frequency signal to a digital-to-analog converter configured in both of the first signal path and the
second signal path, and respectively inputting an output of the digital-to-analog converter in the first signal path and an
output of the digital-to-analog converter in the second signal path to a low-pass filter configured in both of the first signal
path and the second signal path, to generate a first test signal corresponding to the first signal path and a second test
signal corresponding to the second signal path;

respectively sampling the first test signal and the second test signal by at least one analog-to-digital converter, and respectively
feeding sampling results generated by the analog-to-digital converter back to the delay chain and the finite impulse response
filter, to generate a delay signal and a compensated output signal; and

executing a subtraction operation for the delay signal and the compensated output signal to obtain a first calibration coefficient
related to the finite impulse response filter in the second signal path, and calibrating a plurality of tap coefficients of
the finite impulse response filter by the first calibration coefficient, such that the calibrated finite impulse response
filter in the second signal path compensates the mismatches between the first signal path and the second signal path of the
transmitter.

US Pat. No. 9,503,779

NETWORK CONNECTION CONFIGURATION METHOD FOR MULTIMEDIA PLAYER AND RELATED COMPUTER SYSTEM

ALI Corporation, Hsinchu...

1. A network connection configuration method for a multimedia player comprising:
establishing a Wireless Fidelity (Wi-Fi) connection between a mobile device and a network connection device, such that the
mobile device obtains a service set identification (SSID) and a password thereof of the network connection device;

utilizing an image capture module of the mobile device to capture an optical image corresponding to the multimedia player,
so as to establish a Wi-Fi Direct connection between the mobile device and the multimedia player; and

establishing another Wi-Fi connection between the multimedia player and the network connection device according to the Wi-Fi
connection between the mobile device and the network connection device as well as the Wi-Fi Direct connection between the
mobile device and the multimedia player;

wherein the optical image comprises a personal information number (PIN) utilized for the Wi-Fi Direct connection, such that
the PIN of the optical image is utilized for establishing the Wi-Fi Direct connection between the mobile device and the multimedia
player after the PIN corresponding to the multimedia player is captured, and the SSID and the password thereof of the network
connection device is correspondingly transmitted to the multimedia player to establish the Wi-Fi connection between the multimedia
player and the network connection device.

US Pat. No. 10,033,358

BUFFER CIRCUIT AND VOLTAGE GENERATOR USING THE SAME

ALI CORPORATION, Hsinchu...

1. A buffer circuit, having an input terminal for receiving an input signal and an output terminal for providing an output signal, wherein the buffer circuit comprises:a transistor cascode circuit biased at a first voltage and receiving the input signal;
a latch circuit biased at a second voltage, wherein the voltage level of the second voltage is negative;
a first transistor and a second transistor coupled between the transistor cascode circuit and the latch circuit, wherein a gate terminal of the first transistor is coupled to a gate terminal of the second transistor; and
a voltage generator providing a biasing voltage to the gate terminals of the first transistor and the second transistor according to the second voltage;
wherein the voltage generator adjusts a voltage level of the biasing voltage dynamically according to a voltage level of the second voltage; and the biasing voltage is at a first level when the buffer circuit is initially turned on, and the biasing voltage is at a second level when the buffer circuit enters a steady state.

US Pat. No. 10,090,993

PACKAGED CIRCUIT

ALi Corporation, Hsinchu...

1. A packaged circuit, comprising:a digital controller, parallel outputting digital data in parallel via a parallel data channel, wherein the digital data comprises a plurality of data bits;
a port physical layer, comprising a clock generator, and outputting a data signal according to the data bits, wherein the clock generator outputs a clock signal to the digital controller; and
a digital coding circuit, coupled between the digital controller and the port physical layer, receiving the digital data and the clock signal, generating a plurality of clock bits, and outputting the clock bits to the port physical layer,
wherein the port physical layer converts the clock bits into an output clock and outputs the output clock,
wherein the port physical layer comprises a first output-port-circuit and a second output-port-circuit, and the digital coding circuit outputs the clock bits to the first output-port-circuit or the second output-port-circuit according to an operating state of the packaged circuit.

US Pat. No. 9,762,336

CALIBRATION METHOD AND CALIBRATION CIRCUIT

ALI CORPORATION, Hsinchu...

7. A calibration circuit, used to calibrate mismatches between a first signal path and a second signal path of a receiver,
wherein a delay chain is configured in the first signal path of the receiver to delay a signal transmitted through the first
signal path, and a finite impulse response filter is configured in the second signal path of the receiver to compensate the
mismatches between the first signal path and the second signal path, the calibration circuit comprising:
a frequency mixing signal generating unit, inputting a multiple-frequency signal to a first mixer in the first signal path
and to a second mixer in the second signal path, to generate a first frequency mixing signal corresponding to the first mixer
and a second frequency mixing signal corresponding to the second mixer;

a test signal generating unit, utilizing a first switching circuit to select from the first frequency mixing signal and the
second frequency mixing signal, respectively inputting a selection result generated by the first switching circuit and the
second frequency mixing signal to a low-pass filter in the first signal path and to a low-pass filter in the second signal
path, and respectively inputting an output of the low-pass filter in the first signal path and an output of the low-pass filter
in the second signal path to an analog-to-digital converter in the first signal path and an analog-to-digital converter in
the second signal path, to generate a first test signal corresponding to the first signal path and a second test signal corresponding
to the second signal path; and

a calibration unit, respectively inputting the first test signal and the second test signal to the delay chain and the finite
impulse response filter to generate a delay signal and a compensated output signal, executing a subtraction operation between
the delay signal and the compensated output signal to obtain a first calibration coefficient related to the finite impulse
response filter in the second signal path, and calibrating a plurality of tap coefficients of the finite impulse response
filter by the first calibration coefficient, such that the calibrated finite impulse response filter in the second signal
path compensates the mismatches between the first signal path and the second signal path.

US Pat. No. 9,952,828

WLAN PLAYER AND WLAN SYSTEM FOR SYNCHRONIZING PLAYING SPEED AND METHOD THEREOF

ALi Corporation, Hsinchu...

1. A wireless local area network (WLAN) player for synchronizing playing speed, comprising:a speed adjusting module, adapted to adjust a speed that the wireless local area network player plays a medium according to a first playing-progress value and a first clock value of another WLAN player, so as to synchronously play the medium together with said another WLAN player,
wherein the first playing-progress value is a progress that said another WLAN player plays the medium, and the first clock value is a self-WLAN-clock value of said another WLAN player,
wherein the WLAN player has a second playing-progress value and a second clock value, the second playing-progress value is a progress that the WLAN player plays the medium, and the second clock value is a self-WLAN-clock value of the WLAN player,
wherein the speed adjusting module is configured to:
calculate a progress difference between the second playing-progress value and the first playing-progress value;
calculate a time difference between the second clock value and the first clock value;
calculate a specific progress difference according to the progress difference and the time difference; and
adjust the speed that the WLAN player plays the medium according to the specific progress difference.

US Pat. No. 10,050,667

NETWORK CONNECTION DEVICE AND CABLE STATUS DETECTION METHOD

ALi Corporation, Hsinchu...

1. A network connection device comprising:an interface module, configured to connect a connection cable;
a physical layer transmission circuit, coupled to the interface module and configured to send signal to the connection cable or receive signal from the connection cable through the interface module; and
a cable status detection module, coupled to the physical layer transmission circuit and the interface module,
wherein the cable status detection module is configured to receive a notification notifying that the physical layer transmission circuit is in a disable state,
wherein the cable status detection module is configured to detect a status of the connection cable when the physical layer transmission circuit is in the disable state and generate a detection result of the connection cable,
wherein the cable status detection module comprises a reception circuit which is coupled to the interface module and configured to receive a first feedback signal from the connection cable in response to a first pulse signal,
wherein the reception circuit comprises:
a direct current elimination circuit, configured to execute direct current bias elimination on the first feedback signal; and
a channel compensation circuit, coupled to the direct current elimination circuit and configured to execute channel compensation on the first feedback signal.

US Pat. No. 9,832,459

OUTPUT CIRCUIT AND METHOD FOR DETECTING WHETHER LOAD CONNECTED TO CONNECTION PORT CORRESPONDING TO OUTPUT CIRCUIT

ALI Corporation, Hsinchu...

1. An output circuit for generating an output to an output terminal that is coupled to a connecting port, comprising:
a level adjustment circuit, coupled to the output terminal, for generating at least one adjusted signal according to a first
voltage signal at the output terminal in a first period and a second voltage signal at the output terminal in a second period;
and

a determination circuit, coupled to the level adjustment circuit, for generating a determination signal according to the at
least one adjusted signal, wherein the determination signal indicates whether a load is connected to the connecting port.

US Pat. No. 9,935,606

SYSTEM ON CHIP AND CORRECTION METHOD OF TERMINATION IMPEDANCE ELEMENT THEREOF

ALi Corporation, Hsinchu...

1. A system on chip, comprising:a pad, coupled to an external dynamic random access memory chip, wherein the external dynamic random access memory chip comprises a corrected termination impedance element;
a first termination impedance element, coupled to the pad;
a correction circuit, coupled to a control terminal of the first termination impedance element, to control an impedance value of the first termination impedance element, wherein during an initialization period, the correction circuit corrects the impedance value of the first termination impedance element according to an impedance value of the corrected termination impedance element; and
a second termination impedance element, wherein a first terminal of the second termination impedance element is coupled to the pad, a second terminal of the second termination impedance element is coupled to a first voltage rail line of the system on chip, and a control terminal of the second termination impedance element is coupled to the correction circuit;
wherein during the initialization period, the correction circuit turns off the second termination impedance element, and corrects the impedance value of the first termination impedance element according to the impedance value of the corrected termination impedance element;
wherein during the initialization period, the correction circuit corrects an impedance value of the second termination impedance element according to the impedance value of the first termination impedance element after correcting the impedance value of the first termination impedance element is completed; and
wherein the correction circuit comprises:
a first reference impedance element, wherein a first terminal of the first reference impedance element is coupled to a common node, and a second terminal of the first reference impedance element is coupled to a second voltage rail line of the system on chip, wherein an impedance value of the first reference impedance element and the impedance value of the first termination impedance element are controlled correlatively; and
a second reference impedance element, wherein a first terminal of the second reference impedance element is coupled to the common node, and a second terminal of the second reference impedance element is coupled to the first voltage rail line of the system on chip, wherein an impedance value of the second reference impedance element and the impedance value of the second termination impedance element are both controlled correlatively.

US Pat. No. 10,008,114

VEHICLE SEARCHING SYSTEM AND METHOD FOR SEARCHING VEHICLE

ALi Corporation, Hsinchu...

1. A vehicle searching system, comprising:a vehicle electronic device, capturing a plurality of images along a moving direction of a vehicle, and providing a positioning information of the vehicle and determining whether the vehicle sends a parking stall signal, wherein the vehicle electronic device also comprises
a driving event data record module, configured to capture the plurality of images along the moving direction of the vehicle,
a positioning module, configured to provide the positioning information of the vehicle, and
a vehicle control circuit, configured to send the parking stall signal when the vehicle is stalled;
a data storage device, communicating with the vehicle electronic device, and configured to store data, wherein the driving event data record module selects at least one parking image from the plurality of images for transmitting to the data storage device when receiving the parking stall signal, and the positioning module provides the positioning information of the vehicle to the data storage device when receiving the parking stall signal; and
a mobile device, communicating with the data storage device,
wherein the vehicle electronic device receives the parking stall signal to select the at least one parking image from the plurality of images and obtain the positioning information of the vehicle, and transmits the at least one parking image and the positioning information to the data storage device for storage, and
the mobile device obtains the at least one parking image and the positioning information from the data storage device, and displays the at least one parking image and presents the positioning information in a graphical interface.

US Pat. No. 10,057,088

TERMINAL CIRCUIT AND OUTPUT STAGE CIRCUIT HAVING THE SAME

ALI CORPORATION, Hsinchu...

1. A terminal circuit configured between a transmitter and an external circuit, wherein the transmitter provides a differential signal to the external circuit, and the terminal circuit comprises:a first switch, wherein a first end of the first switch is biased by a first voltage, the first switch is controlled by a first control signal and the first voltage is provided by the transmitter;
a first resistor and a second resistor, wherein a first end of the first resistor and a first end of the second resistor receive the differential signal;
a second switch coupled between a second end of the first switch and a second end of the first resistor and controlled by a second control signal; and
a third switch coupled between the second end of the first switch and a second end of the second resistor and controlled by a third control signal;
wherein when the transmitter operates in a power-off mode, a voltage level of the first voltage is in ground level, and the first control signal, the second control signal and the third control signal are disabled to turn off the first switch, the second switch and the third switch.

US Pat. No. 10,194,194

TUNER CIRCUIT WITH ZERO POWER LOOP THROUGH

ALi Corporation, Hsinchu...

15. A video broadcasting system, comprising:a first tuner, receiving a radio frequency signal from a transceiver, comprising a first terminal, a second terminal, an internal resistor connected between the second terminal and a ground terminal, and a loop through circuit connected between the first terminal and second terminal, and delivering the radio frequency signal received from the first terminal to the second terminal via the loop through circuit; and
a second tuner, comprising an input terminal connected to the second terminal of the first tuner, the second tuner receives the radio frequency signal from the first tuner and provides a voltage to the first tuner through the input terminal, the second tuner is connected immediately subsequent to the first tuner; and
an external resistor, directly connected between the first tuner and the second tuner, wherein the internal resistor and the external resistor generate a divided voltage based on the voltage provided by the second tuner,
wherein the loop through circuit of the first tuner comprises:
a logic control, connected to the internal resistor to obtain the divided voltage as operational power and in response to detecting of internal power supply of the first tuner not being available or a low noise amplifier of the first tuner being disabled, outputting a control signal for providing a loop through path for delivering the radio frequency signal received from the transceiver to the second tuner according to the control signal.

US Pat. No. 10,249,705

CAPACITOR ARRAY STRUCTURE

ALi Corporation, Hsinchu...

1. A capacitor array structure, comprising:N capacitor units each comprising an upper electrode and a lower electrode,
wherein the upper electrode and the lower electrode comprise a plurality of metal portions, and the metal portions are patterned,
wherein the capacitor units are arranged adjacent to one another along a first axial direction to form a capacitor series, and an ith capacitor unit of the capacitor units comprises:
a first metal layer comprising a first metal portion of the lower electrode;
a second metal layer disposed above the first metal layer and comprising a second metal portion of the lower electrode and a first metal portion of the upper electrode; and
a third metal layer disposed above the second metal layer and comprising a third metal portion of the lower electrode, a fourth metal portion of the lower electrode, and a second metal portion of the upper electrode,
wherein i is a positive integer not larger than N and N is a positive integer, wherein i is larger than or equal to 2,
wherein the second metal portion of the lower electrode has an opening, and a side of the first metal portion of the upper electrode is exposed in the opening, such that the side of the first metal portion of the upper electrode is adjacent to the lower electrode of an (i-1)th capacitor unit.