US Pat. No. 9,857,532

SEMICONDUCTOR DEVICE PACKAGES

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device comprising:
a substrate including a surface and a sidewall;
a passivation layer on the surface; and
an optical element in the substrate and exposed from the sidewall of the substrate,
wherein the sidewall of the substrate is inclined such that the sidewall of the substrate and the surface of the substrate
form an internal angle of approximately 87 degrees to approximately 89 degrees, and

wherein the passivation layer comprises a curved sidewall adjacent to the sidewall of the substrate.

US Pat. No. 9,484,307

FAN-OUT WAFER LEVEL PACKAGING STRUCTURE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:
a first die comprising a first pad and a first passivation layer;
a second die comprising a second pad and a second passivation layer, wherein the first die has a first sidewall and the second
die has a second sidewall;

an encapsulant surrounding the first die and the second die and comprising a first surface;
a dielectric layer covering at least a portion of the first passivation layer and at least a portion of the second passivation
layer, and further covering the encapsulant between the first die and the second die, wherein the dielectric layer comprises:

a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant; and
a third surface opposite to the second surface; and
a redistribution layer electrically connecting to the first pad and the second pad and disposed above the third surface of
the dielectric layer;

wherein a first roughness of the first surface of the encapsulant is greater than a second roughness of the third surface
of the dielectric layer.

US Pat. No. 9,319,001

AMPLIFIER CIRCUIT, BIASING BLOCK WITH OUTPUT GAIN COMPENSATION THEREOF, AND ELECTRONIC APPARATUS

Advanced Semiconductor En...

1. An amplifier circuit, comprising:
an amplifier block, configured to receive an input signal, and amplify the input signal to generate an output signal; and
a biasing block, coupled to the amplifier block, configured to provide biasing voltages to bias the amplifier block, and compensate
an output gain of the amplifier block before the output gain of the amplifier block is compressed, so as to extend a P1 dB
compression point of the amplifier block, wherein the biasing current are substantially independent to temperature and/or
system voltage variation;

wherein the biasing block comprises:
a DC biasing circuit, coupled to the amplifier block, to provide the biasing voltages to bias the amplifier block; and
an output gain compensation circuit, coupled to the amplifier block and the DC biasing circuit, to receive the biasing voltages
and a feedback signal related to the output signal, wherein when an input power of the input signal increases to a specific
level, the feedback signal indicates the output gain compensation circuit to compensate the output gain of the amplifier block;

wherein the DC biasing circuit comprises four transistors to form a Wilson current mirror.

US Pat. No. 9,955,590

REDISTRIBUTION LAYER STRUCTURE, SEMICONDUCTOR SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE, CHIP STRUCTURE, AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A redistribution layer structure, comprising:a dielectric layer comprising an upper portion and a lower portion, the lower portion of the dielectric layer defining at least one trench, and the upper portion of the dielectric layer comprising an anti-plating layer disposed on a surface of the lower portion of the dielectric layer and defining an opening; and
a conductive material plated in the trench within the opening,
wherein the anti-plating layer does not extend over the trench, the anti-plating layer includes a hydrophobic material, and the lower portion of the dielectric layer defining the trench is hydrophilic.

US Pat. No. 9,269,673

SEMICONDUCTOR DEVICE PACKAGES

Advanced Semiconductor En...

1. A semiconductor device package comprising:
a substrate having a first surface, a second surface opposite to the first surface, and a lateral surface extending between
the first and second surfaces;

at least one component mounted on the first surface of the substrate;
a package body disposed on the first surface of the substrate and covering the component;
a first conductive layer covering the package body and at least a portion of the substrate;
a first shielding layer covering the first conductive layer, the first shielding layer having a first thickness and comprising
a high conductivity material;

a second shielding layer covering the first shielding layer, the second shielding layer having a second thickness and comprising
a high permeability material, a ratio of the first thickness to the second thickness being in a range of 0.2 to 3; and

a second conductive layer covering the second shielding layer.

US Pat. No. 9,117,697

SEMICONDUCTOR SUBSTRATE AND METHOD FOR MAKING THE SAME

Advanced Semiconductor En...

1. A manufacturing method of a semiconductor substrate, comprising:
providing an embedded circuit substrate, the embedded circuit substrate comprising an insulation layer, a first circuit layer
and a plurality of conductive vias, wherein the insulation layer has a first surface and a second surface, the first circuit
layer is embedded in the first surface of the insulation layer, and exposed from the first surface of the insulation layer,
and the conductive vias penetrate through the insulation layer and contact the first circuit layer;

forming a photoresist layer on the first circuit layer, wherein the photoresist layer has a plurality of openings, and the
openings expose part of the first circuit layer; and

forming a plurality of bumps directly on the exposed first circuit layer.

US Pat. No. 9,443,921

SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR MANUFACTURING PROCESS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:
a first dielectric layer having a first surface and a second surface opposite to the first surface;
a die pad within the first dielectric layer;
an active component within the first dielectric layer and disposed on the die pad;
a plurality of first metal bars disposed on the first surface of the first dielectric layer, the plurality of first metal
bars being substantially parallel to each other, and at least one of the plurality of first metal bars being electrically
connected to the active component;

a plurality of second metal bars disposed on the second surface of the first dielectric layer, the plurality of second metal
bars being substantially parallel to each other; and

a plurality of through vias penetrating the first dielectric layer and connecting each of the plurality of first metal bars
to a corresponding second metal bar.

US Pat. No. 9,420,695

SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure comprising:
a first dielectric layer having a first surface and a second surface opposite the first surface;
a second dielectric layer having a first surface and a second surface opposite the first surface, the second surface of the
first dielectric layer being attached to the first surface of the second dielectric layer;

a component within the second dielectric layer comprising at least two electrical contacts, the electrical contacts being
adjacent to the second surface of the first dielectric layer;

a first patterned conductive layer within the first dielectric layer and adjacent to the first surface of the first dielectric
layer;

at least two first conductive vias penetrating the first dielectric layer and electrically connecting the electrical contacts
with the first patterned conductive layer;

a second conductive via formed in the first dielectric layer, the second conductive via having a top surface and a bottom
surface, the second conductive via tapering from the top surface to the bottom surface so that a width of the top surface
is greater than a width of the bottom surface; and

a third conductive via formed in the second dielectric layer, the third conductive via having a top surface and a bottom surface,
the third conductive via tapering from the bottom surface to the top surface so that a width of the top surface is less than
a width of the bottom surface, the top surface of the third conductive via being joined to the bottom surface of the second
conductive via,

wherein a height of the third conductive via is greater than a height of the second conductive via.

US Pat. No. 9,089,268

NEURAL SENSING DEVICE AND METHOD FOR MAKING THE SAME

Advanced Semiconductor En...

1. A neural sensing device, comprising:
a base having an active surface and a backside surface;
an integrated circuit portion disposed on the active surface of the base; and
a plurality of microprobes protruding from the backside surface of the base, each of the microprobes having a conductive via
disposed therein and electrically connected to the integrated circuit portion;

wherein each of the microprobes has a probe body and an isolation layer, wherein the probe body protrudes from the backside
surface of the base, the conductive via penetrates through the probe body, and the isolation layer covers the probe body and
has an opening to expose a tip of the conductive via.

US Pat. No. 10,074,622

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a substrate including a first surface;
a first package body encapsulating the first surface of the substrate;
a permeable element including a first portion disposed on the first surface of the substrate and a second portion disposed on the first package body; and
a coil within the first package body,
wherein the first portion of the permeable element and the second portion of the permeable element are separated by the first package body.

US Pat. No. 9,426,891

CIRCUIT BOARD WITH EMBEDDED PASSIVE COMPONENT AND MANUFACTURING METHOD THEREOF

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device substrate, comprising:
a first dielectric layer comprising a body portion and a wall portion protruded from a first surface of the body portion,
the wall portion having an end;

a second dielectric layer having a first surface and an opposing second surface, the first surface of the second dielectric
layer being adjacent to the first surface of the body portion, the second dielectric layer surrounding the wall portion, the
end of the wall portion extending beyond the second surface of the second dielectric layer;

an electronic component comprising a first electrical contact and a second electrical contact, at least a part of the electronic
component being surrounded by the wall portion;

a first patterned conductive layer embedded in the second surface of the second dielectric layer; and
a second patterned conductive layer disposed on the second surface of the second dielectric layer and an exposed surface of
the first patterned conductive layer, wherein the second patterned conductive layer is aligned with the first electrical contact,
the second electrical contact and the end of the wall portion.

US Pat. No. 9,148,088

RF STACKED POWER AMPLIFIER BIAS METHOD

Advanced Semiconductor En...

1. A RF stacked power amplifier, comprising:
a voltage-dividing circuit, receiving a system voltage and dividing the system voltage so as to output a first reference partial
voltage and a second reference partial voltage;

a negative feedback bias circuit, electrically connected to the voltage-dividing circuit so as to receive the second reference
partial voltage, the negative feedback bias circuit receiving a negative feedback reference voltage and correspondingly outputting
a second bias reference voltage according to a result of comparing the second reference partial voltage and the negative feedback
reference voltage;

a current source circuit, electrically connected to the voltage-dividing circuit so as to receive the first reference partial
voltage, the current source circuit determining a bias reference current according to the first reference partial voltage;
and

a stacked amplifying circuit, electrically connected to the current source circuit and the negative feedback bias circuit,
the stacked amplifying circuit outputting the negative feedback reference voltage and determining an operation bias point
according to a first bias reference voltage and the bias reference current;

wherein in AC mode the stacked amplifying circuit receives and amplifies a RF input signal and correspondingly outputs a RF
output signal.

US Pat. No. 9,508,671

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:
a semiconductor element having a surface, the semiconductor element including at least one bonding pad disposed adjacent to
the surface;

two pillar structures disposed on the one bonding pad; and
an insulation layer disposed adjacent to the surface of the semiconductor element, wherein the insulation layer defines two
openings, each of the two openings exposing a portion of the one bonding pad, and the two pillar structures are disposed in
respective ones of the two openings;

wherein the two pillar structures are symmetric and formed of a same material.

US Pat. No. 9,496,238

SLOPED BONDING STRUCTURE FOR SEMICONDUCTOR PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A bonding structure, comprising:
a substrate, having a top surface and comprising at least one bonding pad, wherein the bonding pad is disposed adjacent to
the top surface of the substrate and has a sloped surface; and

a semiconductor element, comprising at least one pillar;
wherein each pillar is bonded to a portion of the sloped surface of a corresponding one of the at least one bonding pad, and
a gap is formed between a sidewall of the pillar and the sloped surface of the corresponding bonding pad;

wherein the substrate further comprises a first insulation layer disposed on the top surface thereof and between the bonding
pads, and the semiconductor element further comprises a second insulation layer between the pillars, wherein the first insulation
layer contacts the second insulation layer.

US Pat. No. 9,166,530

LOW NOISE AMPLIFIER AND RECEIVER

Advanced Semiconductor En...

1. A low noise amplifier, comprising:
a current mirror circuit, used for providing a mapping current;
a bias circuit, electrically connected to the current mirror circuit, the bias circuit used for receiving a mapping current
and outputting a first bias voltage and a second bias voltage according to the mapping current;

a cascode amplifying circuit, electrically connected to the bias circuit so as to respectively receive the first bias voltage
and the second bias voltage, and accordingly to work at an operation bias point, the cascode amplifying circuit used for receiving
and amplifying a RF input signal and accordingly outputting a RF output signal; and

a power gain compensating circuit, electrically connected between the cascode amplifying circuit and the current mirror circuit,
the power gain compensating circuit used for receiving the RF output signal and accordingly outputting a gain compensating
signal to the current mirror circuit so as to dynamically adjust current value of the mapping current, further compensating
power gain of the low noise amplifier in order to increase linearity.

US Pat. No. 9,141,125

BANDGAP REFERENCE VOLTAGE GENERATING CIRCUIT AND ELECTRONIC SYSTEM USING THE SAME

Advanced Semiconductor En...

1. A bandgap reference voltage generating circuit, used for providing a reference voltage, the bandgap reference voltage generating
circuit, comprising:
a four-terminal current source circuit, electrically connected to a first system voltage, wherein when the first system voltage
is larger than a threshold voltage value, a first voltage, a second voltage and a first current outputted from the four-terminal
current source circuit are independent of variation of the first system voltage;

a regulator circuit, electrically connected to the four-terminal current source circuit, wherein when the regulator circuit
receives the first voltage and the second voltage, and when the first system voltage is larger than the threshold voltage
value, the reference voltage outputted from the regulator circuit is independent of variation of the first system voltage
via voltage difference steadily between the first voltage and the second voltage; and

a temperature-compensating circuit, electrically connected to the four-terminal current source circuit and the regulator circuit,
wherein the temperature-compensating circuit receives the first current and compensates a temperature curve of the reference
voltage outputted from the regulator circuit.

US Pat. No. 9,397,074

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

Advanced Semiconductor En...

1. A semiconductor device package, comprising:
a first substrate having a top surface;
a first set of electrical components disposed on the top surface of the first substrate;
at least one stud having a top surface and a bottom surface, the bottom surface of the stud disposed on the top surface of
the first substrate;

a tapering electrical interconnection having a top surface and a bottom surface, the bottom surface of the electrical interconnection
being disposed at the top surface of the stud, a width of the stud is greater than or equal to a width of the bottom surface
of the electrical interconnection; and

a first package body disposed on the top surface of the first substrate, encapsulating the first set of electrical components,
the stud and a portion of the electrical interconnection, the first package body exposing the top surface of the electrical
interconnection.

US Pat. No. 9,373,601

SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A method of making a semiconductor substrate, comprising:
providing a substrate, the substrate comprising:
a first patterned metal layer;
a second patterned metal layer spaced from the first patterned metal layer;
a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer and covering the
second patterned metal layer, wherein the dielectric layer defines first openings exposing the second patterned metal layer,
and the dielectric layer further defines a via opening extending from the first patterned metal layer to the second patterned
metal layer; and

a conductive material disposed in the via opening and electrically connecting the first patterned metal layer to the second
patterned metal layer; and

providing a carrier layer on the dielectric layer, wherein the carrier layer defines second openings exposing the second patterned
metal layer.

US Pat. No. 9,343,333

WAFER LEVEL SEMICONDUCTOR PACKAGE AND MANUFACTURING METHODS THEREOF

Advanced Semiconductor En...

1. A method of forming a semiconductor package, the method comprising:
providing a semiconductor die having an active surface;
placing an interposer element adjacent to the die, the interposer element having an upper surface and a lower surface, the
interposer element having at least one first conductive via extending to the lower surface;

encapsulating portions of the semiconductor die and portions of the interposer element with an encapsulant such that the active
surface of the semiconductor die, the lower surface of the interposer element, and portions of the encapsulant form a lower
substantially coplanar surface; and

forming a lower redistribution layer on the lower substantially coplanar surface, the lower redistribution layer electrically
connecting the interposer element to the active surface of the semiconductor die.

US Pat. No. 9,172,131

SEMICONDUCTOR STRUCTURE HAVING APERTURE ANTENNA

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor structure comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a circuit portion formed on the first surface of the substrate and comprising a wave guiding slot and a microstrip line overlapped
with the wave guiding slot;

a chip disposed on the circuit portion wherein the microstrip line is positioned in the circuit portion outside a footprint
of the chip; and

an antenna formed on the second surface of the substrate and overlapped with the wave guiding slot.

US Pat. No. 10,096,578

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package device, comprising:a substrate;
an electronic component disposed on the substrate, the electronic component having a first surface adjacent to the substrate and a second surface opposite to the first surface, wherein the second surface has at least five edges; and
a package body encapsulating the electronic component and exposing the second surface of the electronic component.

US Pat. No. 9,960,136

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:a first circuit layer;
a copper pillar disposed adjacent to the first circuit layer;
a second circuit layer comprising an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium; and
a solder layer disposed between the copper pillar and the surface finish layer, the solder layer comprising a first intermetallic compound (IMC) and a second IMC, wherein the first IMC comprises a combination of two or more of copper, nickel and tin, the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both, the first IMC comprises a top layer and a bottom layer, and materials of the top layer and the bottom layer are the same.

US Pat. No. 9,812,387

SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor substrate, comprising:
a first dielectric structure having a first surface and a second surface opposite the first surface;
a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface
faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth
surface, wherein a cavity is defined by the through hole and the first dielectric structure;

a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and
a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including
at least one conductive trace;

wherein the first dielectric structure defines at least one opening to expose a portion of the second patterned conductive
layer.

US Pat. No. 9,484,313

SEMICONDUCTOR PACKAGES WITH THERMAL-ENHANCED CONFORMAL SHIELDING AND RELATED METHODS

Advanced Semiconductor En...

1. A semiconductor package, comprising:
a substrate having an upper surface, a lower surface opposite the upper surface, and a lateral surface adjacent to a periphery
of the substrate and extending between the upper surface and the lower surface;

a grounding segment disposed adjacent the periphery of the substrate;
a die disposed adjacent to the upper surface of the substrate, wherein the die has an active surface and a backside surface
opposite the active surface;

a package body disposed on the upper surface of the substrate and at least partially encapsulating the die, wherein the package
body has an upper surface and at least one side surface, and wherein the backside surface of the die is exposed from the upper
surface of the package body;

a first metal layer disposed on the upper surface of the package body and the backside surface of the die, wherein the first
metal layer has an extending portion disposed on the at least one side surface of the package body and contacting the upper
surface of the substrate, and wherein the extending portion of the first metal layer has an outer surface coplanar with the
lateral surface of the substrate; and

a second metal layer disposed over the first metal layer and the lateral surface of the substrate, and electrically connected
to the grounding segment;

wherein the backside surface of the die is substantially coplanar with the upper surface of the package body.

US Pat. No. 9,443,813

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:
a semiconductor die comprising a copper pillar;
a semiconductor element comprising an electrical contact and a surface finish layer disposed on the electrical contact, wherein
a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium; and

a solder layer disposed between the copper pillar and the surface finish layer, the solder layer comprising a first intermetallic
compound (IMC) and a second IMC, wherein the first IMC comprises a combination of two or more of copper, nickel and tin, and
the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.

US Pat. No. 9,406,552

SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIA AND MANUFACTURING PROCESS

Advanced Semiconductor En...

1. A semiconductor device, comprising:
a semiconductor chip including a plurality of conductive pads;
a package body at least partially encapsulating the semiconductor chip, the package body being a composite material which
includes resin and fillers and having at least one hole formed therein defining a hole sidewall which is partially defined
by portions of the fillers protruding from the resin and is of a first surface roughness value; and

at least one through package body via disposed in the hole, the via comprising a dielectric material disposed on the hole
sidewall of the hole and defining at least one bore having a bore sidewall which is of a second surface roughness value less
than the first surface roughness value.

US Pat. No. 9,236,356

SEMICONDUCTOR PACKAGE WITH GROUNDING AND SHIELDING LAYERS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:
a substrate including a lateral surface and a bottom surface;
a grounding layer buried in the substrate and extending horizontally in the substrate, wherein the grounding layer is separated
from the lateral surface of the substrate;

a grounding trace extending to the lateral surface of the substrate, wherein the grounding trace and the grounding layer are
disposed on different layers of the substrate;

a via formed between the grounding trace and the grounding layer to electrically connect the grounding trace and the grounding
layer;

a chip arranged on the substrate;
a package body enveloping the chip and including a lateral surface; and
a shielding layer covering the lateral surface of the package body and the lateral surface of the substrate, and electrically
connected to the grounding layer, wherein a bottom surface of the shielding layer is separated from the bottom surface of
the substrate.

US Pat. No. 9,171,792

SEMICONDUCTOR DEVICE PACKAGES HAVING A SIDE-BY-SIDE DEVICE ARRANGEMENT AND STACKING FUNCTIONALITY

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:
a substrate including a top surface;
a first die coupled to the top surface of the substrate;
a second die coupled to the top surface of the substrate;
a plurality of first connecting elements coupled to the top surface of the substrate;
a plurality of second connecting elements;
a package body covering the first die and the second die;
a plurality of first openings in the package body, the first openings exposing the first connecting elements; and
a plurality of second openings in the package body, the second openings exposing the second connecting elements;
wherein the first connecting elements are spaced by a first pitch P1, the second connecting elements are spaced by a second pitch P2, and the first pitch P1 is not equal to the second pitch P2.

US Pat. No. 9,065,389

RADIO FREQUENCY POWER AMPLIFIER WITH NO REFERENCE VOLTAGE FOR BIASING AND ELECTRONIC SYSTEM

ADVANCED SEMICONDUCTOR EN...

1. A radio frequency power amplifier, comprising:
a three-terminal current source circuit, receiving a first system voltage and accordingly outputting a first current and a
second current, wherein a source voltage exists between a first output terminal and a second terminal;

wherein the three-terminal current source circuit comprises: a first transistor, having a drain coupled to the first system
voltage; and a first resistor, having a terminal being the first output terminal coupled to a source of the first transistor
and outputting the first current, and another terminal being the second terminal coupled to a gate of the first transistor
and outputting the second current, wherein the source voltage exists between the two terminals of the first resistor;

a current mirror circuit, electrically connected to the three-terminal current source circuit, the current mirror circuit
receiving the first current and the second current and accordingly generating a bias current; and

an output-stage circuit, electrically connected to the current mirror circuit, the output-stage circuit receiving the bias
current so as to operate at an operation point;

wherein through the source voltage of the three-terminal current source circuit, when the first system voltage operates between
a first voltage and a second voltage, the output-stage circuit outputs an output current with temperature-compensation which
is stable with respect to changes of the first system voltage.

US Pat. No. 9,984,898

SUBSTRATE, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A substrate, comprising:a dielectric layer having a first surface and a second surface opposite to the first surface;
a first circuit layer disposed adjacent to the first surface of the dielectric layer, and including at least one trace and at least one first conductive element connected to the trace, wherein the first conductive element does not extend through the dielectric layer; and
at least one second conductive element extending through the dielectric layer, wherein an area of an upper surface of the second conductive element is substantially equal to an area of an upper surface of the first conductive element.

US Pat. No. 9,196,595

SEMICONDUCTOR BONDING STRUCTURE

Advanced Semiconductor En...

1. A semiconductor bonding structure, comprising:
a first pillar comprising a first metal;
a second pillar comprising the first metal;
an intermediate area, located between the first pillar and the second pillar, and comprising the first metal;
a first interface, located between the first pillar and the intermediate area, and comprising the first metal and an oxide
of a second metal, wherein the content percentage of the first metal in the first interface is less than that of the first
metal in the intermediate area; and

a second interface, located between the second pillar and the intermediate area, and comprising the first metal and the oxide
of the second metal, wherein the content percentage of the first metal in the second interface is less than that of the first
metal in the intermediate area.

US Pat. No. 9,123,981

TUNABLE RADIO FREQUENCY COUPLER AND MANUFACTURING METHOD THEREOF

Advanced Semiconductor En...

1. A tunable radio frequency (RF) coupler comprising:
an insulating layer;
a first transmission line; and
a second transmission line located corresponding to said first transmission line, wherein said insulating layer is disposed
between said first transmission line and said second transmission line, and said second transmission line comprises:

a plurality of segments separated from each other and arranged in alignment with an extending path of said first transmission
line, wherein at least two of said segments are electrically connected to each other through at least one wire.

US Pat. No. 9,070,793

SEMICONDUCTOR DEVICE PACKAGES HAVING ELECTROMAGNETIC INTERFERENCE SHIELDING AND RELATED METHODS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:
a substrate including a carrier surface;
a plurality of dies coupled to the carrier surface of the substrate and electrically connected to the substrate;
an electromagnetic interference (EMI) shield, including a connecting element and a shield layer that are discrete components,
the connecting element including a first end and a second end opposite the first end, wherein the first end has a larger,
lateral surface area than the second end;

a first grounding segment coupled to the carrier surface, wherein the second end of the connecting element is coupled to the
first grounding segment;

at least one second grounding segment disposed at a periphery of the substrate wherein the shield layer is coupled to the
at least one second grounding segment; and

a package body covering the dies and partially covering the first end of the connecting element, a portion of the first end
of the connecting element spaced from the substrate being exposed from the package body;

wherein the connecting element extends between adjacent ones of the dies, thereby dividing the semiconductor device package
into a plurality of compartments, with each compartment containing at least one of the dies; and

wherein the shield layer is disposed over the package body and the exposed portion of the first end of the connecting element.

US Pat. No. 9,653,656

LED PACKAGES AND RELATED METHODS

Advanced Semiconductor En...

1. A light-emitting diode (LED) package, comprising:
a lead frame including a die pad and at least one electrode, the at least one electrode being isolated from the die pad by
at least one gap, the die pad including first and second trenches located within the opening of the housing, both ends of
each of the first and second trenches opening into the at least one gap;

a first insulator partially encapsulating the lead frame such that a portion of an upper surface of the die pad and a portion
of the at least one electrode are exposed from the first insulator and the at least one gap and the first and second trenches
are at least partially filled by the first insulator;

an LED chip disposed on the exposed portion of the upper surface of the die pad and located between the first and second trenches;
wherein the die pad has a lower surface such that the lower surface is exposed to an exterior of the package, the exposed
lower surface being contiguous;

wherein the die pad includes at least one upper surface protrusion which is oriented towards the exterior of the package and
is partially encapsulated by the first insulator; and

wherein the at least one electrode has a lower surface and an upper surface such the lower surface is smaller than the upper
surface and the at least one electrode has an upper surface protrusion which is oriented towards an interior of the package
wherein the upper surface protrusion has a lower surface which is smaller than the at least one electrode lower surface.

US Pat. No. 9,224,707

SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND PROCESS FOR MANUFACTURING

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:
a package substrate, comprising:
a dielectric layer
a first circuit layer disposed on or in the dielectric layer;
a plurality of pillars disposed on the first circuit layer, wherein each of the pillars has a top surface adapted for making
external electrical connection, and the top surfaces of the pillars are substantially coplanar with each other;

a second circuit layer; and
a plurality of interconnection metals;
wherein the dielectric layer has a plurality of openings, and the interconnection metals are disposed in the openings of the
dielectric layer to connect the second circuit layer and the circuit layer;

a die attached to the package substrate; and
a molding compound encapsulating the die.

US Pat. No. 9,153,542

SEMICONDUCTOR PACKAGE HAVING AN ANTENNA AND MANUFACTURING METHOD THEREOF

Advanced Semiconductor En...

1. A semiconductor package comprising:
a first substrate including a ground layer;
an interposer disposed on an upper surface of the first substrate and having at least one opening;
a first die disposed in the at least one opening and coupled to the first substrate;
a second substrate coupled to the interposer, disposed over the first substrate and having an area less than an area of the
first substrate;

a second die disposed on a lower surface of the second substrate;
a third die embedded within the second substrate;
an inductor disposed on an upper surface of the second substrate wherein the inductor is electrically connected to the second
die and the third die;

a package body encapsulating portions of the first substrate, the interposer, the second substrate, the first die and the
second die, the package body having a lateral surface and an upper surface; and

a metal layer disposed on the lateral surface and the upper surface of the package body wherein the metal layer is electrically
connected to the first substrate and wherein the metal layer has voids that overlie the inductor.

US Pat. No. 9,947,635

SEMICONDUCTOR PACKAGE, INTERPOSER AND SEMICONDUCTOR PROCESS FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a first semiconductor device, comprising:
a first main body having a bottom surface;
at least one first columnar portion protruding from the bottom surface of the first main body; and
at least two first conductive layers disposed on side surfaces of the first columnar portion, wherein the first conductive layers do not physically contact each other; and
a second semiconductor device, comprising:
a second main body having a top surface facing the bottom surface of the first main body;
at least one second columnar portion protruding from the top surface of the second main body; and
at least two second conductive layers disposed on side surfaces of the second columnar portion, wherein the second conductive layers do not physically contact each other;
wherein the first conductive layers are electrically coupled to the second conductive layers.

US Pat. No. 9,129,954

SEMICONDUCTOR PACKAGE INCLUDING ANTENNA LAYER AND MANUFACTURING METHOD THEREOF

Advanced Semiconductor En...

1. A semiconductor package comprising:
a substrate;
a semiconductor chip disposed on the substrate;
a package body encapsulating the semiconductor chip and including an upper surface;
an antenna layer formed on the upper surface of the package body, the antenna layer including two antenna slot groups connected
together, wherein each antenna slot group includes a first wave guiding slot extending along a first direction, and a first
irradiation slot group extending along a second direction, wherein the first irradiation slot group is connected to the first
wave guiding slot.

US Pat. No. 9,054,118

HEAT DISSIPATING SEMICONDUCTOR DEVICE PACKAGES AND RELATED METHODS

ADVANCED SEMICONDUCTOR EN...

1. A method of making a plurality of semiconductor device packages, the method comprising:
arranging a plurality of semiconductor devices on a substrate;
placing the substrate in apposition with a heat sink matrix, wherein the semiconductor devices are disposed between the substrate
and the heat sink matrix;

forming a package body between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor
devices;

forming a plurality of first slots extending through the heat sink matrix and partially extending into the package body; and
forming a plurality of second slots, wherein the second slots extend through the substrate and into the package body, singulating
the plurality of semiconductor device packages.

US Pat. No. 10,096,569

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A method for manufacturing a semiconductor device, comprising:providing a first electronic component including a first metal contact and a second electronic component including a second metal contact;
irradiating an electromagnetic radiation on the first metal contact to change a lattice of the first metal contact; and
bonding the first metal contact to the second metal contact under a pressure and a temperature.

US Pat. No. 9,184,716

LOW NOISE AMPLIFIER AND RECEIVER

ADVANCED SEMICONDUCTOR EN...

1. A low noise amplifier, comprising:
a current mirror circuit, providing a first current and a third current according to a system voltage and a preset current,
wherein the first current and the third current are mapping current of the preset current;

a bias circuit, electrically connected to the current mirror circuit, the bias circuit receiving the first current and third
current and outputting a first bias voltage and a second bias voltage according to the first current and the third current;

a cascode amplifying circuit, electrically connected to the bias circuit so as to respectively receive the first bias voltage
and the second bias voltage, and accordingly to work at an operation bias point, the cascode amplifying circuit is used for
receiving and amplifying a radio frequency (RF) input signal and accordingly outputting a RF output signal; and

a power gain compensating circuit, electrically connected between the cascode amplifying circuit and the current mirror circuit,
the power gain compensating circuit receiving the RF output signal and accordingly outputting a gain compensating signal to
the current mirror circuit so as to dynamically adjust current values of the first current and the third current and change
bias region of the cascode amplifying circuit, further compensating power gain of the low noise amplifier in order to increase
1 dB gain compression point (P1 dB).

US Pat. No. 9,148,097

ELECTRONIC SYSTEM—RADIO FREQUENCY POWER AMPLIFIER AND METHOD FOR DYNAMIC ADJUSTING BIAS POINT

Advanced Semiconductor En...

1. An RF power amplifier, configured for amplifying a received RF input signal, the RF power amplifier comprising:
a bias circuit, configured to receive a first system voltage and to provide a work voltage according to the first system voltage;
an output-stage circuit, electrically connected to the bias circuit, the output-stage circuit configured to receive the work
voltage so as to operate at an operation bias point; and

a dynamic bias controlling circuit, electrically connected between the bias circuit and the output-stage circuit, the dynamic
bias controlling circuit configured to detect the RF input signal and to output a compensation voltage to the bias circuit
according to a change of the RF input signal;

wherein the bias circuit comprises:
a first transistor, having an emitter connected to a ground voltage, and having a base connected to the dynamic bias controlling
circuit for receiving the compensation voltage;

a second transistor, having a base connected to a collector of the first transistor, and having a collector connected to the
first system voltage;

a first reference resistor, having one terminal connected to the first system voltage, and having another terminal connected
to the base of the second transistor, wherein the first reference resistor is configured for generating a first reference
current;

a first resistor, having one terminal connected to an emitter of the second transistor, and having another terminal connected
to the base of the first transistor; and

a second resistor, having one terminal connected to the emitter of the second transistor, and having another terminal connected
to the output-stage circuit and configured to output the work voltage;

wherein the first reference current is equal to a sum of a collector current of the first transistor and a base current of
the second transistor; and

wherein, when an input power of the RF input signal increases such that the operation bias point offsets and the work voltage
decreases, the work voltage is increased by the bias circuit according to the compensation voltage received so as to recover
or elevate the operation bias point.

US Pat. No. 9,105,613

METHOD OF MANUFACTURING ELECTRONIC PACKAGE MODULE AND ELECTRONIC PACKAGE MODULE MANUFACTURED BY THE SAME

Advanced Semiconductor En...

1. A method of manufacturing an electronic package module, the method comprising:
providing a circuit board having a first mounting face and a second mounting face, wherein the first mounting face has at
least one first encapsulation region and at least one first predetermined region, and the second mounting face has at least
one second encapsulation region and at least one second predetermined region;

mounting at least one first-type electronic component on the first mounting face at the first encapsulation region;
forming a first dam structure at the boundary between the first encapsulation region and the first predetermined region;
forming a first encapsulation at the first encapsulation region;
forming a second dam structure at the boundary between the second encapsulation region and the second predetermined region;
forming a second encapsulation at the second encapsulation region;
forming a first metal shield layer at the first encapsulation region, wherein the first metal shield layer contacts at least
one contact pad on the circuit board;

forming a first sacrificial layer on the first metal shield layer;
forming a second metal shield layer at the second encapsulation region, wherein the second metal shield layer contacts the
circuit board; and

removing the first sacrificial layer.

US Pat. No. 10,049,976

SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor substrate, comprising:an insulating layer; and
a first conductive circuit layer embedded at a first surface of the insulating layer, the first conductive circuit layer having an upper surface and comprising a first portion and a second portion, the first portion comprising a bonding pad and one portion of a conductive trace and the second portion comprising another portion of the conductive trace, wherein an upper surface of the first portion is not coplanar with an upper surface of the second portion,
and wherein the bonding pad is lower than the first surface of the insulating layer, and the entire upper surface of the first conductive circuit layer is exposed from the insulating layer.

US Pat. No. 9,659,853

DOUBLE SIDE VIA LAST METHOD FOR DOUBLE EMBEDDED PATTERNED SUBSTRATE

ADVANCED SEMICONDUCTOR EN...

1. An interposer substrate, comprising:
a dielectric layer with a first surface and a second surface opposite to the first surface, wherein the dielectric layer is
formed of a same material throughout the dielectric layer;

a first circuit pattern embedded in the dielectric layer and disposed at the first surface of the dielectric layer;
a second circuit pattern embedded in the dielectric layer and disposed at the second surface of the dielectric layer;
a middle patterned conductive layer disposed within the dielectric layer and between the first circuit pattern and the second
circuit pattern, wherein the middle patterned conductive layer is single layered;

at least one first conductive via connecting the first circuit pattern to the middle patterned conductive layer, each of the
at least one first conductive via including a first end with a first width adjacent to the first circuit pattern and a second
end with a second width adjacent to the middle patterned conductive layer, wherein the first width is greater than the second
width; and

at least one second conductive via connecting the second circuit pattern to the middle patterned conductive layer, each of
the at least one second conductive via including a third end with a third width adjacent to the second circuit pattern and
a fourth end with a fourth width adjacent to the middle patterned conductive layer, wherein the third width is greater than
the fourth width.

US Pat. No. 9,253,887

FABRICATION METHOD OF EMBEDDED CHIP SUBSTRATE

ADVANCED SEMICONDUCTOR EN...

1. A fabrication method of an embedded chip substrate, the fabrication method comprising:
providing a core layer that has an opening;
providing a first insulation layer and a first conductive layer, the first conductive layer being disposed on the first insulation
layer;

disposing the core layer on the first insulation layer, the first insulation layer being located between the core layer and
the first conductive layer, the opening and the first insulation layer forming a recess;

adhering a chip to the first insulation layer via a bottom adhesion layer in the recess;
providing a second insulation layer and a second conductive layer, the second conductive layer being disposed on the second
insulation layer;

laminating the second insulation layer on the core layer in a manner that the recess is filled by a portion of the first insulation
layer; and

respectively patterning the first conductive layer and the second conductive layer, so as to form a first circuit layer and
a second circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer, and the second
circuit layer is electrically connected to the chip.

US Pat. No. 9,850,124

SEMICONDUCTOR DEVICE PACKAGE FOR REDUCING PARASITIC LIGHT AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:
a carrier having a top surface;
a sensor element disposed on or within the carrier; and
a cover comprising:
a base substrate having a top surface, a bottom surface and an inner sidewall, the inner sidewall defining a penetrating hole
extending from the top surface of the base substrate to the bottom surface of the base substrate; and

a periphery barrier coupled to the bottom surface of the base substrate and disposed on the top surface of the carrier; and
a filter disposed on the top surface of the base substrate and covering the penetrating hole;
(i) wherein the inner sidewall of the base substrate is divided into an upper portion and a lower portion, the upper portion
is substantially perpendicular to the top surface of the base substrate, and the lower portion is tilted; or

(ii) wherein the entire inner sidewall of the base substrate is tilted; and
wherein the lower portion of the inner sidewall or the entire inner sidewall is tilted at an angle of between about 10° to
less than about 90°, relative to the top surface of the base substrate.

US Pat. No. 9,768,139

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:
a semiconductor element, the semiconductor element comprising at least one bonding pad disposed adjacent to a surface of the
semiconductor element;

two pillar structures disposed on a single bonding pad of the at least one bonding pad, wherein each of the pillar structures
comprises an under bump metallization (UBM) layer; and

an insulation layer disposed adjacent to the surface of the semiconductor element, wherein the insulation layer defines an
opening, the opening exposing a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

US Pat. No. 9,698,120

PACKAGE PROCESS AND PACKAGE STRUCTURE

ADVANCED SEMICONDUCTOR EN...

1. A package process, comprising:
providing a carrier board having an adhesive layer configured thereon;
configuring a plurality of first semiconductor devices on the adhesive layer, wherein the plurality of the first semiconductor
devices is separated from one another and fixed on the carrier board through the adhesive layer;

forming a first molding compound on the carrier board to cover one or more sidewalls of each of the plurality of the first
semiconductor devices and to fill first gaps between the plurality of the first semiconductor devices so as to form a chip
array board comprising the first semiconductor devices and the molding compound;

forming a plurality of first underfills, on the plurality of the first semiconductor devices respectively, wherein each of
the plurality of the first underfills covers the corresponding first semiconductor device and a portion of the first molding
compound surrounding the corresponding first semiconductor device;

flip-chip bonding a plurality of second semiconductor devices to the plurality of the first semiconductor devices respectively,
each of the plurality of the second semiconductor devices is flip-chip bonded to the corresponding first semiconductor device
by a plurality of second conductive bumps of each of the plurality of the second semiconductor devices passing through the
corresponding first underfill;

forming a second molding compound on the chip array board to at least cover one or more sidewalls of each of the plurality
of the second semiconductor devices and to fill second gaps between the plurality of the second semiconductor devices;

separating the chip array board from the adhesive layer; and
forming a plurality of chip package units, wherein each of the plurality of the chip package units includes at least one of
the plurality of the first semiconductor devices and at least one of the plurality of the second semiconductor devices.

US Pat. No. 9,196,597

SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:
a substrate including:
a first patterned conductive layer having an upper surface;
a first dielectric layer disposed adjacent to the upper surface of the first patterned conductive layer, the first dielectric
layer exposing a portion of the first patterned conductive layer to form a plurality of first contact pads;

a second patterned conductive layer below the first patterned conductive layer and having a lower surface;
a second dielectric layer between the first patterned conductive layer and the second patterned conductive layer, wherein:
the second dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second
patterned conductive layer; and

the second patterned conductive layer includes a plurality of second contact pads exposed by the second dielectric layer;
and

a plurality of conductive posts, each of the plurality of conductive posts extending from the first patterned conductive layer
to the second patterned conductive layer, the each of the plurality of conductive posts filling the corresponding one of the
plurality of openings in the second dielectric layer;

a die electrically connected to the plurality of first contact pads; and
a package body covering the first dielectric layer and the die;
wherein at least one of the plurality of conductive posts has an upper surface having a first area and a lower surface having
a second area, and the first area is larger than the second area.

US Pat. No. 9,173,583

NEURAL SENSING DEVICE AND METHOD FOR MAKING THE SAME

Advanced Semiconductor En...

1. A neural sensing device, comprising:
a base having an active surface and a backside surface;
an integrated circuit portion disposed on the active surface of the base; and
a plurality of microprobes disposed on the backside surface of the base, each of the microprobes comprising:
a probe body protruding from the backside surface of the base and including a tip at a distal end;
a first isolation layer covering the probe body;
a conductive layer covering the first isolation layer and electrically connected to the integrated circuit portion; and
a second isolation layer covering the conductive layer and having an opening to expose the conductive layer around a portion
of the tip.

US Pat. No. 10,141,252

SEMICONDUCTOR PACKAGES

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a passivation layer having a first surface and a second surface opposite to the first surface, the passivation layer defining a through hole extending from the first surface to the second surface, the through hole further defined by a first sidewall and a second sidewall of the passivation layer;
a first conductive layer on the first surface of the passivation layer and the first sidewall;
a second conductive layer on the second surface of the passivation layer and the second sidewall; and
a third conductive layer between the first conductive layer and the second conductive layer,
wherein the third conductive layer comprises a first seed layer adjacent to the first conductive layer and a second seed layer adjacent to the second conductive layer,
wherein the passivation layer comprises a first polymer layer and a second polymer layer,
wherein the first seed layer is disposed between the first conductive layer and the first polymer layer and the second seed layer is disposed between the second conductive layer and the second polymer layer.

US Pat. No. 10,121,929

OPTICAL DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. An optical device, comprising:a carrier including a light transmitting layer and a light shielding layer disposed on the light transmitting layer;
a light emitter disposed on the carrier;
a light detector disposed on the carrier;
a light transmitting encapsulant encapsulating the light emitter and the light detector; and
a light shielding wall disposed in the light transmitting encapsulant and in contact with the light transmitting encapsulant and the light shielding layer.

US Pat. No. 9,219,048

SUBSTRATE HAVING PILLAR GROUP AND SEMICONDUCTOR PACKAGE HAVING PILLAR GROUP

ADVANCED SEMICONDUCTOR EN...

1. A substrate, comprising:
a body having a surface;
a conductive pad group disposed on the surface, wherein the conductive pad group comprises a plurality of conductive pads
each with at least one inner side and at least one outer side, a first inner side of a first conductive pad is faced towards
a second inner side of an adjacent second conductive pad, and the first inner side and the second inner side are separated
by a spaced section;

a plurality of conductive traces electrically connected to respective ones of the conductive pads; and
a metal pillar group formed on the conductive pad group, the metal pillar group including a plurality of metal pillars formed
on corresponding ones of the conductive pads;

wherein a metal pillar of the metal pillar group includes a pillar inner side and a pillar outer side, and either: the pillar
inner side partially aligns with the first inner side of the first conductive pad; or the pillar outer side partially aligns
with an outer side of a corresponding conductive pad.

US Pat. No. 9,059,379

LIGHT-EMITTING SEMICONDUCTOR PACKAGES AND RELATED METHODS

Advanced Semiconductor En...

1. A light-emitting semiconductor package, comprising:
a central barrier defining an interior space;
a plurality of leads surrounding the central barrier, and electrically isolated from each other;
a light-emitting device disposed in the interior space and having an upper light-emitting surface and a lower light-emitting
surface, the light-emitting device being electrically connected to the plurality of leads;

a first encapsulant covering the upper light-emitting surface of the light-emitting device;
a package body encapsulating portions of the central barrier, portions of each of the plurality of leads, and the first encapsulant;
and

a second encapsulant, covering the lower light-emitting surface of the light-emitting device, wherein light emitted from the
lower light-emitting surface of the light-emitting device is capable of passing through the second encapsulant;

wherein portions of the first and second encapsulants are located within the interior space and laterally restricted by the
central barrier, wherein side portions of the central barrier and the plurality of leads each include an upper sloped portion,
a lower sloped portion, and peaks at a junction of the upper and lower sloped portions, and the first encapsulant contacts
the second encapsulant near the peaks of the plurality of leads within the interior space.

US Pat. No. 9,984,983

SEMICONDUCTOR PACKAGES WITH THERMAL-ENHANCED CONFORMAL SHIELDING AND RELATED METHODS

Advanced Semiconductor En...

1. A semiconductor package, comprising:a substrate having an upper surface and a lateral surface adjacent to a periphery of the substrate;
a grounding segment disposed adjacent the periphery of the substrate;
a die disposed adjacent to the upper surface of the substrate, wherein the die has an active surface and a backside surface opposite the active surface;
a package body disposed on the upper surface of the substrate and at least partially encapsulating the die, wherein the package body has an upper surface and at least one side surface, and wherein the backside surface of the die is exposed from the upper surface of the package body;
a heat dissipation layer disposed on the upper surface of the package body and the backside surface of the die, wherein the heat dissipation layer has an extending portion disposed on the at least one side surface of the package body and having an end surface contacting the upper surface of the substrate, and wherein the extending portion of the heat dissipation layer has an outer surface coplanar with the lateral surface of the substrate; and
a shielding layer disposed over the heat dissipation layer and in contact with the lateral surface of the substrate, and electrically connected to the grounding segment.

US Pat. No. 9,349,611

STACKABLE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Advanced Semiconductor En...

1. A manufacturing method, comprising:
providing a carrier;
disposing a semiconductor device over the carrier such that an active surface of the semiconductor device faces the carrier,
wherein the semiconductor device includes a pad adjacent to the active surface;

forming a package body over the carrier and the semiconductor device, wherein the package body includes a first package surface
and a second package surface opposite to the first package surface, and the first package surface faces the carrier;

forming a through-hole in the package body, wherein the through-hole extends between the first package surface and the second
package surface;

separating the carrier from the package body;
forming a dielectric layer adjacent to the first package surface, wherein the dielectric layer exposes the pad and the through-hole;
forming a conductive via in the through-hole, wherein the conductive via includes a first end, adjacent to the first package
surface, and a second end, adjacent to the second package surface;

forming a patterned conductive layer adjacent to the dielectric layer, wherein the patterned conductive layer is electrically
connected to at least one of the pad and the first end of the conductive via; and

forming a stud bump adjacent to the second end of the conductive via.

US Pat. No. 9,190,367

SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a plurality of components including a first component mounted on the first surface of the substrate, and a second component
mounted on the second surface of the substrate;

an interposer having a first surface;
an electrical interconnect connecting the first surface of the interposer to the second surface of the substrate; and
a first package body disposed on the second surface of the substrate and encapsulating the second component, the electrical
interconnect and at least a portion of the interposer;

wherein a sum of a thickness of the interposer and a height of the electrical interconnect is substantially equal to a height
of the first package body; and

wherein a lateral surface of the substrate, a lateral surface of the interposer, and a lateral surface of the first package
body are substantially coplanar.

US Pat. No. 9,984,993

BONDING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A method of manufacturing a bonding structure, comprising:(a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, the at least one bonding pad having a sloped surface with a first slope;
(b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and the at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope, and the at least one pillar further has a top surface and an edge portion defined by the sidewall of the pillar and the top surface of the pillar; and
(c) bonding the at least one pillar to a portion of the sloped surface of the at least one bonding pad, wherein bonding the at least one pillar comprises pressing the at least one pillar against the sloped surface of the at least one bonding pad and carrying out a metal fusion bonding or a metal eutectic bonding between the edge portion of the at least one pillar and the sloped surface of the at least one bonding pad.

US Pat. No. 9,978,688

SEMICONDUCTOR PACKAGE HAVING A WAVEGUIDE ANTENNA AND MANUFACTURING METHOD THEREOF

Advanced Semiconductor En...

1. A semiconductor package comprising:a substrate including a chip;
a grounding layer disposed on the substrate;
an encapsulant covering the chip and the grounding layer;
a conductive via extending from an upper surface of the encapsulant to the grounding layer;
a shielding layer disposed on the encapsulant, the shielding layer
electrically connected to the conductive via;
at least one signal emitting opening in the encapsulant exposing a cavity defining a waveguide;
a feeding contact on the substrate; and
a conductive element disposed directly on the feeding contact and encapsulated by the encapsulant;
wherein the signal emitting opening is disposed on a lateral surface of the encapsulant and corresponds to the conductive element, and
wherein the conductive via and the conductive element are arranged along the waveguide, and
wherein the conductive via and the conductive element have a substantially same height.

US Pat. No. 9,578,737

SUBSTRATE STRUCTURE AND PACKAGE STRUCTURE USING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A substrate structure, comprising:
a substrate core having a first surface and a second surface opposite to the first surface;
a plurality of traces disposed on the first surface;
a plurality of first metal tiles to increase the strength of the substrate structure, wherein the first metal tiles are disposed
on the first surface;

a plurality of second metal tiles to increase the strength of the substrate structure, wherein the second metal tiles are
disposed on the second surface;

a plurality of first electrically-functioning circuits disposed on the first surface; and
a plurality of second electrically-functioning circuits disposed on the second surface;
wherein, the traces, the first electrically-functioning circuits, and the first metal tiles along the first surface add up
to a first metal structure covering a first proportion of the first surface, the second electrically-functioning circuits
and the second metal tiles along the second surface add up to a second metal structure covering a second proportion of the
second surface, and a difference between the first proportion and the second proportion is within 15%.

US Pat. No. 9,437,576

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising
a substrate having a top surface;
a first electrical component disposed on the top surface of the substrate;
a second electrical component disposed on the top surface of the substrate, the second electrical component having a top surface;
a conductive frame defining a top portion and a rim substantially perpendicular to the top portion, the top portion having
a top surface, the conductive frame disposed on the top surface of the substrate to cover the first electrical component,
the conductive frame including at least one opening in the top portion of the conductive frame, the at least one opening exposing
the second electrical component, and the top surface of the top portion of the conductive frame being substantially coplanar
with the top surface of the second electrical component; and

an electromagnetic interference shield in contact with the top surface of the top portion of the conductive frame, an outer
lateral surface of the rim of the conductive frame, and the top surface of the second electrical component.

US Pat. No. 9,406,658

EMBEDDED COMPONENT DEVICE AND MANUFACTURING METHODS THEREOF

ADVANCED SEMICONDUCTOR EN...

1. An embedded component device, comprising:
an electronic component including an electrical contact;
an upper patterned conductive layer;
a single dielectric layer between the upper patterned conductive layer and the electronic component, the dielectric layer
having a first opening exposing the electrical contact;

a first electrical interconnect extending from the electrical contact to the upper patterned conductive layer, wherein the
first electrical interconnect fills the first opening;

a lower patterned conductive layer embedded in the dielectric layer, the dielectric layer having a second opening extending
from the lower patterned conductive layer to the upper patterned conductive layer, the second opening having an upper portion
exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer;

a conductive via located at the lower portion of the second opening; and
a second electrical interconnect filling the upper portion of the second opening;
wherein the second electrical interconnect includes a top surface having a first area, and includes a bottom surface having
a second area, and the first area is different from the second area; and

wherein the conductive via includes an upper surface having a third area substantially parallel to the second area, and the
third area is larger than the second area.

US Pat. No. 9,165,900

SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING SAME

Advanced Semiconductor En...

1. A semiconductor package, comprising:
a substrate, including:
a dielectric layer having a plurality of openings;
a conductive layer disposed adjacent to the dielectric layer;
a plurality of conductive vias disposed in respective ones of the openings; and
an etching stop layer disposed in the openings and physically contacting a top end of each of the plurality of conductive
vias;

wherein the conductive layer and the conductive vias are formed of the same material;
a chip attached to a top side of the substrate and connected to the conductive layer; and
a plurality of conductive bumps disposed adjacent to respective ones of the conductive vias,
wherein the etching stop layer is physically contacting the conductive layer at a bottom surface of the conductive layer,
and a bottom end of each conductive via is connected to the respective conductive bump such that the bottom end of the conductive
via does not protrude from the respective opening.

US Pat. No. 9,461,001

SEMICONDUCTOR DEVICE PACKAGE INTEGRATED WITH COIL FOR WIRELESS CHARGING AND ELECTROMAGNETIC INTERFERENCE SHIELDING, AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising
a carrier having a top surface;
an electronic component disposed on the top surface of the carrier;
at least two conductive elements disposed on the top surface of the carrier;
a package body disposed on the top surface of the carrier and encapsulating the electronic component and a portion of each
of the conductive elements;

a shield disposed on the package body and covering an exterior of the package body;
a magnetic insulating layer disposed on a top surface of the shield; and
a patterned conductive layer disposed on the magnetic insulating layer,
wherein each of the conductive elements electrically connects the patterned conductive layer to the electronic component;
and

wherein the shield comprises multiple non-magnetic conductive layers, multiple insulating layers and multiple magnetic conductive
layers, and wherein at least one of the insulating layers is located between each non-magnetic conductive layer and a neighboring
magnetic conductive layer.

US Pat. No. 9,553,072

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:
a substrate;
a plurality of electrical components disposed on the substrate;
a conductive frame disposed on the substrate, the conductive frame including:
a top portion including at least one opening;
a rim connected to the top portion and surrounding the electrical components; and
at least one compartment extending from the top portion of the conductive frame and separating one or more of the electrical
components from others of the electrical components; and

an electromagnetic interference shield in contact with the top portion and the rim of the conductive frame.

US Pat. No. 10,256,173

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:a substrate having a first surface and a second surface opposite to the first surface;
a sensor plate attached and electrically connected to the second surface of the substrate, wherein the sensor plate is a glass plate;
a first package body disposed adjacent to the first surface of the substrate, the first package body defining at least one cavity; and
at least one connecting element disposed adjacent to the first surface of the substrate and in a corresponding cavity, wherein a space is defined between a periphery surface of a portion of the connecting element and a sidewall of a portion of the cavity, and an end portion of the connecting element extends beyond an outermost surface of the first package body.

US Pat. No. 9,960,137

SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR FORMING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package ready for assembly, comprising:a semiconductor substrate;
a first under-bump-metallurgy (UBM) layer disposed on the semiconductor substrate;
a first conductive pillar disposed on the first UBM layer; and
a second conductive pillar disposed on the first conductive pillar;
wherein a material of the first conductive pillar is different from a material of the second conductive pillar, and the material of the second conductive pillar includes an antioxidant, and the first conductive pillar has a width, the second conductive pillar has a height, and the height is greater than the width by at least 0.65 times.

US Pat. No. 9,618,191

LIGHT EMITTING PACKAGE AND LED BULB

Advanced Semiconductor En...

1. A structure comprising:
a first device mounting portion comprising a first surface and a second surface;
a second device mounting portion comprising a first surface and a second surface; and
a plurality of light emitting devices mounted on the first and second surfaces of the first device mounting portion, and on
the first and second surfaces of the second device mounting portion, wherein the light emitting devices on the second surface
of the first device mounting portion are arranged in a plurality of columns, spaced by a pitch that decreases with increasing
distance from the second device mounting portion, and wherein the light emitting devices on the second surface of the second
device mounting portion are arranged in a plurality of columns, spaced by a pitch that decreases with increasing distance
from the first device mounting portion.

US Pat. No. 9,570,381

SEMICONDUCTOR PACKAGES AND RELATED MANUFACTURING METHODS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:
a die pad;
a plurality of leads surrounding the die pad, wherein each of the leads comprises an inner lead portion and an outer lead
portion, and wherein at least one lead further comprises a trace portion;

a chip disposed on the die pad and electrically connected to ones of the plurality of leads;
a molding compound encapsulating the chip, the inner lead portions and the trace portion, wherein the outer lead portions
and a bottom surface of the trace portion are exposed from the molding compound; and

an insulating layer covering the bottom surface of the trace portion, and wherein the insulating layer further covers a portion
of a bottom surface of the molding compound.

US Pat. No. 9,478,500

INTERPOSER SUBSTRATE, SEMICONDUCTOR STRUCTURE AND FABRICATING PROCESS THEREOF

ADVANCED SEMICONDUCTOR EN...

1. An interposer substrate, comprising:
a first core layer;
a first conductive layer on a first side of the interposer substrate and comprising a plurality of first pads;
a second conductive layer on a second side of the interposer substrate and comprising a plurality of second pads, wherein
the second side of the interposer substrate is opposite the first side of the interposer substrate;

a plurality of conductive vias electrically connecting the first conductive layer and the second conductive layer; and
a reinforcement structure in the interposer substrate;
wherein the interposer substrate defines a cavity.

US Pat. No. 10,074,602

SUBSTRATE, SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING PROCESS

ADVANCED SEMICONDUCTOR EN...

13. A semiconductor package structure, comprising:a first conductive structure comprising a first dielectric layer and a first circuit layer embedded in the first dielectric layer, wherein a portion of the first circuit layer is exposed from a first surface of the first dielectric layer for external connection;
a second conductive structure attached to the first conductive structure and comprising at least one second dielectric layer disposed on a second surface of the first dielectric layer and at least one second circuit layer embedded in the second dielectric layer, wherein the second circuit layer is electrically connected to the first circuit layer;
a third conductive structure attached to the second conductive structure and comprising a third dielectric layer disposed on the second conductive structure and a third circuit layer disposed on the third dielectric layer, wherein the third circuit layer is electrically connected to the second circuit layer, a portion of the third circuit layer is for external connection, a material of the second dielectric layer is different from a material of the first dielectric layer and a material of the third dielectric layer, and the first conductive structure, the second conductive structure, and the third conductive structure form a substrate;
a semiconductor die electrically connected to the exposed portion of the first circuit layer; and
an encapsulant covering the semiconductor die and a surface of the substrate.

US Pat. No. 9,960,121

SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIA AND MANUFACTURING PROCESS FOR SAME

Advanced Semiconductor En...

1. A semiconductor device, comprising:a semiconductor chip including a plurality of conductive pads;
a package body at least partially encapsulating the semiconductor chip and having a top surface and bottom surface opposite to the top surface, the package body being a composite material which includes resin and fillers;
a conductive layer disposed on the bottom surface of the package body; and
at least one through via within the package body and electrically connected to the conductive layer, the via extending from the conductive layer and protruding out of the top surface of the package body;
wherein:
the package body has at least one hole formed therein defining a hole sidewall and the via is disposed in the hole and comprises a dielectric material which is disposed on the hole sidewall of the hole;
the hole sidewall is partially defined by portions of the fillers protruding from the resin and is of a first surface roughness value; and
the dielectric material defines at least one bore having a bore sidewall which is of a second surface roughness value less than the first surface roughness value.

US Pat. No. 9,953,930

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A method for manufacturing a semiconductor package structure, comprising:(a) providing a substrate with a semiconductor element disposed thereon; and
(b) providing an encapsulant, an adhesion layer and a metal cap to form the semiconductor package structure, wherein the encapsulant covers the semiconductor element, the adhesion layer is disposed on the encapsulant, the metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant;
wherein (b) includes:
(b1) forming the encapsulant on the substrate to cover the semiconductor element;
(b2) providing a metal foil;
(b3) forming the adhesion layer on a surface of the metal foil;
(b4) disposing the metal foil above the encapsulant, wherein the adhesion layer faces the encapsulant; and
(b5) punching the metal foil to the encapsulant, so as to form the metal cap attached to the encapsulant by the adhesion layer, such that the metal cap is conformal with the encapsulant.

US Pat. No. 9,911,877

ELECTRONIC DEVICE, PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. An electronic device, comprising:
a light source;
a light receiver;
a first light guide structure facing a light emitting surface of the light source and facing a lateral wall of the light receiver;
and

a second light guide structure over the light receiver and coupled to the first light guide structure,
wherein the light receiver and the second light guide structure defines a cavity between the light receiver and the second
light guide structure, the light receiver includes a top surface including a light receiving region, the light receiving region
is exposed to the cavity, and the first light guide structure covers a portion of the top surface of the light receiver and
exposes the light receiving region.

US Pat. No. 9,768,103

FABRICATION METHOD OF EMBEDDED CHIP SUBSTRATE

ADVANCED SEMICONDUCTOR EN...

1. An embedded chip substrate, comprising:
a dielectric layer defining an opening having an inner side wall;
a first circuit layer disposed over the dielectric layer;
a second circuit layer disposed over the dielectric layer on a side of the dielectric layer opposite to the first circuit
layer;

a conductive through hole extending from a top surface of the dielectric layer to a bottom surface of the dielectric layer;
a first insulation layer disposed over the first circuit layer;
a second insulation layer disposed over the second circuit layer;
a chip having a side wall, the chip adhered in a recess formed by the opening and the second insulation layer;
a plurality of first vias in the first insulation layer;
a third circuit layer disposed over the first insulation layer and electrically connected to the chip through the first vias;
and

a fourth circuit layer disposed over the second insulation layer, the fourth circuit layer electrically connected to the first
circuit layer through the conductive through hole;

wherein the first insulation layer extends into a space between the inner side wall of the opening and the side wall of the
chip.

US Pat. No. 9,721,899

EMBEDDED COMPONENT PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. An embedded component package structure, comprising:
a substrate having a first surface and a second surface opposite the first surface, the substrate defining a through hole
extending from the first surface to the second surface;

a first conductive component extending from the first surface of the substrate to the second surface of the substrate;
a first conductive layer disposed on the first surface of the substrate;
a second conductive layer disposed on the second surface of the substrate and electrically connected to the first conductive
layer by the first conductive component;

at least one die disposed in the through hole, the die having an active surface and a back surface opposite the active surface,
the back surface exposed from the second surface of the substrate;

a first dielectric layer covering the active surface of the die and the first surface of the substrate;
a second conductive component;
a third conductive layer disposed on the first dielectric layer and electrically connected to the die by the second conductive
component; and

a first metal layer disposed directly on the back surface of the die, wherein the first metal layer extends laterally to the
second conductive layer, and is electrically connected to the first conductive layer.

US Pat. No. 9,589,871

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:
a leadframe comprising:
a main portion having a first surface and a second surface; and
a protrusion portion protruding from the second surface of the main portion;
a semiconductor die bonded to the main portion, wherein a position of the protrusion portion corresponds to a position of
the semiconductor die and the protrusion portion protrudes from the second surface of the main portion below the die;

a first insulator covering the semiconductor die and a portion of the first surface of the main portion; and
a conductive pattern disposed on the first insulator and electrically connected to the semiconductor die.

US Pat. No. 9,922,917

SEMICONDUCTOR PACKAGE INCLUDING SUBSTRATES SPACED BY AT LEAST ONE ELECTRICAL CONNECTING ELEMENT

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:
a first substrate having a first lateral surface, a first upper surface, a bottom surface and a plurality of bottom pads,
wherein the bottom pads are disposed adjacent to the bottom surface;

a first semiconductor device mounted to the first upper surface of the first substrate;
a molding compound covering the first lateral surface and the first upper surface of the first substrate and at least a portion
of the first semiconductor device; and

at least one thermal conductive element disposed on the molding compound;
wherein a surface of the first semiconductor device is substantially coplanar with a first surface of the molding compound.

US Pat. No. 9,852,971

INTERPOSER, SEMICONDUCTOR PACKAGE STRUCTURE, AND SEMICONDUCTOR PROCESS

ADVANCED SEMICONDUCTOR EN...

1. An interposer, comprising:
an interconnection structure comprising:
a metal layer defining at least one through hole having a side wall;
at least one metal via disposed in the through hole, and a space defined between the at least one metal via and the side wall
of the through hole; and

an isolation material filling the space; and
a redistribution layer disposed on a surface of the interconnection structure and electrically connected to the metal via,
wherein the redistribution layer is electrically connected to the metal layer.

US Pat. No. 10,032,652

SEMICONDUCTOR PACKAGE HAVING IMPROVED PACKAGE-ON-PACKAGE INTERCONNECTION

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a substrate;
a semiconductor element mounted on the substrate;
at least one connecting element disposed on the substrate and adjacent to the semiconductor element; and
an encapsulant covering at least a portion of the semiconductor element and at least a portion of the connecting element,
wherein the encapsulant has a top surface, the encapsulant defines a first groove surrounding the connecting element and a second groove surrounding the semiconductor element, the connecting element is exposed from and extends upwardly from the top surface of the encapsulant, the encapsulant further defines at least one accommodating cavity for accommodating a portion of the connecting element, and a sidewall of the first groove and a sidewall of the accommodating cavity intersect to form a peak portion, wherein the peak portion surrounds and contacts the connecting element.

US Pat. No. 9,984,985

SEMICONDUCTOR PACKAGE DEVICE WITH ANTENNA ARRAY

ADVANCED SEMICONDUCTOR EN...

14. A semiconductor package device, comprising:a substrate having a first surface, a second surface opposite to the first surface, a first lateral surface extending between the first surface and the second surface, a second lateral surface opposite to the first lateral surface, and a third lateral surface extending between the first lateral surface of the substrate and the second lateral surface of the substrate;
a first antenna disposed on the first surface of the substrate;
an electronic component disposed on the second surface of the substrate;
a package body disposed on the second surface of the substrate and encapsulating the electronic component, the package body having a first lateral surface substantially coplanar with the first lateral surface of the substrate and a second lateral surface substantially coplanar with the second lateral surface of the substrate;
a first metal strip disposed on the first lateral surface of the substrate and on the first lateral surface of the package body;
a second metal strip disposed on the second lateral surface of the substrate and on the second lateral surface of the package body, wherein the second metal strip electrically connects to the first metal strip; and
a second antenna disposed on the third lateral surface of the substrate.

US Pat. No. 9,929,078

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:a conductive structure having a first surface and a second surface opposite the first surface;
at least two semiconductor elements disposed on and electrically connected to the first surface of the conductive structure; and
an encapsulant covering the semiconductor elements and the first surface of the conductive structure, wherein the encapsulant has a width ‘L’ and defines at least one notch portion, a minimum distance ‘d’ is between a bottom surface of the notch portion and the second surface of the conductive structure, the encapsulant has a Young's modulus ‘E’ and a rupture strength ‘Sr’, and L/(K×d)>E/Sr, wherein ‘K’ is a stress concentration factor with a value of greater than 1.2.

US Pat. No. 9,917,043

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

11. A semiconductor package comprising:
a redistribution layer having a first surface and a second surface opposite to the first surface;
a conductive pad on the first surface of the redistribution layer;
a dielectric layer on the first surface of the redistribution layer to cover a first portion of the conductive pad and to
expose a second portion of the conductive pad;

a silicon layer on the dielectric layer, the silicon layer defining a recess to expose the second portion of the conductive
pad;

a conductive contact disposed over the silicon layer and extending into the recess of the silicon layer; and
a passivation layer on the silicon layer and extending into the recess to cover a sidewall of the recess and a part of the
second portion of the conductive pad.

US Pat. No. 9,837,352

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:
a substrate having a first surface and a second surface;
at least one integrated passive device including at least one capacitor disposed adjacent to the first surface of the substrate,
wherein the capacitor includes a lower electrode disposed on the first surface of the substrate;

a first redistribution layer disposed adjacent to the first surface of the substrate;
a second redistribution layer disposed adjacent to the second surface of the substrate; and
a plurality of conductive vias extending through the substrate, and electrically connecting the first redistribution layer
and the second redistribution layer.

US Pat. No. 9,443,785

SEMICONDUCTOR PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:
a substrate;
a semiconductor device mounted to the substrate;
an adhesive disposed above the semiconductor device;
a thermal conductive element disposed above the adhesive; and
a molding compound covering a side surface of the substrate and at least a part of a side surface of the semiconductor device;
wherein a lateral surface of the thermal conductive element is coplanar with a lateral surface of the adhesive.

US Pat. No. 10,177,268

OPTICAL DEVICE, OPTICAL MODULE STRUCTURE AND MANUFACTURING PROCESS

ADVANCED SEMICONDUCTOR EN...

1. An optical device, comprising:an emitter;
a detector disposed adjacent to the emitter;
an encapsulation layer encapsulating the emitter and the detector;
a dielectric layer disposed on the emitter, the detector and the encapsulation layer;
a redistribution layer disposed on the dielectric layer and electrically connected to the emitter and the detector; and
a light shielding structure disposed on the encapsulation layer and corresponding to a location between the emitter and the detector.

US Pat. No. 10,147,835

OPTICAL DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. An optical device, comprising:a carrier including a light transmitting layer and a light shielding layer disposed on the light transmitting layer;
a light emitter disposed on the carrier;
a light detector disposed on the carrier;
a light transmitting encapsulant encapsulating the light emitter and the light detector; and
a light shielding wall disposed in the light transmitting encapsulant and in contact with the light transmitting encapsulant and the light shielding layer.

US Pat. No. 10,002,849

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

11. A method for manufacturing a semiconductor package structure, comprising:(a) disposing at least one semiconductor element on a conductive structure, wherein the conductive structure includes at least one insulation layer and at least one circuit layer;
(b) disposing an encapsulant on the conductive structure to cover the semiconductor element;
(c) attaching a supporting structure on the conductive structure to surround the semiconductor element; and
(d) disposing a metal layer on or in the encapsulant, wherein the metal layer is electrically insulated from the conductive structure.

US Pat. No. 9,978,705

SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR PACKAGE STRUCTURE HAVING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:a substrate comprising:
an insulating layer having a top surface and a side surface;
a conductive circuit layer recessed from the top surface of the insulating layer, wherein the conductive circuit layer comprises at least one pad, and a side surface of the pad extends along the side surface of the insulating layer; and
a conductive bump disposed on the pad of the conductive circuit layer, wherein the conductive bump comprises a first portion and a second portion, and the second portion and the pad are integrated, and wherein a side surface of the second portion of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space;
a semiconductor chip; and
a solder material electrically connecting the conductive bump and the semiconductor chip, wherein a portion of the solder material is disposed in the accommodating space.

US Pat. No. 9,773,753

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:
a first die having a first surface and a second surface opposite to the first surface, the first die comprising at least one
first pad disposed adjacent to the first surface of the first die;

a second die having a first surface and a second surface opposite to the first surface, the second die comprising at least
one second pad disposed adjacent to the first surface of the second die;

a first dielectric layer disposed on at least a portion of the first surface of the first die and at least a portion of the
first surface of the second die; and

at least one first trace disposed on the first dielectric layer and connecting the first pad to the second pad, the first
trace comprising an end portion adjacent to the first pad and a body portion, wherein the end portion extends at an angle
?1 relative to a direction of extension of the body portion.

US Pat. No. 9,721,799

SEMICONDUCTOR PACKAGE WITH REDUCED VIA HOLE WIDTH AND REDUCED PAD PATCH AND MANUFACTURING METHOD THEREOF

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package comprising:
an encapsulation layer having a first surface, the encapsulation layer comprising a first material;
a component within the encapsulation layer, the component having a front surface and comprising a plurality of pads on the
front surface;

a dielectric layer on the first surface of the encapsulation layer, the dielectric layer comprising a second material, and
the dielectric layer defining a plurality of via holes; wherein the first material is different than the second material;
wherein the plurality of pads of the component are against the dielectric layer; and wherein the dielectric layer has a second
surface opposite the first surface of the encapsulation layer, and each of the plurality of via holes extends from the second
surface of the dielectric layer to a respective one of the plurality of pads; and

a first patterned conductive layer embedded at the second surface of the dielectric layer and surrounding the via holes.

US Pat. No. 9,653,407

SEMICONDUCTOR DEVICE PACKAGES

ADVANCED SEMICONDUCTOR EN...

1. A method of manufacturing a semiconductor device package, comprising:
(a) providing a substrate having a top surface, a bottom surface opposite to the top surface, and a lateral surface extending
from the top surface to the bottom surface, wherein the lateral surface includes a first portion adjacent to the bottom surface
and a second portion aligned with the first portion and adjacent to the top surface, the substrate including a grounding element
exposed at the second portion of the lateral surface of the substrate;

(b) attaching at least one electronic component on the top surface of the substrate;
(c) forming a package body on the substrate to encapsulate the electronic component and the top surface of the substrate;
(d) covering the first portion of the lateral surface and the bottom surface of the substrate with a first adhesive;
(e) forming a conductive layer on a top surface and a lateral surface of the package body, the second portion of the lateral
surface of the substrate, and an exposed portion of the grounding element; and

(f) removing the first adhesive.

US Pat. No. 9,437,532

SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND PROCESS FOR MANUFACTURING

Advanced Semiconductor En...

1. A semiconductor package, comprising:
a package substrate comprising:
a dielectric layer;
a first circuit layer disposed on or in the dielectric layer; and
a plurality of pillars disposed on the first circuit layer, wherein each of the pillars has a recess portion in the top end
of the pillar;

a die; and
a plurality of solder balls disposed on the die, wherein each of the solder balls is bonded to each of the pillars and kept
at the recess portion.

US Pat. No. 10,186,779

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a carrier comprising a top surface;
an electrical component disposed over the top surface of the carrier;
an antenna disposed over the top surface of the carrier and spaced from the electrical component;
a conductive pad disposed over the top surface of the carrier and beneath the antenna, wherein the conductive pad comprises a resonant structure; and
a conductive line electrically connected to the electrical component and extending within the carrier,
wherein a part of the conductive line is located beneath the antenna and the resonant structure of the conductive pad.

US Pat. No. 10,177,099

SEMICONDUCTOR PACKAGE STRUCTURE, PACKAGE ON PACKAGE STRUCTURE AND PACKAGING METHOD

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:a substrate having a lateral surface, a first surface and a second surface opposite to the first surface and a first coefficient of thermal expansion CTE1;
a first semiconductor device disposed adjacent to the first surface of the substrate, wherein the first semiconductor device is a semiconductor die;
a first encapsulant having a side surface, the first encapsulant disposed on the first surface of the substrate, covering at least a portion of the first semiconductor device, and having a second coefficient of thermal expansion CTE2; and
a second encapsulant having a side surface, the second encapsulant disposed on the second surface of the substrate and having a third coefficient of thermal expansion CTE3,
wherein a difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3, and the side surface of the first encapsulant, the side surface of the second encapsulant and the lateral surface of the substrate are substantially coplanar.

US Pat. No. 10,069,051

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A electronic device, comprising:a first carrier;
a first electronic component disposed on the first carrier;
a second carrier defining an aperture and disposed on the first carrier, wherein the aperture is positioned over the first electronic component and exposes the first electronic component;
a second electronic component disposed on the second carrier;
an encapsulant covering the second electronic component;
a lens defining a cavity and disposed on the aperture of the first second carrier.

US Pat. No. 10,037,975

SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a first encapsulation layer having a first surface and a second surface different from the first surface;
a redistribution layer disposed on the second surface of the first encapsulation layer;
a first die disposed on the redistribution layer;
a second encapsulation layer covering the first die and the redistribution layer; and
an electrical connection terminal electrically connected to the redistribution layer,
wherein the first encapsulation layer surrounds the electrical connection terminal and exposes a portion of the electrical connection terminal, and
wherein a contact angle of the first surface of the first encapsulation layer is less than a contact angle of the second surface of the first encapsulation layer.

US Pat. No. 10,025,033

OPTICAL FIBER STRUCTURE, OPTICAL COMMUNICATION APPARATUS AND MANUFACTURING PROCESS FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. An optical fiber structure comprising:a core portion;
a cladding portion enclosing the core portion, wherein the cladding portion includes a light reflection surface and a light incident surface, the light reflection surface is inclined at an angle of about 30 degrees to about 60 degrees with respect to the core portion, and the light incident surface is substantially flat and is substantially parallel with the core portion; and
a grating structure disposed on the light incident surface, wherein the grating structure includes a plurality of periodic protrusions, and the periodic protrusions and the cladding portion have a common refractive index for constructive light interference;
wherein a minimum distance between the core portion and the light incident surface is less than about 18.5 ?m and greater than about 0.8 ?m.

US Pat. No. 9,978,715

SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure comprising:a first substrate comprising an upper surface and a plurality of first substrate upper conductive pads;
a second substrate comprising a lower surface and a plurality of second substrate lower conductive pads, wherein the upper surface of the first substrate faces the lower surface of the second substrate;
a die electrically connected to the upper surface of the first substrate;
a plurality of interconnection elements connecting the first substrate upper conductive pads and the second substrate lower conductive pads; and
an encapsulation material including a plurality of fillers, disposed between the upper surface of the first substrate and the lower surface of the second substrate, the encapsulation material encapsulating the die and the interconnection elements and defining a plurality of accommodation spaces to accommodate respective ones of the interconnection elements, a profile of each of the accommodation spaces being defined by a respective one of the interconnection elements, wherein the encapsulation material is cured from a B-stage material, and
wherein a thickness of the encapsulation material including the fillers between the lower surface of the second substrate and a top surface of the die is smaller than about 20 micrometers.

US Pat. No. 9,966,333

SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor substrate, comprising:a first dielectric structure having a first surface and a second surface opposite the first surface;
a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure;
a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and
a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace,
wherein the first dielectric structure defines at least one opening, a periphery of the opening corresponds to a periphery of the through hole of the second dielectric structure, and the opening is recessed from the first surface of the first dielectric structure.

US Pat. No. 9,891,048

MEASUREMENT EQUIPMENT

ADVANCED SEMICONDUCTOR EN...

1. A measurement equipment comprising:
a rack;
a first camera disposed on the rack;
a second camera disposed on the rack, the first camera and the second cameras disposed at different positions relative to
a to-be-measured object;

a third camera disposed on the rack;
a fourth camera disposed on the rack, the third camera and the fourth cameras disposed at different positions relative to
the to-be-measured object; and

a processing device connected to the first camera, the second camera, the third camera, and the fourth camera,
wherein the first camera and the second camera are configured to capture an entire image of the to-be-measured object, the
entire image of the to-be-measured object is captured by the first camera and the second camera by simultaneously focusing
on the to-be-measured object, the third camera and the fourth camera are configured to capture a plurality of local images
of a plurality of local areas of the to-be-measured object, and each of the local images is captured by the third camera and
the fourth camera by simultaneously focusing on a corresponding one of the local areas of the to-be-measured object;

wherein the processing device is configured to analyze the entire image and the local images to obtain in-plane deformation,
distortion and warpage of the to-be-measured object.

US Pat. No. 9,564,346

PACKAGE CARRIER, SEMICONDUCTOR PACKAGE, AND PROCESS FOR FABRICATING SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor fabrication process, comprising:
(a) forming a first conductive pattern adjacent to a carrier;
(b) forming a plurality of first conductive post segments on the first conductive pattern; and
(c) applying a dielectric layer to the first conductive pattern and exposing the first conductive post segments, wherein (c)
includes:

(c1) applying a dielectric layer to cover the first conductive pattern and the first conductive post segments;
(c2) forming a plurality of openings in the dielectric layer, such that the first conductive post segments are exposed by
the openings; and

(c3) forming a plurality of second conductive post segments on the first conductive post segments and at least partially within
the openings;

wherein a diameter of each opening is smaller than a diameter of the corresponding first conductive post segment such that
the diameter of each second conductive post segment is smaller than the diameter of the corresponding first conductive post
segment.

US Pat. No. 10,217,649

SEMICONDUCTOR DEVICE PACKAGE HAVING AN UNDERFILL BARRIER

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising;a substrate including:
a top surface defining a mounting area, and
a barrier section on the top surface and adjacent to the mounting area;
a semiconductor device mounted on the mounting area of the substrate; and
an underfill disposed between the semiconductor device and the mounting area of the substrate, wherein a contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.

US Pat. No. 10,186,467

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package device, comprising:a die having a first surface and a second surface opposite to the first surface, the die comprising a first electrode disposed at the first surface of the die and a second electrode disposed at the second surface of the die;
an adhesive layer disposed on the first surface of the die; and
an encapsulant layer encapsulating the die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

US Pat. No. 10,037,974

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising: a package substrate comprising a first surface, a second surface opposite to the first surface, and an edge; a first electronic device positioned over and electrically connected to the package substrate through the first surface; a second electronic device positioned over and electrically connected to the first electronic device; and a first molding layer positioned over the package substrate, wherein the first molding layer: encapsulates a portion of the first surface of the package substrate; and comprises a portion extending from the first surface of the package substrate to the second surface of the package substrate and covering the edge of the package substrate, wherein a thickness of the portion of the first molding layer measured in a direction parallel to the edge of the package substrate is substantially equal to a total thickness of the package substrate measured in the direction, and the first molding layer is further located between the first electronic device and the second electronic device.

US Pat. No. 10,005,660

SEMICONDUCTOR PACKAGE DEVICE INCLUDING MICROELECTROMECHANICAL SYSTEM

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package device comprising:a carrier having a first surface and a second surface opposite the first surface;
a first microelectromechanical system (MEMS) disposed in the carrier, the first MEMS being exposed from the first surface of the carrier and exposed from the second surface of the carrier;
a first electronic component disposed on the first surface of the carrier and electrically connected to the first MEMS; and
a ring block structure disposed on the first surface of the carrier, wherein the ring block structure surrounds the first MEMS and the first electronic component.

US Pat. No. 9,984,986

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:a substrate;
a patterned conductive layer on the substrate;
a passivation layer on the substrate and surrounding the patterned conductive layer;
a first under bump metallurgy (UBM) and a second UBM on the passivation layer and electrically connected to the patterned conductive layer; and
an isolation structure on the passivation layer and between the first UBM and the second UBM, wherein the isolation structure is a protrusion from the passivation layer.

US Pat. No. 9,960,102

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a first semiconductor component comprising a first substrate having a first surface and a second surface opposite to the first surface, the first semiconductor component further comprising at least one first bonding pad disposed adjacent to the first surface of the first substrate and at least one conductive via structure extending from the second surface of the first substrate to the first bonding pad, wherein the first surface of the first substrate is an active surface of the first substrate;
a second semiconductor component comprising a second substrate having a first surface and a second surface opposite to the first surface, the second semiconductor component further comprising a redistribution layer disposed on the first surface of the second substrate, and at least one second bonding pad disposed on the redistribution layer, wherein the first surface of the second substrate is an active surface of the second substrate, and the first surface of the first substrate faces the first surface of the second substrate; and
at least one connecting element disposed between the first bonding pad and the second bonding pad.

US Pat. No. 9,929,132

SEMICONDUCTOR DEVICE AND PROCESS OF MAKING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:a substrate;
a first patterned metal layer disposed on the substrate, the first patterned metal layer including a first part and a second part;
a first dielectric layer disposed on the first part of the first patterned metal layer;
a second metal layer disposed on the first dielectric layer; and
a third metal layer, wherein the third metal layer is disposed on the first part of the first patterned metal layer or disposed between the first part of the first patterned metal layer and the first dielectric layer;
wherein the first part of the first patterned metal layer, the first dielectric layer and the second metal layer form a capacitor, and
wherein the first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

US Pat. No. 9,853,011

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:
a conductive structure;
a semiconductor element disposed on and electrically connected to the conductive structure;
a supporting structure disposed on the conductive structure and surrounding the semiconductor element;
an encapsulant covering the semiconductor element; and
a metal layer disposed on or embedded in the encapsulant, wherein the metal layer is electrically insulated from the conductive
structure.

US Pat. No. 9,748,196

SEMICONDUCTOR PACKAGE STRUCTURE INCLUDING DIE AND SUBSTRATE ELECTRICALLY CONNECTED THROUGH CONDUCTIVE SEGMENTS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:
a die, comprising:
a semiconductor substrate;
a plurality of interconnect metal layers, disposed adjacent to a surface of the semiconductor substrate; and
at least one inter-level dielectric disposed between ones of the plurality of interconnect metal layers;
wherein an outermost interconnect metal layer includes a plurality of first conductive segments exposed from a surface of
the inter-level dielectric for external connections; and

a package substrate, comprising:
a substrate body; and
a plurality of second conductive segments disposed adjacent to a surface of the substrate body and exposed from the surface
of the substrate body, wherein the second conductive segments are electrically connected to corresponding ones of the first
conductive segments;

wherein one of the first conductive segments comprises a first metal, a corresponding one of the second conductive segments
comprises the first metal, and the semiconductor package structure further comprises:

a middle region, located between the one of the first conductive segments and the corresponding one of the second conductive
segments, and comprising the first metal;

a first interface, located between the one of the first conductive segments and the middle region, and comprising the first
metal, wherein a proportion of content of the first metal in the first interface is less than that of the first metal in the
middle region; and

a second interface, located between the corresponding one of the second conductive segments and the middle region, and comprising
the first metal, wherein a proportion of content of the first metal in the second interface is less than that of the first
metal in the middle region, the second interface further comprising an oxide of a second metal.

US Pat. No. 9,728,451

THROUGH SILICON VIAS FOR SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF

ADVANCED SEMICONDUCTOR EN...

1. A method of forming a conductive through silicon via in a semiconductor wafer, comprising the steps:
a.) providing a semiconductor wafer including:
a substrate defining opposed top and bottom surfaces;
a circuitry which is disposed on the top surface of the substrate and comprises a plurality of metal interconnect layers integrated
therein in spaced relation to each other;

a first pad which has a solid portion and a plurality of perforations, and is provided in a first one of the plurality of
metal interconnect layers; and

a second pad which has a solid portion and a plurality of perforations, and is provided in a second one of the plurality of
metal interconnect layers in a position relative to the first pad such that the plurality of perforations of the first pad
are aligned with respective sections of the solid portion defined by the plurality of perforations of the second pad;

b.) etching the bottom surface of the substrate, which forms a through hole therein which exposes the first pad; and
c.) forming a conductive via in the through hole, which extends into electrically conductive contact with the first pad.

US Pat. No. 9,589,840

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor element, comprising:
a main body defining at least one receiving space penetrating through the main body;
a plurality of conductive vias penetrating through the main body; and
at least one filler located in the receiving space, wherein a coefficient of thermal expansion (CTE) of the filler is different
from that of the main body and the conductive vias, and the filler is located between at least two conductive vias;

wherein the at least one receiving space has at least one first opening on a surface of the main body, and a length of the
first opening is greater than a pitch between two conductive vias,

wherein the filler divides the main body into a plurality of individual blocks,
wherein the plurality of individual blocks are fully isolated from one another by the filler.

US Pat. No. 10,199,336

ANTENNA PACKAGE DEVICE

ADVANCED SEMICONDUCTOR EN...

1. An antenna semiconductor package device, comprising:a first conductive layer;
a second conductive layer over the first conductive layer and separated from the first conductive layer;
a first conductive element connecting the first conductive layer to the second conductive layer; and
a first directing element adjacent to the first conductive layer and separated from the first conductive layer by a first gap,
wherein the first conductive element, the first conductive layer and the second conductive layer define a waveguide cavity and a radiation opening, and
wherein the first directing element is outside of the waveguide cavity.

US Pat. No. 10,181,448

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR PACKAGES

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:a semiconductor element;
a trace disposed adjacent to a surface of the semiconductor element and including a bonding pad, wherein the bonding pad is a contact pad of the trace; and
a pillar disposed on the bonding pad, the pillar including:
a first end wall,
a second end wall opposite the first end wall,
a first side wall,
a second side wall opposite the first side wall, and
an extended portion at a corner of the pillar towards the trace,
wherein the first side wall and the second side wall connect the first end wall to the second end wall, and
one or both of the first side wall and the second side wall incline inwardly in a plan view from the first end wall to the second end wall;
wherein the pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

US Pat. No. 10,026,676

SEMICONDUCTOR LEAD FRAME PACKAGE AND LED PACKAGE

Advanced Semiconductor En...

1. A structure comprising:a die pad;
a lead comprising a main portion, an electrode portion, and a connecting portion connecting the main portion and the electrode portion;
a die disposed on a top surface of the die pad and electrically connected to the main portion of the lead disposed above the die pad; and
an insulator body partially encapsulating the die pad and the lead, the insulator body comprising:
a top surface;
a bottom surface; and
a lateral surface extending between the top surface and the bottom surface,
wherein, the electrode portion of the lead is folded onto a top surface of the insulator body, the connecting portion of the lead is disposed on the lateral surface of the insulator body, and a bottom surface of the die pad is exposed from the bottom surface of the insulator body;
wherein the electrode portion is folded upward onto the top surface of the insulator body that is opposite to the bottom surface of the die pad.

US Pat. No. 9,837,701

SEMICONDUCTOR PACKAGE INCLUDING ANTENNA SUBSTRATE AND MANUFACTURING METHOD THEREOF

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package comprising:
a package substrate including an upper surface;
a semiconductor device disposed adjacent to the upper surface of the package substrate;
an antenna substrate directly disposed on the semiconductor device without an intervening layer, the antenna substrate covering
the semiconductor device, the antenna substrate including:

a core layer including an upper surface, a lower surface, a lateral surface extending between the upper surface and the lower
surface of the core layer, a feeding conductive via and a grounding conductive via;

a grounding layer formed on the lower surface of the core layer; and
an antenna layer formed on the upper surface of the core layer and electrically connected to the grounding layer through the
grounding conductive via; and

a package body encapsulating and in contact with the semiconductor device and the entire lateral surface of the core layer
of the antenna substrate.

US Pat. No. 9,754,906

DOUBLE PLATED CONDUCTIVE PILLAR PACKAGE SUBSTRATE

ADVANCED SEMICONDUCTOR EN...

15. A semiconductor packaging structure, comprising:
a first substrate;
a second substrate; and
a conductive pillar extending between the first substrate and the second substrate, wherein the conductive pillar includes:
a first portion, having a first thickness, adjacent to the first substrate,
a second portion, having a second thickness that is less than the first thickness, adjacent to the second substrate, the second
portion including a first sub-portion and a second sub-portion, wherein the second portion includes corners between the first
sub-portion and the second sub-portion; and

a seed layer disposed between the first portion and the second portion,
wherein a side surface of the first portion is substantially coplanar to a side surface of the second portion,
wherein a combined thickness of the first portion and the second portion is about 50 ?m to about 150 ?m.

US Pat. No. 9,711,473

SEMICONDUCTOR DIE, SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor die, comprising:
a semiconductor body having a first surface, a second surface and a side surface extending between the first surface and the
second surface;

an insulating layer disposed on the first surface and the side surface of the semiconductor body, the insulating layer comprising
a first insulating layer over the semiconductor body and a second insulating layer over the first insulating later, the insulating
layer including a step structure;

a conductive circuit layer electrically connected to the first surface of the semiconductor body, the conductive circuit layer
comprising at least one pad; and

at least one conductive bump electrically connected to a respective pad.

US Pat. No. 10,424,545

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package device, comprisinga substrate having a top surface;
a shielding wall disposed on the top surface, the shielding wall comprising a conductive main body and a plurality of protruding portions extending from the conductive main body in a direction substantially parallel to the top surface of the substrate;
a package body encapsulating the shielding wall; and
at least two electronic components disposed on the substrate,
wherein at least one of the protruding portions is disposed between the at least two electronic components and separates the at least two electronic components.

US Pat. No. 10,217,712

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PROCESS FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a substrate including at least one first pad;
a dielectric layer disposed on the substrate and defining at least one through hole corresponding to the at least one first pad, the dielectric layer having a top surface and a bottom surface opposite to the top surface;
at least one conductive pillar disposed in the at least one through hole, the at least one conductive pillar including a body portion and a cap portion, such that a gap is defined between a sidewall of the at least one through hole and the conductive pillar, and the cap portion is located between the top surface of the dielectric layer and the bottom surface of the dielectric layer; and
an electrical device disposed on the dielectric layer and electrically connected to the body portion of the at least one conductive pillar;
wherein the body portion is physically connected to the cap portion, the cap portion is electrically connected to the at least one first pad, the cap portion is located between the body portion and the first pad, and a maximum width of the cap portion is greater than a maximum width of the body portion.

US Pat. No. 10,128,198

DOUBLE SIDE VIA LAST METHOD FOR DOUBLE EMBEDDED PATTERNED SUBSTRATE

ADVANCED SEMICONDUCTOR EN...

1. An interposer substrate, comprising:a dielectric layer including a first surface and a second surface opposite to the first surface, wherein the dielectric layer is formed of a same material throughout the dielectric layer;
a first circuit pattern embedded in the dielectric layer and disposed adjacent to the first surface of the dielectric layer, wherein the first circuit pattern includes a first trace;
a second circuit pattern embedded in the dielectric layer and disposed adjacent to the second surface of the dielectric layer;
a middle patterned conductive layer disposed within the dielectric layer and between the first circuit pattern and the second circuit pattern, wherein the middle patterned conductive layer includes a middle trace, and a width of the middle trace is greater than a width of the first trace;
a first conductive via connecting the first circuit pattern to the middle patterned conductive layer, wherein the first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, and a width of the first conductive via decreases from the first end to the second end; and
a second conductive via connecting the second circuit pattern to the middle patterned conductive layer, wherein the second conductive via includes a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, and a width of the second conductive via decreases from the third end to the fourth end.

US Pat. No. 10,096,542

SUBSTRATE, SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING PROCESS

ADVANCED SEMICONDUCTOR EN...

21. A substrate, comprising:a first dielectric structure;
a first circuit layer embedded in the first dielectric structure, wherein the first circuit layer does not protrude from a first surface of the first dielectric structure, and a line width/line space (L/S) of the first circuit layer is greater than about 7 ?m/about 7 ?m;
a second dielectric structure disposed on the first surface of the first dielectric structure; and
a second circuit layer embedded in the second dielectric structure, wherein the second circuit layer is electrically connected to the first circuit layer, a first surface of the second circuit layer is substantially coplanar with a first surface of the second dielectric structure, a surface roughness value of a first surface of the first circuit layer is different from a surface roughness value of the first surface of the second circuit layer, and an L/S of the second circuit layer is less than about 7 ?m/about 7 ?m.

US Pat. No. 10,056,325

SEMICONDUCTOR PACKAGE HAVING A TRENCH PENETRATING A MAIN BODY

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor element, comprising:a main body defining at least one trench penetrating through the main body;
a plurality of conductive vias penetrating through the main body; and
at least one filler located in the trench, wherein a coefficient of thermal expansion (CTE) of the filler is different from that of the main body, and the filler is located between at least two conductive vias;
wherein the at least one trench has at least one first opening on a surface of the main body, and a length of the first opening is greater than a pitch between two conductive vias,
wherein the filler divides the main body into a plurality of individual blocks, and the plurality of individual blocks are fully isolated from one another by the filler.

US Pat. No. 10,002,843

SEMICONDUCTOR SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor substrate structure, comprising:a conductive structure having a first conductive surface and a second conductive surface opposite to the first conductive surface, wherein the conductive structure includes at least one conductive trace; and
a dielectric structure covering at least a portion of the conductive structure, and having a first dielectric surface and a second dielectric surface opposite to the first dielectric surface, wherein the first conductive surface does not protrude from the first dielectric surface, the second conductive surface is recessed from the second dielectric surface, the dielectric structure is a homogeneous dielectric layer that includes, or is formed from, a cured photo-sensitive resin, and the dielectric structure defines a dielectric opening in the second dielectric surface to expose a portion of the second conductive surface, wherein a side wall defining the dielectric opening is curved, the dielectric opening has a first width at the second dielectric surface and a second width at a middle portion of the dielectric opening, the first width is greater than the second width, and an entirety of the side wall of the dielectric opening in cross-section has a continuous curvature.

US Pat. No. 9,905,722

OPTICAL DEVICE, OPTICAL MODULE STRUCTURE AND MANUFACTURING PROCESS

ADVANCED SEMICONDUCTOR EN...

1. An optical device, comprising:
an emitter having a first surface, a second surface opposite to the first surface and at least one side surface extending
between the first surface and the second surface of the emitter;

a detector having a first surface, a second surface opposite to the first surface and at least one side surface extending
between the first surface and the second surface of the detector;

an encapsulation layer covering the second surface and the side surface of the emitter and the second surface and the side
surface of the detector;

a dielectric layer disposed on the first surface of the emitter and the first surface of the detector, the dielectric layer
defining at least one opening corresponding to a location between the emitter and the detector;

a redistribution layer disposed on the dielectric layer and electrically connected to the emitter and the detector; and
a light shielding structure disposed in the opening of the dielectric layer.

US Pat. No. 9,711,426

FAN-OUT WAFER LEVEL PACKAGING STRUCTURE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:
a first die comprising a first pad and a first passivation layer;
a second die comprising a second pad and a second passivation layer, wherein the first die has a first sidewall and the second
die has a second sidewall;

an encapsulant surrounding the first die and the second die and comprising a first surface;
a dielectric layer covering at least a portion of the first passivation layer and at least a portion of the second passivation
layer, and further covering the encapsulant between the first die and the second die, wherein the dielectric layer comprises:

a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant; and
a third surface opposite to the second surface; and
a redistribution layer electrically connected to the first pad and the second pad and disposed above the third surface of
the dielectric layer;

wherein surfaces of the first die are not coplanar with corresponding surfaces of the second die;
wherein the first passivation layer has a fourth surface adjacent to the dielectric layer; and
wherein an angle between the fourth surface of the first passivation layer and a side surface of the dielectric layer is greater
than 90 degrees, and wherein the side surface of the dielectric layer is formed between the second surface and the third surface
of the dielectric layer.

US Pat. No. 9,653,415

SEMICONDUCTOR DEVICE PACKAGES AND METHOD OF MAKING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package comprising:
a substrate;
a semiconductor device disposed on the substrate;
a plurality of electronic components disposed on the substrate;
a first package body covering the semiconductor device without covering the plurality of electronic components, thereby exposing
the plurality of electronic components from the device package;

a patterned conductive layer formed on the first package body; and
a feeding element electrically connecting the patterned conductive layer to the plurality of electronic components, wherein
the feeding element penetrates the first package body.

US Pat. No. 9,589,906

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising
a die pad having a top surface;
a row of leads comprising a first lead and a second lead, the row of leads being arranged along a side of the die pad, wherein
the first lead has a first lateral surface, and the second lead has a second lateral surface;

a component disposed on the top surface of the die pad;
a package body encapsulating the component, the die pad, the first lead, and the second lead, the package body exposing the
first lateral surface of the first lead and covering the second lateral surface of the second lead; and

a conformal shield covering the package body and connected to the first lateral surface of the first lead.

US Pat. No. 9,583,427

SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A method of making a semiconductor package structure, comprising:
providing a semiconductor substrate, the semiconductor substrate comprising:
a first patterned metal layer;
a second patterned metal layer spaced from and electrically connected to the first patterned metal layer;
a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer and covering the
second patterned metal layer, wherein the dielectric layer defines first openings exposing the second patterned metal layer;
and

a carrier layer abutting the dielectric layer;
electrically connecting a die to the first patterned metal layer; and
removing the carrier layer,
wherein the dielectric layer has a surface roughness determined by a surface roughness of the carrier layer.

US Pat. No. 9,564,393

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MAKING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package comprising:
a substrate;
a semiconductor device disposed on a surface of the substrate, the semiconductor device including a first contact pad and
a second contact pad disposed on an upper surface of the semiconductor device;

a dielectric layer disposed on the surface of the substrate and covering the semiconductor device, and further covering a
portion of the first contact pad and a portion of the second contact pad;

a conductive bar disposed on a remaining portion of the first contact pad exposed by the dielectric layer; and
a conductive pillar disposed on a remaining portion of the second contact pad exposed by the dielectric layer.

US Pat. No. 10,229,892

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:at least one semiconductor element;
an encapsulant covering at least a portion of the at least one semiconductor element, the encapsulant having a first surface and a second surface opposite to the first surface;
a first circuitry disposed adjacent to the first surface of the encapsulant;
a second circuitry disposed adjacent to the second surface of the encapsulant; and
at least one first stud bump disposed in the encapsulant, and electrically connecting the first circuitry and the second circuitry, wherein the first stud bump contacts the second circuitry directly and protrudes from the first surface of the encapsulant.

US Pat. No. 10,229,894

SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor process comprising:(a) electrically connecting a die to an upper surface of a first substrate, wherein the first substrate comprises a plurality of first substrate upper conductive pads, and wherein the first substrate upper conductive pads are exposed on the upper surface of the first substrate;
(b) forming a plurality of first conductive parts on the respective first substrate upper conductive pads;
(c) applying an encapsulation material on the upper surface of the first substrate to encapsulate the die and the first conductive parts, wherein the encapsulation material is a B-stage adhesive;
(d) forming a plurality of openings on the encapsulation material to expose the first conductive parts;
(e) pressing a second substrate onto the encapsulation material to adhere a lower surface of the second substrate to the encapsulation material, wherein the second substrate comprises a plurality of second substrate lower conductive pads and a plurality of second conductive parts, wherein the second substrate lower conductive pads are exposed on the lower surface of the second substrate, wherein the second conductive parts are deposited on the respective second substrate lower conductive pads, and wherein each of the first conductive parts contacts a corresponding one of the second conductive parts; and
(f) heating to fuse the first conductive parts and the corresponding second conductive parts to form a plurality of interconnection elements and to solidify the encapsulation material to a C-stage adhesive.

US Pat. No. 10,083,911

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a flexible substrate;
an electronic component disposed on the flexible substrate;
at least one flexible member disposed on the flexible substrate; and
a package body encapsulating the electronic component and including a first part and a second part separated from the first part by the at least one flexible member,
wherein the at least one flexible member is non-conductive.

US Pat. No. 10,074,586

THERMAL DISSIPATION DEVICE AND SEMICONDUCTOR PACKAGE DEVICE INCLUDING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A thermal dissipation device, comprising:a main body having an upper surface, a lower surface opposite to the upper surface, and a lateral surface, the main body defining an injection hole extending through the main body, and the main body including an inner ring protruding from the upper surface and adjacent to the injection hole and an outer ring protruding from the upper surface and adjacent to the lateral surface; and
a support member connecting the lateral surface of the main body,
wherein an upper surface of the inner ring is higher than an upper surface of the outer ring, and a first intersection point between the inner ring and the upper surface of the main body is higher than a second intersection point between the outer ring and the upper surface of the main body.

US Pat. No. 10,068,851

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:a first dielectric layer defining at least one through hole;
a conductive element disposed in the through hole and including a first portion and a second portion, wherein a first surface of the first portion is planar and substantially coplanar with a first surface of the first dielectric layer, and a portion of a first surface of the second portion is recessed from the first surface of the first dielectric layer;
a first circuit structure disposed on the first dielectric layer;
a semiconductor die electrically connected to the first circuit structure; and
an encapsulant covering the semiconductor die.

US Pat. No. 10,014,250

SEMICONDUCTOR DEVICES

ADVANCED SEMICONDUCTOR EN...

17. A semiconductor device, comprising:a substrate;
a first patterned conductive layer disposed over the substrate, the first patterned conductive layer comprising a plurality of first crossbars separated from one another and a plurality of third crossbars separated from one another, the first crossbars bending in a first direction, and the third crossbars bending in a third direction;
a second patterned conductive layer disposed over the second conductive layer, the second patterned conductive layer comprising a plurality of second crossbars separated from one another and a plurality of fourth crossbars separated from one another, the second crossbars bending in a second direction, and the fourth crossbars bending in a fourth direction;
a plurality of columnar structures disposed between the first crossbars and the second crossbars and electrically coupling the first crossbars and the second crossbars;
wherein one first crossbar of the first patterned conductive layer is electrically coupled to one second crossbar of the second patterned conductive layer through one columnar structure, and the one second crossbar of the second patterned conductive layer is electrically coupled to another one first crossbar of the first patterned conductive layer through another one columnar structure.

US Pat. No. 9,881,845

ELECTRONIC DEVICE, LID STRUCTURE AND PACKAGE STRUCTURE

ADVANCED SEMICONDUCTOR EN...

1. An electronic device, comprising:
a transducer comprising a sensing area; and
a covering structure that covers the transducer, wherein the covering structure comprises a shelter portion and defines at
least one aperture, the shelter portion covers the sensing area, the aperture includes a first curved surface and a second
curved surface farther away from the sensing area than the first curved surface, and a first center of a first curvature of
the first curved surface is at a different location than a second center of a second curvature of the second curved surface;

wherein the first center of the first curvature is located between the first curved surface and the second center of the second
curvature.

US Pat. No. 9,741,675

BUMP STRUCTURES, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PACKAGE HAVING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:
a body comprising a first surface;
at least one conductive metal pad disposed on the first surface; and
at least one metal pillar, wherein each metal pillar is formed on a corresponding one of the at least one conductive metal
pad and comprises a concave side wall and a convex side wall opposite the concave side wall, a center of curvature of the
concave side wall coinciding with a center of curvature of the convex side wall, the concave side wall and the convex side
wall being orthogonal to the corresponding conductive metal pad, wherein each metal pillar further comprises a first end wall
and a second end wall, each of the first end wall and the second end wall connects the concave side wall and the convex side
wall, the first end wall and the second end wall being orthogonal to the corresponding conductive metal pad.

US Pat. No. 9,564,376

SEMICONDUCTOR PROCESS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor process, comprising:
(a) providing a semiconductor element;
(b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between
the semiconductor element and the carrier;

(c) cutting the semiconductor element to form a plurality of semiconductor element units; and
(d) removing the semiconductor element units from the adhesive layer.

US Pat. No. 10,687,419

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package device, comprising:a first dielectric layer having a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface;
a first interconnection layer within the first dielectric layer, the first interconnection layer comprising a redistribution layer (RDL);
a second interconnection layer on the second surface of the first dielectric layer and extending from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer, wherein the second interconnection layer is in contact with the first interconnection layer;
a second dielectric layer covering the second surface and the lateral surface of the first dielectric layer and the second interconnection layer;
a conductive pad disposed on a bottom surface of the second dielectric layer and extending into the second dielectric layer to electrically connect to the second interconnection layer;
a first seed layer disposed between the first interconnection layer and the second interconnection layer; and
a second seed layer disposed between the second interconnection layer and the conductive pad,
wherein the first interconnection layer has a surface coplanar with the first surface of the first dielectric layer;
wherein the second interconnection layer includes a first portion and the second portion connected the first portion, the first portion is surrounded by the first dielectric layer and the second portion is surrounded by the second dielectric layer; and
wherein the first seed layer is surrounded by the first dielectric layer and the second dielectric layer.

US Pat. No. 10,658,319

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR PACKAGES

ADVANCED SEMICONDUCTOR EN...

11. A substrate, comprising:a trace disposed adjacent to a surface of the substrate and including a bonding pad, wherein the bonding pad is a contact pad of the trace; and
the bonding pad including:
a first end wall,
a second end wall opposite the first end wall,
a first side wall, and
a second side wall opposite the first side wall,
wherein the first side wall and the second side wall connect the first end wall to the second end wall, and
the first end wall is wider than the second end wall;
wherein the first end wall is closer to the trace than is the second end wall, and the first end wall includes a sloped portion.

US Pat. No. 10,424,547

SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A substrate for packaging a semiconductor device, comprising:a first dielectric layer having a first surface and a second surface opposite to the first surface, the first dielectric layer comprising a first portion adjacent to the first surface, a second portion adjacent to the second surface, and a reinforcement structure between the first portion and the second portion;
a first patterned conductive layer adjacent to the first surface of the first dielectric layer; and
a second patterned conductive layer adjacent to the second surface of the first dielectric layer,
wherein a thickness of the first portion of the first dielectric layer is different from a thickness of the second portion of the first dielectric layer,
a density of the first patterned conductive layer is greater than a density of the second patterned conductive layer,
the thickness of the first portion of the first dielectric layer is greater than the thickness of the second portion of the first dielectric layer, and
a thickness of the first patterned conductive layer is substantially the same as a thickness of the second patterned conductive layer.

US Pat. No. 10,407,298

MICROELECTROMECHANICAL SYSTEMS AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. An electronic device, comprising:a substrate defining an opening penetrating the substrate;
a microelectromechanical systems (MEMS) device having an active surface facing away from the substrate and a sensing region facing toward the opening;
an attachment element disposed on the substrate and surrounding the opening and the sensing region of the MEMS device;
a die disposed on the substrate;
a package body covering the die and exposing the MEMS device; and
a metal lid disposed on the package body, wherein the metal lid defines an opening exposing the MEMS device,
wherein the attachment element includes a B-stage silicon soft adhesive material, and
the package body defines a cavity to accommodate the MEMS device, and a sidewall of the cavity includes a protrusion portion.

US Pat. No. 10,344,383

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. An apparatus for processing a wafer, the apparatus comprising:a ceramic wall defining a chamber for accommodating the wafer, the ceramic wall having a first surface defining a first opening; and
a metal wall surrounding the ceramic wall, the metal wall having a second surface defining a second opening adjacent to the first opening; and
a frame covering the second surface.

US Pat. No. 10,134,683

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a first circuit layer having a first surface and a second surface opposite to the first surface;
a first electronic component disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer;
a shielding element disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer, wherein the shielding element is disposed adjacent to at least one side of the first electronic component;
a shielding layer disposed over the first electronic component and over the shielding element, wherein the shielding layer is electrically connected to the shielding element;
a molding layer encapsulating the first electronic component, the shielding element and a portion of the shielding layer, wherein an upper surface of the molding layer and an upper surface of the shielding layer are substantially coplanar;
at least one conductive post extending through the molding layer and electrically connected to the first circuit layer;
a second circuit layer disposed over the molding layer, the shielding layer and the at least one conductive post, and electrically connected to the shielding layer and to the at least one conductive post; and
an electronic device disposed over and electrically connected to the second circuit layer.

US Pat. No. 10,049,893

SEMICONDUCTOR DEVICE WITH A CONDUCTIVE POST

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a substrate having a first surface and a second surface opposite the first surface;
a pad including a first portion and a second portion, the pad disposed on the first surface of the substrate;
a first isolation layer disposed on the first surface and covering the first portion of the pad, the first isolation layer having a top surface;
an interconnection layer disposed on the second portion of the pad and having a top surface; and
a pre-formed conductive post disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer;
wherein the top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.

US Pat. No. 9,991,193

SEMICONDUCTOR DEVICE PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a first conductive base having a first surface and a second surface opposite to the first surface and defining a first cavity in the first surface of the first conductive base, the first cavity having a bottom surface;
a first semiconductor die disposed on the bottom surface of the first cavity;
a dielectric layer disposed on the first semiconductor die, the first surface and the second surface of the first conductive base and filling the first cavity, wherein the dielectric layer has a first surface and a second surface opposite to the first surface;
a first patterned conductive layer disposed on the first surface of the dielectric layer;
a second patterned conductive layer disposed on the second surface of the dielectric layer;
a plurality of first interconnection structures disposed in the dielectric layer and electrically connected to the first semiconductor die and the first patterned conductive layer; and
a plurality of second interconnection structures disposed in the dielectric layer and electrically connected to the second surface of the first conductive base and the second patterned conductive layer.

US Pat. No. 9,984,989

SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR PACKAGE STRUCTURE

ADVANCED SEMICONDUCTOR EN...

1. A substrate for a semiconductor package structure, comprising:an insulating layer having a first surface;
a first conductive patterned layer recessed relative to the first surface of the insulating layer, the first conductive patterned layer comprising a plurality of conductive traces; and
a plurality of conductive bumps disposed on the first conductive patterned layer, wherein each conductive bump has a first dimension along a first direction substantially parallel to a respective conductive trace and a second dimension along a second direction perpendicular to the first direction, the first dimension is greater than the second dimension, the second dimension of the conductive bump is smaller than a width of the conductive trace along an entirety of the conductive bump; and only a portion of the conductive trace is recessed below the first surface of the insulating layer.

US Pat. No. 9,977,147

OPTICAL MODULE, METHOD OF MAKING THE SAME AND ELECTRONIC DEVICE INCLUDING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. An optical module, comprising:a carrier;
a light-emitting component disposed over the carrier;
an optical sensor disposed over the carrier;
a housing disposed over the carrier and encircling the light-emitting component and the optical sensor, the housing defining a first accommodation space and a second accommodation space, the first accommodation space including a first aperture and a second aperture below the first aperture, the first aperture having a first aperture size, the second aperture having a second aperture size, the first aperture size greater than the second aperture size, the second accommodation space including a third aperture and a fourth aperture below the third aperture, the third aperture having a third aperture size, and the fourth aperture having a fourth aperture size,
the housing comprising:
a first sidewall surrounding the first aperture;
a second sidewall surrounding the second aperture; and
a first support portion where a bottom end of the first sidewall and a top end of the second sidewall meet;
a first lens located in the first aperture and supported by the first support portion;
a third sidewall surrounding the third aperture;
a fourth sidewall surrounding the fourth aperture;
a fifth sidewall located below the fourth sidewall and surrounding a fifth aperture, the fifth aperture having a fifth aperture size, the fifth aperture size greater than the fourth aperture size;
a second support portion where a bottom end of the third sidewall and a top end of the fourth sidewall meet; and
a second lens located in the third aperture and supported by the second support portion;
wherein one of the light-emitting component and the optical sensor is located in the second aperture of the first accommodation space, and the other one of the light-emitting component and the optical sensor is located in the second accommodation space.

US Pat. No. 9,922,938

SEMICONDUCTOR DEVICE PACKAGE INTEGRATED WITH COIL FOR WIRELESS CHARGING AND ELECTROMAGNETIC INTERFERENCE SHIELDING, AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:
a carrier having a top surface and a bottom surface;
a grounding element;
a plurality of electrical connections extending between the top surface of the carrier and the bottom surface of the carrier;
a first electronic component disposed on the carrier;
a second electronic component disposed on a pad of the carrier and is electrically connected to at least one of the electrical
connections;

a package body disposed on the carrier and encapsulating the first electronic component and the second electronic component;
a shield disposed on the package body, wherein the shield covers at least a top surface and a lateral surface of the package
body, wherein the shield comprises a plurality of non-magnetic conductive layers, a plurality of insulating layers and a plurality
of magnetic conductive layers, and wherein at least one of the insulating layers is located between each non-magnetic conductive
layer and a neighboring magnetic conductive layer; wherein the plurality of electrical connections includes a first electrical
connection that electrically connects the shield to the grounding element; and

an interconnection electrically connecting at least one of the non-magnetic conductive layers of the shield to at least one
of the magnetic conductive layers of the shield.

US Pat. No. 9,911,709

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING PROCESS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:
a first semiconductor die including a first active surface and a plurality of first bumps disposed adjacent to the first active
surface;

a second semiconductor die including a second active surface and a plurality of second bumps disposed adjacent to the second
active surface, wherein the second bumps are bonded to respective ones of the first bumps; and

a plurality of supporting structures disposed between the first active surface of the first semiconductor die and the second
active surface of the second semiconductor die, wherein the supporting structures are electrically isolated and are disposed
adjacent to a peripheral region of the second active surface of the second semiconductor die, wherein each of the supporting
structures includes a first dummy bump and a second dummy bump bonded to the first dummy bump.

US Pat. No. 9,871,005

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:
a carrier;
an electronic component disposed over a top surface of the carrier;
a package body disposed over the top surface of the carrier and covering the electronic component; and
a shield layer, comprising a first electrically conductive layer, a first magnetically permeable layer, and a second electrically
conductive layer;

wherein the first magnetically permeable layer is interposed between and directly contacts the first electrically conductive
layer and the second electrically conductive layer, and a permeability of the first magnetically permeable layer is higher
than each of a permeability of the first electrically conductive layer and a permeability of the second electrically conductive
layer.

US Pat. No. 9,859,232

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package device, comprising:
a substrate having a first area and a second area;
a semiconductor device on the first area of the substrate;
an antenna pattern on the second area of the substrate;
a first electronic component on the antenna pattern and electrically connected to the antenna pattern; and
a first package body encapsulating the first area of the substrate and the semiconductor device and exposing the antenna pattern,
the first electronic component and the second area of the substrate.

US Pat. No. 9,831,195

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:
a first chip having a first surface and a second surface opposite the first surface;
a supporter surrounding an edge of the first chip, wherein the supporter includes a recessed portion;
a conductive layer disposed over the first surface of the first chip and electrically connected to the first chip;
an insulation layer disposed over the first surface of the first chip, wherein the insulation layer extends toward and overlaps
the supporter in a vertical projection direction; and

an encapsulant between the first chip and the supporter and surrounding at least the edge of the first chip.

US Pat. No. 10,510,705

SEMICONDUCTOR PACKAGE STRUCTURE HAVING A SECOND ENCAPSULANT EXTENDING IN A CAVITY DEFINED BY A FIRST ENCAPSULANT

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:a first semiconductor die;
a second semiconductor die disposed on the first semiconductor die;
a plurality of conductive elements each comprising a first portion and a second portion, and disposed around the first semiconductor die and the second semiconductor die;
a first encapsulant surrounding the first semiconductor die and the respective first portions of the conductive elements; and
a second encapsulant covering a portion of a top portion of the first semiconductor die and surrounding the respective second portions of the conductive elements, wherein the second encapsulant directly contacts the first encapsulant, the first encapsulant defines a cavity to expose at least the portion of the top portion of the first semiconductor die, and the second encapsulant covers the first encapsulant and extends into the cavity.

US Pat. No. 10,408,875

TESTING SYSTEM, METHOD FOR TESTING AN INTEGRATED CIRCUIT AND A CIRCUIT BOARD INCLUDING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A testing system, comprising:a subtractor configured to receive a first voltage of an integrated circuit (IC) being tested and a second voltage of the IC being tested, and to derive a difference between the first voltage and the second voltage; and
a divider configured to receive the difference between the first voltage and the second voltage, and to derive a resistance of the IC being tested by dividing (i) the difference between the first voltage and the second voltage by (ii) a difference between a first current applied to the IC being tested and a second current applied to the IC being tested,
wherein the first voltage corresponds to the first current, and the second voltage corresponds to the second current.

US Pat. No. 10,177,283

LED PACKAGES AND RELATED METHODS

Advanced Semiconductor En...

1. A light-emitting diode (LED) package, comprising:a lead frame including a die pad and at least one electrode, the at least one electrode being isolated from the die pad by at least one gap, the die pad including a trench, one end of the trench being connected to the at least one gap;
a first insulator partially encapsulating the lead frame to expose an upper surface of the die pad and a portion of the at least one electrode, the first insulator partially filling the at least one gap and the trench; and
a chip disposed on the upper surface of the die pad between the trench and the at least one gap.

US Pat. No. 10,083,888

SEMICONDUCTOR DEVICE PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a conductive base, a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth; and
a semiconductor die disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface, the second surface of the semiconductor die bonded to the bottom surface of the cavity;
wherein a distance between the first surface of the semiconductor die and the first surface of the conductive base is about 20% of the depth of the cavity,
wherein a portion of the conductive base defining a sidewall of the cavity further defines an opening.

US Pat. No. 10,083,902

SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure comprising:a first dielectric layer having a first surface and a second surface opposite the first surface;
a second dielectric layer having a first surface and a second surface opposite the first surface, the second surface of the first dielectric layer being attached to the first surface of the second dielectric layer;
a component within the second dielectric layer and in direct contact with the second dielectric layer, the component comprising at least two electrical contacts;
a first patterned conductive layer exposed from the first surface of the first dielectric layer and embedded in the first dielectric layer without protruding from the first surface of the first dielectric layer; and
at least two conductive vias penetrating the first dielectric layer or the second dielectric layer, each conductive via electrically connected to a respective one of the at least two electrical contacts.

US Pat. No. 9,997,442

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor substrate, comprising:an interconnection structure;
a first dielectric layer surrounding the interconnection structure, the first dielectric layer having a first surface; and
a second dielectric layer disposed on the first dielectric layer, the second dielectric layer having a first sidewall and a second sidewall;
wherein the first sidewall and the second sidewall of the second dielectric layer and the first surface of the first dielectric layer define a first cavity; and
wherein the first sidewall of the second dielectric layer is laterally displaced from the second sidewall of the second dielectric layer.

US Pat. No. 9,881,917

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device, comprising:
a substrate;
a first capacitor comprising a first conductive layer, a first insulating layer and a second conductive layer, the first insulating
layer having a first peripheral edge, and the second conductive layer having a second peripheral edge;

a second capacitor comprising a third conductive layer, a second insulating layer and the second conductive layer, the second
insulating layer having a third peripheral edge, and the third conductive layer having a fourth peripheral edge;

a conductive post extending through the substrate and directly connected to the first conductive layer;
a passivation layer surrounding the first capacitor and the second capacitor;
conductive pads disposed on the passivation layer, wherein the conductive pads comprise a first conductive pad configured
as an input electrode and a second conductive pad configured as an output electrode; and

interconnect structures extending through the passivation layer, each interconnect structure connected to a corresponding
one of the first, second, and third conductive layers and one of the conductive pads, wherein the interconnect structures
include:

a first interconnect structure connected to the first conductive layer;
a second interconnect structure connected to the second conductive layer; and
a third interconnect structure connected to the third conductive layer;
wherein the first interconnect structure, the second interconnect structure, and the third interconnect structure are configurably
connected for external access to any of: the first capacitor, the second capacitor, or the first capacitor and the second
capacitor in parallel, and

wherein at least a first side of each of the first, second, third and fourth peripheral edges are aligned with one another,
and a second side of at least one of the first, second, third and fourth peripheral edges is laterally displaced from the
second side of at least another one of the first, second, third and fourth peripheral edges.

US Pat. No. 10,658,306

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:a first chip having a first surface and a second surface opposite the first surface;
a supporter surrounding an edge of the first chip, wherein the supporter includes a first segment and a second segment connected to each other, a thickness of the second segment is smaller than a thickness of the first segment, an upper surface of the second segment is recessed from an upper surface of the first segment to define a recessed portion, and two opposite sides of the recessed portion are defined by the first segment;
a conductive layer disposed over the first surface of the first chip and electrically connected to the first chip;
an insulation layer disposed over the first surface of the first chip; and
an encapsulant between the first chip and the supporter and surrounding at least the edge of the first chip.

US Pat. No. 10,304,765

SEMICONDUCTOR DEVICE PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a substrate having a first sidewall, a first surface and a second surface opposite to the first surface;
a first insulation layer on the first surface of the substrate and having a second sidewall, wherein the first insulation layer has a first surface and a second surface adjacent to the substrate and opposite to the first surface of the first insulation layer;
a support film on the second surface of the substrate and having a third sidewall, wherein the support film has a first surface adjacent to the substrate and a second surface opposite to the first surface of the support film; and
an interconnection structure extending from the first surface of the first insulation layer to the second surface of the support film via the first insulation layer and the support film, the interconnection structure being in direct contact with the first, second and third sidewalls.

US Pat. No. 10,211,161

SEMICONDUCTOR PACKAGE STRUCTURE HAVING A PROTECTION LAYER

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:a semiconductor substrate;
at least one semiconductor die disposed on the semiconductor substrate;
an encapsulant covering at least a portion of the at least one semiconductor die, wherein the encapsulant has a first surface and a lateral surface;
a protection layer covering the first surface and the lateral surface of the encapsulant;
a plurality of conductive elements surrounding the lateral surface of the encapsulant; and
a redistribution layer electrically connecting the at least one semiconductor die and the conductive elements.

US Pat. No. 10,134,677

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package device comprising:a first interconnection structure having a first pitch;
a non-silicon interposer surrounding the first interconnection structure, the non-silicon interposer comprising a second interconnection structure and a third interconnection structure disposed on the first interconnection structure, wherein the second interconnection structure has a second pitch and the third interconnection structure has a third pitch, and wherein the second pitch or the third pitch is larger than the first pitch; and
a first die above the first interconnection structure and electrically connected to the first interconnection structure.

US Pat. No. 10,068,854

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package device comprising:a substrate having a top surface;
a passive component disposed on the substrate and having a top surface;
an active component disposed on the substrate and having a top surface; and
a package body disposed on the substrate, the package body comprising a first portion covering the active component and the passive component, and a second portion covering the passive component, wherein a top surface of the second portion of the package body is higher than a top surface of the first portion of the package body,
wherein a distance between the top surface of the active component and the top surface of the substrate is greater than a distance between the top surface of the passive component and the top surface of the substrate.

US Pat. No. 9,953,931

SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a substrate having a first surface and a second surface opposite to the first surface;
a first electronic component on the first surface of the substrate;
a first conductive pad on the first surface of the substrate;
a second conductive pad on the first surface of the substrate;
a first frame board on the first surface of the substrate and surrounding the first electronic component, the first frame board comprising a first conductive via and a second electronic component;
an encapsulation layer encapsulating the first electronic component and the first frame board; and
a conductive layer on the first frame board and the encapsulation layer,
wherein the first conductive via is electrically connected to the second conductive pad and the conductive layer, and the second electronic component is electrically connected to the first conductive pad.

US Pat. No. 9,917,071

SEMICONDUCTOR PACKAGES

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:
a first substrate comprising a first interconnection structure extending from a surface of the first substrate, the first
interconnection structure comprising grains of a first size;

a second substrate comprising:
a second interconnection structure comprising grains of a second size; and
a third interconnection structure disposed between the first interconnection structure and the second interconnection structure,
the third interconnection structure comprising:

grains of a third size;
a first sidewall inclined at a first angle to a reference plane; and
a second sidewall inclined at a second angle to the reference plane;
wherein the first angle is different from the second angle, the first sidewall is disposed between the first substrate and
the second sidewall, and the third size is smaller than both the first size and the second size.

US Pat. No. 10,629,519

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:an electronic device;
a conductive frame disposed on and electrically connected to the electronic device, the conductive frame comprising a plurality of leads;
a first molding layer covering the electronic device and a portion of the conductive frame, and disposed between at least two adjacent ones of the leads; and
a plurality of electrical contacts disposed over and electrically connected to the electronic device, wherein a portion of at least one of plurality of the plurality of electrical contacts protrudes from the first molding layer, and
wherein at least one end of at least one of the plurality of leads is exposed from a lateral side of the first molding layer.

US Pat. No. 10,591,688

OPTICAL DEVICE PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. An optical device package, comprising:a waveguide, the waveguide comprising:
a main body; and
a plurality of forks, wherein each of the plurality of forks has a tapering end and is extended from the main body, and wherein each of the tapering ends of the forks comprises a facet for receiving light, the plurality of forks having a substantially constant thickness; and
an optical fiber having a surface configured to output the light into the waveguide;
wherein a lateral distance between the surface of the optical fiber and at least one of the facets is less than about 25 micrometers (?m).

US Pat. No. 10,508,935

OPTICAL MODULE AND MANUFACTURING PROCESS THEREOF

ADVANCED SEMICONDUCTOR EN...

1. An optical module, comprising:a carrier;
a light source disposed adjacent to a surface of the carrier;
a light detector disposed adjacent to the surface of the carrier; and
a molding compound encapsulating the light source and the light detector, and including at least one sloped structure, the at least one sloped structure comprising a sloped surface extended between a side surface and a top surface of the molding compound; and
a lid disposed between the light source and the light detector, and surrounding the light source and the light detector.

US Pat. No. 10,436,635

ACTIVE OPTICAL COMPONENT WITH PASSIVE OPTICAL COMPONENT AND ENCAPSULANT FOR AN OPTICAL DEVICE AND ELECTRICAL DEVICE INCLUDING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. An optical device, comprising:an active optical component comprising an optical area;
an encapsulant covering the active optical component and comprising a platform disposed above the active optical component, wherein the platform protrudes above a remainder of the encapsulant, the encapsulant defines a recess portion, and the encapsulant is a monolithic structure;
a passive optical component adhered to the encapsulant above the active optical component, wherein the passive optical component has an optical axis, the optical axis is substantially aligned with a center of the optical area, and an area of a surface of the encapsulant including the recess portion facing the passive optical component is less than an area of a surface of the passive optical component facing the encapsulant; and
an adhesive gel, wherein the passive optical component is positioned over the recess portion of the encapsulant and in contact with the adhesive gel.

US Pat. No. 10,424,566

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. An electronic device, comprising:a carrier having a top surface;
an emitter disposed on a first portion of the top surface of the carrier;
a detector disposed on a second portion of the top surface of the carrier, the detector having a surface;
a separation wall disposed on the top surface of the carrier between the emitter and the detector; and
a first light shielding layer disposed adjacent to the top surface of the carrier and extending from the separation wall to the second portion of the carrier, wherein the first light shielding layer covers a first portion of the surface of the detector and exposes a second portion of the surface of the detector, and wherein the first light shielding layer extends underneath the detector.